lael-labs/linux

Documentation/devicetree/bindings/iio/adc/sprd,sc2720-adc.yaml+0−17

@@ -80,23 +80,6 @@ required: · 79 unmodified lines
80	additionalProperties: false	80	additionalProperties: false
81		81
82	examples:	82	examples:
83	- \|
84	#include <dt-bindings/interrupt-controller/irq.h>
85	pmic {
86	#address-cells = <1>;
87	#size-cells = <0>;
88	adc@480 {
89	compatible = "sprd,sc2731-adc";
90	reg = <0x480>;
91	interrupt-parent = <&sc2731_pmic>;
92	interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
93	#io-channel-cells = <1>;
94	hwlocks = <&hwlock 4>;
95	nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
96	nvmem-cell-names = "big_scale_calib", "small_scale_calib";
97	};
98	};
99
100	- \|	83	- \|
101	#include <dt-bindings/interrupt-controller/irq.h>	84	#include <dt-bindings/interrupt-controller/irq.h>
102	pmic {	85	pmic {

Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml+1−1

@@ -19,7 +19,7 @@ description: \| · 18 unmodified lines
19	by the PMIC that is defined as a Multi-Function Device (MFD).	19	by the PMIC that is defined as a Multi-Function Device (MFD).
20		20
21	For MediaTek MT6323/MT6397 PMIC bindings see	21	For MediaTek MT6323/MT6397 PMIC bindings see
22	Documentation/devicetree/bindings/mfd/mt6397.txt	22	Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
23		23
24	properties:	24	properties:
25	compatible:	25	compatible:

Documentation/devicetree/bindings/leds/leds-mt6323.txt+0−63

@@ -1,63 +0,0 @@
1	Device Tree Bindings for LED support on MT6323 PMIC
2
3	MT6323 LED controller is subfunction provided by MT6323 PMIC, so the LED
4	controllers are defined as the subnode of the function node provided by MT6323
5	PMIC controller that is being defined as one kind of Muti-Function Device (MFD)
6	using shared bus called PMIC wrapper for each subfunction to access remote
7	MT6323 PMIC hardware.
8
9	For MT6323 MFD bindings see:
10	Documentation/devicetree/bindings/mfd/mt6397.txt
11	For MediaTek PMIC wrapper bindings see:
12	Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
13
14	Required properties:
15	- compatible : Must be one of
16	- "mediatek,mt6323-led"
17	- "mediatek,mt6331-led"
18	- "mediatek,mt6332-led"
19	- address-cells : Must be 1
20	- size-cells : Must be 0
21
22	Each led is represented as a child node of the mediatek,mt6323-led that
23	describes the initial behavior for each LED physically and currently only four
24	LED child nodes can be supported.
25
26	Required properties for the LED child node:
27	- reg : LED channel number (0..3)
28
29	Optional properties for the LED child node:
30	- label : See Documentation/devicetree/bindings/leds/common.txt
31	- linux,default-trigger : See Documentation/devicetree/bindings/leds/common.txt
32	- default-state: See Documentation/devicetree/bindings/leds/common.txt
33
34	Example:
35
36	mt6323: pmic {
37	compatible = "mediatek,mt6323";
38
39	...
40
41	mt6323led: leds {
42	compatible = "mediatek,mt6323-led";
43	#address-cells = <1>;
44	#size-cells = <0>;
45
46	led@0 {
47	reg = <0>;
48	label = "LED0";
49	linux,default-trigger = "timer";
50	default-state = "on";
51	};
52	led@1 {
53	reg = <1>;
54	label = "LED1";
55	default-state = "off";
56	};
57	led@2 {
58	reg = <2>;
59	label = "LED2";
60	default-state = "on";
61	};
62	};
63	};

Documentation/devicetree/bindings/leds/sprd,sc2731-bltc.yaml+0−31

@@ -50,35 +50,4 @@ required: · 49 unmodified lines
50	- '#size-cells'	50	- '#size-cells'
51		51
52	additionalProperties: false	52	additionalProperties: false
53
54	examples:
55	- \|
56	#include <dt-bindings/leds/common.h>
57
58	pmic {
59	#address-cells = <1>;
60	#size-cells = <0>;
61
62	led-controller@200 {
63	compatible = "sprd,sc2731-bltc";
64	reg = <0x200>;
65	#address-cells = <1>;
66	#size-cells = <0>;
67
68	led@0 {
69	reg = <0x0>;
70	color = <LED_COLOR_ID_RED>;
71	};
72
73	led@1 {
74	reg = <0x1>;
75	color = <LED_COLOR_ID_GREEN>;
76	};
77
78	led@2 {
79	reg = <0x2>;
80	color = <LED_COLOR_ID_BLUE>;
81	};
82	};
83	};
84	...	53	...

Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml+7−1

 description:
   The Aspeed System Control Unit manages the global behaviour of the SoC,
   configuring elements such as clocks, pinmux, and reset.
+  In AST2700 SOC which has two soc connection, each soc have its own scu
+  register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.
 maintainers:
   - Joel Stanley <joel@jms.id.au>
           - aspeed,ast2400-scu
           - aspeed,ast2500-scu
           - aspeed,ast2600-scu
+          - aspeed,ast2700-scu0
+          - aspeed,ast2700-scu1
       - const: syscon
       - const: simple-mfd
   ranges: true
   '#address-cells':
-    const: 1
+    minimum: 1
+    maximum: 2
   '#size-cells':
     const: 1
               - aspeed,ast2400-silicon-id
               - aspeed,ast2500-silicon-id
               - aspeed,ast2600-silicon-id
+              - aspeed,ast2700-silicon-id
           - const: aspeed,silicon-id
       reg:

Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml+598−0

@@ -0,0 +1,598 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/mfd/mediatek,mt6397.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: MediaTek MT6397/MT6323 PMIC
	8
	9	maintainers:
	10	- Sen Chu <sen.chu@mediatek.com>
	11	- Macpaul Lin <macpaul.lin@mediatek.com>
	12
	13	description: \|
	14	MT6397/MT6323 is a power management system chip.
	15	Please see the sub-modules below for supported features.
	16
	17	MT6397/MT6323 is a multifunction device with the following sub modules:
	18	- Regulators
	19	- RTC
	20	- ADC
	21	- Audio codec
	22	- GPIO
	23	- Clock
	24	- LED
	25	- Keys
	26	- Power controller
	27
	28	It is interfaced to host controller using SPI interface by a proprietary hardware
	29	called PMIC wrapper or pwrap. MT6397/MT6323 PMIC is a child device of pwrap.
	30	See the following for pwrap node definitions:
	31	Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
	32
	33	properties:
	34	compatible:
	35	oneOf:
	36	- enum:
	37	- mediatek,mt6323
	38	- mediatek,mt6331 # "mediatek,mt6331" for PMIC MT6331 and MT6332.
	39	- mediatek,mt6358
	40	- mediatek,mt6359
	41	- mediatek,mt6397
	42	- items:
	43	- enum:
	44	- mediatek,mt6366
	45	- const: mediatek,mt6358
	46
	47	interrupts:
	48	maxItems: 1
	49
	50	interrupt-controller: true
	51
	52	"#interrupt-cells":
	53	const: 2
	54
	55	rtc:
	56	type: object
	57	$ref: /schemas/rtc/rtc.yaml#
	58	unevaluatedProperties: false
	59	description:
	60	MT6397 Real Time Clock.
	61
	62	properties:
	63	compatible:
	64	oneOf:
	65	- enum:
	66	- mediatek,mt6323-rtc
	67	- mediatek,mt6331-rtc
	68	- mediatek,mt6358-rtc
	69	- mediatek,mt6397-rtc
	70	- items:
	71	- enum:
	72	- mediatek,mt6366-rtc
	73	- const: mediatek,mt6358-rtc
	74
	75	start-year: true
	76
	77	required:
	78	- compatible
	79
	80	regulators:
	81	type: object
	82	description:
	83	List of child nodes that specify the regulators.
	84	additionalProperties: true
	85
	86	properties:
	87	compatible:
	88	oneOf:
	89	- enum:
	90	- mediatek,mt6323-regulator
	91	- mediatek,mt6358-regulator
	92	- mediatek,mt6359-regulator
	93	- mediatek,mt6397-regulator
	94	- items:
	95	- enum:
	96	- mediatek,mt6366-regulator
	97	- const: mediatek,mt6358-regulator
	98
	99	required:
	100	- compatible
	101
	102	adc:
	103	type: object
	104	$ref: /schemas/iio/adc/mediatek,mt6359-auxadc.yaml#
	105	unevaluatedProperties: false
	106
	107	audio-codec:
	108	type: object
	109	description:
	110	Audio codec support with MT6358 and MT6397.
	111	additionalProperties: true
	112
	113	properties:
	114	compatible:
	115	oneOf:
	116	- enum:
	117	- mediatek,mt6358-sound
	118	- mediatek,mt6359-codec
	119	- mediatek,mt6397-codec
	120	- items:
	121	- enum:
	122	- mediatek,mt6366-sound
	123	- const: mediatek,mt6358-sound
	124
	125	required:
	126	- compatible
	127
	128	clocks:
	129	type: object
	130	additionalProperties: false
	131	description:
	132	This is a clock buffer node for mt6397. However, there are no sub nodes
	133	or any public document exposed in public.
	134
	135	properties:
	136	compatible:
	137	const: mediatek,mt6397-clk
	138
	139	'#clock-cells':
	140	const: 1
	141
	142	required:
	143	- compatible
	144
	145	leds:
	146	type: object
	147	additionalProperties: false
	148	description: \|
	149	MT6323 LED controller is subfunction provided by MT6323 PMIC, so the LED
	150	controllers are defined as the subnode of the function node provided by MT6323
	151	PMIC controller that is being defined as one kind of Muti-Function Device (MFD)
	152	using shared bus called PMIC wrapper for each subfunction to access remote
	153	MT6323 PMIC hardware.
	154
	155	Each led is represented as a child node of the mediatek,mt6323-led that
	156	describes the initial behavior for each LED physically and currently only four
	157	LED child nodes can be supported.
	158
	159	properties:
	160	compatible:
	161	enum:
	162	- mediatek,mt6323-led
	163	- mediatek,mt6331-led
	164	- mediatek,mt6332-led
	165
	166	reg:
	167	maxItems: 1
	168
	169	"#address-cells":
	170	const: 1
	171
	172	"#size-cells":
	173	const: 0
	174
	175	patternProperties:
	176	"^led@[0-3]$":
	177	type: object
	178	$ref: /schemas/leds/common.yaml#
	179	unevaluatedProperties: false
	180
	181	properties:
	182	reg:
	183	description:
	184	LED channel number (0..3)
	185	minimum: 0
	186	maximum: 3
	187
	188	required:
	189	- reg
	190
	191	required:
	192	- compatible
	193	- "#address-cells"
	194	- "#size-cells"
	195
	196	keys:
	197	type: object
	198	$ref: /schemas/input/mediatek,pmic-keys.yaml
	199	unevaluatedProperties: false
	200	description:
	201	Power and Home keys.
	202
	203	power-controller:
	204	type: object
	205	additionalProperties: false
	206	description:
	207	The power controller which could be found on PMIC is responsible for
	208	externally powering off or on the remote MediaTek SoC through the
	209	circuit BBPU (baseband power up).
	210
	211	properties:
	212	compatible:
	213	const: mediatek,mt6323-pwrc
	214
	215	'#power-domain-cells':
	216	const: 0
	217
	218	pinctrl:
	219	type: object
	220	$ref: /schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml
	221	unevaluatedProperties: false
	222	description:
	223	Pin controller
	224
	225	required:
	226	- compatible
	227	- regulators
	228
	229	additionalProperties: false
	230
	231	examples:
	232	- \|
	233	#include <dt-bindings/interrupt-controller/arm-gic.h>
	234	#include <dt-bindings/leds/common.h>
	235
	236	pmic {
	237	compatible = "mediatek,mt6323";
	238	interrupt-parent = <&pio>;
	239	interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
	240	interrupt-controller;
	241	#interrupt-cells = <2>;
	242
	243	leds {
	244	compatible = "mediatek,mt6323-led";
	245	#address-cells = <1>;
	246	#size-cells = <0>;
	247	};
	248
	249	regulators {
	250	compatible = "mediatek,mt6323-regulator";
	251
	252	buck_vproc {
	253	regulator-name = "vproc";
	254	regulator-min-microvolt = < 700000>;
	255	regulator-max-microvolt = <1350000>;
	256	regulator-ramp-delay = <12500>;
	257	regulator-always-on;
	258	regulator-boot-on;
	259	};
	260
	261	buck_vsys {
	262	regulator-name = "vsys";
	263	regulator-min-microvolt = <1400000>;
	264	regulator-max-microvolt = <2987500>;
	265	regulator-ramp-delay = <25000>;
	266	regulator-always-on;
	267	regulator-boot-on;
	268	};
	269
	270	buck_vpa {
	271	regulator-name = "vpa";
	272	regulator-min-microvolt = < 500000>;
	273	regulator-max-microvolt = <3650000>;
	274	};
	275
	276	ldo_vtcxo {
	277	regulator-name = "vtcxo";
	278	regulator-min-microvolt = <2800000>;
	279	regulator-max-microvolt = <2800000>;
	280	regulator-enable-ramp-delay = <90>;
	281	regulator-always-on;
	282	regulator-boot-on;
	283	};
	284
	285	ldo_vcn28 {
	286	regulator-name = "vcn28";
	287	regulator-min-microvolt = <2800000>;
	288	regulator-max-microvolt = <2800000>;
	289	regulator-enable-ramp-delay = <185>;
	290	};
	291
	292	ldo_vcn33_bt {
	293	regulator-name = "vcn33_bt";
	294	regulator-min-microvolt = <3300000>;
	295	regulator-max-microvolt = <3600000>;
	296	regulator-enable-ramp-delay = <185>;
	297	};
	298
	299	ldo_vcn33_wifi {
	300	regulator-name = "vcn33_wifi";
	301	regulator-min-microvolt = <3300000>;
	302	regulator-max-microvolt = <3600000>;
	303	regulator-enable-ramp-delay = <185>;
	304	};
	305
	306	ldo_va {
	307	regulator-name = "va";
	308	regulator-min-microvolt = <2800000>;
	309	regulator-max-microvolt = <2800000>;
	310	regulator-enable-ramp-delay = <216>;
	311	regulator-always-on;
	312	regulator-boot-on;
	313	};
	314
	315	ldo_vcama {
	316	regulator-name = "vcama";
	317	regulator-min-microvolt = <1500000>;
	318	regulator-max-microvolt = <2800000>;
	319	regulator-enable-ramp-delay = <216>;
	320	};
	321
	322	ldo_vio28 {
	323	regulator-name = "vio28";
	324	regulator-min-microvolt = <2800000>;
	325	regulator-max-microvolt = <2800000>;
	326	regulator-enable-ramp-delay = <216>;
	327	regulator-always-on;
	328	regulator-boot-on;
	329	};
	330
	331	ldo_vusb {
	332	regulator-name = "vusb";
	333	regulator-min-microvolt = <3300000>;
	334	regulator-max-microvolt = <3300000>;
	335	regulator-enable-ramp-delay = <216>;
	336	regulator-boot-on;
	337	};
	338
	339	ldo_vmc {
	340	regulator-name = "vmc";
	341	regulator-min-microvolt = <1800000>;
	342	regulator-max-microvolt = <3300000>;
	343	regulator-enable-ramp-delay = <36>;
	344	regulator-boot-on;
	345	};
	346
	347	ldo_vmch {
	348	regulator-name = "vmch";
	349	regulator-min-microvolt = <3000000>;
	350	regulator-max-microvolt = <3300000>;
	351	regulator-enable-ramp-delay = <36>;
	352	regulator-boot-on;
	353	};
	354
	355	ldo_vemc3v3 {
	356	regulator-name = "vemc3v3";
	357	regulator-min-microvolt = <3000000>;
	358	regulator-max-microvolt = <3300000>;
	359	regulator-enable-ramp-delay = <36>;
	360	regulator-boot-on;
	361	};
	362
	363	ldo_vgp1 {
	364	regulator-name = "vgp1";
	365	regulator-min-microvolt = <1200000>;
	366	regulator-max-microvolt = <3300000>;
	367	regulator-enable-ramp-delay = <216>;
	368	};
	369
	370	ldo_vgp2 {
	371	regulator-name = "vgp2";
	372	regulator-min-microvolt = <1200000>;
	373	regulator-max-microvolt = <3000000>;
	374	regulator-enable-ramp-delay = <216>;
	375	};
	376
	377	ldo_vgp3 {
	378	regulator-name = "vgp3";
	379	regulator-min-microvolt = <1200000>;
	380	regulator-max-microvolt = <1800000>;
	381	regulator-enable-ramp-delay = <216>;
	382	};
	383
	384	ldo_vcn18 {
	385	regulator-name = "vcn18";
	386	regulator-min-microvolt = <1800000>;
	387	regulator-max-microvolt = <1800000>;
	388	regulator-enable-ramp-delay = <216>;
	389	};
	390
	391	ldo_vsim1 {
	392	regulator-name = "vsim1";
	393	regulator-min-microvolt = <1800000>;
	394	regulator-max-microvolt = <3000000>;
	395	regulator-enable-ramp-delay = <216>;
	396	};
	397
	398	ldo_vsim2 {
	399	regulator-name = "vsim2";
	400	regulator-min-microvolt = <1800000>;
	401	regulator-max-microvolt = <3000000>;
	402	regulator-enable-ramp-delay = <216>;
	403	};
	404
	405	ldo_vrtc {
	406	regulator-name = "vrtc";
	407	regulator-min-microvolt = <2800000>;
	408	regulator-max-microvolt = <2800000>;
	409	regulator-always-on;
	410	regulator-boot-on;
	411	};
	412
	413	ldo_vcamaf {
	414	regulator-name = "vcamaf";
	415	regulator-min-microvolt = <1200000>;
	416	regulator-max-microvolt = <3300000>;
	417	regulator-enable-ramp-delay = <216>;
	418	};
	419
	420	ldo_vibr {
	421	regulator-name = "vibr";
	422	regulator-min-microvolt = <1200000>;
	423	regulator-max-microvolt = <3300000>;
	424	regulator-enable-ramp-delay = <36>;
	425	};
	426
	427	ldo_vrf18 {
	428	regulator-name = "vrf18";
	429	regulator-min-microvolt = <1825000>;
	430	regulator-max-microvolt = <1825000>;
	431	regulator-enable-ramp-delay = <187>;
	432	};
	433
	434	ldo_vm {
	435	regulator-name = "vm";
	436	regulator-min-microvolt = <1200000>;
	437	regulator-max-microvolt = <1800000>;
	438	regulator-enable-ramp-delay = <216>;
	439	regulator-always-on;
	440	regulator-boot-on;
	441	};
	442
	443	ldo_vio18 {
	444	regulator-name = "vio18";
	445	regulator-min-microvolt = <1800000>;
	446	regulator-max-microvolt = <1800000>;
	447	regulator-enable-ramp-delay = <216>;
	448	regulator-always-on;
	449	regulator-boot-on;
	450	};
	451
	452	ldo_vcamd {
	453	regulator-name = "vcamd";
	454	regulator-min-microvolt = <1200000>;
	455	regulator-max-microvolt = <1800000>;
	456	regulator-enable-ramp-delay = <216>;
	457	};
	458
	459	ldo_vcamio {
	460	regulator-name = "vcamio";
	461	regulator-min-microvolt = <1800000>;
	462	regulator-max-microvolt = <1800000>;
	463	regulator-enable-ramp-delay = <216>;
	464	};
	465	};
	466
	467	keys {
	468	compatible = "mediatek,mt6323-keys";
	469	mediatek,long-press-mode = <1>;
	470	power-off-time-sec = <0>;
	471
	472	power {
	473	linux,keycodes = <116>;
	474	wakeup-source;
	475	};
	476
	477	home {
	478	linux,keycodes = <114>;
	479	};
	480	};
	481
	482	power-controller {
	483	compatible = "mediatek,mt6323-pwrc";
	484	#power-domain-cells = <0>;
	485	};
	486
	487	rtc {
	488	compatible = "mediatek,mt6323-rtc";
	489	};
	490	};
	491
	492	- \|
	493	#include <dt-bindings/input/input.h>
	494	#include <dt-bindings/interrupt-controller/arm-gic.h>
	495
	496	pmic {
	497	compatible = "mediatek,mt6358";
	498	interrupt-controller;
	499	#interrupt-cells = <2>;
	500
	501	audio-codec {
	502	compatible = "mediatek,mt6358-sound";
	503	Avdd-supply = <&mt6358_vaud28_reg>;
	504	mediatek,dmic-mode = <0>;
	505	};
	506
	507	regulators {
	508	compatible = "mediatek,mt6358-regulator";
	509
	510	buck_vdram1 {
	511	regulator-name = "vdram1";
	512	regulator-min-microvolt = <500000>;
	513	regulator-max-microvolt = <2087500>;
	514	regulator-ramp-delay = <12500>;
	515	regulator-enable-ramp-delay = <0>;
	516	regulator-always-on;
	517	regulator-allowed-modes = <0 1>;
	518	};
	519
	520	// ...
	521
	522	ldo_vsim2 {
	523	regulator-name = "vsim2";
	524	regulator-min-microvolt = <1700000>;
	525	regulator-max-microvolt = <3100000>;
	526	regulator-enable-ramp-delay = <540>;
	527	};
	528	};
	529
	530	rtc {
	531	compatible = "mediatek,mt6358-rtc";
	532	};
	533
	534	keys {
	535	compatible = "mediatek,mt6358-keys";
	536
	537	power {
	538	linux,keycodes = <KEY_POWER>;
	539	wakeup-source;
	540	};
	541
	542	home {
	543	linux,keycodes = <KEY_HOME>;
	544	};
	545	};
	546	};
	547
	548	- \|
	549	#include <dt-bindings/interrupt-controller/arm-gic.h>
	550
	551	pmic {
	552	compatible = "mediatek,mt6397";
	553
	554	interrupt-parent = <&pio>;
	555	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
	556	interrupt-controller;
	557	#interrupt-cells = <2>;
	558
	559	audio-codec {
	560	compatible = "mediatek,mt6397-codec";
	561	};
	562
	563	clocks {
	564	compatible = "mediatek,mt6397-clk";
	565	#clock-cells = <1>;
	566	};
	567
	568	pinctrl {
	569	compatible = "mediatek,mt6397-pinctrl";
	570	gpio-controller;
	571	#gpio-cells = <2>;
	572	};
	573
	574	regulators {
	575	compatible = "mediatek,mt6397-regulator";
	576
	577	buck_vpca15 {
	578	regulator-name = "vpca15";
	579	regulator-min-microvolt = < 850000>;
	580	regulator-max-microvolt = <1350000>;
	581	regulator-ramp-delay = <12500>;
	582	regulator-enable-ramp-delay = <200>;
	583	};
	584
	585	// ...
	586
	587	ldo_vibr {
	588	regulator-name = "vibr";
	589	regulator-min-microvolt = <1200000>;
	590	regulator-max-microvolt = <3300000>;
	591	regulator-enable-ramp-delay = <218>;
	592	};
	593	};
	594
	595	rtc {
	596	compatible = "mediatek,mt6397-rtc";
	597	};
	598	};

Documentation/devicetree/bindings/mfd/mt6397.txt+0−110

@@ -1,110 +0,0 @@
1	MediaTek MT6397/MT6323 Multifunction Device Driver
2
3	MT6397/MT6323 is a multifunction device with the following sub modules:
4	- Regulator
5	- RTC
6	- Audio codec
7	- GPIO
8	- Clock
9	- LED
10	- Keys
11	- Power controller
12
13	It is interfaced to host controller using SPI interface by a proprietary hardware
14	called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap.
15	See the following for pwarp node definitions:
16	../soc/mediatek/mediatek,pwrap.yaml
17
18	This document describes the binding for MFD device and its sub module.
19
20	Required properties:
21	compatible:
22	"mediatek,mt6323" for PMIC MT6323
23	"mediatek,mt6331" for PMIC MT6331 and MT6332
24	"mediatek,mt6357" for PMIC MT6357
25	"mediatek,mt6358" for PMIC MT6358
26	"mediatek,mt6359" for PMIC MT6359
27	"mediatek,mt6366", "mediatek,mt6358" for PMIC MT6366
28	"mediatek,mt6397" for PMIC MT6397
29
30	Optional subnodes:
31
32	- rtc
33	Required properties: Should be one of follows
34	- compatible: "mediatek,mt6323-rtc"
35	- compatible: "mediatek,mt6331-rtc"
36	- compatible: "mediatek,mt6358-rtc"
37	- compatible: "mediatek,mt6397-rtc"
38	For details, see ../rtc/rtc-mt6397.txt
39	- regulators
40	Required properties:
41	- compatible: "mediatek,mt6323-regulator"
42	see ../regulator/mt6323-regulator.txt
43	- compatible: "mediatek,mt6358-regulator"
44	- compatible: "mediatek,mt6366-regulator", "mediatek-mt6358-regulator"
45	see ../regulator/mt6358-regulator.txt
46	- compatible: "mediatek,mt6397-regulator"
47	see ../regulator/mt6397-regulator.txt
48	- codec
49	Required properties:
50	- compatible: "mediatek,mt6397-codec" or "mediatek,mt6358-sound"
51	- clk
52	Required properties:
53	- compatible: "mediatek,mt6397-clk"
54	- led
55	Required properties:
56	- compatible: "mediatek,mt6323-led"
57	see ../leds/leds-mt6323.txt
58
59	- keys
60	Required properties: Should be one of the following
61	- compatible: "mediatek,mt6323-keys"
62	- compatible: "mediatek,mt6331-keys"
63	- compatible: "mediatek,mt6397-keys"
64	see ../input/mtk-pmic-keys.txt
65
66	- power-controller
67	Required properties:
68	- compatible: "mediatek,mt6323-pwrc"
69	For details, see ../power/reset/mt6323-poweroff.txt
70
71	- pin-controller
72	Required properties:
73	- compatible: "mediatek,mt6397-pinctrl"
74	For details, see ../pinctrl/pinctrl-mt65xx.txt
75
76	Example:
77	pwrap: pwrap@1000f000 {
78	compatible = "mediatek,mt8135-pwrap";
79
80	...
81
82	pmic {
83	compatible = "mediatek,mt6397";
84
85	codec: mt6397codec {
86	compatible = "mediatek,mt6397-codec";
87	};
88
89	regulators {
90	compatible = "mediatek,mt6397-regulator";
91
92	mt6397_vpca15_reg: buck_vpca15 {
93	regulator-compatible = "buck_vpca15";
94	regulator-name = "vpca15";
95	regulator-min-microvolt = <850000>;
96	regulator-max-microvolt = <1400000>;
97	regulator-ramp-delay = <12500>;
98	regulator-always-on;
99	};
100
101	mt6397_vgp4_reg: ldo_vgp4 {
102	regulator-compatible = "ldo_vgp4";
103	regulator-name = "vgp4";
104	regulator-min-microvolt = <1200000>;
105	regulator-max-microvolt = <3300000>;
106	regulator-enable-ramp-delay = <218>;
107	};
108	};
109	};
110	};

Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml+2−0

           - qcom,pmc8180
           - qcom,pmc8180c
           - qcom,pmc8380
+          - qcom,pmd8028
           - qcom,pmd9635
           - qcom,pmi632
           - qcom,pmi8950
           - qcom,pmi8962
           - qcom,pmi8994
           - qcom,pmi8998
+          - qcom,pmih0108
           - qcom,pmk8002
           - qcom,pmk8350
           - qcom,pmk8550

Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml+4−0

           - qcom,msm8998-tcsr
           - qcom,qcm2290-tcsr
           - qcom,qcs404-tcsr
+          - qcom,qcs615-tcsr
+          - qcom,qcs8300-tcsr
+          - qcom,sa8255p-tcsr
           - qcom,sa8775p-tcsr
           - qcom,sc7180-tcsr
           - qcom,sc7280-tcsr
           - qcom,tcsr-msm8226
           - qcom,tcsr-msm8660
           - qcom,tcsr-msm8916
+          - qcom,tcsr-msm8917
           - qcom,tcsr-msm8953
           - qcom,tcsr-msm8960
           - qcom,tcsr-msm8974

Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml+114−0

@@ -0,0 +1,114 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/mfd/realtek,rtl9301-switch.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Realtek Switch with Internal CPU
	8
	9	maintainers:
	10	- Chris Packham <chris.packham@alliedtelesis.co.nz>
	11
	12	description:
	13	The RTL9300 is a series of is an Ethernet switches with an integrated CPU. A
	14	number of different peripherals are accessed through a common register block,
	15	represented here as a syscon node.
	16
	17	properties:
	18	compatible:
	19	items:
	20	- enum:
	21	- realtek,rtl9301-switch
	22	- realtek,rtl9302b-switch
	23	- realtek,rtl9302c-switch
	24	- realtek,rtl9303-switch
	25	- const: syscon
	26	- const: simple-mfd
	27
	28	reg:
	29	maxItems: 1
	30
	31	'#address-cells':
	32	const: 1
	33
	34	'#size-cells':
	35	const: 1
	36
	37	patternProperties:
	38	'reboot@[0-9a-f]+$':
	39	$ref: /schemas/power/reset/syscon-reboot.yaml#
	40
	41	'i2c@[0-9a-f]+$':
	42	$ref: /schemas/i2c/realtek,rtl9301-i2c.yaml#
	43
	44	required:
	45	- compatible
	46	- reg
	47
	48	additionalProperties: false
	49
	50	examples:
	51	- \|
	52	ethernet-switch@1b000000 {
	53	compatible = "realtek,rtl9301-switch", "syscon", "simple-mfd";
	54	reg = <0x1b000000 0x10000>;
	55	#address-cells = <1>;
	56	#size-cells = <1>;
	57
	58	reboot@c {
	59	compatible = "syscon-reboot";
	60	reg = <0x0c 0x4>;
	61	value = <0x01>;
	62	};
	63
	64	i2c@36c {
	65	compatible = "realtek,rtl9301-i2c";
	66	reg = <0x36c 0x14>;
	67	#address-cells = <1>;
	68	#size-cells = <0>;
	69
	70	i2c@0 {
	71	reg = <0>;
	72	#address-cells = <1>;
	73	#size-cells = <0>;
	74	gpio@20 {
	75	compatible = "nxp,pca9555";
	76	gpio-controller;
	77	#gpio-cells = <2>;
	78	reg = <0x20>;
	79	};
	80	};
	81
	82	i2c@2 {
	83	reg = <2>;
	84	#address-cells = <1>;
	85	#size-cells = <0>;
	86	gpio@20 {
	87	compatible = "nxp,pca9555";
	88	gpio-controller;
	89	#gpio-cells = <2>;
	90	reg = <0x20>;
	91	};
	92	};
	93	};
	94
	95	i2c@388 {
	96	compatible = "realtek,rtl9301-i2c";
	97	reg = <0x388 0x14>;
	98	#address-cells = <1>;
	99	#size-cells = <0>;
	100
	101	i2c@7 {
	102	reg = <7>;
	103	#address-cells = <1>;
	104	#size-cells = <0>;
	105	gpio@20 {
	106	compatible = "nxp,pca9555";
	107	gpio-controller;
	108	#gpio-cells = <2>;
	109	reg = <0x20>;
	110	};
	111	};
	112	};
	113	};
	114

Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml+7−6

     minimum: 0
     maximum: 1
-  rohm,charger-sense-resistor-ohms:
+  rohm,charger-sense-resistor-micro-ohms:
-    minimum: 10000000
+    minimum: 10000
-    maximum: 50000000
+    maximum: 50000
+    default: 30000
     description: |
       BD71827 and BD71828 have SAR ADC for measuring charging currents.
       External sense resistor (RSENSE in data sheet) should be used. If some
-      other but 30MOhm resistor is used the resistance value should be given
+      other but 30mOhm resistor is used the resistance value should be given
-      here in Ohms.
+      here in microohms.
   regulators:
     $ref: /schemas/regulator/rohm,bd71828-regulator.yaml
             #gpio-cells = <2>;
             gpio-reserved-ranges = <0 1>, <2 1>;
-            rohm,charger-sense-resistor-ohms = <10000000>;
+            rohm,charger-sense-resistor-micro-ohms = <10000>;
             regulators {
                 buck1: BUCK1 {

Documentation/devicetree/bindings/mfd/samsung,s2dos05.yaml+99−0

@@ -0,0 +1,99 @@
	1	# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/mfd/samsung,s2dos05.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Samsung S2DOS05 Power Management IC
	8
	9	maintainers:
	10	- Dzmitry Sankouski <dsankouski@gmail.com>
	11
	12	description:
	13	This is a device tree bindings for S2DOS family of Power Management IC (PMIC).
	14
	15	The S2DOS05 is a companion power management IC for the panel and touchscreen
	16	in smart phones. Provides voltage regulators and
	17	ADC for power/current measurements.
	18
	19	Regulator section has 4 LDO and 1 BUCK regulators and also
	20	provides ELVDD, ELVSS, AVDD lines.
	21
	22	properties:
	23	compatible:
	24	const: samsung,s2dos05
	25
	26	reg:
	27	maxItems: 1
	28
	29	regulators:
	30	patternProperties:
	31	"^buck\|ldo[1-4]$":
	32	type: object
	33	$ref: /schemas/regulator/regulator.yaml#
	34	unevaluatedProperties: false
	35
	36	required:
	37	- regulator-name
	38
	39	additionalProperties: false
	40
	41	required:
	42	- compatible
	43	- reg
	44	- regulators
	45
	46	additionalProperties: false
	47
	48	examples:
	49	- \|
	50	i2c {
	51	#address-cells = <1>;
	52	#size-cells = <0>;
	53
	54	pmic@60 {
	55	compatible = "samsung,s2dos05";
	56	reg = <0x60>;
	57
	58	regulators {
	59	ldo1 {
	60	regulator-active-discharge = <1>;
	61	regulator-min-microvolt = <1500000>;
	62	regulator-max-microvolt = <2000000>;
	63	regulator-name = "ldo1";
	64	};
	65
	66	ldo2 {
	67	regulator-active-discharge = <1>;
	68	regulator-boot-on;
	69	regulator-min-microvolt = <1800000>;
	70	regulator-max-microvolt = <1800000>;
	71	regulator-name = "ldo2";
	72	};
	73
	74	ldo3 {
	75	regulator-active-discharge = <1>;
	76	regulator-boot-on;
	77	regulator-min-microvolt = <3000000>;
	78	regulator-max-microvolt = <3000000>;
	79	regulator-name = "ldo3";
	80	};
	81
	82	ldo4 {
	83	regulator-active-discharge = <1>;
	84	regulator-min-microvolt = <2700000>;
	85	regulator-max-microvolt = <3775000>;
	86	regulator-name = "ldo4";
	87	};
	88
	89	buck {
	90	regulator-active-discharge = <1>;
	91	regulator-min-microvolt = <850000>;
	92	regulator-max-microvolt = <2100000>;
	93	regulator-name = "buck";
	94	};
	95	};
	96	};
	97	};
	98
	99	...

Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml+252−0

@@ -0,0 +1,252 @@
	1	# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/mfd/sprd,sc2731.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Spreadtrum SC27xx PMIC
	8
	9	maintainers:
	10	- Orson Zhai <orsonzhai@gmail.com>
	11	- Baolin Wang <baolin.wang7@gmail.com>
	12	- Chunyan Zhang <zhang.lyra@gmail.com>
	13
	14	description: \|
	15	Spreadtrum PMICs belonging to the SC27xx series integrate all mobile handset
	16	power management, audio codec, battery management and user interface support
	17	functions in a single chip. They have 6 major functional blocks:
	18	- DCDCs to support CPU, memory
	19	- LDOs to support both internal and external requirements
	20	- Battery management system, such as charger, fuel gauge
	21	- Audio codec
	22	- User interface functions, such as indicator, flash LED and so on
	23	- IC level interface, such as power on/off control, RTC, typec and so on
	24
	25	properties:
	26	$nodename:
	27	pattern: '^pmic@[0-9a-f]+$'
	28
	29	compatible:
	30	enum:
	31	- sprd,sc2720
	32	- sprd,sc2721
	33	- sprd,sc2723
	34	- sprd,sc2730
	35	- sprd,sc2731
	36
	37	reg:
	38	maxItems: 1
	39
	40	interrupts:
	41	maxItems: 1
	42
	43	interrupt-controller: true
	44	spi-max-frequency: true
	45
	46	'#address-cells':
	47	const: 1
	48
	49	'#interrupt-cells':
	50	const: 1
	51
	52	'#size-cells':
	53	const: 0
	54
	55	regulators:
	56	type: object
	57	$ref: /schemas/regulator/sprd,sc2731-regulator.yaml#
	58
	59	patternProperties:
	60	"^adc@[0-9a-f]+$":
	61	type: object
	62	$ref: /schemas/iio/adc/sprd,sc2720-adc.yaml#
	63
	64	"^charger@[0-9a-f]+$":
	65	type: object
	66	$ref: /schemas/power/supply/sc2731-charger.yaml#
	67
	68	"^efuse@[0-9a-f]+$":
	69	type: object
	70	additionalProperties: true
	71	properties:
	72	compatible:
	73	enum:
	74	- sprd,sc2720-efuse
	75	- sprd,sc2721-efuse
	76	- sprd,sc2723-efuse
	77	- sprd,sc2730-efuse
	78	- sprd,sc2731-efuse
	79
	80	"^fuel-gauge@[0-9a-f]+$":
	81	type: object
	82	$ref: /schemas/power/supply/sc27xx-fg.yaml#
	83
	84	"^gpio@[0-9a-f]+$":
	85	type: object
	86	$ref: /schemas/gpio/sprd,gpio-eic.yaml#
	87
	88	"^led-controller@[0-9a-f]+$":
	89	type: object
	90	$ref: /schemas/leds/sprd,sc2731-bltc.yaml#
	91
	92	"^rtc@[0-9a-f]+$":
	93	type: object
	94	$ref: /schemas/rtc/sprd,sc2731-rtc.yaml#
	95
	96	"^vibrator@[0-9a-f]+$":
	97	type: object
	98	$ref: /schemas/input/sprd,sc27xx-vibrator.yaml#
	99
	100	required:
	101	- compatible
	102	- reg
	103	- interrupts
	104	- interrupt-controller
	105	- spi-max-frequency
	106	- '#address-cells'
	107	- '#interrupt-cells'
	108	- '#size-cells'
	109
	110	additionalProperties: false
	111
	112	examples:
	113	- \|
	114	#include <dt-bindings/gpio/gpio.h>
	115	#include <dt-bindings/interrupt-controller/arm-gic.h>
	116	#include <dt-bindings/interrupt-controller/irq.h>
	117	#include <dt-bindings/leds/common.h>
	118
	119	spi {
	120	#address-cells = <1>;
	121	#size-cells = <0>;
	122
	123	sc2731_pmic: pmic@0 {
	124	compatible = "sprd,sc2731";
	125	reg = <0>;
	126	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	127	interrupt-controller;
	128	spi-max-frequency = <26000000>;
	129	#address-cells = <1>;
	130	#interrupt-cells = <1>;
	131	#size-cells = <0>;
	132
	133	charger@0 {
	134	compatible = "sprd,sc2731-charger";
	135	reg = <0x0>;
	136	phys = <&ssphy>;
	137	monitored-battery = <&bat>;
	138	};
	139
	140	led-controller@200 {
	141	compatible = "sprd,sc2731-bltc";
	142	reg = <0x200>;
	143	#address-cells = <1>;
	144	#size-cells = <0>;
	145
	146	led@0 {
	147	reg = <0x0>;
	148	color = <LED_COLOR_ID_RED>;
	149	};
	150
	151	led@1 {
	152	reg = <0x1>;
	153	color = <LED_COLOR_ID_GREEN>;
	154	};
	155
	156	led@2 {
	157	reg = <0x2>;
	158	color = <LED_COLOR_ID_BLUE>;
	159	};
	160	};
	161
	162	rtc@280 {
	163	compatible = "sprd,sc2731-rtc";
	164	reg = <0x280>;
	165	interrupt-parent = <&sc2731_pmic>;
	166	interrupts = <2>;
	167	};
	168
	169	pmic_eic: gpio@300 {
	170	compatible = "sprd,sc2731-eic";
	171	reg = <0x300>;
	172	interrupt-parent = <&sc2731_pmic>;
	173	interrupts = <5>;
	174	gpio-controller;
	175	#gpio-cells = <2>;
	176	interrupt-controller;
	177	#interrupt-cells = <2>;
	178	};
	179
	180	efuse@380 {
	181	compatible = "sprd,sc2731-efuse";
	182	reg = <0x380>;
	183	hwlocks = <&hwlock 12>;
	184	#address-cells = <1>;
	185	#size-cells = <1>;
	186
	187	/* Data cells */
	188	fgu_calib: calib@6 {
	189	reg = <0x6 0x2>;
	190	bits = <0 9>;
	191	};
	192
	193	adc_big_scale: calib@24 {
	194	reg = <0x24 0x2>;
	195	};
	196
	197	adc_small_scale: calib@26 {
	198	reg = <0x26 0x2>;
	199	};
	200	};
	201
	202	adc@480 {
	203	compatible = "sprd,sc2731-adc";
	204	reg = <0x480>;
	205	interrupt-parent = <&sc2731_pmic>;
	206	interrupts = <0>;
	207	#io-channel-cells = <1>;
	208	hwlocks = <&hwlock 4>;
	209	nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
	210	nvmem-cell-names = "big_scale_calib", "small_scale_calib";
	211	};
	212
	213	fuel-gauge@a00 {
	214	compatible = "sprd,sc2731-fgu";
	215	reg = <0xa00>;
	216	battery-detect-gpios = <&pmic_eic 9 GPIO_ACTIVE_HIGH>;
	217	interrupt-parent = <&sc2731_pmic>;
	218	interrupts = <4>;
	219	io-channels = <&pmic_adc 5>, <&pmic_adc 14>;
	220	io-channel-names = "bat-temp", "charge-vol";
	221	nvmem-cells = <&fgu_calib>;
	222	nvmem-cell-names = "fgu_calib";
	223	monitored-battery = <&bat>;
	224	sprd,calib-resistance-micro-ohms = <21500>;
	225	};
	226
	227	vibrator@ec8 {
	228	compatible = "sprd,sc2731-vibrator";
	229	reg = <0xec8>;
	230	};
	231
	232	regulators {
	233	compatible = "sprd,sc2731-regulator";
	234
	235	BUCK_CPU0 {
	236	regulator-name = "vddarm0";
	237	regulator-min-microvolt = <400000>;
	238	regulator-max-microvolt = <1996875>;
	239	regulator-ramp-delay = <25000>;
	240	regulator-always-on;
	241	};
	242
	243	LDO_CAMA0 {
	244	regulator-name = "vddcama0";
	245	regulator-min-microvolt = <1200000>;
	246	regulator-max-microvolt = <3750000>;
	247	regulator-enable-ramp-delay = <100>;
	248	};
	249	};
	250	};
	251	};
	252	...

Documentation/devicetree/bindings/mfd/sprd,sc27xx-pmic.txt+0−40

@@ -1,40 +0,0 @@
1	Spreadtrum SC27xx Power Management Integrated Circuit (PMIC)
2
3	The Spreadtrum SC27xx series PMICs contain SC2720, SC2721, SC2723, SC2730
4	and SC2731. The Spreadtrum PMIC belonging to SC27xx series integrates all
5	mobile handset power management, audio codec, battery management and user
6	interface support function in a single chip. It has 6 major functional
7	blocks:
8	- DCDCs to support CPU, memory.
9	- LDOs to support both internal and external requirement.
10	- Battery management system, such as charger, fuel gauge.
11	- Audio codec.
12	- User interface function, such as indicator, flash LED and so on.
13	- IC level interface, such as power on/off control, RTC and typec and so on.
14
15	Required properties:
16	- compatible: Should be one of the following:
17	"sprd,sc2720"
18	"sprd,sc2721"
19	"sprd,sc2723"
20	"sprd,sc2730"
21	"sprd,sc2731"
22	- reg: The address of the device chip select, should be 0.
23	- spi-max-frequency: Typically set to 26000000.
24	- interrupts: The interrupt line the device is connected to.
25	- interrupt-controller: Marks the device node as an interrupt controller.
26	- #interrupt-cells: The number of cells to describe an PMIC IRQ, must be 2.
27	- #address-cells: Child device offset number of cells, must be 1.
28	- #size-cells: Child device size number of cells, must be 0.
29
30	Example:
31	pmic@0 {
32	compatible = "sprd,sc2731";
33	reg = <0>;
34	spi-max-frequency = <26000000>;
35	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
36	interrupt-controller;
37	#interrupt-cells = <2>;
38	#address-cells = <1>;
39	#size-cells = <0>;
40	};

Documentation/devicetree/bindings/mfd/syscon.yaml+2−0

           - mediatek,mt8173-pctl-a-syscfg
           - mediatek,mt8365-syscfg
           - microchip,lan966x-cpu-syscon
+          - microchip,mpfs-sysreg-scb
           - microchip,sam9x60-sfr
           - microchip,sama7g5-ddr3phy
           - mscc,ocelot-cpu-syscon
           - mediatek,mt8173-pctl-a-syscfg
           - mediatek,mt8365-syscfg
           - microchip,lan966x-cpu-syscon
+          - microchip,mpfs-sysreg-scb
           - microchip,sam9x60-sfr
           - microchip,sama7g5-ddr3phy
           - mscc,ocelot-cpu-syscon

Documentation/devicetree/bindings/mfd/ti,twl.yaml+30−2

           $ref: /schemas/iio/adc/ti,twl4030-madc.yaml
           unevaluatedProperties: false
-        bci:
+        charger:
           type: object
           $ref: /schemas/power/supply/twl4030-charger.yaml
           unevaluatedProperties: false
             regulator-initial-mode: false
       properties:
+        charger:
+          type: object
+          properties:
+            compatible:
+              const: ti,twl6030-charger
         gpadc:
           type: object
           properties:
             regulator-initial-mode: false
       properties:
+        charger:
+          type: object
+          properties:
+            compatible:
+              items:
+                - const: ti,twl6032-charger
+                - const: ti,twl6030-charger
         gpadc:
           type: object
           properties:
   "#clock-cells":
     const: 1
+  charger:
+    type: object
+    additionalProperties: true
+    properties:
+      compatible: true
+    required:
+      - compatible
   rtc:
     type: object
     additionalProperties: false
         interrupt-controller;
         #interrupt-cells = <1>;
+        charger {
+          compatible = "ti,twl6030-charger";
+          interrupts = <2>, <5>;
+          io-channels = <&gpadc 10>;
+          io-channel-names = "vusb";
+          monitored-battery = <&bat>;
+        };
         gpadc {
           compatible = "ti,twl6030-gpadc";
           interrupts = <6>;
         interrupt-controller;
         #interrupt-cells = <1>;
-        bci {
+        charger {
           compatible = "ti,twl4030-bci";
           interrupts = <9>, <2>;
           bci3v1-supply = <&vusb3v1>;

Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml+3−0

                 - x-powers,axp15060
                 - x-powers,axp305
                 - x-powers,axp313a
+                - x-powers,axp323
     then:
       required:
           contains:
             enum:
               - x-powers,axp313a
+              - x-powers,axp323
               - x-powers,axp15060
               - x-powers,axp717
           - x-powers,axp221
           - x-powers,axp223
           - x-powers,axp313a
+          - x-powers,axp323
           - x-powers,axp717
           - x-powers,axp803
           - x-powers,axp806

Documentation/devicetree/bindings/mfd/zii,rave-sp.txt+0−39

@@ -1,39 +0,0 @@
1	Zodiac Inflight Innovations RAVE Supervisory Processor
2
3	RAVE Supervisory Processor communicates with SoC over UART. It is
4	expected that its Device Tree node is specified as a child of a node
5	corresponding to UART controller used for communication.
6
7	Required parent device properties:
8
9	- compatible: Should be one of:
10	- "zii,rave-sp-niu"
11	- "zii,rave-sp-mezz"
12	- "zii,rave-sp-esb"
13	- "zii,rave-sp-rdu1"
14	- "zii,rave-sp-rdu2"
15
16	- current-speed: Should be set to baud rate SP device is using
17
18	RAVE SP consists of the following sub-devices:
19
20	Device Description
21	------ -----------
22	rave-sp-wdt : Watchdog
23	rave-sp-nvmem : Interface to onboard EEPROM
24	rave-sp-backlight : Display backlight
25	rave-sp-hwmon : Interface to onboard hardware sensors
26	rave-sp-leds : Interface to onboard LEDs
27	rave-sp-input : Interface to onboard power button
28
29	Example of usage:
30
31	rdu {
32	compatible = "zii,rave-sp-rdu2";
33	current-speed = <1000000>;
34
35	watchdog {
36	compatible = "zii,rave-sp-watchdog";
37	};
38	};
39

Documentation/devicetree/bindings/mfd/zii,rave-sp.yaml+63−0

@@ -0,0 +1,63 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/mfd/zii,rave-sp.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Zodiac Inflight Innovations RAVE Supervisory Processor
	8
	9	maintainers:
	10	- Frank Li <Frank.Li@nxp.com>
	11
	12	description:
	13	RAVE Supervisory Processor communicates with SoC over UART. It is
	14	expected that its Device Tree node is specified as a child of a node
	15	corresponding to UART controller used for communication.
	16
	17	properties:
	18	compatible:
	19	enum:
	20	- zii,rave-sp-niu
	21	- zii,rave-sp-mezz
	22	- zii,rave-sp-esb
	23	- zii,rave-sp-rdu1
	24	- zii,rave-sp-rdu2
	25
	26	"#address-cells":
	27	const: 1
	28
	29	"#size-cells":
	30	const: 1
	31
	32	watchdog:
	33	$ref: /schemas/watchdog/zii,rave-sp-wdt.yaml
	34
	35	backlight:
	36	$ref: /schemas/leds/backlight/zii,rave-sp-backlight.yaml
	37
	38	pwrbutton:
	39	$ref: /schemas/input/zii,rave-sp-pwrbutton.yaml
	40
	41	patternProperties:
	42	'^eeprom@[0-9a-f]+$':
	43	$ref: /schemas/nvmem/zii,rave-sp-eeprom.yaml
	44
	45	required:
	46	- compatible
	47
	48	allOf:
	49	- $ref: /schemas/serial/serial-peripheral-props.yaml
	50
	51	unevaluatedProperties: false
	52
	53	examples:
	54	- \|
	55	mfd {
	56	compatible = "zii,rave-sp-rdu2";
	57	current-speed = <1000000>;
	58
	59	watchdog {
	60	compatible = "zii,rave-sp-watchdog";
	61	};
	62	};
	63

Documentation/devicetree/bindings/power/reset/mt6323-poweroff.txt+0−20

@@ -1,20 +0,0 @@
1	Device Tree Bindings for Power Controller on MediaTek PMIC
2
3	The power controller which could be found on PMIC is responsible for externally
4	powering off or on the remote MediaTek SoC through the circuit BBPU.
5
6	Required properties:
7	- compatible: Should be one of follows
8	"mediatek,mt6323-pwrc": for MT6323 PMIC
9
10	Example:
11
12	pmic {
13	compatible = "mediatek,mt6323";
14
15	...
16
17	power-controller {
18	compatible = "mediatek,mt6323-pwrc";
19	};
20	}

Documentation/devicetree/bindings/power/supply/sc2731-charger.yaml+1−20

@@ -30,23 +30,4 @@ properties: · 29 unmodified lines
30	- constant-charge-voltage-max-microvolt: maximum constant input voltage.	30	- constant-charge-voltage-max-microvolt: maximum constant input voltage.
31		31
32	additionalProperties: false	32	additionalProperties: false
33		33	...
34	examples:
35	- \|
36	bat: battery {
37	compatible = "simple-battery";
38	charge-term-current-microamp = <120000>;
39	constant-charge-voltage-max-microvolt = <4350000>;
40	};
41
42	pmic {
43	#address-cells = <1>;
44	#size-cells = <0>;
45
46	battery@a00 {
47	compatible = "sprd,sc2731-charger";
48	reg = <0x0>;
49	phys = <&ssphy>;
50	monitored-battery = <&bat>;
51	};
52	};

Documentation/devicetree/bindings/power/supply/sc27xx-fg.yaml+1−37

@@ -65,40 +65,4 @@ required: · 64 unmodified lines
65	- monitored-battery	65	- monitored-battery
66		66
67	additionalProperties: false	67	additionalProperties: false
68		68	...
69	examples:
70	- \|
71	#include <dt-bindings/gpio/gpio.h>
72	bat: battery {
73	compatible = "simple-battery";
74	charge-full-design-microamp-hours = <1900000>;
75	constant-charge-voltage-max-microvolt = <4350000>;
76	ocv-capacity-celsius = <20>;
77	ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>,
78	<4022000 85>, <3983000 80>, <3949000 75>,
79	<3917000 70>, <3889000 65>, <3864000 60>,
80	<3835000 55>, <3805000 50>, <3787000 45>,
81	<3777000 40>, <3773000 35>, <3770000 30>,
82	<3765000 25>, <3752000 20>, <3724000 15>,
83	<3680000 10>, <3605000 5>, <3400000 0>;
84	// ...
85	};
86
87	pmic {
88	#address-cells = <1>;
89	#size-cells = <0>;
90
91	battery@a00 {
92	compatible = "sprd,sc2731-fgu";
93	reg = <0xa00>;
94	battery-detect-gpios = <&pmic_eic 9 GPIO_ACTIVE_HIGH>;
95	interrupt-parent = <&sc2731_pmic>;
96	interrupts = <4>;
97	io-channels = <&pmic_adc 5>, <&pmic_adc 14>;
98	io-channel-names = "bat-temp", "charge-vol";
99	nvmem-cells = <&fgu_calib>;
100	nvmem-cell-names = "fgu_calib";
101	monitored-battery = <&bat>;
102	sprd,calib-resistance-micro-ohms = <21500>;
103	};
104	};

Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.yaml+0−21

@@ -43,25 +43,4 @@ required: · 42 unmodified lines
43	- compatible	43	- compatible
44		44
45	additionalProperties: false	45	additionalProperties: false
46
47	examples:
48	- \|
49	regulators {
50	compatible = "sprd,sc2731-regulator";
51
52	BUCK_CPU0 {
53	regulator-name = "vddarm0";
54	regulator-min-microvolt = <400000>;
55	regulator-max-microvolt = <1996875>;
56	regulator-ramp-delay = <25000>;
57	regulator-always-on;
58	};
59
60	LDO_CAMA0 {
61	regulator-name = "vddcama0";
62	regulator-min-microvolt = <1200000>;
63	regulator-max-microvolt = <3750000>;
64	regulator-enable-ramp-delay = <100>;
65	};
66	};
67	...	46	...

Documentation/devicetree/bindings/rtc/rtc-mt6397.txt+0−31

@@ -1,31 +0,0 @@
1	Device-Tree bindings for MediaTek PMIC based RTC
2
3	MediaTek PMIC based RTC is an independent function of MediaTek PMIC that works
4	as a type of multi-function device (MFD). The RTC can be configured and set up
5	with PMIC wrapper bus which is a common resource shared with the other
6	functions found on the same PMIC.
7
8	For MediaTek PMIC MFD bindings, see:
9	../mfd/mt6397.txt
10
11	For MediaTek PMIC wrapper bus bindings, see:
12	../soc/mediatek/pwrap.txt
13
14	Required properties:
15	- compatible: Should be one of follows
16	"mediatek,mt6323-rtc": for MT6323 PMIC
17	"mediatek,mt6358-rtc": for MT6358 PMIC
18	"mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC
19	"mediatek,mt6397-rtc": for MT6397 PMIC
20
21	Example:
22
23	pmic {
24	compatible = "mediatek,mt6323";
25
26	...
27
28	rtc {
29	compatible = "mediatek,mt6323-rtc";
30	};
31	};

Documentation/devicetree/bindings/rtc/sprd,sc2731-rtc.yaml+0−16

@@ -30,20 +30,4 @@ allOf: · 29 unmodified lines
30	- $ref: rtc.yaml#	30	- $ref: rtc.yaml#
31		31
32	unevaluatedProperties: false	32	unevaluatedProperties: false
33
34	examples:
35	- \|
36	#include <dt-bindings/interrupt-controller/irq.h>
37
38	pmic {
39	#address-cells = <1>;
40	#size-cells = <0>;
41
42	rtc@280 {
43	compatible = "sprd,sc2731-rtc";
44	reg = <0x280>;
45	interrupt-parent = <&sc2731_pmic>;
46	interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
47	};
48	};
49	...	33	...

MAINTAINERS+7−3

@@ -14458,10 +14458,12 @@ F: Documentation/devicetree/bindings/net/bluetooth/mediatek,mt7921s-bluetooth.ya · 14457 unmodified lines
14458	F: drivers/bluetooth/btmtkuart.c	14458	F: drivers/bluetooth/btmtkuart.c
14459		14459
14460	MEDIATEK BOARD LEVEL SHUTDOWN DRIVERS	14460	MEDIATEK BOARD LEVEL SHUTDOWN DRIVERS
		14461	M: Sen Chu <sen.chu@mediatek.com>
14461	M: Sean Wang <sean.wang@mediatek.com>	14462	M: Sean Wang <sean.wang@mediatek.com>
		14463	M: Macpaul Lin <macpaul.lin@mediatek.com>
14462	L: linux-pm@vger.kernel.org	14464	L: linux-pm@vger.kernel.org
14463	S: Maintained	14465	S: Maintained
14464	F: Documentation/devicetree/bindings/power/reset/mt6323-poweroff.txt	14466	F: Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
14465	F: drivers/power/reset/mt6323-poweroff.c	14467	F: drivers/power/reset/mt6323-poweroff.c
14466		14468
14467	MEDIATEK CIR DRIVER	14469	MEDIATEK CIR DRIVER
@@ -14624,9 +14626,11 @@ F: Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml · 156 unmodified lines
14624	F: drivers/mtd/nand/raw/mtk_*	14626	F: drivers/mtd/nand/raw/mtk_*
14625		14627
14626	MEDIATEK PMIC LED DRIVER	14628	MEDIATEK PMIC LED DRIVER
		14629	M: Sen Chu <sen.chu@mediatek.com>
14627	M: Sean Wang <sean.wang@mediatek.com>	14630	M: Sean Wang <sean.wang@mediatek.com>
		14631	M: Macpaul Lin <macpaul.lin@mediatek.com>
14628	S: Maintained	14632	S: Maintained
14629	F: Documentation/devicetree/bindings/leds/leds-mt6323.txt	14633	F: Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
14630	F: drivers/leds/leds-mt6323.c	14634	F: drivers/leds/leds-mt6323.c
14631		14635
14632	MEDIATEK RANDOM NUMBER GENERATOR SUPPORT	14636	MEDIATEK RANDOM NUMBER GENERATOR SUPPORT
@@ -20578,7 +20582,7 @@ L: linux-samsung-soc@vger.kernel.org · 5945 unmodified lines
20578	S: Maintained	20582	S: Maintained
20579	B: mailto:linux-samsung-soc@vger.kernel.org	20583	B: mailto:linux-samsung-soc@vger.kernel.org
20580	F: Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml	20584	F: Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml
20581	F: Documentation/devicetree/bindings/mfd/samsung,s2m*.yaml	20585	F: Documentation/devicetree/bindings/mfd/samsung,s2*.yaml
20582	F: Documentation/devicetree/bindings/mfd/samsung,s5m*.yaml	20586	F: Documentation/devicetree/bindings/mfd/samsung,s5m*.yaml
20583	F: Documentation/devicetree/bindings/regulator/samsung,s2m*.yaml	20587	F: Documentation/devicetree/bindings/regulator/samsung,s2m*.yaml
20584	F: Documentation/devicetree/bindings/regulator/samsung,s5m*.yaml	20588	F: Documentation/devicetree/bindings/regulator/samsung,s5m*.yaml

drivers/mfd/88pm886.c+1−0

@@ -37,6 +37,7 @@ static struct resource pm886_onkey_resources[] = { · 36 unmodified lines
37	static struct mfd_cell pm886_devs[] = {	37	static struct mfd_cell pm886_devs[] = {
38	MFD_CELL_RES("88pm886-onkey", pm886_onkey_resources),	38	MFD_CELL_RES("88pm886-onkey", pm886_onkey_resources),
39	MFD_CELL_NAME("88pm886-regulator"),	39	MFD_CELL_NAME("88pm886-regulator"),
		40	MFD_CELL_NAME("88pm886-rtc"),
40	};	41	};
41		42
42	static int pm886_power_off_handler(struct sys_off_data *sys_off_data)	43	static int pm886_power_off_handler(struct sys_off_data *sys_off_data)

drivers/mfd/Kconfig+1−1

@@ -25,7 +25,7 @@ config MFD_ADP5585 · 24 unmodified lines
25	select MFD_CORE	25	select MFD_CORE
26	select REGMAP_I2C	26	select REGMAP_I2C
27	depends on I2C	27	depends on I2C
28	depends on OF \|\| COMPILE_TEST	28	depends on OF
29	help	29	help
30	Say yes here to add support for the Analog Devices ADP5585 GPIO	30	Say yes here to add support for the Analog Devices ADP5585 GPIO
31	expander, PWM and keypad controller. This includes the I2C driver and	31	expander, PWM and keypad controller. This includes the I2C driver and

drivers/mfd/ab8500-sysctrl.c+1−1

@@ -159,7 +159,7 @@ static struct platform_driver ab8500_sysctrl_driver = { · 158 unmodified lines
159	.of_match_table = ab8500_sysctrl_match,	159	.of_match_table = ab8500_sysctrl_match,
160	},	160	},
161	.probe = ab8500_sysctrl_probe,	161	.probe = ab8500_sysctrl_probe,
162	.remove_new = ab8500_sysctrl_remove,	162	.remove = ab8500_sysctrl_remove,
163	};	163	};
164		164
165	static int __init ab8500_sysctrl_init(void)	165	static int __init ab8500_sysctrl_init(void)

drivers/mfd/atmel-flexcom.c+1−1

@@ -95,7 +95,7 @@ static int __maybe_unused atmel_flexcom_resume_noirq(struct device *dev) · 94 unmodified lines
95	if (err)	95	if (err)
96	return err;	96	return err;
97		97
98	val = FLEX_MR_OPMODE(ddata->opmode),	98	val = FLEX_MR_OPMODE(ddata->opmode);
99	writel(val, ddata->base + FLEX_MR);	99	writel(val, ddata->base + FLEX_MR);
100		100
101	clk_disable_unprepare(ddata->clk);	101	clk_disable_unprepare(ddata->clk);

drivers/mfd/atmel-smc.c+2−2

 /**
  * atmel_hsmc_cs_conf_apply - apply an SMC CS conf
  * @regmap: the HSMC regmap
- * @cs: the CS id
  * @layout: the layout of registers
+ * @cs: the CS id
  * @conf: the SMC CS conf to apply
  *
  * Applies an SMC CS configuration.
 /**
  * atmel_hsmc_cs_conf_get - retrieve the current SMC CS conf
  * @regmap: the HSMC regmap
- * @cs: the CS id
  * @layout: the layout of registers
+ * @cs: the CS id
  * @conf: the SMC CS conf object to store the current conf
  *
  * Retrieve the SMC CS configuration.

drivers/mfd/axp20x-i2c.c+1−0

@@ -65,6 +65,7 @@ static const struct of_device_id axp20x_i2c_of_match[] = { · 64 unmodified lines
65	{ .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },	65	{ .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },
66	{ .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },	66	{ .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
67	{ .compatible = "x-powers,axp313a", .data = (void *)AXP313A_ID },	67	{ .compatible = "x-powers,axp313a", .data = (void *)AXP313A_ID },
		68	{ .compatible = "x-powers,axp323", .data = (void *)AXP323_ID },
68	{ .compatible = "x-powers,axp717", .data = (void *)AXP717_ID },	69	{ .compatible = "x-powers,axp717", .data = (void *)AXP717_ID },
69	{ .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },	70	{ .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
70	{ .compatible = "x-powers,axp806", .data = (void *)AXP806_ID },	71	{ .compatible = "x-powers,axp806", .data = (void *)AXP806_ID },

drivers/mfd/axp20x.c+42−16

 #define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE	BIT(4)
 static const char * const axp20x_model_names[] = {
-	"AXP152",
+	[AXP152_ID] = "AXP152",
-	"AXP192",
+	[AXP192_ID] = "AXP192",
-	"AXP202",
+	[AXP202_ID] = "AXP202",
-	"AXP209",
+	[AXP209_ID] = "AXP209",
-	"AXP221",
+	[AXP221_ID] = "AXP221",
-	"AXP223",
+	[AXP223_ID] = "AXP223",
-	"AXP288",
+	[AXP288_ID] = "AXP288",
-	"AXP313a",
+	[AXP313A_ID] = "AXP313a",
-	"AXP717",
+	[AXP323_ID] = "AXP323",
-	"AXP803",
+	[AXP717_ID] = "AXP717",
-	"AXP806",
+	[AXP803_ID] = "AXP803",
-	"AXP809",
+	[AXP806_ID] = "AXP806",
-	"AXP813",
+	[AXP809_ID] = "AXP809",
-	"AXP15060",
+	[AXP813_ID] = "AXP813",
+	[AXP15060_ID] = "AXP15060",
 };
 static const struct regmap_range axp152_writeable_ranges[] = {
 	regmap_reg_range(AXP313A_ON_INDICATE, AXP313A_IRQ_STATE),
 };
+static const struct regmap_range axp323_writeable_ranges[] = {
+	regmap_reg_range(AXP313A_ON_INDICATE, AXP323_DCDC_MODE_CTRL2),
+};
 static const struct regmap_range axp313a_volatile_ranges[] = {
 	regmap_reg_range(AXP313A_SHUTDOWN_CTRL, AXP313A_SHUTDOWN_CTRL),
 	regmap_reg_range(AXP313A_IRQ_STATE, AXP313A_IRQ_STATE),
 	.n_yes_ranges = ARRAY_SIZE(axp313a_writeable_ranges),
 };
+static const struct regmap_access_table axp323_writeable_table = {
+	.yes_ranges = axp323_writeable_ranges,
+	.n_yes_ranges = ARRAY_SIZE(axp323_writeable_ranges),
+};
 static const struct regmap_access_table axp313a_volatile_table = {
 	.yes_ranges = axp313a_volatile_ranges,
 	.n_yes_ranges = ARRAY_SIZE(axp313a_volatile_ranges),
 	.cache_type = REGCACHE_MAPLE,
 };
+static const struct regmap_config axp323_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+	.wr_table = &axp323_writeable_table,
+	.volatile_table = &axp313a_volatile_table,
+	.max_register = AXP323_DCDC_MODE_CTRL2,
+	.cache_type = REGCACHE_MAPLE,
+};
 static const struct regmap_config axp717_regmap_config = {
 	.reg_bits = 8,
 	.val_bits = 8,
 	unsigned int shutdown_reg;
 	switch (axp20x->variant) {
+	case AXP323_ID:
 	case AXP313A_ID:
 		shutdown_reg = AXP313A_SHUTDOWN_CTRL;
 		break;
 		axp20x->regmap_cfg = &axp313a_regmap_config;
 		axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip;
 		break;
+	case AXP323_ID:
+		axp20x->nr_cells = ARRAY_SIZE(axp313a_cells);
+		axp20x->cells = axp313a_cells;
+		axp20x->regmap_cfg = &axp323_regmap_config;
+		axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip;
+		break;
 	case AXP717_ID:
 		axp20x->nr_cells = ARRAY_SIZE(axp717_cells);
 		axp20x->cells = axp717_cells;
 		axp20x->regmap_irq_chip = &axp15060_regmap_irq_chip;
 		break;
 	default:
-		dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
+		dev_err(dev, "unsupported AXP20X ID %u\n", axp20x->variant);
 		return -EINVAL;
 	}
 		}
 	}
-	ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
+	ret = mfd_add_devices(axp20x->dev, PLATFORM_DEVID_AUTO, axp20x->cells,
 			      axp20x->nr_cells, NULL, 0, NULL);
 	if (ret) {

drivers/mfd/cgbc-core.c+12−3

 	ret = cgbc_get_version(cgbc);
 	if (ret)
-		return ret;
+		goto release_session;
+	ret = mfd_add_devices(cgbc->dev, -1, cgbc_devs, ARRAY_SIZE(cgbc_devs),
+			      NULL, 0, NULL);
+	if (ret)
+		goto release_session;
-	return mfd_add_devices(cgbc->dev, -1, cgbc_devs, ARRAY_SIZE(cgbc_devs), NULL, 0, NULL);
+	return 0;
+release_session:
+	cgbc_session_release(cgbc);
+	return ret;
 }
 static int cgbc_probe(struct platform_device *pdev)
 		.dev_groups	= cgbc_groups,
 	},
 	.probe		= cgbc_probe,
-	.remove_new	= cgbc_remove,
+	.remove		= cgbc_remove,
 };
 static const struct dmi_system_id cgbc_dmi_table[] __initconst = {

drivers/mfd/cros_ec_dev.c+23−4

 	{ .name = "cros-keyboard-leds", },
 };
+static const struct mfd_cell cros_ec_ucsi_cells[] = {
+	{ .name = "cros_ec_ucsi", },
+};
 static const struct cros_feature_to_cells cros_subdevices[] = {
 	{
 		.id		= EC_FEATURE_CEC,
 		.num_cells	= ARRAY_SIZE(cros_ec_rtc_cells),
 	},
 	{
-		.id		= EC_FEATURE_USB_PD,
+		.id		= EC_FEATURE_UCSI_PPM,
-		.mfd_cells	= cros_usbpd_charger_cells,
+		.mfd_cells	= cros_ec_ucsi_cells,
-		.num_cells	= ARRAY_SIZE(cros_usbpd_charger_cells),
+		.num_cells	= ARRAY_SIZE(cros_ec_ucsi_cells),
 	},
 	{
 		.id		= EC_FEATURE_HANG_DETECT,
 		}
 	}
+	/*
+	 * UCSI provides power supply information so we don't need to separately
+	 * load the cros_usbpd_charger driver.
+	 */
+	if (cros_ec_check_features(ec, EC_FEATURE_USB_PD) &&
+	    !cros_ec_check_features(ec, EC_FEATURE_UCSI_PPM)) {
+		retval = mfd_add_hotplug_devices(ec->dev,
+						 cros_usbpd_charger_cells,
+						 ARRAY_SIZE(cros_usbpd_charger_cells));
+		if (retval)
+			dev_warn(ec->dev, "failed to add usbpd-charger: %d\n",
+				 retval);
+	}
 	/*
 	 * Lightbar is a special case. Newer devices support autodetection,
 	 * but older ones do not.
 	},
 	.id_table = cros_ec_id,
 	.probe = ec_device_probe,
-	.remove_new = ec_device_remove,
+	.remove = ec_device_remove,
 };
 static int __init cros_ec_dev_init(void)

drivers/mfd/cs42l43.c+56−9

@@ -967,7 +967,6 @@ static void cs42l43_boot_work(struct work_struct *work) · 966 unmodified lines
967		967
968	err:	968	err:
969	pm_runtime_put_sync(cs42l43->dev);	969	pm_runtime_put_sync(cs42l43->dev);
970	cs42l43_dev_remove(cs42l43);
971	}	970	}
972		971
973	static int cs42l43_power_up(struct cs42l43 *cs42l43)	972	static int cs42l43_power_up(struct cs42l43 *cs42l43)
@@ -1101,6 +1100,8 @@ EXPORT_SYMBOL_NS_GPL(cs42l43_dev_probe, MFD_CS42L43); · 127 unmodified lines
1101		1100
1102	void cs42l43_dev_remove(struct cs42l43 *cs42l43)	1101	void cs42l43_dev_remove(struct cs42l43 *cs42l43)
1103	{	1102	{
		1103	cancel_work_sync(&cs42l43->boot_work);
		1104
1104	cs42l43_power_down(cs42l43);	1105	cs42l43_power_down(cs42l43);
1105	}	1106	}
1106	EXPORT_SYMBOL_NS_GPL(cs42l43_dev_remove, MFD_CS42L43);	1107	EXPORT_SYMBOL_NS_GPL(cs42l43_dev_remove, MFD_CS42L43);
@@ -1108,16 +1109,39 @@ EXPORT_SYMBOL_NS_GPL(cs42l43_dev_remove, MFD_CS42L43); · 1 unmodified line
1108	static int cs42l43_suspend(struct device *dev)	1109	static int cs42l43_suspend(struct device *dev)
1109	{	1110	{
1110	struct cs42l43 *cs42l43 = dev_get_drvdata(dev);	1111	struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
		1112	static const struct reg_sequence mask_all[] = {
		1113	{ CS42L43_DECIM_MASK, 0xFFFFFFFF, },
		1114	{ CS42L43_EQ_MIX_MASK, 0xFFFFFFFF, },
		1115	{ CS42L43_ASP_MASK, 0xFFFFFFFF, },
		1116	{ CS42L43_PLL_MASK, 0xFFFFFFFF, },
		1117	{ CS42L43_SOFT_MASK, 0xFFFFFFFF, },
		1118	{ CS42L43_SWIRE_MASK, 0xFFFFFFFF, },
		1119	{ CS42L43_MSM_MASK, 0xFFFFFFFF, },
		1120	{ CS42L43_ACC_DET_MASK, 0xFFFFFFFF, },
		1121	{ CS42L43_I2C_TGT_MASK, 0xFFFFFFFF, },
		1122	{ CS42L43_SPI_MSTR_MASK, 0xFFFFFFFF, },
		1123	{ CS42L43_SW_TO_SPI_BRIDGE_MASK, 0xFFFFFFFF, },
		1124	{ CS42L43_OTP_MASK, 0xFFFFFFFF, },
		1125	{ CS42L43_CLASS_D_AMP_MASK, 0xFFFFFFFF, },
		1126	{ CS42L43_GPIO_INT_MASK, 0xFFFFFFFF, },
		1127	{ CS42L43_ASRC_MASK, 0xFFFFFFFF, },
		1128	{ CS42L43_HPOUT_MASK, 0xFFFFFFFF, },
		1129	};
1111	int ret;	1130	int ret;
1112		1131
1113	/*	1132	ret = pm_runtime_resume_and_get(dev);
1114	* Don't care about being resumed here, but the driver does want	1133	if (ret) {
1115	* force_resume to always trigger an actual resume, so that register	1134	dev_err(cs42l43->dev, "Failed to resume for suspend: %d\n", ret);
1116	* state for the MCU/GPIOs is returned as soon as possible after system	1135	return ret;
1117	* resume. force_resume will resume if the reference count is resumed on	1136	}
1118	* suspend hence the get_noresume.	1137
1119	*/	1138	/* The IRQs will be re-enabled on resume by the cache sync */
1120	pm_runtime_get_noresume(dev);	1139	ret = regmap_multi_reg_write_bypassed(cs42l43->regmap,
		1140	mask_all, ARRAY_SIZE(mask_all));
		1141	if (ret) {
		1142	dev_err(cs42l43->dev, "Failed to mask IRQs: %d\n", ret);
		1143	return ret;
		1144	}
1121		1145
1122	ret = pm_runtime_force_suspend(dev);	1146	ret = pm_runtime_force_suspend(dev);
1123	if (ret) {	1147	if (ret) {
@@ -1132,6 +1156,26 @@ static int cs42l43_suspend(struct device *dev) · 8 unmodified lines
1132	if (ret)	1156	if (ret)
1133	return ret;	1157	return ret;
1134		1158
		1159	disable_irq(cs42l43->irq);
		1160
		1161	return 0;
		1162	}
		1163
		1164	static int cs42l43_suspend_noirq(struct device *dev)
		1165	{
		1166	struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
		1167
		1168	enable_irq(cs42l43->irq);
		1169
		1170	return 0;
		1171	}
		1172
		1173	static int cs42l43_resume_noirq(struct device *dev)
		1174	{
		1175	struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
		1176
		1177	disable_irq(cs42l43->irq);
		1178
1135	return 0;	1179	return 0;
1136	}	1180	}
1137		1181
@@ -1144,6 +1188,8 @@ static int cs42l43_resume(struct device *dev) · 6 unmodified lines
1144	if (ret)	1188	if (ret)
1145	return ret;	1189	return ret;
1146		1190
		1191	enable_irq(cs42l43->irq);
		1192
1147	ret = pm_runtime_force_resume(dev);	1193	ret = pm_runtime_force_resume(dev);
1148	if (ret) {	1194	if (ret) {
1149	dev_err(cs42l43->dev, "Failed to force resume: %d\n", ret);	1195	dev_err(cs42l43->dev, "Failed to force resume: %d\n", ret);
@@ -1211,6 +1257,7 @@ err: · 61 unmodified lines
1211		1257
1212	EXPORT_NS_GPL_DEV_PM_OPS(cs42l43_pm_ops, MFD_CS42L43) = {	1258	EXPORT_NS_GPL_DEV_PM_OPS(cs42l43_pm_ops, MFD_CS42L43) = {
1213	SYSTEM_SLEEP_PM_OPS(cs42l43_suspend, cs42l43_resume)	1259	SYSTEM_SLEEP_PM_OPS(cs42l43_suspend, cs42l43_resume)
		1260	NOIRQ_SYSTEM_SLEEP_PM_OPS(cs42l43_suspend_noirq, cs42l43_resume_noirq)
1214	RUNTIME_PM_OPS(cs42l43_runtime_suspend, cs42l43_runtime_resume, NULL)	1261	RUNTIME_PM_OPS(cs42l43_runtime_suspend, cs42l43_runtime_resume, NULL)
1215	};	1262	};
1216		1263

drivers/mfd/da9052-spi.c+1−1

@@ -37,7 +37,7 @@ static int da9052_spi_probe(struct spi_device *spi) · 36 unmodified lines
37	spi_set_drvdata(spi, da9052);	37	spi_set_drvdata(spi, da9052);
38		38
39	config = da9052_regmap_config;	39	config = da9052_regmap_config;
40	config.read_flag_mask = 1;	40	config.write_flag_mask = 1;
41	config.reg_bits = 7;	41	config.reg_bits = 7;
42	config.pad_bits = 1;	42	config.pad_bits = 1;
43	config.val_bits = 8;	43	config.val_bits = 8;

drivers/mfd/exynos-lpass.c+2−2

@@ -179,13 +179,13 @@ static const struct of_device_id exynos_lpass_of_match[] = { · 178 unmodified lines
179	MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);	179	MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);
180		180
181	static struct platform_driver exynos_lpass_driver = {	181	static struct platform_driver exynos_lpass_driver = {
182	.driver = {	182	.driver = {
183	.name = "exynos-lpass",	183	.name = "exynos-lpass",
184	.pm = &lpass_pm_ops,	184	.pm = &lpass_pm_ops,
185	.of_match_table = exynos_lpass_of_match,	185	.of_match_table = exynos_lpass_of_match,
186	},	186	},
187	.probe = exynos_lpass_probe,	187	.probe = exynos_lpass_probe,
188	.remove_new = exynos_lpass_remove,	188	.remove = exynos_lpass_remove,
189	};	189	};
190	module_platform_driver(exynos_lpass_driver);	190	module_platform_driver(exynos_lpass_driver);
191		191

drivers/mfd/fsl-imx25-tsadc.c+1−1

@@ -211,7 +211,7 @@ static struct platform_driver mx25_tsadc_driver = { · 210 unmodified lines
211	.of_match_table = mx25_tsadc_ids,	211	.of_match_table = mx25_tsadc_ids,
212	},	212	},
213	.probe = mx25_tsadc_probe,	213	.probe = mx25_tsadc_probe,
214	.remove_new = mx25_tsadc_remove,	214	.remove = mx25_tsadc_remove,
215	};	215	};
216	module_platform_driver(mx25_tsadc_driver);	216	module_platform_driver(mx25_tsadc_driver);
217		217

drivers/mfd/hi655x-pmic.c+4−4

@@ -159,12 +159,12 @@ static const struct of_device_id hi655x_pmic_match[] = { · 158 unmodified lines
159	MODULE_DEVICE_TABLE(of, hi655x_pmic_match);	159	MODULE_DEVICE_TABLE(of, hi655x_pmic_match);
160		160
161	static struct platform_driver hi655x_pmic_driver = {	161	static struct platform_driver hi655x_pmic_driver = {
162	.driver = {	162	.driver = {
163	.name = "hi655x-pmic",	163	.name = "hi655x-pmic",
164	.of_match_table = hi655x_pmic_match,	164	.of_match_table = hi655x_pmic_match,
165	},	165	},
166	.probe = hi655x_pmic_probe,	166	.probe = hi655x_pmic_probe,
167	.remove_new = hi655x_pmic_remove,	167	.remove = hi655x_pmic_remove,
168	};	168	};
169	module_platform_driver(hi655x_pmic_driver);	169	module_platform_driver(hi655x_pmic_driver);
170		170

drivers/mfd/intel-lpss-acpi.c+1−1

@@ -208,7 +208,7 @@ static void intel_lpss_acpi_remove(struct platform_device *pdev) · 207 unmodified lines
208		208
209	static struct platform_driver intel_lpss_acpi_driver = {	209	static struct platform_driver intel_lpss_acpi_driver = {
210	.probe = intel_lpss_acpi_probe,	210	.probe = intel_lpss_acpi_probe,
211	.remove_new = intel_lpss_acpi_remove,	211	.remove = intel_lpss_acpi_remove,
212	.driver = {	212	.driver = {
213	.name = "intel-lpss",	213	.name = "intel-lpss",
214	.acpi_match_table = intel_lpss_acpi_ids,	214	.acpi_match_table = intel_lpss_acpi_ids,

drivers/mfd/intel_soc_pmic_bxtwc.c+111−66

@@ -6,16 +6,27 @@ · 5 unmodified lines
6	*/	6	*/
7		7
8	#include <linux/acpi.h>	8	#include <linux/acpi.h>
		9	#include <linux/array_size.h>
9	#include <linux/bits.h>	10	#include <linux/bits.h>
10	#include <linux/delay.h>	11	#include <linux/delay.h>
		12	#include <linux/device.h>
11	#include <linux/err.h>	13	#include <linux/err.h>
		14	#include <linux/errno.h>
		15	#include <linux/gfp_types.h>
12	#include <linux/interrupt.h>	16	#include <linux/interrupt.h>
13	#include <linux/kernel.h>	17	#include <linux/ioport.h>
		18	#include <linux/kstrtox.h>
14	#include <linux/mfd/core.h>	19	#include <linux/mfd/core.h>
15	#include <linux/mfd/intel_soc_pmic.h>	20	#include <linux/mfd/intel_soc_pmic.h>
16	#include <linux/mfd/intel_soc_pmic_bxtwc.h>	21	#include <linux/mfd/intel_soc_pmic_bxtwc.h>
		22	#include <linux/mod_devicetable.h>
17	#include <linux/module.h>	23	#include <linux/module.h>
18	#include <linux/platform_data/x86/intel_scu_ipc.h>	24	#include <linux/platform_data/x86/intel_scu_ipc.h>
		25	#include <linux/platform_device.h>
		26	#include <linux/pm.h>
		27	#include <linux/regmap.h>
		28	#include <linux/sysfs.h>
		29	#include <linux/types.h>
19		30
20	/* PMIC device registers */	31	/* PMIC device registers */
21	#define REG_ADDR_MASK GENMASK(15, 8)	32	#define REG_ADDR_MASK GENMASK(15, 8)
@@ -148,6 +159,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip = { · 126 unmodified lines
148		159
149	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {	160	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {
150	.name = "bxtwc_irq_chip_pwrbtn",	161	.name = "bxtwc_irq_chip_pwrbtn",
		162	.domain_suffix = "PWRBTN",
151	.status_base = BXTWC_PWRBTNIRQ,	163	.status_base = BXTWC_PWRBTNIRQ,
152	.mask_base = BXTWC_MPWRBTNIRQ,	164	.mask_base = BXTWC_MPWRBTNIRQ,
153	.irqs = bxtwc_regmap_irqs_pwrbtn,	165	.irqs = bxtwc_regmap_irqs_pwrbtn,
@@ -157,6 +169,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = { · 3 unmodified lines
157		169
158	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {	170	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
159	.name = "bxtwc_irq_chip_tmu",	171	.name = "bxtwc_irq_chip_tmu",
		172	.domain_suffix = "TMU",
160	.status_base = BXTWC_TMUIRQ,	173	.status_base = BXTWC_TMUIRQ,
161	.mask_base = BXTWC_MTMUIRQ,	174	.mask_base = BXTWC_MTMUIRQ,
162	.irqs = bxtwc_regmap_irqs_tmu,	175	.irqs = bxtwc_regmap_irqs_tmu,
@@ -166,6 +179,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = { · 3 unmodified lines
166		179
167	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {	180	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
168	.name = "bxtwc_irq_chip_bcu",	181	.name = "bxtwc_irq_chip_bcu",
		182	.domain_suffix = "BCU",
169	.status_base = BXTWC_BCUIRQ,	183	.status_base = BXTWC_BCUIRQ,
170	.mask_base = BXTWC_MBCUIRQ,	184	.mask_base = BXTWC_MBCUIRQ,
171	.irqs = bxtwc_regmap_irqs_bcu,	185	.irqs = bxtwc_regmap_irqs_bcu,
@@ -175,6 +189,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = { · 3 unmodified lines
175		189
176	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {	190	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
177	.name = "bxtwc_irq_chip_adc",	191	.name = "bxtwc_irq_chip_adc",
		192	.domain_suffix = "ADC",
178	.status_base = BXTWC_ADCIRQ,	193	.status_base = BXTWC_ADCIRQ,
179	.mask_base = BXTWC_MADCIRQ,	194	.mask_base = BXTWC_MADCIRQ,
180	.irqs = bxtwc_regmap_irqs_adc,	195	.irqs = bxtwc_regmap_irqs_adc,
@@ -184,6 +199,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = { · 3 unmodified lines
184		199
185	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {	200	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
186	.name = "bxtwc_irq_chip_chgr",	201	.name = "bxtwc_irq_chip_chgr",
		202	.domain_suffix = "CHGR",
187	.status_base = BXTWC_CHGR0IRQ,	203	.status_base = BXTWC_CHGR0IRQ,
188	.mask_base = BXTWC_MCHGR0IRQ,	204	.mask_base = BXTWC_MCHGR0IRQ,
189	.irqs = bxtwc_regmap_irqs_chgr,	205	.irqs = bxtwc_regmap_irqs_chgr,
@@ -193,6 +209,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = { · 3 unmodified lines
193		209
194	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {	210	static const struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
195	.name = "bxtwc_irq_chip_crit",	211	.name = "bxtwc_irq_chip_crit",
		212	.domain_suffix = "CRIT",
196	.status_base = BXTWC_CRITIRQ,	213	.status_base = BXTWC_CRITIRQ,
197	.mask_base = BXTWC_MCRITIRQ,	214	.mask_base = BXTWC_MCRITIRQ,
198	.irqs = bxtwc_regmap_irqs_crit,	215	.irqs = bxtwc_regmap_irqs_crit,
@@ -230,44 +247,55 @@ static const struct resource tmu_resources[] = { · 31 unmodified lines
230	};	247	};
231		248
232	static struct mfd_cell bxt_wc_dev[] = {	249	static struct mfd_cell bxt_wc_dev[] = {
233	{
234	.name = "bxt_wcove_gpadc",
235	.num_resources = ARRAY_SIZE(adc_resources),
236	.resources = adc_resources,
237	},
238	{	250	{
239	.name = "bxt_wcove_thermal",	251	.name = "bxt_wcove_thermal",
240	.num_resources = ARRAY_SIZE(thermal_resources),	252	.num_resources = ARRAY_SIZE(thermal_resources),
241	.resources = thermal_resources,	253	.resources = thermal_resources,
242	},	254	},
243	{	255	{
244	.name = "bxt_wcove_usbc",	256	.name = "bxt_wcove_gpio",
245	.num_resources = ARRAY_SIZE(usbc_resources),	257	.num_resources = ARRAY_SIZE(gpio_resources),
246	.resources = usbc_resources,	258	.resources = gpio_resources,
247	},	259	},
248	{	260	{
249	.name = "bxt_wcove_ext_charger",	261	.name = "bxt_wcove_region",
250	.num_resources = ARRAY_SIZE(charger_resources),
251	.resources = charger_resources,
252	},	262	},
		263	};
		264
		265	static const struct mfd_cell bxt_wc_tmu_dev[] = {
		266	{
		267	.name = "bxt_wcove_tmu",
		268	.num_resources = ARRAY_SIZE(tmu_resources),
		269	.resources = tmu_resources,
		270	},
		271	};
		272
		273	static const struct mfd_cell bxt_wc_bcu_dev[] = {
253	{	274	{
254	.name = "bxt_wcove_bcu",	275	.name = "bxt_wcove_bcu",
255	.num_resources = ARRAY_SIZE(bcu_resources),	276	.num_resources = ARRAY_SIZE(bcu_resources),
256	.resources = bcu_resources,	277	.resources = bcu_resources,
257	},	278	},
		279	};
		280
		281	static const struct mfd_cell bxt_wc_adc_dev[] = {
258	{	282	{
259	.name = "bxt_wcove_tmu",	283	.name = "bxt_wcove_gpadc",
260	.num_resources = ARRAY_SIZE(tmu_resources),	284	.num_resources = ARRAY_SIZE(adc_resources),
261	.resources = tmu_resources,	285	.resources = adc_resources,
262	},	286	},
		287	};
263		288
		289	static struct mfd_cell bxt_wc_chgr_dev[] = {
264	{	290	{
265	.name = "bxt_wcove_gpio",	291	.name = "bxt_wcove_usbc",
266	.num_resources = ARRAY_SIZE(gpio_resources),	292	.num_resources = ARRAY_SIZE(usbc_resources),
267	.resources = gpio_resources,	293	.resources = usbc_resources,
268	},	294	},
269	{	295	{
270	.name = "bxt_wcove_region",	296	.name = "bxt_wcove_ext_charger",
		297	.num_resources = ARRAY_SIZE(charger_resources),
		298	.resources = charger_resources,
271	},	299	},
272	};	300	};
273		301
@@ -347,6 +375,7 @@ static ssize_t addr_store(struct device *dev, · 73 unmodified lines
347		375
348	return count;	376	return count;
349	}	377	}
		378	static DEVICE_ATTR_ADMIN_RW(addr);
350		379
351	static ssize_t val_show(struct device *dev,	380	static ssize_t val_show(struct device *dev,
352	struct device_attribute attr, char buf)	381	struct device_attribute attr, char buf)
@@ -383,23 +412,14 @@ static ssize_t val_store(struct device *dev, · 30 unmodified lines
383	}	412	}
384	return count;	413	return count;
385	}	414	}
386
387	static DEVICE_ATTR_ADMIN_RW(addr);
388	static DEVICE_ATTR_ADMIN_RW(val);	415	static DEVICE_ATTR_ADMIN_RW(val);
		416
389	static struct attribute *bxtwc_attrs[] = {	417	static struct attribute *bxtwc_attrs[] = {
390	&dev_attr_addr.attr,	418	&dev_attr_addr.attr,
391	&dev_attr_val.attr,	419	&dev_attr_val.attr,
392	NULL	420	NULL
393	};	421	};
394		422	ATTRIBUTE_GROUPS(bxtwc);
395	static const struct attribute_group bxtwc_group = {
396	.attrs = bxtwc_attrs,
397	};
398
399	static const struct attribute_group *bxtwc_groups[] = {
400	&bxtwc_group,
401	NULL
402	};
403		423
404	static const struct regmap_config bxtwc_regmap_config = {	424	static const struct regmap_config bxtwc_regmap_config = {
405	.reg_bits = 16,	425	.reg_bits = 16,
@@ -414,15 +434,39 @@ static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic, · 8 unmodified lines
414	const struct regmap_irq_chip *chip,	434	const struct regmap_irq_chip *chip,
415	struct regmap_irq_chip_data **data)	435	struct regmap_irq_chip_data **data)
416	{	436	{
417	int irq;	437	struct device *dev = pmic->dev;
		438	int irq, ret;
418		439
419	irq = regmap_irq_get_virq(pdata, pirq);	440	irq = regmap_irq_get_virq(pdata, pirq);
420	if (irq < 0)	441	if (irq < 0)
421	return dev_err_probe(pmic->dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",	442	return dev_err_probe(dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",
422	pirq, chip->name);	443	pirq, chip->name);
423		444
424	return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,	445	ret = devm_regmap_add_irq_chip(dev, pmic->regmap, irq, irq_flags, 0, chip, data);
425	0, chip, data);	446	if (ret)
		447	return dev_err_probe(dev, ret, "Failed to add %s IRQ chip\n", chip->name);
		448
		449	return 0;
		450	}
		451
		452	static int bxtwc_add_chained_devices(struct intel_soc_pmic *pmic,
		453	const struct mfd_cell *cells, int n_devs,
		454	struct regmap_irq_chip_data *pdata,
		455	int pirq, int irq_flags,
		456	const struct regmap_irq_chip *chip,
		457	struct regmap_irq_chip_data **data)
		458	{
		459	struct device *dev = pmic->dev;
		460	struct irq_domain *domain;
		461	int ret;
		462
		463	ret = bxtwc_add_chained_irq_chip(pmic, pdata, pirq, irq_flags, chip, data);
		464	if (ret)
		465	return ret;
		466
		467	domain = regmap_irq_get_domain(*data);
		468
		469	return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, cells, n_devs, NULL, 0, domain);
426	}	470	}
427		471
428	static int bxtwc_probe(struct platform_device *pdev)	472	static int bxtwc_probe(struct platform_device *pdev)
@@ -466,48 +510,49 @@ static int bxtwc_probe(struct platform_device *pdev) · 37 unmodified lines
466	if (ret)	510	if (ret)
467	return dev_err_probe(dev, ret, "Failed to add IRQ chip\n");	511	return dev_err_probe(dev, ret, "Failed to add IRQ chip\n");
468		512
		513	ret = bxtwc_add_chained_devices(pmic, bxt_wc_tmu_dev, ARRAY_SIZE(bxt_wc_tmu_dev),
		514	pmic->irq_chip_data,
		515	BXTWC_TMU_LVL1_IRQ,
		516	IRQF_ONESHOT,
		517	&bxtwc_regmap_irq_chip_tmu,
		518	&pmic->irq_chip_data_tmu);
		519	if (ret)
		520	return ret;
		521
469	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,	522	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
470	BXTWC_PWRBTN_LVL1_IRQ,	523	BXTWC_PWRBTN_LVL1_IRQ,
471	IRQF_ONESHOT,	524	IRQF_ONESHOT,
472	&bxtwc_regmap_irq_chip_pwrbtn,	525	&bxtwc_regmap_irq_chip_pwrbtn,
473	&pmic->irq_chip_data_pwrbtn);	526	&pmic->irq_chip_data_pwrbtn);
474	if (ret)	527	if (ret)
475	return dev_err_probe(dev, ret, "Failed to add PWRBTN IRQ chip\n");	528	return ret;
476
477	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
478	BXTWC_TMU_LVL1_IRQ,
479	IRQF_ONESHOT,
480	&bxtwc_regmap_irq_chip_tmu,
481	&pmic->irq_chip_data_tmu);
482	if (ret)
483	return dev_err_probe(dev, ret, "Failed to add TMU IRQ chip\n");
484		529
485	/* Add chained IRQ handler for BCU IRQs */	530	ret = bxtwc_add_chained_devices(pmic, bxt_wc_bcu_dev, ARRAY_SIZE(bxt_wc_bcu_dev),
486	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,	531	pmic->irq_chip_data,
487	BXTWC_BCU_LVL1_IRQ,	532	BXTWC_BCU_LVL1_IRQ,
488	IRQF_ONESHOT,	533	IRQF_ONESHOT,
489	&bxtwc_regmap_irq_chip_bcu,	534	&bxtwc_regmap_irq_chip_bcu,
490	&pmic->irq_chip_data_bcu);	535	&pmic->irq_chip_data_bcu);
491	if (ret)	536	if (ret)
492	return dev_err_probe(dev, ret, "Failed to add BUC IRQ chip\n");	537	return ret;
493		538
494	/* Add chained IRQ handler for ADC IRQs */	539	ret = bxtwc_add_chained_devices(pmic, bxt_wc_adc_dev, ARRAY_SIZE(bxt_wc_adc_dev),
495	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,	540	pmic->irq_chip_data,
496	BXTWC_ADC_LVL1_IRQ,	541	BXTWC_ADC_LVL1_IRQ,
497	IRQF_ONESHOT,	542	IRQF_ONESHOT,
498	&bxtwc_regmap_irq_chip_adc,	543	&bxtwc_regmap_irq_chip_adc,
499	&pmic->irq_chip_data_adc);	544	&pmic->irq_chip_data_adc);
500	if (ret)	545	if (ret)
501	return dev_err_probe(dev, ret, "Failed to add ADC IRQ chip\n");	546	return ret;
502		547
503	/* Add chained IRQ handler for CHGR IRQs */	548	ret = bxtwc_add_chained_devices(pmic, bxt_wc_chgr_dev, ARRAY_SIZE(bxt_wc_chgr_dev),
504	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,	549	pmic->irq_chip_data,
505	BXTWC_CHGR_LVL1_IRQ,	550	BXTWC_CHGR_LVL1_IRQ,
506	IRQF_ONESHOT,	551	IRQF_ONESHOT,
507	&bxtwc_regmap_irq_chip_chgr,	552	&bxtwc_regmap_irq_chip_chgr,
508	&pmic->irq_chip_data_chgr);	553	&pmic->irq_chip_data_chgr);
509	if (ret)	554	if (ret)
510	return dev_err_probe(dev, ret, "Failed to add CHGR IRQ chip\n");	555	return ret;
511		556
512	/* Add chained IRQ handler for CRIT IRQs */	557	/* Add chained IRQ handler for CRIT IRQs */
513	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,	558	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
@@ -516,7 +561,7 @@ static int bxtwc_probe(struct platform_device *pdev) · 2 unmodified lines
516	&bxtwc_regmap_irq_chip_crit,	561	&bxtwc_regmap_irq_chip_crit,
517	&pmic->irq_chip_data_crit);	562	&pmic->irq_chip_data_crit);
518	if (ret)	563	if (ret)
519	return dev_err_probe(dev, ret, "Failed to add CRIT IRQ chip\n");	564	return ret;
520		565
521	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, bxt_wc_dev, ARRAY_SIZE(bxt_wc_dev),	566	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, bxt_wc_dev, ARRAY_SIZE(bxt_wc_dev),
522	NULL, 0, NULL);	567	NULL, 0, NULL);
@@ -571,7 +616,7 @@ static struct platform_driver bxtwc_driver = { · 48 unmodified lines
571	.probe = bxtwc_probe,	616	.probe = bxtwc_probe,
572	.shutdown = bxtwc_shutdown,	617	.shutdown = bxtwc_shutdown,
573	.driver = {	618	.driver = {
574	.name = "BXTWC PMIC",	619	.name = "intel_soc_pmic_bxtwc",
575	.pm = pm_sleep_ptr(&bxtwc_pm_ops),	620	.pm = pm_sleep_ptr(&bxtwc_pm_ops),
576	.acpi_match_table = bxtwc_acpi_ids,	621	.acpi_match_table = bxtwc_acpi_ids,
577	.dev_groups = bxtwc_groups,	622	.dev_groups = bxtwc_groups,

drivers/mfd/intel_soc_pmic_chtwc.c+1−1

@@ -267,7 +267,7 @@ static const struct acpi_device_id cht_wc_acpi_ids[] = { · 266 unmodified lines
267		267
268	static struct i2c_driver cht_wc_driver = {	268	static struct i2c_driver cht_wc_driver = {
269	.driver = {	269	.driver = {
270	.name = "CHT Whiskey Cove PMIC",	270	.name = "intel_soc_pmic_chtwc",
271	.pm = pm_sleep_ptr(&cht_wc_pm_ops),	271	.pm = pm_sleep_ptr(&cht_wc_pm_ops),
272	.acpi_match_table = cht_wc_acpi_ids,	272	.acpi_match_table = cht_wc_acpi_ids,
273	},	273	},

drivers/mfd/intel_soc_pmic_crc.c+8−1

 };
 MODULE_DEVICE_TABLE(acpi, crystal_cove_acpi_match);
+static const struct i2c_device_id crystal_cove_i2c_match[] = {
+	{ "intel_soc_pmic_crc" },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, crystal_cove_i2c_match);
 static struct i2c_driver crystal_cove_i2c_driver = {
 	.driver = {
-		.name = "crystal_cove_i2c",
+		.name = "intel_soc_pmic_crc",
 		.pm = pm_sleep_ptr(&crystal_cove_pm_ops),
 		.acpi_match_table = crystal_cove_acpi_match,
 	},
+	.id_table = crystal_cove_i2c_match,
 	.probe = crystal_cove_i2c_probe,
 	.remove = crystal_cove_i2c_remove,
 	.shutdown = crystal_cove_shutdown,

drivers/mfd/ipaq-micro.c+1−0

@@ -130,6 +130,7 @@ static void micro_rx_msg(struct ipaq_micro micro, u8 id, int len, u8 data) · 129 unmodified lines
130	default:	130	default:
131	dev_err(micro->dev,	131	dev_err(micro->dev,
132	"unknown msg %d [%d] %*ph\n", id, len, len, data);	132	"unknown msg %d [%d] %*ph\n", id, len, len, data);
		133	break;
133	}	134	}
134	spin_unlock(&micro->lock);	135	spin_unlock(&micro->lock);
135	}	136	}

drivers/mfd/kempld-core.c+1−1

@@ -486,7 +486,7 @@ static struct platform_driver kempld_driver = { · 485 unmodified lines
486	.dev_groups = pld_groups,	486	.dev_groups = pld_groups,
487	},	487	},
488	.probe = kempld_probe,	488	.probe = kempld_probe,
489	.remove_new = kempld_remove,	489	.remove = kempld_remove,
490	};	490	};
491		491
492	static const struct dmi_system_id kempld_dmi_table[] __initconst = {	492	static const struct dmi_system_id kempld_dmi_table[] __initconst = {

drivers/mfd/mcp-sa11x0.c+1−1

@@ -286,7 +286,7 @@ static const struct dev_pm_ops mcp_sa11x0_pm_ops = { · 285 unmodified lines
286		286
287	static struct platform_driver mcp_sa11x0_driver = {	287	static struct platform_driver mcp_sa11x0_driver = {
288	.probe = mcp_sa11x0_probe,	288	.probe = mcp_sa11x0_probe,
289	.remove_new = mcp_sa11x0_remove,	289	.remove = mcp_sa11x0_remove,
290	.driver = {	290	.driver = {
291	.name = DRIVER_NAME,	291	.name = DRIVER_NAME,
292	.pm = pm_sleep_ptr(&mcp_sa11x0_pm_ops),	292	.pm = pm_sleep_ptr(&mcp_sa11x0_pm_ops),

drivers/mfd/mt6397-core.c+32−0

 #include <linux/regmap.h>
 #include <linux/mfd/core.h>
 #include <linux/mfd/mt6323/core.h>
+#include <linux/mfd/mt6328/core.h>
 #include <linux/mfd/mt6331/core.h>
 #include <linux/mfd/mt6357/core.h>
 #include <linux/mfd/mt6358/core.h>
 #include <linux/mfd/mt6359/core.h>
 #include <linux/mfd/mt6397/core.h>
 #include <linux/mfd/mt6323/registers.h>
+#include <linux/mfd/mt6328/registers.h>
 #include <linux/mfd/mt6331/registers.h>
 #include <linux/mfd/mt6357/registers.h>
 #include <linux/mfd/mt6358/registers.h>
 	DEFINE_RES_IRQ_NAMED(MT6323_IRQ_STATUS_FCHRKEY, "homekey"),
 };
+static const struct resource mt6328_keys_resources[] = {
+	DEFINE_RES_IRQ_NAMED(MT6328_IRQ_STATUS_PWRKEY, "powerkey"),
+	DEFINE_RES_IRQ_NAMED(MT6328_IRQ_STATUS_HOMEKEY, "homekey"),
+	DEFINE_RES_IRQ_NAMED(MT6328_IRQ_STATUS_PWRKEY_R, "powerkey_r"),
+	DEFINE_RES_IRQ_NAMED(MT6328_IRQ_STATUS_HOMEKEY_R, "homekey_r"),
+};
 static const struct resource mt6357_keys_resources[] = {
 	DEFINE_RES_IRQ_NAMED(MT6357_IRQ_PWRKEY, "powerkey"),
 	DEFINE_RES_IRQ_NAMED(MT6357_IRQ_HOMEKEY, "homekey"),
 	},
 };
+static const struct mfd_cell mt6328_devs[] = {
+	{
+		.name = "mt6328-regulator",
+		.of_compatible = "mediatek,mt6328-regulator"
+	}, {
+		.name = "mtk-pmic-keys",
+		.num_resources = ARRAY_SIZE(mt6328_keys_resources),
+		.resources = mt6328_keys_resources,
+		.of_compatible = "mediatek,mt6328-keys"
+	},
+};
 static const struct mfd_cell mt6357_devs[] = {
 	{
 		.name = "mt6359-auxadc",
 	.irq_init = mt6397_irq_init,
 };
+static const struct chip_data mt6328_core = {
+	.cid_addr = MT6328_HWCID,
+	.cid_shift = 0,
+	.cells = mt6328_devs,
+	.cell_size = ARRAY_SIZE(mt6328_devs),
+	.irq_init = mt6397_irq_init,
+};
 static const struct chip_data mt6357_core = {
 	.cid_addr = MT6357_SWCID,
 	.cid_shift = 8,
 	{
 		.compatible = "mediatek,mt6323",
 		.data = &mt6323_core,
+	}, {
+		.compatible = "mediatek,mt6328",
+		.data = &mt6328_core,
 	}, {
 		.compatible = "mediatek,mt6331",
 		.data = &mt6331_mt6332_core,

drivers/mfd/mt6397-irq.c+23−0

 #include <linux/suspend.h>
 #include <linux/mfd/mt6323/core.h>
 #include <linux/mfd/mt6323/registers.h>
+#include <linux/mfd/mt6328/core.h>
+#include <linux/mfd/mt6328/registers.h>
 #include <linux/mfd/mt6331/core.h>
 #include <linux/mfd/mt6331/registers.h>
 #include <linux/mfd/mt6397/core.h>
 		     mt6397->irq_masks_cur[0]);
 	regmap_write(mt6397->regmap, mt6397->int_con[1],
 		     mt6397->irq_masks_cur[1]);
+	if (mt6397->int_con[2])
+		regmap_write(mt6397->regmap, mt6397->int_con[2],
+			     mt6397->irq_masks_cur[2]);
 	mutex_unlock(&mt6397->irqlock);
 }
 	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
 	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
+	if (mt6397->int_status[2])
+		mt6397_irq_handle_reg(mt6397, mt6397->int_status[2], 32);
 	return IRQ_HANDLED;
 }
 			     chip->int_con[0], chip->wake_mask[0]);
 		regmap_write(chip->regmap,
 			     chip->int_con[1], chip->wake_mask[1]);
+		if (chip->int_con[2])
+			regmap_write(chip->regmap,
+				     chip->int_con[2], chip->wake_mask[2]);
 		enable_irq_wake(chip->irq);
 		break;
 			     chip->int_con[0], chip->irq_masks_cur[0]);
 		regmap_write(chip->regmap,
 			     chip->int_con[1], chip->irq_masks_cur[1]);
+		if (chip->int_con[2])
+			regmap_write(chip->regmap,
+				     chip->int_con[2], chip->irq_masks_cur[2]);
 		disable_irq_wake(chip->irq);
 		break;
 		chip->int_status[0] = MT6323_INT_STATUS0;
 		chip->int_status[1] = MT6323_INT_STATUS1;
 		break;
+	case MT6328_CHIP_ID:
+		chip->int_con[0] = MT6328_INT_CON0;
+		chip->int_con[1] = MT6328_INT_CON1;
+		chip->int_con[2] = MT6328_INT_CON2;
+		chip->int_status[0] = MT6328_INT_STATUS0;
+		chip->int_status[1] = MT6328_INT_STATUS1;
+		chip->int_status[2] = MT6328_INT_STATUS2;
+		break;
 	case MT6331_CHIP_ID:
 		chip->int_con[0] = MT6331_INT_CON0;
 		chip->int_con[1] = MT6331_INT_CON1;
 	/* Mask all interrupt sources */
 	regmap_write(chip->regmap, chip->int_con[0], 0x0);
 	regmap_write(chip->regmap, chip->int_con[1], 0x0);
+	if (chip->int_con[2])
+		regmap_write(chip->regmap, chip->int_con[2], 0x0);
 	chip->pm_nb.notifier_call = mt6397_irq_pm_notifier;
 	chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,

drivers/mfd/mxs-lradc.c+1−1

@@ -243,7 +243,7 @@ static struct platform_driver mxs_lradc_driver = { · 242 unmodified lines
243	.of_match_table = mxs_lradc_dt_ids,	243	.of_match_table = mxs_lradc_dt_ids,
244	},	244	},
245	.probe = mxs_lradc_probe,	245	.probe = mxs_lradc_probe,
246	.remove_new = mxs_lradc_remove,	246	.remove = mxs_lradc_remove,
247	};	247	};
248	module_platform_driver(mxs_lradc_driver);	248	module_platform_driver(mxs_lradc_driver);
249		249

drivers/mfd/omap-usb-host.c+1−1

@@ -843,7 +843,7 @@ static struct platform_driver usbhs_omap_driver = { · 842 unmodified lines
843	.of_match_table = usbhs_omap_dt_ids,	843	.of_match_table = usbhs_omap_dt_ids,
844	},	844	},
845	.probe = usbhs_omap_probe,	845	.probe = usbhs_omap_probe,
846	.remove_new = usbhs_omap_remove,	846	.remove = usbhs_omap_remove,
847	};	847	};
848		848
849	MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");	849	MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");

drivers/mfd/omap-usb-tll.c+1−1

@@ -301,7 +301,7 @@ static struct platform_driver usbtll_omap_driver = { · 300 unmodified lines
301	.of_match_table = usbtll_omap_dt_ids,	301	.of_match_table = usbtll_omap_dt_ids,
302	},	302	},
303	.probe = usbtll_omap_probe,	303	.probe = usbtll_omap_probe,
304	.remove_new = usbtll_omap_remove,	304	.remove = usbtll_omap_remove,
305	};	305	};
306		306
307	int omap_tll_init(struct usbhs_omap_platform_data *pdata)	307	int omap_tll_init(struct usbhs_omap_platform_data *pdata)

drivers/mfd/pcf50633-adc.c+1−1

@@ -243,7 +243,7 @@ static struct platform_driver pcf50633_adc_driver = { · 242 unmodified lines
243	.name = "pcf50633-adc",	243	.name = "pcf50633-adc",
244	},	244	},
245	.probe = pcf50633_adc_probe,	245	.probe = pcf50633_adc_probe,
246	.remove_new = pcf50633_adc_remove,	246	.remove = pcf50633_adc_remove,
247	};	247	};
248		248
249	module_platform_driver(pcf50633_adc_driver);	249	module_platform_driver(pcf50633_adc_driver);

drivers/mfd/qcom-pm8xxx.c+1−1

@@ -595,7 +595,7 @@ static void pm8xxx_remove(struct platform_device *pdev) · 594 unmodified lines
595		595
596	static struct platform_driver pm8xxx_driver = {	596	static struct platform_driver pm8xxx_driver = {
597	.probe = pm8xxx_probe,	597	.probe = pm8xxx_probe,
598	.remove_new = pm8xxx_remove,	598	.remove = pm8xxx_remove,
599	.driver = {	599	.driver = {
600	.name = "pm8xxx-core",	600	.name = "pm8xxx-core",
601	.of_match_table = pm8xxx_id_table,	601	.of_match_table = pm8xxx_id_table,

drivers/mfd/rk8xx-core.c+3−3

@@ -618,7 +618,7 @@ static int rk808_power_off(struct sys_off_data *data) · 617 unmodified lines
618	bit = DEV_OFF;	618	bit = DEV_OFF;
619	break;	619	break;
620	case RK808_ID:	620	case RK808_ID:
621	reg = RK808_DEVCTRL_REG,	621	reg = RK808_DEVCTRL_REG;
622	bit = DEV_OFF_RST;	622	bit = DEV_OFF_RST;
623	break;	623	break;
624	case RK809_ID:	624	case RK809_ID:
@@ -785,8 +785,8 @@ int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap · 160 unmodified lines
785	if (ret)	785	if (ret)
786	return dev_err_probe(dev, ret, "failed to add MFD devices\n");	786	return dev_err_probe(dev, ret, "failed to add MFD devices\n");
787		787
788	if (device_property_read_bool(dev, "rockchip,system-power-controller") \|\|	788	if (device_property_read_bool(dev, "system-power-controller") \|\|
789	device_property_read_bool(dev, "system-power-controller")) {	789	device_property_read_bool(dev, "rockchip,system-power-controller")) {
790	ret = devm_register_sys_off_handler(dev,	790	ret = devm_register_sys_off_handler(dev,
791	SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,	791	SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
792	&rk808_power_off, rk808);	792	&rk808_power_off, rk808);

drivers/mfd/rohm-bd71828.c+6−6

@@ -32,15 +32,15 @@ static struct gpio_keys_platform_data bd71828_powerkey_data = { · 31 unmodified lines
32	};	32	};
33		33
34	static const struct resource bd71815_rtc_irqs[] = {	34	static const struct resource bd71815_rtc_irqs[] = {
35	DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd71815-rtc-alm-0"),	35	DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd70528-rtc-alm-0"),
36	DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd71815-rtc-alm-1"),	36	DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd70528-rtc-alm-1"),
37	DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd71815-rtc-alm-2"),	37	DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd70528-rtc-alm-2"),
38	};	38	};
39		39
40	static const struct resource bd71828_rtc_irqs[] = {	40	static const struct resource bd71828_rtc_irqs[] = {
41	DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd71828-rtc-alm-0"),	41	DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd70528-rtc-alm-0"),
42	DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd71828-rtc-alm-1"),	42	DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd70528-rtc-alm-1"),
43	DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd71828-rtc-alm-2"),	43	DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"),
44	};	44	};
45		45
46	static struct resource bd71815_power_irqs[] = {	46	static struct resource bd71815_power_irqs[] = {

drivers/mfd/rohm-bd96801.c+242−35

@@ -5,13 +5,9 @@ · 4 unmodified lines
5	* ROHM BD96801 PMIC driver	5	* ROHM BD96801 PMIC driver
6	*	6	*
7	* This version of the "BD86801 scalable PMIC"'s driver supports only very	7	* This version of the "BD86801 scalable PMIC"'s driver supports only very
8	* basic set of the PMIC features. Most notably, there is no support for	8	* basic set of the PMIC features.
9	* the ERRB interrupt and the configurations which should be done when the	9	* Most notably, there is no support for the configurations which should
10	* PMIC is in STBY mode.	10	* be done when the PMIC is in STBY mode.
11	*
12	* Supporting the ERRB interrupt would require dropping the regmap-IRQ
13	* usage or working around (or accepting a presense of) a naming conflict
14	* in debugFS IRQs.
15	*	11	*
16	* Being able to reliably do the configurations like changing the	12	* Being able to reliably do the configurations like changing the
17	* regulator safety limits (like limits for the over/under -voltages, over	13	* regulator safety limits (like limits for the over/under -voltages, over
@@ -23,16 +19,14 @@ · 5 unmodified lines
23	* be the need to configure these safety limits. Hence it's not simple to	19	* be the need to configure these safety limits. Hence it's not simple to
24	* come up with a generic solution.	20	* come up with a generic solution.
25	*	21	*
26	* Users who require the ERRB handling and STBY state configurations can	22	* Users who require the STBY state configurations can have a look at the
27	* have a look at the original RFC:	23	* original RFC:
28	* https://lore.kernel.org/all/cover.1712920132.git.mazziesaccount@gmail.com/	24	* https://lore.kernel.org/all/cover.1712920132.git.mazziesaccount@gmail.com/
29	* which implements a workaround to debugFS naming conflict and some of	25	* which implements some of the safety limit configurations - but leaves the
30	* the safety limit configurations - but leaves the state change handling	26	* state change handling and synchronization to be implemented.
31	* and synchronization to be implemented.
32	*	27	*
33	* It would be great to hear (and receive a patch!) if you implement the	28	* It would be great to hear (and receive a patch!) if you implement the
34	* STBY configuration support or a proper fix to the debugFS naming	29	* STBY configuration support or a proper fix in your downstream driver ;)
35	* conflict in your downstream driver ;)
36	*/	30	*/
37		31
38	#include <linux/i2c.h>	32	#include <linux/i2c.h>
@@ -46,6 +40,64 @@ · 7 unmodified lines
46	#include <linux/mfd/rohm-bd96801.h>	40	#include <linux/mfd/rohm-bd96801.h>
47	#include <linux/mfd/rohm-generic.h>	41	#include <linux/mfd/rohm-generic.h>
48		42
		43	static const struct resource regulator_errb_irqs[] = {
		44	DEFINE_RES_IRQ_NAMED(BD96801_OTP_ERR_STAT, "bd96801-otp-err"),
		45	DEFINE_RES_IRQ_NAMED(BD96801_DBIST_ERR_STAT, "bd96801-dbist-err"),
		46	DEFINE_RES_IRQ_NAMED(BD96801_EEP_ERR_STAT, "bd96801-eep-err"),
		47	DEFINE_RES_IRQ_NAMED(BD96801_ABIST_ERR_STAT, "bd96801-abist-err"),
		48	DEFINE_RES_IRQ_NAMED(BD96801_PRSTB_ERR_STAT, "bd96801-prstb-err"),
		49	DEFINE_RES_IRQ_NAMED(BD96801_DRMOS1_ERR_STAT, "bd96801-drmoserr1"),
		50	DEFINE_RES_IRQ_NAMED(BD96801_DRMOS2_ERR_STAT, "bd96801-drmoserr2"),
		51	DEFINE_RES_IRQ_NAMED(BD96801_SLAVE_ERR_STAT, "bd96801-slave-err"),
		52	DEFINE_RES_IRQ_NAMED(BD96801_VREF_ERR_STAT, "bd96801-vref-err"),
		53	DEFINE_RES_IRQ_NAMED(BD96801_TSD_ERR_STAT, "bd96801-tsd"),
		54	DEFINE_RES_IRQ_NAMED(BD96801_UVLO_ERR_STAT, "bd96801-uvlo-err"),
		55	DEFINE_RES_IRQ_NAMED(BD96801_OVLO_ERR_STAT, "bd96801-ovlo-err"),
		56	DEFINE_RES_IRQ_NAMED(BD96801_OSC_ERR_STAT, "bd96801-osc-err"),
		57	DEFINE_RES_IRQ_NAMED(BD96801_PON_ERR_STAT, "bd96801-pon-err"),
		58	DEFINE_RES_IRQ_NAMED(BD96801_POFF_ERR_STAT, "bd96801-poff-err"),
		59	DEFINE_RES_IRQ_NAMED(BD96801_CMD_SHDN_ERR_STAT, "bd96801-cmd-shdn-err"),
		60
		61	DEFINE_RES_IRQ_NAMED(BD96801_INT_PRSTB_WDT_ERR, "bd96801-prstb-wdt-err"),
		62	DEFINE_RES_IRQ_NAMED(BD96801_INT_CHIP_IF_ERR, "bd96801-chip-if-err"),
		63	DEFINE_RES_IRQ_NAMED(BD96801_INT_SHDN_ERR_STAT, "bd96801-int-shdn-err"),
		64
		65	DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_PVIN_ERR_STAT, "bd96801-buck1-pvin-err"),
		66	DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVP_ERR_STAT, "bd96801-buck1-ovp-err"),
		67	DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVP_ERR_STAT, "bd96801-buck1-uvp-err"),
		68	DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_SHDN_ERR_STAT, "bd96801-buck1-shdn-err"),
		69
		70	DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_PVIN_ERR_STAT, "bd96801-buck2-pvin-err"),
		71	DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVP_ERR_STAT, "bd96801-buck2-ovp-err"),
		72	DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVP_ERR_STAT, "bd96801-buck2-uvp-err"),
		73	DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_SHDN_ERR_STAT, "bd96801-buck2-shdn-err"),
		74
		75	DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_PVIN_ERR_STAT, "bd96801-buck3-pvin-err"),
		76	DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVP_ERR_STAT, "bd96801-buck3-ovp-err"),
		77	DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVP_ERR_STAT, "bd96801-buck3-uvp-err"),
		78	DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_SHDN_ERR_STAT, "bd96801-buck3-shdn-err"),
		79
		80	DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_PVIN_ERR_STAT, "bd96801-buck4-pvin-err"),
		81	DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVP_ERR_STAT, "bd96801-buck4-ovp-err"),
		82	DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVP_ERR_STAT, "bd96801-buck4-uvp-err"),
		83	DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_SHDN_ERR_STAT, "bd96801-buck4-shdn-err"),
		84
		85	DEFINE_RES_IRQ_NAMED(BD96801_LDO5_PVIN_ERR_STAT, "bd96801-ldo5-pvin-err"),
		86	DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVP_ERR_STAT, "bd96801-ldo5-ovp-err"),
		87	DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVP_ERR_STAT, "bd96801-ldo5-uvp-err"),
		88	DEFINE_RES_IRQ_NAMED(BD96801_LDO5_SHDN_ERR_STAT, "bd96801-ldo5-shdn-err"),
		89
		90	DEFINE_RES_IRQ_NAMED(BD96801_LDO6_PVIN_ERR_STAT, "bd96801-ldo6-pvin-err"),
		91	DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVP_ERR_STAT, "bd96801-ldo6-ovp-err"),
		92	DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVP_ERR_STAT, "bd96801-ldo6-uvp-err"),
		93	DEFINE_RES_IRQ_NAMED(BD96801_LDO6_SHDN_ERR_STAT, "bd96801-ldo6-shdn-err"),
		94
		95	DEFINE_RES_IRQ_NAMED(BD96801_LDO7_PVIN_ERR_STAT, "bd96801-ldo7-pvin-err"),
		96	DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVP_ERR_STAT, "bd96801-ldo7-ovp-err"),
		97	DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVP_ERR_STAT, "bd96801-ldo7-uvp-err"),
		98	DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "bd96801-ldo7-shdn-err"),
		99	};
		100
49	static const struct resource regulator_intb_irqs[] = {	101	static const struct resource regulator_intb_irqs[] = {
50	DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "bd96801-core-thermal"),	102	DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "bd96801-core-thermal"),
51		103
@@ -90,20 +142,14 @@ static const struct resource regulator_intb_irqs[] = { · 38 unmodified lines
90	DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "bd96801-ldo7-undervolt"),	142	DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "bd96801-ldo7-undervolt"),
91	};	143	};
92		144
93	static const struct resource wdg_intb_irqs[] = {	145	enum {
94	DEFINE_RES_IRQ_NAMED(BD96801_WDT_ERR_STAT, "bd96801-wdg"),	146	WDG_CELL = 0,
		147	REGULATOR_CELL,
95	};	148	};
96		149
97	static struct mfd_cell bd96801_cells[] = {	150	static struct mfd_cell bd96801_cells[] = {
98	{	151	[WDG_CELL] = { .name = "bd96801-wdt", },
99	.name = "bd96801-wdt",	152	[REGULATOR_CELL] = { .name = "bd96801-regulator", },
100	.resources = wdg_intb_irqs,
101	.num_resources = ARRAY_SIZE(wdg_intb_irqs),
102	}, {
103	.name = "bd96801-regulator",
104	.resources = regulator_intb_irqs,
105	.num_resources = ARRAY_SIZE(regulator_intb_irqs),
106	},
107	};	153	};
108		154
109	static const struct regmap_range bd96801_volatile_ranges[] = {	155	static const struct regmap_range bd96801_volatile_ranges[] = {
@@ -128,6 +174,91 @@ static const struct regmap_access_table volatile_regs = { · 18 unmodified lines
128	.n_yes_ranges = ARRAY_SIZE(bd96801_volatile_ranges),	174	.n_yes_ranges = ARRAY_SIZE(bd96801_volatile_ranges),
129	};	175	};
130		176
		177	/*
		178	* For ERRB we need main register bit mapping as bit(0) indicates active IRQ
		179	* in one of the first 3 sub IRQ registers, For INTB we can use default 1 to 1
		180	* mapping.
		181	*/
		182	static unsigned int bit0_offsets[] = {0, 1, 2}; /* System stat, 3 registers */
		183	static unsigned int bit1_offsets[] = {3}; /* Buck 1 stat */
		184	static unsigned int bit2_offsets[] = {4}; /* Buck 2 stat */
		185	static unsigned int bit3_offsets[] = {5}; /* Buck 3 stat */
		186	static unsigned int bit4_offsets[] = {6}; /* Buck 4 stat */
		187	static unsigned int bit5_offsets[] = {7}; /* LDO 5 stat */
		188	static unsigned int bit6_offsets[] = {8}; /* LDO 6 stat */
		189	static unsigned int bit7_offsets[] = {9}; /* LDO 7 stat */
		190
		191	static const struct regmap_irq_sub_irq_map errb_sub_irq_offsets[] = {
		192	REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
		193	REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
		194	REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
		195	REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
		196	REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
		197	REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
		198	REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
		199	REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
		200	};
		201
		202	static const struct regmap_irq bd96801_errb_irqs[] = {
		203	/* Reg 0x52 Fatal ERRB1 */
		204	REGMAP_IRQ_REG(BD96801_OTP_ERR_STAT, 0, BD96801_OTP_ERR_MASK),
		205	REGMAP_IRQ_REG(BD96801_DBIST_ERR_STAT, 0, BD96801_DBIST_ERR_MASK),
		206	REGMAP_IRQ_REG(BD96801_EEP_ERR_STAT, 0, BD96801_EEP_ERR_MASK),
		207	REGMAP_IRQ_REG(BD96801_ABIST_ERR_STAT, 0, BD96801_ABIST_ERR_MASK),
		208	REGMAP_IRQ_REG(BD96801_PRSTB_ERR_STAT, 0, BD96801_PRSTB_ERR_MASK),
		209	REGMAP_IRQ_REG(BD96801_DRMOS1_ERR_STAT, 0, BD96801_DRMOS1_ERR_MASK),
		210	REGMAP_IRQ_REG(BD96801_DRMOS2_ERR_STAT, 0, BD96801_DRMOS2_ERR_MASK),
		211	REGMAP_IRQ_REG(BD96801_SLAVE_ERR_STAT, 0, BD96801_SLAVE_ERR_MASK),
		212	/* 0x53 Fatal ERRB2 */
		213	REGMAP_IRQ_REG(BD96801_VREF_ERR_STAT, 1, BD96801_VREF_ERR_MASK),
		214	REGMAP_IRQ_REG(BD96801_TSD_ERR_STAT, 1, BD96801_TSD_ERR_MASK),
		215	REGMAP_IRQ_REG(BD96801_UVLO_ERR_STAT, 1, BD96801_UVLO_ERR_MASK),
		216	REGMAP_IRQ_REG(BD96801_OVLO_ERR_STAT, 1, BD96801_OVLO_ERR_MASK),
		217	REGMAP_IRQ_REG(BD96801_OSC_ERR_STAT, 1, BD96801_OSC_ERR_MASK),
		218	REGMAP_IRQ_REG(BD96801_PON_ERR_STAT, 1, BD96801_PON_ERR_MASK),
		219	REGMAP_IRQ_REG(BD96801_POFF_ERR_STAT, 1, BD96801_POFF_ERR_MASK),
		220	REGMAP_IRQ_REG(BD96801_CMD_SHDN_ERR_STAT, 1, BD96801_CMD_SHDN_ERR_MASK),
		221	/* 0x54 Fatal INTB shadowed to ERRB */
		222	REGMAP_IRQ_REG(BD96801_INT_PRSTB_WDT_ERR, 2, BD96801_INT_PRSTB_WDT_ERR_MASK),
		223	REGMAP_IRQ_REG(BD96801_INT_CHIP_IF_ERR, 2, BD96801_INT_CHIP_IF_ERR_MASK),
		224	REGMAP_IRQ_REG(BD96801_INT_SHDN_ERR_STAT, 2, BD96801_INT_SHDN_ERR_MASK),
		225	/* Reg 0x55 BUCK1 ERR IRQs */
		226	REGMAP_IRQ_REG(BD96801_BUCK1_PVIN_ERR_STAT, 3, BD96801_OUT_PVIN_ERR_MASK),
		227	REGMAP_IRQ_REG(BD96801_BUCK1_OVP_ERR_STAT, 3, BD96801_OUT_OVP_ERR_MASK),
		228	REGMAP_IRQ_REG(BD96801_BUCK1_UVP_ERR_STAT, 3, BD96801_OUT_UVP_ERR_MASK),
		229	REGMAP_IRQ_REG(BD96801_BUCK1_SHDN_ERR_STAT, 3, BD96801_OUT_SHDN_ERR_MASK),
		230	/* Reg 0x56 BUCK2 ERR IRQs */
		231	REGMAP_IRQ_REG(BD96801_BUCK2_PVIN_ERR_STAT, 4, BD96801_OUT_PVIN_ERR_MASK),
		232	REGMAP_IRQ_REG(BD96801_BUCK2_OVP_ERR_STAT, 4, BD96801_OUT_OVP_ERR_MASK),
		233	REGMAP_IRQ_REG(BD96801_BUCK2_UVP_ERR_STAT, 4, BD96801_OUT_UVP_ERR_MASK),
		234	REGMAP_IRQ_REG(BD96801_BUCK2_SHDN_ERR_STAT, 4, BD96801_OUT_SHDN_ERR_MASK),
		235	/* Reg 0x57 BUCK3 ERR IRQs */
		236	REGMAP_IRQ_REG(BD96801_BUCK3_PVIN_ERR_STAT, 5, BD96801_OUT_PVIN_ERR_MASK),
		237	REGMAP_IRQ_REG(BD96801_BUCK3_OVP_ERR_STAT, 5, BD96801_OUT_OVP_ERR_MASK),
		238	REGMAP_IRQ_REG(BD96801_BUCK3_UVP_ERR_STAT, 5, BD96801_OUT_UVP_ERR_MASK),
		239	REGMAP_IRQ_REG(BD96801_BUCK3_SHDN_ERR_STAT, 5, BD96801_OUT_SHDN_ERR_MASK),
		240	/* Reg 0x58 BUCK4 ERR IRQs */
		241	REGMAP_IRQ_REG(BD96801_BUCK4_PVIN_ERR_STAT, 6, BD96801_OUT_PVIN_ERR_MASK),
		242	REGMAP_IRQ_REG(BD96801_BUCK4_OVP_ERR_STAT, 6, BD96801_OUT_OVP_ERR_MASK),
		243	REGMAP_IRQ_REG(BD96801_BUCK4_UVP_ERR_STAT, 6, BD96801_OUT_UVP_ERR_MASK),
		244	REGMAP_IRQ_REG(BD96801_BUCK4_SHDN_ERR_STAT, 6, BD96801_OUT_SHDN_ERR_MASK),
		245	/* Reg 0x59 LDO5 ERR IRQs */
		246	REGMAP_IRQ_REG(BD96801_LDO5_PVIN_ERR_STAT, 7, BD96801_OUT_PVIN_ERR_MASK),
		247	REGMAP_IRQ_REG(BD96801_LDO5_OVP_ERR_STAT, 7, BD96801_OUT_OVP_ERR_MASK),
		248	REGMAP_IRQ_REG(BD96801_LDO5_UVP_ERR_STAT, 7, BD96801_OUT_UVP_ERR_MASK),
		249	REGMAP_IRQ_REG(BD96801_LDO5_SHDN_ERR_STAT, 7, BD96801_OUT_SHDN_ERR_MASK),
		250	/* Reg 0x5a LDO6 ERR IRQs */
		251	REGMAP_IRQ_REG(BD96801_LDO6_PVIN_ERR_STAT, 8, BD96801_OUT_PVIN_ERR_MASK),
		252	REGMAP_IRQ_REG(BD96801_LDO6_OVP_ERR_STAT, 8, BD96801_OUT_OVP_ERR_MASK),
		253	REGMAP_IRQ_REG(BD96801_LDO6_UVP_ERR_STAT, 8, BD96801_OUT_UVP_ERR_MASK),
		254	REGMAP_IRQ_REG(BD96801_LDO6_SHDN_ERR_STAT, 8, BD96801_OUT_SHDN_ERR_MASK),
		255	/* Reg 0x5b LDO7 ERR IRQs */
		256	REGMAP_IRQ_REG(BD96801_LDO7_PVIN_ERR_STAT, 9, BD96801_OUT_PVIN_ERR_MASK),
		257	REGMAP_IRQ_REG(BD96801_LDO7_OVP_ERR_STAT, 9, BD96801_OUT_OVP_ERR_MASK),
		258	REGMAP_IRQ_REG(BD96801_LDO7_UVP_ERR_STAT, 9, BD96801_OUT_UVP_ERR_MASK),
		259	REGMAP_IRQ_REG(BD96801_LDO7_SHDN_ERR_STAT, 9, BD96801_OUT_SHDN_ERR_MASK),
		260	};
		261
131	static const struct regmap_irq bd96801_intb_irqs[] = {	262	static const struct regmap_irq bd96801_intb_irqs[] = {
132	/* STATUS SYSTEM INTB */	263	/* STATUS SYSTEM INTB */
133	REGMAP_IRQ_REG(BD96801_TW_STAT, 0, BD96801_TW_STAT_MASK),	264	REGMAP_IRQ_REG(BD96801_TW_STAT, 0, BD96801_TW_STAT_MASK),
@@ -176,8 +307,25 @@ static const struct regmap_irq bd96801_intb_irqs[] = { · 42 unmodified lines
176	REGMAP_IRQ_REG(BD96801_LDO7_UVD_STAT, 7, BD96801_LDO_UVD_STAT_MASK),	307	REGMAP_IRQ_REG(BD96801_LDO7_UVD_STAT, 7, BD96801_LDO_UVD_STAT_MASK),
177	};	308	};
178		309
179	static struct regmap_irq_chip bd96801_irq_chip_intb = {	310	static const struct regmap_irq_chip bd96801_irq_chip_errb = {
		311	.name = "bd96801-irq-errb",
		312	.domain_suffix = "errb",
		313	.main_status = BD96801_REG_INT_MAIN,
		314	.num_main_regs = 1,
		315	.irqs = &bd96801_errb_irqs[0],
		316	.num_irqs = ARRAY_SIZE(bd96801_errb_irqs),
		317	.status_base = BD96801_REG_INT_SYS_ERRB1,
		318	.mask_base = BD96801_REG_MASK_SYS_ERRB,
		319	.ack_base = BD96801_REG_INT_SYS_ERRB1,
		320	.init_ack_masked = true,
		321	.num_regs = 10,
		322	.irq_reg_stride = 1,
		323	.sub_reg_offsets = &errb_sub_irq_offsets[0],
		324	};
		325
		326	static const struct regmap_irq_chip bd96801_irq_chip_intb = {
180	.name = "bd96801-irq-intb",	327	.name = "bd96801-irq-intb",
		328	.domain_suffix = "intb",
181	.main_status = BD96801_REG_INT_MAIN,	329	.main_status = BD96801_REG_INT_MAIN,
182	.num_main_regs = 1,	330	.num_main_regs = 1,
183	.irqs = &bd96801_intb_irqs[0],	331	.irqs = &bd96801_intb_irqs[0],
@@ -194,16 +342,20 @@ static const struct regmap_config bd96801_regmap_config = { · 10 unmodified lines
194	.reg_bits = 8,	342	.reg_bits = 8,
195	.val_bits = 8,	343	.val_bits = 8,
196	.volatile_table = &volatile_regs,	344	.volatile_table = &volatile_regs,
197	.cache_type = REGCACHE_RBTREE,	345	.cache_type = REGCACHE_MAPLE,
198	};	346	};
199		347
200	static int bd96801_i2c_probe(struct i2c_client *i2c)	348	static int bd96801_i2c_probe(struct i2c_client *i2c)
201	{	349	{
202	struct regmap_irq_chip_data *intb_irq_data;	350	struct regmap_irq_chip_data intb_irq_data, errb_irq_data;
		351	struct irq_domain intb_domain, errb_domain;
203	const struct fwnode_handle *fwnode;	352	const struct fwnode_handle *fwnode;
204	struct irq_domain *intb_domain;	353	struct resource *regulator_res;
		354	struct resource wdg_irq;
205	struct regmap *regmap;	355	struct regmap *regmap;
206	int ret, intb_irq;	356	int intb_irq, errb_irq, num_intb, num_errb = 0;
		357	int num_regu_irqs, wdg_irq_no;
		358	int i, ret;
207		359
208	fwnode = dev_fwnode(&i2c->dev);	360	fwnode = dev_fwnode(&i2c->dev);
209	if (!fwnode)	361	if (!fwnode)
@@ -213,6 +365,23 @@ static int bd96801_i2c_probe(struct i2c_client *i2c) · 3 unmodified lines
213	if (intb_irq < 0)	365	if (intb_irq < 0)
214	return dev_err_probe(&i2c->dev, intb_irq, "INTB IRQ not configured\n");	366	return dev_err_probe(&i2c->dev, intb_irq, "INTB IRQ not configured\n");
215		367
		368	num_intb = ARRAY_SIZE(regulator_intb_irqs);
		369
		370	/* ERRB may be omitted if processor is powered by the PMIC */
		371	errb_irq = fwnode_irq_get_byname(fwnode, "errb");
		372	if (errb_irq < 0)
		373	errb_irq = 0;
		374
		375	if (errb_irq)
		376	num_errb = ARRAY_SIZE(regulator_errb_irqs);
		377
		378	num_regu_irqs = num_intb + num_errb;
		379
		380	regulator_res = devm_kcalloc(&i2c->dev, num_regu_irqs,
		381	sizeof(*regulator_res), GFP_KERNEL);
		382	if (!regulator_res)
		383	return -ENOMEM;
		384
216	regmap = devm_regmap_init_i2c(i2c, &bd96801_regmap_config);	385	regmap = devm_regmap_init_i2c(i2c, &bd96801_regmap_config);
217	if (IS_ERR(regmap))	386	if (IS_ERR(regmap))
218	return dev_err_probe(&i2c->dev, PTR_ERR(regmap),	387	return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
@@ -230,12 +399,50 @@ static int bd96801_i2c_probe(struct i2c_client *i2c) · 11 unmodified lines
230		399
231	intb_domain = regmap_irq_get_domain(intb_irq_data);	400	intb_domain = regmap_irq_get_domain(intb_irq_data);
232		401
233	ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,	402	/*
234	bd96801_cells,	403	* MFD core code is built to handle only one IRQ domain. BD96801
235	ARRAY_SIZE(bd96801_cells), NULL, 0,	404	* has two domains so we do IRQ mapping here and provide the
236	intb_domain);	405	* already mapped IRQ numbers to sub-devices.
		406	*/
		407	for (i = 0; i < num_intb; i++) {
		408	struct resource *res = &regulator_res[i];
		409
		410	*res = regulator_intb_irqs[i];
		411	res->start = res->end = irq_create_mapping(intb_domain,
		412	res->start);
		413	}
		414
		415	wdg_irq_no = irq_create_mapping(intb_domain, BD96801_WDT_ERR_STAT);
		416	wdg_irq = DEFINE_RES_IRQ_NAMED(wdg_irq_no, "bd96801-wdg");
		417	bd96801_cells[WDG_CELL].resources = &wdg_irq;
		418	bd96801_cells[WDG_CELL].num_resources = 1;
		419
		420	if (!num_errb)
		421	goto skip_errb;
		422
		423	ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, errb_irq, IRQF_ONESHOT,
		424	0, &bd96801_irq_chip_errb, &errb_irq_data);
		425	if (ret)
		426	return dev_err_probe(&i2c->dev, ret,
		427	"Failed to add ERRB IRQ chip\n");
		428
		429	errb_domain = regmap_irq_get_domain(errb_irq_data);
		430
		431	for (i = 0; i < num_errb; i++) {
		432	struct resource *res = &regulator_res[num_intb + i];
		433
		434	*res = regulator_errb_irqs[i];
		435	res->start = res->end = irq_create_mapping(errb_domain, res->start);
		436	}
		437
		438	skip_errb:
		439	bd96801_cells[REGULATOR_CELL].resources = regulator_res;
		440	bd96801_cells[REGULATOR_CELL].num_resources = num_regu_irqs;
		441
		442	ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, bd96801_cells,
		443	ARRAY_SIZE(bd96801_cells), NULL, 0, NULL);
237	if (ret)	444	if (ret)
238	dev_err(&i2c->dev, "Failed to create subdevices\n");	445	dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n");
239		446
240	return ret;	447	return ret;
241	}	448	}

drivers/mfd/rt5033.c+2−2

@@ -81,8 +81,8 @@ static int rt5033_i2c_probe(struct i2c_client *i2c) · 80 unmodified lines
81	chip_rev = dev_id & RT5033_CHIP_REV_MASK;	81	chip_rev = dev_id & RT5033_CHIP_REV_MASK;
82	dev_info(&i2c->dev, "Device found (rev. %d)\n", chip_rev);	82	dev_info(&i2c->dev, "Device found (rev. %d)\n", chip_rev);
83		83
84	ret = regmap_add_irq_chip(rt5033->regmap, rt5033->irq,	84	ret = devm_regmap_add_irq_chip(rt5033->dev, rt5033->regmap,
85	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,	85	rt5033->irq, IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
86	0, &rt5033_irq_chip, &rt5033->irq_data);	86	0, &rt5033_irq_chip, &rt5033->irq_data);
87	if (ret) {	87	if (ret) {
88	dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",	88	dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",

drivers/mfd/sec-core.c+11−0

 	},
 };
+static const struct mfd_cell s2dos05_devs[] = {
+	{ .name = "s2dos05-regulator", },
+};
 static const struct mfd_cell s2mps11_devs[] = {
 	{ .name = "s2mps11-regulator", },
 	{ .name = "s2mps14-rtc", },
 	{
 		.compatible = "samsung,s5m8767-pmic",
 		.data = (void *)S5M8767X,
+	}, {
+		.compatible = "samsung,s2dos05",
+		.data = (void *)S2DOS05,
 	}, {
 		.compatible = "samsung,s2mps11-pmic",
 		.data = (void *)S2MPS11X,
 		sec_devs = s5m8767_devs;
 		num_sec_devs = ARRAY_SIZE(s5m8767_devs);
 		break;
+	case S2DOS05:
+		sec_devs = s2dos05_devs;
+		num_sec_devs = ARRAY_SIZE(s2dos05_devs);
+		break;
 	case S2MPA01:
 		sec_devs = s2mpa01_devs;
 		num_sec_devs = ARRAY_SIZE(s2mpa01_devs);

drivers/mfd/sm501.c+1−1

@@ -1705,7 +1705,7 @@ static struct platform_driver sm501_plat_driver = { · 1704 unmodified lines
1705	.of_match_table = of_sm501_match_tbl,	1705	.of_match_table = of_sm501_match_tbl,
1706	},	1706	},
1707	.probe = sm501_plat_probe,	1707	.probe = sm501_plat_probe,
1708	.remove_new = sm501_plat_remove,	1708	.remove = sm501_plat_remove,
1709	.suspend = pm_sleep_ptr(sm501_plat_suspend),	1709	.suspend = pm_sleep_ptr(sm501_plat_suspend),
1710	.resume = pm_sleep_ptr(sm501_plat_resume),	1710	.resume = pm_sleep_ptr(sm501_plat_resume),
1711	};	1711	};

drivers/mfd/stm32-timers.c+1−1

@@ -326,7 +326,7 @@ MODULE_DEVICE_TABLE(of, stm32_timers_of_match); · 325 unmodified lines
326		326
327	static struct platform_driver stm32_timers_driver = {	327	static struct platform_driver stm32_timers_driver = {
328	.probe = stm32_timers_probe,	328	.probe = stm32_timers_probe,
329	.remove_new = stm32_timers_remove,	329	.remove = stm32_timers_remove,
330	.driver = {	330	.driver = {
331	.name = "stm32-timers",	331	.name = "stm32-timers",
332	.of_match_table = stm32_timers_of_match,	332	.of_match_table = stm32_timers_of_match,

drivers/mfd/syscon.c+5−0

 	syscon_config.reg_stride = reg_io_width;
 	syscon_config.val_bits = reg_io_width * 8;
 	syscon_config.max_register = resource_size(&res) - reg_io_width;
+	if (!syscon_config.max_register)
+		syscon_config.max_register_is_0 = true;
 	regmap = regmap_init_mmio(NULL, base, &syscon_config);
 	kfree(syscon_config.name);
 		return -ENOMEM;
 	syscon_config.max_register = resource_size(res) - 4;
+	if (!syscon_config.max_register)
+		syscon_config.max_register_is_0 = true;
 	if (pdata)
 		syscon_config.name = pdata->label;
 	syscon->regmap = devm_regmap_init_mmio(dev, base, &syscon_config);

drivers/mfd/ti_am335x_tscadc.c+1−1

@@ -377,7 +377,7 @@ static struct platform_driver ti_tscadc_driver = { · 376 unmodified lines
377	.of_match_table = ti_tscadc_dt_ids,	377	.of_match_table = ti_tscadc_dt_ids,
378	},	378	},
379	.probe = ti_tscadc_probe,	379	.probe = ti_tscadc_probe,
380	.remove_new = ti_tscadc_remove,	380	.remove = ti_tscadc_remove,
381		381
382	};	382	};
383		383

drivers/mfd/tps65010.c+2−6

 	 */
 	if (client->irq > 0) {
 		status = request_irq(client->irq, tps65010_irq,
-				     IRQF_TRIGGER_FALLING, DRIVER_NAME, tps);
+				     IRQF_TRIGGER_FALLING | IRQF_NO_AUTOEN,
+				     DRIVER_NAME, tps);
 		if (status < 0) {
 			dev_dbg(&client->dev, "can't get IRQ %d, err %d\n",
 					client->irq, status);
 			return status;
 		}
-		/* annoying race here, ideally we'd have an option
-		 * to claim the irq now and enable it later.
-		 * FIXME genirq IRQF_NOAUTOEN now solves that ...
-		 */
-		disable_irq(client->irq);
 		set_bit(FLAG_IRQ_ENABLE, &tps->flags);
 	} else
 		dev_warn(&client->dev, "IRQ not configured!\n");

drivers/mfd/tps65911-comparator.c+1−1

@@ -154,7 +154,7 @@ static struct platform_driver tps65911_comparator_driver = { · 153 unmodified lines
154	.name = "tps65911-comparator",	154	.name = "tps65911-comparator",
155	},	155	},
156	.probe = tps65911_comparator_probe,	156	.probe = tps65911_comparator_probe,
157	.remove_new = tps65911_comparator_remove,	157	.remove = tps65911_comparator_remove,
158	};	158	};
159		159
160	static int __init tps65911_comparator_init(void)	160	static int __init tps65911_comparator_init(void)

drivers/mfd/tqmx86.c+79−36

 #define TQMX86_REG_BOARD_ID_E39C2	7
 #define TQMX86_REG_BOARD_ID_70EB	8
 #define TQMX86_REG_BOARD_ID_80UC	9
+#define TQMX86_REG_BOARD_ID_120UC	10
 #define TQMX86_REG_BOARD_ID_110EB	11
 #define TQMX86_REG_BOARD_ID_E40M	12
 #define TQMX86_REG_BOARD_ID_E40S	13
 #define TQMX86_REG_BOARD_ID_E40C1	14
 #define TQMX86_REG_BOARD_ID_E40C2	15
+#define TQMX86_REG_BOARD_ID_130UC	16
+#define TQMX86_REG_BOARD_ID_E41S	19
 #define TQMX86_REG_BOARD_REV	0x01
 #define TQMX86_REG_IO_EXT_INT	0x06
 #define TQMX86_REG_IO_EXT_INT_NONE		0
 #define TQMX86_REG_IO_EXT_INT_9			2
 #define TQMX86_REG_IO_EXT_INT_12		3
 #define TQMX86_REG_IO_EXT_INT_MASK		0x3
+#define TQMX86_REG_IO_EXT_INT_I2C1_SHIFT	0
 #define TQMX86_REG_IO_EXT_INT_GPIO_SHIFT	4
 #define TQMX86_REG_SAUC		0x17
 static uint gpio_irq;
 module_param(gpio_irq, uint, 0);
-MODULE_PARM_DESC(gpio_irq, "GPIO IRQ number (7, 9, 12)");
+MODULE_PARM_DESC(gpio_irq, "GPIO IRQ number (valid parameters: 7, 9, 12)");
-static const struct resource tqmx_i2c_soft_resources[] = {
+static uint i2c1_irq;
-	DEFINE_RES_IO(TQMX86_IOBASE_I2C, TQMX86_IOSIZE_I2C),
+module_param(i2c1_irq, uint, 0);
+MODULE_PARM_DESC(i2c1_irq, "I2C1 IRQ number (valid parameters: 7, 9, 12)");
+enum tqmx86_i2c1_resource_type {
+	TQMX86_I2C1_IO,
+	TQMX86_I2C1_IRQ,
+};
+static struct resource tqmx_i2c_soft_resources[] = {
+	[TQMX86_I2C1_IO] = DEFINE_RES_IO(TQMX86_IOBASE_I2C, TQMX86_IOSIZE_I2C),
+	/* Placeholder for IRQ resource */
+	[TQMX86_I2C1_IRQ] = {},
 };
 static const struct resource tqmx_watchdog_resources[] = {
 	DEFINE_RES_IO(TQMX86_IOBASE_WATCHDOG, TQMX86_IOSIZE_WATCHDOG),
 };
-/*
+enum tqmx86_gpio_resource_type {
- * The IRQ resource must be first, since it is updated with the
+	TQMX86_GPIO_IO,
- * configured IRQ in the probe function.
+	TQMX86_GPIO_IRQ,
- */
+};
 static struct resource tqmx_gpio_resources[] = {
-	DEFINE_RES_IRQ(0),
+	[TQMX86_GPIO_IO] = DEFINE_RES_IO(TQMX86_IOBASE_GPIO, TQMX86_IOSIZE_GPIO),
-	DEFINE_RES_IO(TQMX86_IOBASE_GPIO, TQMX86_IOSIZE_GPIO),
+	/* Placeholder for IRQ resource */
+	[TQMX86_GPIO_IRQ] = {},
 };
 static struct i2c_board_info tqmx86_i2c_devices[] = {
 		return "TQMx70EB";
 	case TQMX86_REG_BOARD_ID_80UC:
 		return "TQMx80UC";
+	case TQMX86_REG_BOARD_ID_120UC:
+		return "TQMx120UC";
 	case TQMX86_REG_BOARD_ID_110EB:
 		return "TQMx110EB";
 	case TQMX86_REG_BOARD_ID_E40M:
 		return "TQMxE40C1";
 	case TQMX86_REG_BOARD_ID_E40C2:
 		return "TQMxE40C2";
+	case TQMX86_REG_BOARD_ID_130UC:
+		return "TQMx130UC";
+	case TQMX86_REG_BOARD_ID_E41S:
+		return "TQMxE41S";
 	default:
 		return "Unknown";
 	}
 	case TQMX86_REG_BOARD_ID_60EB:
 	case TQMX86_REG_BOARD_ID_70EB:
 	case TQMX86_REG_BOARD_ID_80UC:
+	case TQMX86_REG_BOARD_ID_120UC:
 	case TQMX86_REG_BOARD_ID_110EB:
 	case TQMX86_REG_BOARD_ID_E40M:
 	case TQMX86_REG_BOARD_ID_E40S:
 	case TQMX86_REG_BOARD_ID_E40C1:
 	case TQMX86_REG_BOARD_ID_E40C2:
+	case TQMX86_REG_BOARD_ID_130UC:
+	case TQMX86_REG_BOARD_ID_E41S:
 		return 24000;
 	case TQMX86_REG_BOARD_ID_E39MS:
 	case TQMX86_REG_BOARD_ID_E39C1:
 	}
 }
-static int tqmx86_probe(struct platform_device *pdev)
+static int tqmx86_setup_irq(struct device *dev, const char *label, u8 irq,
+			    void __iomem *io_base, u8 reg_shift)
 {
-	u8 board_id, sauc, rev, i2c_det, io_ext_int_val;
+	u8 val, readback;
-	struct device *dev = &pdev->dev;
+	int irq_cfg;
-	u8 gpio_irq_cfg, readback;
-	const char *board_name;
-	void __iomem *io_base;
-	int err;
-	switch (gpio_irq) {
+	switch (irq) {
 	case 0:
-		gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_NONE;
+		irq_cfg = TQMX86_REG_IO_EXT_INT_NONE;
 		break;
 	case 7:
-		gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_7;
+		irq_cfg = TQMX86_REG_IO_EXT_INT_7;
 		break;
 	case 9:
-		gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_9;
+		irq_cfg = TQMX86_REG_IO_EXT_INT_9;
 		break;
 	case 12:
-		gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_12;
+		irq_cfg = TQMX86_REG_IO_EXT_INT_12;
 		break;
 	default:
-		pr_err("tqmx86: Invalid GPIO IRQ (%d)\n", gpio_irq);
+		dev_err(dev, "invalid %s IRQ (%d)\n", label, irq);
 		return -EINVAL;
 	}
+	val = ioread8(io_base + TQMX86_REG_IO_EXT_INT);
+	val &= ~(TQMX86_REG_IO_EXT_INT_MASK << reg_shift);
+	val |= (irq_cfg & TQMX86_REG_IO_EXT_INT_MASK) << reg_shift;
+	iowrite8(val, io_base + TQMX86_REG_IO_EXT_INT);
+	readback = ioread8(io_base + TQMX86_REG_IO_EXT_INT);
+	if (readback != val) {
+		dev_warn(dev, "%s interrupts not supported\n", label);
+		return -EINVAL;
+	}
+	return 0;
+}
+static int tqmx86_probe(struct platform_device *pdev)
+{
+	u8 board_id, sauc, rev, i2c_det;
+	struct device *dev = &pdev->dev;
+	const char *board_name;
+	void __iomem *io_base;
+	int err;
 	io_base = devm_ioport_map(dev, TQMX86_IOBASE, TQMX86_IOSIZE);
 	if (!io_base)
 		return -ENOMEM;
 	 */
 	i2c_det = inb(TQMX86_REG_I2C_DETECT);
-	if (gpio_irq_cfg) {
+	if (gpio_irq) {
-		io_ext_int_val =
+		err = tqmx86_setup_irq(dev, "GPIO", gpio_irq, io_base,
-			gpio_irq_cfg << TQMX86_REG_IO_EXT_INT_GPIO_SHIFT;
+				       TQMX86_REG_IO_EXT_INT_GPIO_SHIFT);
-		iowrite8(io_ext_int_val, io_base + TQMX86_REG_IO_EXT_INT);
+		if (!err)
-		readback = ioread8(io_base + TQMX86_REG_IO_EXT_INT);
+			tqmx_gpio_resources[TQMX86_GPIO_IRQ] = DEFINE_RES_IRQ(gpio_irq);
-		if (readback != io_ext_int_val) {
-			dev_warn(dev, "GPIO interrupts not supported.\n");
-			return -EINVAL;
-		}
-		/* Assumes the IRQ resource is first. */
-		tqmx_gpio_resources[0].start = gpio_irq;
-	} else {
-		tqmx_gpio_resources[0].flags = 0;
 	}
 	ocores_platform_data.clock_khz = tqmx86_board_id_to_clk_rate(dev, board_id);
 	if (i2c_det == TQMX86_REG_I2C_DETECT_SOFT) {
+		if (i2c1_irq) {
+			err = tqmx86_setup_irq(dev, "I2C1", i2c1_irq, io_base,
+					       TQMX86_REG_IO_EXT_INT_I2C1_SHIFT);
+			if (!err)
+				tqmx_i2c_soft_resources[TQMX86_I2C1_IRQ] = DEFINE_RES_IRQ(i2c1_irq);
+		}
 		err = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
 					   tqmx86_i2c_soft_dev,
 					   ARRAY_SIZE(tqmx86_i2c_soft_dev),

drivers/mfd/twl-core.c+18−8

@@ -711,6 +711,10 @@ static struct of_dev_auxdata twl_auxdata_lookup[] = { · 710 unmodified lines
711	{ /* sentinel */ },	711	{ /* sentinel */ },
712	};	712	};
713		713
		714	static const struct mfd_cell twl6030_cells[] = {
		715	{ .name = "twl6030-clk" },
		716	};
		717
714	static const struct mfd_cell twl6032_cells[] = {	718	static const struct mfd_cell twl6032_cells[] = {
715	{ .name = "twl6032-clk" },	719	{ .name = "twl6032-clk" },
716	};	720	};
@@ -861,17 +865,23 @@ twl_probe(struct i2c_client *client) · 144 unmodified lines
861	TWL4030_DCDC_GLOBAL_CFG);	865	TWL4030_DCDC_GLOBAL_CFG);
862	}	866	}
863		867
864	if (id->driver_data == (TWL6030_CLASS \| TWL6032_SUBCLASS)) {	868	if (twl_class_is_6030()) {
865	status = devm_mfd_add_devices(&client->dev,	869	const struct mfd_cell *cells;
866	PLATFORM_DEVID_NONE,	870	int num_cells;
867	twl6032_cells,	871
868	ARRAY_SIZE(twl6032_cells),	872	if (id->driver_data & TWL6032_SUBCLASS) {
869	NULL, 0, NULL);	873	cells = twl6032_cells;
		874	num_cells = ARRAY_SIZE(twl6032_cells);
		875	} else {
		876	cells = twl6030_cells;
		877	num_cells = ARRAY_SIZE(twl6030_cells);
		878	}
		879
		880	status = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE,
		881	cells, num_cells, NULL, 0, NULL);
870	if (status < 0)	882	if (status < 0)
871	goto free;	883	goto free;
872	}
873		884
874	if (twl_class_is_6030()) {
875	if (of_device_is_system_power_controller(node)) {	885	if (of_device_is_system_power_controller(node)) {
876	if (!pm_power_off)	886	if (!pm_power_off)
877	pm_power_off = twl6030_power_off;	887	pm_power_off = twl6030_power_off;

drivers/mfd/twl4030-audio.c+1−1

@@ -276,7 +276,7 @@ static struct platform_driver twl4030_audio_driver = { · 275 unmodified lines
276	.of_match_table = twl4030_audio_of_match,	276	.of_match_table = twl4030_audio_of_match,
277	},	277	},
278	.probe = twl4030_audio_probe,	278	.probe = twl4030_audio_probe,
279	.remove_new = twl4030_audio_remove,	279	.remove = twl4030_audio_remove,
280	};	280	};
281		281
282	module_platform_driver(twl4030_audio_driver);	282	module_platform_driver(twl4030_audio_driver);

drivers/mfd/wcd934x.c+1−1

 	  SLIM_DEV_IDX_WCD9340, SLIM_DEV_INSTANCE_ID_WCD9340 },
 	{}
 };
+MODULE_DEVICE_TABLE(slim, wcd934x_slim_id);
 static struct slim_driver wcd934x_slim_driver = {
 	.driver = {
 module_slim_driver(wcd934x_slim_driver);
 MODULE_DESCRIPTION("WCD934X slim driver");
 MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("slim:217:250:*");
 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");

drivers/platform/x86/intel/bxtwc_tmu.c+6−16

 static int bxt_wcove_tmu_probe(struct platform_device *pdev)
 {
 	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
-	struct regmap_irq_chip_data *regmap_irq_chip;
 	struct wcove_tmu *wctmu;
-	int ret, virq, irq;
+	int ret;
 	wctmu = devm_kzalloc(&pdev->dev, sizeof(*wctmu), GFP_KERNEL);
 	if (!wctmu)
 	wctmu->dev = &pdev->dev;
 	wctmu->regmap = pmic->regmap;
-	irq = platform_get_irq(pdev, 0);
+	wctmu->irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
+	if (wctmu->irq < 0)
-		return irq;
+		return wctmu->irq;
-	regmap_irq_chip = pmic->irq_chip_data_tmu;
+	ret = devm_request_threaded_irq(&pdev->dev, wctmu->irq,
-	virq = regmap_irq_get_virq(regmap_irq_chip, irq);
-	if (virq < 0) {
-		dev_err(&pdev->dev,
-			"failed to get virtual interrupt=%d\n", irq);
-		return virq;
-	}
-	ret = devm_request_threaded_irq(&pdev->dev, virq,
 					NULL, bxt_wcove_tmu_irq_handler,
 					IRQF_ONESHOT, "bxt_wcove_tmu", wctmu);
 	if (ret) {
 		dev_err(&pdev->dev, "request irq failed: %d,virq: %d\n",
-							ret, virq);
+			ret, wctmu->irq);
 		return ret;
 	}
-	wctmu->irq = virq;
 	/* Unmask TMU second level Wake & System alarm */
 	regmap_update_bits(wctmu->regmap, BXTWC_MTMUIRQ_REG,

drivers/regulator/axp20x-regulator.c+12−1

 		step = 150;
 		break;
 	case AXP313A_ID:
+	case AXP323_ID:
 	case AXP717_ID:
 	case AXP15060_ID:
 		/* The DCDC PWM frequency seems to be fixed to 3 MHz. */
 		}
 		break;
+	case AXP323_ID:
+		regmap_read(axp20x->regmap, AXP323_DCDC_MODE_CTRL2, &reg);
+		switch (id) {
+		case AXP313A_DCDC2:
+			return !!(reg & BIT(1));
+		}
+		break;
 	default:
 		return false;
 	}
 						  "x-powers,drive-vbus-en");
 		break;
 	case AXP313A_ID:
+	case AXP323_ID:
 		regulators = axp313a_regulators;
 		nregulators = AXP313A_REG_ID_MAX;
 		break;
 		nregulators = AXP15060_REG_ID_MAX;
 		break;
 	default:
-		dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
+		dev_err(&pdev->dev, "Unsupported AXP variant: %d\n",
 			axp20x->variant);
 		return -EINVAL;
 	}

drivers/rtc/rtc-bd70528.c+1−4

 {
 	struct bd70528_rtc *bd_rtc;
 	const struct rtc_class_ops *rtc_ops;
-	const char *irq_name;
 	int ret;
 	struct rtc_device *rtc;
 	int irq;
 	switch (chip) {
 	case ROHM_CHIP_TYPE_BD71815:
-		irq_name = "bd71815-rtc-alm-0";
 		bd_rtc->reg_time_start = BD71815_REG_RTC_START;
 		/*
 		hour_reg = BD71815_REG_HOUR;
 		break;
 	case ROHM_CHIP_TYPE_BD71828:
-		irq_name = "bd71828-rtc-alm-0";
 		bd_rtc->reg_time_start = BD71828_REG_RTC_START;
 		bd_rtc->bd718xx_alm_block_start = BD71828_REG_RTC_ALM_START;
 		hour_reg = BD71828_REG_RTC_HOUR;
 		return -ENOENT;
 	}
-	irq = platform_get_irq_byname(pdev, irq_name);
+	irq = platform_get_irq_byname(pdev, "bd70528-rtc-alm-0");
 	if (irq < 0)
 		return irq;

drivers/usb/typec/tcpm/wcove.c+0−4

 	if (irq < 0)
 		return irq;
-	irq = regmap_irq_get_virq(pmic->irq_chip_data_chgr, irq);
-	if (irq < 0)
-		return irq;
 	ret = guid_parse(WCOVE_DSM_UUID, &wcove->guid);
 	if (ret)
 		return ret;

include/dt-bindings/clock/aspeed,ast2700-scu.h+163−0

@@ -0,0 +1,163 @@
	1	/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
	2	/*
	3	* Device Tree binding constants for AST2700 clock controller.
	4	*
	5	* Copyright (c) 2024 Aspeed Technology Inc.
	6	*/
	7
	8	#ifndef __DT_BINDINGS_CLOCK_AST2700_H
	9	#define __DT_BINDINGS_CLOCK_AST2700_H
	10
	11	/* SOC0 clk */
	12	#define SCU0_CLKIN 0
	13	#define SCU0_CLK_24M 1
	14	#define SCU0_CLK_192M 2
	15	#define SCU0_CLK_UART 3
	16	#define SCU0_CLK_UART_DIV13 3
	17	#define SCU0_CLK_PSP 4
	18	#define SCU0_CLK_HPLL 5
	19	#define SCU0_CLK_HPLL_DIV2 6
	20	#define SCU0_CLK_HPLL_DIV4 7
	21	#define SCU0_CLK_HPLL_DIV_AHB 8
	22	#define SCU0_CLK_DPLL 9
	23	#define SCU0_CLK_MPLL 10
	24	#define SCU0_CLK_MPLL_DIV2 11
	25	#define SCU0_CLK_MPLL_DIV4 12
	26	#define SCU0_CLK_MPLL_DIV8 13
	27	#define SCU0_CLK_MPLL_DIV_AHB 14
	28	#define SCU0_CLK_D0 15
	29	#define SCU0_CLK_D1 16
	30	#define SCU0_CLK_CRT0 17
	31	#define SCU0_CLK_CRT1 18
	32	#define SCU0_CLK_MPHY 19
	33	#define SCU0_CLK_AXI0 20
	34	#define SCU0_CLK_AXI1 21
	35	#define SCU0_CLK_AHB 22
	36	#define SCU0_CLK_APB 23
	37	#define SCU0_CLK_UART4 24
	38	#define SCU0_CLK_EMMCMUX 25
	39	#define SCU0_CLK_EMMC 26
	40	#define SCU0_CLK_U2PHY_CLK12M 27
	41	#define SCU0_CLK_U2PHY_REFCLK 28
	42
	43	/* SOC0 clk-gate */
	44	#define SCU0_CLK_GATE_MCLK 29
	45	#define SCU0_CLK_GATE_ECLK 30
	46	#define SCU0_CLK_GATE_2DCLK 31
	47	#define SCU0_CLK_GATE_VCLK 32
	48	#define SCU0_CLK_GATE_BCLK 33
	49	#define SCU0_CLK_GATE_VGA0CLK 34
	50	#define SCU0_CLK_GATE_REFCLK 35
	51	#define SCU0_CLK_GATE_PORTBUSB2CLK 36
	52	#define SCU0_CLK_GATE_UHCICLK 37
	53	#define SCU0_CLK_GATE_VGA1CLK 38
	54	#define SCU0_CLK_GATE_DDRPHYCLK 39
	55	#define SCU0_CLK_GATE_E2M0CLK 40
	56	#define SCU0_CLK_GATE_HACCLK 41
	57	#define SCU0_CLK_GATE_PORTAUSB2CLK 42
	58	#define SCU0_CLK_GATE_UART4CLK 43
	59	#define SCU0_CLK_GATE_SLICLK 44
	60	#define SCU0_CLK_GATE_DACCLK 45
	61	#define SCU0_CLK_GATE_DP 46
	62	#define SCU0_CLK_GATE_E2M1CLK 47
	63	#define SCU0_CLK_GATE_CRT0CLK 48
	64	#define SCU0_CLK_GATE_CRT1CLK 49
	65	#define SCU0_CLK_GATE_ECDSACLK 50
	66	#define SCU0_CLK_GATE_RSACLK 51
	67	#define SCU0_CLK_GATE_RVAS0CLK 52
	68	#define SCU0_CLK_GATE_UFSCLK 53
	69	#define SCU0_CLK_GATE_EMMCCLK 54
	70	#define SCU0_CLK_GATE_RVAS1CLK 55
	71
	72	/* SOC1 clk */
	73	#define SCU1_CLKIN 0
	74	#define SCU1_CLK_HPLL 1
	75	#define SCU1_CLK_APLL 2
	76	#define SCU1_CLK_APLL_DIV2 3
	77	#define SCU1_CLK_APLL_DIV4 4
	78	#define SCU1_CLK_DPLL 5
	79	#define SCU1_CLK_UXCLK 6
	80	#define SCU1_CLK_HUXCLK 7
	81	#define SCU1_CLK_UARTX 8
	82	#define SCU1_CLK_HUARTX 9
	83	#define SCU1_CLK_AHB 10
	84	#define SCU1_CLK_APB 11
	85	#define SCU1_CLK_UART0 12
	86	#define SCU1_CLK_UART1 13
	87	#define SCU1_CLK_UART2 14
	88	#define SCU1_CLK_UART3 15
	89	#define SCU1_CLK_UART5 16
	90	#define SCU1_CLK_UART6 17
	91	#define SCU1_CLK_UART7 18
	92	#define SCU1_CLK_UART8 19
	93	#define SCU1_CLK_UART9 20
	94	#define SCU1_CLK_UART10 21
	95	#define SCU1_CLK_UART11 22
	96	#define SCU1_CLK_UART12 23
	97	#define SCU1_CLK_UART13 24
	98	#define SCU1_CLK_UART14 25
	99	#define SCU1_CLK_APLL_DIVN 26
	100	#define SCU1_CLK_SDMUX 27
	101	#define SCU1_CLK_SDCLK 28
	102	#define SCU1_CLK_RMII 29
	103	#define SCU1_CLK_RGMII 30
	104	#define SCU1_CLK_MACHCLK 31
	105	#define SCU1_CLK_MAC0RCLK 32
	106	#define SCU1_CLK_MAC1RCLK 33
	107	#define SCU1_CLK_CAN 34
	108
	109	/* SOC1 clk gate */
	110	#define SCU1_CLK_GATE_LCLK0 35
	111	#define SCU1_CLK_GATE_LCLK1 36
	112	#define SCU1_CLK_GATE_ESPI0CLK 37
	113	#define SCU1_CLK_GATE_ESPI1CLK 38
	114	#define SCU1_CLK_GATE_SDCLK 39
	115	#define SCU1_CLK_GATE_IPEREFCLK 40
	116	#define SCU1_CLK_GATE_REFCLK 41
	117	#define SCU1_CLK_GATE_LPCHCLK 42
	118	#define SCU1_CLK_GATE_MAC0CLK 43
	119	#define SCU1_CLK_GATE_MAC1CLK 44
	120	#define SCU1_CLK_GATE_MAC2CLK 45
	121	#define SCU1_CLK_GATE_UART0CLK 46
	122	#define SCU1_CLK_GATE_UART1CLK 47
	123	#define SCU1_CLK_GATE_UART2CLK 48
	124	#define SCU1_CLK_GATE_UART3CLK 49
	125	#define SCU1_CLK_GATE_I2CCLK 50
	126	#define SCU1_CLK_GATE_I3C0CLK 51
	127	#define SCU1_CLK_GATE_I3C1CLK 52
	128	#define SCU1_CLK_GATE_I3C2CLK 53
	129	#define SCU1_CLK_GATE_I3C3CLK 54
	130	#define SCU1_CLK_GATE_I3C4CLK 55
	131	#define SCU1_CLK_GATE_I3C5CLK 56
	132	#define SCU1_CLK_GATE_I3C6CLK 57
	133	#define SCU1_CLK_GATE_I3C7CLK 58
	134	#define SCU1_CLK_GATE_I3C8CLK 59
	135	#define SCU1_CLK_GATE_I3C9CLK 60
	136	#define SCU1_CLK_GATE_I3C10CLK 61
	137	#define SCU1_CLK_GATE_I3C11CLK 62
	138	#define SCU1_CLK_GATE_I3C12CLK 63
	139	#define SCU1_CLK_GATE_I3C13CLK 64
	140	#define SCU1_CLK_GATE_I3C14CLK 65
	141	#define SCU1_CLK_GATE_I3C15CLK 66
	142	#define SCU1_CLK_GATE_UART5CLK 67
	143	#define SCU1_CLK_GATE_UART6CLK 68
	144	#define SCU1_CLK_GATE_UART7CLK 69
	145	#define SCU1_CLK_GATE_UART8CLK 70
	146	#define SCU1_CLK_GATE_UART9CLK 71
	147	#define SCU1_CLK_GATE_UART10CLK 72
	148	#define SCU1_CLK_GATE_UART11CLK 73
	149	#define SCU1_CLK_GATE_UART12CLK 74
	150	#define SCU1_CLK_GATE_FSICLK 75
	151	#define SCU1_CLK_GATE_LTPIPHYCLK 76
	152	#define SCU1_CLK_GATE_LTPICLK 77
	153	#define SCU1_CLK_GATE_VGALCLK 78
	154	#define SCU1_CLK_GATE_UHCICLK 79
	155	#define SCU1_CLK_GATE_CANCLK 80
	156	#define SCU1_CLK_GATE_PCICLK 81
	157	#define SCU1_CLK_GATE_SLICLK 82
	158	#define SCU1_CLK_GATE_E2MCLK 83
	159	#define SCU1_CLK_GATE_PORTCUSB2CLK 84
	160	#define SCU1_CLK_GATE_PORTDUSB2CLK 85
	161	#define SCU1_CLK_GATE_LTPI1TXCLK 86
	162
	163	#endif

include/dt-bindings/reset/aspeed,ast2700-scu.h+124−0

@@ -0,0 +1,124 @@
	1	/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
	2	/*
	3	* Device Tree binding constants for AST2700 reset controller.
	4	*
	5	* Copyright (c) 2024 Aspeed Technology Inc.
	6	*/
	7
	8	#ifndef _MACH_ASPEED_AST2700_RESET_H_
	9	#define _MACH_ASPEED_AST2700_RESET_H_
	10
	11	/* SOC0 */
	12	#define SCU0_RESET_SDRAM 0
	13	#define SCU0_RESET_DDRPHY 1
	14	#define SCU0_RESET_RSA 2
	15	#define SCU0_RESET_SHA3 3
	16	#define SCU0_RESET_HACE 4
	17	#define SCU0_RESET_SOC 5
	18	#define SCU0_RESET_VIDEO 6
	19	#define SCU0_RESET_2D 7
	20	#define SCU0_RESET_PCIS 8
	21	#define SCU0_RESET_RVAS0 9
	22	#define SCU0_RESET_RVAS1 10
	23	#define SCU0_RESET_SM3 11
	24	#define SCU0_RESET_SM4 12
	25	#define SCU0_RESET_CRT0 13
	26	#define SCU0_RESET_ECC 14
	27	#define SCU0_RESET_DP_PCI 15
	28	#define SCU0_RESET_UFS 16
	29	#define SCU0_RESET_EMMC 17
	30	#define SCU0_RESET_PCIE1RST 18
	31	#define SCU0_RESET_PCIE1RSTOE 19
	32	#define SCU0_RESET_PCIE0RST 20
	33	#define SCU0_RESET_PCIE0RSTOE 21
	34	#define SCU0_RESET_JTAG 22
	35	#define SCU0_RESET_MCTP0 23
	36	#define SCU0_RESET_MCTP1 24
	37	#define SCU0_RESET_XDMA0 25
	38	#define SCU0_RESET_XDMA1 26
	39	#define SCU0_RESET_H2X1 27
	40	#define SCU0_RESET_DP 28
	41	#define SCU0_RESET_DP_MCU 29
	42	#define SCU0_RESET_SSP 30
	43	#define SCU0_RESET_H2X0 31
	44	#define SCU0_RESET_PORTA_VHUB 32
	45	#define SCU0_RESET_PORTA_PHY3 33
	46	#define SCU0_RESET_PORTA_XHCI 34
	47	#define SCU0_RESET_PORTB_VHUB 35
	48	#define SCU0_RESET_PORTB_PHY3 36
	49	#define SCU0_RESET_PORTB_XHCI 37
	50	#define SCU0_RESET_PORTA_VHUB_EHCI 38
	51	#define SCU0_RESET_PORTB_VHUB_EHCI 39
	52	#define SCU0_RESET_UHCI 40
	53	#define SCU0_RESET_TSP 41
	54	#define SCU0_RESET_E2M0 42
	55	#define SCU0_RESET_E2M1 43
	56	#define SCU0_RESET_VLINK 44
	57
	58	/* SOC1 */
	59	#define SCU1_RESET_LPC0 0
	60	#define SCU1_RESET_LPC1 1
	61	#define SCU1_RESET_MII 2
	62	#define SCU1_RESET_PECI 3
	63	#define SCU1_RESET_PWM 4
	64	#define SCU1_RESET_MAC0 5
	65	#define SCU1_RESET_MAC1 6
	66	#define SCU1_RESET_MAC2 7
	67	#define SCU1_RESET_ADC 8
	68	#define SCU1_RESET_SD 9
	69	#define SCU1_RESET_ESPI0 10
	70	#define SCU1_RESET_ESPI1 11
	71	#define SCU1_RESET_JTAG1 12
	72	#define SCU1_RESET_SPI0 13
	73	#define SCU1_RESET_SPI1 14
	74	#define SCU1_RESET_SPI2 15
	75	#define SCU1_RESET_I3C0 16
	76	#define SCU1_RESET_I3C1 17
	77	#define SCU1_RESET_I3C2 18
	78	#define SCU1_RESET_I3C3 19
	79	#define SCU1_RESET_I3C4 20
	80	#define SCU1_RESET_I3C5 21
	81	#define SCU1_RESET_I3C6 22
	82	#define SCU1_RESET_I3C7 23
	83	#define SCU1_RESET_I3C8 24
	84	#define SCU1_RESET_I3C9 25
	85	#define SCU1_RESET_I3C10 26
	86	#define SCU1_RESET_I3C11 27
	87	#define SCU1_RESET_I3C12 28
	88	#define SCU1_RESET_I3C13 29
	89	#define SCU1_RESET_I3C14 30
	90	#define SCU1_RESET_I3C15 31
	91	#define SCU1_RESET_MCU0 32
	92	#define SCU1_RESET_MCU1 33
	93	#define SCU1_RESET_H2A_SPI1 34
	94	#define SCU1_RESET_H2A_SPI2 35
	95	#define SCU1_RESET_UART0 36
	96	#define SCU1_RESET_UART1 37
	97	#define SCU1_RESET_UART2 38
	98	#define SCU1_RESET_UART3 39
	99	#define SCU1_RESET_I2C_FILTER 40
	100	#define SCU1_RESET_CALIPTRA 41
	101	#define SCU1_RESET_XDMA 42
	102	#define SCU1_RESET_FSI 43
	103	#define SCU1_RESET_CAN 44
	104	#define SCU1_RESET_MCTP 45
	105	#define SCU1_RESET_I2C 46
	106	#define SCU1_RESET_UART6 47
	107	#define SCU1_RESET_UART7 48
	108	#define SCU1_RESET_UART8 49
	109	#define SCU1_RESET_UART9 50
	110	#define SCU1_RESET_LTPI0 51
	111	#define SCU1_RESET_VGAL 52
	112	#define SCU1_RESET_LTPI1 53
	113	#define SCU1_RESET_ACE 54
	114	#define SCU1_RESET_E2M 55
	115	#define SCU1_RESET_UHCI 56
	116	#define SCU1_RESET_PORTC_USB2UART 57
	117	#define SCU1_RESET_PORTC_VHUB_EHCI 58
	118	#define SCU1_RESET_PORTD_USB2UART 59
	119	#define SCU1_RESET_PORTD_VHUB_EHCI 60
	120	#define SCU1_RESET_H2X 61
	121	#define SCU1_RESET_I3CDMA 62
	122	#define SCU1_RESET_PCIE2RST 63
	123
	124	#endif /* _MACH_ASPEED_AST2700_RESET_H_ */

include/linux/mfd/axp20x.h+3−1

 	AXP223_ID,
 	AXP288_ID,
 	AXP313A_ID,
+	AXP323_ID,
 	AXP717_ID,
 	AXP803_ID,
 	AXP806_ID,
 #define AXP313A_SHUTDOWN_CTRL		0x1a
 #define AXP313A_IRQ_EN			0x20
 #define AXP313A_IRQ_STATE		0x21
+#define AXP323_DCDC_MODE_CTRL2		0x22
 #define AXP717_ON_INDICATE		0x00
 #define AXP717_PMU_STATUS_2		0x01
 	unsigned long			irq_flags;
 	struct regmap			*regmap;
 	struct regmap_irq_chip_data	*regmap_irqc;
-	long				variant;
+	enum axp20x_variants		variant;
 	int                             nr_cells;
 	const struct mfd_cell           *cells;
 	const struct regmap_config	*regmap_cfg;

include/linux/mfd/max77693-private.h+0−11

@@ -419,17 +419,6 @@ enum max77693_haptic_reg { · 418 unmodified lines
419	#define MAX77693_CONFIG2_MEN 6	419	#define MAX77693_CONFIG2_MEN 6
420	#define MAX77693_CONFIG2_HTYP 5	420	#define MAX77693_CONFIG2_HTYP 5
421		421
422	enum max77693_irq_source {
423	LED_INT = 0,
424	TOPSYS_INT,
425	CHG_INT,
426	MUIC_INT1,
427	MUIC_INT2,
428	MUIC_INT3,
429
430	MAX77693_IRQ_GROUP_NR,
431	};
432
433	#define SRC_IRQ_CHARGER BIT(0)	422	#define SRC_IRQ_CHARGER BIT(0)
434	#define SRC_IRQ_TOP BIT(1)	423	#define SRC_IRQ_TOP BIT(1)
435	#define SRC_IRQ_FLASH BIT(2)	424	#define SRC_IRQ_FLASH BIT(2)

include/linux/mfd/mt6328/core.h+53−0

@@ -0,0 +1,53 @@
	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* Copyright (c) 2015 MediaTek Inc.
	4	* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
	5	*/
	6
	7	#ifndef __MFD_MT6328_CORE_H__
	8	#define __MFD_MT6328_CORE_H__
	9
	10	enum mt6328_irq_status_numbers {
	11	MT6328_IRQ_STATUS_PWRKEY = 0,
	12	MT6328_IRQ_STATUS_HOMEKEY,
	13	MT6328_IRQ_STATUS_PWRKEY_R,
	14	MT6328_IRQ_STATUS_HOMEKEY_R,
	15	MT6328_IRQ_STATUS_THR_H,
	16	MT6328_IRQ_STATUS_THR_L,
	17	MT6328_IRQ_STATUS_BAT_H,
	18	MT6328_IRQ_STATUS_BAT_L,
	19	MT6328_IRQ_STATUS_RTC,
	20	MT6328_IRQ_STATUS_AUDIO,
	21	MT6328_IRQ_STATUS_ACCDET,
	22	MT6328_IRQ_STATUS_ACCDET_EINT,
	23	MT6328_IRQ_STATUS_ACCDET_NEGV,
	24	MT6328_IRQ_STATUS_NI_LBAT_INT,
	25	MT6328_IRQ_STATUS_VPROC_OC = 16,
	26	MT6328_IRQ_STATUS_VSYS_OC,
	27	MT6328_IRQ_STATUS_VLTE_OC,
	28	MT6328_IRQ_STATUS_VCORE_OC,
	29	MT6328_IRQ_STATUS_VPA_OC,
	30	MT6328_IRQ_STATUS_LDO_OC,
	31	MT6328_IRQ_STATUS_BAT2_H,
	32	MT6328_IRQ_STATUS_BAT2_L,
	33	MT6328_IRQ_STATUS_VISMPS0_H,
	34	MT6328_IRQ_STATUS_VISMPS0_L,
	35	MT6328_IRQ_STATUS_AUXADC_IMP,
	36	MT6328_IRQ_STATUS_OV = 32,
	37	MT6328_IRQ_STATUS_BVALID_DET,
	38	MT6328_IRQ_STATUS_VBATON_HV,
	39	MT6328_IRQ_STATUS_VBATON_UNDET,
	40	MT6328_IRQ_STATUS_WATCHDOG,
	41	MT6328_IRQ_STATUS_PCHR_CM_VDEC,
	42	MT6328_IRQ_STATUS_CHRDET,
	43	MT6328_IRQ_STATUS_PCHR_CM_VINC,
	44	MT6328_IRQ_STATUS_FG_BAT_H,
	45	MT6328_IRQ_STATUS_FG_BAT_L,
	46	MT6328_IRQ_STATUS_FG_CUR_H,
	47	MT6328_IRQ_STATUS_FG_CUR_L,
	48	MT6328_IRQ_STATUS_FG_ZCV,
	49	MT6328_IRQ_STATUS_SPKL_D,
	50	MT6328_IRQ_STATUS_SPKL_AB,
	51	};
	52
	53	#endif /* __MFD_MT6323_CORE_H__ */

include/linux/mfd/mt6328/registers.h+822−0

@@ -0,0 +1,822 @@
	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
	4	*/
	5
	6	#ifndef __MFD_MT6328_REGISTERS_H__
	7	#define __MFD_MT6328_REGISTERS_H__
	8
	9	/* PMIC Registers */
	10	#define MT6328_STRUP_CON0 0x0000
	11	#define MT6328_STRUP_CON2 0x0002
	12	#define MT6328_STRUP_CON3 0x0004
	13	#define MT6328_STRUP_CON4 0x0006
	14	#define MT6328_STRUP_CON5 0x0008
	15	#define MT6328_STRUP_CON6 0x000a
	16	#define MT6328_STRUP_CON7 0x000c
	17	#define MT6328_STRUP_CON8 0x000e
	18	#define MT6328_STRUP_CON9 0x0010
	19	#define MT6328_STRUP_CON10 0x0012
	20	#define MT6328_STRUP_CON11 0x0014
	21	#define MT6328_STRUP_CON12 0x0016
	22	#define MT6328_STRUP_CON13 0x0018
	23	#define MT6328_STRUP_CON14 0x001a
	24	#define MT6328_STRUP_CON15 0x001c
	25	#define MT6328_STRUP_CON16 0x001e
	26	#define MT6328_STRUP_CON17 0x0020
	27	#define MT6328_STRUP_CON18 0x0022
	28	#define MT6328_STRUP_CON19 0x0024
	29	#define MT6328_STRUP_CON20 0x0026
	30	#define MT6328_STRUP_CON21 0x0028
	31	#define MT6328_STRUP_CON22 0x002a
	32	#define MT6328_STRUP_CON23 0x002c
	33	#define MT6328_STRUP_CON24 0x002e
	34	#define MT6328_STRUP_CON25 0x0030
	35	#define MT6328_STRUP_CON26 0x0032
	36	#define MT6328_STRUP_CON27 0x0034
	37	#define MT6328_STRUP_CON28 0x0036
	38	#define MT6328_STRUP_CON29 0x0038
	39	#define MT6328_STRUP_CON30 0x003a
	40	#define MT6328_STRUP_CON31 0x003c
	41	#define MT6328_STRUP_CON32 0x003e
	42	#define MT6328_STRUP_ANA_CON0 0x0040
	43	#define MT6328_HWCID 0x0200
	44	#define MT6328_SWCID 0x0202
	45	#define MT6328_TOP_CON 0x0204
	46	#define MT6328_TEST_OUT 0x0206
	47	#define MT6328_TEST_CON0 0x0208
	48	#define MT6328_TEST_CON1 0x020a
	49	#define MT6328_TESTMODE_SW 0x020c
	50	#define MT6328_EN_STATUS0 0x020e
	51	#define MT6328_EN_STATUS1 0x0210
	52	#define MT6328_EN_STATUS2 0x0212
	53	#define MT6328_OCSTATUS0 0x0214
	54	#define MT6328_OCSTATUS1 0x0216
	55	#define MT6328_OCSTATUS2 0x0218
	56	#define MT6328_PGDEBSTATUS 0x021a
	57	#define MT6328_PGSTATUS 0x021c
	58	#define MT6328_THERMALSTATUS 0x021e
	59	#define MT6328_TOPSTATUS 0x0220
	60	#define MT6328_TDSEL_CON 0x0222
	61	#define MT6328_RDSEL_CON 0x0224
	62	#define MT6328_SMT_CON0 0x0226
	63	#define MT6328_SMT_CON1 0x0228
	64	#define MT6328_SMT_CON2 0x022a
	65	#define MT6328_DRV_CON0 0x022c
	66	#define MT6328_DRV_CON1 0x022e
	67	#define MT6328_DRV_CON2 0x0230
	68	#define MT6328_DRV_CON3 0x0232
	69	#define MT6328_TOP_STATUS 0x0234
	70	#define MT6328_TOP_STATUS_SET 0x0236
	71	#define MT6328_TOP_STATUS_CLR 0x0238
	72	#define MT6328_RGS_ANA_MON 0x023a
	73	#define MT6328_TOP_CKPDN_CON0 0x023c
	74	#define MT6328_TOP_CKPDN_CON0_SET 0x023e
	75	#define MT6328_TOP_CKPDN_CON0_CLR 0x0240
	76	#define MT6328_TOP_CKPDN_CON1 0x0242
	77	#define MT6328_TOP_CKPDN_CON1_SET 0x0244
	78	#define MT6328_TOP_CKPDN_CON1_CLR 0x0246
	79	#define MT6328_TOP_CKPDN_CON2 0x0248
	80	#define MT6328_TOP_CKPDN_CON2_SET 0x024a
	81	#define MT6328_TOP_CKPDN_CON2_CLR 0x024c
	82	#define MT6328_TOP_CKPDN_CON3 0x024e
	83	#define MT6328_TOP_CKPDN_CON3_SET 0x0250
	84	#define MT6328_TOP_CKPDN_CON3_CLR 0x0252
	85	#define MT6328_TOP_CKPDN_CON4 0x0254
	86	#define MT6328_TOP_CKPDN_CON4_SET 0x0256
	87	#define MT6328_TOP_CKPDN_CON4_CLR 0x0258
	88	#define MT6328_TOP_CKSEL_CON0 0x025a
	89	#define MT6328_TOP_CKSEL_CON0_SET 0x025c
	90	#define MT6328_TOP_CKSEL_CON0_CLR 0x025e
	91	#define MT6328_TOP_CKSEL_CON1 0x0260
	92	#define MT6328_TOP_CKSEL_CON1_SET 0x0262
	93	#define MT6328_TOP_CKSEL_CON1_CLR 0x0264
	94	#define MT6328_TOP_CKSEL_CON2 0x0266
	95	#define MT6328_TOP_CKSEL_CON2_SET 0x0268
	96	#define MT6328_TOP_CKSEL_CON2_CLR 0x026a
	97	#define MT6328_TOP_CKDIVSEL_CON0 0x026c
	98	#define MT6328_TOP_CKDIVSEL_CON0_SET 0x026e
	99	#define MT6328_TOP_CKDIVSEL_CON0_CLR 0x0270
	100	#define MT6328_TOP_CKDIVSEL_CON1 0x0272
	101	#define MT6328_TOP_CKDIVSEL_CON1_SET 0x0274
	102	#define MT6328_TOP_CKDIVSEL_CON1_CLR 0x0276
	103	#define MT6328_TOP_CKHWEN_CON0 0x0278
	104	#define MT6328_TOP_CKHWEN_CON0_SET 0x027a
	105	#define MT6328_TOP_CKHWEN_CON0_CLR 0x027c
	106	#define MT6328_TOP_CKHWEN_CON1 0x027e
	107	#define MT6328_TOP_CKHWEN_CON1_SET 0x0280
	108	#define MT6328_TOP_CKHWEN_CON1_CLR 0x0282
	109	#define MT6328_TOP_CKTST_CON0 0x0284
	110	#define MT6328_TOP_CKTST_CON1 0x0286
	111	#define MT6328_TOP_CKTST_CON2 0x0288
	112	#define MT6328_TOP_CLKSQ 0x028a
	113	#define MT6328_TOP_CLKSQ_SET 0x028c
	114	#define MT6328_TOP_CLKSQ_CLR 0x028e
	115	#define MT6328_TOP_CLKSQ_RTC 0x0290
	116	#define MT6328_TOP_CLKSQ_RTC_SET 0x0292
	117	#define MT6328_TOP_CLKSQ_RTC_CLR 0x0294
	118	#define MT6328_TOP_CLK_TRIM 0x0296
	119	#define MT6328_TOP_RST_CON0 0x0298
	120	#define MT6328_TOP_RST_CON0_SET 0x029a
	121	#define MT6328_TOP_RST_CON0_CLR 0x029c
	122	#define MT6328_TOP_RST_CON1 0x029e
	123	#define MT6328_TOP_RST_MISC 0x02a0
	124	#define MT6328_TOP_RST_MISC_SET 0x02a2
	125	#define MT6328_TOP_RST_MISC_CLR 0x02a4
	126	#define MT6328_TOP_RST_STATUS 0x02a6
	127	#define MT6328_TOP_RST_STATUS_SET 0x02a8
	128	#define MT6328_TOP_RST_STATUS_CLR 0x02aa
	129	#define MT6328_INT_CON0 0x02ac
	130	#define MT6328_INT_CON0_SET 0x02ae
	131	#define MT6328_INT_CON0_CLR 0x02b0
	132	#define MT6328_INT_CON1 0x02b2
	133	#define MT6328_INT_CON1_SET 0x02b4
	134	#define MT6328_INT_CON1_CLR 0x02b6
	135	#define MT6328_INT_CON2 0x02b8
	136	#define MT6328_INT_CON2_SET 0x02ba
	137	#define MT6328_INT_CON2_CLR 0x02bc
	138	#define MT6328_INT_MISC_CON 0x02be
	139	#define MT6328_INT_MISC_CON_SET 0x02c0
	140	#define MT6328_INT_MISC_CON_CLR 0x02c2
	141	#define MT6328_INT_STATUS0 0x02c4
	142	#define MT6328_INT_STATUS1 0x02c6
	143	#define MT6328_INT_STATUS2 0x02c8
	144	#define MT6328_OC_GEAR_0 0x02ca
	145	#define MT6328_FQMTR_CON0 0x02cc
	146	#define MT6328_FQMTR_CON1 0x02ce
	147	#define MT6328_FQMTR_CON2 0x02d0
	148	#define MT6328_RG_SPI_CON 0x02d2
	149	#define MT6328_DEW_DIO_EN 0x02d4
	150	#define MT6328_DEW_READ_TEST 0x02d6
	151	#define MT6328_DEW_WRITE_TEST 0x02d8
	152	#define MT6328_DEW_CRC_SWRST 0x02da
	153	#define MT6328_DEW_CRC_EN 0x02dc
	154	#define MT6328_DEW_CRC_VAL 0x02de
	155	#define MT6328_DEW_DBG_MON_SEL 0x02e0
	156	#define MT6328_DEW_CIPHER_KEY_SEL 0x02e2
	157	#define MT6328_DEW_CIPHER_IV_SEL 0x02e4
	158	#define MT6328_DEW_CIPHER_EN 0x02e6
	159	#define MT6328_DEW_CIPHER_RDY 0x02e8
	160	#define MT6328_DEW_CIPHER_MODE 0x02ea
	161	#define MT6328_DEW_CIPHER_SWRST 0x02ec
	162	#define MT6328_DEW_RDDMY_NO 0x02ee
	163	#define MT6328_INT_TYPE_CON0 0x02f0
	164	#define MT6328_INT_TYPE_CON0_SET 0x02f2
	165	#define MT6328_INT_TYPE_CON0_CLR 0x02f4
	166	#define MT6328_INT_TYPE_CON1 0x02f6
	167	#define MT6328_INT_TYPE_CON1_SET 0x02f8
	168	#define MT6328_INT_TYPE_CON1_CLR 0x02fa
	169	#define MT6328_INT_TYPE_CON2 0x02fc
	170	#define MT6328_INT_TYPE_CON2_SET 0x02fe
	171	#define MT6328_INT_TYPE_CON2_CLR 0x0300
	172	#define MT6328_INT_STA 0x0302
	173	#define MT6328_BUCK_ALL_CON0 0x0400
	174	#define MT6328_BUCK_ALL_CON1 0x0402
	175	#define MT6328_BUCK_ALL_CON2 0x0404
	176	#define MT6328_BUCK_ALL_CON3 0x0406
	177	#define MT6328_BUCK_ALL_CON4 0x0408
	178	#define MT6328_BUCK_ALL_CON5 0x040a
	179	#define MT6328_BUCK_ALL_CON6 0x040c
	180	#define MT6328_BUCK_ALL_CON9 0x040e
	181	#define MT6328_BUCK_ALL_CON12 0x0410
	182	#define MT6328_BUCK_ALL_CON13 0x0412
	183	#define MT6328_BUCK_ALL_CON14 0x0414
	184	#define MT6328_BUCK_ALL_CON16 0x0416
	185	#define MT6328_BUCK_ALL_CON18 0x0418
	186	#define MT6328_BUCK_ALL_CON19 0x041a
	187	#define MT6328_BUCK_ALL_CON20 0x041c
	188	#define MT6328_BUCK_ALL_CON21 0x041e
	189	#define MT6328_BUCK_ALL_CON22 0x0420
	190	#define MT6328_BUCK_ALL_CON23 0x0422
	191	#define MT6328_BUCK_ALL_CON24 0x0424
	192	#define MT6328_BUCK_ALL_CON25 0x0426
	193	#define MT6328_BUCK_ALL_CON26 0x0428
	194	#define MT6328_BUCK_ALL_CON27 0x042a
	195	#define MT6328_BUCK_ALL_CON28 0x042c
	196	#define MT6328_SMPS_TOP_ANA_CON0 0x042e
	197	#define MT6328_SMPS_TOP_ANA_CON1 0x0430
	198	#define MT6328_SMPS_TOP_ANA_CON2 0x0432
	199	#define MT6328_SMPS_TOP_ANA_CON3 0x0434
	200	#define MT6328_SMPS_TOP_ANA_CON4 0x0436
	201	#define MT6328_SMPS_TOP_ANA_CON5 0x0438
	202	#define MT6328_SMPS_TOP_ANA_CON6 0x043a
	203	#define MT6328_SMPS_TOP_ANA_CON7 0x043c
	204	#define MT6328_SMPS_TOP_ANA_CON8 0x043e
	205	#define MT6328_VCORE_ANA_CON0 0x0440
	206	#define MT6328_VCORE_ANA_CON1 0x0442
	207	#define MT6328_VCORE_ANA_CON2 0x0444
	208	#define MT6328_VCORE_ANA_CON3 0x0446
	209	#define MT6328_VCORE_ANA_CON4 0x0448
	210	#define MT6328_VSYS22_ANA_CON0 0x044a
	211	#define MT6328_VSYS22_ANA_CON1 0x044c
	212	#define MT6328_VSYS22_ANA_CON2 0x044e
	213	#define MT6328_VSYS22_ANA_CON3 0x0450
	214	#define MT6328_VSYS22_ANA_CON4 0x0452
	215	#define MT6328_VPROC_ANA_CON0 0x0454
	216	#define MT6328_VPROC_ANA_CON1 0x0456
	217	#define MT6328_VPROC_ANA_CON2 0x0458
	218	#define MT6328_VPROC_ANA_CON3 0x045a
	219	#define MT6328_VPROC_ANA_CON4 0x045c
	220	#define MT6328_OSC32_ANA_CON0 0x045e
	221	#define MT6328_OSC32_ANA_CON1 0x0460
	222	#define MT6328_VPA_ANA_CON0 0x0462
	223	#define MT6328_VPA_ANA_CON1 0x0464
	224	#define MT6328_VPA_ANA_CON2 0x0466
	225	#define MT6328_VPA_ANA_CON3 0x0468
	226	#define MT6328_VLTE_ANA_CON0 0x046a
	227	#define MT6328_VLTE_ANA_CON1 0x046c
	228	#define MT6328_VLTE_ANA_CON2 0x046e
	229	#define MT6328_VLTE_ANA_CON3 0x0470
	230	#define MT6328_VLTE_ANA_CON4 0x0472
	231	#define MT6328_VPROC_CON0 0x0474
	232	#define MT6328_VPROC_CON1 0x0476
	233	#define MT6328_VPROC_CON2 0x0478
	234	#define MT6328_VPROC_CON3 0x047a
	235	#define MT6328_VPROC_CON4 0x047c
	236	#define MT6328_VPROC_CON5 0x047e
	237	#define MT6328_VPROC_CON6 0x0480
	238	#define MT6328_VPROC_CON7 0x0482
	239	#define MT6328_VPROC_CON8 0x0484
	240	#define MT6328_VPROC_CON9 0x0486
	241	#define MT6328_VPROC_CON10 0x0488
	242	#define MT6328_VPROC_CON11 0x048a
	243	#define MT6328_VPROC_CON12 0x048c
	244	#define MT6328_VPROC_CON13 0x048e
	245	#define MT6328_VPROC_CON14 0x0490
	246	#define MT6328_VPROC_CON15 0x0492
	247	#define MT6328_VPROC_CON16 0x0494
	248	#define MT6328_VPROC_CON17 0x0496
	249	#define MT6328_VPROC_CON18 0x0498
	250	#define MT6328_VPROC_CON19 0x049a
	251	#define MT6328_VSRAM_CON0 0x049c
	252	#define MT6328_VSRAM_CON1 0x049e
	253	#define MT6328_VSRAM_CON2 0x04a0
	254	#define MT6328_VSRAM_CON3 0x04a2
	255	#define MT6328_VSRAM_CON4 0x04a4
	256	#define MT6328_VSRAM_CON5 0x04a6
	257	#define MT6328_VSRAM_CON6 0x04a8
	258	#define MT6328_VSRAM_CON7 0x04aa
	259	#define MT6328_VSRAM_CON8 0x04ac
	260	#define MT6328_VSRAM_CON9 0x04ae
	261	#define MT6328_VSRAM_CON10 0x04b0
	262	#define MT6328_VSRAM_CON11 0x04b2
	263	#define MT6328_VSRAM_CON12 0x04b4
	264	#define MT6328_VSRAM_CON13 0x04b6
	265	#define MT6328_VSRAM_CON14 0x04b8
	266	#define MT6328_VSRAM_CON15 0x04ba
	267	#define MT6328_VSRAM_CON16 0x04bc
	268	#define MT6328_VSRAM_CON17 0x04be
	269	#define MT6328_VSRAM_CON18 0x04c0
	270	#define MT6328_VSRAM_CON19 0x04c2
	271	#define MT6328_VLTE_CON0 0x04c4
	272	#define MT6328_VLTE_CON1 0x04c6
	273	#define MT6328_VLTE_CON2 0x04c8
	274	#define MT6328_VLTE_CON3 0x04ca
	275	#define MT6328_VLTE_CON4 0x04cc
	276	#define MT6328_VLTE_CON5 0x04ce
	277	#define MT6328_VLTE_CON6 0x04d0
	278	#define MT6328_VLTE_CON7 0x04d2
	279	#define MT6328_VLTE_CON8 0x04d4
	280	#define MT6328_VLTE_CON9 0x04d6
	281	#define MT6328_VLTE_CON10 0x04d8
	282	#define MT6328_VLTE_CON11 0x04da
	283	#define MT6328_VLTE_CON12 0x04dc
	284	#define MT6328_VLTE_CON13 0x04de
	285	#define MT6328_VLTE_CON14 0x04e0
	286	#define MT6328_VLTE_CON15 0x04e2
	287	#define MT6328_VLTE_CON16 0x04e4
	288	#define MT6328_VLTE_CON17 0x04e6
	289	#define MT6328_VLTE_CON18 0x04e8
	290	#define MT6328_VLTE_CON19 0x04ea
	291	#define MT6328_VCORE1_CON0 0x0600
	292	#define MT6328_VCORE1_CON1 0x0602
	293	#define MT6328_VCORE1_CON2 0x0604
	294	#define MT6328_VCORE1_CON3 0x0606
	295	#define MT6328_VCORE1_CON4 0x0608
	296	#define MT6328_VCORE1_CON5 0x060a
	297	#define MT6328_VCORE1_CON6 0x060c
	298	#define MT6328_VCORE1_CON7 0x060e
	299	#define MT6328_VCORE1_CON8 0x0610
	300	#define MT6328_VCORE1_CON9 0x0612
	301	#define MT6328_VCORE1_CON10 0x0614
	302	#define MT6328_VCORE1_CON11 0x0616
	303	#define MT6328_VCORE1_CON12 0x0618
	304	#define MT6328_VCORE1_CON13 0x061a
	305	#define MT6328_VCORE1_CON14 0x061c
	306	#define MT6328_VCORE1_CON15 0x061e
	307	#define MT6328_VCORE1_CON16 0x0620
	308	#define MT6328_VCORE1_CON17 0x0622
	309	#define MT6328_VCORE1_CON18 0x0624
	310	#define MT6328_VCORE1_CON19 0x0626
	311	#define MT6328_VSYS22_CON0 0x0628
	312	#define MT6328_VSYS22_CON1 0x062a
	313	#define MT6328_VSYS22_CON2 0x062c
	314	#define MT6328_VSYS22_CON3 0x062e
	315	#define MT6328_VSYS22_CON4 0x0630
	316	#define MT6328_VSYS22_CON5 0x0632
	317	#define MT6328_VSYS22_CON6 0x0634
	318	#define MT6328_VSYS22_CON7 0x0636
	319	#define MT6328_VSYS22_CON8 0x0638
	320	#define MT6328_VSYS22_CON9 0x063a
	321	#define MT6328_VSYS22_CON10 0x063c
	322	#define MT6328_VSYS22_CON11 0x063e
	323	#define MT6328_VSYS22_CON12 0x0640
	324	#define MT6328_VSYS22_CON13 0x0642
	325	#define MT6328_VSYS22_CON14 0x0644
	326	#define MT6328_VSYS22_CON15 0x0646
	327	#define MT6328_VSYS22_CON16 0x0648
	328	#define MT6328_VSYS22_CON17 0x064a
	329	#define MT6328_VSYS22_CON18 0x064c
	330	#define MT6328_VSYS22_CON19 0x064e
	331	#define MT6328_VPA_CON0 0x0650
	332	#define MT6328_VPA_CON1 0x0652
	333	#define MT6328_VPA_CON2 0x0654
	334	#define MT6328_VPA_CON3 0x0656
	335	#define MT6328_VPA_CON4 0x0658
	336	#define MT6328_VPA_CON5 0x065a
	337	#define MT6328_VPA_CON6 0x065c
	338	#define MT6328_VPA_CON7 0x065e
	339	#define MT6328_VPA_CON8 0x0660
	340	#define MT6328_VPA_CON9 0x0662
	341	#define MT6328_VPA_CON10 0x0664
	342	#define MT6328_VPA_CON11 0x0666
	343	#define MT6328_VPA_CON12 0x0668
	344	#define MT6328_VPA_CON13 0x066a
	345	#define MT6328_VPA_CON14 0x066c
	346	#define MT6328_VPA_CON15 0x066e
	347	#define MT6328_VPA_CON16 0x0670
	348	#define MT6328_VPA_CON17 0x0672
	349	#define MT6328_VPA_CON18 0x0674
	350	#define MT6328_VPA_CON19 0x0676
	351	#define MT6328_VPA_CON20 0x0678
	352	#define MT6328_VPA_CON21 0x067a
	353	#define MT6328_VPA_CON22 0x067c
	354	#define MT6328_VPA_CON23 0x067e
	355	#define MT6328_VPA_CON24 0x0680
	356	#define MT6328_BUCK_K_CON0 0x0682
	357	#define MT6328_BUCK_K_CON1 0x0684
	358	#define MT6328_BUCK_K_CON2 0x0686
	359	#define MT6328_BUCK_K_CON3 0x0688
	360	#define MT6328_ZCD_CON0 0x0800
	361	#define MT6328_ZCD_CON1 0x0802
	362	#define MT6328_ZCD_CON2 0x0804
	363	#define MT6328_ZCD_CON3 0x0806
	364	#define MT6328_ZCD_CON4 0x0808
	365	#define MT6328_ZCD_CON5 0x080a
	366	#define MT6328_ISINK0_CON0 0x080c
	367	#define MT6328_ISINK0_CON1 0x080e
	368	#define MT6328_ISINK0_CON2 0x0810
	369	#define MT6328_ISINK0_CON3 0x0812
	370	#define MT6328_ISINK1_CON0 0x0814
	371	#define MT6328_ISINK1_CON1 0x0816
	372	#define MT6328_ISINK1_CON2 0x0818
	373	#define MT6328_ISINK1_CON3 0x081a
	374	#define MT6328_ISINK2_CON1 0x081c
	375	#define MT6328_ISINK3_CON1 0x081e
	376	#define MT6328_ISINK_ANA0 0x0820
	377	#define MT6328_ISINK_ANA1 0x0822
	378	#define MT6328_ISINK_PHASE_DLY 0x0824
	379	#define MT6328_ISINK_SFSTR 0x0826
	380	#define MT6328_ISINK_EN_CTRL 0x0828
	381	#define MT6328_ISINK_MODE_CTRL 0x082a
	382	#define MT6328_VTCXO_0_CON0 0x0a00
	383	#define MT6328_VTCXO_1_CON0 0x0a02
	384	#define MT6328_VAUD28_CON0 0x0a04
	385	#define MT6328_VAUX18_CON0 0x0a06
	386	#define MT6328_VRF18_0_CON0 0x0a08
	387	#define MT6328_VRF18_0_CON1 0x0a0a
	388	#define MT6328_VCAMA_CON0 0x0a0c
	389	#define MT6328_VCN28_CON0 0x0a0e
	390	#define MT6328_VCN33_CON0 0x0a10
	391	#define MT6328_VCN33_CON1 0x0a12
	392	#define MT6328_VCN33_CON2 0x0a14
	393	#define MT6328_VRF18_1_CON0 0x0a16
	394	#define MT6328_VRF18_1_CON1 0x0a18
	395	#define MT6328_VUSB33_CON0 0x0a1a
	396	#define MT6328_VMCH_CON0 0x0a1c
	397	#define MT6328_VMCH_CON1 0x0a1e
	398	#define MT6328_VMC_CON0 0x0a20
	399	#define MT6328_VMC_CON1 0x0a22
	400	#define MT6328_VEMC_3V3_CON0 0x0a24
	401	#define MT6328_VEMC_3V3_CON1 0x0a26
	402	#define MT6328_VIO28_CON0 0x0a28
	403	#define MT6328_VCAMAF_CON0 0x0a2a
	404	#define MT6328_VGP1_CON0 0x0a2c
	405	#define MT6328_VGP1_CON1 0x0a2e
	406	#define MT6328_VEFUSE_CON0 0x0a30
	407	#define MT6328_VSIM1_CON0 0x0a32
	408	#define MT6328_VSIM2_CON0 0x0a34
	409	#define MT6328_VIO18_CON0 0x0a36
	410	#define MT6328_VIBR_CON0 0x0a38
	411	#define MT6328_VCN18_CON0 0x0a3a
	412	#define MT6328_VCAM_CON0 0x0a3c
	413	#define MT6328_VCAMIO_CON0 0x0a3e
	414	#define MT6328_LDO_VSRAM_CON0 0x0a40
	415	#define MT6328_LDO_VSRAM_CON1 0x0a42
	416	#define MT6328_VTREF_CON0 0x0a44
	417	#define MT6328_VM_CON0 0x0a46
	418	#define MT6328_VM_CON1 0x0a48
	419	#define MT6328_VRTC_CON0 0x0a4a
	420	#define MT6328_LDO_OCFB0 0x0a4c
	421	#define MT6328_ALDO_ANA_CON0 0x0a4e
	422	#define MT6328_ADLDO_ANA_CON1 0x0a50
	423	#define MT6328_ADLDO_ANA_CON2 0x0a52
	424	#define MT6328_ADLDO_ANA_CON3 0x0a54
	425	#define MT6328_ADLDO_ANA_CON4 0x0a56
	426	#define MT6328_ADLDO_ANA_CON5 0x0a58
	427	#define MT6328_ADLDO_ANA_CON6 0x0a5a
	428	#define MT6328_ADLDO_ANA_CON7 0x0a5c
	429	#define MT6328_ADLDO_ANA_CON8 0x0a5e
	430	#define MT6328_ADLDO_ANA_CON9 0x0a60
	431	#define MT6328_ADLDO_ANA_CON10 0x0a62
	432	#define MT6328_ADLDO_ANA_CON11 0x0a64
	433	#define MT6328_ADLDO_ANA_CON12 0x0a66
	434	#define MT6328_ADLDO_ANA_CON13 0x0a68
	435	#define MT6328_DLDO_ANA_CON0 0x0a6a
	436	#define MT6328_DLDO_ANA_CON1 0x0a6c
	437	#define MT6328_DLDO_ANA_CON2 0x0a6e
	438	#define MT6328_DLDO_ANA_CON3 0x0a70
	439	#define MT6328_DLDO_ANA_CON4 0x0a72
	440	#define MT6328_DLDO_ANA_CON5 0x0a74
	441	#define MT6328_SLDO_ANA_CON0 0x0a76
	442	#define MT6328_SLDO_ANA_CON1 0x0a78
	443	#define MT6328_SLDO_ANA_CON2 0x0a7a
	444	#define MT6328_SLDO_ANA_CON3 0x0a7c
	445	#define MT6328_SLDO_ANA_CON4 0x0a7e
	446	#define MT6328_SLDO_ANA_CON5 0x0a80
	447	#define MT6328_SLDO_ANA_CON6 0x0a82
	448	#define MT6328_SLDO_ANA_CON7 0x0a84
	449	#define MT6328_SLDO_ANA_CON8 0x0a86
	450	#define MT6328_SLDO_ANA_CON9 0x0a88
	451	#define MT6328_SLDO_ANA_CON10 0x0a8a
	452	#define MT6328_LDO_RSV_CON0 0x0a8c
	453	#define MT6328_LDO_RSV_CON1 0x0a8e
	454	#define MT6328_SPK_CON0 0x0a90
	455	#define MT6328_SPK_CON1 0x0a92
	456	#define MT6328_SPK_CON2 0x0a94
	457	#define MT6328_SPK_CON3 0x0a96
	458	#define MT6328_SPK_CON4 0x0a98
	459	#define MT6328_SPK_CON5 0x0a9a
	460	#define MT6328_SPK_CON6 0x0a9c
	461	#define MT6328_SPK_CON7 0x0a9e
	462	#define MT6328_SPK_CON8 0x0aa0
	463	#define MT6328_SPK_CON9 0x0aa2
	464	#define MT6328_SPK_CON10 0x0aa4
	465	#define MT6328_SPK_CON11 0x0aa6
	466	#define MT6328_SPK_CON12 0x0aa8
	467	#define MT6328_SPK_CON13 0x0aaa
	468	#define MT6328_SPK_CON14 0x0aac
	469	#define MT6328_SPK_CON15 0x0aae
	470	#define MT6328_SPK_CON16 0x0ab0
	471	#define MT6328_SPK_ANA_CON0 0x0ab2
	472	#define MT6328_SPK_ANA_CON1 0x0ab4
	473	#define MT6328_SPK_ANA_CON3 0x0ab6
	474	#define MT6328_OTP_CON0 0x0c00
	475	#define MT6328_OTP_CON1 0x0c02
	476	#define MT6328_OTP_CON2 0x0c04
	477	#define MT6328_OTP_CON3 0x0c06
	478	#define MT6328_OTP_CON4 0x0c08
	479	#define MT6328_OTP_CON5 0x0c0a
	480	#define MT6328_OTP_CON6 0x0c0c
	481	#define MT6328_OTP_CON7 0x0c0e
	482	#define MT6328_OTP_CON8 0x0c10
	483	#define MT6328_OTP_CON9 0x0c12
	484	#define MT6328_OTP_CON10 0x0c14
	485	#define MT6328_OTP_CON11 0x0c16
	486	#define MT6328_OTP_CON12 0x0c18
	487	#define MT6328_OTP_CON13 0x0c1a
	488	#define MT6328_OTP_CON14 0x0c1c
	489	#define MT6328_OTP_DOUT_0_15 0x0c1e
	490	#define MT6328_OTP_DOUT_16_31 0x0c20
	491	#define MT6328_OTP_DOUT_32_47 0x0c22
	492	#define MT6328_OTP_DOUT_48_63 0x0c24
	493	#define MT6328_OTP_DOUT_64_79 0x0c26
	494	#define MT6328_OTP_DOUT_80_95 0x0c28
	495	#define MT6328_OTP_DOUT_96_111 0x0c2a
	496	#define MT6328_OTP_DOUT_112_127 0x0c2c
	497	#define MT6328_OTP_DOUT_128_143 0x0c2e
	498	#define MT6328_OTP_DOUT_144_159 0x0c30
	499	#define MT6328_OTP_DOUT_160_175 0x0c32
	500	#define MT6328_OTP_DOUT_176_191 0x0c34
	501	#define MT6328_OTP_DOUT_192_207 0x0c36
	502	#define MT6328_OTP_DOUT_208_223 0x0c38
	503	#define MT6328_OTP_DOUT_224_239 0x0c3a
	504	#define MT6328_OTP_DOUT_240_255 0x0c3c
	505	#define MT6328_OTP_DOUT_256_271 0x0c3e
	506	#define MT6328_OTP_DOUT_272_287 0x0c40
	507	#define MT6328_OTP_DOUT_288_303 0x0c42
	508	#define MT6328_OTP_DOUT_304_319 0x0c44
	509	#define MT6328_OTP_DOUT_320_335 0x0c46
	510	#define MT6328_OTP_DOUT_336_351 0x0c48
	511	#define MT6328_OTP_DOUT_352_367 0x0c4a
	512	#define MT6328_OTP_DOUT_368_383 0x0c4c
	513	#define MT6328_OTP_DOUT_384_399 0x0c4e
	514	#define MT6328_OTP_DOUT_400_415 0x0c50
	515	#define MT6328_OTP_DOUT_416_431 0x0c52
	516	#define MT6328_OTP_DOUT_432_447 0x0c54
	517	#define MT6328_OTP_DOUT_448_463 0x0c56
	518	#define MT6328_OTP_DOUT_464_479 0x0c58
	519	#define MT6328_OTP_DOUT_480_495 0x0c5a
	520	#define MT6328_OTP_DOUT_496_511 0x0c5c
	521	#define MT6328_OTP_VAL_0_15 0x0c5e
	522	#define MT6328_OTP_VAL_16_31 0x0c60
	523	#define MT6328_OTP_VAL_32_47 0x0c62
	524	#define MT6328_OTP_VAL_48_63 0x0c64
	525	#define MT6328_OTP_VAL_64_79 0x0c66
	526	#define MT6328_OTP_VAL_80_95 0x0c68
	527	#define MT6328_OTP_VAL_96_111 0x0c6a
	528	#define MT6328_OTP_VAL_112_127 0x0c6c
	529	#define MT6328_OTP_VAL_128_143 0x0c6e
	530	#define MT6328_OTP_VAL_144_159 0x0c70
	531	#define MT6328_OTP_VAL_160_175 0x0c72
	532	#define MT6328_OTP_VAL_176_191 0x0c74
	533	#define MT6328_OTP_VAL_192_207 0x0c76
	534	#define MT6328_OTP_VAL_208_223 0x0c78
	535	#define MT6328_OTP_VAL_224_239 0x0c7a
	536	#define MT6328_OTP_VAL_240_255 0x0c7c
	537	#define MT6328_OTP_VAL_256_271 0x0c7e
	538	#define MT6328_OTP_VAL_272_287 0x0c80
	539	#define MT6328_OTP_VAL_288_303 0x0c82
	540	#define MT6328_OTP_VAL_304_319 0x0c84
	541	#define MT6328_OTP_VAL_320_335 0x0c86
	542	#define MT6328_OTP_VAL_336_351 0x0c88
	543	#define MT6328_OTP_VAL_352_367 0x0c8a
	544	#define MT6328_OTP_VAL_368_383 0x0c8c
	545	#define MT6328_OTP_VAL_384_399 0x0c8e
	546	#define MT6328_OTP_VAL_400_415 0x0c90
	547	#define MT6328_OTP_VAL_416_431 0x0c92
	548	#define MT6328_OTP_VAL_432_447 0x0c94
	549	#define MT6328_OTP_VAL_448_463 0x0c96
	550	#define MT6328_OTP_VAL_464_479 0x0c98
	551	#define MT6328_OTP_VAL_480_495 0x0c9a
	552	#define MT6328_OTP_VAL_496_511 0x0c9c
	553	#define MT6328_RTC_MIX_CON0 0x0c9e
	554	#define MT6328_RTC_MIX_CON1 0x0ca0
	555	#define MT6328_RTC_MIX_CON2 0x0ca2
	556	#define MT6328_FGADC_CON0 0x0ca4
	557	#define MT6328_FGADC_CON1 0x0ca6
	558	#define MT6328_FGADC_CON2 0x0ca8
	559	#define MT6328_FGADC_CON3 0x0caa
	560	#define MT6328_FGADC_CON4 0x0cac
	561	#define MT6328_FGADC_CON5 0x0cae
	562	#define MT6328_FGADC_CON6 0x0cb0
	563	#define MT6328_FGADC_CON7 0x0cb2
	564	#define MT6328_FGADC_CON8 0x0cb4
	565	#define MT6328_FGADC_CON9 0x0cb6
	566	#define MT6328_FGADC_CON10 0x0cb8
	567	#define MT6328_FGADC_CON11 0x0cba
	568	#define MT6328_FGADC_CON12 0x0cbc
	569	#define MT6328_FGADC_CON13 0x0cbe
	570	#define MT6328_FGADC_CON14 0x0cc0
	571	#define MT6328_FGADC_CON15 0x0cc2
	572	#define MT6328_FGADC_CON16 0x0cc4
	573	#define MT6328_FGADC_CON17 0x0cc6
	574	#define MT6328_FGADC_CON18 0x0cc8
	575	#define MT6328_FGADC_CON19 0x0cca
	576	#define MT6328_FGADC_CON20 0x0ccc
	577	#define MT6328_FGADC_CON21 0x0cce
	578	#define MT6328_FGADC_CON22 0x0cd0
	579	#define MT6328_FGADC_CON23 0x0cd2
	580	#define MT6328_FGADC_CON24 0x0cd4
	581	#define MT6328_FGADC_CON25 0x0cd6
	582	#define MT6328_FGADC_CON26 0x0cd8
	583	#define MT6328_FGADC_CON27 0x0cda
	584	#define MT6328_AUDDEC_ANA_CON0 0x0cdc
	585	#define MT6328_AUDDEC_ANA_CON1 0x0cde
	586	#define MT6328_AUDDEC_ANA_CON2 0x0ce0
	587	#define MT6328_AUDDEC_ANA_CON3 0x0ce2
	588	#define MT6328_AUDDEC_ANA_CON4 0x0ce4
	589	#define MT6328_AUDDEC_ANA_CON5 0x0ce6
	590	#define MT6328_AUDDEC_ANA_CON6 0x0ce8
	591	#define MT6328_AUDDEC_ANA_CON7 0x0cea
	592	#define MT6328_AUDDEC_ANA_CON8 0x0cec
	593	#define MT6328_AUDENC_ANA_CON0 0x0cee
	594	#define MT6328_AUDENC_ANA_CON1 0x0cf0
	595	#define MT6328_AUDENC_ANA_CON2 0x0cf2
	596	#define MT6328_AUDENC_ANA_CON3 0x0cf4
	597	#define MT6328_AUDENC_ANA_CON4 0x0cf6
	598	#define MT6328_AUDENC_ANA_CON5 0x0cf8
	599	#define MT6328_AUDENC_ANA_CON6 0x0cfa
	600	#define MT6328_AUDENC_ANA_CON7 0x0cfc
	601	#define MT6328_AUDENC_ANA_CON8 0x0cfe
	602	#define MT6328_AUDENC_ANA_CON9 0x0d00
	603	#define MT6328_AUDENC_ANA_CON10 0x0d02
	604	#define MT6328_AUDNCP_CLKDIV_CON0 0x0d04
	605	#define MT6328_AUDNCP_CLKDIV_CON1 0x0d06
	606	#define MT6328_AUDNCP_CLKDIV_CON2 0x0d08
	607	#define MT6328_AUDNCP_CLKDIV_CON3 0x0d0a
	608	#define MT6328_AUDNCP_CLKDIV_CON4 0x0d0c
	609	#define MT6328_AUXADC_ADC0 0x0e00
	610	#define MT6328_AUXADC_ADC1 0x0e02
	611	#define MT6328_AUXADC_ADC2 0x0e04
	612	#define MT6328_AUXADC_ADC3 0x0e06
	613	#define MT6328_AUXADC_ADC4 0x0e08
	614	#define MT6328_AUXADC_ADC5 0x0e0a
	615	#define MT6328_AUXADC_ADC6 0x0e0c
	616	#define MT6328_AUXADC_ADC7 0x0e0e
	617	#define MT6328_AUXADC_ADC8 0x0e10
	618	#define MT6328_AUXADC_ADC9 0x0e12
	619	#define MT6328_AUXADC_ADC10 0x0e14
	620	#define MT6328_AUXADC_ADC11 0x0e16
	621	#define MT6328_AUXADC_ADC12 0x0e18
	622	#define MT6328_AUXADC_ADC13 0x0e1a
	623	#define MT6328_AUXADC_ADC14 0x0e1c
	624	#define MT6328_AUXADC_ADC15 0x0e1e
	625	#define MT6328_AUXADC_ADC16 0x0e20
	626	#define MT6328_AUXADC_ADC17 0x0e22
	627	#define MT6328_AUXADC_ADC18 0x0e24
	628	#define MT6328_AUXADC_ADC19 0x0e26
	629	#define MT6328_AUXADC_ADC20 0x0e28
	630	#define MT6328_AUXADC_ADC21 0x0e2a
	631	#define MT6328_AUXADC_ADC22 0x0e2c
	632	#define MT6328_AUXADC_ADC23 0x0e2e
	633	#define MT6328_AUXADC_ADC24 0x0e30
	634	#define MT6328_AUXADC_ADC25 0x0e32
	635	#define MT6328_AUXADC_ADC26 0x0e34
	636	#define MT6328_AUXADC_ADC27 0x0e36
	637	#define MT6328_AUXADC_ADC28 0x0e38
	638	#define MT6328_AUXADC_ADC29 0x0e3a
	639	#define MT6328_AUXADC_ADC30 0x0e3c
	640	#define MT6328_AUXADC_ADC31 0x0e3e
	641	#define MT6328_AUXADC_ADC32 0x0e40
	642	#define MT6328_AUXADC_ADC33 0x0e42
	643	#define MT6328_AUXADC_BUF0 0x0e44
	644	#define MT6328_AUXADC_BUF1 0x0e46
	645	#define MT6328_AUXADC_BUF2 0x0e48
	646	#define MT6328_AUXADC_BUF3 0x0e4a
	647	#define MT6328_AUXADC_BUF4 0x0e4c
	648	#define MT6328_AUXADC_BUF5 0x0e4e
	649	#define MT6328_AUXADC_BUF6 0x0e50
	650	#define MT6328_AUXADC_BUF7 0x0e52
	651	#define MT6328_AUXADC_BUF8 0x0e54
	652	#define MT6328_AUXADC_BUF9 0x0e56
	653	#define MT6328_AUXADC_BUF10 0x0e58
	654	#define MT6328_AUXADC_BUF11 0x0e5a
	655	#define MT6328_AUXADC_BUF12 0x0e5c
	656	#define MT6328_AUXADC_BUF13 0x0e5e
	657	#define MT6328_AUXADC_BUF14 0x0e60
	658	#define MT6328_AUXADC_BUF15 0x0e62
	659	#define MT6328_AUXADC_BUF16 0x0e64
	660	#define MT6328_AUXADC_BUF17 0x0e66
	661	#define MT6328_AUXADC_BUF18 0x0e68
	662	#define MT6328_AUXADC_BUF19 0x0e6a
	663	#define MT6328_AUXADC_BUF20 0x0e6c
	664	#define MT6328_AUXADC_BUF21 0x0e6e
	665	#define MT6328_AUXADC_BUF22 0x0e70
	666	#define MT6328_AUXADC_BUF23 0x0e72
	667	#define MT6328_AUXADC_BUF24 0x0e74
	668	#define MT6328_AUXADC_BUF25 0x0e76
	669	#define MT6328_AUXADC_BUF26 0x0e78
	670	#define MT6328_AUXADC_BUF27 0x0e7a
	671	#define MT6328_AUXADC_BUF28 0x0e7c
	672	#define MT6328_AUXADC_BUF29 0x0e7e
	673	#define MT6328_AUXADC_BUF30 0x0e80
	674	#define MT6328_AUXADC_BUF31 0x0e82
	675	#define MT6328_AUXADC_STA0 0x0e84
	676	#define MT6328_AUXADC_STA1 0x0e86
	677	#define MT6328_AUXADC_RQST0 0x0e88
	678	#define MT6328_AUXADC_RQST0_SET 0x0e8a
	679	#define MT6328_AUXADC_RQST0_CLR 0x0e8c
	680	#define MT6328_AUXADC_RQST1 0x0e8e
	681	#define MT6328_AUXADC_RQST1_SET 0x0e90
	682	#define MT6328_AUXADC_RQST1_CLR 0x0e92
	683	#define MT6328_AUXADC_CON0 0x0e94
	684	#define MT6328_AUXADC_CON0_SET 0x0e96
	685	#define MT6328_AUXADC_CON0_CLR 0x0e98
	686	#define MT6328_AUXADC_CON1 0x0e9a
	687	#define MT6328_AUXADC_CON2 0x0e9c
	688	#define MT6328_AUXADC_CON3 0x0e9e
	689	#define MT6328_AUXADC_CON4 0x0ea0
	690	#define MT6328_AUXADC_CON5 0x0ea2
	691	#define MT6328_AUXADC_CON6 0x0ea4
	692	#define MT6328_AUXADC_CON7 0x0ea6
	693	#define MT6328_AUXADC_CON8 0x0ea8
	694	#define MT6328_AUXADC_CON9 0x0eaa
	695	#define MT6328_AUXADC_CON10 0x0eac
	696	#define MT6328_AUXADC_CON11 0x0eae
	697	#define MT6328_AUXADC_CON12 0x0eb0
	698	#define MT6328_AUXADC_CON13 0x0eb2
	699	#define MT6328_AUXADC_CON14 0x0eb4
	700	#define MT6328_AUXADC_CON15 0x0eb6
	701	#define MT6328_AUXADC_CON16 0x0eb8
	702	#define MT6328_AUXADC_AUTORPT0 0x0eba
	703	#define MT6328_AUXADC_LBAT0 0x0ebc
	704	#define MT6328_AUXADC_LBAT1 0x0ebe
	705	#define MT6328_AUXADC_LBAT2 0x0ec0
	706	#define MT6328_AUXADC_LBAT3 0x0ec2
	707	#define MT6328_AUXADC_LBAT4 0x0ec4
	708	#define MT6328_AUXADC_LBAT5 0x0ec6
	709	#define MT6328_AUXADC_LBAT6 0x0ec8
	710	#define MT6328_AUXADC_ACCDET 0x0eca
	711	#define MT6328_AUXADC_THR0 0x0ecc
	712	#define MT6328_AUXADC_THR1 0x0ece
	713	#define MT6328_AUXADC_THR2 0x0ed0
	714	#define MT6328_AUXADC_THR3 0x0ed2
	715	#define MT6328_AUXADC_THR4 0x0ed4
	716	#define MT6328_AUXADC_THR5 0x0ed6
	717	#define MT6328_AUXADC_THR6 0x0ed8
	718	#define MT6328_AUXADC_EFUSE0 0x0eda
	719	#define MT6328_AUXADC_EFUSE1 0x0edc
	720	#define MT6328_AUXADC_EFUSE2 0x0ede
	721	#define MT6328_AUXADC_EFUSE3 0x0ee0
	722	#define MT6328_AUXADC_EFUSE4 0x0ee2
	723	#define MT6328_AUXADC_EFUSE5 0x0ee4
	724	#define MT6328_AUXADC_DBG0 0x0ee6
	725	#define MT6328_AUXADC_IMP0 0x0ee8
	726	#define MT6328_AUXADC_IMP1 0x0eea
	727	#define MT6328_AUXADC_VISMPS0_1 0x0eec
	728	#define MT6328_AUXADC_VISMPS0_2 0x0eee
	729	#define MT6328_AUXADC_VISMPS0_3 0x0ef0
	730	#define MT6328_AUXADC_VISMPS0_4 0x0ef2
	731	#define MT6328_AUXADC_VISMPS0_5 0x0ef4
	732	#define MT6328_AUXADC_VISMPS0_6 0x0ef6
	733	#define MT6328_AUXADC_VISMPS0_7 0x0ef8
	734	#define MT6328_AUXADC_LBAT2_1 0x0efa
	735	#define MT6328_AUXADC_LBAT2_2 0x0efc
	736	#define MT6328_AUXADC_LBAT2_3 0x0efe
	737	#define MT6328_AUXADC_LBAT2_4 0x0f00
	738	#define MT6328_AUXADC_LBAT2_5 0x0f02
	739	#define MT6328_AUXADC_LBAT2_6 0x0f04
	740	#define MT6328_AUXADC_LBAT2_7 0x0f06
	741	#define MT6328_AUXADC_MDBG_0 0x0f08
	742	#define MT6328_AUXADC_MDBG_1 0x0f0a
	743	#define MT6328_AUXADC_MDBG_2 0x0f0c
	744	#define MT6328_AUXADC_MDRT_0 0x0f0e
	745	#define MT6328_AUXADC_MDRT_1 0x0f10
	746	#define MT6328_AUXADC_MDRT_2 0x0f12
	747	#define MT6328_ACCDET_CON0 0x0f14
	748	#define MT6328_ACCDET_CON1 0x0f16
	749	#define MT6328_ACCDET_CON2 0x0f18
	750	#define MT6328_ACCDET_CON3 0x0f1a
	751	#define MT6328_ACCDET_CON4 0x0f1c
	752	#define MT6328_ACCDET_CON5 0x0f1e
	753	#define MT6328_ACCDET_CON6 0x0f20
	754	#define MT6328_ACCDET_CON7 0x0f22
	755	#define MT6328_ACCDET_CON8 0x0f24
	756	#define MT6328_ACCDET_CON9 0x0f26
	757	#define MT6328_ACCDET_CON10 0x0f28
	758	#define MT6328_ACCDET_CON11 0x0f2a
	759	#define MT6328_ACCDET_CON12 0x0f2c
	760	#define MT6328_ACCDET_CON13 0x0f2e
	761	#define MT6328_ACCDET_CON14 0x0f30
	762	#define MT6328_ACCDET_CON15 0x0f32
	763	#define MT6328_ACCDET_CON16 0x0f34
	764	#define MT6328_ACCDET_CON17 0x0f36
	765	#define MT6328_ACCDET_CON18 0x0f38
	766	#define MT6328_ACCDET_CON19 0x0f3a
	767	#define MT6328_ACCDET_CON20 0x0f3c
	768	#define MT6328_ACCDET_CON21 0x0f3e
	769	#define MT6328_ACCDET_CON22 0x0f40
	770	#define MT6328_ACCDET_CON23 0x0f42
	771	#define MT6328_ACCDET_CON24 0x0f44
	772	#define MT6328_ACCDET_CON25 0x0f46
	773	#define MT6328_CHR_CON0 0x0f48
	774	#define MT6328_CHR_CON1 0x0f4a
	775	#define MT6328_CHR_CON2 0x0f4c
	776	#define MT6328_CHR_CON3 0x0f4e
	777	#define MT6328_CHR_CON4 0x0f50
	778	#define MT6328_CHR_CON5 0x0f52
	779	#define MT6328_CHR_CON6 0x0f54
	780	#define MT6328_CHR_CON7 0x0f56
	781	#define MT6328_CHR_CON8 0x0f58
	782	#define MT6328_CHR_CON9 0x0f5a
	783	#define MT6328_CHR_CON10 0x0f5c
	784	#define MT6328_CHR_CON11 0x0f5e
	785	#define MT6328_CHR_CON12 0x0f60
	786	#define MT6328_CHR_CON13 0x0f62
	787	#define MT6328_CHR_CON14 0x0f64
	788	#define MT6328_CHR_CON15 0x0f66
	789	#define MT6328_CHR_CON16 0x0f68
	790	#define MT6328_CHR_CON17 0x0f6a
	791	#define MT6328_CHR_CON18 0x0f6c
	792	#define MT6328_CHR_CON19 0x0f6e
	793	#define MT6328_CHR_CON20 0x0f70
	794	#define MT6328_CHR_CON21 0x0f72
	795	#define MT6328_CHR_CON22 0x0f74
	796	#define MT6328_CHR_CON23 0x0f76
	797	#define MT6328_CHR_CON24 0x0f78
	798	#define MT6328_CHR_CON25 0x0f7a
	799	#define MT6328_CHR_CON26 0x0f7c
	800	#define MT6328_CHR_CON27 0x0f7e
	801	#define MT6328_CHR_CON28 0x0f80
	802	#define MT6328_CHR_CON29 0x0f82
	803	#define MT6328_CHR_CON30 0x0f84
	804	#define MT6328_CHR_CON31 0x0f86
	805	#define MT6328_CHR_CON32 0x0f88
	806	#define MT6328_CHR_CON33 0x0f8a
	807	#define MT6328_CHR_CON34 0x0f8c
	808	#define MT6328_CHR_CON35 0x0f8e
	809	#define MT6328_CHR_CON36 0x0f90
	810	#define MT6328_CHR_CON37 0x0f92
	811	#define MT6328_CHR_CON38 0x0f94
	812	#define MT6328_CHR_CON39 0x0f96
	813	#define MT6328_CHR_CON40 0x0f98
	814	#define MT6328_CHR_CON41 0x0f9a
	815	#define MT6328_CHR_CON42 0x0f9c
	816	#define MT6328_BATON_CON0 0x0f9e
	817	#define MT6328_CHR_CON43 0x0fa0
	818	#define MT6328_EOSC_CALI_CON0 0x0faa
	819	#define MT6328_EOSC_CALI_CON1 0x0fac
	820	#define MT6328_VRTC_PWM_CON0 0x0fae
	821
	822	#endif /* __MFD_MT6328_REGISTERS_H__ */

include/linux/mfd/mt6397/core.h+6−5

 enum chip_id {
 	MT6323_CHIP_ID = 0x23,
+	MT6328_CHIP_ID = 0x30,
 	MT6331_CHIP_ID = 0x20,
 	MT6332_CHIP_ID = 0x20,
 	MT6357_CHIP_ID = 0x57,
 	int irq;
 	struct irq_domain *irq_domain;
 	struct mutex irqlock;
-	u16 wake_mask[2];
+	u16 wake_mask[3];
-	u16 irq_masks_cur[2];
+	u16 irq_masks_cur[3];
-	u16 irq_masks_cache[2];
+	u16 irq_masks_cache[3];
-	u16 int_con[2];
+	u16 int_con[3];
-	u16 int_status[2];
+	u16 int_status[3];
 	u16 chip_id;
 	void *irq_data;
 };

include/linux/mfd/palmas.h+2−2

@@ -98,8 +98,8 @@ struct palmas_sleep_requestor_info { · 97 unmodified lines
98	};	98	};
99		99
100	struct palmas_regs_info {	100	struct palmas_regs_info {
101	char *name;	101	const char *name;
102	char *sname;	102	const char *sname;
103	u8 vsel_addr;	103	u8 vsel_addr;
104	u8 ctrl_addr;	104	u8 ctrl_addr;
105	u8 tstep_addr;	105	u8 tstep_addr;

include/linux/mfd/samsung/core.h+1−0

@@ -37,6 +37,7 @@ struct gpio_desc; · 36 unmodified lines
37		37
38	enum sec_device_type {	38	enum sec_device_type {
39	S5M8767X,	39	S5M8767X,
		40	S2DOS05,
40	S2MPA01,	41	S2MPA01,
41	S2MPS11X,	42	S2MPS11X,
42	S2MPS13X,	43	S2MPS13X,

include/linux/platform_data/cros_ec_commands.h+32−0

@@ -1312,6 +1312,38 @@ enum ec_feature_code { · 1311 unmodified lines
1312	* The EC supports the AP composing VDMs for us to send.	1312	* The EC supports the AP composing VDMs for us to send.
1313	*/	1313	*/
1314	EC_FEATURE_TYPEC_AP_VDM_SEND = 46,	1314	EC_FEATURE_TYPEC_AP_VDM_SEND = 46,
		1315	/*
		1316	* The EC supports system safe mode panic recovery.
		1317	*/
		1318	EC_FEATURE_SYSTEM_SAFE_MODE = 47,
		1319	/*
		1320	* The EC will reboot on runtime assertion failures.
		1321	*/
		1322	EC_FEATURE_ASSERT_REBOOTS = 48,
		1323	/*
		1324	* The EC image is built with tokenized logging enabled.
		1325	*/
		1326	EC_FEATURE_TOKENIZED_LOGGING = 49,
		1327	/*
		1328	* The EC supports triggering an STB dump.
		1329	*/
		1330	EC_FEATURE_AMD_STB_DUMP = 50,
		1331	/*
		1332	* The EC supports memory dump commands.
		1333	*/
		1334	EC_FEATURE_MEMORY_DUMP = 51,
		1335	/*
		1336	* The EC supports DP2.1 capability
		1337	*/
		1338	EC_FEATURE_TYPEC_DP2_1 = 52,
		1339	/*
		1340	* The MCU is System Companion Processor Core 1
		1341	*/
		1342	EC_FEATURE_SCP_C1 = 53,
		1343	/*
		1344	* The EC supports UCSI PPM.
		1345	*/
		1346	EC_FEATURE_UCSI_PPM = 54,
1315	};	1347	};
1316		1348
1317	#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)	1349	#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)

sound/soc/codecs/cs42l43.c+0−42

@@ -2402,49 +2402,7 @@ static int cs42l43_codec_runtime_resume(struct device *dev) · 2401 unmodified lines
2402	return 0;	2402	return 0;
2403	}	2403	}
2404		2404
2405	static int cs42l43_codec_suspend(struct device *dev)
2406	{
2407	struct cs42l43_codec *priv = dev_get_drvdata(dev);
2408	struct cs42l43 *cs42l43 = priv->core;
2409
2410	disable_irq(cs42l43->irq);
2411
2412	return 0;
2413	}
2414
2415	static int cs42l43_codec_suspend_noirq(struct device *dev)
2416	{
2417	struct cs42l43_codec *priv = dev_get_drvdata(dev);
2418	struct cs42l43 *cs42l43 = priv->core;
2419
2420	enable_irq(cs42l43->irq);
2421
2422	return 0;
2423	}
2424
2425	static int cs42l43_codec_resume(struct device *dev)
2426	{
2427	struct cs42l43_codec *priv = dev_get_drvdata(dev);
2428	struct cs42l43 *cs42l43 = priv->core;
2429
2430	enable_irq(cs42l43->irq);
2431
2432	return 0;
2433	}
2434
2435	static int cs42l43_codec_resume_noirq(struct device *dev)
2436	{
2437	struct cs42l43_codec *priv = dev_get_drvdata(dev);
2438	struct cs42l43 *cs42l43 = priv->core;
2439
2440	disable_irq(cs42l43->irq);
2441
2442	return 0;
2443	}
2444
2445	static const struct dev_pm_ops cs42l43_codec_pm_ops = {	2405	static const struct dev_pm_ops cs42l43_codec_pm_ops = {
2446	SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend, cs42l43_codec_resume)
2447	NOIRQ_SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend_noirq, cs42l43_codec_resume_noirq)
2448	RUNTIME_PM_OPS(NULL, cs42l43_codec_runtime_resume, NULL)	2406	RUNTIME_PM_OPS(NULL, cs42l43_codec_runtime_resume, NULL)
2449	};	2407	};
2450		2408

Merge tag 'mfd-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Keyboard shortcuts

General

Issues and pull requests

Issues, pull requests and Inbox

Repository code