History

drm/i915: enable PS64 support for DG2

It turns out that on production DG2/ATS HW we should have support for PS64. This feature allows to provide a 64K TLB hint at the PTE level, which is a lot more flexible than the current method of enabling 64K GTT pages for the entire page-table, since that leads to all kinds of annoying restrictions, as documented in: commit caa574ffc4aaf4f29b890223878c63e2e7772f62 Author: Matthew Auld <matthew.auld@intel.com> Date: Sat Feb 19 00:17:49 2022 +0530 drm/i915/uapi: document behaviour for DG2 64K support On discrete platforms like DG2, we need to support a minimum page size of 64K when dealing with device local-memory. This is quite tricky for various reasons, so try to document the new implicit uapi for this. With PS64, we can now drop the 2M GTT alignment restriction, and instead only require 64K or larger when dealing with lmem. We still use the compact-pt layout when possible, but only when we are certain that this doesn't interfere with userspace. Note that this is a change in uAPI behaviour, but hopefully shouldn't be a concern (IGT is at least able to autodetect the alignment), since we are only making the GTT alignment constraint less restrictive. Based on a patch from CQ Tang. v2: update the comment wrt scratch page v3: (Nirmoy) - Fix the selftest to actually use the random size, plus some comment improvements, also drop the rem stuff.

Matthew Auld committed 4 years ago

Commit 8133a6d1 parent e55427b10 files · +218 −106Browse files

Unified · Split

10 files
  1. drivers/gpu/drm/i915/gem/selftests/huge_pages.c +156 −1
  2. drivers/gpu/drm/i915/gt/gen8_ppgtt.c +45 −36
  3. drivers/gpu/drm/i915/gt/intel_gtt.c +3 −18
  4. drivers/gpu/drm/i915/gt/intel_gtt.h +1 −0
  5. drivers/gpu/drm/i915/i915_drv.h +0 −7
  6. drivers/gpu/drm/i915/i915_pci.c +0 −2
  7. drivers/gpu/drm/i915/i915_vma.c +2 −7
  8. drivers/gpu/drm/i915/intel_device_info.h +0 −1
  9. drivers/gpu/drm/i915/selftests/i915_gem_gtt.c +1 −8
  10. include/uapi/drm/i915_drm.h +10 −26
drivers/gpu/drm/i915/gem/selftests/huge_pages.c+156−1
@@ -1161,7 +1161,8 @@ static int igt_write_huge(struct drm_i915_private *i915, · 1160 unmodified lines
1161 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));1161 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
1162 1162
1163 size = obj->base.size;1163 size = obj->base.size;
1164 if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K)1164 if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&
1165 !HAS_64K_PAGES(i915))
1165 size = round_up(size, I915_GTT_PAGE_SIZE_2M);1166 size = round_up(size, I915_GTT_PAGE_SIZE_2M);
1166 1167
1167 n = 0;1168 n = 0;
@@ -1214,6 +1215,10 @@ static int igt_write_huge(struct drm_i915_private *i915, · 46 unmodified lines
1214 * size and ensure the vma offset is at the start of the pt1215 * size and ensure the vma offset is at the start of the pt
1215 * boundary, however to improve coverage we opt for testing both1216 * boundary, however to improve coverage we opt for testing both
1216 * aligned and unaligned offsets.1217 * aligned and unaligned offsets.
1218 *
1219 * With PS64 this is no longer the case, but to ensure we
1220 * sometimes get the compact layout for smaller objects, apply
1221 * the round_up anyway.
1217 */1222 */
1218 if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K)1223 if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K)
1219 offset_low = round_down(offset_low,1224 offset_low = round_down(offset_low,
@@ -1411,6 +1416,7 @@ static int igt_ppgtt_sanity_check(void *arg) · 191 unmodified lines
1411 { SZ_2M + SZ_4K, SZ_64K | SZ_4K },1416 { SZ_2M + SZ_4K, SZ_64K | SZ_4K },
1412 { SZ_2M + SZ_4K, SZ_2M | SZ_4K },1417 { SZ_2M + SZ_4K, SZ_2M | SZ_4K },
1413 { SZ_2M + SZ_64K, SZ_2M | SZ_64K },1418 { SZ_2M + SZ_64K, SZ_2M | SZ_64K },
1419 { SZ_2M + SZ_64K, SZ_64K },
1414 };1420 };
1415 int i, j;1421 int i, j;
1416 int err;1422 int err;
@@ -1540,6 +1546,154 @@ out_put: · 123 unmodified lines
1540 return err;1546 return err;
1541}1547}
1542 1548
1549static int igt_ppgtt_mixed(void *arg)
1550{
1551 struct drm_i915_private *i915 = arg;
1552 const unsigned long flags = PIN_OFFSET_FIXED | PIN_USER;
1553 struct drm_i915_gem_object *obj, *on;
1554 struct i915_gem_engines *engines;
1555 struct i915_gem_engines_iter it;
1556 struct i915_address_space *vm;
1557 struct i915_gem_context *ctx;
1558 struct intel_context *ce;
1559 struct file *file;
1560 I915_RND_STATE(prng);
1561 LIST_HEAD(objects);
1562 struct intel_memory_region *mr;
1563 struct i915_vma *vma;
1564 unsigned int count;
1565 u32 i, addr;
1566 int *order;
1567 int n, err;
1568
1569 /*
1570 * Sanity check mixing 4K and 64K pages within the same page-table via
1571 * the new PS64 TLB hint.
1572 */
1573
1574 if (!HAS_64K_PAGES(i915)) {
1575 pr_info("device lacks PS64, skipping\n");
1576 return 0;
1577 }
1578
1579 file = mock_file(i915);
1580 if (IS_ERR(file))
1581 return PTR_ERR(file);
1582
1583 ctx = hugepage_ctx(i915, file);
1584 if (IS_ERR(ctx)) {
1585 err = PTR_ERR(ctx);
1586 goto out;
1587 }
1588 vm = i915_gem_context_get_eb_vm(ctx);
1589
1590 i = 0;
1591 addr = 0;
1592 do {
1593 u32 sz;
1594
1595 sz = i915_prandom_u32_max_state(SZ_4M, &prng);
1596 sz = max_t(u32, sz, SZ_4K);
1597
1598 mr = i915->mm.regions[INTEL_REGION_LMEM_0];
1599 if (i & 1)
1600 mr = i915->mm.regions[INTEL_REGION_SMEM];
1601
1602 obj = i915_gem_object_create_region(mr, sz, 0, 0);
1603 if (IS_ERR(obj)) {
1604 err = PTR_ERR(obj);
1605 goto out_vm;
1606 }
1607
1608 list_add_tail(&obj->st_link, &objects);
1609
1610 vma = i915_vma_instance(obj, vm, NULL);
1611 if (IS_ERR(vma)) {
1612 err = PTR_ERR(vma);
1613 goto err_put;
1614 }
1615
1616 addr = round_up(addr, mr->min_page_size);
1617 err = i915_vma_pin(vma, 0, 0, addr | flags);
1618 if (err)
1619 goto err_put;
1620
1621 if (mr->type == INTEL_MEMORY_LOCAL &&
1622 (vma->resource->page_sizes_gtt & I915_GTT_PAGE_SIZE_4K)) {
1623 err = -EINVAL;
1624 goto err_put;
1625 }
1626
1627 addr += obj->base.size;
1628 i++;
1629 } while (addr <= SZ_16M);
1630
1631 n = 0;
1632 count = 0;
1633 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1634 count++;
1635 if (!intel_engine_can_store_dword(ce->engine))
1636 continue;
1637
1638 n++;
1639 }
1640 i915_gem_context_unlock_engines(ctx);
1641 if (!n)
1642 goto err_put;
1643
1644 order = i915_random_order(count * count, &prng);
1645 if (!order) {
1646 err = -ENOMEM;
1647 goto err_put;
1648 }
1649
1650 i = 0;
1651 addr = 0;
1652 engines = i915_gem_context_lock_engines(ctx);
1653 list_for_each_entry(obj, &objects, st_link) {
1654 u32 rnd = i915_prandom_u32_max_state(UINT_MAX, &prng);
1655
1656 addr = round_up(addr, obj->mm.region->min_page_size);
1657
1658 ce = engines->engines[order[i] % engines->num_engines];
1659 i = (i + 1) % (count * count);
1660 if (!ce || !intel_engine_can_store_dword(ce->engine))
1661 continue;
1662
1663 err = __igt_write_huge(ce, obj, obj->base.size, addr, 0, rnd);
1664 if (err)
1665 break;
1666
1667 err = __igt_write_huge(ce, obj, obj->base.size, addr,
1668 offset_in_page(rnd) / sizeof(u32), rnd + 1);
1669 if (err)
1670 break;
1671
1672 err = __igt_write_huge(ce, obj, obj->base.size, addr,
1673 (PAGE_SIZE / sizeof(u32)) - 1,
1674 rnd + 2);
1675 if (err)
1676 break;
1677
1678 addr += obj->base.size;
1679
1680 cond_resched();
1681 }
1682
1683 i915_gem_context_unlock_engines(ctx);
1684 kfree(order);
1685err_put:
1686 list_for_each_entry_safe(obj, on, &objects, st_link) {
1687 list_del(&obj->st_link);
1688 i915_gem_object_put(obj);
1689 }
1690out_vm:
1691 i915_vm_put(vm);
1692out:
1693 fput(file);
1694 return err;
1695}
1696
1543static int igt_tmpfs_fallback(void *arg)1697static int igt_tmpfs_fallback(void *arg)
1544{1698{
1545 struct drm_i915_private *i915 = arg;1699 struct drm_i915_private *i915 = arg;
@@ -1803,6 +1957,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *i915) · 257 unmodified lines
1803 SUBTEST(igt_ppgtt_smoke_huge),1957 SUBTEST(igt_ppgtt_smoke_huge),
1804 SUBTEST(igt_ppgtt_sanity_check),1958 SUBTEST(igt_ppgtt_sanity_check),
1805 SUBTEST(igt_ppgtt_compact),1959 SUBTEST(igt_ppgtt_compact),
1960 SUBTEST(igt_ppgtt_mixed),
1806 };1961 };
1807 1962
1808 if (!HAS_PPGTT(i915)) {1963 if (!HAS_PPGTT(i915)) {
drivers/gpu/drm/i915/gt/gen8_ppgtt.c+45−36
@@ -476,6 +476,7 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm, · 475 unmodified lines
476 const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);476 const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
477 unsigned int rem = sg_dma_len(iter->sg);477 unsigned int rem = sg_dma_len(iter->sg);
478 u64 start = vma_res->start;478 u64 start = vma_res->start;
479 u64 end = start + vma_res->vma_size;
479 480
480 GEM_BUG_ON(!i915_vm_is_4lvl(vm));481 GEM_BUG_ON(!i915_vm_is_4lvl(vm));
481 482
@@ -489,9 +490,10 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm, · 7 unmodified lines
489 gen8_pte_t encode = pte_encode;490 gen8_pte_t encode = pte_encode;
490 unsigned int page_size;491 unsigned int page_size;
491 gen8_pte_t *vaddr;492 gen8_pte_t *vaddr;
492 u16 index, max;493 u16 index, max, nent, i;
493 494
494 max = I915_PDES;495 max = I915_PDES;
496 nent = 1;
495 497
496 if (vma_res->bi.page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&498 if (vma_res->bi.page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
497 IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&499 IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
@@ -503,25 +505,37 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm, · 5 unmodified lines
503 505
504 vaddr = px_vaddr(pd);506 vaddr = px_vaddr(pd);
505 } else {507 } else {
506 if (encode & GEN12_PPGTT_PTE_LM) {508 index = __gen8_pte_index(start, 0);
507 GEM_BUG_ON(__gen8_pte_index(start, 0) % 16);509 page_size = I915_GTT_PAGE_SIZE;
508 GEM_BUG_ON(rem < I915_GTT_PAGE_SIZE_64K);
509 GEM_BUG_ON(!IS_ALIGNED(iter->dma,
510 I915_GTT_PAGE_SIZE_64K));
511
512 index = __gen8_pte_index(start, 0) / 16;
513 page_size = I915_GTT_PAGE_SIZE_64K;
514
515 max /= 16;
516
517 vaddr = px_vaddr(pd);
518 vaddr[__gen8_pte_index(start, 1)] |= GEN12_PDE_64K;
519 510
520 pt->is_compact = true;511 if (vma_res->bi.page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
521 } else {512 /*
522 GEM_BUG_ON(pt->is_compact);513 * Device local-memory on these platforms should
523 index = __gen8_pte_index(start, 0);514 * always use 64K pages or larger (including GTT
524 page_size = I915_GTT_PAGE_SIZE;515 * alignment), therefore if we know the whole
516 * page-table needs to be filled we can always
517 * safely use the compact-layout. Otherwise fall
518 * back to the TLB hint with PS64. If this is
519 * system memory we only bother with PS64.
520 */
521 if ((encode & GEN12_PPGTT_PTE_LM) &&
522 end - start >= SZ_2M && !index) {
523 index = __gen8_pte_index(start, 0) / 16;
524 page_size = I915_GTT_PAGE_SIZE_64K;
525
526 max /= 16;
527
528 vaddr = px_vaddr(pd);
529 vaddr[__gen8_pte_index(start, 1)] |= GEN12_PDE_64K;
530
531 pt->is_compact = true;
532 } else if (IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
533 rem >= I915_GTT_PAGE_SIZE_64K &&
534 !(index % 16)) {
535 encode |= GEN12_PTE_PS64;
536 page_size = I915_GTT_PAGE_SIZE_64K;
537 nent = 16;
538 }
525 }539 }
526 540
527 vaddr = px_vaddr(pt);541 vaddr = px_vaddr(pt);
@@ -529,7 +543,12 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm, · 1 unmodified line
529 543
530 do {544 do {
531 GEM_BUG_ON(rem < page_size);545 GEM_BUG_ON(rem < page_size);
532 vaddr[index++] = encode | iter->dma;546
547 for (i = 0; i < nent; i++) {
548 vaddr[index++] =
549 encode | (iter->dma + i *
550 I915_GTT_PAGE_SIZE);
551 }
533 552
534 start += page_size;553 start += page_size;
535 iter->dma += page_size;554 iter->dma += page_size;
@@ -745,6 +764,8 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm, · 209 unmodified lines
745 GEM_BUG_ON(!IS_ALIGNED(addr, SZ_64K));764 GEM_BUG_ON(!IS_ALIGNED(addr, SZ_64K));
746 GEM_BUG_ON(!IS_ALIGNED(offset, SZ_64K));765 GEM_BUG_ON(!IS_ALIGNED(offset, SZ_64K));
747 766
767 /* XXX: we don't strictly need to use this layout */
768
748 if (!pt->is_compact) {769 if (!pt->is_compact) {
749 vaddr = px_vaddr(pd);770 vaddr = px_vaddr(pd);
750 vaddr[gen8_pd_index(idx, 1)] |= GEN12_PDE_64K;771 vaddr[gen8_pd_index(idx, 1)] |= GEN12_PDE_64K;
@@ -935,22 +956,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt, · 184 unmodified lines
935 ppgtt->vm.alloc_pt_dma = alloc_pt_dma;956 ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
936 957
937 /*958 /*
938 * On some platforms the hw has dropped support for 4K GTT pages959 * Using SMEM here instead of LMEM has the advantage of not reserving
939 * when dealing with LMEM, and due to the design of 64K GTT960 * high performance memory for a "never" used filler page. It also
940 * pages in the hw, we can only mark the *entire* page-table as961 * removes the device access that would be required to initialise the
941 * operating in 64K GTT mode, since the enable bit is still on962 * scratch page, reducing pressure on an even scarcer resource.
942 * the pde, and not the pte. And since we still need to allow
943 * 4K GTT pages for SMEM objects, we can't have a "normal" 4K
944 * page-table with scratch pointing to LMEM, since that's
945 * undefined from the hw pov. The simplest solution is to just
946 * move the 64K scratch page to SMEM on all platforms and call
947 * it a day, since that should work for all configurations.
948 *
949 * Using SMEM instead of LMEM has the additional advantage of
950 * not reserving high performance memory for a "never" used
951 * filler page. It also removes the device access that would
952 * be required to initialise the scratch page, reducing pressure
953 * on an even scarcer resource.
954 */963 */
955 ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;964 ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
956 965
drivers/gpu/drm/i915/gt/intel_gtt.c+3−18
@@ -269,11 +269,7 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass) · 268 unmodified lines
269 memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,269 memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
270 ARRAY_SIZE(vm->min_alignment));270 ARRAY_SIZE(vm->min_alignment));
271 271
272 if (HAS_64K_PAGES(vm->i915) && NEEDS_COMPACT_PT(vm->i915) &&272 if (HAS_64K_PAGES(vm->i915)) {
273 subclass == VM_CLASS_PPGTT) {
274 vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_2M;
275 vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_2M;
276 } else if (HAS_64K_PAGES(vm->i915)) {
277 vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_64K;273 vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_64K;
278 vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_64K;274 vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_64K;
279 }275 }
@@ -343,7 +339,8 @@ int setup_scratch_page(struct i915_address_space *vm) · 63 unmodified lines
343 */339 */
344 size = I915_GTT_PAGE_SIZE_4K;340 size = I915_GTT_PAGE_SIZE_4K;
345 if (i915_vm_is_4lvl(vm) &&341 if (i915_vm_is_4lvl(vm) &&
346 HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K))342 HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K) &&
343 !HAS_64K_PAGES(vm->i915))
347 size = I915_GTT_PAGE_SIZE_64K;344 size = I915_GTT_PAGE_SIZE_64K;
348 345
349 do {346 do {
@@ -385,18 +382,6 @@ skip: · 35 unmodified lines
385 if (size == I915_GTT_PAGE_SIZE_4K)382 if (size == I915_GTT_PAGE_SIZE_4K)
386 return -ENOMEM;383 return -ENOMEM;
387 384
388 /*
389 * If we need 64K minimum GTT pages for device local-memory,
390 * like on XEHPSDV, then we need to fail the allocation here,
391 * otherwise we can't safely support the insertion of
392 * local-memory pages for this vm, since the HW expects the
393 * correct physical alignment and size when the page-table is
394 * operating in 64K GTT mode, which includes any scratch PTEs,
395 * since userspace can still touch them.
396 */
397 if (HAS_64K_PAGES(vm->i915))
398 return -ENOMEM;
399
400 size = I915_GTT_PAGE_SIZE_4K;385 size = I915_GTT_PAGE_SIZE_4K;
401 } while (1);386 } while (1);
402}387}
drivers/gpu/drm/i915/gt/intel_gtt.h+1−0
@@ -93,6 +93,7 @@ typedef u64 gen8_pte_t; · 92 unmodified lines
93#define GEN12_GGTT_PTE_LM BIT_ULL(1)93#define GEN12_GGTT_PTE_LM BIT_ULL(1)
94 94
95#define GEN12_PDE_64K BIT(6)95#define GEN12_PDE_64K BIT(6)
96#define GEN12_PTE_PS64 BIT(8)
96 97
97/*98/*
98 * Cacheability Control is a 4-bit value. The low three bits are stored in bits99 * Cacheability Control is a 4-bit value. The low three bits are stored in bits
drivers/gpu/drm/i915/i915_drv.h+0−7
@@ -905,13 +905,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 904 unmodified lines
905 */905 */
906#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)906#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
907 907
908/*
909 * Set this flag when platform doesn't allow both 64k pages and 4k pages in
910 * the same PT. this flag means we need to support compact PT layout for the
911 * ppGTT when using the 64K GTT pages.
912 */
913#define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
914
915#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)908#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
916 909
917#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))910#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
drivers/gpu/drm/i915/i915_pci.c+0−2
@@ -1042,7 +1042,6 @@ static const struct intel_device_info xehpsdv_info = { · 1041 unmodified lines
1042 PLATFORM(INTEL_XEHPSDV),1042 PLATFORM(INTEL_XEHPSDV),
1043 NO_DISPLAY,1043 NO_DISPLAY,
1044 .has_64k_pages = 1,1044 .has_64k_pages = 1,
1045 .needs_compact_pt = 1,
1046 .has_media_ratio_mode = 1,1045 .has_media_ratio_mode = 1,
1047 .__runtime.platform_engine_mask =1046 .__runtime.platform_engine_mask =
1048 BIT(RCS0) | BIT(BCS0) |1047 BIT(RCS0) | BIT(BCS0) |
@@ -1064,7 +1063,6 @@ static const struct intel_device_info xehpsdv_info = { · 15 unmodified lines
1064 .has_64k_pages = 1, \1063 .has_64k_pages = 1, \
1065 .has_guc_deprivilege = 1, \1064 .has_guc_deprivilege = 1, \
1066 .has_heci_pxp = 1, \1065 .has_heci_pxp = 1, \
1067 .needs_compact_pt = 1, \
1068 .has_media_ratio_mode = 1, \1066 .has_media_ratio_mode = 1, \
1069 .__runtime.platform_engine_mask = \1067 .__runtime.platform_engine_mask = \
1070 BIT(RCS0) | BIT(BCS0) | \1068 BIT(RCS0) | BIT(BCS0) | \
drivers/gpu/drm/i915/i915_vma.c+2−7
@@ -776,12 +776,6 @@ i915_vma_insert(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, · 775 unmodified lines
776 GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));776 GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
777 777
778 alignment = max(alignment, i915_vm_obj_min_alignment(vma->vm, vma->obj));778 alignment = max(alignment, i915_vm_obj_min_alignment(vma->vm, vma->obj));
779 /*
780 * for compact-pt we round up the reservation to prevent
781 * any smaller pages being used within the same PDE
782 */
783 if (NEEDS_COMPACT_PT(vma->vm->i915))
784 size = round_up(size, alignment);
785 779
786 /* If binding the object/GGTT view requires more space than the entire780 /* If binding the object/GGTT view requires more space than the entire
787 * aperture has, reject it early before evicting everything in a vain781 * aperture has, reject it early before evicting everything in a vain
@@ -820,7 +814,8 @@ i915_vma_insert(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, · 32 unmodified lines
820 * forseeable future. See also i915_ggtt_offset().814 * forseeable future. See also i915_ggtt_offset().
821 */815 */
822 if (upper_32_bits(end - 1) &&816 if (upper_32_bits(end - 1) &&
823 vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {817 vma->page_sizes.sg > I915_GTT_PAGE_SIZE &&
818 !HAS_64K_PAGES(vma->vm->i915)) {
824 /*819 /*
825 * We can't mix 64K and 4K PTEs in the same page-table820 * We can't mix 64K and 4K PTEs in the same page-table
826 * (2M block), and so to avoid the ugliness and821 * (2M block), and so to avoid the ugliness and
drivers/gpu/drm/i915/intel_device_info.h+0−1
@@ -146,7 +146,6 @@ enum intel_ppgtt_type { · 145 unmodified lines
146 /* Keep has_* in alphabetical order */ \146 /* Keep has_* in alphabetical order */ \
147 func(has_64bit_reloc); \147 func(has_64bit_reloc); \
148 func(has_64k_pages); \148 func(has_64k_pages); \
149 func(needs_compact_pt); \
150 func(gpu_reset_clobbers_display); \149 func(gpu_reset_clobbers_display); \
151 func(has_reset_engine); \150 func(has_reset_engine); \
152 func(has_3d_pipeline); \151 func(has_3d_pipeline); \
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c+1−8
@@ -1114,15 +1114,8 @@ static int misaligned_case(struct i915_address_space *vm, struct intel_memory_re · 1113 unmodified lines
1114 expected_node_size = expected_vma_size;1114 expected_node_size = expected_vma_size;
1115 1115
1116 if (HAS_64K_PAGES(vm->i915) && i915_gem_object_is_lmem(obj)) {1116 if (HAS_64K_PAGES(vm->i915) && i915_gem_object_is_lmem(obj)) {
1117 /*
1118 * The compact-pt should expand lmem node to 2MB for the ppGTT,
1119 * for all other cases we should only expect 64K.
1120 */
1121 expected_vma_size = round_up(size, I915_GTT_PAGE_SIZE_64K);1117 expected_vma_size = round_up(size, I915_GTT_PAGE_SIZE_64K);
1122 if (NEEDS_COMPACT_PT(vm->i915) && !i915_is_ggtt(vm))1118 expected_node_size = round_up(size, I915_GTT_PAGE_SIZE_64K);
1123 expected_node_size = round_up(size, I915_GTT_PAGE_SIZE_2M);
1124 else
1125 expected_node_size = round_up(size, I915_GTT_PAGE_SIZE_64K);
1126 }1119 }
1127 1120
1128 if (vma->size != expected_vma_size || vma->node.size != expected_node_size) {1121 if (vma->size != expected_vma_size || vma->node.size != expected_node_size) {
include/uapi/drm/i915_drm.h+10−26
@@ -3509,27 +3509,13 @@ struct drm_i915_gem_create_ext { · 3508 unmodified lines
3509 *3509 *
3510 * The (page-aligned) allocated size for the object will be returned.3510 * The (page-aligned) allocated size for the object will be returned.
3511 *3511 *
3512 * DG2 64K min page size implications:3512 * On platforms like DG2/ATS the kernel will always use 64K or larger
3513 * pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a
3514 * minimum of 64K GTT alignment for such objects.
3513 *3515 *
3514 * On discrete platforms, starting from DG2, we have to contend with GTT3516 * NOTE: Previously the ABI here required a minimum GTT alignment of 2M
3515 * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE3517 * on DG2/ATS, due to how the hardware implemented 64K GTT page support,
3516 * objects. Specifically the hardware only supports 64K or larger GTT3518 * where we had the following complications:
3517 * page sizes for such memory. The kernel will already ensure that all
3518 * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
3519 * sizes underneath.
3520 *
3521 * Note that the returned size here will always reflect any required
3522 * rounding up done by the kernel, i.e 4K will now become 64K on devices
3523 * such as DG2. The kernel will always select the largest minimum
3524 * page-size for the set of possible placements as the value to use when
3525 * rounding up the @size.
3526 *
3527 * Special DG2 GTT address alignment requirement:
3528 *
3529 * The GTT alignment will also need to be at least 2M for such objects.
3530 *
3531 * Note that due to how the hardware implements 64K GTT page support, we
3532 * have some further complications:
3533 *3519 *
3534 * 1) The entire PDE (which covers a 2MB virtual address range), must3520 * 1) The entire PDE (which covers a 2MB virtual address range), must
3535 * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same3521 * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
@@ -3538,12 +3524,10 @@ struct drm_i915_gem_create_ext { · 2 unmodified lines
3538 * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM3524 * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
3539 * objects.3525 * objects.
3540 *3526 *
3541 * To keep things simple for userland, we mandate that any GTT mappings3527 * However on actual production HW this was completely changed to now
3542 * must be aligned to and rounded up to 2MB. The kernel will internally3528 * allow setting a TLB hint at the PTE level (see PS64), which is a lot
3543 * pad them out to the next 2MB boundary. As this only wastes virtual3529 * more flexible than the above. With this the 2M restriction was
3544 * address space and avoids userland having to copy any needlessly3530 * dropped where we now only require 64K.
3545 * complicated PDE sharing scheme (coloring) and only affects DG2, this
3546 * is deemed to be a good compromise.
3547 */3531 */
3548 __u64 size;3532 __u64 size;
3549 3533

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