It turns out that on production DG2/ATS HW we should have support for PS64. This feature allows to provide a 64K TLB hint at the PTE level, which is a lot more flexible than the current method of enabling 64K GTT pages for the entire page-table, since that leads to all kinds of annoying restrictions, as documented in: commit caa574ffc4aaf4f29b890223878c63e2e7772f62 Author: Matthew Auld <matthew.auld@intel.com> Date: Sat Feb 19 00:17:49 2022 +0530 drm/i915/uapi: document behaviour for DG2 64K support On discrete platforms like DG2, we need to support a minimum page size of 64K when dealing with device local-memory. This is quite tricky for various reasons, so try to document the new implicit uapi for this. With PS64, we can now drop the 2M GTT alignment restriction, and instead only require 64K or larger when dealing with lmem. We still use the compact-pt layout when possible, but only when we are certain that this doesn't interfere with userspace. Note that this is a change in uAPI behaviour, but hopefully shouldn't be a concern (IGT is at least able to autodetect the alignment), since we are only making the GTT alignment constraint less restrictive. Based on a patch from CQ Tang. v2: update the comment wrt scratch page v3: (Nirmoy) - Fix the selftest to actually use the random size, plus some comment improvements, also drop the rem stuff.
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| @@ -3509,27 +3509,13 @@ struct drm_i915_gem_create_ext { · 3508 unmodified lines | ||
| 3509 | 3509 | * |
| 3510 | 3510 | * The (page-aligned) allocated size for the object will be returned. |
| 3511 | 3511 | * |
| 3512 | − * DG2 64K min page size implications: | |
| 3512 | + * On platforms like DG2/ATS the kernel will always use 64K or larger | |
| 3513 | + * pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a | |
| 3514 | + * minimum of 64K GTT alignment for such objects. | |
| 3513 | 3515 | * |
| 3514 | − * On discrete platforms, starting from DG2, we have to contend with GTT | |
| 3515 | − * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE | |
| 3516 | − * objects. Specifically the hardware only supports 64K or larger GTT | |
| 3517 | − * page sizes for such memory. The kernel will already ensure that all | |
| 3518 | − * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page | |
| 3519 | − * sizes underneath. | |
| 3520 | − * | |
| 3521 | − * Note that the returned size here will always reflect any required | |
| 3522 | − * rounding up done by the kernel, i.e 4K will now become 64K on devices | |
| 3523 | − * such as DG2. The kernel will always select the largest minimum | |
| 3524 | − * page-size for the set of possible placements as the value to use when | |
| 3525 | − * rounding up the @size. | |
| 3526 | − * | |
| 3527 | − * Special DG2 GTT address alignment requirement: | |
| 3528 | − * | |
| 3529 | − * The GTT alignment will also need to be at least 2M for such objects. | |
| 3530 | − * | |
| 3531 | − * Note that due to how the hardware implements 64K GTT page support, we | |
| 3532 | − * have some further complications: | |
| 3516 | + * NOTE: Previously the ABI here required a minimum GTT alignment of 2M | |
| 3517 | + * on DG2/ATS, due to how the hardware implemented 64K GTT page support, | |
| 3518 | + * where we had the following complications: | |
| 3533 | 3519 | * |
| 3534 | 3520 | * 1) The entire PDE (which covers a 2MB virtual address range), must |
| 3535 | 3521 | * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same |
| @@ -3538,12 +3524,10 @@ struct drm_i915_gem_create_ext { · 2 unmodified lines | ||
| 3538 | 3524 | * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM |
| 3539 | 3525 | * objects. |
| 3540 | 3526 | * |
| 3541 | − * To keep things simple for userland, we mandate that any GTT mappings | |
| 3542 | − * must be aligned to and rounded up to 2MB. The kernel will internally | |
| 3543 | − * pad them out to the next 2MB boundary. As this only wastes virtual | |
| 3544 | − * address space and avoids userland having to copy any needlessly | |
| 3545 | − * complicated PDE sharing scheme (coloring) and only affects DG2, this | |
| 3546 | − * is deemed to be a good compromise. | |
| 3527 | + * However on actual production HW this was completely changed to now | |
| 3528 | + * allow setting a TLB hint at the PTE level (see PS64), which is a lot | |
| 3529 | + * more flexible than the above. With this the 2M restriction was | |
| 3530 | + * dropped where we now only require 64K. | |
| 3547 | 3531 | */ |
| 3548 | 3532 | __u64 size; |
| 3549 | 3533 | |