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drm/i915: Allow user to set cache at BO creation

To comply with the design that buffer objects shall have immutable cache setting through out their life cycle, {set, get}_caching ioctl's are no longer supported from MTL onward. With that change caching policy can only be set at object creation time. The current code applies a default (platform dependent) cache setting for all objects. However this is not optimal for performance tuning. The patch extends the existing gem_create uAPI to let user set PAT index for the object at creation time. The new extension is platform independent, so UMD's can switch to using this extension for older platforms as well, while {set, get}_caching are still supported on these legacy paltforms for compatibility reason. However, since PAT index was not clearly defined for platforms prior to GEN12 (TGL), so we are limiting this externsion to GEN12+ platforms only. See ext_set_pat() in for the implementation details. The documentation related to the PAT/MOCS tables is currently available for Tiger Lake here: https://www.intel.com/content/www/us/en/docs/graphics-for-linux/developer-reference/1-0/tiger-lake.html The documentation for other platforms is currently being updated. BSpec: 45101 Mesa support has been submitted in this merge request: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878 The media driver supprt has bin submitted in this merge request: https://github.com/intel/media-driver/pull/1680 The IGT test related to this change is igt@gem_create@create-ext-set-pat

Fei Yang committed 3 years ago

Commit 81b1b591 parent 1b842f73 files · +87 −0Browse files

Unified · Split

3 files
  1. drivers/gpu/drm/i915/gem/i915_gem_create.c +40 −0
  2. drivers/gpu/drm/i915/gem/i915_gem_object.c +6 −0
  3. include/uapi/drm/i915_drm.h +41 −0
drivers/gpu/drm/i915/gem/i915_gem_create.c+40−0
@@ -245,6 +245,7 @@ struct create_ext { · 244 unmodified lines
245 unsigned int n_placements;245 unsigned int n_placements;
246 unsigned int placement_mask;246 unsigned int placement_mask;
247 unsigned long flags;247 unsigned long flags;
248 unsigned int pat_index;
248};249};
249 250
250static void repr_placements(char *buf, size_t size,251static void repr_placements(char *buf, size_t size,
@@ -394,11 +395,43 @@ static int ext_set_protected(struct i915_user_extension __user *base, void *data · 143 unmodified lines
394 return 0;395 return 0;
395}396}
396 397
398static int ext_set_pat(struct i915_user_extension __user *base, void *data)
399{
400 struct create_ext *ext_data = data;
401 struct drm_i915_private *i915 = ext_data->i915;
402 struct drm_i915_gem_create_ext_set_pat ext;
403 unsigned int max_pat_index;
404
405 BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
406 offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
407
408 /* Limiting the extension only to Meteor Lake */
409 if (!IS_METEORLAKE(i915))
410 return -ENODEV;
411
412 if (copy_from_user(&ext, base, sizeof(ext)))
413 return -EFAULT;
414
415 max_pat_index = INTEL_INFO(i915)->max_pat_index;
416
417 if (ext.pat_index > max_pat_index) {
418 drm_dbg(&i915->drm, "PAT index is invalid: %u\n",
419 ext.pat_index);
420 return -EINVAL;
421 }
422
423 ext_data->pat_index = ext.pat_index;
424
425 return 0;
426}
427
397static const i915_user_extension_fn create_extensions[] = {428static const i915_user_extension_fn create_extensions[] = {
398 [I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,429 [I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
399 [I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,430 [I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
431 [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat,
400};432};
401 433
434#define PAT_INDEX_NOT_SET 0xffff
402/**435/**
403 * i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle to it.436 * i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle to it.
404 * @dev: drm device pointer437 * @dev: drm device pointer
@@ -418,6 +451,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, · 13 unmodified lines
418 if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)451 if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
419 return -EINVAL;452 return -EINVAL;
420 453
454 ext_data.pat_index = PAT_INDEX_NOT_SET;
421 ret = i915_user_extensions(u64_to_user_ptr(args->extensions),455 ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
422 create_extensions,456 create_extensions,
423 ARRAY_SIZE(create_extensions),457 ARRAY_SIZE(create_extensions),
@@ -454,5 +488,11 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, · 30 unmodified lines
454 if (IS_ERR(obj))488 if (IS_ERR(obj))
455 return PTR_ERR(obj);489 return PTR_ERR(obj);
456 490
491 if (ext_data.pat_index != PAT_INDEX_NOT_SET) {
492 i915_gem_object_set_pat_index(obj, ext_data.pat_index);
493 /* Mark pat_index is set by UMD */
494 obj->pat_set_by_user = true;
495 }
496
457 return i915_gem_publish(obj, file, &args->size, &args->handle);497 return i915_gem_publish(obj, file, &args->size, &args->handle);
458}498}
drivers/gpu/drm/i915/gem/i915_gem_object.c+6−0
@@ -208,6 +208,12 @@ bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj) · 207 unmodified lines
208 if (!(obj->flags & I915_BO_ALLOC_USER))208 if (!(obj->flags & I915_BO_ALLOC_USER))
209 return false;209 return false;
210 210
211 /*
212 * Always flush cache for UMD objects at creation time.
213 */
214 if (obj->pat_set_by_user)
215 return true;
216
211 /*217 /*
212 * EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it218 * EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
213 * possible for userspace to bypass the GTT caching bits set by the219 * possible for userspace to bypass the GTT caching bits set by the
include/uapi/drm/i915_drm.h+41−0
@@ -3680,9 +3680,13 @@ struct drm_i915_gem_create_ext { · 3679 unmodified lines
3680 *3680 *
3681 * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see3681 * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
3682 * struct drm_i915_gem_create_ext_protected_content.3682 * struct drm_i915_gem_create_ext_protected_content.
3683 *
3684 * For I915_GEM_CREATE_EXT_SET_PAT usage see
3685 * struct drm_i915_gem_create_ext_set_pat.
3683 */3686 */
3684#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 03687#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
3685#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 13688#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
3689#define I915_GEM_CREATE_EXT_SET_PAT 2
3686 __u64 extensions;3690 __u64 extensions;
3687};3691};
3688 3692
@@ -3797,6 +3801,43 @@ struct drm_i915_gem_create_ext_protected_content { · 108 unmodified lines
3797 __u32 flags;3801 __u32 flags;
3798};3802};
3799 3803
3804/**
3805 * struct drm_i915_gem_create_ext_set_pat - The
3806 * I915_GEM_CREATE_EXT_SET_PAT extension.
3807 *
3808 * If this extension is provided, the specified caching policy (PAT index) is
3809 * applied to the buffer object.
3810 *
3811 * Below is an example on how to create an object with specific caching policy:
3812 *
3813 * .. code-block:: C
3814 *
3815 * struct drm_i915_gem_create_ext_set_pat set_pat_ext = {
3816 * .base = { .name = I915_GEM_CREATE_EXT_SET_PAT },
3817 * .pat_index = 0,
3818 * };
3819 * struct drm_i915_gem_create_ext create_ext = {
3820 * .size = PAGE_SIZE,
3821 * .extensions = (uintptr_t)&set_pat_ext,
3822 * };
3823 *
3824 * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
3825 * if (err) ...
3826 */
3827struct drm_i915_gem_create_ext_set_pat {
3828 /** @base: Extension link. See struct i915_user_extension. */
3829 struct i915_user_extension base;
3830 /**
3831 * @pat_index: PAT index to be set
3832 * PAT index is a bit field in Page Table Entry to control caching
3833 * behaviors for GPU accesses. The definition of PAT index is
3834 * platform dependent and can be found in hardware specifications,
3835 */
3836 __u32 pat_index;
3837 /** @rsvd: reserved for future use */
3838 __u32 rsvd;
3839};
3840
3800/* ID of the protected content session managed by i915 when PXP is active */3841/* ID of the protected content session managed by i915 when PXP is active */
3801#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf3842#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
3802 3843

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