History

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas: - Set the minimum GCC version to 5.1 for arm64 due to earlier compiler bugs. - Make atomic helpers __always_inline to avoid a section mismatch when compiling with clang. - Fix the CMA and crashkernel reservations to use ZONE_DMA (remove the arm64_dma32_phys_limit variable, no longer needed with a dynamic ZONE_DMA sizing in 5.11). - Remove redundant IRQ flag tracing that was leaving lockdep inconsistent with the hardware state. - Revert perf events based hard lockup detector that was causing smp_processor_id() to be called in preemptible context. - Some trivial cleanups - spelling fix, renaming S_FRAME_SIZE to PT_REGS_SIZE, function prototypes added. * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: selftests: Fix spelling of 'Mismatch' arm64: syscall: include prototype for EL0 SVC functions compiler.h: Raise minimum version of GCC to 5.1 for arm64 arm64: make atomic helpers __always_inline arm64: rename S_FRAME_SIZE to PT_REGS_SIZE Revert "arm64: Enable perf events based hard lockup detector" arm64: entry: remove redundant IRQ flag tracing arm64: Remove arm64_dma32_phys_limit and its uses

Linus Torvalds committed 5 years ago

Commit 82821be2 parents f288c89 3a57a6417 files · +56 −107Browse files

Unified · Split

17 files
  1. arch/arm64/Kconfig +0 −2
  2. arch/arm64/include/asm/atomic.h +5 −5
  3. arch/arm64/include/asm/processor.h +1 −2
  4. arch/arm64/kernel/asm-offsets.c +1 −1
  5. arch/arm64/kernel/entry-ftrace.S +6 −6
  6. arch/arm64/kernel/entry.S +7 −7
  7. arch/arm64/kernel/perf_event.c +2 −39
  8. arch/arm64/kernel/probes/kprobes_trampoline.S +3 −3
  9. arch/arm64/kernel/signal.c +0 −7
  10. arch/arm64/kernel/syscall.c +2 −8
  11. arch/arm64/mm/init.c +18 −15
  12. drivers/perf/arm_pmu.c +0 −5
  13. include/asm-generic/bitops/atomic.h +3 −3
  14. include/linux/compiler-gcc.h +6 −0
  15. include/linux/perf/arm_pmu.h +0 −2
  16. tools/testing/selftests/arm64/fp/fpsimd-test.S +1 −1
  17. tools/testing/selftests/arm64/fp/sve-test.S +1 −1
arch/arm64/Kconfig+0−2
@@ -174,8 +174,6 @@ config ARM64 · 173 unmodified lines
174 select HAVE_NMI174 select HAVE_NMI
175 select HAVE_PATA_PLATFORM175 select HAVE_PATA_PLATFORM
176 select HAVE_PERF_EVENTS176 select HAVE_PERF_EVENTS
177 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI && HW_PERF_EVENTS
178 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI
179 select HAVE_PERF_REGS177 select HAVE_PERF_REGS
180 select HAVE_PERF_USER_STACK_DUMP178 select HAVE_PERF_USER_STACK_DUMP
181 select HAVE_REGS_AND_STACK_ACCESS_API179 select HAVE_REGS_AND_STACK_ACCESS_API
arch/arm64/include/asm/atomic.h+5−5
@@ -17,7 +17,7 @@ · 16 unmodified lines
17#include <asm/lse.h>17#include <asm/lse.h>
18 18
19#define ATOMIC_OP(op) \19#define ATOMIC_OP(op) \
20static inline void arch_##op(int i, atomic_t *v) \20static __always_inline void arch_##op(int i, atomic_t *v) \
21{ \21{ \
22 __lse_ll_sc_body(op, i, v); \22 __lse_ll_sc_body(op, i, v); \
23}23}
@@ -32,7 +32,7 @@ ATOMIC_OP(atomic_sub) · 8 unmodified lines
32#undef ATOMIC_OP32#undef ATOMIC_OP
33 33
34#define ATOMIC_FETCH_OP(name, op) \34#define ATOMIC_FETCH_OP(name, op) \
35static inline int arch_##op##name(int i, atomic_t *v) \35static __always_inline int arch_##op##name(int i, atomic_t *v) \
36{ \36{ \
37 return __lse_ll_sc_body(op##name, i, v); \37 return __lse_ll_sc_body(op##name, i, v); \
38}38}
@@ -56,7 +56,7 @@ ATOMIC_FETCH_OPS(atomic_sub_return) · 17 unmodified lines
56#undef ATOMIC_FETCH_OPS56#undef ATOMIC_FETCH_OPS
57 57
58#define ATOMIC64_OP(op) \58#define ATOMIC64_OP(op) \
59static inline void arch_##op(long i, atomic64_t *v) \59static __always_inline void arch_##op(long i, atomic64_t *v) \
60{ \60{ \
61 __lse_ll_sc_body(op, i, v); \61 __lse_ll_sc_body(op, i, v); \
62}62}
@@ -71,7 +71,7 @@ ATOMIC64_OP(atomic64_sub) · 8 unmodified lines
71#undef ATOMIC64_OP71#undef ATOMIC64_OP
72 72
73#define ATOMIC64_FETCH_OP(name, op) \73#define ATOMIC64_FETCH_OP(name, op) \
74static inline long arch_##op##name(long i, atomic64_t *v) \74static __always_inline long arch_##op##name(long i, atomic64_t *v) \
75{ \75{ \
76 return __lse_ll_sc_body(op##name, i, v); \76 return __lse_ll_sc_body(op##name, i, v); \
77}77}
@@ -94,7 +94,7 @@ ATOMIC64_FETCH_OPS(atomic64_sub_return) · 16 unmodified lines
94#undef ATOMIC64_FETCH_OP94#undef ATOMIC64_FETCH_OP
95#undef ATOMIC64_FETCH_OPS95#undef ATOMIC64_FETCH_OPS
96 96
97static inline long arch_atomic64_dec_if_positive(atomic64_t *v)97static __always_inline long arch_atomic64_dec_if_positive(atomic64_t *v)
98{98{
99 return __lse_ll_sc_body(atomic64_dec_if_positive, v);99 return __lse_ll_sc_body(atomic64_dec_if_positive, v);
100}100}
arch/arm64/include/asm/processor.h+1−2
@@ -94,8 +94,7 @@ · 93 unmodified lines
94#endif /* CONFIG_ARM64_FORCE_52BIT */94#endif /* CONFIG_ARM64_FORCE_52BIT */
95 95
96extern phys_addr_t arm64_dma_phys_limit;96extern phys_addr_t arm64_dma_phys_limit;
97extern phys_addr_t arm64_dma32_phys_limit;97#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
98#define ARCH_LOW_ADDRESS_LIMIT ((arm64_dma_phys_limit ? : arm64_dma32_phys_limit) - 1)
99 98
100struct debug_info {99struct debug_info {
101#ifdef CONFIG_HAVE_HW_BREAKPOINT100#ifdef CONFIG_HAVE_HW_BREAKPOINT
arch/arm64/kernel/asm-offsets.c+1−1
@@ -75,7 +75,7 @@ int main(void) · 74 unmodified lines
75 DEFINE(S_SDEI_TTBR1, offsetof(struct pt_regs, sdei_ttbr1));75 DEFINE(S_SDEI_TTBR1, offsetof(struct pt_regs, sdei_ttbr1));
76 DEFINE(S_PMR_SAVE, offsetof(struct pt_regs, pmr_save));76 DEFINE(S_PMR_SAVE, offsetof(struct pt_regs, pmr_save));
77 DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe));77 DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe));
78 DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));78 DEFINE(PT_REGS_SIZE, sizeof(struct pt_regs));
79 BLANK();79 BLANK();
80#ifdef CONFIG_COMPAT80#ifdef CONFIG_COMPAT
81 DEFINE(COMPAT_SIGFRAME_REGS_OFFSET, offsetof(struct compat_sigframe, uc.uc_mcontext.arm_r0));81 DEFINE(COMPAT_SIGFRAME_REGS_OFFSET, offsetof(struct compat_sigframe, uc.uc_mcontext.arm_r0));
arch/arm64/kernel/entry-ftrace.S+6−6
@@ -35,7 +35,7 @@ · 34 unmodified lines
35 */35 */
36 .macro ftrace_regs_entry, allregs=036 .macro ftrace_regs_entry, allregs=0
37 /* Make room for pt_regs, plus a callee frame */37 /* Make room for pt_regs, plus a callee frame */
38 sub sp, sp, #(S_FRAME_SIZE + 16)38 sub sp, sp, #(PT_REGS_SIZE + 16)
39 39
40 /* Save function arguments (and x9 for simplicity) */40 /* Save function arguments (and x9 for simplicity) */
41 stp x0, x1, [sp, #S_X0]41 stp x0, x1, [sp, #S_X0]
@@ -61,15 +61,15 @@ · 19 unmodified lines
61 .endif61 .endif
62 62
63 /* Save the callsite's SP and LR */63 /* Save the callsite's SP and LR */
64 add x10, sp, #(S_FRAME_SIZE + 16)64 add x10, sp, #(PT_REGS_SIZE + 16)
65 stp x9, x10, [sp, #S_LR]65 stp x9, x10, [sp, #S_LR]
66 66
67 /* Save the PC after the ftrace callsite */67 /* Save the PC after the ftrace callsite */
68 str x30, [sp, #S_PC]68 str x30, [sp, #S_PC]
69 69
70 /* Create a frame record for the callsite above pt_regs */70 /* Create a frame record for the callsite above pt_regs */
71 stp x29, x9, [sp, #S_FRAME_SIZE]71 stp x29, x9, [sp, #PT_REGS_SIZE]
72 add x29, sp, #S_FRAME_SIZE72 add x29, sp, #PT_REGS_SIZE
73 73
74 /* Create our frame record within pt_regs. */74 /* Create our frame record within pt_regs. */
75 stp x29, x30, [sp, #S_STACKFRAME]75 stp x29, x30, [sp, #S_STACKFRAME]
@@ -120,7 +120,7 @@ ftrace_common_return: · 44 unmodified lines
120 ldr x9, [sp, #S_PC]120 ldr x9, [sp, #S_PC]
121 121
122 /* Restore the callsite's SP */122 /* Restore the callsite's SP */
123 add sp, sp, #S_FRAME_SIZE + 16123 add sp, sp, #PT_REGS_SIZE + 16
124 124
125 ret x9125 ret x9
126SYM_CODE_END(ftrace_common)126SYM_CODE_END(ftrace_common)
@@ -130,7 +130,7 @@ SYM_CODE_START(ftrace_graph_caller) · 3 unmodified lines
130 ldr x0, [sp, #S_PC]130 ldr x0, [sp, #S_PC]
131 sub x0, x0, #AARCH64_INSN_SIZE // ip (callsite's BL insn)131 sub x0, x0, #AARCH64_INSN_SIZE // ip (callsite's BL insn)
132 add x1, sp, #S_LR // parent_ip (callsite's LR)132 add x1, sp, #S_LR // parent_ip (callsite's LR)
133 ldr x2, [sp, #S_FRAME_SIZE] // parent fp (callsite's FP)133 ldr x2, [sp, #PT_REGS_SIZE] // parent fp (callsite's FP)
134 bl prepare_ftrace_return134 bl prepare_ftrace_return
135 b ftrace_common_return135 b ftrace_common_return
136SYM_CODE_END(ftrace_graph_caller)136SYM_CODE_END(ftrace_graph_caller)
arch/arm64/kernel/entry.S+7−7
@@ -75,7 +75,7 @@ alternative_else_nop_endif · 74 unmodified lines
75 .endif75 .endif
76#endif76#endif
77 77
78 sub sp, sp, #S_FRAME_SIZE78 sub sp, sp, #PT_REGS_SIZE
79#ifdef CONFIG_VMAP_STACK79#ifdef CONFIG_VMAP_STACK
80 /*80 /*
81 * Test whether the SP has overflowed, without corrupting a GPR.81 * Test whether the SP has overflowed, without corrupting a GPR.
@@ -96,7 +96,7 @@ alternative_else_nop_endif · 14 unmodified lines
96 * userspace, and can clobber EL0 registers to free up GPRs.96 * userspace, and can clobber EL0 registers to free up GPRs.
97 */97 */
98 98
99 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */99 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */
100 msr tpidr_el0, x0100 msr tpidr_el0, x0
101 101
102 /* Recover the original x0 value and stash it in tpidrro_el0 */102 /* Recover the original x0 value and stash it in tpidrro_el0 */
@@ -253,7 +253,7 @@ alternative_else_nop_endif · 150 unmodified lines
253 253
254 scs_load tsk, x20254 scs_load tsk, x20
255 .else255 .else
256 add x21, sp, #S_FRAME_SIZE256 add x21, sp, #PT_REGS_SIZE
257 get_current_task tsk257 get_current_task tsk
258 .endif /* \el == 0 */258 .endif /* \el == 0 */
259 mrs x22, elr_el1259 mrs x22, elr_el1
@@ -377,7 +377,7 @@ alternative_else_nop_endif · 117 unmodified lines
377 ldp x26, x27, [sp, #16 * 13]377 ldp x26, x27, [sp, #16 * 13]
378 ldp x28, x29, [sp, #16 * 14]378 ldp x28, x29, [sp, #16 * 14]
379 ldr lr, [sp, #S_LR]379 ldr lr, [sp, #S_LR]
380 add sp, sp, #S_FRAME_SIZE // restore sp380 add sp, sp, #PT_REGS_SIZE // restore sp
381 381
382 .if \el == 0382 .if \el == 0
383alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0383alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
@@ -580,12 +580,12 @@ __bad_stack: · 196 unmodified lines
580 580
581 /*581 /*
582 * Store the original GPRs to the new stack. The orginal SP (minus582 * Store the original GPRs to the new stack. The orginal SP (minus
583 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.583 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
584 */584 */
585 sub sp, sp, #S_FRAME_SIZE585 sub sp, sp, #PT_REGS_SIZE
586 kernel_entry 1586 kernel_entry 1
587 mrs x0, tpidr_el0587 mrs x0, tpidr_el0
588 add x0, x0, #S_FRAME_SIZE588 add x0, x0, #PT_REGS_SIZE
589 str x0, [sp, #S_SP]589 str x0, [sp, #S_SP]
590 590
591 /* Stash the regs for handle_bad_stack */591 /* Stash the regs for handle_bad_stack */
arch/arm64/kernel/perf_event.c+2−39
@@ -23,8 +23,6 @@ · 22 unmodified lines
23#include <linux/platform_device.h>23#include <linux/platform_device.h>
24#include <linux/sched_clock.h>24#include <linux/sched_clock.h>
25#include <linux/smp.h>25#include <linux/smp.h>
26#include <linux/nmi.h>
27#include <linux/cpufreq.h>
28 26
29/* ARMv8 Cortex-A53 specific event types. */27/* ARMv8 Cortex-A53 specific event types. */
30#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC228#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
@@ -1250,21 +1248,10 @@ static struct platform_driver armv8_pmu_driver = { · 1219 unmodified lines
1250 1248
1251static int __init armv8_pmu_driver_init(void)1249static int __init armv8_pmu_driver_init(void)
1252{1250{
1253 int ret;
1254
1255 if (acpi_disabled)1251 if (acpi_disabled)
1256 ret = platform_driver_register(&armv8_pmu_driver);1252 return platform_driver_register(&armv8_pmu_driver);
1257 else1253 else
1258 ret = arm_pmu_acpi_probe(armv8_pmuv3_init);1254 return arm_pmu_acpi_probe(armv8_pmuv3_init);
1259
1260 /*
1261 * Try to re-initialize lockup detector after PMU init in
1262 * case PMU events are triggered via NMIs.
1263 */
1264 if (ret == 0 && arm_pmu_irq_is_nmi())
1265 lockup_detector_init();
1266
1267 return ret;
1268}1255}
1269device_initcall(armv8_pmu_driver_init)1256device_initcall(armv8_pmu_driver_init)
1270 1257
@@ -1322,27 +1309,3 @@ void arch_perf_update_userpage(struct perf_event *event, · 51 unmodified lines
1322 userpg->cap_user_time_zero = 1;1309 userpg->cap_user_time_zero = 1;
1323 userpg->cap_user_time_short = 1;1310 userpg->cap_user_time_short = 1;
1324}1311}
1325
1326#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
1327/*
1328 * Safe maximum CPU frequency in case a particular platform doesn't implement
1329 * cpufreq driver. Although, architecture doesn't put any restrictions on
1330 * maximum frequency but 5 GHz seems to be safe maximum given the available
1331 * Arm CPUs in the market which are clocked much less than 5 GHz. On the other
1332 * hand, we can't make it much higher as it would lead to a large hard-lockup
1333 * detection timeout on parts which are running slower (eg. 1GHz on
1334 * Developerbox) and doesn't possess a cpufreq driver.
1335 */
1336#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz
1337u64 hw_nmi_get_sample_period(int watchdog_thresh)
1338{
1339 unsigned int cpu = smp_processor_id();
1340 unsigned long max_cpu_freq;
1341
1342 max_cpu_freq = cpufreq_get_hw_max_freq(cpu) * 1000UL;
1343 if (!max_cpu_freq)
1344 max_cpu_freq = SAFE_MAX_CPU_FREQ;
1345
1346 return (u64)max_cpu_freq * watchdog_thresh;
1347}
1348#endif
arch/arm64/kernel/probes/kprobes_trampoline.S+3−3
@@ -25,7 +25,7 @@ · 24 unmodified lines
25 stp x24, x25, [sp, #S_X24]25 stp x24, x25, [sp, #S_X24]
26 stp x26, x27, [sp, #S_X26]26 stp x26, x27, [sp, #S_X26]
27 stp x28, x29, [sp, #S_X28]27 stp x28, x29, [sp, #S_X28]
28 add x0, sp, #S_FRAME_SIZE28 add x0, sp, #PT_REGS_SIZE
29 stp lr, x0, [sp, #S_LR]29 stp lr, x0, [sp, #S_LR]
30 /*30 /*
31 * Construct a useful saved PSTATE31 * Construct a useful saved PSTATE
@@ -62,7 +62,7 @@ · 30 unmodified lines
62 .endm62 .endm
63 63
64SYM_CODE_START(kretprobe_trampoline)64SYM_CODE_START(kretprobe_trampoline)
65 sub sp, sp, #S_FRAME_SIZE65 sub sp, sp, #PT_REGS_SIZE
66 66
67 save_all_base_regs67 save_all_base_regs
68 68
@@ -76,7 +76,7 @@ SYM_CODE_START(kretprobe_trampoline) · 7 unmodified lines
76 76
77 restore_all_base_regs77 restore_all_base_regs
78 78
79 add sp, sp, #S_FRAME_SIZE79 add sp, sp, #PT_REGS_SIZE
80 ret80 ret
81 81
82SYM_CODE_END(kretprobe_trampoline)82SYM_CODE_END(kretprobe_trampoline)
arch/arm64/kernel/signal.c+0−7
@@ -914,13 +914,6 @@ static void do_signal(struct pt_regs *regs) · 913 unmodified lines
914asmlinkage void do_notify_resume(struct pt_regs *regs,914asmlinkage void do_notify_resume(struct pt_regs *regs,
915 unsigned long thread_flags)915 unsigned long thread_flags)
916{916{
917 /*
918 * The assembly code enters us with IRQs off, but it hasn't
919 * informed the tracing code of that for efficiency reasons.
920 * Update the trace code with the current status.
921 */
922 trace_hardirqs_off();
923
924 do {917 do {
925 if (thread_flags & _TIF_NEED_RESCHED) {918 if (thread_flags & _TIF_NEED_RESCHED) {
926 /* Unmask Debug and SError for the next task */919 /* Unmask Debug and SError for the next task */
arch/arm64/kernel/syscall.c+2−8
@@ -9,6 +9,7 @@ · 8 unmodified lines
9 9
10#include <asm/daifflags.h>10#include <asm/daifflags.h>
11#include <asm/debug-monitors.h>11#include <asm/debug-monitors.h>
12#include <asm/exception.h>
12#include <asm/fpsimd.h>13#include <asm/fpsimd.h>
13#include <asm/syscall.h>14#include <asm/syscall.h>
14#include <asm/thread_info.h>15#include <asm/thread_info.h>
@@ -165,15 +166,8 @@ static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr, · 150 unmodified lines
165 if (!has_syscall_work(flags) && !IS_ENABLED(CONFIG_DEBUG_RSEQ)) {166 if (!has_syscall_work(flags) && !IS_ENABLED(CONFIG_DEBUG_RSEQ)) {
166 local_daif_mask();167 local_daif_mask();
167 flags = current_thread_info()->flags;168 flags = current_thread_info()->flags;
168 if (!has_syscall_work(flags) && !(flags & _TIF_SINGLESTEP)) {169 if (!has_syscall_work(flags) && !(flags & _TIF_SINGLESTEP))
169 /*
170 * We're off to userspace, where interrupts are
171 * always enabled after we restore the flags from
172 * the SPSR.
173 */
174 trace_hardirqs_on();
175 return;170 return;
176 }
177 local_daif_restore(DAIF_PROCCTX);171 local_daif_restore(DAIF_PROCCTX);
178 }172 }
179 173
arch/arm64/mm/init.c+18−15
@@ -53,13 +53,13 @@ s64 memstart_addr __ro_after_init = -1; · 52 unmodified lines
53EXPORT_SYMBOL(memstart_addr);53EXPORT_SYMBOL(memstart_addr);
54 54
55/*55/*
56 * We create both ZONE_DMA and ZONE_DMA32. ZONE_DMA covers the first 1G of56 * If the corresponding config options are enabled, we create both ZONE_DMA
57 * memory as some devices, namely the Raspberry Pi 4, have peripherals with57 * and ZONE_DMA32. By default ZONE_DMA covers the 32-bit addressable memory
58 * this limited view of the memory. ZONE_DMA32 will cover the rest of the 3258 * unless restricted on specific platforms (e.g. 30-bit on Raspberry Pi 4).
59 * bit addressable memory area.59 * In such case, ZONE_DMA32 covers the rest of the 32-bit addressable memory,
60 * otherwise it is empty.
60 */61 */
61phys_addr_t arm64_dma_phys_limit __ro_after_init;62phys_addr_t arm64_dma_phys_limit __ro_after_init;
62phys_addr_t arm64_dma32_phys_limit __ro_after_init;
63 63
64#ifdef CONFIG_KEXEC_CORE64#ifdef CONFIG_KEXEC_CORE
65/*65/*
@@ -84,7 +84,7 @@ static void __init reserve_crashkernel(void) · 18 unmodified lines
84 84
85 if (crash_base == 0) {85 if (crash_base == 0) {
86 /* Current arm64 boot protocol requires 2MB alignment */86 /* Current arm64 boot protocol requires 2MB alignment */
87 crash_base = memblock_find_in_range(0, arm64_dma32_phys_limit,87 crash_base = memblock_find_in_range(0, arm64_dma_phys_limit,
88 crash_size, SZ_2M);88 crash_size, SZ_2M);
89 if (crash_base == 0) {89 if (crash_base == 0) {
90 pr_warn("cannot allocate crashkernel (size:0x%llx)\n",90 pr_warn("cannot allocate crashkernel (size:0x%llx)\n",
@@ -196,6 +196,7 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max) · 105 unmodified lines
196 unsigned long max_zone_pfns[MAX_NR_ZONES] = {0};196 unsigned long max_zone_pfns[MAX_NR_ZONES] = {0};
197 unsigned int __maybe_unused acpi_zone_dma_bits;197 unsigned int __maybe_unused acpi_zone_dma_bits;
198 unsigned int __maybe_unused dt_zone_dma_bits;198 unsigned int __maybe_unused dt_zone_dma_bits;
199 phys_addr_t __maybe_unused dma32_phys_limit = max_zone_phys(32);
199 200
200#ifdef CONFIG_ZONE_DMA201#ifdef CONFIG_ZONE_DMA
201 acpi_zone_dma_bits = fls64(acpi_iort_dma_get_max_cpu_address());202 acpi_zone_dma_bits = fls64(acpi_iort_dma_get_max_cpu_address());
@@ -205,8 +206,12 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max) · 3 unmodified lines
205 max_zone_pfns[ZONE_DMA] = PFN_DOWN(arm64_dma_phys_limit);206 max_zone_pfns[ZONE_DMA] = PFN_DOWN(arm64_dma_phys_limit);
206#endif207#endif
207#ifdef CONFIG_ZONE_DMA32208#ifdef CONFIG_ZONE_DMA32
208 max_zone_pfns[ZONE_DMA32] = PFN_DOWN(arm64_dma32_phys_limit);209 max_zone_pfns[ZONE_DMA32] = PFN_DOWN(dma32_phys_limit);
210 if (!arm64_dma_phys_limit)
211 arm64_dma_phys_limit = dma32_phys_limit;
209#endif212#endif
213 if (!arm64_dma_phys_limit)
214 arm64_dma_phys_limit = PHYS_MASK + 1;
210 max_zone_pfns[ZONE_NORMAL] = max;215 max_zone_pfns[ZONE_NORMAL] = max;
211 216
212 free_area_init(max_zone_pfns);217 free_area_init(max_zone_pfns);
@@ -394,16 +399,9 @@ void __init arm64_memblock_init(void) · 181 unmodified lines
394 399
395 early_init_fdt_scan_reserved_mem();400 early_init_fdt_scan_reserved_mem();
396 401
397 if (IS_ENABLED(CONFIG_ZONE_DMA32))
398 arm64_dma32_phys_limit = max_zone_phys(32);
399 else
400 arm64_dma32_phys_limit = PHYS_MASK + 1;
401
402 reserve_elfcorehdr();402 reserve_elfcorehdr();
403 403
404 high_memory = __va(memblock_end_of_DRAM() - 1) + 1;404 high_memory = __va(memblock_end_of_DRAM() - 1) + 1;
405
406 dma_contiguous_reserve(arm64_dma32_phys_limit);
407}405}
408 406
409void __init bootmem_init(void)407void __init bootmem_init(void)
@@ -438,6 +436,11 @@ void __init bootmem_init(void) · 28 unmodified lines
438 sparse_init();436 sparse_init();
439 zone_sizes_init(min, max);437 zone_sizes_init(min, max);
440 438
439 /*
440 * Reserve the CMA area after arm64_dma_phys_limit was initialised.
441 */
442 dma_contiguous_reserve(arm64_dma_phys_limit);
443
441 /*444 /*
442 * request_standard_resources() depends on crashkernel's memory being445 * request_standard_resources() depends on crashkernel's memory being
443 * reserved, so do it here.446 * reserved, so do it here.
@@ -455,7 +458,7 @@ void __init bootmem_init(void) · 11 unmodified lines
455void __init mem_init(void)458void __init mem_init(void)
456{459{
457 if (swiotlb_force == SWIOTLB_FORCE ||460 if (swiotlb_force == SWIOTLB_FORCE ||
458 max_pfn > PFN_DOWN(arm64_dma_phys_limit ? : arm64_dma32_phys_limit))461 max_pfn > PFN_DOWN(arm64_dma_phys_limit))
459 swiotlb_init(1);462 swiotlb_init(1);
460 else463 else
461 swiotlb_force = SWIOTLB_NO_FORCE;464 swiotlb_force = SWIOTLB_NO_FORCE;
drivers/perf/arm_pmu.c+0−5
@@ -726,11 +726,6 @@ static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu) · 725 unmodified lines
726 return per_cpu(hw_events->irq, cpu);726 return per_cpu(hw_events->irq, cpu);
727}727}
728 728
729bool arm_pmu_irq_is_nmi(void)
730{
731 return has_nmi;
732}
733
734/*729/*
735 * PMU hardware loses all context when a CPU goes offline.730 * PMU hardware loses all context when a CPU goes offline.
736 * When a CPU is hotplugged back in, since some hardware registers are731 * When a CPU is hotplugged back in, since some hardware registers are
include/asm-generic/bitops/atomic.h+3−3
@@ -11,19 +11,19 @@ · 10 unmodified lines
11 * See Documentation/atomic_bitops.txt for details.11 * See Documentation/atomic_bitops.txt for details.
12 */12 */
13 13
14static inline void set_bit(unsigned int nr, volatile unsigned long *p)14static __always_inline void set_bit(unsigned int nr, volatile unsigned long *p)
15{15{
16 p += BIT_WORD(nr);16 p += BIT_WORD(nr);
17 atomic_long_or(BIT_MASK(nr), (atomic_long_t *)p);17 atomic_long_or(BIT_MASK(nr), (atomic_long_t *)p);
18}18}
19 19
20static inline void clear_bit(unsigned int nr, volatile unsigned long *p)20static __always_inline void clear_bit(unsigned int nr, volatile unsigned long *p)
21{21{
22 p += BIT_WORD(nr);22 p += BIT_WORD(nr);
23 atomic_long_andnot(BIT_MASK(nr), (atomic_long_t *)p);23 atomic_long_andnot(BIT_MASK(nr), (atomic_long_t *)p);
24}24}
25 25
26static inline void change_bit(unsigned int nr, volatile unsigned long *p)26static __always_inline void change_bit(unsigned int nr, volatile unsigned long *p)
27{27{
28 p += BIT_WORD(nr);28 p += BIT_WORD(nr);
29 atomic_long_xor(BIT_MASK(nr), (atomic_long_t *)p);29 atomic_long_xor(BIT_MASK(nr), (atomic_long_t *)p);
include/linux/compiler-gcc.h+6−0
@@ -13,6 +13,12 @@ · 12 unmodified lines
13/* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145 */13/* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145 */
14#if GCC_VERSION < 4090014#if GCC_VERSION < 40900
15# error Sorry, your version of GCC is too old - please use 4.9 or newer.15# error Sorry, your version of GCC is too old - please use 4.9 or newer.
16#elif defined(CONFIG_ARM64) && GCC_VERSION < 50100
17/*
18 * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63293
19 * https://lore.kernel.org/r/20210107111841.GN1551@shell.armlinux.org.uk
20 */
21# error Sorry, your version of GCC is too old - please use 5.1 or newer.
16#endif22#endif
17 23
18/*24/*
include/linux/perf/arm_pmu.h+0−2
@@ -163,8 +163,6 @@ int arm_pmu_acpi_probe(armpmu_init_fn init_fn); · 162 unmodified lines
163static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }163static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
164#endif164#endif
165 165
166bool arm_pmu_irq_is_nmi(void);
167
168/* Internal functions only for core arm_pmu code */166/* Internal functions only for core arm_pmu code */
169struct arm_pmu *armpmu_alloc(void);167struct arm_pmu *armpmu_alloc(void);
170struct arm_pmu *armpmu_alloc_atomic(void);168struct arm_pmu *armpmu_alloc_atomic(void);
tools/testing/selftests/arm64/fp/fpsimd-test.S+1−1
@@ -457,7 +457,7 @@ function barf · 456 unmodified lines
457 mov x11, x1 // actual data457 mov x11, x1 // actual data
458 mov x12, x2 // data size458 mov x12, x2 // data size
459 459
460 puts "Mistatch: PID="460 puts "Mismatch: PID="
461 mov x0, x20461 mov x0, x20
462 bl putdec462 bl putdec
463 puts ", iteration="463 puts ", iteration="
tools/testing/selftests/arm64/fp/sve-test.S+1−1
@@ -625,7 +625,7 @@ function barf · 624 unmodified lines
625 mov x11, x1 // actual data625 mov x11, x1 // actual data
626 mov x12, x2 // data size626 mov x12, x2 // data size
627 627
628 puts "Mistatch: PID="628 puts "Mismatch: PID="
629 mov x0, x20629 mov x0, x20
630 bl putdec630 bl putdec
631 puts ", iteration="631 puts ", iteration="