phy: miphy28lp: Inform the reset framework that our reset line may be shared

On the STiH410 B2120 development board the MiPHY28lp shares its reset line with the Synopsys DWC3 SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD). New functionality in the reset subsystems forces consumers to be explicit when requesting shared/exclusive reset lines.

Lee Jones committed 10 years ago

Commit 8293c8a1 parent ba4a1c21 file · +2 −1Browse files

Unified · Split

drivers/phy/phy-miphy28lp.c+2−1

@@ -1143,7 +1143,8 @@ static int miphy28lp_probe_resets(struct device_node *node, · 1142 unmodified lines
1143	1143	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1144	1144	int err;
1145	1145
1146		− miphy_phy->miphy_rst = of_reset_control_get(node, "miphy-sw-rst");
	1146	+ miphy_phy->miphy_rst =
	1147	+ of_reset_control_get_shared(node, "miphy-sw-rst");
1147	1148
1148	1149	if (IS_ERR(miphy_phy->miphy_rst)) {
1149	1150	dev_err(miphy_dev->dev,