Builds upon the existing NVIDIA 16Bx2 block linear format modifiers by adding more "fields" to the existing parameterized DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK format modifier macro that allow fully defining a unique-across- all-NVIDIA-hardware bit layout using a minimal set of fields and values. The new modifier macro DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D is effectively backwards compatible with the existing macro, introducing a superset of the previously definable format modifiers. Backwards compatibility has two quirks. First, the zero value for the "kind" field, which is implied by the DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK macro, must be special cased in drivers and assumed to map to the pre-Turing generic kind of 0xfe, since a kind of "zero" is reserved for linear buffer layouts on all GPUs. Second, it is assumed backwards compatibility is only needed when running on Tegra GPUs, and specifically Tegra GPUs prior to Xavier. This is based on two assertions: -Tegra GPUs prior to Xavier used a slightly different raw bit layout than desktop GPUs, making it impossible to directly share block linear buffers between the two. -Support for the existing block linear modifiers was incomplete, making them useful only for exporting buffers created by nouveau and importing them to Tegra DRM as framebuffers for scan out. There was no support for adding framebuffers using format modifiers in nouveau, nor importing dma-buf/PRIME GEM objects into nouveau userspace drivers with modifiers in Mesa. Hence it is assumed the prior modifiers were not intended for use on desktop GPUs, and as a corollary, were not intended to support sharing block linear buffers across two different NVIDIA GPUs. v2: - Added canonicalize helper function v3: - Added additional bit to compression field to support Tesla (NV5x,G8x,G9x,GT1xx,GT2xx) class chips.
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| @@ -527,7 +527,113 @@ extern "C" { · 526 unmodified lines | ||
| 527 | 527 | #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) |
| 528 | 528 | |
| 529 | 529 | /* |
| 530 | − * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later | |
| 530 | + * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, | |
| 531 | + * and Tegra GPUs starting with Tegra K1. | |
| 532 | + * | |
| 533 | + * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies | |
| 534 | + * based on the architecture generation. GOBs themselves are then arranged in | |
| 535 | + * 3D blocks, with the block dimensions (in terms of GOBs) always being a power | |
| 536 | + * of two, and hence expressible as their log2 equivalent (E.g., "2" represents | |
| 537 | + * a block depth or height of "4"). | |
| 538 | + * | |
| 539 | + * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format | |
| 540 | + * in full detail. | |
| 541 | + * | |
| 542 | + * Macro | |
| 543 | + * Bits Param Description | |
| 544 | + * ---- ----- ----------------------------------------------------------------- | |
| 545 | + * | |
| 546 | + * 3:0 h log2(height) of each block, in GOBs. Placed here for | |
| 547 | + * compatibility with the existing | |
| 548 | + * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. | |
| 549 | + * | |
| 550 | + * 4:4 - Must be 1, to indicate block-linear layout. Necessary for | |
| 551 | + * compatibility with the existing | |
| 552 | + * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. | |
| 553 | + * | |
| 554 | + * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block | |
| 555 | + * size). Must be zero. | |
| 556 | + * | |
| 557 | + * Note there is no log2(width) parameter. Some portions of the | |
| 558 | + * hardware support a block width of two gobs, but it is impractical | |
| 559 | + * to use due to lack of support elsewhere, and has no known | |
| 560 | + * benefits. | |
| 561 | + * | |
| 562 | + * 11:9 - Reserved (To support 2D-array textures with variable array stride | |
| 563 | + * in blocks, specified via log2(tile width in blocks)). Must be | |
| 564 | + * zero. | |
| 565 | + * | |
| 566 | + * 19:12 k Page Kind. This value directly maps to a field in the page | |
| 567 | + * tables of all GPUs >= NV50. It affects the exact layout of bits | |
| 568 | + * in memory and can be derived from the tuple | |
| 569 | + * | |
| 570 | + * (format, GPU model, compression type, samples per pixel) | |
| 571 | + * | |
| 572 | + * Where compression type is defined below. If GPU model were | |
| 573 | + * implied by the format modifier, format, or memory buffer, page | |
| 574 | + * kind would not need to be included in the modifier itself, but | |
| 575 | + * since the modifier should define the layout of the associated | |
| 576 | + * memory buffer independent from any device or other context, it | |
| 577 | + * must be included here. | |
| 578 | + * | |
| 579 | + * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed | |
| 580 | + * starting with Fermi GPUs. Additionally, the mapping between page | |
| 581 | + * kind and bit layout has changed at various points. | |
| 582 | + * | |
| 583 | + * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping | |
| 584 | + * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping | |
| 585 | + * 2 = Gob Height 8, Turing+ Page Kind mapping | |
| 586 | + * 3 = Reserved for future use. | |
| 587 | + * | |
| 588 | + * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further | |
| 589 | + * bit remapping step that occurs at an even lower level than the | |
| 590 | + * page kind and block linear swizzles. This causes the layout of | |
| 591 | + * surfaces mapped in those SOC's GPUs to be incompatible with the | |
| 592 | + * equivalent mapping on other GPUs in the same system. | |
| 593 | + * | |
| 594 | + * 0 = Tegra K1 - Tegra Parker/TX2 Layout. | |
| 595 | + * 1 = Desktop GPU and Tegra Xavier+ Layout | |
| 596 | + * | |
| 597 | + * 25:23 c Lossless Framebuffer Compression type. | |
| 598 | + * | |
| 599 | + * 0 = none | |
| 600 | + * 1 = ROP/3D, layout 1, exact compression format implied by Page | |
| 601 | + * Kind field | |
| 602 | + * 2 = ROP/3D, layout 2, exact compression format implied by Page | |
| 603 | + * Kind field | |
| 604 | + * 3 = CDE horizontal | |
| 605 | + * 4 = CDE vertical | |
| 606 | + * 5 = Reserved for future use | |
| 607 | + * 6 = Reserved for future use | |
| 608 | + * 7 = Reserved for future use | |
| 609 | + * | |
| 610 | + * 55:25 - Reserved for future use. Must be zero. | |
| 611 | + */ | |
| 612 | +#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ | |
| 613 | + fourcc_mod_code(NVIDIA, (0x10 | \ | |
| 614 | + ((h) & 0xf) | \ | |
| 615 | + (((k) & 0xff) << 12) | \ | |
| 616 | + (((g) & 0x3) << 20) | \ | |
| 617 | + (((s) & 0x1) << 22) | \ | |
| 618 | + (((c) & 0x7) << 23))) | |
| 619 | + | |
| 620 | +/* To grandfather in prior block linear format modifiers to the above layout, | |
| 621 | + * the page kind "0", which corresponds to "pitch/linear" and hence is unusable | |
| 622 | + * with block-linear layouts, is remapped within drivers to the value 0xfe, | |
| 623 | + * which corresponds to the "generic" kind used for simple single-sample | |
| 624 | + * uncompressed color formats on Fermi - Volta GPUs. | |
| 625 | + */ | |
| 626 | +static inline __u64 | |
| 627 | +drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) | |
| 628 | +{ | |
| 629 | + if (!(modifier & 0x10) || (modifier & (0xff << 12))) | |
| 630 | + return modifier; | |
| 631 | + else | |
| 632 | + return modifier | (0xfe << 12); | |
| 633 | +} | |
| 634 | + | |
| 635 | +/* | |
| 636 | + * 16Bx2 Block Linear layout, used by Tegra K1 and later | |
| 531 | 637 | * |
| 532 | 638 | * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked |
| 533 | 639 | * vertically by a power of 2 (1 to 32 GOBs) to form a block. |
| @@ -548,20 +654,20 @@ extern "C" { · 14 unmodified lines | ||
| 548 | 654 | * in full detail. |
| 549 | 655 | */ |
| 550 | 656 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ |
| 551 | − fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) | |
| 657 | + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) | |
| 552 | 658 | |
| 553 | 659 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ |
| 554 | − fourcc_mod_code(NVIDIA, 0x10) | |
| 660 | + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) | |
| 555 | 661 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ |
| 556 | − fourcc_mod_code(NVIDIA, 0x11) | |
| 662 | + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) | |
| 557 | 663 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ |
| 558 | − fourcc_mod_code(NVIDIA, 0x12) | |
| 664 | + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) | |
| 559 | 665 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ |
| 560 | − fourcc_mod_code(NVIDIA, 0x13) | |
| 666 | + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) | |
| 561 | 667 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ |
| 562 | − fourcc_mod_code(NVIDIA, 0x14) | |
| 668 | + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) | |
| 563 | 669 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ |
| 564 | − fourcc_mod_code(NVIDIA, 0x15) | |
| 670 | + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) | |
| 565 | 671 | |
| 566 | 672 | /* |
| 567 | 673 | * Some Broadcom modifiers take parameters, for example the number of |