History

Merge tag 'mailbox-v5.11' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar: - arm: added mhu-v2 controller driver - arm_mhu_db: fix kfree by using devm_ variant - stm32-ipcc: misc cleanup * tag 'mailbox-v5.11' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: arm_mhuv2: Add driver dt-bindings: mailbox : arm,mhuv2: Add bindings mailbox: stm32-ipcc: cast void pointers to unsigned long mailbox: stm32-ipcc: remove duplicate error message mailbox: stm32-ipcc: add COMPILE_TEST dependency mailbox: arm_mhu_db: Fix mhu_db_shutdown by replacing kfree with devm_kfree

Linus Torvalds committed 5 years ago

Commit 83005cd2 parents 74f602d 5a6338c8 files · +1391 −11Browse files

Unified · Split

8 files
  1. Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml +209 −0
  2. MAINTAINERS +9 −0
  3. drivers/mailbox/Kconfig +8 −1
  4. drivers/mailbox/Makefile +2 −0
  5. drivers/mailbox/arm_mhu_db.c +1 −1
  6. drivers/mailbox/arm_mhuv2.c +1136 −0
  7. drivers/mailbox/stm32-ipcc.c +6 −9
  8. include/linux/mailbox/arm_mhuv2_message.h +20 −0
Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml+209−0
@@ -0,0 +1,209 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/mailbox/arm,mhuv2.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: ARM MHUv2 Mailbox Controller
8+
9+maintainers:
10+ - Tushar Khandelwal <tushar.khandelwal@arm.com>
11+ - Viresh Kumar <viresh.kumar@linaro.org>
12+
13+description: |
14+ The Arm Message Handling Unit (MHU) Version 2 is a mailbox controller that has
15+ between 1 and 124 channel windows (each 32-bit wide) to provide unidirectional
16+ communication with remote processor(s), where the number of channel windows
17+ are implementation dependent.
18+
19+ Given the unidirectional nature of the controller, an MHUv2 mailbox may only
20+ be written to or read from. If a pair of MHU controllers is implemented
21+ between two processing elements to provide bidirectional communication, these
22+ must be specified as two separate mailboxes.
23+
24+ If the interrupts property is present in device tree node, then its treated as
25+ a "receiver" mailbox, otherwise a "sender".
26+
27+ An MHU controller must be specified along with the supported transport
28+ protocols. The transport protocols determine the method of data transmission
29+ as well as the number of provided mailbox channels.
30+
31+ Following are the possible transport protocols.
32+
33+ - Data-transfer: Each transfer is made of one or more words, using one or more
34+ channel windows.
35+
36+ - Doorbell: Each transfer is made up of single bit flag, using any one of the
37+ bits in a channel window. A channel window can support up to 32 doorbells
38+ and the entire window shall be used in doorbell protocol. Optionally, data
39+ may be transmitted through a shared memory region, wherein the MHU is used
40+ strictly as an interrupt generation mechanism but that is out of the scope
41+ of these bindings.
42+
43+# We need a select here so we don't match all nodes with 'arm,primecell'
44+select:
45+ properties:
46+ compatible:
47+ contains:
48+ enum:
49+ - arm,mhuv2-tx
50+ - arm,mhuv2-rx
51+ required:
52+ - compatible
53+
54+properties:
55+ compatible:
56+ oneOf:
57+ - description: Sender mode
58+ items:
59+ - const: arm,mhuv2-tx
60+ - const: arm,primecell
61+
62+ - description: Receiver-mode
63+ items:
64+ - const: arm,mhuv2-rx
65+ - const: arm,primecell
66+
67+ reg:
68+ maxItems: 1
69+
70+ interrupts:
71+ description: |
72+ The MHUv2 controller always implements an interrupt in the "receiver"
73+ mode, while the interrupt in the "sender" mode was not available in the
74+ version MHUv2.0, but the later versions do have it.
75+ maxItems: 1
76+
77+ clocks:
78+ maxItems: 1
79+
80+ clock-names:
81+ maxItems: 1
82+
83+ arm,mhuv2-protocols:
84+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
85+ description: |
86+ The MHUv2 controller may contain up to 124 channel windows (each 32-bit
87+ wide). The hardware and the DT bindings allows any combination of those to
88+ be used for various transport protocols.
89+
90+ This property allows a platform to describe how these channel windows are
91+ used in various transport protocols. The entries in this property shall be
92+ present as an array of tuples, where each tuple describes details about
93+ one of the transport protocol being implemented over some channel
94+ window(s).
95+
96+ The first field of a tuple signifies the transfer protocol, 0 is reserved
97+ for doorbell protocol, and 1 is reserved for data-transfer protocol.
98+ Using any other value in the first field of a tuple makes it invalid.
99+
100+ The second field of a tuple signifies the number of channel windows where
101+ the protocol would be used and should be set to a non zero value. For
102+ doorbell protocol this field signifies the number of 32-bit channel
103+ windows that implement the doorbell protocol. For data-transfer protocol,
104+ this field signifies the number of 32-bit channel windows that implement
105+ the data-transfer protocol.
106+
107+ The total number of channel windows specified here shouldn't be more than
108+ the ones implemented by the platform, though one can specify lesser number
109+ of windows here than what the platform implements.
110+
111+ mhu: mailbox@2b1f0000 {
112+ ...
113+
114+ arm,mhuv2-protocols = <0 2>, <1 1>, <1 5>, <1 7>;
115+ }
116+
117+ The above example defines the protocols of an ARM MHUv2 mailbox
118+ controller, where a total of 15 channel windows are used. The first two
119+ windows are used in doorbell protocol (64 doorbells), followed by 1, 5 and
120+ 7 windows (separately) used in data-transfer protocol.
121+
122+ minItems: 1
123+ maxItems: 124
124+ items:
125+ items:
126+ - enum: [ 0, 1 ]
127+ - minimum: 0
128+ maximum: 124
129+
130+
131+ '#mbox-cells':
132+ description: |
133+ It is always set to 2. The first argument in the consumers 'mboxes'
134+ property represents the channel window group, which may be used in
135+ doorbell, or data-transfer protocol, and the second argument (only
136+ relevant in doorbell protocol, should be 0 otherwise) represents the
137+ doorbell number within the 32 bit wide channel window.
138+
139+ From the example given above for arm,mhuv2-protocols, here is how a client
140+ node can reference them.
141+
142+ mboxes = <&mhu 0 5>; // Channel Window Group 0, doorbell 5.
143+ mboxes = <&mhu 1 7>; // Channel Window Group 1, doorbell 7.
144+ mboxes = <&mhu 2 0>; // Channel Window Group 2, data transfer protocol with 1 window.
145+ mboxes = <&mhu 3 0>; // Channel Window Group 3, data transfer protocol with 5 windows.
146+ mboxes = <&mhu 4 0>; // Channel Window Group 4, data transfer protocol with 7 windows.
147+
148+ const: 2
149+
150+if:
151+ # Interrupt is compulsory for receiver
152+ properties:
153+ compatible:
154+ contains:
155+ const: arm,mhuv2-rx
156+then:
157+ required:
158+ - interrupts
159+
160+required:
161+ - compatible
162+ - reg
163+ - '#mbox-cells'
164+ - arm,mhuv2-protocols
165+
166+additionalProperties: false
167+
168+examples:
169+ # Multiple transport protocols implemented by the mailbox controllers
170+ - |
171+ soc {
172+ #address-cells = <2>;
173+ #size-cells = <2>;
174+
175+ mhu_tx: mailbox@2b1f0000 {
176+ #mbox-cells = <2>;
177+ compatible = "arm,mhuv2-tx", "arm,primecell";
178+ reg = <0 0x2b1f0000 0 0x1000>;
179+ clocks = <&clock 0>;
180+ clock-names = "apb_pclk";
181+ interrupts = <0 45 4>;
182+ arm,mhuv2-protocols = <1 5>, <1 2>, <1 5>, <1 7>, <0 2>;
183+ };
184+
185+ mhu_rx: mailbox@2b1f1000 {
186+ #mbox-cells = <2>;
187+ compatible = "arm,mhuv2-rx", "arm,primecell";
188+ reg = <0 0x2b1f1000 0 0x1000>;
189+ clocks = <&clock 0>;
190+ clock-names = "apb_pclk";
191+ interrupts = <0 46 4>;
192+ arm,mhuv2-protocols = <1 1>, <1 7>, <0 2>;
193+ };
194+
195+ mhu_client: scb@2e000000 {
196+ compatible = "fujitsu,mb86s70-scb-1.0";
197+ reg = <0 0x2e000000 0 0x4000>;
198+
199+ mboxes =
200+ //data-transfer protocol with 5 windows, mhu-tx
201+ <&mhu_tx 2 0>,
202+ //data-transfer protocol with 7 windows, mhu-tx
203+ <&mhu_tx 3 0>,
204+ //doorbell protocol channel 4, doorbell 27, mhu-tx
205+ <&mhu_tx 4 27>,
206+ //data-transfer protocol with 1 window, mhu-rx
207+ <&mhu_rx 0 0>;
208+ };
209+ };
MAINTAINERS+9−0
@@ -10524,6 +10524,15 @@ F: drivers/mailbox/ · 10523 unmodified lines
1052410524 F: include/linux/mailbox_client.h
1052510525 F: include/linux/mailbox_controller.h
1052610526
10527+MAILBOX ARM MHUv2
10528+M: Viresh Kumar <viresh.kumar@linaro.org>
10529+M: Tushar Khandelwal <Tushar.Khandelwal@arm.com>
10530+L: linux-kernel@vger.kernel.org
10531+S: Maintained
10532+F: drivers/mailbox/arm_mhuv2.c
10533+F: include/linux/mailbox/arm_mhuv2_message.h
10534+F: Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
10535+
1052710536 MAN-PAGES: MANUAL PAGES FOR LINUX -- Sections 2, 3, 4, 5, and 7
1052810537 M: Michael Kerrisk <mtk.manpages@gmail.com>
1052910538 L: linux-man@vger.kernel.org
drivers/mailbox/Kconfig+8−1
@@ -16,6 +16,13 @@ config ARM_MHU · 15 unmodified lines
1616 The controller has 3 mailbox channels, the last of which can be
1717 used in Secure mode only.
1818
19+config ARM_MHU_V2
20+ tristate "ARM MHUv2 Mailbox"
21+ depends on ARM_AMBA
22+ help
23+ Say Y here if you want to build the ARM MHUv2 controller driver,
24+ which provides unidirectional mailboxes between processing elements.
25+
1926 config IMX_MBOX
2027 tristate "i.MX Mailbox"
2128 depends on ARCH_MXC || COMPILE_TEST
@@ -201,7 +208,7 @@ config BCM_FLEXRM_MBOX · 179 unmodified lines
201208
202209 config STM32_IPCC
203210 tristate "STM32 IPCC Mailbox"
204− depends on MACH_STM32MP157
211+ depends on MACH_STM32MP157 || COMPILE_TEST
205212 help
206213 Mailbox implementation for STMicroelectonics STM32 family chips
207214 with hardware for Inter-Processor Communication Controller (IPCC)
drivers/mailbox/Makefile+2−0
@@ -7,6 +7,8 @@ obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o · 6 unmodified lines
77
88 obj-$(CONFIG_ARM_MHU) += arm_mhu.o arm_mhu_db.o
99
10+obj-$(CONFIG_ARM_MHU_V2) += arm_mhuv2.o
11+
1012 obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o
1113
1214 obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o
drivers/mailbox/arm_mhu_db.c+1−1
@@ -180,7 +180,7 @@ static void mhu_db_shutdown(struct mbox_chan *chan) · 179 unmodified lines
180180
181181 /* Reset channel */
182182 mhu_db_mbox_clear_irq(chan);
183− kfree(chan->con_priv);
183+ devm_kfree(mbox->dev, chan->con_priv);
184184 chan->con_priv = NULL;
185185 }
186186
drivers/mailbox/arm_mhuv2.c+1136−0
@@ -0,0 +1,1136 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * ARM Message Handling Unit Version 2 (MHUv2) driver.
4+ *
5+ * Copyright (C) 2020 ARM Ltd.
6+ * Copyright (C) 2020 Linaro Ltd.
7+ *
8+ * An MHUv2 mailbox controller can provide up to 124 channel windows (each 32
9+ * bit long) and the driver allows any combination of both the transport
10+ * protocol modes: data-transfer and doorbell, to be used on those channel
11+ * windows.
12+ *
13+ * The transport protocols should be specified in the device tree entry for the
14+ * device. The transport protocols determine how the underlying hardware
15+ * resources of the device are utilized when transmitting data. Refer to the
16+ * device tree bindings of the ARM MHUv2 controller for more details.
17+ *
18+ * The number of registered mailbox channels is dependent on both the underlying
19+ * hardware - mainly the number of channel windows implemented by the platform,
20+ * as well as the selected transport protocols.
21+ *
22+ * The MHUv2 controller can work both as a sender and receiver, but the driver
23+ * and the DT bindings support unidirectional transfers for better allocation of
24+ * the channels. That is, this driver will be probed for two separate devices
25+ * for each mailbox controller, a sender device and a receiver device.
26+ */
27+
28+#include <linux/amba/bus.h>
29+#include <linux/interrupt.h>
30+#include <linux/mailbox_controller.h>
31+#include <linux/mailbox/arm_mhuv2_message.h>
32+#include <linux/module.h>
33+#include <linux/of_address.h>
34+#include <linux/spinlock.h>
35+
36+/* ====== MHUv2 Registers ====== */
37+
38+/* Maximum number of channel windows */
39+#define MHUV2_CH_WN_MAX 124
40+/* Number of combined interrupt status registers */
41+#define MHUV2_CMB_INT_ST_REG_CNT 4
42+#define MHUV2_STAT_BYTES (sizeof(u32))
43+#define MHUV2_STAT_BITS (MHUV2_STAT_BYTES * __CHAR_BIT__)
44+
45+#define LSB_MASK(n) ((1 << (n * __CHAR_BIT__)) - 1)
46+#define MHUV2_PROTOCOL_PROP "arm,mhuv2-protocols"
47+
48+/* Register Message Handling Unit Configuration fields */
49+struct mhu_cfg_t {
50+ u32 num_ch : 7;
51+ u32 pad : 25;
52+} __packed;
53+
54+/* register Interrupt Status fields */
55+struct int_st_t {
56+ u32 nr2r : 1;
57+ u32 r2nr : 1;
58+ u32 pad : 30;
59+} __packed;
60+
61+/* Register Interrupt Clear fields */
62+struct int_clr_t {
63+ u32 nr2r : 1;
64+ u32 r2nr : 1;
65+ u32 pad : 30;
66+} __packed;
67+
68+/* Register Interrupt Enable fields */
69+struct int_en_t {
70+ u32 r2nr : 1;
71+ u32 nr2r : 1;
72+ u32 chcomb : 1;
73+ u32 pad : 29;
74+} __packed;
75+
76+/* Register Implementer Identification fields */
77+struct iidr_t {
78+ u32 implementer : 12;
79+ u32 revision : 4;
80+ u32 variant : 4;
81+ u32 product_id : 12;
82+} __packed;
83+
84+/* Register Architecture Identification Register fields */
85+struct aidr_t {
86+ u32 arch_minor_rev : 4;
87+ u32 arch_major_rev : 4;
88+ u32 pad : 24;
89+} __packed;
90+
91+/* Sender Channel Window fields */
92+struct mhu2_send_ch_wn_reg {
93+ u32 stat;
94+ u8 pad1[0x0C - 0x04];
95+ u32 stat_set;
96+ u32 int_st;
97+ u32 int_clr;
98+ u32 int_en;
99+ u8 pad2[0x20 - 0x1C];
100+} __packed;
101+
102+/* Sender frame register fields */
103+struct mhu2_send_frame_reg {
104+ struct mhu2_send_ch_wn_reg ch_wn[MHUV2_CH_WN_MAX];
105+ struct mhu_cfg_t mhu_cfg;
106+ u32 resp_cfg;
107+ u32 access_request;
108+ u32 access_ready;
109+ struct int_st_t int_st;
110+ struct int_clr_t int_clr;
111+ struct int_en_t int_en;
112+ u32 reserved0;
113+ u32 chcomb_int_st[MHUV2_CMB_INT_ST_REG_CNT];
114+ u8 pad[0xFC8 - 0xFB0];
115+ struct iidr_t iidr;
116+ struct aidr_t aidr;
117+} __packed;
118+
119+/* Receiver Channel Window fields */
120+struct mhu2_recv_ch_wn_reg {
121+ u32 stat;
122+ u32 stat_masked;
123+ u32 stat_clear;
124+ u8 reserved0[0x10 - 0x0C];
125+ u32 mask;
126+ u32 mask_set;
127+ u32 mask_clear;
128+ u8 pad[0x20 - 0x1C];
129+} __packed;
130+
131+/* Receiver frame register fields */
132+struct mhu2_recv_frame_reg {
133+ struct mhu2_recv_ch_wn_reg ch_wn[MHUV2_CH_WN_MAX];
134+ struct mhu_cfg_t mhu_cfg;
135+ u8 reserved0[0xF90 - 0xF84];
136+ struct int_st_t int_st;
137+ struct int_clr_t int_clr;
138+ struct int_en_t int_en;
139+ u32 pad;
140+ u32 chcomb_int_st[MHUV2_CMB_INT_ST_REG_CNT];
141+ u8 reserved2[0xFC8 - 0xFB0];
142+ struct iidr_t iidr;
143+ struct aidr_t aidr;
144+} __packed;
145+
146+
147+/* ====== MHUv2 data structures ====== */
148+
149+enum mhuv2_transport_protocol {
150+ DOORBELL = 0,
151+ DATA_TRANSFER = 1
152+};
153+
154+enum mhuv2_frame {
155+ RECEIVER_FRAME,
156+ SENDER_FRAME
157+};
158+
159+/**
160+ * struct mhuv2 - MHUv2 mailbox controller data
161+ *
162+ * @mbox: Mailbox controller belonging to the MHU frame.
163+ * @send/recv: Base address of the register mapping region.
164+ * @frame: Frame type: RECEIVER_FRAME or SENDER_FRAME.
165+ * @irq: Interrupt.
166+ * @windows: Channel windows implemented by the platform.
167+ * @minor: Minor version of the controller.
168+ * @length: Length of the protocols array in bytes.
169+ * @protocols: Raw protocol information, derived from device tree.
170+ * @doorbell_pending_lock: spinlock required for correct operation of Tx
171+ * interrupt for doorbells.
172+ */
173+struct mhuv2 {
174+ struct mbox_controller mbox;
175+ union {
176+ struct mhu2_send_frame_reg __iomem *send;
177+ struct mhu2_recv_frame_reg __iomem *recv;
178+ };
179+ enum mhuv2_frame frame;
180+ unsigned int irq;
181+ unsigned int windows;
182+ unsigned int minor;
183+ unsigned int length;
184+ u32 *protocols;
185+
186+ spinlock_t doorbell_pending_lock;
187+};
188+
189+#define mhu_from_mbox(_mbox) container_of(_mbox, struct mhuv2, mbox)
190+
191+/**
192+ * struct mhuv2_protocol_ops - MHUv2 operations
193+ *
194+ * Each transport protocol must provide an implementation of the operations
195+ * provided here.
196+ *
197+ * @rx_startup: Startup callback for receiver.
198+ * @rx_shutdown: Shutdown callback for receiver.
199+ * @read_data: Reads and clears newly available data.
200+ * @tx_startup: Startup callback for receiver.
201+ * @tx_shutdown: Shutdown callback for receiver.
202+ * @last_tx_done: Report back if the last tx is completed or not.
203+ * @send_data: Send data to the receiver.
204+ */
205+struct mhuv2_protocol_ops {
206+ int (*rx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan);
207+ void (*rx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan);
208+ void *(*read_data)(struct mhuv2 *mhu, struct mbox_chan *chan);
209+
210+ void (*tx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan);
211+ void (*tx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan);
212+ int (*last_tx_done)(struct mhuv2 *mhu, struct mbox_chan *chan);
213+ int (*send_data)(struct mhuv2 *mhu, struct mbox_chan *chan, void *arg);
214+};
215+
216+/*
217+ * MHUv2 mailbox channel's private information
218+ *
219+ * @ops: protocol specific ops for the channel.
220+ * @ch_wn_idx: Channel window index allocated to the channel.
221+ * @windows: Total number of windows consumed by the channel, only relevant
222+ * in DATA_TRANSFER protocol.
223+ * @doorbell: Doorbell bit number within the ch_wn_idx window, only relevant
224+ * in DOORBELL protocol.
225+ * @pending: Flag indicating pending doorbell interrupt, only relevant in
226+ * DOORBELL protocol.
227+ */
228+struct mhuv2_mbox_chan_priv {
229+ const struct mhuv2_protocol_ops *ops;
230+ u32 ch_wn_idx;
231+ union {
232+ u32 windows;
233+ struct {
234+ u32 doorbell;
235+ u32 pending;
236+ };
237+ };
238+};
239+
240+/* Macro for reading a bitfield within a physically mapped packed struct */
241+#define readl_relaxed_bitfield(_regptr, _field) \
242+ ({ \
243+ u32 _regval; \
244+ _regval = readl_relaxed((_regptr)); \
245+ (*(typeof((_regptr)))(&_regval))._field; \
246+ })
247+
248+/* Macro for writing a bitfield within a physically mapped packed struct */
249+#define writel_relaxed_bitfield(_value, _regptr, _field) \
250+ ({ \
251+ u32 _regval; \
252+ _regval = readl_relaxed(_regptr); \
253+ (*(typeof(_regptr))(&_regval))._field = _value; \
254+ writel_relaxed(_regval, _regptr); \
255+ })
256+
257+
258+/* =================== Doorbell transport protocol operations =============== */
259+
260+static int mhuv2_doorbell_rx_startup(struct mhuv2 *mhu, struct mbox_chan *chan)
261+{
262+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
263+
264+ writel_relaxed(BIT(priv->doorbell),
265+ &mhu->recv->ch_wn[priv->ch_wn_idx].mask_clear);
266+ return 0;
267+}
268+
269+static void mhuv2_doorbell_rx_shutdown(struct mhuv2 *mhu,
270+ struct mbox_chan *chan)
271+{
272+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
273+
274+ writel_relaxed(BIT(priv->doorbell),
275+ &mhu->recv->ch_wn[priv->ch_wn_idx].mask_set);
276+}
277+
278+static void *mhuv2_doorbell_read_data(struct mhuv2 *mhu, struct mbox_chan *chan)
279+{
280+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
281+
282+ writel_relaxed(BIT(priv->doorbell),
283+ &mhu->recv->ch_wn[priv->ch_wn_idx].stat_clear);
284+ return NULL;
285+}
286+
287+static int mhuv2_doorbell_last_tx_done(struct mhuv2 *mhu,
288+ struct mbox_chan *chan)
289+{
290+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
291+
292+ return !(readl_relaxed(&mhu->send->ch_wn[priv->ch_wn_idx].stat) &
293+ BIT(priv->doorbell));
294+}
295+
296+static int mhuv2_doorbell_send_data(struct mhuv2 *mhu, struct mbox_chan *chan,
297+ void *arg)
298+{
299+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
300+ unsigned long flags;
301+
302+ spin_lock_irqsave(&mhu->doorbell_pending_lock, flags);
303+
304+ priv->pending = 1;
305+ writel_relaxed(BIT(priv->doorbell),
306+ &mhu->send->ch_wn[priv->ch_wn_idx].stat_set);
307+
308+ spin_unlock_irqrestore(&mhu->doorbell_pending_lock, flags);
309+
310+ return 0;
311+}
312+
313+static const struct mhuv2_protocol_ops mhuv2_doorbell_ops = {
314+ .rx_startup = mhuv2_doorbell_rx_startup,
315+ .rx_shutdown = mhuv2_doorbell_rx_shutdown,
316+ .read_data = mhuv2_doorbell_read_data,
317+ .last_tx_done = mhuv2_doorbell_last_tx_done,
318+ .send_data = mhuv2_doorbell_send_data,
319+};
320+#define IS_PROTOCOL_DOORBELL(_priv) (_priv->ops == &mhuv2_doorbell_ops)
321+
322+/* ============= Data transfer transport protocol operations ================ */
323+
324+static int mhuv2_data_transfer_rx_startup(struct mhuv2 *mhu,
325+ struct mbox_chan *chan)
326+{
327+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
328+ int i = priv->ch_wn_idx + priv->windows - 1;
329+
330+ /*
331+ * The protocol mandates that all but the last status register must be
332+ * masked.
333+ */
334+ writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_clear);
335+ return 0;
336+}
337+
338+static void mhuv2_data_transfer_rx_shutdown(struct mhuv2 *mhu,
339+ struct mbox_chan *chan)
340+{
341+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
342+ int i = priv->ch_wn_idx + priv->windows - 1;
343+
344+ writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set);
345+}
346+
347+static void *mhuv2_data_transfer_read_data(struct mhuv2 *mhu,
348+ struct mbox_chan *chan)
349+{
350+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
351+ const int windows = priv->windows;
352+ struct arm_mhuv2_mbox_msg *msg;
353+ u32 *data;
354+ int i, idx;
355+
356+ msg = kzalloc(sizeof(*msg) + windows * MHUV2_STAT_BYTES, GFP_KERNEL);
357+ if (!msg)
358+ return ERR_PTR(-ENOMEM);
359+
360+ data = msg->data = msg + 1;
361+ msg->len = windows * MHUV2_STAT_BYTES;
362+
363+ /*
364+ * Messages are expected in order of most significant word to least
365+ * significant word. Refer mhuv2_data_transfer_send_data() for more
366+ * details.
367+ *
368+ * We also need to read the stat register instead of stat_masked, as we
369+ * masked all but the last window.
370+ *
371+ * Last channel window must be cleared as the final operation. Upon
372+ * clearing the last channel window register, which is unmasked in
373+ * data-transfer protocol, the interrupt is de-asserted.
374+ */
375+ for (i = 0; i < windows; i++) {
376+ idx = priv->ch_wn_idx + i;
377+ data[windows - 1 - i] = readl_relaxed(&mhu->recv->ch_wn[idx].stat);
378+ writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[idx].stat_clear);
379+ }
380+
381+ return msg;
382+}
383+
384+static void mhuv2_data_transfer_tx_startup(struct mhuv2 *mhu,
385+ struct mbox_chan *chan)
386+{
387+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
388+ int i = priv->ch_wn_idx + priv->windows - 1;
389+
390+ /* Enable interrupts only for the last window */
391+ if (mhu->minor) {
392+ writel_relaxed(0x1, &mhu->send->ch_wn[i].int_clr);
393+ writel_relaxed(0x1, &mhu->send->ch_wn[i].int_en);
394+ }
395+}
396+
397+static void mhuv2_data_transfer_tx_shutdown(struct mhuv2 *mhu,
398+ struct mbox_chan *chan)
399+{
400+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
401+ int i = priv->ch_wn_idx + priv->windows - 1;
402+
403+ if (mhu->minor)
404+ writel_relaxed(0x0, &mhu->send->ch_wn[i].int_en);
405+}
406+
407+static int mhuv2_data_transfer_last_tx_done(struct mhuv2 *mhu,
408+ struct mbox_chan *chan)
409+{
410+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
411+ int i = priv->ch_wn_idx + priv->windows - 1;
412+
413+ /* Just checking the last channel window should be enough */
414+ return !readl_relaxed(&mhu->send->ch_wn[i].stat);
415+}
416+
417+/*
418+ * Message will be transmitted from most significant to least significant word.
419+ * This is to allow for messages shorter than channel windows to still trigger
420+ * the receiver interrupt which gets activated when the last stat register is
421+ * written. As an example, a 6-word message is to be written on a 4-channel MHU
422+ * connection: Registers marked with '*' are masked, and will not generate an
423+ * interrupt on the receiver side once written.
424+ *
425+ * u32 *data = [0x00000001], [0x00000002], [0x00000003], [0x00000004],
426+ * [0x00000005], [0x00000006]
427+ *
428+ * ROUND 1:
429+ * stat reg To write Write sequence
430+ * [ stat 3 ] <- [0x00000001] 4 <- triggers interrupt on receiver
431+ * [ stat 2 ] <- [0x00000002] 3
432+ * [ stat 1 ] <- [0x00000003] 2
433+ * [ stat 0 ] <- [0x00000004] 1
434+ *
435+ * data += 4 // Increment data pointer by number of stat regs
436+ *
437+ * ROUND 2:
438+ * stat reg To write Write sequence
439+ * [ stat 3 ] <- [0x00000005] 2 <- triggers interrupt on receiver
440+ * [ stat 2 ] <- [0x00000006] 1
441+ * [ stat 1 ] <- [0x00000000]
442+ * [ stat 0 ] <- [0x00000000]
443+ */
444+static int mhuv2_data_transfer_send_data(struct mhuv2 *mhu,
445+ struct mbox_chan *chan, void *arg)
446+{
447+ const struct arm_mhuv2_mbox_msg *msg = arg;
448+ int bytes_left = msg->len, bytes_to_send, bytes_in_round, i;
449+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
450+ int windows = priv->windows;
451+ u32 *data = msg->data, word;
452+
453+ while (bytes_left) {
454+ if (!data[0]) {
455+ dev_err(mhu->mbox.dev, "Data aligned at first window can't be zero to guarantee interrupt generation at receiver");
456+ return -EINVAL;
457+ }
458+
459+ while(!mhuv2_data_transfer_last_tx_done(mhu, chan))
460+ continue;
461+
462+ bytes_in_round = min(bytes_left, (int)(windows * MHUV2_STAT_BYTES));
463+
464+ for (i = windows - 1; i >= 0; i--) {
465+ /* Data less than windows can transfer ? */
466+ if (unlikely(bytes_in_round <= i * MHUV2_STAT_BYTES))
467+ continue;
468+
469+ word = data[i];
470+ bytes_to_send = bytes_in_round & (MHUV2_STAT_BYTES - 1);
471+ if (unlikely(bytes_to_send))
472+ word &= LSB_MASK(bytes_to_send);
473+ else
474+ bytes_to_send = MHUV2_STAT_BYTES;
475+
476+ writel_relaxed(word, &mhu->send->ch_wn[priv->ch_wn_idx + windows - 1 - i].stat_set);
477+ bytes_left -= bytes_to_send;
478+ bytes_in_round -= bytes_to_send;
479+ }
480+
481+ data += windows;
482+ }
483+
484+ return 0;
485+}
486+
487+static const struct mhuv2_protocol_ops mhuv2_data_transfer_ops = {
488+ .rx_startup = mhuv2_data_transfer_rx_startup,
489+ .rx_shutdown = mhuv2_data_transfer_rx_shutdown,
490+ .read_data = mhuv2_data_transfer_read_data,
491+ .tx_startup = mhuv2_data_transfer_tx_startup,
492+ .tx_shutdown = mhuv2_data_transfer_tx_shutdown,
493+ .last_tx_done = mhuv2_data_transfer_last_tx_done,
494+ .send_data = mhuv2_data_transfer_send_data,
495+};
496+
497+/* Interrupt handlers */
498+
499+static struct mbox_chan *get_irq_chan_comb(struct mhuv2 *mhu, u32 *reg)
500+{
501+ struct mbox_chan *chans = mhu->mbox.chans;
502+ int channel = 0, i, offset = 0, windows, protocol, ch_wn;
503+ u32 stat;
504+
505+ for (i = 0; i < MHUV2_CMB_INT_ST_REG_CNT; i++) {
506+ stat = readl_relaxed(reg + i);
507+ if (!stat)
508+ continue;
509+
510+ ch_wn = i * MHUV2_STAT_BITS + __builtin_ctz(stat);
511+
512+ for (i = 0; i < mhu->length; i += 2) {
513+ protocol = mhu->protocols[i];
514+ windows = mhu->protocols[i + 1];
515+
516+ if (ch_wn >= offset + windows) {
517+ if (protocol == DOORBELL)
518+ channel += MHUV2_STAT_BITS * windows;
519+ else
520+ channel++;
521+
522+ offset += windows;
523+ continue;
524+ }
525+
526+ /* Return first chan of the window in doorbell mode */
527+ if (protocol == DOORBELL)
528+ channel += MHUV2_STAT_BITS * (ch_wn - offset);
529+
530+ return &chans[channel];
531+ }
532+ }
533+
534+ return ERR_PTR(-EIO);
535+}
536+
537+static irqreturn_t mhuv2_sender_interrupt(int irq, void *data)
538+{
539+ struct mhuv2 *mhu = data;
540+ struct device *dev = mhu->mbox.dev;
541+ struct mhuv2_mbox_chan_priv *priv;
542+ struct mbox_chan *chan;
543+ unsigned long flags;
544+ int i, found = 0;
545+ u32 stat;
546+
547+ chan = get_irq_chan_comb(mhu, mhu->send->chcomb_int_st);
548+ if (IS_ERR(chan)) {
549+ dev_warn(dev, "Failed to find channel for the Tx interrupt\n");
550+ return IRQ_NONE;
551+ }
552+ priv = chan->con_priv;
553+
554+ if (!IS_PROTOCOL_DOORBELL(priv)) {
555+ writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx + priv->windows - 1].int_clr);
556+
557+ if (chan->cl) {
558+ mbox_chan_txdone(chan, 0);
559+ return IRQ_HANDLED;
560+ }
561+
562+ dev_warn(dev, "Tx interrupt Received on channel (%u) not currently attached to a mailbox client\n",
563+ priv->ch_wn_idx);
564+ return IRQ_NONE;
565+ }
566+
567+ /* Clear the interrupt first, so we don't miss any doorbell later */
568+ writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx].int_clr);
569+
570+ /*
571+ * In Doorbell mode, make sure no new transitions happen while the
572+ * interrupt handler is trying to find the finished doorbell tx
573+ * operations, else we may think few of the transfers were complete
574+ * before they actually were.
575+ */
576+ spin_lock_irqsave(&mhu->doorbell_pending_lock, flags);
577+
578+ /*
579+ * In case of doorbell mode, the first channel of the window is returned
580+ * by get_irq_chan_comb(). Find all the pending channels here.
581+ */
582+ stat = readl_relaxed(&mhu->send->ch_wn[priv->ch_wn_idx].stat);
583+
584+ for (i = 0; i < MHUV2_STAT_BITS; i++) {
585+ priv = chan[i].con_priv;
586+
587+ /* Find cases where pending was 1, but stat's bit is cleared */
588+ if (priv->pending ^ ((stat >> i) & 0x1)) {
589+ BUG_ON(!priv->pending);
590+
591+ if (!chan->cl) {
592+ dev_warn(dev, "Tx interrupt received on doorbell (%u : %u) channel not currently attached to a mailbox client\n",
593+ priv->ch_wn_idx, i);
594+ continue;
595+ }
596+
597+ mbox_chan_txdone(&chan[i], 0);
598+ priv->pending = 0;
599+ found++;
600+ }
601+ }
602+
603+ spin_unlock_irqrestore(&mhu->doorbell_pending_lock, flags);
604+
605+ if (!found) {
606+ /*
607+ * We may have already processed the doorbell in the previous
608+ * iteration if the interrupt came right after we cleared it but
609+ * before we read the stat register.
610+ */
611+ dev_dbg(dev, "Couldn't find the doorbell (%u) for the Tx interrupt interrupt\n",
612+ priv->ch_wn_idx);
613+ return IRQ_NONE;
614+ }
615+
616+ return IRQ_HANDLED;
617+}
618+
619+static struct mbox_chan *get_irq_chan_comb_rx(struct mhuv2 *mhu)
620+{
621+ struct mhuv2_mbox_chan_priv *priv;
622+ struct mbox_chan *chan;
623+ u32 stat;
624+
625+ chan = get_irq_chan_comb(mhu, mhu->recv->chcomb_int_st);
626+ if (IS_ERR(chan))
627+ return chan;
628+
629+ priv = chan->con_priv;
630+ if (!IS_PROTOCOL_DOORBELL(priv))
631+ return chan;
632+
633+ /*
634+ * In case of doorbell mode, the first channel of the window is returned
635+ * by the routine. Find the exact channel here.
636+ */
637+ stat = readl_relaxed(&mhu->recv->ch_wn[priv->ch_wn_idx].stat_masked);
638+ BUG_ON(!stat);
639+
640+ return chan + __builtin_ctz(stat);
641+}
642+
643+static struct mbox_chan *get_irq_chan_stat_rx(struct mhuv2 *mhu)
644+{
645+ struct mbox_chan *chans = mhu->mbox.chans;
646+ struct mhuv2_mbox_chan_priv *priv;
647+ u32 stat;
648+ int i = 0;
649+
650+ while (i < mhu->mbox.num_chans) {
651+ priv = chans[i].con_priv;
652+ stat = readl_relaxed(&mhu->recv->ch_wn[priv->ch_wn_idx].stat_masked);
653+
654+ if (stat) {
655+ if (IS_PROTOCOL_DOORBELL(priv))
656+ i += __builtin_ctz(stat);
657+ return &chans[i];
658+ }
659+
660+ i += IS_PROTOCOL_DOORBELL(priv) ? MHUV2_STAT_BITS : 1;
661+ }
662+
663+ return ERR_PTR(-EIO);
664+}
665+
666+static struct mbox_chan *get_irq_chan_rx(struct mhuv2 *mhu)
667+{
668+ if (!mhu->minor)
669+ return get_irq_chan_stat_rx(mhu);
670+
671+ return get_irq_chan_comb_rx(mhu);
672+}
673+
674+static irqreturn_t mhuv2_receiver_interrupt(int irq, void *arg)
675+{
676+ struct mhuv2 *mhu = arg;
677+ struct mbox_chan *chan = get_irq_chan_rx(mhu);
678+ struct device *dev = mhu->mbox.dev;
679+ struct mhuv2_mbox_chan_priv *priv;
680+ int ret = IRQ_NONE;
681+ void *data;
682+
683+ if (IS_ERR(chan)) {
684+ dev_warn(dev, "Failed to find channel for the rx interrupt\n");
685+ return IRQ_NONE;
686+ }
687+ priv = chan->con_priv;
688+
689+ /* Read and clear the data first */
690+ data = priv->ops->read_data(mhu, chan);
691+
692+ if (!chan->cl) {
693+ dev_warn(dev, "Received data on channel (%u) not currently attached to a mailbox client\n",
694+ priv->ch_wn_idx);
695+ } else if (IS_ERR(data)) {
696+ dev_err(dev, "Failed to read data: %lu\n", PTR_ERR(data));
697+ } else {
698+ mbox_chan_received_data(chan, data);
699+ ret = IRQ_HANDLED;
700+ }
701+
702+ kfree(data);
703+ return ret;
704+}
705+
706+/* Sender and receiver ops */
707+static bool mhuv2_sender_last_tx_done(struct mbox_chan *chan)
708+{
709+ struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
710+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
711+
712+ return priv->ops->last_tx_done(mhu, chan);
713+}
714+
715+static int mhuv2_sender_send_data(struct mbox_chan *chan, void *data)
716+{
717+ struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
718+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
719+
720+ if (!priv->ops->last_tx_done(mhu, chan))
721+ return -EBUSY;
722+
723+ return priv->ops->send_data(mhu, chan, data);
724+}
725+
726+static int mhuv2_sender_startup(struct mbox_chan *chan)
727+{
728+ struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
729+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
730+
731+ if (priv->ops->tx_startup)
732+ priv->ops->tx_startup(mhu, chan);
733+ return 0;
734+}
735+
736+static void mhuv2_sender_shutdown(struct mbox_chan *chan)
737+{
738+ struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
739+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
740+
741+ if (priv->ops->tx_shutdown)
742+ priv->ops->tx_shutdown(mhu, chan);
743+}
744+
745+static const struct mbox_chan_ops mhuv2_sender_ops = {
746+ .send_data = mhuv2_sender_send_data,
747+ .startup = mhuv2_sender_startup,
748+ .shutdown = mhuv2_sender_shutdown,
749+ .last_tx_done = mhuv2_sender_last_tx_done,
750+};
751+
752+static int mhuv2_receiver_startup(struct mbox_chan *chan)
753+{
754+ struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
755+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
756+
757+ return priv->ops->rx_startup(mhu, chan);
758+}
759+
760+static void mhuv2_receiver_shutdown(struct mbox_chan *chan)
761+{
762+ struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
763+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
764+
765+ priv->ops->rx_shutdown(mhu, chan);
766+}
767+
768+static int mhuv2_receiver_send_data(struct mbox_chan *chan, void *data)
769+{
770+ dev_err(chan->mbox->dev,
771+ "Trying to transmit on a receiver MHU frame\n");
772+ return -EIO;
773+}
774+
775+static bool mhuv2_receiver_last_tx_done(struct mbox_chan *chan)
776+{
777+ dev_err(chan->mbox->dev, "Trying to Tx poll on a receiver MHU frame\n");
778+ return true;
779+}
780+
781+static const struct mbox_chan_ops mhuv2_receiver_ops = {
782+ .send_data = mhuv2_receiver_send_data,
783+ .startup = mhuv2_receiver_startup,
784+ .shutdown = mhuv2_receiver_shutdown,
785+ .last_tx_done = mhuv2_receiver_last_tx_done,
786+};
787+
788+static struct mbox_chan *mhuv2_mbox_of_xlate(struct mbox_controller *mbox,
789+ const struct of_phandle_args *pa)
790+{
791+ struct mhuv2 *mhu = mhu_from_mbox(mbox);
792+ struct mbox_chan *chans = mbox->chans;
793+ int channel = 0, i, offset, doorbell, protocol, windows;
794+
795+ if (pa->args_count != 2)
796+ return ERR_PTR(-EINVAL);
797+
798+ offset = pa->args[0];
799+ doorbell = pa->args[1];
800+ if (doorbell >= MHUV2_STAT_BITS)
801+ goto out;
802+
803+ for (i = 0; i < mhu->length; i += 2) {
804+ protocol = mhu->protocols[i];
805+ windows = mhu->protocols[i + 1];
806+
807+ if (protocol == DOORBELL) {
808+ if (offset < windows)
809+ return &chans[channel + MHUV2_STAT_BITS * offset + doorbell];
810+
811+ channel += MHUV2_STAT_BITS * windows;
812+ offset -= windows;
813+ } else {
814+ if (offset == 0) {
815+ if (doorbell)
816+ goto out;
817+
818+ return &chans[channel];
819+ }
820+
821+ channel++;
822+ offset--;
823+ }
824+ }
825+
826+out:
827+ dev_err(mbox->dev, "Couldn't xlate to a valid channel (%d: %d)\n",
828+ pa->args[0], doorbell);
829+ return ERR_PTR(-ENODEV);
830+}
831+
832+static int mhuv2_verify_protocol(struct mhuv2 *mhu)
833+{
834+ struct device *dev = mhu->mbox.dev;
835+ int protocol, windows, channels = 0, total_windows = 0, i;
836+
837+ for (i = 0; i < mhu->length; i += 2) {
838+ protocol = mhu->protocols[i];
839+ windows = mhu->protocols[i + 1];
840+
841+ if (!windows) {
842+ dev_err(dev, "Window size can't be zero (%d)\n", i);
843+ return -EINVAL;
844+ }
845+ total_windows += windows;
846+
847+ if (protocol == DOORBELL) {
848+ channels += MHUV2_STAT_BITS * windows;
849+ } else if (protocol == DATA_TRANSFER) {
850+ channels++;
851+ } else {
852+ dev_err(dev, "Invalid protocol (%d) present in %s property at index %d\n",
853+ protocol, MHUV2_PROTOCOL_PROP, i);
854+ return -EINVAL;
855+ }
856+ }
857+
858+ if (total_windows > mhu->windows) {
859+ dev_err(dev, "Channel windows can't be more than what's implemented by the hardware ( %d: %d)\n",
860+ total_windows, mhu->windows);
861+ return -EINVAL;
862+ }
863+
864+ mhu->mbox.num_chans = channels;
865+ return 0;
866+}
867+
868+static int mhuv2_allocate_channels(struct mhuv2 *mhu)
869+{
870+ struct mbox_controller *mbox = &mhu->mbox;
871+ struct mhuv2_mbox_chan_priv *priv;
872+ struct device *dev = mbox->dev;
873+ struct mbox_chan *chans;
874+ int protocol, windows = 0, next_window = 0, i, j, k;
875+
876+ chans = devm_kcalloc(dev, mbox->num_chans, sizeof(*chans), GFP_KERNEL);
877+ if (!chans)
878+ return -ENOMEM;
879+
880+ mbox->chans = chans;
881+
882+ for (i = 0; i < mhu->length; i += 2) {
883+ next_window += windows;
884+
885+ protocol = mhu->protocols[i];
886+ windows = mhu->protocols[i + 1];
887+
888+ if (protocol == DATA_TRANSFER) {
889+ priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
890+ if (!priv)
891+ return -ENOMEM;
892+
893+ priv->ch_wn_idx = next_window;
894+ priv->ops = &mhuv2_data_transfer_ops;
895+ priv->windows = windows;
896+ chans++->con_priv = priv;
897+ continue;
898+ }
899+
900+ for (j = 0; j < windows; j++) {
901+ for (k = 0; k < MHUV2_STAT_BITS; k++) {
902+ priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
903+ if (!priv)
904+ return -ENOMEM;
905+
906+ priv->ch_wn_idx = next_window + j;
907+ priv->ops = &mhuv2_doorbell_ops;
908+ priv->doorbell = k;
909+ chans++->con_priv = priv;
910+ }
911+
912+ /*
913+ * Permanently enable interrupt as we can't
914+ * control it per doorbell.
915+ */
916+ if (mhu->frame == SENDER_FRAME && mhu->minor)
917+ writel_relaxed(0x1, &mhu->send->ch_wn[priv->ch_wn_idx].int_en);
918+ }
919+ }
920+
921+ /* Make sure we have initialized all channels */
922+ BUG_ON(chans - mbox->chans != mbox->num_chans);
923+
924+ return 0;
925+}
926+
927+static int mhuv2_parse_channels(struct mhuv2 *mhu)
928+{
929+ struct device *dev = mhu->mbox.dev;
930+ const struct device_node *np = dev->of_node;
931+ int ret, count;
932+ u32 *protocols;
933+
934+ count = of_property_count_u32_elems(np, MHUV2_PROTOCOL_PROP);
935+ if (count <= 0 || count % 2) {
936+ dev_err(dev, "Invalid %s property (%d)\n", MHUV2_PROTOCOL_PROP,
937+ count);
938+ return -EINVAL;
939+ }
940+
941+ protocols = devm_kmalloc_array(dev, count, sizeof(*protocols), GFP_KERNEL);
942+ if (!protocols)
943+ return -ENOMEM;
944+
945+ ret = of_property_read_u32_array(np, MHUV2_PROTOCOL_PROP, protocols, count);
946+ if (ret) {
947+ dev_err(dev, "Failed to read %s property: %d\n",
948+ MHUV2_PROTOCOL_PROP, ret);
949+ return ret;
950+ }
951+
952+ mhu->protocols = protocols;
953+ mhu->length = count;
954+
955+ ret = mhuv2_verify_protocol(mhu);
956+ if (ret)
957+ return ret;
958+
959+ return mhuv2_allocate_channels(mhu);
960+}
961+
962+static int mhuv2_tx_init(struct amba_device *adev, struct mhuv2 *mhu,
963+ void __iomem *reg)
964+{
965+ struct device *dev = mhu->mbox.dev;
966+ int ret, i;
967+
968+ mhu->frame = SENDER_FRAME;
969+ mhu->mbox.ops = &mhuv2_sender_ops;
970+ mhu->send = reg;
971+
972+ mhu->windows = readl_relaxed_bitfield(&mhu->send->mhu_cfg, num_ch);
973+ mhu->minor = readl_relaxed_bitfield(&mhu->send->aidr, arch_minor_rev);
974+
975+ spin_lock_init(&mhu->doorbell_pending_lock);
976+
977+ /*
978+ * For minor version 1 and forward, tx interrupt is provided by
979+ * the controller.
980+ */
981+ if (mhu->minor && adev->irq[0]) {
982+ ret = devm_request_threaded_irq(dev, adev->irq[0], NULL,
983+ mhuv2_sender_interrupt,
984+ IRQF_ONESHOT, "mhuv2-tx", mhu);
985+ if (ret) {
986+ dev_err(dev, "Failed to request tx IRQ, fallback to polling mode: %d\n",
987+ ret);
988+ } else {
989+ mhu->mbox.txdone_irq = true;
990+ mhu->mbox.txdone_poll = false;
991+ mhu->irq = adev->irq[0];
992+
993+ writel_relaxed_bitfield(1, &mhu->send->int_en, chcomb);
994+
995+ /* Disable all channel interrupts */
996+ for (i = 0; i < mhu->windows; i++)
997+ writel_relaxed(0x0, &mhu->send->ch_wn[i].int_en);
998+
999+ goto out;
1000+ }
1001+ }
1002+
1003+ mhu->mbox.txdone_irq = false;
1004+ mhu->mbox.txdone_poll = true;
1005+ mhu->mbox.txpoll_period = 1;
1006+
1007+out:
1008+ /* Wait for receiver to be ready */
1009+ writel_relaxed(0x1, &mhu->send->access_request);
1010+ while (!readl_relaxed(&mhu->send->access_ready))
1011+ continue;
1012+
1013+ return 0;
1014+}
1015+
1016+static int mhuv2_rx_init(struct amba_device *adev, struct mhuv2 *mhu,
1017+ void __iomem *reg)
1018+{
1019+ struct device *dev = mhu->mbox.dev;
1020+ int ret, i;
1021+
1022+ mhu->frame = RECEIVER_FRAME;
1023+ mhu->mbox.ops = &mhuv2_receiver_ops;
1024+ mhu->recv = reg;
1025+
1026+ mhu->windows = readl_relaxed_bitfield(&mhu->recv->mhu_cfg, num_ch);
1027+ mhu->minor = readl_relaxed_bitfield(&mhu->recv->aidr, arch_minor_rev);
1028+
1029+ mhu->irq = adev->irq[0];
1030+ if (!mhu->irq) {
1031+ dev_err(dev, "Missing receiver IRQ\n");
1032+ return -EINVAL;
1033+ }
1034+
1035+ ret = devm_request_threaded_irq(dev, mhu->irq, NULL,
1036+ mhuv2_receiver_interrupt, IRQF_ONESHOT,
1037+ "mhuv2-rx", mhu);
1038+ if (ret) {
1039+ dev_err(dev, "Failed to request rx IRQ\n");
1040+ return ret;
1041+ }
1042+
1043+ /* Mask all the channel windows */
1044+ for (i = 0; i < mhu->windows; i++)
1045+ writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set);
1046+
1047+ if (mhu->minor)
1048+ writel_relaxed_bitfield(1, &mhu->recv->int_en, chcomb);
1049+
1050+ return 0;
1051+}
1052+
1053+static int mhuv2_probe(struct amba_device *adev, const struct amba_id *id)
1054+{
1055+ struct device *dev = &adev->dev;
1056+ const struct device_node *np = dev->of_node;
1057+ struct mhuv2 *mhu;
1058+ void __iomem *reg;
1059+ int ret = -EINVAL;
1060+
1061+ reg = devm_of_iomap(dev, dev->of_node, 0, NULL);
1062+ if (!reg)
1063+ return -ENOMEM;
1064+
1065+ mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
1066+ if (!mhu)
1067+ return -ENOMEM;
1068+
1069+ mhu->mbox.dev = dev;
1070+ mhu->mbox.of_xlate = mhuv2_mbox_of_xlate;
1071+
1072+ if (of_device_is_compatible(np, "arm,mhuv2-tx"))
1073+ ret = mhuv2_tx_init(adev, mhu, reg);
1074+ else if (of_device_is_compatible(np, "arm,mhuv2-rx"))
1075+ ret = mhuv2_rx_init(adev, mhu, reg);
1076+ else
1077+ dev_err(dev, "Invalid compatible property\n");
1078+
1079+ if (ret)
1080+ return ret;
1081+
1082+ /* Channel windows can't be 0 */
1083+ BUG_ON(!mhu->windows);
1084+
1085+ ret = mhuv2_parse_channels(mhu);
1086+ if (ret)
1087+ return ret;
1088+
1089+ amba_set_drvdata(adev, mhu);
1090+
1091+ ret = devm_mbox_controller_register(dev, &mhu->mbox);
1092+ if (ret)
1093+ dev_err(dev, "failed to register ARM MHUv2 driver %d\n", ret);
1094+
1095+ return ret;
1096+}
1097+
1098+static int mhuv2_remove(struct amba_device *adev)
1099+{
1100+ struct mhuv2 *mhu = amba_get_drvdata(adev);
1101+
1102+ if (mhu->frame == SENDER_FRAME)
1103+ writel_relaxed(0x0, &mhu->send->access_request);
1104+
1105+ return 0;
1106+}
1107+
1108+static struct amba_id mhuv2_ids[] = {
1109+ {
1110+ /* 2.0 */
1111+ .id = 0xbb0d1,
1112+ .mask = 0xfffff,
1113+ },
1114+ {
1115+ /* 2.1 */
1116+ .id = 0xbb076,
1117+ .mask = 0xfffff,
1118+ },
1119+ { 0, 0 },
1120+};
1121+MODULE_DEVICE_TABLE(amba, mhuv2_ids);
1122+
1123+static struct amba_driver mhuv2_driver = {
1124+ .drv = {
1125+ .name = "arm-mhuv2",
1126+ },
1127+ .id_table = mhuv2_ids,
1128+ .probe = mhuv2_probe,
1129+ .remove = mhuv2_remove,
1130+};
1131+module_amba_driver(mhuv2_driver);
1132+
1133+MODULE_LICENSE("GPL v2");
1134+MODULE_DESCRIPTION("ARM MHUv2 Driver");
1135+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
1136+MODULE_AUTHOR("Tushar Khandelwal <tushar.khandelwal@arm.com>");
drivers/mailbox/stm32-ipcc.c+6−9
@@ -144,11 +144,11 @@ static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data) · 143 unmodified lines
144144
145145 static int stm32_ipcc_send_data(struct mbox_chan *link, void *data)
146146 {
147− unsigned int chan = (unsigned int)link->con_priv;
147+ unsigned long chan = (unsigned long)link->con_priv;
148148 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
149149 controller);
150150
151− dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);
151+ dev_dbg(ipcc->controller.dev, "%s: chan:%lu\n", __func__, chan);
152152
153153 /* set channel n occupied */
154154 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
@@ -163,7 +163,7 @@ static int stm32_ipcc_send_data(struct mbox_chan *link, void *data) · 8 unmodified lines
163163
164164 static int stm32_ipcc_startup(struct mbox_chan *link)
165165 {
166− unsigned int chan = (unsigned int)link->con_priv;
166+ unsigned long chan = (unsigned long)link->con_priv;
167167 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
168168 controller);
169169 int ret;
@@ -183,7 +183,7 @@ static int stm32_ipcc_startup(struct mbox_chan *link) · 13 unmodified lines
183183
184184 static void stm32_ipcc_shutdown(struct mbox_chan *link)
185185 {
186− unsigned int chan = (unsigned int)link->con_priv;
186+ unsigned long chan = (unsigned long)link->con_priv;
187187 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
188188 controller);
189189
@@ -206,7 +206,7 @@ static int stm32_ipcc_probe(struct platform_device *pdev) · 16 unmodified lines
206206 struct device_node *np = dev->of_node;
207207 struct stm32_ipcc *ipcc;
208208 struct resource *res;
209− unsigned int i;
209+ unsigned long i;
210210 int ret;
211211 u32 ip_ver;
212212 static const char * const irq_name[] = {"rx", "tx"};
@@ -257,9 +257,6 @@ static int stm32_ipcc_probe(struct platform_device *pdev) · 44 unmodified lines
257257 for (i = 0; i < IPCC_IRQ_NUM; i++) {
258258 ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);
259259 if (ipcc->irqs[i] < 0) {
260− if (ipcc->irqs[i] != -EPROBE_DEFER)
261− dev_err(dev, "no IRQ specified %s\n",
262− irq_name[i]);
263260 ret = ipcc->irqs[i];
264261 goto err_clk;
265262 }
@@ -268,7 +265,7 @@ static int stm32_ipcc_probe(struct platform_device *pdev) · 2 unmodified lines
268265 irq_thread[i], IRQF_ONESHOT,
269266 dev_name(dev), ipcc);
270267 if (ret) {
271− dev_err(dev, "failed to request irq %d (%d)\n", i, ret);
268+ dev_err(dev, "failed to request irq %lu (%d)\n", i, ret);
272269 goto err_clk;
273270 }
274271 }
include/linux/mailbox/arm_mhuv2_message.h+20−0
@@ -0,0 +1,20 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * ARM MHUv2 Mailbox Message
4+ *
5+ * Copyright (C) 2020 Arm Ltd.
6+ * Copyright (C) 2020 Linaro Ltd.
7+ */
8+
9+#ifndef _LINUX_ARM_MHUV2_MESSAGE_H_
10+#define _LINUX_ARM_MHUV2_MESSAGE_H_
11+
12+#include <linux/types.h>
13+
14+/* Data structure for data-transfer protocol */
15+struct arm_mhuv2_mbox_msg {
16+ void *data;
17+ size_t len;
18+};
19+
20+#endif /* _LINUX_ARM_MHUV2_MESSAGE_H_ */