History

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms and a couple of the small driver subsystems we merge through our tree: - A driver for SCU (system control) on NXP i.MX8QXP - Qualcomm Always-on Subsystem messaging driver (AOSS QMP) - Qualcomm PM support for MSM8998 - Support for a newer version of DRAM PHY driver for Broadcom (DPFE) - Reset controller support for Bitmain BM1880 - TI SCI (System Control Interface) support for CPU control on AM654 processors - More TI sysc refactoring and rework" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits) reset: remove redundant null check on pointer dev soc: rockchip: work around clang warning dt-bindings: reset: imx7: Fix the spelling of 'indices' soc: imx: Add i.MX8MN SoC driver support soc: aspeed: lpc-ctrl: Fix probe error handling soc: qcom: geni: Add support for ACPI firmware: ti_sci: Fix gcc unused-but-set-variable warning firmware: ti_sci: Use the correct style for SPDX License Identifier soc: imx8: Use existing of_root directly soc: imx8: Fix potential kernel dump in error path firmware/psci: psci_checker: Park kthreads before stopping them memory: move jedec_ddr.h from include/memory to drivers/memory/ memory: move jedec_ddr_data.c from lib/ to drivers/memory/ MAINTAINERS: Remove myself as qcom maintainer soc: aspeed: lpc-ctrl: make parameter optional soc: qcom: apr: Don't use reg for domain id soc: qcom: fix QCOM_AOSS_QMP dependency and build errors memory: tegra: Fix -Wunused-const-variable firmware: tegra: Early resume BPMP soc/tegra: Select pinctrl for Tegra194 ...

Linus Torvalds committed 7 years ago

Commit 8362fd62 parents 24e4491 8c0993670 files · +4760 −635Browse files

Showing the changes to include/linux (3 of 70 files). Show all

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3 files
  1. include/linux/platform_data/ti-sysc.h +12 −0
  2. include/linux/scmi_protocol.h +1 −0
  3. include/linux/soc/ti/ti_sci_protocol.h +246 −0
include/linux/platform_data/ti-sysc.h+12−0
@@ -19,6 +19,7 @@ enum ti_sysc_module_type { · 18 unmodified lines
1919
2020 struct ti_sysc_cookie {
2121 void *data;
22+ void *clkdm;
2223 };
2324
2425 /**
@@ -46,6 +47,10 @@ struct sysc_regbits { · 21 unmodified lines
4647 s8 emufree_shift;
4748 };
4849
50+#define SYSC_MODULE_QUIRK_HDQ1W BIT(17)
51+#define SYSC_MODULE_QUIRK_I2C BIT(16)
52+#define SYSC_MODULE_QUIRK_WDT BIT(15)
53+#define SYSS_QUIRK_RESETDONE_INVERTED BIT(14)
4954 #define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13)
5055 #define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12)
5156 #define SYSC_QUIRK_SWSUP_SIDLE BIT(11)
@@ -125,9 +130,16 @@ struct ti_sysc_module_data { · 73 unmodified lines
125130 };
126131
127132 struct device;
133+struct clk;
128134
129135 struct ti_sysc_platform_data {
130136 struct of_dev_auxdata *auxdata;
137+ int (*init_clockdomain)(struct device *dev, struct clk *fck,
138+ struct clk *ick, struct ti_sysc_cookie *cookie);
139+ void (*clkdm_deny_idle)(struct device *dev,
140+ const struct ti_sysc_cookie *cookie);
141+ void (*clkdm_allow_idle)(struct device *dev,
142+ const struct ti_sysc_cookie *cookie);
131143 int (*init_module)(struct device *dev,
132144 const struct ti_sysc_module_data *data,
133145 struct ti_sysc_cookie *cookie);
include/linux/scmi_protocol.h+1−0
@@ -144,6 +144,7 @@ struct scmi_power_ops { · 143 unmodified lines
144144 struct scmi_sensor_info {
145145 u32 id;
146146 u8 type;
147+ s8 scale;
147148 char name[SCMI_MAX_STR_SIZE];
148149 };
149150
include/linux/soc/ti/ti_sci_protocol.h+246−0
@@ -241,12 +241,254 @@ struct ti_sci_rm_irq_ops { · 240 unmodified lines
241241 u16 global_event, u8 vint_status_bit);
242242 };
243243
244+/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
245+#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
246+/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
247+#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
248+ /* RA config.count parameter is valid for RM ring configure TI_SCI message */
249+#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
250+/* RA config.mode parameter is valid for RM ring configure TI_SCI message */
251+#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
252+/* RA config.size parameter is valid for RM ring configure TI_SCI message */
253+#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
254+/* RA config.order_id parameter is valid for RM ring configure TISCI message */
255+#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
256+
257+#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
258+ (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
259+ TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
260+ TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
261+ TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
262+ TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
263+
264+/**
265+ * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
266+ * @config: configure the SoC Navigator Subsystem Ring Accelerator ring
267+ * @get_config: get the SoC Navigator Subsystem Ring Accelerator ring
268+ * configuration
269+ */
270+struct ti_sci_rm_ringacc_ops {
271+ int (*config)(const struct ti_sci_handle *handle,
272+ u32 valid_params, u16 nav_id, u16 index,
273+ u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
274+ u8 size, u8 order_id
275+ );
276+ int (*get_config)(const struct ti_sci_handle *handle,
277+ u32 nav_id, u32 index, u8 *mode,
278+ u32 *addr_lo, u32 *addr_hi, u32 *count,
279+ u8 *size, u8 *order_id);
280+};
281+
282+/**
283+ * struct ti_sci_rm_psil_ops - PSI-L thread operations
284+ * @pair: pair PSI-L source thread to a destination thread.
285+ * If the src_thread is mapped to UDMA tchan, the corresponding channel's
286+ * TCHAN_THRD_ID register is updated.
287+ * If the dst_thread is mapped to UDMA rchan, the corresponding channel's
288+ * RCHAN_THRD_ID register is updated.
289+ * @unpair: unpair PSI-L source thread from a destination thread.
290+ * If the src_thread is mapped to UDMA tchan, the corresponding channel's
291+ * TCHAN_THRD_ID register is cleared.
292+ * If the dst_thread is mapped to UDMA rchan, the corresponding channel's
293+ * RCHAN_THRD_ID register is cleared.
294+ */
295+struct ti_sci_rm_psil_ops {
296+ int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
297+ u32 src_thread, u32 dst_thread);
298+ int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
299+ u32 src_thread, u32 dst_thread);
300+};
301+
302+/* UDMAP channel types */
303+#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
304+#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */
305+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
306+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
307+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
308+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
309+
310+#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
311+#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
312+
313+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
314+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
315+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
316+
317+/* UDMAP TX/RX channel valid_params common declarations */
318+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
319+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
320+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
321+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
322+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
323+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
324+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
325+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
326+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
327+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
328+
329+/**
330+ * Configures a Navigator Subsystem UDMAP transmit channel
331+ *
332+ * Configures a Navigator Subsystem UDMAP transmit channel registers.
333+ * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
334+ */
335+struct ti_sci_msg_rm_udmap_tx_ch_cfg {
336+ u32 valid_params;
337+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
338+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
339+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
340+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
341+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
342+ u16 nav_id;
343+ u16 index;
344+ u8 tx_pause_on_err;
345+ u8 tx_filt_einfo;
346+ u8 tx_filt_pswords;
347+ u8 tx_atype;
348+ u8 tx_chan_type;
349+ u8 tx_supr_tdpkt;
350+ u16 tx_fetch_size;
351+ u8 tx_credit_count;
352+ u16 txcq_qnum;
353+ u8 tx_priority;
354+ u8 tx_qos;
355+ u8 tx_orderid;
356+ u16 fdepth;
357+ u8 tx_sched_priority;
358+ u8 tx_burst_size;
359+};
360+
361+/**
362+ * Configures a Navigator Subsystem UDMAP receive channel
363+ *
364+ * Configures a Navigator Subsystem UDMAP receive channel registers.
365+ * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
366+ */
367+struct ti_sci_msg_rm_udmap_rx_ch_cfg {
368+ u32 valid_params;
369+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
370+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
371+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
372+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
373+ u16 nav_id;
374+ u16 index;
375+ u16 rx_fetch_size;
376+ u16 rxcq_qnum;
377+ u8 rx_priority;
378+ u8 rx_qos;
379+ u8 rx_orderid;
380+ u8 rx_sched_priority;
381+ u16 flowid_start;
382+ u16 flowid_cnt;
383+ u8 rx_pause_on_err;
384+ u8 rx_atype;
385+ u8 rx_chan_type;
386+ u8 rx_ignore_short;
387+ u8 rx_ignore_long;
388+ u8 rx_burst_size;
389+};
390+
391+/**
392+ * Configures a Navigator Subsystem UDMAP receive flow
393+ *
394+ * Configures a Navigator Subsystem UDMAP receive flow's registers.
395+ * See @tis_ci_msg_rm_udmap_flow_cfg_req
396+ */
397+struct ti_sci_msg_rm_udmap_flow_cfg {
398+ u32 valid_params;
399+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
400+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
401+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
402+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
403+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
404+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
405+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
406+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
407+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
408+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
409+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
410+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
411+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
412+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
413+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
414+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
415+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
416+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
417+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
418+ u16 nav_id;
419+ u16 flow_index;
420+ u8 rx_einfo_present;
421+ u8 rx_psinfo_present;
422+ u8 rx_error_handling;
423+ u8 rx_desc_type;
424+ u16 rx_sop_offset;
425+ u16 rx_dest_qnum;
426+ u8 rx_src_tag_hi;
427+ u8 rx_src_tag_lo;
428+ u8 rx_dest_tag_hi;
429+ u8 rx_dest_tag_lo;
430+ u8 rx_src_tag_hi_sel;
431+ u8 rx_src_tag_lo_sel;
432+ u8 rx_dest_tag_hi_sel;
433+ u8 rx_dest_tag_lo_sel;
434+ u16 rx_fdq0_sz0_qnum;
435+ u16 rx_fdq1_qnum;
436+ u16 rx_fdq2_qnum;
437+ u16 rx_fdq3_qnum;
438+ u8 rx_ps_location;
439+};
440+
441+/**
442+ * struct ti_sci_rm_udmap_ops - UDMA Management operations
443+ * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
444+ * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
445+ * @rx_flow_cfg1: configure SoC Navigator Subsystem UDMA receive flow.
446+ */
447+struct ti_sci_rm_udmap_ops {
448+ int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
449+ const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
450+ int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
451+ const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
452+ int (*rx_flow_cfg)(const struct ti_sci_handle *handle,
453+ const struct ti_sci_msg_rm_udmap_flow_cfg *params);
454+};
455+
456+/**
457+ * struct ti_sci_proc_ops - Processor Control operations
458+ * @request: Request to control a physical processor. The requesting host
459+ * should be in the processor access list
460+ * @release: Relinquish a physical processor control
461+ * @handover: Handover a physical processor control to another host
462+ * in the permitted list
463+ * @set_config: Set base configuration of a processor
464+ * @set_control: Setup limited control flags in specific cases
465+ * @get_status: Get the state of physical processor
466+ *
467+ * NOTE: The following paramteres are generic in nature for all these ops,
468+ * -handle: Pointer to TI SCI handle as retrieved by *ti_sci_get_handle
469+ * -pid: Processor ID
470+ * -hid: Host ID
471+ */
472+struct ti_sci_proc_ops {
473+ int (*request)(const struct ti_sci_handle *handle, u8 pid);
474+ int (*release)(const struct ti_sci_handle *handle, u8 pid);
475+ int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid);
476+ int (*set_config)(const struct ti_sci_handle *handle, u8 pid,
477+ u64 boot_vector, u32 cfg_set, u32 cfg_clr);
478+ int (*set_control)(const struct ti_sci_handle *handle, u8 pid,
479+ u32 ctrl_set, u32 ctrl_clr);
480+ int (*get_status)(const struct ti_sci_handle *handle, u8 pid,
481+ u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags,
482+ u32 *status_flags);
483+};
484+
244485 /**
245486 * struct ti_sci_ops - Function support for TI SCI
246487 * @dev_ops: Device specific operations
247488 * @clk_ops: Clock specific operations
248489 * @rm_core_ops: Resource management core operations.
249490 * @rm_irq_ops: IRQ management specific operations
491+ * @proc_ops: Processor Control specific operations
250492 */
251493 struct ti_sci_ops {
252494 struct ti_sci_core_ops core_ops;
@@ -254,6 +496,10 @@ struct ti_sci_ops { · 1 unmodified line
254496 struct ti_sci_clk_ops clk_ops;
255497 struct ti_sci_rm_core_ops rm_core_ops;
256498 struct ti_sci_rm_irq_ops rm_irq_ops;
499+ struct ti_sci_rm_ringacc_ops rm_ring_ops;
500+ struct ti_sci_rm_psil_ops rm_psil_ops;
501+ struct ti_sci_rm_udmap_ops rm_udmap_ops;
502+ struct ti_sci_proc_ops proc_ops;
257503 };
258504
259505 /**