PCI defines display class VGA regions at I/O port address 0x3b0, 0x3c0 and MMIO address 0xa0000. As these are non-overlapping, we can ignore the I/O port vs MMIO difference and expose them both in a single region. We make use of the VGA arbiter around each access to configure chipset access as necessary.
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| @@ -303,6 +303,15 @@ enum { · 302 unmodified lines | |||
| 303 | VFIO_PCI_BAR5_REGION_INDEX, | 303 | VFIO_PCI_BAR5_REGION_INDEX, |
| 304 | VFIO_PCI_ROM_REGION_INDEX, | 304 | VFIO_PCI_ROM_REGION_INDEX, |
| 305 | VFIO_PCI_CONFIG_REGION_INDEX, | 305 | VFIO_PCI_CONFIG_REGION_INDEX, |
| 306 | /* | ||
| 307 | * Expose VGA regions defined for PCI base class 03, subclass 00. | ||
| 308 | * This includes I/O port ranges 0x3b0 to 0x3bb and 0x3c0 to 0x3df | ||
| 309 | * as well as the MMIO range 0xa0000 to 0xbffff. Each implemented | ||
| 310 | * range is found at it's identity mapped offset from the region | ||
| 311 | * offset, for example 0x3b0 is region_info.offset + 0x3b0. Areas | ||
| 312 | * between described ranges are unimplemented. | ||
| 313 | */ | ||
| 314 | VFIO_PCI_VGA_REGION_INDEX, | ||
| 306 | VFIO_PCI_NUM_REGIONS | 315 | VFIO_PCI_NUM_REGIONS |
| 307 | }; | 316 | }; |
| 308 | 317 | ||