History

Merge tag 'drm-next-2019-03-06' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie: "This is the main drm pull request for the 5.1 merge window. The big changes I'd highlight are: - nouveau has HMM support now, there is finally an in-tree user so we can quieten down the rip it out people. - i915 now enables fastboot by default on Skylake+ - Displayport Multistream support has been refactored and should hopefully be more reliable. Core: - header cleanups aiming towards removing drmP.h - dma-buf fence seqnos to 64-bits - common helper for DP mst hotplug for radeon,i915,amdgpu + new refcounting scheme - MST i2c improvements - drm_syncobj_cb removal - ARM FB compression fourcc - P010 + P016 fourcc - allwinner tiled format modifier - i2c over aux I2C_M_STOP support - DRM_AUTH handling fixes TTM: - ref/unref renaming New driver: - ARM komeda display driver scheduler: - refactor mirror list handling - rework hw fence processing - 0 run queue entity fix bridge: - TI DS90C185 LVDS bridge - thc631lvdm83d bridge improvements - cadence + allwinner DSI ported to generic phy panels: - Sitronix ST7701 panel - Kingdisplay KD097D04 - LeMaker BL035-RGB-002 - PDA 91-00156-A0 - Innolux EE101IA-01D i915: - Enable fastboot by default on SKL+/VLV/CHV - Export RPCS configuration for ICL media driver - Coffelake PCI ID - CNL clocks setup fixes - ACPI/PMIC support for MIPI/DSI - Per-engine WA init for all engines - Shrinker locking fixes - Kerneldoc updates - Lots of ring improvements and reset fixes - Coffeelake GVT Support - VFIO GVT EDID Region support - runtime PM wakeref tracking - ILK->IVB primary plane enable delays - userptr mutex locking fixes - DSI fixes - LVDS/TV cleanups - HW readout fixes - LUT robustness fixes - ICL display and watermark fixes - gem mmap race fix amdgpu: - add scheduled dependencies interface - DCC on scanout surfaces - vega10/20 BACO support - Multiple IH rings on soc15 - XGMI locking fixes - DC i2c/aux cleanups - runtime SMU debug interface - Kexec improvmeents - SR-IOV fixes - DC freesync + ABM fixes - GDS fixes - GPUVM fixes - vega20 PCIE DPM switching fixes - Context priority handling fixes radeon: - fix missing break in evergreen parser nouveau: - SVM support via HMM msm: - QCOM Compressed modifier support exynos: - s5pv210 rotator support imx: - zpos property support - pending update fixes v3d: - cache flush improvments vc4: - reflection support - HDMI overscan support tegra: - CEC refactoring - HDMI audio fixes - Tegra186 prep work - SOR crossbar device tree fixes sun4i: - implicit fencing support - YUV and scalar support improvements - A23 support - tiling fixes atmel-hlcdc: - clipping and rotation property fixes qxl: - BO and PRIME improvements - generic fbdev emulation dw-hdmi: - HDMI 2.0 2160p - YUV420 ouput rockchip: - implicit fencing support - reflection proerties virtio-gpu: - use generic fbdev emulation tilcdc: - cpufreq vs crtc init fix rcar-du: - R8A774C0 support - D3/E3 RGB output routing fixes and DPAD0 support - RA87744 LVDS support bochs: - atomic and generic fbdev emulation - ID mismatch error on bochs load meson: - remove firmware fbs" * tag 'drm-next-2019-03-06' of git://anongit.freedesktop.org/drm/drm: (1130 commits) drm/amd/display: Use vrr friendly pageflip throttling in DC. drm/imx: only send commit done event when all state has been applied drm/imx: allow building under COMPILE_TEST drm/imx: imx-tve: depend on COMMON_CLK drm/imx: ipuv3-plane: add zpos property drm/imx: ipuv3-plane: add function to query atomic update status gpu: ipu-v3: prg: add function to get channel configure status gpu: ipu-v3: pre: add double buffer status readback drm/amdgpu: Bump amdgpu version for context priority override. drm/amdgpu/powerplay: fix typo in BACO header guards drm/amdgpu/powerplay: fix return codes in BACO code drm/amdgpu: add missing license on baco files drm/bochs: Fix the ID mismatch error drm/nouveau/dmem: use dma addresses during migration copies drm/nouveau/dmem: use physical vram addresses during migration copies drm/nouveau/dmem: extend copy function to allow direct use of physical addresses drm/nouveau/svm: new ioctl to migrate process memory to GPU memory drm/nouveau/dmem: device memory helpers for SVM drm/nouveau/svm: initial support for shared virtual memory drm/nouveau: prepare for enabling svm with existing userspace interfaces ...

Linus Torvalds committed 7 years ago

Commit 851ca772 parents b5dd0c6 4b057e71141 files · +39562 −37911Browse files

Showing the changes to include/uapi (5 of 1141 files). Show all

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5 files
  1. include/uapi/drm/amdgpu_drm.h +8 −1
  2. include/uapi/drm/drm_fourcc.h +63 −0
  3. include/uapi/drm/i915_drm.h +64 −0
  4. include/uapi/drm/nouveau_drm.h +51 −0
  5. include/uapi/drm/v3d_drm.h +8 −0
include/uapi/drm/amdgpu_drm.h+8−1
@@ -272,13 +272,14 @@ union drm_amdgpu_vm { · 271 unmodified lines
272 272
273/* sched ioctl */273/* sched ioctl */
274#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1274#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
275#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
275 276
276struct drm_amdgpu_sched_in {277struct drm_amdgpu_sched_in {
277 /* AMDGPU_SCHED_OP_* */278 /* AMDGPU_SCHED_OP_* */
278 __u32 op;279 __u32 op;
279 __u32 fd;280 __u32 fd;
280 __s32 priority;281 __s32 priority;
281 __u32 flags;282 __u32 ctx_id;
282};283};
283 284
284union drm_amdgpu_sched {285union drm_amdgpu_sched {
@@ -523,6 +524,7 @@ struct drm_amdgpu_gem_va { · 238 unmodified lines
523#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04524#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
524#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05525#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
525#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06526#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
527#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
526 528
527struct drm_amdgpu_cs_chunk {529struct drm_amdgpu_cs_chunk {
528 __u32 chunk_id;530 __u32 chunk_id;
@@ -565,6 +567,11 @@ union drm_amdgpu_cs { · 36 unmodified lines
565 * caches (L2/vL1/sL1/I$). */567 * caches (L2/vL1/sL1/I$). */
566#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)568#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
567 569
570/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
571 * This will reset wave ID counters for the IB.
572 */
573#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
574
568struct drm_amdgpu_cs_chunk_ib {575struct drm_amdgpu_cs_chunk_ib {
569 __u32 _pad;576 __u32 _pad;
570 /** AMDGPU_IB_FLAG_* */577 /** AMDGPU_IB_FLAG_* */
include/uapi/drm/drm_fourcc.h+63−0
@@ -195,6 +195,27 @@ extern "C" { · 194 unmodified lines
195#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */195#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
196#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */196#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
197 197
198/*
199 * 2 plane YCbCr MSB aligned
200 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
201 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
202 */
203#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
204
205/*
206 * 2 plane YCbCr MSB aligned
207 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
208 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
209 */
210#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
211
212/*
213 * 2 plane YCbCr MSB aligned
214 * index 0 = Y plane, [15:0] Y little endian
215 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
216 */
217#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
218
198/*219/*
199 * 3 plane YCbCr220 * 3 plane YCbCr
200 * index 0: Y plane, [7:0] Y221 * index 0: Y plane, [7:0] Y
@@ -238,6 +259,8 @@ extern "C" { · 37 unmodified lines
238#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06259#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
239#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07260#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
240#define DRM_FORMAT_MOD_VENDOR_ARM 0x08261#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
262#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
263
241/* add more to the end as needed */264/* add more to the end as needed */
242 265
243#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)266#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
@@ -572,6 +595,9 @@ extern "C" { · 328 unmodified lines
572 * AFBC has several features which may be supported and/or used, which are595 * AFBC has several features which may be supported and/or used, which are
573 * represented using bits in the modifier. Not all combinations are valid,596 * represented using bits in the modifier. Not all combinations are valid,
574 * and different devices or use-cases may support different combinations.597 * and different devices or use-cases may support different combinations.
598 *
599 * Further information on the use of AFBC modifiers can be found in
600 * Documentation/gpu/afbc.rst
575 */601 */
576#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)602#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
577 603
@@ -581,10 +607,18 @@ extern "C" { · 3 unmodified lines
581 * Indicates the superblock size(s) used for the AFBC buffer. The buffer607 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
582 * size (in pixels) must be aligned to a multiple of the superblock size.608 * size (in pixels) must be aligned to a multiple of the superblock size.
583 * Four lowest significant bits(LSBs) are reserved for block size.609 * Four lowest significant bits(LSBs) are reserved for block size.
610 *
611 * Where one superblock size is specified, it applies to all planes of the
612 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
613 * the first applies to the Luma plane and the second applies to the Chroma
614 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
615 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
584 */616 */
585#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf617#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
586#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)618#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
587#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)619#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
620#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
621#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
588 622
589/*623/*
590 * AFBC lossless colorspace transform624 * AFBC lossless colorspace transform
@@ -644,6 +678,35 @@ extern "C" { · 53 unmodified lines
644 */678 */
645#define AFBC_FORMAT_MOD_SC (1ULL << 9)679#define AFBC_FORMAT_MOD_SC (1ULL << 9)
646 680
681/*
682 * AFBC double-buffer
683 *
684 * Indicates that the buffer is allocated in a layout safe for front-buffer
685 * rendering.
686 */
687#define AFBC_FORMAT_MOD_DB (1ULL << 10)
688
689/*
690 * AFBC buffer content hints
691 *
692 * Indicates that the buffer includes per-superblock content hints.
693 */
694#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
695
696/*
697 * Allwinner tiled modifier
698 *
699 * This tiling mode is implemented by the VPU found on all Allwinner platforms,
700 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
701 * planes.
702 *
703 * With this tiling, the luminance samples are disposed in tiles representing
704 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
705 * The pixel order in each tile is linear and the tiles are disposed linearly,
706 * both in row-major order.
707 */
708#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
709
647#if defined(__cplusplus)710#if defined(__cplusplus)
648}711}
649#endif712#endif
include/uapi/drm/i915_drm.h+64−0
@@ -1486,9 +1486,73 @@ struct drm_i915_gem_context_param { · 1485 unmodified lines
1486#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */1486#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1487#define I915_CONTEXT_DEFAULT_PRIORITY 01487#define I915_CONTEXT_DEFAULT_PRIORITY 0
1488#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */1488#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1489 /*
1490 * When using the following param, value should be a pointer to
1491 * drm_i915_gem_context_param_sseu.
1492 */
1493#define I915_CONTEXT_PARAM_SSEU 0x7
1489 __u64 value;1494 __u64 value;
1490};1495};
1491 1496
1497/**
1498 * Context SSEU programming
1499 *
1500 * It may be necessary for either functional or performance reason to configure
1501 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
1502 * Sub-slice/EU).
1503 *
1504 * This is done by configuring SSEU configuration using the below
1505 * @struct drm_i915_gem_context_param_sseu for every supported engine which
1506 * userspace intends to use.
1507 *
1508 * Not all GPUs or engines support this functionality in which case an error
1509 * code -ENODEV will be returned.
1510 *
1511 * Also, flexibility of possible SSEU configuration permutations varies between
1512 * GPU generations and software imposed limitations. Requesting such a
1513 * combination will return an error code of -EINVAL.
1514 *
1515 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
1516 * favour of a single global setting.
1517 */
1518struct drm_i915_gem_context_param_sseu {
1519 /*
1520 * Engine class & instance to be configured or queried.
1521 */
1522 __u16 engine_class;
1523 __u16 engine_instance;
1524
1525 /*
1526 * Unused for now. Must be cleared to zero.
1527 */
1528 __u32 flags;
1529
1530 /*
1531 * Mask of slices to enable for the context. Valid values are a subset
1532 * of the bitmask value returned for I915_PARAM_SLICE_MASK.
1533 */
1534 __u64 slice_mask;
1535
1536 /*
1537 * Mask of subslices to enable for the context. Valid values are a
1538 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
1539 */
1540 __u64 subslice_mask;
1541
1542 /*
1543 * Minimum/Maximum number of EUs to enable per subslice for the
1544 * context. min_eus_per_subslice must be inferior or equal to
1545 * max_eus_per_subslice.
1546 */
1547 __u16 min_eus_per_subslice;
1548 __u16 max_eus_per_subslice;
1549
1550 /*
1551 * Unused for now. Must be cleared to zero.
1552 */
1553 __u32 rsvd;
1554};
1555
1492enum drm_i915_oa_format {1556enum drm_i915_oa_format {
1493 I915_OA_FORMAT_A13 = 1, /* HSW only */1557 I915_OA_FORMAT_A13 = 1, /* HSW only */
1494 I915_OA_FORMAT_A29, /* HSW only */1558 I915_OA_FORMAT_A29, /* HSW only */
include/uapi/drm/nouveau_drm.h+51−0
@@ -133,12 +133,63 @@ struct drm_nouveau_gem_cpu_fini { · 132 unmodified lines
133#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */133#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
134#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */134#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
135#define DRM_NOUVEAU_NVIF 0x07135#define DRM_NOUVEAU_NVIF 0x07
136#define DRM_NOUVEAU_SVM_INIT 0x08
137#define DRM_NOUVEAU_SVM_BIND 0x09
136#define DRM_NOUVEAU_GEM_NEW 0x40138#define DRM_NOUVEAU_GEM_NEW 0x40
137#define DRM_NOUVEAU_GEM_PUSHBUF 0x41139#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
138#define DRM_NOUVEAU_GEM_CPU_PREP 0x42140#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
139#define DRM_NOUVEAU_GEM_CPU_FINI 0x43141#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
140#define DRM_NOUVEAU_GEM_INFO 0x44142#define DRM_NOUVEAU_GEM_INFO 0x44
141 143
144struct drm_nouveau_svm_init {
145 __u64 unmanaged_addr;
146 __u64 unmanaged_size;
147};
148
149struct drm_nouveau_svm_bind {
150 __u64 header;
151 __u64 va_start;
152 __u64 va_end;
153 __u64 npages;
154 __u64 stride;
155 __u64 result;
156 __u64 reserved0;
157 __u64 reserved1;
158};
159
160#define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
161#define NOUVEAU_SVM_BIND_COMMAND_BITS 8
162#define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
163#define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
164#define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
165#define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
166#define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
167#define NOUVEAU_SVM_BIND_TARGET_BITS 32
168#define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
169
170/*
171 * Below is use to validate ioctl argument, userspace can also use it to make
172 * sure that no bit are set beyond known fields for a given kernel version.
173 */
174#define NOUVEAU_SVM_BIND_VALID_BITS 48
175#define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
176
177
178/*
179 * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
180 * result: number of page successfuly migrate to the target memory.
181 */
182#define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
183
184/*
185 * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
186 */
187#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
188
189
190#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
191#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
192
142#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)193#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
143#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)194#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
144#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)195#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
include/uapi/drm/v3d_drm.h+8−0
@@ -52,6 +52,14 @@ extern "C" { · 51 unmodified lines
52 *52 *
53 * This asks the kernel to have the GPU execute an optional binner53 * This asks the kernel to have the GPU execute an optional binner
54 * command list, and a render command list.54 * command list, and a render command list.
55 *
56 * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
57 * each CL executes. The VCD cache should be flushed (if necessary)
58 * by the submitted CLs. The TLB writes are guaranteed to have been
59 * flushed by the time the render done IRQ happens, which is the
60 * trigger for out_sync. Any dirtying of cachelines by the job (only
61 * possible using TMU writes) must be flushed by the caller using the
62 * CL's cache flush commands.
55 */63 */
56struct drm_v3d_submit_cl {64struct drm_v3d_submit_cl {
57 /* Pointer to the binner command list.65 /* Pointer to the binner command list.

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