History

Merge drm/drm-next into drm-xe-next

Need to sync some header include that propagated through drm-intel-next. v2: After some changes in drm/drm-next

Rodrigo Vivi committed 2 years ago

Commit 8664e762 parents 33991ae 541b1b0616 files · +27860 −18095Browse files

Unified · Split

616 files
  1. Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml +0 −2
  2. Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml +77 −0
  3. Documentation/devicetree/bindings/display/panel/panel-edp-legacy.yaml +117 −0
  4. Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml +30 −0
  5. Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml +6 −0
  6. Documentation/devicetree/bindings/display/panel/panel-simple.yaml +2 −56
  7. Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml +95 −0
  8. Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.yaml +0 −30
  9. Documentation/devicetree/bindings/display/panel/wl-355608-a8.yaml +60 −0
  10. Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml +2 −0
  11. Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +4 −1
  12. Documentation/devicetree/bindings/vendor-prefixes.yaml +6 −0
  13. Documentation/gpu/drm-internals.rst +2 −8
  14. Documentation/gpu/drm-kms-helpers.rst +9 −3
  15. Documentation/gpu/i915.rst +1 −4
  16. Documentation/gpu/kms-properties.csv +0 −2
  17. Documentation/gpu/todo.rst +40 −30
  18. MAINTAINERS +6 −5
  19. arch/x86/kernel/early-quirks.c +42 −43
  20. drivers/accel/ivpu/Makefile +7 −4
  21. drivers/accel/ivpu/ivpu_debugfs.c +87 −2
  22. drivers/accel/ivpu/ivpu_drv.c +99 −14
  23. drivers/accel/ivpu/ivpu_drv.h +53 −9
  24. drivers/accel/ivpu/ivpu_fw.c +50 −11
  25. drivers/accel/ivpu/ivpu_fw.h +4 −0
  26. drivers/accel/ivpu/ivpu_gem.h +7 −4
  27. drivers/accel/ivpu/ivpu_hw.c +331 −0
  28. drivers/accel/ivpu/ivpu_hw.h +77 −122
  29. drivers/accel/ivpu/ivpu_hw_37xx.c +0 −1065
  30. drivers/accel/ivpu/ivpu_hw_37xx_reg.h +0 −72
  31. drivers/accel/ivpu/ivpu_hw_40xx.c +0 −1250
  32. drivers/accel/ivpu/ivpu_hw_40xx_reg.h +9 −85
  33. drivers/accel/ivpu/ivpu_hw_btrs.c +905 −0
  34. drivers/accel/ivpu/ivpu_hw_btrs.h +50 −0
  35. drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h +108 −0
  36. drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h +83 −0
  37. drivers/accel/ivpu/ivpu_hw_ip.c +1174 −0
  38. drivers/accel/ivpu/ivpu_hw_ip.h +36 −0
  39. drivers/accel/ivpu/ivpu_ipc.c +9 −11
  40. drivers/accel/ivpu/ivpu_ipc.h +5 −3
  41. drivers/accel/ivpu/ivpu_job.c +263 −61
  42. drivers/accel/ivpu/ivpu_job.h +5 −1
  43. drivers/accel/ivpu/ivpu_jsm_msg.c +294 −17
  44. drivers/accel/ivpu/ivpu_jsm_msg.h +21 −1
  45. drivers/accel/ivpu/ivpu_mmu.c +15 −7
  46. drivers/accel/ivpu/ivpu_mmu_context.c +86 −0
  47. drivers/accel/ivpu/ivpu_mmu_context.h +2 −0
  48. drivers/accel/ivpu/ivpu_ms.c +309 −0
  49. drivers/accel/ivpu/ivpu_ms.h +36 −0
  50. drivers/accel/ivpu/ivpu_pm.c +82 −29
  51. drivers/accel/ivpu/ivpu_pm.h +7 −3
  52. drivers/accel/ivpu/ivpu_sysfs.c +58 −0
  53. drivers/accel/ivpu/ivpu_sysfs.h +13 −0
  54. drivers/accel/ivpu/vpu_boot_api.h +14 −2
  55. drivers/accel/ivpu/vpu_jsm_api.h +11 −3
  56. drivers/char/agp/amd64-agp.c +1 −0
  57. drivers/char/agp/intel-agp.c +2 −1
  58. drivers/char/agp/intel-gtt.c +2 −1
  59. drivers/char/agp/sis-agp.c +1 −0
  60. drivers/char/agp/via-agp.c +1 −0
  61. drivers/dma-buf/dma-fence-array.c +4 −6
  62. drivers/dma-buf/dma-heap.c +2 −2
  63. drivers/dma-buf/dma-resv.c +7 −0
  64. drivers/dma-buf/heaps/cma_heap.c +2 −2
  65. drivers/dma-buf/heaps/system_heap.c +2 −2
  66. drivers/gpu/drm/Kconfig +15 −1
  67. drivers/gpu/drm/Makefile +3 −3
  68. drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +0 −16
  69. drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h +0 −1
  70. drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +3 −3
  71. drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +2 −6
  72. drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +2 −2
  73. drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +2 −2
  74. drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +2 −2
  75. drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +2 −2
  76. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +1 −1
  77. drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +35 −14
  78. drivers/gpu/drm/arm/display/komeda/komeda_drv.c +6 −2
  79. drivers/gpu/drm/arm/display/komeda/komeda_kms.h +1 −0
  80. drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c +2 −2
  81. drivers/gpu/drm/ast/ast_drv.c +2 −2
  82. drivers/gpu/drm/atmel-hlcdc/Kconfig +1 −1
  83. drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +141 −31
  84. drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +105 −0
  85. drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +108 −24
  86. drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +309 −60
  87. drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +0 −5
  88. drivers/gpu/drm/bridge/analogix/analogix-anx6345.c +7 −13
  89. drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c +12 −16
  90. drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +44 −128
  91. drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +2 −20
  92. drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +15 −104
  93. drivers/gpu/drm/bridge/analogix/anx7625.c +17 −19
  94. drivers/gpu/drm/bridge/analogix/anx7625.h +2 −8
  95. drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 −5
  96. drivers/gpu/drm/bridge/imx/imx-ldb-helper.c +0 −5
  97. drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c +0 −5
  98. drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c +0 −5
  99. drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c +0 −5
  100. drivers/gpu/drm/bridge/ite-it6505.c +50 −30
  101. drivers/gpu/drm/bridge/lontium-lt9611.c +1 −0
  102. drivers/gpu/drm/bridge/lontium-lt9611uxc.c +1 −5
  103. drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c +0 −5
  104. drivers/gpu/drm/bridge/nxp-ptn3460.c +0 −5
  105. drivers/gpu/drm/bridge/panel.c +0 −5
  106. drivers/gpu/drm/bridge/samsung-dsim.c +23 −2
  107. drivers/gpu/drm/bridge/sii902x.c +33 −13
  108. drivers/gpu/drm/bridge/sii9234.c +1 −0
  109. drivers/gpu/drm/bridge/sil-sii8620.c +1 −0
  110. drivers/gpu/drm/bridge/simple-bridge.c +1 −17
  111. drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +0 −5
  112. drivers/gpu/drm/bridge/tc358767.c +22 −5
  113. drivers/gpu/drm/bridge/ti-tfp410.c +0 −5
  114. drivers/gpu/drm/ci/build-igt.sh +40 −1
  115. drivers/gpu/drm/ci/build.sh +7 −3
  116. drivers/gpu/drm/ci/build.yml +1 −0
  117. drivers/gpu/drm/ci/container.yml +4 −8
  118. drivers/gpu/drm/ci/gitlab-ci.yml +32 −15
  119. drivers/gpu/drm/ci/igt_runner.sh +8 −7
  120. drivers/gpu/drm/ci/image-tags.yml +2 −2
  121. drivers/gpu/drm/ci/lava-submit.sh +2 −2
  122. drivers/gpu/drm/ci/test.yml +33 −8
  123. drivers/gpu/drm/ci/testlist.txt +0 −2761
  124. drivers/gpu/drm/ci/x86_64.config +1 −0
  125. drivers/gpu/drm/ci/xfails/amdgpu-stoney-fails.txt +27 −14
  126. drivers/gpu/drm/ci/xfails/amdgpu-stoney-flakes.txt +7 −0
  127. drivers/gpu/drm/ci/xfails/amdgpu-stoney-skips.txt +32 −1
  128. drivers/gpu/drm/ci/xfails/i915-amly-fails.txt +31 −0
  129. drivers/gpu/drm/ci/xfails/i915-amly-flakes.txt +9 −0
  130. drivers/gpu/drm/ci/xfails/i915-amly-skips.txt +21 −1
  131. drivers/gpu/drm/ci/xfails/i915-apl-fails.txt +26 −20
  132. drivers/gpu/drm/ci/xfails/i915-apl-flakes.txt +6 −0
  133. drivers/gpu/drm/ci/xfails/i915-apl-skips.txt +25 −1
  134. drivers/gpu/drm/ci/xfails/i915-cml-fails.txt +38 −0
  135. drivers/gpu/drm/ci/xfails/i915-cml-flakes.txt +6 −0
  136. drivers/gpu/drm/ci/xfails/i915-cml-skips.txt +23 −0
  137. drivers/gpu/drm/ci/xfails/i915-glk-fails.txt +34 −7
  138. drivers/gpu/drm/ci/xfails/i915-glk-flakes.txt +7 −0
  139. drivers/gpu/drm/ci/xfails/i915-glk-skips.txt +25 −1
  140. drivers/gpu/drm/ci/xfails/i915-kbl-fails.txt +19 −23
  141. drivers/gpu/drm/ci/xfails/i915-kbl-flakes.txt +6 −1
  142. drivers/gpu/drm/ci/xfails/i915-kbl-skips.txt +35 −1
  143. drivers/gpu/drm/ci/xfails/i915-tgl-fails.txt +42 −35
  144. drivers/gpu/drm/ci/xfails/i915-tgl-skips.txt +27 −1
  145. drivers/gpu/drm/ci/xfails/i915-whl-fails.txt +40 −23
  146. drivers/gpu/drm/ci/xfails/i915-whl-flakes.txt +6 −0
  147. drivers/gpu/drm/ci/xfails/i915-whl-skips.txt +21 −1
  148. drivers/gpu/drm/ci/xfails/mediatek-mt8173-fails.txt +12 −18
  149. drivers/gpu/drm/ci/xfails/mediatek-mt8173-flakes.txt +11 −0
  150. drivers/gpu/drm/ci/xfails/mediatek-mt8173-skips.txt +16 −0
  151. drivers/gpu/drm/ci/xfails/mediatek-mt8183-fails.txt +8 −13
  152. drivers/gpu/drm/ci/xfails/mediatek-mt8183-skips.txt +18 −0
  153. drivers/gpu/drm/ci/xfails/meson-g12b-fails.txt +8 −16
  154. drivers/gpu/drm/ci/xfails/meson-g12b-skips.txt +18 −0
  155. drivers/gpu/drm/ci/xfails/msm-apq8016-fails.txt +11 −15
  156. drivers/gpu/drm/ci/xfails/msm-apq8016-skips.txt +15 −0
  157. drivers/gpu/drm/ci/xfails/msm-apq8096-fails.txt +7 −1
  158. drivers/gpu/drm/ci/xfails/msm-apq8096-flakes.txt +6 −0
  159. drivers/gpu/drm/ci/xfails/msm-apq8096-skips.txt +25 −1
  160. drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-fails.txt +174 −1
  161. drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-flakes.txt +8 −0
  162. drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-skips.txt +19 −0
  163. drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-fails.txt +174 −1
  164. drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-flakes.txt +6 −0
  165. drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-skips.txt +16 −0
  166. drivers/gpu/drm/ci/xfails/msm-sdm845-fails.txt +7 −31
  167. drivers/gpu/drm/ci/xfails/msm-sdm845-flakes.txt +11 −14
  168. drivers/gpu/drm/ci/xfails/msm-sdm845-skips.txt +19 −0
  169. drivers/gpu/drm/ci/xfails/rockchip-rk3288-fails.txt +8 −54
  170. drivers/gpu/drm/ci/xfails/rockchip-rk3288-skips.txt +20 −1
  171. drivers/gpu/drm/ci/xfails/rockchip-rk3399-fails.txt +8 −75
  172. drivers/gpu/drm/ci/xfails/rockchip-rk3399-flakes.txt +6 −7
  173. drivers/gpu/drm/ci/xfails/rockchip-rk3399-skips.txt +19 −0
  174. drivers/gpu/drm/ci/xfails/update-xfails.py +2 −2
  175. drivers/gpu/drm/ci/xfails/virtio_gpu-none-fails.txt +68 −26
  176. drivers/gpu/drm/ci/xfails/virtio_gpu-none-skips.txt +19 −1
  177. drivers/gpu/drm/ci/xfails/vkms-none-fails.txt +57 −0
  178. drivers/gpu/drm/ci/xfails/vkms-none-flakes.txt +69 −0
  179. drivers/gpu/drm/ci/xfails/vkms-none-skips.txt +119 −0
  180. drivers/gpu/drm/display/Kconfig +7 −0
  181. drivers/gpu/drm/display/Makefile +2 −0
  182. drivers/gpu/drm/display/drm_hdmi_helper.c +61 −0
  183. drivers/gpu/drm/display/drm_hdmi_state_helper.c +752 −0
  184. drivers/gpu/drm/drm_atomic.c +11 −0
  185. drivers/gpu/drm/drm_atomic_uapi.c +4 −0
  186. drivers/gpu/drm/drm_bridge.c +0 −42
  187. drivers/gpu/drm/drm_bridge_connector.c +91 −16
  188. drivers/gpu/drm/drm_connector.c +201 −0
  189. drivers/gpu/drm/drm_crtc_internal.h +2 −0
  190. drivers/gpu/drm/drm_debugfs.c +156 −2
  191. drivers/gpu/drm/drm_drv.c +3 −3
  192. drivers/gpu/drm/drm_edid.c +33 −28
  193. drivers/gpu/drm/drm_fb_helper.c +2 −9
  194. drivers/gpu/drm/drm_fbdev_dma.c +52 −14
  195. drivers/gpu/drm/drm_fbdev_shmem.c +317 −0
  196. drivers/gpu/drm/drm_fbdev_ttm.c +40 −40
  197. drivers/gpu/drm/drm_ioctl.c +3 −2
  198. drivers/gpu/drm/drm_mipi_dbi.c +54 −23
  199. drivers/gpu/drm/drm_mipi_dsi.c +322 −0
  200. drivers/gpu/drm/drm_mm.c +0 −35
  201. drivers/gpu/drm/drm_mode_object.c +1 −0
  202. drivers/gpu/drm/drm_modes.c +4 −1
  203. drivers/gpu/drm/drm_panel_orientation_quirks.c +1 −0
  204. drivers/gpu/drm/drm_panic.c +200 −84
  205. drivers/gpu/drm/drm_print.c +30 −42
  206. drivers/gpu/drm/drm_probe_helper.c +7 −6
  207. drivers/gpu/drm/drm_simple_kms_helper.c +1 −0
  208. drivers/gpu/drm/drm_sysfs.c +2 −22
  209. drivers/gpu/drm/gma500/cdv_intel_dp.c +1 −1
  210. drivers/gpu/drm/gud/gud_drv.c +3 −2
  211. drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +2 −2
  212. drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c +10 −7
  213. drivers/gpu/drm/hisilicon/kirin/Kconfig +1 −1
  214. drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c +5 −6
  215. drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h +2 −0
  216. drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h +1 −1
  217. drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c +2 −2
  218. drivers/gpu/drm/hyperv/hyperv_drm_drv.c +2 −2
  219. drivers/gpu/drm/i2c/tda998x_drv.c +10 −9
  220. drivers/gpu/drm/i915/Kconfig +0 −1
  221. drivers/gpu/drm/i915/Makefile +3 −24
  222. drivers/gpu/drm/i915/display/dvo_ns2501.c +0 −1
  223. drivers/gpu/drm/i915/display/g4x_dp.c +16 −21
  224. drivers/gpu/drm/i915/display/i9xx_plane.c +58 −46
  225. drivers/gpu/drm/i915/display/i9xx_plane_regs.h +112 −0
  226. drivers/gpu/drm/i915/display/i9xx_wm.c +57 −57
  227. drivers/gpu/drm/i915/display/icl_dsi.c +29 −17
  228. drivers/gpu/drm/i915/display/intel_alpm.c +414 −0
  229. drivers/gpu/drm/i915/display/intel_alpm.h +27 −0
  230. drivers/gpu/drm/i915/display/intel_atomic.c +0 −1
  231. drivers/gpu/drm/i915/display/intel_atomic_plane.c +44 −18
  232. drivers/gpu/drm/i915/display/intel_atomic_plane.h +1 −0
  233. drivers/gpu/drm/i915/display/intel_audio.c +16 −1
  234. drivers/gpu/drm/i915/display/intel_audio_regs.h +3 −0
  235. drivers/gpu/drm/i915/display/intel_bios.c +129 −114
  236. drivers/gpu/drm/i915/display/intel_bw.c +63 −2
  237. drivers/gpu/drm/i915/display/intel_cdclk.c +51 −79
  238. drivers/gpu/drm/i915/display/intel_color.c +88 −55
  239. drivers/gpu/drm/i915/display/intel_color.h +3 −1
  240. drivers/gpu/drm/i915/display/intel_color_regs.h +5 −0
  241. drivers/gpu/drm/i915/display/intel_crt.c +31 −19
  242. drivers/gpu/drm/i915/display/intel_crtc.c +6 −9
  243. drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +8 −7
  244. drivers/gpu/drm/i915/display/intel_cursor.c +80 −22
  245. drivers/gpu/drm/i915/display/intel_cursor_regs.h +112 −0
  246. drivers/gpu/drm/i915/display/intel_cx0_phy.c +323 −45
  247. drivers/gpu/drm/i915/display/intel_cx0_phy.h +4 −4
  248. drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +40 −8
  249. drivers/gpu/drm/i915/display/intel_ddi.c +65 −64
  250. drivers/gpu/drm/i915/display/intel_display.c +466 −357
  251. drivers/gpu/drm/i915/display/intel_display.h +8 −5
  252. drivers/gpu/drm/i915/display/intel_display_debugfs.c +8 −4
  253. drivers/gpu/drm/i915/display/intel_display_device.c +654 −283
  254. drivers/gpu/drm/i915/display/intel_display_device.h +88 −1
  255. drivers/gpu/drm/i915/display/intel_display_irq.c +29 −17
  256. drivers/gpu/drm/i915/display/intel_display_limits.h +14 −7
  257. drivers/gpu/drm/i915/display/intel_display_params.c +1 −1
  258. drivers/gpu/drm/i915/display/intel_display_power.c +12 −8
  259. drivers/gpu/drm/i915/display/intel_display_power_well.c +7 −7
  260. drivers/gpu/drm/i915/display/intel_display_types.h +62 −25
  261. drivers/gpu/drm/i915/display/intel_dkl_phy.c +0 −1
  262. drivers/gpu/drm/i915/display/intel_dmc.c +14 −7
  263. drivers/gpu/drm/i915/display/intel_dmc.h +3 −3
  264. drivers/gpu/drm/i915/display/intel_dp.c +248 −166
  265. drivers/gpu/drm/i915/display/intel_dp.h +15 −9
  266. drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +130 −19
  267. drivers/gpu/drm/i915/display/intel_dp_aux_regs.h +14 −4
  268. drivers/gpu/drm/i915/display/intel_dp_hdcp.c +3 −2
  269. drivers/gpu/drm/i915/display/intel_dp_link_training.c +527 −11
  270. drivers/gpu/drm/i915/display/intel_dp_link_training.h +7 −1
  271. drivers/gpu/drm/i915/display/intel_dp_mst.c +48 −36
  272. drivers/gpu/drm/i915/display/intel_dpll.c +34 −29
  273. drivers/gpu/drm/i915/display/intel_dpll_mgr.h +1 −0
  274. drivers/gpu/drm/i915/display/intel_dpt.c +5 −4
  275. drivers/gpu/drm/i915/display/intel_dpt.h +3 −2
  276. drivers/gpu/drm/i915/display/intel_dpt_common.c +1 −0
  277. drivers/gpu/drm/i915/display/intel_drrs.c +4 −4
  278. drivers/gpu/drm/i915/display/intel_dsb.c +10 −21
  279. drivers/gpu/drm/i915/display/intel_dsb.h +9 −0
  280. drivers/gpu/drm/i915/display/intel_dsi_vbt.c +3 −3
  281. drivers/gpu/drm/i915/display/intel_dvo.c +3 −2
  282. drivers/gpu/drm/i915/display/intel_encoder.c +39 −0
  283. drivers/gpu/drm/i915/display/intel_encoder.h +16 −0
  284. drivers/gpu/drm/i915/display/intel_fb.c +30 −15
  285. drivers/gpu/drm/i915/display/intel_fb_pin.c +35 −40
  286. drivers/gpu/drm/i915/display/intel_fb_pin.h +6 −6
  287. drivers/gpu/drm/i915/display/intel_fbc.c +16 −22
  288. drivers/gpu/drm/i915/display/intel_fbdev.c +21 −19
  289. drivers/gpu/drm/i915/display/intel_fbdev_fb.c +3 −3
  290. drivers/gpu/drm/i915/display/intel_fbdev_fb.h +2 −2
  291. drivers/gpu/drm/i915/display/intel_fdi.c +8 −7
  292. drivers/gpu/drm/i915/display/intel_fifo_underrun.c +8 −5
  293. drivers/gpu/drm/i915/display/intel_frontbuffer.c +2 −0
  294. drivers/gpu/drm/i915/display/intel_hdcp.c +26 −1
  295. drivers/gpu/drm/i915/display/intel_hdcp_gsc.c +1 −1
  296. drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c +1 −1
  297. drivers/gpu/drm/i915/display/intel_hdmi.c +23 −18
  298. drivers/gpu/drm/i915/display/intel_hotplug_irq.c +8 −4
  299. drivers/gpu/drm/i915/display/intel_lpe_audio.c +1 −1
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  614. include/uapi/linux/dma-heap.h +1 −1
  615. lib/fonts/Kconfig +10 −10
  616. sound/x86/intel_hdmi_audio.c +1 −1
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml+0−2
@@ -32,8 +32,6 @@ properties: · 31 unmodified lines
32 - innolux,hj110iz-01a32 - innolux,hj110iz-01a
33 # STARRY 2081101QFH032011-53G 10.1" WUXGA TFT LCD panel33 # STARRY 2081101QFH032011-53G 10.1" WUXGA TFT LCD panel
34 - starry,2081101qfh032011-53g34 - starry,2081101qfh032011-53g
35 # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel
36 - starry,himax83102-j02
37 # STARRY ili9882t 10.51" WUXGA TFT LCD panel35 # STARRY ili9882t 10.51" WUXGA TFT LCD panel
38 - starry,ili9882t36 - starry,ili9882t
39 37
Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml+77−0
@@ -0,0 +1,77 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/panel/himax,hx83102.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Himax HX83102 MIPI-DSI LCD panel controller
8
9maintainers:
10 - Cong Yang <yangcong5@huaqin.corp-partner.google.com>
11
12allOf:
13 - $ref: panel-common.yaml#
14
15properties:
16 compatible:
17 items:
18 - enum:
19 # Boe nv110wum-l60 11.0" WUXGA TFT LCD panel
20 - boe,nv110wum-l60
21 # IVO t109nw41 11.0" WUXGA TFT LCD panel
22 - ivo,t109nw41
23 # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel
24 - starry,himax83102-j02
25 - const: himax,hx83102
26
27 reg:
28 description: the virtual channel number of a DSI peripheral
29
30 enable-gpios:
31 description: a GPIO spec for the enable pin
32
33 pp1800-supply:
34 description: core voltage supply
35
36 avdd-supply:
37 description: phandle of the regulator that provides positive voltage
38
39 avee-supply:
40 description: phandle of the regulator that provides negative voltage
41
42 backlight: true
43 port: true
44 rotation: true
45
46required:
47 - compatible
48 - reg
49 - enable-gpios
50 - pp1800-supply
51 - avdd-supply
52 - avee-supply
53
54additionalProperties: false
55
56examples:
57 - |
58 dsi {
59 #address-cells = <1>;
60 #size-cells = <0>;
61 panel@0 {
62 compatible = "starry,himax83102-j02", "himax,hx83102";
63 reg = <0>;
64 enable-gpios = <&pio 45 0>;
65 avdd-supply = <&ppvarn_lcd>;
66 avee-supply = <&ppvarp_lcd>;
67 pp1800-supply = <&pp1800_lcd>;
68 backlight = <&backlight_lcd0>;
69 port {
70 panel_in: endpoint {
71 remote-endpoint = <&dsi_out>;
72 };
73 };
74 };
75 };
76
77...
Documentation/devicetree/bindings/display/panel/panel-edp-legacy.yaml+117−0
@@ -0,0 +1,117 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/panel/panel-edp-legacy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Legacy eDP panels from before the "edp-panel" compatible
8
9maintainers:
10 - Douglas Anderson <dianders@chromium.org>
11
12description: |
13 This binding file is a collection of eDP panels from before the generic
14 "edp-panel" compatible was introduced. It is kept around to support old
15 dts files. The only reason one might add a new panel here instead of using
16 the generic "edp-panel" is if it needed to be used on an eDP controller
17 that doesn't support the generic "edp-panel" compatible, but it should be
18 a strong preference to add the generic "edp-panel" compatible instead.
19
20allOf:
21 - $ref: panel-common.yaml#
22
23properties:
24 compatible:
25 enum:
26 # compatible must be listed in alphabetical order, ordered by compatible.
27 # The description in the comment is mandatory for each compatible.
28
29 # AU Optronics Corporation 10.1" WSVGA TFT LCD panel
30 - auo,b101ean01
31 # AUO B116XAK01 eDP TFT LCD panel
32 - auo,b116xa01
33 # AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
34 - auo,b133htn01
35 # AU Optronics Corporation 13.3" WXGA (1366x768) TFT LCD panel
36 - auo,b133xtn01
37 # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
38 - boe,nv101wxmn51
39 # BOE NV133FHM-N61 13.3" FHD (1920x1080) TFT LCD Panel
40 - boe,nv110wtm-n61
41 # BOE NV110WTM-N61 11.0" 2160x1440 TFT LCD Panel
42 - boe,nv133fhm-n61
43 # BOE NV133FHM-N62 13.3" FHD (1920x1080) TFT LCD Panel
44 - boe,nv133fhm-n62
45 # BOE NV140FHM-N49 14.0" FHD a-Si FT panel
46 - boe,nv140fhmn49
47 # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
48 - innolux,n116bca-ea1
49 # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
50 - innolux,n116bge
51 # InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel
52 - innolux,n125hce-gn1
53 # Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel
54 - innolux,p120zdg-bf1
55 # King & Display KD116N21-30NV-A010 eDP TFT LCD panel
56 - kingdisplay,kd116n21-30nv-a010
57 # LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel
58 - lg,lp079qx1-sp0v
59 # LG 9.7" (2048x1536 pixels) TFT LCD panel
60 - lg,lp097qx1-spa1
61 # LG 12.0" (1920x1280 pixels) TFT LCD panel
62 - lg,lp120up1
63 # LG 12.9" (2560x1700 pixels) TFT LCD panel
64 - lg,lp129qe
65 # NewEast Optoelectronics CO., LTD WJFH116008A eDP TFT LCD panel
66 - neweast,wjfh116008a
67 # Samsung 12.2" (2560x1600 pixels) TFT LCD panel
68 - samsung,lsn122dl01-c01
69 # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel
70 - samsung,ltn140at29-301
71 # Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel
72 - sharp,ld-d5116z01b
73 # Sharp 12.3" (2400x1600 pixels) TFT LCD panel
74 - sharp,lq123p1jx31
75
76 backlight: true
77 ddc-i2c-bus: true
78 enable-gpios: true
79 panel-timing: true
80 port: true
81 power-supply: true
82 no-hpd: true
83 hpd-gpios: true
84
85additionalProperties: false
86
87required:
88 - compatible
89 - power-supply
90
91examples:
92 - |
93 panel: panel {
94 compatible = "innolux,n116bge";
95 power-supply = <&panel_regulator>;
96 backlight = <&backlight>;
97
98 panel-timing {
99 clock-frequency = <74250000>;
100 hactive = <1366>;
101 hfront-porch = <136>;
102 hback-porch = <60>;
103 hsync-len = <30>;
104 hsync-active = <0>;
105 vactive = <768>;
106 vfront-porch = <8>;
107 vback-porch = <12>;
108 vsync-len = <12>;
109 vsync-active = <0>;
110 };
111
112 port {
113 panel_in_edp: endpoint {
114 remote-endpoint = <&edp_out_panel>;
115 };
116 };
117 };
Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml+30−0
@@ -50,6 +50,12 @@ description: | · 49 unmodified lines
50 | Command or data |50 | Command or data |
51 |<D7><D6><D5><D4><D3><D2><D1><D0>|51 |<D7><D6><D5><D4><D3><D2><D1><D0>|
52 52
53 The standard defines one pixel format for type C: RGB111. The industry
54 however has decided to provide the type A/B interface pixel formats also on
55 the Type C interface and most common among these are RGB565 and RGB666.
56 The MIPI DCS command set_address_mode (36h) has one bit that controls RGB/BGR
57 order. This gives each supported RGB format a BGR variant.
58
53 The panel resolution is specified using the panel-timing node properties59 The panel resolution is specified using the panel-timing node properties
54 hactive (width) and vactive (height). The other mandatory panel-timing60 hactive (width) and vactive (height). The other mandatory panel-timing
55 properties should be set to zero except clock-frequency which can be61 properties should be set to zero except clock-frequency which can be
@@ -93,6 +99,28 @@ properties: · 37 unmodified lines
93 99
94 spi-3wire: true100 spi-3wire: true
95 101
102 format:
103 description: >
104 Pixel format in bit order as going on the wire:
105 * `x2r1g1b1r1g1b1` - RGB111, 2 pixels per byte
106 * `x2b1g1r1b1g1r1` - BGR111, 2 pixels per byte
107 * `x1r1g1b1x1r1g1b1` - RGB111, 2 pixels per byte
108 * `x1b1g1r1x1b1g1r1` - BGR111, 2 pixels per byte
109 * `r5g6b5` - RGB565, 2 bytes
110 * `b5g6r5` - BGR565, 2 bytes
111 * `r6x2g6x2b6x2` - RGB666, 3 bytes
112 * `b6x2g6x2r6x2` - BGR666, 3 bytes
113 enum:
114 - x2r1g1b1r1g1b1
115 - x2b1g1r1b1g1r1
116 - x1r1g1b1x1r1g1b1
117 - x1b1g1r1x1b1g1r1
118 - r5g6b5
119 - b5g6r5
120 - r6x2g6x2b6x2
121 - b6x2g6x2r6x2
122 default: r5g6b5
123
96required:124required:
97 - compatible125 - compatible
98 - reg126 - reg
@@ -119,6 +147,8 @@ examples: · 20 unmodified lines
119 reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;147 reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
120 write-only;148 write-only;
121 149
150 format = "r5g6b5";
151
122 backlight = <&backlight>;152 backlight = <&backlight>;
123 153
124 width-mm = <35>;154 width-mm = <35>;
Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml+6−0
@@ -41,6 +41,12 @@ properties: · 40 unmodified lines
41 - auo,g190ean0141 - auo,g190ean01
42 # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel42 # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel
43 - koe,tx26d202vm0bwa43 - koe,tx26d202vm0bwa
44 # Lincoln Technology Solutions, LCD185-101CT 10.1" TFT 1920x1200
45 - lincolntech,lcd185-101ct
46 # Microtips Technology MF-101HIEBCAF0 10.1" WUXGA (1920x1200) TFT LCD panel
47 - microtips,mf-101hiebcaf0
48 # Microtips Technology MF-103HIEB0GA0 10.25" 1920x720 TFT LCD panel
49 - microtips,mf-103hieb0ga0
44 # NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel50 # NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel
45 - nlt,nl192108ac18-02d51 - nlt,nl192108ac18-02d
46 52
Documentation/devicetree/bindings/display/panel/panel-simple.yaml+2−56
@@ -41,22 +41,10 @@ properties: · 40 unmodified lines
41 - ampire,am800600p5tmqw-tb8h41 - ampire,am800600p5tmqw-tb8h
42 # AU Optronics Corporation 10.1" WSVGA TFT LCD panel42 # AU Optronics Corporation 10.1" WSVGA TFT LCD panel
43 - auo,b101aw0343 - auo,b101aw03
44 # AU Optronics Corporation 10.1" WSVGA TFT LCD panel
45 - auo,b101ean01
46 # AU Optronics Corporation 10.1" WXGA TFT LCD panel44 # AU Optronics Corporation 10.1" WXGA TFT LCD panel
47 - auo,b101xtn0145 - auo,b101xtn01
48 # AUO B116XAK01 eDP TFT LCD panel
49 - auo,b116xa01
50 # AU Optronics Corporation 11.6" HD (1366x768) color TFT-LCD panel46 # AU Optronics Corporation 11.6" HD (1366x768) color TFT-LCD panel
51 - auo,b116xw0347 - auo,b116xw03
52 # AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
53 - auo,b133han05
54 # AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
55 - auo,b133htn01
56 # AU Optronics Corporation 13.3" WXGA (1366x768) TFT LCD panel
57 - auo,b133xtn01
58 # AU Optronics Corporation 14.0" FHD (1920x1080) color TFT-LCD panel
59 - auo,b140han06
60 # AU Optronics Corporation 7.0" FHD (800 x 480) TFT LCD panel48 # AU Optronics Corporation 7.0" FHD (800 x 480) TFT LCD panel
61 - auo,g070vvn0149 - auo,g070vvn01
62 # AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel50 # AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel
@@ -81,16 +69,6 @@ properties: · 18 unmodified lines
81 - boe,ev121wxm-n10-185069 - boe,ev121wxm-n10-1850
82 # BOE HV070WSA-100 7.01" WSVGA TFT LCD panel70 # BOE HV070WSA-100 7.01" WSVGA TFT LCD panel
83 - boe,hv070wsa-10071 - boe,hv070wsa-100
84 # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
85 - boe,nv101wxmn51
86 # BOE NV133FHM-N61 13.3" FHD (1920x1080) TFT LCD Panel
87 - boe,nv110wtm-n61
88 # BOE NV110WTM-N61 11.0" 2160x1440 TFT LCD Panel
89 - boe,nv133fhm-n61
90 # BOE NV133FHM-N62 13.3" FHD (1920x1080) TFT LCD Panel
91 - boe,nv133fhm-n62
92 # BOE NV140FHM-N49 14.0" FHD a-Si FT panel
93 - boe,nv140fhmn49
94 # Crystal Clear Technology CMT430B19N00 4.3" 480x272 TFT-LCD panel72 # Crystal Clear Technology CMT430B19N00 4.3" 480x272 TFT-LCD panel
95 - cct,cmt430b19n0073 - cct,cmt430b19n00
96 # CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel74 # CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel
@@ -172,8 +150,6 @@ properties: · 75 unmodified lines
172 - hannstar,hsd100pxn1150 - hannstar,hsd100pxn1
173 # Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel151 # Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel
174 - hit,tx23d38vm0caa152 - hit,tx23d38vm0caa
175 # InfoVision Optoelectronics M133NWF4 R0 13.3" FHD (1920x1080) TFT LCD panel
176 - ivo,m133nwf4-r0
177 # Innolux AT043TN24 4.3" WQVGA TFT LCD panel153 # Innolux AT043TN24 4.3" WQVGA TFT LCD panel
178 - innolux,at043tn24154 - innolux,at043tn24
179 # Innolux AT070TN92 7.0" WQVGA TFT LCD panel155 # Innolux AT070TN92 7.0" WQVGA TFT LCD panel
@@ -192,22 +168,12 @@ properties: · 12 unmodified lines
192 - innolux,g121x1-l03168 - innolux,g121x1-l03
193 # Innolux Corporation 12.1" G121XCE-L01 XGA (1024x768) TFT LCD panel169 # Innolux Corporation 12.1" G121XCE-L01 XGA (1024x768) TFT LCD panel
194 - innolux,g121xce-l01170 - innolux,g121xce-l01
195 # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
196 - innolux,n116bca-ea1
197 # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
198 - innolux,n116bge
199 # InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel
200 - innolux,n125hce-gn1
201 # InnoLux 15.6" FHD (1920x1080) TFT LCD panel171 # InnoLux 15.6" FHD (1920x1080) TFT LCD panel
202 - innolux,g156hce-l01172 - innolux,g156hce-l01
203 # InnoLux 15.6" WXGA TFT LCD panel173 # InnoLux 15.6" WXGA TFT LCD panel
204 - innolux,n156bge-l21174 - innolux,n156bge-l21
205 # Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel
206 - innolux,p120zdg-bf1
207 # Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel175 # Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel
208 - innolux,zj070na-01p176 - innolux,zj070na-01p
209 # King & Display KD116N21-30NV-A010 eDP TFT LCD panel
210 - kingdisplay,kd116n21-30nv-a010
211 # Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel177 # Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel
212 - koe,tx14d24vm1bpa178 - koe,tx14d24vm1bpa
213 # Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel179 # Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
@@ -220,14 +186,6 @@ properties: · 6 unmodified lines
220 - lemaker,bl035-rgb-002186 - lemaker,bl035-rgb-002
221 # LG 7" (800x480 pixels) TFT LCD panel187 # LG 7" (800x480 pixels) TFT LCD panel
222 - lg,lb070wv8188 - lg,lb070wv8
223 # LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel
224 - lg,lp079qx1-sp0v
225 # LG 9.7" (2048x1536 pixels) TFT LCD panel
226 - lg,lp097qx1-spa1
227 # LG 12.0" (1920x1280 pixels) TFT LCD panel
228 - lg,lp120up1
229 # LG 12.9" (2560x1700 pixels) TFT LCD panel
230 - lg,lp129qe
231 # Logic Technologies LT161010-2NHC 7" WVGA TFT Cap Touch Module189 # Logic Technologies LT161010-2NHC 7" WVGA TFT Cap Touch Module
232 - logictechno,lt161010-2nhc190 - logictechno,lt161010-2nhc
233 # Logic Technologies LT161010-2NHR 7" WVGA TFT Resistive Touch Module191 # Logic Technologies LT161010-2NHR 7" WVGA TFT Resistive Touch Module
@@ -254,8 +212,6 @@ properties: · 20 unmodified lines
254 - nec,nl4827hc19-05b212 - nec,nl4827hc19-05b
255 # Netron-DY E231732 7.0" WSVGA TFT LCD panel213 # Netron-DY E231732 7.0" WSVGA TFT LCD panel
256 - netron-dy,e231732214 - netron-dy,e231732
257 # NewEast Optoelectronics CO., LTD WJFH116008A eDP TFT LCD panel
258 - neweast,wjfh116008a
259 # Newhaven Display International 480 x 272 TFT LCD panel215 # Newhaven Display International 480 x 272 TFT LCD panel
260 - newhaven,nhd-4.3-480272ef-atxl216 - newhaven,nhd-4.3-480272ef-atxl
261 # New Vision Display 7.0" 800 RGB x 480 TFT LCD panel217 # New Vision Display 7.0" 800 RGB x 480 TFT LCD panel
@@ -280,6 +236,8 @@ properties: · 18 unmodified lines
280 - powertip,ph128800t006-zhc01236 - powertip,ph128800t006-zhc01
281 # POWERTIP PH800480T013-IDF2 7.0" WVGA TFT LCD panel237 # POWERTIP PH800480T013-IDF2 7.0" WVGA TFT LCD panel
282 - powertip,ph800480t013-idf02238 - powertip,ph800480t013-idf02
239 # PrimeView PM070WL4 7.0" 800x480 TFT LCD panel
240 - primeview,pm070wl4
283 # QiaoDian XianShi Corporation 4"3 TFT LCD panel241 # QiaoDian XianShi Corporation 4"3 TFT LCD panel
284 - qiaodian,qd43003c0-40242 - qiaodian,qd43003c0-40
285 # Shenzhen QiShenglong Industrialist Co., Ltd. Gopher 2b 4.3" 480(RGB)x272 TFT LCD panel243 # Shenzhen QiShenglong Industrialist Co., Ltd. Gopher 2b 4.3" 480(RGB)x272 TFT LCD panel
@@ -290,16 +248,10 @@ properties: · 4 unmodified lines
290 - rocktech,rk070er9427248 - rocktech,rk070er9427
291 # Rocktech Display Ltd. RK043FN48H 4.3" 480x272 LCD-TFT panel249 # Rocktech Display Ltd. RK043FN48H 4.3" 480x272 LCD-TFT panel
292 - rocktech,rk043fn48h250 - rocktech,rk043fn48h
293 # Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
294 - samsung,atna33xc20
295 # Samsung 12.2" (2560x1600 pixels) TFT LCD panel
296 - samsung,lsn122dl01-c01
297 # Samsung Electronics 10.1" WXGA (1280x800) TFT LCD panel251 # Samsung Electronics 10.1" WXGA (1280x800) TFT LCD panel
298 - samsung,ltl101al01252 - samsung,ltl101al01
299 # Samsung Electronics 10.1" WSVGA TFT LCD panel253 # Samsung Electronics 10.1" WSVGA TFT LCD panel
300 - samsung,ltn101nt05254 - samsung,ltn101nt05
301 # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel
302 - samsung,ltn140at29-301
303 # Satoz SAT050AT40H12R2 5.0" WVGA TFT LCD panel255 # Satoz SAT050AT40H12R2 5.0" WVGA TFT LCD panel
304 - satoz,sat050at40h12r2256 - satoz,sat050at40h12r2
305 # Sharp LQ035Q7DB03 3.5" QVGA TFT LCD panel257 # Sharp LQ035Q7DB03 3.5" QVGA TFT LCD panel
@@ -308,18 +260,12 @@ properties: · 2 unmodified lines
308 - sharp,lq070y3dg3b260 - sharp,lq070y3dg3b
309 # Sharp Display Corp. LQ101K1LY04 10.07" WXGA TFT LCD panel261 # Sharp Display Corp. LQ101K1LY04 10.07" WXGA TFT LCD panel
310 - sharp,lq101k1ly04262 - sharp,lq101k1ly04
311 # Sharp 12.3" (2400x1600 pixels) TFT LCD panel
312 - sharp,lq123p1jx31
313 # Sharp 14" (1920x1080 pixels) TFT LCD panel
314 - sharp,lq140m1jw46
315 # Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel263 # Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel
316 - sharp,ls020b1dd01d264 - sharp,ls020b1dd01d
317 # Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel265 # Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel
318 - shelly,sca07010-bfn-lnn266 - shelly,sca07010-bfn-lnn
319 # Starry KR070PE2T 7" WVGA TFT LCD panel267 # Starry KR070PE2T 7" WVGA TFT LCD panel
320 - starry,kr070pe2t268 - starry,kr070pe2t
321 # Starry 12.2" (1920x1200 pixels) TFT LCD panel
322 - starry,kr122ea0sra
323 # Startek KD070WVFPA043-C069A 7" TFT LCD panel269 # Startek KD070WVFPA043-C069A 7" TFT LCD panel
324 - startek,kd070wvfpa270 - startek,kd070wvfpa
325 # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel271 # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel
Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml+95−0
@@ -0,0 +1,95 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/panel/samsung,atna33xc20.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
8
9maintainers:
10 - Douglas Anderson <dianders@chromium.org>
11
12allOf:
13 - $ref: panel-common.yaml#
14
15properties:
16 compatible:
17 const: samsung,atna33xc20
18
19 enable-gpios: true
20 port: true
21 power-supply: true
22 no-hpd: true
23 hpd-gpios: true
24
25additionalProperties: false
26
27required:
28 - compatible
29 - enable-gpios
30 - power-supply
31
32examples:
33 - |
34 #include <dt-bindings/clock/qcom,rpmh.h>
35 #include <dt-bindings/gpio/gpio.h>
36 #include <dt-bindings/interrupt-controller/irq.h>
37
38 i2c {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 bridge@2d {
43 compatible = "ti,sn65dsi86";
44 reg = <0x2d>;
45
46 interrupt-parent = <&tlmm>;
47 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
48
49 enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
50
51 vpll-supply = <&src_pp1800_s4a>;
52 vccio-supply = <&src_pp1800_s4a>;
53 vcca-supply = <&src_pp1200_l2a>;
54 vcc-supply = <&src_pp1200_l2a>;
55
56 clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
57 clock-names = "refclk";
58
59 no-hpd;
60
61 ports {
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 port@0 {
66 reg = <0>;
67 endpoint {
68 remote-endpoint = <&dsi0_out>;
69 };
70 };
71
72 port@1 {
73 reg = <1>;
74 sn65dsi86_out: endpoint {
75 remote-endpoint = <&panel_in_edp>;
76 };
77 };
78 };
79
80 aux-bus {
81 panel {
82 compatible = "samsung,atna33xc20";
83 enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
84 power-supply = <&pp3300_dx_edp>;
85 hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
86
87 port {
88 panel_in_edp: endpoint {
89 remote-endpoint = <&sn65dsi86_out>;
90 };
91 };
92 };
93 };
94 };
95 };
Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.yaml+0−30
@@ -1,30 +0,0 @@
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/panel/sharp,ld-d5116z01b.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel
8
9maintainers:
10 - Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
11
12allOf:
13 - $ref: panel-common.yaml#
14
15properties:
16 compatible:
17 const: sharp,ld-d5116z01b
18
19 power-supply: true
20 backlight: true
21 port: true
22 no-hpd: true
23
24additionalProperties: false
25
26required:
27 - compatible
28 - power-supply
29
30...
Documentation/devicetree/bindings/display/panel/wl-355608-a8.yaml+60−0
@@ -0,0 +1,60 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/panel/wl-355608-a8.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: WL-355608-A8 3.5" (640x480 pixels) 24-bit IPS LCD panel
8
9maintainers:
10 - Ryan Walklin <ryan@testtoast.com>
11
12allOf:
13 - $ref: panel-common.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
15
16properties:
17 compatible:
18 const: wl-355608-a8
19
20 reg:
21 maxItems: 1
22
23 spi-3wire: true
24
25required:
26 - compatible
27 - reg
28 - port
29 - power-supply
30 - reset-gpios
31
32unevaluatedProperties: false
33
34examples:
35 - |
36 #include <dt-bindings/gpio/gpio.h>
37
38 spi {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 panel@0 {
43 compatible = "wl-355608-a8";
44 reg = <0>;
45
46 spi-3wire;
47 spi-max-frequency = <3125000>;
48
49 reset-gpios = <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14
50
51 backlight = <&backlight>;
52 power-supply = <&reg_lcd>;
53
54 port {
55 endpoint {
56 remote-endpoint = <&tcon_lcd0_out_lcd>;
57 };
58 };
59 };
60 };
Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml+2−0
@@ -15,6 +15,7 @@ properties: · 14 unmodified lines
15 items:15 items:
16 - enum:16 - enum:
17 - rockchip,px30-mipi-dsi17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3128-mipi-dsi
18 - rockchip,rk3288-mipi-dsi19 - rockchip,rk3288-mipi-dsi
19 - rockchip,rk3399-mipi-dsi20 - rockchip,rk3399-mipi-dsi
20 - rockchip,rk3568-mipi-dsi21 - rockchip,rk3568-mipi-dsi
@@ -77,6 +78,7 @@ allOf: · 56 unmodified lines
77 contains:78 contains:
78 enum:79 enum:
79 - rockchip,px30-mipi-dsi80 - rockchip,px30-mipi-dsi
81 - rockchip,rk3128-mipi-dsi
80 - rockchip,rk3568-mipi-dsi82 - rockchip,rk3568-mipi-dsi
81 - rockchip,rv1126-mipi-dsi83 - rockchip,rv1126-mipi-dsi
82 84
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml+4−1
@@ -34,6 +34,7 @@ properties: · 33 unmodified lines
34 - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable34 - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
35 - items:35 - items:
36 - enum:36 - enum:
37 - mediatek,mt8188-mali
37 - mediatek,mt8192-mali38 - mediatek,mt8192-mali
38 - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable39 - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
39 40
@@ -195,7 +196,9 @@ allOf: · 155 unmodified lines
195 properties:196 properties:
196 compatible:197 compatible:
197 contains:198 contains:
198 const: mediatek,mt8183b-mali199 enum:
200 - mediatek,mt8183b-mali
201 - mediatek,mt8188-mali
199 then:202 then:
200 properties:203 properties:
201 power-domains:204 power-domains:
Documentation/devicetree/bindings/vendor-prefixes.yaml+6−0
@@ -820,6 +820,8 @@ patternProperties: · 819 unmodified lines
820 description: Lichee Pi820 description: Lichee Pi
821 "^linaro,.*":821 "^linaro,.*":
822 description: Linaro Limited822 description: Linaro Limited
823 "^lincolntech,.*":
824 description: Lincoln Technology Solutions
823 "^lineartechnology,.*":825 "^lineartechnology,.*":
824 description: Linear Technology826 description: Linear Technology
825 "^linksprite,.*":827 "^linksprite,.*":
@@ -924,6 +926,8 @@ patternProperties: · 98 unmodified lines
924 description: Microsoft Corporation926 description: Microsoft Corporation
925 "^microsys,.*":927 "^microsys,.*":
926 description: MicroSys Electronics GmbH928 description: MicroSys Electronics GmbH
929 "^microtips,.*":
930 description: Microtips Technology USA
927 "^mikroe,.*":931 "^mikroe,.*":
928 description: MikroElektronika d.o.o.932 description: MikroElektronika d.o.o.
929 "^mikrotik,.*":933 "^mikrotik,.*":
@@ -1160,6 +1164,8 @@ patternProperties: · 230 unmodified lines
1160 description: PowerVR (deprecated, use img)1164 description: PowerVR (deprecated, use img)
1161 "^powkiddy,.*":1165 "^powkiddy,.*":
1162 description: Powkiddy1166 description: Powkiddy
1167 "^primeview,.*":
1168 description: Prime View International (PVI)
1163 "^primux,.*":1169 "^primux,.*":
1164 description: Primux Trading, S.L.1170 description: Primux Trading, S.L.
1165 "^probox2,.*":1171 "^probox2,.*":
Documentation/gpu/drm-internals.rst+2−8
@@ -57,8 +57,8 @@ is larger than the driver minor, the DRM_IOCTL_SET_VERSION call will · 56 unmodified lines
57return an error. Otherwise the driver's set_version() method will be57return an error. Otherwise the driver's set_version() method will be
58called with the requested version.58called with the requested version.
59 59
60Name, Description and Date60Name and Description
61~~~~~~~~~~~~~~~~~~~~~~~~~~61~~~~~~~~~~~~~~~~~~~~
62 62
63char \*name; char \*desc; char \*date;63char \*name; char \*desc; char \*date;
64The driver name is printed to the kernel log at initialization time,64The driver name is printed to the kernel log at initialization time,
@@ -69,12 +69,6 @@ The driver description is a purely informative string passed to · 4 unmodified lines
69userspace through the DRM_IOCTL_VERSION ioctl and otherwise unused by69userspace through the DRM_IOCTL_VERSION ioctl and otherwise unused by
70the kernel.70the kernel.
71 71
72The driver date, formatted as YYYYMMDD, is meant to identify the date of
73the latest modification to the driver. However, as most drivers fail to
74update it, its value is mostly useless. The DRM core prints it to the
75kernel log at initialization time and passes it to userspace through the
76DRM_IOCTL_VERSION ioctl.
77
78Module Initialization72Module Initialization
79---------------------73---------------------
80 74
Documentation/gpu/drm-kms-helpers.rst+9−3
@@ -110,15 +110,21 @@ fbdev Helper Functions Reference · 109 unmodified lines
110.. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c110.. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c
111 :doc: fbdev helpers111 :doc: fbdev helpers
112 112
113.. kernel-doc:: drivers/gpu/drm/drm_fbdev_dma.c
114 :export:
115
116.. kernel-doc:: drivers/gpu/drm/drm_fbdev_shmem.c
117 :export:
118
119.. kernel-doc:: drivers/gpu/drm/drm_fbdev_ttm.c
120 :export:
121
113.. kernel-doc:: include/drm/drm_fb_helper.h122.. kernel-doc:: include/drm/drm_fb_helper.h
114 :internal:123 :internal:
115 124
116.. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c125.. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c
117 :export:126 :export:
118 127
119.. kernel-doc:: drivers/gpu/drm/drm_fbdev_generic.c
120 :export:
121
122format Helper Functions Reference128format Helper Functions Reference
123=================================129=================================
124 130
Documentation/gpu/i915.rst+1−4
@@ -150,7 +150,7 @@ High Definition Audio · 149 unmodified lines
150.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c150.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
151 :internal:151 :internal:
152 152
153.. kernel-doc:: include/drm/i915_component.h153.. kernel-doc:: include/drm/intel/i915_component.h
154 :internal:154 :internal:
155 155
156Intel HDMI LPE Audio Support156Intel HDMI LPE Audio Support
@@ -210,9 +210,6 @@ DMC wakelock support · 53 unmodified lines
210.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c210.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c
211 :doc: DMC wakelock support211 :doc: DMC wakelock support
212 212
213.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c
214 :internal:
215
216Video BIOS Table (VBT)213Video BIOS Table (VBT)
217----------------------214----------------------
218 215
Documentation/gpu/kms-properties.csv+0−2
@@ -17,7 +17,6 @@ Owner Module/Drivers,Group,Property Name,Type,Property Values,Object attached,De · 16 unmodified lines
17,Virtual GPU,“suggested X”,RANGE,"Min=0, Max=0xffffffff",Connector,property to suggest an X offset for a connector17,Virtual GPU,“suggested X”,RANGE,"Min=0, Max=0xffffffff",Connector,property to suggest an X offset for a connector
18,,“suggested Y”,RANGE,"Min=0, Max=0xffffffff",Connector,property to suggest an Y offset for a connector18,,“suggested Y”,RANGE,"Min=0, Max=0xffffffff",Connector,property to suggest an Y offset for a connector
19,Optional,"""aspect ratio""",ENUM,"{ ""None"", ""4:3"", ""16:9"" }",Connector,TDB19,Optional,"""aspect ratio""",ENUM,"{ ""None"", ""4:3"", ""16:9"" }",Connector,TDB
20i915,Generic,"""Broadcast RGB""",ENUM,"{ ""Automatic"", ""Full"", ""Limited 16:235"" }",Connector,"When this property is set to Limited 16:235 and CTM is set, the hardware will be programmed with the result of the multiplication of CTM by the limited range matrix to ensure the pixels normally in the range 0..1.0 are remapped to the range 16/255..235/255."
21,,“audio”,ENUM,"{ ""force-dvi"", ""off"", ""auto"", ""on"" }",Connector,TBD20,,“audio”,ENUM,"{ ""force-dvi"", ""off"", ""auto"", ""on"" }",Connector,TBD
22,SDVO-TV,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD21,SDVO-TV,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD
23,,"""left_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD22,,"""left_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
@@ -38,7 +37,6 @@ i915,Generic,"""Broadcast RGB""",ENUM,"{ ""Automatic"", ""Full"", ""Limited 16:2 · 14 unmodified lines
38,,“dot_crawl”,RANGE,"Min=0, Max=1",Connector,TBD37,,“dot_crawl”,RANGE,"Min=0, Max=1",Connector,TBD
39,SDVO-TV/LVDS,“brightness”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD38,SDVO-TV/LVDS,“brightness”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
40CDV gma-500,Generic,"""Broadcast RGB""",ENUM,"{ “Full”, “Limited 16:235” }",Connector,TBD39CDV gma-500,Generic,"""Broadcast RGB""",ENUM,"{ “Full”, “Limited 16:235” }",Connector,TBD
41,,"""Broadcast RGB""",ENUM,"{ “off”, “auto”, “on” }",Connector,TBD
42Poulsbo,Generic,“backlight”,RANGE,"Min=0, Max=100",Connector,TBD40Poulsbo,Generic,“backlight”,RANGE,"Min=0, Max=100",Connector,TBD
43,SDVO-TV,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD41,SDVO-TV,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD
44,,"""left_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD42,,"""left_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
Documentation/gpu/todo.rst+40−30
@@ -243,19 +243,6 @@ Contact: Maintainer of the driver you plan to convert · 242 unmodified lines
243 243
244Level: Intermediate244Level: Intermediate
245 245
246Convert drivers to use drm_fbdev_generic_setup()
247------------------------------------------------
248
249Most drivers can use drm_fbdev_generic_setup(). Driver have to implement
250atomic modesetting and GEM vmap support. Historically, generic fbdev emulation
251expected the framebuffer in system memory or system-like memory. By employing
252struct iosys_map, drivers with frambuffers in I/O memory can be supported
253as well.
254
255Contact: Maintainer of the driver you plan to convert
256
257Level: Intermediate
258
259Reimplement functions in drm_fbdev_fb_ops without fbdev246Reimplement functions in drm_fbdev_fb_ops without fbdev
260-------------------------------------------------------247-------------------------------------------------------
261 248
@@ -482,30 +469,53 @@ Contact: Thomas Zimmermann <tzimmermann@suse.de> · 220 unmodified lines
482 469
483Level: Starter470Level: Starter
484 471
485Clean up checks for already prepared/enabled in panels472Remove disable/unprepare in remove/shutdown in panel-simple and panel-edp
486------------------------------------------------------473-------------------------------------------------------------------------
474
475As of commit d2aacaf07395 ("drm/panel: Check for already prepared/enabled in
476drm_panel"), we have a check in the drm_panel core to make sure nobody
477double-calls prepare/enable/disable/unprepare. Eventually that should probably
478be turned into a WARN_ON() or somehow made louder, but right now we actually
479expect it to trigger and so we don't want it to be too loud.
480
481Specifically, that warning will trigger for panel-edp and panel-simple at
482shutdown time because those panels hardcode a call to drm_panel_disable()
483and drm_panel_unprepare() at shutdown and remove time that they call regardless
484of panel state. On systems with a properly coded DRM modeset driver that
485calls drm_atomic_helper_shutdown() this is pretty much guaranteed to cause
486the warning to fire.
487
488Unfortunately we can't safely remove the calls in panel-edp and panel-simple
489until we're sure that all DRM modeset drivers that are used with those panels
490properly call drm_atomic_helper_shutdown(). This TODO item is to validate
491that all DRM modeset drivers used with panel-edp and panel-simple properly
492call drm_atomic_helper_shutdown() and then remove the calls to
493disable/unprepare from those panels. Alternatively, this TODO item could be
494removed by convincing stakeholders that those calls are fine and downgrading
495the error message in drm_panel_disable() / drm_panel_unprepare() to a
496debug-level message.
487 497
488In a whole pile of panel drivers, we have code to make the498Contact: Douglas Anderson <dianders@chromium.org>
489prepare/unprepare/enable/disable callbacks behave as no-ops if they've already
490been called. To get some idea of the duplicated code, try::
491 499
492 git grep 'if.*>prepared' -- drivers/gpu/drm/panel500Level: Intermediate
493 git grep 'if.*>enabled' -- drivers/gpu/drm/panel
494 501
495In the patch ("drm/panel: Check for already prepared/enabled in drm_panel")502Transition away from using mipi_dsi_*_write_seq()
496we've moved this check to the core. Now we can most definitely remove the503-------------------------------------------------
497check from the individual panels and save a pile of code.
498 504
499In adition to removing the check from the individual panels, it is believed505The macros mipi_dsi_generic_write_seq() and mipi_dsi_dcs_write_seq() are
500that even the core shouldn't need this check and that should be considered506non-intuitive because, if there are errors, they return out of the *caller's*
501an error if other code ever relies on this check. The check in the core507function. We should move all callers to use mipi_dsi_generic_write_seq_multi()
502currently prints a warning whenever something is relying on this check with508and mipi_dsi_dcs_write_seq_multi() macros instead.
503dev_warn(). After a little while, we likely want to promote this to a509
504WARN(1) to help encourage folks not to rely on this behavior.510Once all callers are transitioned, the macros and the functions that they call,
511mipi_dsi_generic_write_chatty() and mipi_dsi_dcs_write_buffer_chatty(), can
512probably be removed. Alternatively, if people feel like the _multi() variants
513are overkill for some use cases, we could keep the mipi_dsi_*_write_seq()
514variants but change them not to return out of the caller.
505 515
506Contact: Douglas Anderson <dianders@chromium.org>516Contact: Douglas Anderson <dianders@chromium.org>
507 517
508Level: Starter/Intermediate518Level: Starter
509 519
510 520
511Core refactorings521Core refactorings
MAINTAINERS+6−5
@@ -6909,7 +6909,7 @@ DRM DRIVER FOR LG SW43408 PANELS · 6908 unmodified lines
6909M: Sumit Semwal <sumit.semwal@linaro.org>6909M: Sumit Semwal <sumit.semwal@linaro.org>
6910M: Caleb Connolly <caleb.connolly@linaro.org>6910M: Caleb Connolly <caleb.connolly@linaro.org>
6911S: Maintained6911S: Maintained
6912T: git git://anongit.freedesktop.org/drm/drm-misc6912T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
6913F: Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml6913F: Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml
6914F: drivers/gpu/drm/panel/panel-lg-sw43408.c6914F: drivers/gpu/drm/panel/panel-lg-sw43408.c
6915 6915
@@ -7196,6 +7196,7 @@ L: dri-devel@lists.freedesktop.org · 280 unmodified lines
7196S: Maintained7196S: Maintained
7197T: git https://gitlab.freedesktop.org/drm/misc/kernel.git7197T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
7198F: Documentation/gpu/vkms.rst7198F: Documentation/gpu/vkms.rst
7199F: drivers/gpu/drm/ci/xfails/vkms*
7199F: drivers/gpu/drm/vkms/7200F: drivers/gpu/drm/vkms/
7200 7201
7201DRM DRIVER FOR VIRTUALBOX VIRTUAL GPU7202DRM DRIVER FOR VIRTUALBOX VIRTUAL GPU
@@ -7566,7 +7567,6 @@ F: include/drm/gpu_scheduler.h · 364 unmodified lines
7566DRM PANEL DRIVERS7567DRM PANEL DRIVERS
7567M: Neil Armstrong <neil.armstrong@linaro.org>7568M: Neil Armstrong <neil.armstrong@linaro.org>
7568R: Jessica Zhang <quic_jesszhan@quicinc.com>7569R: Jessica Zhang <quic_jesszhan@quicinc.com>
7569R: Sam Ravnborg <sam@ravnborg.org>
7570L: dri-devel@lists.freedesktop.org7570L: dri-devel@lists.freedesktop.org
7571S: Maintained7571S: Maintained
7572T: git https://gitlab.freedesktop.org/drm/misc/kernel.git7572T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
@@ -11012,6 +11012,7 @@ S: Supported · 3439 unmodified lines
11012F: drivers/gpu/drm/i915/display/11012F: drivers/gpu/drm/i915/display/
11013F: drivers/gpu/drm/xe/display/11013F: drivers/gpu/drm/xe/display/
11014F: drivers/gpu/drm/xe/compat-i915-headers11014F: drivers/gpu/drm/xe/compat-i915-headers
11015F: include/drm/intel/
11015 11016
11016INTEL DRM I915 DRIVER (Meteor Lake, DG2 and older excluding Poulsbo, Moorestown and derivative)11017INTEL DRM I915 DRIVER (Meteor Lake, DG2 and older excluding Poulsbo, Moorestown and derivative)
11017M: Jani Nikula <jani.nikula@linux.intel.com>11018M: Jani Nikula <jani.nikula@linux.intel.com>
@@ -11024,12 +11025,12 @@ W: https://drm.pages.freedesktop.org/intel-docs/ · 6 unmodified lines
11024Q: http://patchwork.freedesktop.org/project/intel-gfx/11025Q: http://patchwork.freedesktop.org/project/intel-gfx/
11025B: https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html11026B: https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html
11026C: irc://irc.oftc.net/intel-gfx11027C: irc://irc.oftc.net/intel-gfx
11027T: git git://anongit.freedesktop.org/drm-intel11028T: git https://gitlab.freedesktop.org/drm/i915/kernel.git
11028F: Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon11029F: Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
11029F: Documentation/gpu/i915.rst11030F: Documentation/gpu/i915.rst
11030F: drivers/gpu/drm/ci/xfails/i915*11031F: drivers/gpu/drm/ci/xfails/i915*
11031F: drivers/gpu/drm/i915/11032F: drivers/gpu/drm/i915/
11032F: include/drm/i915*11033F: include/drm/intel/
11033F: include/uapi/drm/i915_drm.h11034F: include/uapi/drm/i915_drm.h
11034 11035
11035INTEL DRM XE DRIVER (Lunar Lake and newer)11036INTEL DRM XE DRIVER (Lunar Lake and newer)
@@ -11045,7 +11046,7 @@ T: git https://gitlab.freedesktop.org/drm/xe/kernel.git · 9 unmodified lines
11045F: Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon11046F: Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
11046F: Documentation/gpu/xe/11047F: Documentation/gpu/xe/
11047F: drivers/gpu/drm/xe/11048F: drivers/gpu/drm/xe/
11048F: include/drm/xe*11049F: include/drm/intel/
11049F: include/uapi/drm/xe_drm.h11050F: include/uapi/drm/xe_drm.h
11050 11051
11051INTEL ETHERNET DRIVERS11052INTEL ETHERNET DRIVERS
arch/x86/kernel/early-quirks.c+42−43
@@ -17,8 +17,8 @@ · 16 unmodified lines
17#include <linux/bcma/bcma.h>17#include <linux/bcma/bcma.h>
18#include <linux/bcma/bcma_regs.h>18#include <linux/bcma/bcma_regs.h>
19#include <linux/platform_data/x86/apple.h>19#include <linux/platform_data/x86/apple.h>
20#include <drm/i915_drm.h>20#include <drm/intel/i915_drm.h>
21#include <drm/i915_pciids.h>21#include <drm/intel/i915_pciids.h>
22#include <asm/pci-direct.h>22#include <asm/pci-direct.h>
23#include <asm/dma.h>23#include <asm/dma.h>
24#include <asm/io_apic.h>24#include <asm/io_apic.h>
@@ -518,47 +518,46 @@ static const struct intel_early_ops gen11_early_ops __initconst = { · 493 unmodified lines
518 518
519/* Intel integrated GPUs for which we need to reserve "stolen memory" */519/* Intel integrated GPUs for which we need to reserve "stolen memory" */
520static const struct pci_device_id intel_early_ids[] __initconst = {520static const struct pci_device_id intel_early_ids[] __initconst = {
521 INTEL_I830_IDS(&i830_early_ops),521 INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_early_ops),
522 INTEL_I845G_IDS(&i845_early_ops),522 INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_early_ops),
523 INTEL_I85X_IDS(&i85x_early_ops),523 INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_early_ops),
524 INTEL_I865G_IDS(&i865_early_ops),524 INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865_early_ops),
525 INTEL_I915G_IDS(&gen3_early_ops),525 INTEL_I915G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
526 INTEL_I915GM_IDS(&gen3_early_ops),526 INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
527 INTEL_I945G_IDS(&gen3_early_ops),527 INTEL_I945G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
528 INTEL_I945GM_IDS(&gen3_early_ops),528 INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
529 INTEL_VLV_IDS(&gen6_early_ops),529 INTEL_VLV_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
530 INTEL_PINEVIEW_G_IDS(&gen3_early_ops),530 INTEL_PNV_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
531 INTEL_PINEVIEW_M_IDS(&gen3_early_ops),531 INTEL_I965G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
532 INTEL_I965G_IDS(&gen3_early_ops),532 INTEL_G33_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
533 INTEL_G33_IDS(&gen3_early_ops),533 INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
534 INTEL_I965GM_IDS(&gen3_early_ops),534 INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
535 INTEL_GM45_IDS(&gen3_early_ops),535 INTEL_G45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
536 INTEL_G45_IDS(&gen3_early_ops),536 INTEL_ILK_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
537 INTEL_IRONLAKE_D_IDS(&gen3_early_ops),537 INTEL_SNB_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
538 INTEL_IRONLAKE_M_IDS(&gen3_early_ops),538 INTEL_IVB_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
539 INTEL_SNB_D_IDS(&gen6_early_ops),539 INTEL_HSW_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
540 INTEL_SNB_M_IDS(&gen6_early_ops),540 INTEL_BDW_IDS(INTEL_VGA_DEVICE, &gen8_early_ops),
541 INTEL_IVB_M_IDS(&gen6_early_ops),541 INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_early_ops),
542 INTEL_IVB_D_IDS(&gen6_early_ops),542 INTEL_SKL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
543 INTEL_HSW_IDS(&gen6_early_ops),543 INTEL_BXT_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
544 INTEL_BDW_IDS(&gen8_early_ops),544 INTEL_KBL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
545 INTEL_CHV_IDS(&chv_early_ops),545 INTEL_CFL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
546 INTEL_SKL_IDS(&gen9_early_ops),546 INTEL_WHL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
547 INTEL_BXT_IDS(&gen9_early_ops),547 INTEL_CML_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
548 INTEL_KBL_IDS(&gen9_early_ops),548 INTEL_GLK_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
549 INTEL_CFL_IDS(&gen9_early_ops),549 INTEL_CNL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
550 INTEL_GLK_IDS(&gen9_early_ops),550 INTEL_ICL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
551 INTEL_CNL_IDS(&gen9_early_ops),551 INTEL_EHL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
552 INTEL_ICL_11_IDS(&gen11_early_ops),552 INTEL_JSL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
553 INTEL_EHL_IDS(&gen11_early_ops),553 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
554 INTEL_JSL_IDS(&gen11_early_ops),554 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
555 INTEL_TGL_12_IDS(&gen11_early_ops),555 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
556 INTEL_RKL_IDS(&gen11_early_ops),556 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
557 INTEL_ADLS_IDS(&gen11_early_ops),557 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
558 INTEL_ADLP_IDS(&gen11_early_ops),558 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
559 INTEL_ADLN_IDS(&gen11_early_ops),559 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
560 INTEL_RPLS_IDS(&gen11_early_ops),560 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
561 INTEL_RPLP_IDS(&gen11_early_ops),
562};561};
563 562
564struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);563struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
drivers/accel/ivpu/Makefile+7−4
@@ -1,19 +1,22 @@
1# SPDX-License-Identifier: GPL-2.0-only1# SPDX-License-Identifier: GPL-2.0-only
2# Copyright (C) 2023 Intel Corporation2# Copyright (C) 2023-2024 Intel Corporation
3 3
4intel_vpu-y := \4intel_vpu-y := \
5 ivpu_drv.o \5 ivpu_drv.o \
6 ivpu_fw.o \6 ivpu_fw.o \
7 ivpu_fw_log.o \7 ivpu_fw_log.o \
8 ivpu_gem.o \8 ivpu_gem.o \
9 ivpu_hw_37xx.o \9 ivpu_hw.o \
10 ivpu_hw_40xx.o \10 ivpu_hw_btrs.o \
11 ivpu_hw_ip.o \
11 ivpu_ipc.o \12 ivpu_ipc.o \
12 ivpu_job.o \13 ivpu_job.o \
13 ivpu_jsm_msg.o \14 ivpu_jsm_msg.o \
14 ivpu_mmu.o \15 ivpu_mmu.o \
15 ivpu_mmu_context.o \16 ivpu_mmu_context.o \
16 ivpu_pm.o17 ivpu_ms.o \
18 ivpu_pm.o \
19 ivpu_sysfs.o
17 20
18intel_vpu-$(CONFIG_DEBUG_FS) += ivpu_debugfs.o21intel_vpu-$(CONFIG_DEBUG_FS) += ivpu_debugfs.o
19 22
drivers/accel/ivpu/ivpu_debugfs.c+87−2
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0-only1// SPDX-License-Identifier: GPL-2.0-only
2/*2/*
3 * Copyright (C) 2020-2023 Intel Corporation3 * Copyright (C) 2020-2024 Intel Corporation
4 */4 */
5 5
6#include <linux/debugfs.h>6#include <linux/debugfs.h>
@@ -145,6 +145,30 @@ static const struct file_operations dvfs_mode_fops = { · 138 unmodified lines
145 .write = dvfs_mode_fops_write,145 .write = dvfs_mode_fops_write,
146};146};
147 147
148static ssize_t
149fw_dyndbg_fops_write(struct file *file, const char __user *user_buf, size_t size, loff_t *pos)
150{
151 struct ivpu_device *vdev = file->private_data;
152 char buffer[VPU_DYNDBG_CMD_MAX_LEN] = {};
153 int ret;
154
155 if (size >= VPU_DYNDBG_CMD_MAX_LEN)
156 return -EINVAL;
157
158 ret = strncpy_from_user(buffer, user_buf, size);
159 if (ret < 0)
160 return ret;
161
162 ivpu_jsm_dyndbg_control(vdev, buffer, size);
163 return size;
164}
165
166static const struct file_operations fw_dyndbg_fops = {
167 .owner = THIS_MODULE,
168 .open = simple_open,
169 .write = fw_dyndbg_fops_write,
170};
171
148static int fw_log_show(struct seq_file *s, void *v)172static int fw_log_show(struct seq_file *s, void *v)
149{173{
150 struct ivpu_device *vdev = s->private;174 struct ivpu_device *vdev = s->private;
@@ -335,6 +359,61 @@ static const struct file_operations ivpu_reset_engine_fops = { · 184 unmodified lines
335 .write = ivpu_reset_engine_fn,359 .write = ivpu_reset_engine_fn,
336};360};
337 361
362static ssize_t
363ivpu_resume_engine_fn(struct file *file, const char __user *user_buf, size_t size, loff_t *pos)
364{
365 struct ivpu_device *vdev = file->private_data;
366
367 if (!size)
368 return -EINVAL;
369
370 if (ivpu_jsm_hws_resume_engine(vdev, DRM_IVPU_ENGINE_COMPUTE))
371 return -ENODEV;
372 if (ivpu_jsm_hws_resume_engine(vdev, DRM_IVPU_ENGINE_COPY))
373 return -ENODEV;
374
375 return size;
376}
377
378static const struct file_operations ivpu_resume_engine_fops = {
379 .owner = THIS_MODULE,
380 .open = simple_open,
381 .write = ivpu_resume_engine_fn,
382};
383
384static int dct_active_get(void *data, u64 *active_percent)
385{
386 struct ivpu_device *vdev = data;
387
388 *active_percent = vdev->pm->dct_active_percent;
389
390 return 0;
391}
392
393static int dct_active_set(void *data, u64 active_percent)
394{
395 struct ivpu_device *vdev = data;
396 int ret;
397
398 if (active_percent > 100)
399 return -EINVAL;
400
401 ret = ivpu_rpm_get(vdev);
402 if (ret)
403 return ret;
404
405 if (active_percent)
406 ret = ivpu_pm_dct_enable(vdev, active_percent);
407 else
408 ret = ivpu_pm_dct_disable(vdev);
409
410 ivpu_rpm_put(vdev);
411
412 return ret;
413}
414
415DEFINE_DEBUGFS_ATTRIBUTE(ivpu_dct_fops, dct_active_get, dct_active_set, "%llu\n");
416
338void ivpu_debugfs_init(struct ivpu_device *vdev)417void ivpu_debugfs_init(struct ivpu_device *vdev)
339{418{
340 struct dentry *debugfs_root = vdev->drm.debugfs_root;419 struct dentry *debugfs_root = vdev->drm.debugfs_root;
@@ -347,6 +426,8 @@ void ivpu_debugfs_init(struct ivpu_device *vdev) · 6 unmodified lines
347 debugfs_create_file("dvfs_mode", 0200, debugfs_root, vdev,426 debugfs_create_file("dvfs_mode", 0200, debugfs_root, vdev,
348 &dvfs_mode_fops);427 &dvfs_mode_fops);
349 428
429 debugfs_create_file("fw_dyndbg", 0200, debugfs_root, vdev,
430 &fw_dyndbg_fops);
350 debugfs_create_file("fw_log", 0644, debugfs_root, vdev,431 debugfs_create_file("fw_log", 0644, debugfs_root, vdev,
351 &fw_log_fops);432 &fw_log_fops);
352 debugfs_create_file("fw_trace_destination_mask", 0200, debugfs_root, vdev,433 debugfs_create_file("fw_trace_destination_mask", 0200, debugfs_root, vdev,
@@ -358,8 +439,12 @@ void ivpu_debugfs_init(struct ivpu_device *vdev) · 5 unmodified lines
358 439
359 debugfs_create_file("reset_engine", 0200, debugfs_root, vdev,440 debugfs_create_file("reset_engine", 0200, debugfs_root, vdev,
360 &ivpu_reset_engine_fops);441 &ivpu_reset_engine_fops);
442 debugfs_create_file("resume_engine", 0200, debugfs_root, vdev,
443 &ivpu_resume_engine_fops);
361 444
362 if (ivpu_hw_gen(vdev) >= IVPU_HW_40XX)445 if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_40XX) {
363 debugfs_create_file("fw_profiling_freq_drive", 0200,446 debugfs_create_file("fw_profiling_freq_drive", 0200,
364 debugfs_root, vdev, &fw_profiling_freq_fops);447 debugfs_root, vdev, &fw_profiling_freq_fops);
448 debugfs_create_file("dct", 0644, debugfs_root, vdev, &ivpu_dct_fops);
449 }
365}450}
drivers/accel/ivpu/ivpu_drv.c+99−14
@@ -26,7 +26,9 @@ · 25 unmodified lines
26#include "ivpu_jsm_msg.h"26#include "ivpu_jsm_msg.h"
27#include "ivpu_mmu.h"27#include "ivpu_mmu.h"
28#include "ivpu_mmu_context.h"28#include "ivpu_mmu_context.h"
29#include "ivpu_ms.h"
29#include "ivpu_pm.h"30#include "ivpu_pm.h"
31#include "ivpu_sysfs.h"
30 32
31#ifndef DRIVER_VERSION_STR33#ifndef DRIVER_VERSION_STR
32#define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \34#define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \
@@ -51,10 +53,18 @@ u8 ivpu_pll_max_ratio = U8_MAX; · 18 unmodified lines
51module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644);53module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644);
52MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set NPU frequency");54MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set NPU frequency");
53 55
56int ivpu_sched_mode;
57module_param_named(sched_mode, ivpu_sched_mode, int, 0444);
58MODULE_PARM_DESC(sched_mode, "Scheduler mode: 0 - Default scheduler, 1 - Force HW scheduler");
59
54bool ivpu_disable_mmu_cont_pages;60bool ivpu_disable_mmu_cont_pages;
55module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0644);61module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0444);
56MODULE_PARM_DESC(disable_mmu_cont_pages, "Disable MMU contiguous pages optimization");62MODULE_PARM_DESC(disable_mmu_cont_pages, "Disable MMU contiguous pages optimization");
57 63
64bool ivpu_force_snoop;
65module_param_named(force_snoop, ivpu_force_snoop, bool, 0444);
66MODULE_PARM_DESC(force_snoop, "Force snooping for NPU host memory access");
67
58struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv)68struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv)
59{69{
60 struct ivpu_device *vdev = file_priv->vdev;70 struct ivpu_device *vdev = file_priv->vdev;
@@ -74,7 +84,6 @@ static void file_priv_unbind(struct ivpu_device *vdev, struct ivpu_file_priv *fi · 13 unmodified lines
74 ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id);84 ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id);
75 85
76 ivpu_cmdq_release_all_locked(file_priv);86 ivpu_cmdq_release_all_locked(file_priv);
77 ivpu_jsm_context_release(vdev, file_priv->ctx.id);
78 ivpu_bo_unbind_all_bos_from_context(vdev, &file_priv->ctx);87 ivpu_bo_unbind_all_bos_from_context(vdev, &file_priv->ctx);
79 ivpu_mmu_user_context_fini(vdev, &file_priv->ctx);88 ivpu_mmu_user_context_fini(vdev, &file_priv->ctx);
80 file_priv->bound = false;89 file_priv->bound = false;
@@ -97,6 +106,7 @@ static void file_priv_release(struct kref *ref) · 16 unmodified lines
97 mutex_unlock(&vdev->context_list_lock);106 mutex_unlock(&vdev->context_list_lock);
98 pm_runtime_put_autosuspend(vdev->drm.dev);107 pm_runtime_put_autosuspend(vdev->drm.dev);
99 108
109 mutex_destroy(&file_priv->ms_lock);
100 mutex_destroy(&file_priv->lock);110 mutex_destroy(&file_priv->lock);
101 kfree(file_priv);111 kfree(file_priv);
102}112}
@@ -119,7 +129,7 @@ static int ivpu_get_capabilities(struct ivpu_device *vdev, struct drm_ivpu_param · 16 unmodified lines
119{129{
120 switch (args->index) {130 switch (args->index) {
121 case DRM_IVPU_CAP_METRIC_STREAMER:131 case DRM_IVPU_CAP_METRIC_STREAMER:
122 args->value = 0;132 args->value = 1;
123 break;133 break;
124 case DRM_IVPU_CAP_DMA_MEMORY_RANGE:134 case DRM_IVPU_CAP_DMA_MEMORY_RANGE:
125 args->value = 1;135 args->value = 1;
@@ -228,10 +238,13 @@ static int ivpu_open(struct drm_device *dev, struct drm_file *file) · 102 unmodified lines
228 goto err_dev_exit;238 goto err_dev_exit;
229 }239 }
230 240
241 INIT_LIST_HEAD(&file_priv->ms_instance_list);
242
231 file_priv->vdev = vdev;243 file_priv->vdev = vdev;
232 file_priv->bound = true;244 file_priv->bound = true;
233 kref_init(&file_priv->ref);245 kref_init(&file_priv->ref);
234 mutex_init(&file_priv->lock);246 mutex_init(&file_priv->lock);
247 mutex_init(&file_priv->ms_lock);
235 248
236 mutex_lock(&vdev->context_list_lock);249 mutex_lock(&vdev->context_list_lock);
237 250
@@ -260,6 +273,7 @@ err_xa_erase: · 22 unmodified lines
260 xa_erase_irq(&vdev->context_xa, ctx_id);273 xa_erase_irq(&vdev->context_xa, ctx_id);
261err_unlock:274err_unlock:
262 mutex_unlock(&vdev->context_list_lock);275 mutex_unlock(&vdev->context_list_lock);
276 mutex_destroy(&file_priv->ms_lock);
263 mutex_destroy(&file_priv->lock);277 mutex_destroy(&file_priv->lock);
264 kfree(file_priv);278 kfree(file_priv);
265err_dev_exit:279err_dev_exit:
@@ -275,6 +289,7 @@ static void ivpu_postclose(struct drm_device *dev, struct drm_file *file) · 9 unmodified lines
275 ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n",289 ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n",
276 file_priv->ctx.id, current->comm, task_pid_nr(current));290 file_priv->ctx.id, current->comm, task_pid_nr(current));
277 291
292 ivpu_ms_cleanup(file_priv);
278 ivpu_file_priv_put(&file_priv);293 ivpu_file_priv_put(&file_priv);
279}294}
280 295
@@ -285,6 +300,10 @@ static const struct drm_ioctl_desc ivpu_drm_ioctls[] = { · 4 unmodified lines
285 DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, 0),300 DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, 0),
286 DRM_IOCTL_DEF_DRV(IVPU_SUBMIT, ivpu_submit_ioctl, 0),301 DRM_IOCTL_DEF_DRV(IVPU_SUBMIT, ivpu_submit_ioctl, 0),
287 DRM_IOCTL_DEF_DRV(IVPU_BO_WAIT, ivpu_bo_wait_ioctl, 0),302 DRM_IOCTL_DEF_DRV(IVPU_BO_WAIT, ivpu_bo_wait_ioctl, 0),
303 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_START, ivpu_ms_start_ioctl, 0),
304 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_GET_DATA, ivpu_ms_get_data_ioctl, 0),
305 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_STOP, ivpu_ms_stop_ioctl, 0),
306 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_GET_INFO, ivpu_ms_get_info_ioctl, 0),
288};307};
289 308
290static int ivpu_wait_for_ready(struct ivpu_device *vdev)309static int ivpu_wait_for_ready(struct ivpu_device *vdev)
@@ -301,7 +320,7 @@ static int ivpu_wait_for_ready(struct ivpu_device *vdev) · 10 unmodified lines
301 320
302 timeout = jiffies + msecs_to_jiffies(vdev->timeout.boot);321 timeout = jiffies + msecs_to_jiffies(vdev->timeout.boot);
303 while (1) {322 while (1) {
304 ivpu_ipc_irq_handler(vdev, NULL);323 ivpu_ipc_irq_handler(vdev);
305 ret = ivpu_ipc_receive(vdev, &cons, &ipc_hdr, NULL, 0);324 ret = ivpu_ipc_receive(vdev, &cons, &ipc_hdr, NULL, 0);
306 if (ret != -ETIMEDOUT || time_after_eq(jiffies, timeout))325 if (ret != -ETIMEDOUT || time_after_eq(jiffies, timeout))
307 break;326 break;
@@ -323,6 +342,21 @@ static int ivpu_wait_for_ready(struct ivpu_device *vdev) · 15 unmodified lines
323 return ret;342 return ret;
324}343}
325 344
345static int ivpu_hw_sched_init(struct ivpu_device *vdev)
346{
347 int ret = 0;
348
349 if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) {
350 ret = ivpu_jsm_hws_setup_priority_bands(vdev);
351 if (ret) {
352 ivpu_err(vdev, "Failed to enable hw scheduler: %d", ret);
353 return ret;
354 }
355 }
356
357 return ret;
358}
359
326/**360/**
327 * ivpu_boot() - Start VPU firmware361 * ivpu_boot() - Start VPU firmware
328 * @vdev: VPU device362 * @vdev: VPU device
@@ -356,6 +390,15 @@ int ivpu_boot(struct ivpu_device *vdev) · 27 unmodified lines
356 enable_irq(vdev->irq);390 enable_irq(vdev->irq);
357 ivpu_hw_irq_enable(vdev);391 ivpu_hw_irq_enable(vdev);
358 ivpu_ipc_enable(vdev);392 ivpu_ipc_enable(vdev);
393
394 if (ivpu_fw_is_cold_boot(vdev)) {
395 ret = ivpu_pm_dct_init(vdev);
396 if (ret)
397 return ret;
398
399 return ivpu_hw_sched_init(vdev);
400 }
401
359 return 0;402 return 0;
360}403}
361 404
@@ -408,11 +451,52 @@ static const struct drm_driver driver = { · 46 unmodified lines
408 .minor = DRM_IVPU_DRIVER_MINOR,451 .minor = DRM_IVPU_DRIVER_MINOR,
409};452};
410 453
454static void ivpu_context_abort_invalid(struct ivpu_device *vdev)
455{
456 struct ivpu_file_priv *file_priv;
457 unsigned long ctx_id;
458
459 mutex_lock(&vdev->context_list_lock);
460
461 xa_for_each(&vdev->context_xa, ctx_id, file_priv) {
462 if (!file_priv->has_mmu_faults || file_priv->aborted)
463 continue;
464
465 mutex_lock(&file_priv->lock);
466 ivpu_context_abort_locked(file_priv);
467 file_priv->aborted = true;
468 mutex_unlock(&file_priv->lock);
469 }
470
471 mutex_unlock(&vdev->context_list_lock);
472}
473
411static irqreturn_t ivpu_irq_thread_handler(int irq, void *arg)474static irqreturn_t ivpu_irq_thread_handler(int irq, void *arg)
412{475{
413 struct ivpu_device *vdev = arg;476 struct ivpu_device *vdev = arg;
477 u8 irq_src;
478
479 if (kfifo_is_empty(&vdev->hw->irq.fifo))
480 return IRQ_NONE;
414 481
415 return ivpu_ipc_irq_thread_handler(vdev);482 while (kfifo_get(&vdev->hw->irq.fifo, &irq_src)) {
483 switch (irq_src) {
484 case IVPU_HW_IRQ_SRC_IPC:
485 ivpu_ipc_irq_thread_handler(vdev);
486 break;
487 case IVPU_HW_IRQ_SRC_MMU_EVTQ:
488 ivpu_context_abort_invalid(vdev);
489 break;
490 case IVPU_HW_IRQ_SRC_DCT:
491 ivpu_pm_dct_irq_thread_handler(vdev);
492 break;
493 default:
494 ivpu_err_ratelimited(vdev, "Unknown IRQ source: %u\n", irq_src);
495 break;
496 }
497 }
498
499 return IRQ_HANDLED;
416}500}
417 501
418static int ivpu_irq_init(struct ivpu_device *vdev)502static int ivpu_irq_init(struct ivpu_device *vdev)
@@ -426,9 +510,11 @@ static int ivpu_irq_init(struct ivpu_device *vdev) · 7 unmodified lines
426 return ret;510 return ret;
427 }511 }
428 512
513 ivpu_irq_handlers_init(vdev);
514
429 vdev->irq = pci_irq_vector(pdev, 0);515 vdev->irq = pci_irq_vector(pdev, 0);
430 516
431 ret = devm_request_threaded_irq(vdev->drm.dev, vdev->irq, vdev->hw->ops->irq_handler,517 ret = devm_request_threaded_irq(vdev->drm.dev, vdev->irq, ivpu_hw_irq_handler,
432 ivpu_irq_thread_handler, IRQF_NO_AUTOEN, DRIVER_NAME, vdev);518 ivpu_irq_thread_handler, IRQF_NO_AUTOEN, DRIVER_NAME, vdev);
433 if (ret)519 if (ret)
434 ivpu_err(vdev, "Failed to request an IRQ %d\n", ret);520 ivpu_err(vdev, "Failed to request an IRQ %d\n", ret);
@@ -505,13 +591,10 @@ static int ivpu_dev_init(struct ivpu_device *vdev) · 70 unmodified lines
505 if (!vdev->pm)591 if (!vdev->pm)
506 return -ENOMEM;592 return -ENOMEM;
507 593
508 if (ivpu_hw_gen(vdev) >= IVPU_HW_40XX) {594 if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_40XX)
509 vdev->hw->ops = &ivpu_hw_40xx_ops;
510 vdev->hw->dma_bits = 48;595 vdev->hw->dma_bits = 48;
511 } else {596 else
512 vdev->hw->ops = &ivpu_hw_37xx_ops;
513 vdev->hw->dma_bits = 38;597 vdev->hw->dma_bits = 38;
514 }
515 598
516 vdev->platform = IVPU_PLATFORM_INVALID;599 vdev->platform = IVPU_PLATFORM_INVALID;
517 vdev->context_xa_limit.min = IVPU_USER_CONTEXT_MIN_SSID;600 vdev->context_xa_limit.min = IVPU_USER_CONTEXT_MIN_SSID;
@@ -540,7 +623,7 @@ static int ivpu_dev_init(struct ivpu_device *vdev) · 22 unmodified lines
540 goto err_xa_destroy;623 goto err_xa_destroy;
541 624
542 /* Init basic HW info based on buttress registers which are accessible before power up */625 /* Init basic HW info based on buttress registers which are accessible before power up */
543 ret = ivpu_hw_info_init(vdev);626 ret = ivpu_hw_init(vdev);
544 if (ret)627 if (ret)
545 goto err_xa_destroy;628 goto err_xa_destroy;
546 629
@@ -612,13 +695,14 @@ static void ivpu_bo_unbind_all_user_contexts(struct ivpu_device *vdev) · 65 unmodified lines
612 695
613static void ivpu_dev_fini(struct ivpu_device *vdev)696static void ivpu_dev_fini(struct ivpu_device *vdev)
614{697{
698 ivpu_jobs_abort_all(vdev);
699 ivpu_pm_cancel_recovery(vdev);
615 ivpu_pm_disable(vdev);700 ivpu_pm_disable(vdev);
616 ivpu_prepare_for_reset(vdev);701 ivpu_prepare_for_reset(vdev);
617 ivpu_shutdown(vdev);702 ivpu_shutdown(vdev);
618 703
619 ivpu_jobs_abort_all(vdev);704 ivpu_ms_cleanup_all(vdev);
620 ivpu_job_done_consumer_fini(vdev);705 ivpu_job_done_consumer_fini(vdev);
621 ivpu_pm_cancel_recovery(vdev);
622 ivpu_bo_unbind_all_user_contexts(vdev);706 ivpu_bo_unbind_all_user_contexts(vdev);
623 707
624 ivpu_ipc_fini(vdev);708 ivpu_ipc_fini(vdev);
@@ -658,6 +742,7 @@ static int ivpu_probe(struct pci_dev *pdev, const struct pci_device_id *id) · 33 unmodified lines
658 return ret;742 return ret;
659 743
660 ivpu_debugfs_init(vdev);744 ivpu_debugfs_init(vdev);
745 ivpu_sysfs_init(vdev);
661 746
662 ret = drm_dev_register(&vdev->drm, 0);747 ret = drm_dev_register(&vdev->drm, 0);
663 if (ret) {748 if (ret) {
drivers/accel/ivpu/ivpu_drv.h+53−9
@@ -27,8 +27,15 @@ · 26 unmodified lines
27#define PCI_DEVICE_ID_ARL 0xad1d27#define PCI_DEVICE_ID_ARL 0xad1d
28#define PCI_DEVICE_ID_LNL 0x643e28#define PCI_DEVICE_ID_LNL 0x643e
29 29
30#define IVPU_HW_37XX 3730#define IVPU_HW_IP_37XX 37
31#define IVPU_HW_40XX 4031#define IVPU_HW_IP_40XX 40
32#define IVPU_HW_IP_50XX 50
33#define IVPU_HW_IP_60XX 60
34
35#define IVPU_HW_IP_REV_LNL_B0 4
36
37#define IVPU_HW_BTRS_MTL 1
38#define IVPU_HW_BTRS_LNL 2
32 39
33#define IVPU_GLOBAL_CONTEXT_MMU_SSID 040#define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
34/* SSID 1 is used by the VPU to represent reserved context */41/* SSID 1 is used by the VPU to represent reserved context */
@@ -39,7 +46,11 @@ · 4 unmodified lines
39#define IVPU_MIN_DB 146#define IVPU_MIN_DB 1
40#define IVPU_MAX_DB 25547#define IVPU_MAX_DB 255
41 48
42#define IVPU_NUM_ENGINES 249#define IVPU_NUM_ENGINES 2
50#define IVPU_NUM_PRIORITIES 4
51#define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_ENGINES * IVPU_NUM_PRIORITIES)
52
53#define IVPU_CMDQ_INDEX(engine, priority) ((engine) * IVPU_NUM_PRIORITIES + (priority))
43 54
44#define IVPU_PLATFORM_SILICON 055#define IVPU_PLATFORM_SILICON 0
45#define IVPU_PLATFORM_SIMICS 256#define IVPU_PLATFORM_SIMICS 2
@@ -93,6 +104,7 @@ struct ivpu_wa_table { · 47 unmodified lines
93 bool interrupt_clear_with_0;104 bool interrupt_clear_with_0;
94 bool disable_clock_relinquish;105 bool disable_clock_relinquish;
95 bool disable_d0i3_msg;106 bool disable_d0i3_msg;
107 bool wp0_during_power_up;
96};108};
97 109
98struct ivpu_hw_info;110struct ivpu_hw_info;
@@ -131,11 +143,13 @@ struct ivpu_device { · 32 unmodified lines
131 143
132 atomic64_t unique_id_counter;144 atomic64_t unique_id_counter;
133 145
146 ktime_t busy_start_ts;
147 ktime_t busy_time;
148
134 struct {149 struct {
135 int boot;150 int boot;
136 int jsm;151 int jsm;
137 int tdr;152 int tdr;
138 int reschedule_suspend;
139 int autosuspend;153 int autosuspend;
140 int d0i3_entry_msg;154 int d0i3_entry_msg;
141 } timeout;155 } timeout;
@@ -149,22 +163,31 @@ struct ivpu_file_priv { · 7 unmodified lines
149 struct kref ref;163 struct kref ref;
150 struct ivpu_device *vdev;164 struct ivpu_device *vdev;
151 struct mutex lock; /* Protects cmdq */165 struct mutex lock; /* Protects cmdq */
152 struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES];166 struct ivpu_cmdq *cmdq[IVPU_NUM_CMDQS_PER_CTX];
153 struct ivpu_mmu_context ctx;167 struct ivpu_mmu_context ctx;
168 struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
169 struct list_head ms_instance_list;
170 struct ivpu_bo *ms_info_bo;
154 bool has_mmu_faults;171 bool has_mmu_faults;
155 bool bound;172 bool bound;
173 bool aborted;
156};174};
157 175
158extern int ivpu_dbg_mask;176extern int ivpu_dbg_mask;
159extern u8 ivpu_pll_min_ratio;177extern u8 ivpu_pll_min_ratio;
160extern u8 ivpu_pll_max_ratio;178extern u8 ivpu_pll_max_ratio;
179extern int ivpu_sched_mode;
161extern bool ivpu_disable_mmu_cont_pages;180extern bool ivpu_disable_mmu_cont_pages;
181extern bool ivpu_force_snoop;
162 182
163#define IVPU_TEST_MODE_FW_TEST BIT(0)183#define IVPU_TEST_MODE_FW_TEST BIT(0)
164#define IVPU_TEST_MODE_NULL_HW BIT(1)184#define IVPU_TEST_MODE_NULL_HW BIT(1)
165#define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)185#define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)
166#define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)186#define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)
167#define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)187#define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)
188#define IVPU_TEST_MODE_PREEMPTION_DISABLE BIT(6)
189#define IVPU_TEST_MODE_HWS_EXTRA_EVENTS BIT(7)
190#define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8)
168extern int ivpu_test_mode;191extern int ivpu_test_mode;
169 192
170struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);193struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
@@ -184,16 +207,32 @@ static inline u16 ivpu_device_id(struct ivpu_device *vdev) · 13 unmodified lines
184 return to_pci_dev(vdev->drm.dev)->device;207 return to_pci_dev(vdev->drm.dev)->device;
185}208}
186 209
187static inline int ivpu_hw_gen(struct ivpu_device *vdev)210static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
188{211{
189 switch (ivpu_device_id(vdev)) {212 switch (ivpu_device_id(vdev)) {
190 case PCI_DEVICE_ID_MTL:213 case PCI_DEVICE_ID_MTL:
191 case PCI_DEVICE_ID_ARL:214 case PCI_DEVICE_ID_ARL:
192 return IVPU_HW_37XX;215 return IVPU_HW_IP_37XX;
193 case PCI_DEVICE_ID_LNL:216 case PCI_DEVICE_ID_LNL:
194 return IVPU_HW_40XX;217 return IVPU_HW_IP_40XX;
195 default:218 default:
196 ivpu_err(vdev, "Unknown NPU device\n");219 dump_stack();
220 ivpu_err(vdev, "Unknown NPU IP generation\n");
221 return 0;
222 }
223}
224
225static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
226{
227 switch (ivpu_device_id(vdev)) {
228 case PCI_DEVICE_ID_MTL:
229 case PCI_DEVICE_ID_ARL:
230 return IVPU_HW_BTRS_MTL;
231 case PCI_DEVICE_ID_LNL:
232 return IVPU_HW_BTRS_LNL;
233 default:
234 dump_stack();
235 ivpu_err(vdev, "Unknown buttress generation\n");
197 return 0;236 return 0;
198 }237 }
199}238}
@@ -231,4 +270,9 @@ static inline bool ivpu_is_fpga(struct ivpu_device *vdev) · 31 unmodified lines
231 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;270 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
232}271}
233 272
273static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
274{
275 return ivpu_force_snoop;
276}
277
234#endif /* __IVPU_DRV_H__ */278#endif /* __IVPU_DRV_H__ */
drivers/accel/ivpu/ivpu_fw.c+50−11
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0-only1// SPDX-License-Identifier: GPL-2.0-only
2/*2/*
3 * Copyright (C) 2020-2023 Intel Corporation3 * Copyright (C) 2020-2024 Intel Corporation
4 */4 */
5 5
6#include <linux/firmware.h>6#include <linux/firmware.h>
@@ -44,6 +44,8 @@ · 37 unmodified lines
44#define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \44#define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \
45 ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor)45 ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor)
46 46
47#define IVPU_FOCUS_PRESENT_TIMER_MS 1000
48
47static char *ivpu_firmware;49static char *ivpu_firmware;
48module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644);50module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644);
49MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/..");51MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/..");
@@ -52,10 +54,10 @@ static struct { · 2 unmodified lines
52 int gen;54 int gen;
53 const char *name;55 const char *name;
54} fw_names[] = {56} fw_names[] = {
55 { IVPU_HW_37XX, "vpu_37xx.bin" },57 { IVPU_HW_IP_37XX, "vpu_37xx.bin" },
56 { IVPU_HW_37XX, "intel/vpu/vpu_37xx_v0.0.bin" },58 { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" },
57 { IVPU_HW_40XX, "vpu_40xx.bin" },59 { IVPU_HW_IP_40XX, "vpu_40xx.bin" },
58 { IVPU_HW_40XX, "intel/vpu/vpu_40xx_v0.0.bin" },60 { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" },
59};61};
60 62
61static int ivpu_fw_request(struct ivpu_device *vdev)63static int ivpu_fw_request(struct ivpu_device *vdev)
@@ -71,7 +73,7 @@ static int ivpu_fw_request(struct ivpu_device *vdev) · 9 unmodified lines
71 }73 }
72 74
73 for (i = 0; i < ARRAY_SIZE(fw_names); i++) {75 for (i = 0; i < ARRAY_SIZE(fw_names); i++) {
74 if (fw_names[i].gen != ivpu_hw_gen(vdev))76 if (fw_names[i].gen != ivpu_hw_ip_gen(vdev))
75 continue;77 continue;
76 78
77 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev);79 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev);
@@ -121,6 +123,14 @@ ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_hea · 43 unmodified lines
121 return false;123 return false;
122}124}
123 125
126static bool is_within_range(u64 addr, size_t size, u64 range_start, size_t range_size)
127{
128 if (addr < range_start || addr + size > range_start + range_size)
129 return false;
130
131 return true;
132}
133
124static int ivpu_fw_parse(struct ivpu_device *vdev)134static int ivpu_fw_parse(struct ivpu_device *vdev)
125{135{
126 struct ivpu_fw_info *fw = vdev->fw;136 struct ivpu_fw_info *fw = vdev->fw;
@@ -200,10 +210,27 @@ static int ivpu_fw_parse(struct ivpu_device *vdev) · 73 unmodified lines
200 210
201 fw->dvfs_mode = 0;211 fw->dvfs_mode = 0;
202 212
213 fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size;
214 fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size;
215
216 if (fw_hdr->ro_section_start_address && !is_within_range(fw_hdr->ro_section_start_address,
217 fw_hdr->ro_section_size,
218 fw_hdr->image_load_address,
219 fw_hdr->image_size)) {
220 ivpu_err(vdev, "Invalid read-only section: start address 0x%llx, size %u\n",
221 fw_hdr->ro_section_start_address, fw_hdr->ro_section_size);
222 return -EINVAL;
223 }
224
225 fw->read_only_addr = fw_hdr->ro_section_start_address;
226 fw->read_only_size = fw_hdr->ro_section_size;
227
203 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n",228 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n",
204 fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size);229 fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size);
205 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n",230 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n",
206 fw->runtime_addr, image_load_addr, fw->entry_point);231 fw->runtime_addr, image_load_addr, fw->entry_point);
232 ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n",
233 fw->read_only_addr, fw->read_only_size);
207 234
208 return 0;235 return 0;
209}236}
@@ -241,7 +268,7 @@ static int ivpu_fw_update_global_range(struct ivpu_device *vdev) · 31 unmodified lines
241 return -EINVAL;268 return -EINVAL;
242 }269 }
243 270
244 ivpu_hw_init_range(&vdev->hw->ranges.global, start, size);271 ivpu_hw_range_init(&vdev->hw->ranges.global, start, size);
245 return 0;272 return 0;
246}273}
247 274
@@ -265,6 +292,13 @@ static int ivpu_fw_mem_init(struct ivpu_device *vdev) · 17 unmodified lines
265 return -ENOMEM;292 return -ENOMEM;
266 }293 }
267 294
295 ret = ivpu_mmu_context_set_pages_ro(vdev, &vdev->gctx, fw->read_only_addr,
296 fw->read_only_size);
297 if (ret) {
298 ivpu_err(vdev, "Failed to set firmware image read-only\n");
299 goto err_free_fw_mem;
300 }
301
268 fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE,302 fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE,
269 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);303 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
270 if (!fw->mem_log_crit) {304 if (!fw->mem_log_crit) {
@@ -464,6 +498,8 @@ static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_ · 193 unmodified lines
464 boot_params->punit_telemetry_sram_size);498 boot_params->punit_telemetry_sram_size);
465 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n",499 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n",
466 boot_params->vpu_telemetry_enable);500 boot_params->vpu_telemetry_enable);
501 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_scheduling_mode = 0x%x\n",
502 boot_params->vpu_scheduling_mode);
467 ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n",503 ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n",
468 boot_params->dvfs_mode);504 boot_params->dvfs_mode);
469 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n",505 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n",
@@ -504,7 +540,7 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params · 34 unmodified lines
504 540
505 boot_params->magic = VPU_BOOT_PARAMS_MAGIC;541 boot_params->magic = VPU_BOOT_PARAMS_MAGIC;
506 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number;542 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number;
507 boot_params->frequency = ivpu_hw_reg_pll_freq_get(vdev);543 boot_params->frequency = ivpu_hw_pll_freq_get(vdev);
508 544
509 /*545 /*
510 * This param is a debug firmware feature. It switches default clock546 * This param is a debug firmware feature. It switches default clock
@@ -561,9 +597,12 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params · 50 unmodified lines
561 boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr;597 boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr;
562 boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb);598 boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb);
563 599
564 boot_params->punit_telemetry_sram_base = ivpu_hw_reg_telemetry_offset_get(vdev);600 boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev);
565 boot_params->punit_telemetry_sram_size = ivpu_hw_reg_telemetry_size_get(vdev);601 boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev);
566 boot_params->vpu_telemetry_enable = ivpu_hw_reg_telemetry_enable_get(vdev);602 boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev);
603 boot_params->vpu_scheduling_mode = vdev->hw->sched_mode;
604 if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW)
605 boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS;
567 boot_params->dvfs_mode = vdev->fw->dvfs_mode;606 boot_params->dvfs_mode = vdev->fw->dvfs_mode;
568 if (!IVPU_WA(disable_d0i3_msg))607 if (!IVPU_WA(disable_d0i3_msg))
569 boot_params->d0i3_delayed_entry = 1;608 boot_params->d0i3_delayed_entry = 1;
drivers/accel/ivpu/ivpu_fw.h+4−0
@@ -28,6 +28,10 @@ struct ivpu_fw_info { · 27 unmodified lines
28 u32 trace_destination_mask;28 u32 trace_destination_mask;
29 u64 trace_hw_component_mask;29 u64 trace_hw_component_mask;
30 u32 dvfs_mode;30 u32 dvfs_mode;
31 u32 primary_preempt_buf_size;
32 u32 secondary_preempt_buf_size;
33 u64 read_only_addr;
34 u32 read_only_size;
31};35};
32 36
33int ivpu_fw_init(struct ivpu_device *vdev);37int ivpu_fw_init(struct ivpu_device *vdev);
drivers/accel/ivpu/ivpu_gem.h+7−4
@@ -60,14 +60,17 @@ static inline u32 ivpu_bo_cache_mode(struct ivpu_bo *bo) · 59 unmodified lines
60 return bo->flags & DRM_IVPU_BO_CACHE_MASK;60 return bo->flags & DRM_IVPU_BO_CACHE_MASK;
61}61}
62 62
63static inline bool ivpu_bo_is_snooped(struct ivpu_bo *bo)63static inline struct ivpu_device *ivpu_bo_to_vdev(struct ivpu_bo *bo)
64{64{
65 return ivpu_bo_cache_mode(bo) == DRM_IVPU_BO_CACHED;65 return to_ivpu_device(bo->base.base.dev);
66}66}
67 67
68static inline struct ivpu_device *ivpu_bo_to_vdev(struct ivpu_bo *bo)68static inline bool ivpu_bo_is_snooped(struct ivpu_bo *bo)
69{69{
70 return to_ivpu_device(bo->base.base.dev);70 if (ivpu_is_force_snoop_enabled(ivpu_bo_to_vdev(bo)))
71 return true;
72
73 return ivpu_bo_cache_mode(bo) == DRM_IVPU_BO_CACHED;
71}74}
72 75
73static inline void *ivpu_to_cpu_addr(struct ivpu_bo *bo, u32 vpu_addr)76static inline void *ivpu_to_cpu_addr(struct ivpu_bo *bo, u32 vpu_addr)
drivers/accel/ivpu/ivpu_hw.c+331−0
@@ -0,0 +1,331 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020 - 2024 Intel Corporation
4 */
5
6#include "ivpu_drv.h"
7#include "ivpu_hw.h"
8#include "ivpu_hw_btrs.h"
9#include "ivpu_hw_ip.h"
10
11#include <linux/dmi.h>
12
13static char *platform_to_str(u32 platform)
14{
15 switch (platform) {
16 case IVPU_PLATFORM_SILICON:
17 return "SILICON";
18 case IVPU_PLATFORM_SIMICS:
19 return "SIMICS";
20 case IVPU_PLATFORM_FPGA:
21 return "FPGA";
22 default:
23 return "Invalid platform";
24 }
25}
26
27static const struct dmi_system_id dmi_platform_simulation[] = {
28 {
29 .ident = "Intel Simics",
30 .matches = {
31 DMI_MATCH(DMI_BOARD_NAME, "lnlrvp"),
32 DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
33 DMI_MATCH(DMI_BOARD_SERIAL, "123456789"),
34 },
35 },
36 {
37 .ident = "Intel Simics",
38 .matches = {
39 DMI_MATCH(DMI_BOARD_NAME, "Simics"),
40 },
41 },
42 { }
43};
44
45static void platform_init(struct ivpu_device *vdev)
46{
47 if (dmi_check_system(dmi_platform_simulation))
48 vdev->platform = IVPU_PLATFORM_SIMICS;
49 else
50 vdev->platform = IVPU_PLATFORM_SILICON;
51
52 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n",
53 platform_to_str(vdev->platform), vdev->platform);
54}
55
56static void wa_init(struct ivpu_device *vdev)
57{
58 vdev->wa.punit_disabled = ivpu_is_fpga(vdev);
59 vdev->wa.clear_runtime_mem = false;
60
61 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
62 vdev->wa.interrupt_clear_with_0 = ivpu_hw_btrs_irqs_clear_with_0_mtl(vdev);
63
64 if (ivpu_device_id(vdev) == PCI_DEVICE_ID_LNL &&
65 ivpu_revision(vdev) < IVPU_HW_IP_REV_LNL_B0)
66 vdev->wa.disable_clock_relinquish = true;
67
68 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
69 vdev->wa.wp0_during_power_up = true;
70
71 IVPU_PRINT_WA(punit_disabled);
72 IVPU_PRINT_WA(clear_runtime_mem);
73 IVPU_PRINT_WA(interrupt_clear_with_0);
74 IVPU_PRINT_WA(disable_clock_relinquish);
75 IVPU_PRINT_WA(wp0_during_power_up);
76}
77
78static void timeouts_init(struct ivpu_device *vdev)
79{
80 if (ivpu_test_mode & IVPU_TEST_MODE_DISABLE_TIMEOUTS) {
81 vdev->timeout.boot = -1;
82 vdev->timeout.jsm = -1;
83 vdev->timeout.tdr = -1;
84 vdev->timeout.autosuspend = -1;
85 vdev->timeout.d0i3_entry_msg = -1;
86 } else if (ivpu_is_fpga(vdev)) {
87 vdev->timeout.boot = 100000;
88 vdev->timeout.jsm = 50000;
89 vdev->timeout.tdr = 2000000;
90 vdev->timeout.autosuspend = -1;
91 vdev->timeout.d0i3_entry_msg = 500;
92 } else if (ivpu_is_simics(vdev)) {
93 vdev->timeout.boot = 50;
94 vdev->timeout.jsm = 500;
95 vdev->timeout.tdr = 10000;
96 vdev->timeout.autosuspend = -1;
97 vdev->timeout.d0i3_entry_msg = 100;
98 } else {
99 vdev->timeout.boot = 1000;
100 vdev->timeout.jsm = 500;
101 vdev->timeout.tdr = 2000;
102 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
103 vdev->timeout.autosuspend = 10;
104 else
105 vdev->timeout.autosuspend = 100;
106 vdev->timeout.d0i3_entry_msg = 5;
107 }
108}
109
110static void memory_ranges_init(struct ivpu_device *vdev)
111{
112 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
113 ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
114 ivpu_hw_range_init(&vdev->hw->ranges.user, 0xc0000000, 255 * SZ_1M);
115 ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x180000000, SZ_2G);
116 ivpu_hw_range_init(&vdev->hw->ranges.dma, 0x200000000, SZ_8G);
117 } else {
118 ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
119 ivpu_hw_range_init(&vdev->hw->ranges.user, 0x80000000, SZ_256M);
120 ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x80000000 + SZ_256M, SZ_2G - SZ_256M);
121 ivpu_hw_range_init(&vdev->hw->ranges.dma, 0x200000000, SZ_8G);
122 }
123}
124
125static int wp_enable(struct ivpu_device *vdev)
126{
127 return ivpu_hw_btrs_wp_drive(vdev, true);
128}
129
130static int wp_disable(struct ivpu_device *vdev)
131{
132 return ivpu_hw_btrs_wp_drive(vdev, false);
133}
134
135int ivpu_hw_power_up(struct ivpu_device *vdev)
136{
137 int ret;
138
139 if (IVPU_WA(wp0_during_power_up)) {
140 /* WP requests may fail when powering down, so issue WP 0 here */
141 ret = wp_disable(vdev);
142 if (ret)
143 ivpu_warn(vdev, "Failed to disable workpoint: %d\n", ret);
144 }
145
146 ret = ivpu_hw_btrs_d0i3_disable(vdev);
147 if (ret)
148 ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret);
149
150 ret = wp_enable(vdev);
151 if (ret) {
152 ivpu_err(vdev, "Failed to enable workpoint: %d\n", ret);
153 return ret;
154 }
155
156 if (ivpu_hw_btrs_gen(vdev) >= IVPU_HW_BTRS_LNL) {
157 if (IVPU_WA(disable_clock_relinquish))
158 ivpu_hw_btrs_clock_relinquish_disable_lnl(vdev);
159 ivpu_hw_btrs_profiling_freq_reg_set_lnl(vdev);
160 ivpu_hw_btrs_ats_print_lnl(vdev);
161 }
162
163 ret = ivpu_hw_ip_host_ss_configure(vdev);
164 if (ret) {
165 ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
166 return ret;
167 }
168
169 ivpu_hw_ip_idle_gen_disable(vdev);
170
171 ret = ivpu_hw_btrs_wait_for_clock_res_own_ack(vdev);
172 if (ret) {
173 ivpu_err(vdev, "Timed out waiting for clock resource own ACK\n");
174 return ret;
175 }
176
177 ret = ivpu_hw_ip_pwr_domain_enable(vdev);
178 if (ret) {
179 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
180 return ret;
181 }
182
183 ret = ivpu_hw_ip_host_ss_axi_enable(vdev);
184 if (ret) {
185 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
186 return ret;
187 }
188
189 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_LNL)
190 ivpu_hw_btrs_set_port_arbitration_weights_lnl(vdev);
191
192 ret = ivpu_hw_ip_top_noc_enable(vdev);
193 if (ret)
194 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);
195
196 return ret;
197}
198
199static void save_d0i3_entry_timestamp(struct ivpu_device *vdev)
200{
201 vdev->hw->d0i3_entry_host_ts = ktime_get_boottime();
202 vdev->hw->d0i3_entry_vpu_ts = ivpu_hw_ip_read_perf_timer_counter(vdev);
203}
204
205int ivpu_hw_reset(struct ivpu_device *vdev)
206{
207 int ret = 0;
208
209 if (ivpu_hw_btrs_ip_reset(vdev)) {
210 ivpu_err(vdev, "Failed to reset NPU IP\n");
211 ret = -EIO;
212 }
213
214 if (wp_disable(vdev)) {
215 ivpu_err(vdev, "Failed to disable workpoint\n");
216 ret = -EIO;
217 }
218
219 return ret;
220}
221
222int ivpu_hw_power_down(struct ivpu_device *vdev)
223{
224 int ret = 0;
225
226 save_d0i3_entry_timestamp(vdev);
227
228 if (!ivpu_hw_is_idle(vdev))
229 ivpu_warn(vdev, "NPU not idle during power down\n");
230
231 if (ivpu_hw_reset(vdev)) {
232 ivpu_err(vdev, "Failed to reset NPU\n");
233 ret = -EIO;
234 }
235
236 if (ivpu_hw_btrs_d0i3_enable(vdev)) {
237 ivpu_err(vdev, "Failed to enter D0I3\n");
238 ret = -EIO;
239 }
240
241 return ret;
242}
243
244int ivpu_hw_init(struct ivpu_device *vdev)
245{
246 ivpu_hw_btrs_info_init(vdev);
247 ivpu_hw_btrs_freq_ratios_init(vdev);
248 memory_ranges_init(vdev);
249 platform_init(vdev);
250 wa_init(vdev);
251 timeouts_init(vdev);
252
253 return 0;
254}
255
256int ivpu_hw_boot_fw(struct ivpu_device *vdev)
257{
258 int ret;
259
260 ivpu_hw_ip_snoop_disable(vdev);
261 ivpu_hw_ip_tbu_mmu_enable(vdev);
262 ret = ivpu_hw_ip_soc_cpu_boot(vdev);
263 if (ret)
264 ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret);
265
266 return ret;
267}
268
269void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable)
270{
271 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
272 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
273 return;
274 }
275
276 if (enable)
277 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_HIGH;
278 else
279 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
280}
281
282void ivpu_irq_handlers_init(struct ivpu_device *vdev)
283{
284 INIT_KFIFO(vdev->hw->irq.fifo);
285
286 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
287 vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_37xx;
288 else
289 vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_40xx;
290
291 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
292 vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_mtl;
293 else
294 vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_lnl;
295}
296
297void ivpu_hw_irq_enable(struct ivpu_device *vdev)
298{
299 kfifo_reset(&vdev->hw->irq.fifo);
300 ivpu_hw_ip_irq_enable(vdev);
301 ivpu_hw_btrs_irq_enable(vdev);
302}
303
304void ivpu_hw_irq_disable(struct ivpu_device *vdev)
305{
306 ivpu_hw_btrs_irq_disable(vdev);
307 ivpu_hw_ip_irq_disable(vdev);
308}
309
310irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr)
311{
312 struct ivpu_device *vdev = ptr;
313 bool ip_handled, btrs_handled;
314
315 ivpu_hw_btrs_global_int_disable(vdev);
316
317 btrs_handled = ivpu_hw_btrs_irq_handler(vdev, irq);
318 if (!ivpu_hw_is_idle((vdev)) || !btrs_handled)
319 ip_handled = ivpu_hw_ip_irq_handler(vdev, irq);
320 else
321 ip_handled = false;
322
323 /* Re-enable global interrupts to re-trigger MSI for pending interrupts */
324 ivpu_hw_btrs_global_int_enable(vdev);
325
326 if (!kfifo_is_empty(&vdev->hw->irq.fifo))
327 return IRQ_WAKE_THREAD;
328 if (ip_handled || btrs_handled)
329 return IRQ_HANDLED;
330 return IRQ_NONE;
331}
drivers/accel/ivpu/ivpu_hw.h+77−122
@@ -1,39 +1,22 @@
1/* SPDX-License-Identifier: GPL-2.0-only */1/* SPDX-License-Identifier: GPL-2.0-only */
2/*2/*
3 * Copyright (C) 2020-2023 Intel Corporation3 * Copyright (C) 2020-2024 Intel Corporation
4 */4 */
5 5
6#ifndef __IVPU_HW_H__6#ifndef __IVPU_HW_H__
7#define __IVPU_HW_H__7#define __IVPU_HW_H__
8 8
9#include <linux/kfifo.h>
10
9#include "ivpu_drv.h"11#include "ivpu_drv.h"
12#include "ivpu_hw_btrs.h"
13#include "ivpu_hw_ip.h"
10 14
11struct ivpu_hw_ops {15#define IVPU_HW_IRQ_FIFO_LENGTH 1024
12 int (*info_init)(struct ivpu_device *vdev);16
13 int (*power_up)(struct ivpu_device *vdev);17#define IVPU_HW_IRQ_SRC_IPC 1
14 int (*boot_fw)(struct ivpu_device *vdev);18#define IVPU_HW_IRQ_SRC_MMU_EVTQ 2
15 int (*power_down)(struct ivpu_device *vdev);19#define IVPU_HW_IRQ_SRC_DCT 3
16 int (*reset)(struct ivpu_device *vdev);
17 bool (*is_idle)(struct ivpu_device *vdev);
18 int (*wait_for_idle)(struct ivpu_device *vdev);
19 void (*wdt_disable)(struct ivpu_device *vdev);
20 void (*diagnose_failure)(struct ivpu_device *vdev);
21 u32 (*profiling_freq_get)(struct ivpu_device *vdev);
22 void (*profiling_freq_drive)(struct ivpu_device *vdev, bool enable);
23 u32 (*reg_pll_freq_get)(struct ivpu_device *vdev);
24 u32 (*ratio_to_freq)(struct ivpu_device *vdev, u32 ratio);
25 u32 (*reg_telemetry_offset_get)(struct ivpu_device *vdev);
26 u32 (*reg_telemetry_size_get)(struct ivpu_device *vdev);
27 u32 (*reg_telemetry_enable_get)(struct ivpu_device *vdev);
28 void (*reg_db_set)(struct ivpu_device *vdev, u32 db_id);
29 u32 (*reg_ipc_rx_addr_get)(struct ivpu_device *vdev);
30 u32 (*reg_ipc_rx_count_get)(struct ivpu_device *vdev);
31 void (*reg_ipc_tx_set)(struct ivpu_device *vdev, u32 vpu_addr);
32 void (*irq_clear)(struct ivpu_device *vdev);
33 void (*irq_enable)(struct ivpu_device *vdev);
34 void (*irq_disable)(struct ivpu_device *vdev);
35 irqreturn_t (*irq_handler)(int irq, void *ptr);
36};
37 20
38struct ivpu_addr_range {21struct ivpu_addr_range {
39 resource_size_t start;22 resource_size_t start;
@@ -41,7 +24,11 @@ struct ivpu_addr_range { · 1 unmodified line
41};24};
42 25
43struct ivpu_hw_info {26struct ivpu_hw_info {
44 const struct ivpu_hw_ops *ops;27 struct {
28 bool (*btrs_irq_handler)(struct ivpu_device *vdev, int irq);
29 bool (*ip_irq_handler)(struct ivpu_device *vdev, int irq);
30 DECLARE_KFIFO(fifo, u8, IVPU_HW_IRQ_FIFO_LENGTH);
31 } irq;
45 struct {32 struct {
46 struct ivpu_addr_range global;33 struct ivpu_addr_range global;
47 struct ivpu_addr_range user;34 struct ivpu_addr_range user;
@@ -59,6 +46,7 @@ struct ivpu_hw_info { · 11 unmodified lines
59 u32 profiling_freq;46 u32 profiling_freq;
60 } pll;47 } pll;
61 u32 tile_fuse;48 u32 tile_fuse;
49 u32 sched_mode;
62 u32 sku;50 u32 sku;
63 u16 config;51 u16 config;
64 int dma_bits;52 int dma_bits;
@@ -66,140 +54,107 @@ struct ivpu_hw_info { · 1 unmodified line
66 u64 d0i3_entry_vpu_ts;54 u64 d0i3_entry_vpu_ts;
67};55};
68 56
69extern const struct ivpu_hw_ops ivpu_hw_37xx_ops;57int ivpu_hw_init(struct ivpu_device *vdev);
70extern const struct ivpu_hw_ops ivpu_hw_40xx_ops;58int ivpu_hw_power_up(struct ivpu_device *vdev);
71 59int ivpu_hw_power_down(struct ivpu_device *vdev);
72static inline int ivpu_hw_info_init(struct ivpu_device *vdev)60int ivpu_hw_reset(struct ivpu_device *vdev);
73{61int ivpu_hw_boot_fw(struct ivpu_device *vdev);
74 return vdev->hw->ops->info_init(vdev);62void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable);
75};63void ivpu_irq_handlers_init(struct ivpu_device *vdev);
76 64void ivpu_hw_irq_enable(struct ivpu_device *vdev);
77static inline int ivpu_hw_power_up(struct ivpu_device *vdev)65void ivpu_hw_irq_disable(struct ivpu_device *vdev);
78{66irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr);
79 ivpu_dbg(vdev, PM, "HW power up\n");
80 67
81 return vdev->hw->ops->power_up(vdev);68static inline u32 ivpu_hw_btrs_irq_handler(struct ivpu_device *vdev, int irq)
82};
83
84static inline int ivpu_hw_boot_fw(struct ivpu_device *vdev)
85{
86 return vdev->hw->ops->boot_fw(vdev);
87};
88
89static inline bool ivpu_hw_is_idle(struct ivpu_device *vdev)
90{
91 return vdev->hw->ops->is_idle(vdev);
92};
93
94static inline int ivpu_hw_wait_for_idle(struct ivpu_device *vdev)
95{69{
96 return vdev->hw->ops->wait_for_idle(vdev);70 return vdev->hw->irq.btrs_irq_handler(vdev, irq);
97};71}
98
99static inline int ivpu_hw_power_down(struct ivpu_device *vdev)
100{
101 ivpu_dbg(vdev, PM, "HW power down\n");
102
103 return vdev->hw->ops->power_down(vdev);
104};
105
106static inline int ivpu_hw_reset(struct ivpu_device *vdev)
107{
108 ivpu_dbg(vdev, PM, "HW reset\n");
109
110 return vdev->hw->ops->reset(vdev);
111};
112
113static inline void ivpu_hw_wdt_disable(struct ivpu_device *vdev)
114{
115 vdev->hw->ops->wdt_disable(vdev);
116};
117 72
118static inline u32 ivpu_hw_profiling_freq_get(struct ivpu_device *vdev)73static inline u32 ivpu_hw_ip_irq_handler(struct ivpu_device *vdev, int irq)
119{74{
120 return vdev->hw->ops->profiling_freq_get(vdev);75 return vdev->hw->irq.ip_irq_handler(vdev, irq);
121};76}
122 77
123static inline void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable)78static inline void ivpu_hw_range_init(struct ivpu_addr_range *range, u64 start, u64 size)
124{79{
125 return vdev->hw->ops->profiling_freq_drive(vdev, enable);80 range->start = start;
126};81 range->end = start + size;
82}
127 83
128/* Register indirect accesses */84static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range)
129static inline u32 ivpu_hw_reg_pll_freq_get(struct ivpu_device *vdev)
130{85{
131 return vdev->hw->ops->reg_pll_freq_get(vdev);86 return range->end - range->start;
132};87}
133 88
134static inline u32 ivpu_hw_ratio_to_freq(struct ivpu_device *vdev, u32 ratio)89static inline u32 ivpu_hw_ratio_to_freq(struct ivpu_device *vdev, u32 ratio)
135{90{
136 return vdev->hw->ops->ratio_to_freq(vdev, ratio);91 return ivpu_hw_btrs_ratio_to_freq(vdev, ratio);
137}92}
138 93
139static inline u32 ivpu_hw_reg_telemetry_offset_get(struct ivpu_device *vdev)94static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev)
140{95{
141 return vdev->hw->ops->reg_telemetry_offset_get(vdev);96 ivpu_hw_ip_irq_clear(vdev);
142};97}
143 98
144static inline u32 ivpu_hw_reg_telemetry_size_get(struct ivpu_device *vdev)99static inline u32 ivpu_hw_pll_freq_get(struct ivpu_device *vdev)
145{100{
146 return vdev->hw->ops->reg_telemetry_size_get(vdev);101 return ivpu_hw_btrs_pll_freq_get(vdev);
147};102}
148 103
149static inline u32 ivpu_hw_reg_telemetry_enable_get(struct ivpu_device *vdev)104static inline u32 ivpu_hw_profiling_freq_get(struct ivpu_device *vdev)
150{105{
151 return vdev->hw->ops->reg_telemetry_enable_get(vdev);106 return vdev->hw->pll.profiling_freq;
152};107}
153 108
154static inline void ivpu_hw_reg_db_set(struct ivpu_device *vdev, u32 db_id)109static inline void ivpu_hw_diagnose_failure(struct ivpu_device *vdev)
155{110{
156 vdev->hw->ops->reg_db_set(vdev, db_id);111 ivpu_hw_ip_diagnose_failure(vdev);
157};112 ivpu_hw_btrs_diagnose_failure(vdev);
113}
158 114
159static inline u32 ivpu_hw_reg_ipc_rx_addr_get(struct ivpu_device *vdev)115static inline u32 ivpu_hw_telemetry_offset_get(struct ivpu_device *vdev)
160{116{
161 return vdev->hw->ops->reg_ipc_rx_addr_get(vdev);117 return ivpu_hw_btrs_telemetry_offset_get(vdev);
162};118}
163 119
164static inline u32 ivpu_hw_reg_ipc_rx_count_get(struct ivpu_device *vdev)120static inline u32 ivpu_hw_telemetry_size_get(struct ivpu_device *vdev)
165{121{
166 return vdev->hw->ops->reg_ipc_rx_count_get(vdev);122 return ivpu_hw_btrs_telemetry_size_get(vdev);
167};123}
168 124
169static inline void ivpu_hw_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)125static inline u32 ivpu_hw_telemetry_enable_get(struct ivpu_device *vdev)
170{126{
171 vdev->hw->ops->reg_ipc_tx_set(vdev, vpu_addr);127 return ivpu_hw_btrs_telemetry_enable_get(vdev);
172};128}
173 129
174static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev)130static inline bool ivpu_hw_is_idle(struct ivpu_device *vdev)
175{131{
176 vdev->hw->ops->irq_clear(vdev);132 return ivpu_hw_btrs_is_idle(vdev);
177};133}
178 134
179static inline void ivpu_hw_irq_enable(struct ivpu_device *vdev)135static inline int ivpu_hw_wait_for_idle(struct ivpu_device *vdev)
180{136{
181 vdev->hw->ops->irq_enable(vdev);137 return ivpu_hw_btrs_wait_for_idle(vdev);
182};138}
183 139
184static inline void ivpu_hw_irq_disable(struct ivpu_device *vdev)140static inline void ivpu_hw_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
185{141{
186 vdev->hw->ops->irq_disable(vdev);142 ivpu_hw_ip_ipc_tx_set(vdev, vpu_addr);
187};143}
188 144
189static inline void ivpu_hw_init_range(struct ivpu_addr_range *range, u64 start, u64 size)145static inline void ivpu_hw_db_set(struct ivpu_device *vdev, u32 db_id)
190{146{
191 range->start = start;147 ivpu_hw_ip_db_set(vdev, db_id);
192 range->end = start + size;
193}148}
194 149
195static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range)150static inline u32 ivpu_hw_ipc_rx_addr_get(struct ivpu_device *vdev)
196{151{
197 return range->end - range->start;152 return ivpu_hw_ip_ipc_rx_addr_get(vdev);
198}153}
199 154
200static inline void ivpu_hw_diagnose_failure(struct ivpu_device *vdev)155static inline u32 ivpu_hw_ipc_rx_count_get(struct ivpu_device *vdev)
201{156{
202 vdev->hw->ops->diagnose_failure(vdev);157 return ivpu_hw_ip_ipc_rx_count_get(vdev);
203}158}
204 159
205#endif /* __IVPU_HW_H__ */160#endif /* __IVPU_HW_H__ */
drivers/accel/ivpu/ivpu_hw_37xx.c+0−1065
@@ -1,1065 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6#include "ivpu_drv.h"
7#include "ivpu_fw.h"
8#include "ivpu_hw_37xx_reg.h"
9#include "ivpu_hw_reg_io.h"
10#include "ivpu_hw.h"
11#include "ivpu_ipc.h"
12#include "ivpu_mmu.h"
13#include "ivpu_pm.h"
14
15#define TILE_FUSE_ENABLE_BOTH 0x0
16#define TILE_SKU_BOTH 0x3630
17
18/* Work point configuration values */
19#define CONFIG_1_TILE 0x01
20#define CONFIG_2_TILE 0x02
21#define PLL_RATIO_5_3 0x01
22#define PLL_RATIO_4_3 0x02
23#define WP_CONFIG(tile, ratio) (((tile) << 8) | (ratio))
24#define WP_CONFIG_1_TILE_5_3_RATIO WP_CONFIG(CONFIG_1_TILE, PLL_RATIO_5_3)
25#define WP_CONFIG_1_TILE_4_3_RATIO WP_CONFIG(CONFIG_1_TILE, PLL_RATIO_4_3)
26#define WP_CONFIG_2_TILE_5_3_RATIO WP_CONFIG(CONFIG_2_TILE, PLL_RATIO_5_3)
27#define WP_CONFIG_2_TILE_4_3_RATIO WP_CONFIG(CONFIG_2_TILE, PLL_RATIO_4_3)
28#define WP_CONFIG_0_TILE_PLL_OFF WP_CONFIG(0, 0)
29
30#define PLL_REF_CLK_FREQ (50 * 1000000)
31#define PLL_SIMULATION_FREQ (10 * 1000000)
32#define PLL_PROF_CLK_FREQ (38400 * 1000)
33#define PLL_DEFAULT_EPP_VALUE 0x80
34
35#define TIM_SAFE_ENABLE 0xf1d0dead
36#define TIM_WATCHDOG_RESET_VALUE 0xffffffff
37
38#define TIMEOUT_US (150 * USEC_PER_MSEC)
39#define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC)
40#define PLL_TIMEOUT_US (1500 * USEC_PER_MSEC)
41#define IDLE_TIMEOUT_US (5 * USEC_PER_MSEC)
42
43#define ICB_0_IRQ_MASK ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \
44 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \
45 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \
46 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \
47 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \
48 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \
49 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))
50
51#define ICB_1_IRQ_MASK ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \
52 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \
53 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))
54
55#define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK)
56
57#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \
58 (REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR)))
59
60#define BUTTRESS_ALL_IRQ_MASK (BUTTRESS_IRQ_MASK | \
61 (REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE)))
62
63#define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK)
64#define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
65
66#define ITF_FIREWALL_VIOLATION_MASK ((REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \
67 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \
68 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \
69 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \
70 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \
71 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \
72 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))
73
74static void ivpu_hw_wa_init(struct ivpu_device *vdev)
75{
76 vdev->wa.punit_disabled = false;
77 vdev->wa.clear_runtime_mem = false;
78
79 REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, BUTTRESS_ALL_IRQ_MASK);
80 if (REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) == BUTTRESS_ALL_IRQ_MASK) {
81 /* Writing 1s does not clear the interrupt status register */
82 vdev->wa.interrupt_clear_with_0 = true;
83 REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0);
84 }
85
86 IVPU_PRINT_WA(punit_disabled);
87 IVPU_PRINT_WA(clear_runtime_mem);
88 IVPU_PRINT_WA(interrupt_clear_with_0);
89}
90
91static void ivpu_hw_timeouts_init(struct ivpu_device *vdev)
92{
93 vdev->timeout.boot = 1000;
94 vdev->timeout.jsm = 500;
95 vdev->timeout.tdr = 2000;
96 vdev->timeout.reschedule_suspend = 10;
97 vdev->timeout.autosuspend = 10;
98 vdev->timeout.d0i3_entry_msg = 5;
99}
100
101static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev)
102{
103 return REGB_POLL_FLD(VPU_37XX_BUTTRESS_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
104}
105
106/* Send KMD initiated workpoint change */
107static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio,
108 u16 target_ratio, u16 config)
109{
110 int ret;
111 u32 val;
112
113 ret = ivpu_pll_wait_for_cmd_send(vdev);
114 if (ret) {
115 ivpu_err(vdev, "Failed to sync before WP request: %d\n", ret);
116 return ret;
117 }
118
119 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0);
120 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
121 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
122 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, val);
123
124 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1);
125 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
126 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, PLL_DEFAULT_EPP_VALUE, val);
127 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, val);
128
129 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2);
130 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val);
131 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, val);
132
133 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_CMD);
134 val = REG_SET_FLD(VPU_37XX_BUTTRESS_WP_REQ_CMD, SEND, val);
135 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_CMD, val);
136
137 ret = ivpu_pll_wait_for_cmd_send(vdev);
138 if (ret)
139 ivpu_err(vdev, "Failed to sync after WP request: %d\n", ret);
140
141 return ret;
142}
143
144static int ivpu_pll_wait_for_lock(struct ivpu_device *vdev, bool enable)
145{
146 u32 exp_val = enable ? 0x1 : 0x0;
147
148 if (IVPU_WA(punit_disabled))
149 return 0;
150
151 return REGB_POLL_FLD(VPU_37XX_BUTTRESS_PLL_STATUS, LOCK, exp_val, PLL_TIMEOUT_US);
152}
153
154static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev)
155{
156 if (IVPU_WA(punit_disabled))
157 return 0;
158
159 return REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, READY, 1, PLL_TIMEOUT_US);
160}
161
162static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
163{
164 struct ivpu_hw_info *hw = vdev->hw;
165 u8 fuse_min_ratio, fuse_max_ratio, fuse_pn_ratio;
166 u32 fmin_fuse, fmax_fuse;
167
168 fmin_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMIN_FUSE);
169 fuse_min_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMIN_FUSE, MIN_RATIO, fmin_fuse);
170 fuse_pn_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMIN_FUSE, PN_RATIO, fmin_fuse);
171
172 fmax_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMAX_FUSE);
173 fuse_max_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMAX_FUSE, MAX_RATIO, fmax_fuse);
174
175 hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio);
176 hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio);
177 hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
178}
179
180static int ivpu_hw_37xx_wait_for_vpuip_bar(struct ivpu_device *vdev)
181{
182 return REGV_POLL_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, AON, 0, 100);
183}
184
185static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)
186{
187 struct ivpu_hw_info *hw = vdev->hw;
188 u16 target_ratio;
189 u16 config;
190 int ret;
191
192 if (IVPU_WA(punit_disabled)) {
193 ivpu_dbg(vdev, PM, "Skipping PLL request\n");
194 return 0;
195 }
196
197 if (enable) {
198 target_ratio = hw->pll.pn_ratio;
199 config = hw->config;
200 } else {
201 target_ratio = 0;
202 config = 0;
203 }
204
205 ivpu_dbg(vdev, PM, "PLL workpoint request: config 0x%04x pll ratio 0x%x\n",
206 config, target_ratio);
207
208 ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio, target_ratio, config);
209 if (ret) {
210 ivpu_err(vdev, "Failed to send PLL workpoint request: %d\n", ret);
211 return ret;
212 }
213
214 ret = ivpu_pll_wait_for_lock(vdev, enable);
215 if (ret) {
216 ivpu_err(vdev, "Timed out waiting for PLL lock\n");
217 return ret;
218 }
219
220 if (enable) {
221 ret = ivpu_pll_wait_for_status_ready(vdev);
222 if (ret) {
223 ivpu_err(vdev, "Timed out waiting for PLL ready status\n");
224 return ret;
225 }
226
227 ret = ivpu_hw_37xx_wait_for_vpuip_bar(vdev);
228 if (ret) {
229 ivpu_err(vdev, "Timed out waiting for NPU IP bar\n");
230 return ret;
231 }
232 }
233
234 return 0;
235}
236
237static int ivpu_pll_enable(struct ivpu_device *vdev)
238{
239 return ivpu_pll_drive(vdev, true);
240}
241
242static int ivpu_pll_disable(struct ivpu_device *vdev)
243{
244 return ivpu_pll_drive(vdev, false);
245}
246
247static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev)
248{
249 u32 val = 0;
250
251 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val);
252 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val);
253 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val);
254
255 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val);
256}
257
258static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable)
259{
260 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET);
261
262 if (enable) {
263 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val);
264 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val);
265 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val);
266 } else {
267 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val);
268 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val);
269 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val);
270 }
271
272 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val);
273}
274
275static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable)
276{
277 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET);
278
279 if (enable) {
280 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val);
281 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val);
282 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val);
283 } else {
284 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val);
285 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val);
286 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val);
287 }
288
289 REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val);
290}
291
292static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val)
293{
294 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);
295
296 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val))
297 return -EIO;
298
299 return 0;
300}
301
302static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
303{
304 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN);
305
306 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val))
307 return -EIO;
308
309 return 0;
310}
311
312static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
313{
314 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY);
315
316 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val))
317 return -EIO;
318
319 return 0;
320}
321
322static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val)
323{
324 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);
325
326 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) ||
327 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val))
328 return -EIO;
329
330 return 0;
331}
332
333static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
334{
335 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN);
336
337 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
338 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
339 return -EIO;
340
341 return 0;
342}
343
344static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
345{
346 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY);
347
348 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
349 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
350 return -EIO;
351
352 return 0;
353}
354
355static int ivpu_boot_host_ss_configure(struct ivpu_device *vdev)
356{
357 ivpu_boot_host_ss_rst_clr_assert(vdev);
358
359 return ivpu_boot_noc_qreqn_check(vdev, 0x0);
360}
361
362static void ivpu_boot_vpu_idle_gen_disable(struct ivpu_device *vdev)
363{
364 REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, 0x0);
365}
366
367static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable)
368{
369 int ret;
370 u32 val;
371
372 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);
373 if (enable)
374 val = REG_SET_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
375 else
376 val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
377 REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val);
378
379 ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
380 if (ret) {
381 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
382 return ret;
383 }
384
385 ret = ivpu_boot_noc_qdeny_check(vdev, 0x0);
386 if (ret)
387 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
388
389 return ret;
390}
391
392static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev)
393{
394 return ivpu_boot_host_ss_axi_drive(vdev, true);
395}
396
397static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable)
398{
399 int ret;
400 u32 val;
401
402 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);
403 if (enable) {
404 val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
405 val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
406 } else {
407 val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
408 val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
409 }
410 REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val);
411
412 ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
413 if (ret) {
414 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
415 return ret;
416 }
417
418 ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0);
419 if (ret)
420 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
421
422 return ret;
423}
424
425static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev)
426{
427 return ivpu_boot_host_ss_top_noc_drive(vdev, true);
428}
429
430static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable)
431{
432 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
433
434 if (enable)
435 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val);
436 else
437 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val);
438
439 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
440}
441
442static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable)
443{
444 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0);
445
446 if (enable)
447 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
448 else
449 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
450
451 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
452}
453
454static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val)
455{
456 return REGV_POLL_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0, MSS_CPU,
457 exp_val, PWR_ISLAND_STATUS_TIMEOUT_US);
458}
459
460static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable)
461{
462 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0);
463
464 if (enable)
465 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val);
466 else
467 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val);
468
469 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val);
470}
471
472static void ivpu_boot_dpu_active_drive(struct ivpu_device *vdev, bool enable)
473{
474 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE);
475
476 if (enable)
477 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val);
478 else
479 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val);
480
481 REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val);
482}
483
484static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev)
485{
486 int ret;
487
488 ivpu_boot_pwr_island_trickle_drive(vdev, true);
489 ivpu_boot_pwr_island_drive(vdev, true);
490
491 ret = ivpu_boot_wait_for_pwr_island_status(vdev, 0x1);
492 if (ret) {
493 ivpu_err(vdev, "Timed out waiting for power island status\n");
494 return ret;
495 }
496
497 ret = ivpu_boot_top_noc_qrenqn_check(vdev, 0x0);
498 if (ret) {
499 ivpu_err(vdev, "Failed qrenqn check %d\n", ret);
500 return ret;
501 }
502
503 ivpu_boot_host_ss_clk_drive(vdev, true);
504 ivpu_boot_pwr_island_isolation_drive(vdev, false);
505 ivpu_boot_host_ss_rst_drive(vdev, true);
506 ivpu_boot_dpu_active_drive(vdev, true);
507
508 return ret;
509}
510
511static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
512{
513 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);
514
515 val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val);
516 val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val);
517 val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val);
518
519 REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val);
520}
521
522static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev)
523{
524 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV);
525
526 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);
527 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);
528 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);
529 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);
530
531 REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val);
532}
533
534static void ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev)
535{
536 u32 val;
537
538 val = REGV_RD32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC);
539 val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTRUN0, val);
540
541 val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val);
542 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
543
544 val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val);
545 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
546
547 val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val);
548 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
549
550 val = vdev->fw->entry_point >> 9;
551 REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);
552
553 val = REG_SET_FLD(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, DONE, val);
554 REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);
555
556 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
557 vdev->fw->entry_point == vdev->fw->cold_boot_entry_point ? "cold boot" : "resume");
558}
559
560static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable)
561{
562 int ret;
563 u32 val;
564
565 ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
566 if (ret) {
567 ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
568 return ret;
569 }
570
571 val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL);
572 if (enable)
573 val = REG_SET_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, I3, val);
574 else
575 val = REG_CLR_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, I3, val);
576 REGB_WR32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, val);
577
578 ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
579 if (ret)
580 ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
581
582 return ret;
583}
584
585static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev)
586{
587 struct ivpu_hw_info *hw = vdev->hw;
588
589 hw->tile_fuse = TILE_FUSE_ENABLE_BOTH;
590 hw->sku = TILE_SKU_BOTH;
591 hw->config = WP_CONFIG_2_TILE_4_3_RATIO;
592
593 ivpu_pll_init_frequency_ratios(vdev);
594
595 ivpu_hw_init_range(&hw->ranges.global, 0x80000000, SZ_512M);
596 ivpu_hw_init_range(&hw->ranges.user, 0xc0000000, 255 * SZ_1M);
597 ivpu_hw_init_range(&hw->ranges.shave, 0x180000000, SZ_2G);
598 ivpu_hw_init_range(&hw->ranges.dma, 0x200000000, SZ_8G);
599
600 vdev->platform = IVPU_PLATFORM_SILICON;
601 ivpu_hw_wa_init(vdev);
602 ivpu_hw_timeouts_init(vdev);
603
604 return 0;
605}
606
607static int ivpu_hw_37xx_ip_reset(struct ivpu_device *vdev)
608{
609 int ret;
610 u32 val;
611
612 if (IVPU_WA(punit_disabled))
613 return 0;
614
615 ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US);
616 if (ret) {
617 ivpu_err(vdev, "Timed out waiting for TRIGGER bit\n");
618 return ret;
619 }
620
621 val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_IP_RESET);
622 val = REG_SET_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, val);
623 REGB_WR32(VPU_37XX_BUTTRESS_VPU_IP_RESET, val);
624
625 ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US);
626 if (ret)
627 ivpu_err(vdev, "Timed out waiting for RESET completion\n");
628
629 return ret;
630}
631
632static int ivpu_hw_37xx_reset(struct ivpu_device *vdev)
633{
634 int ret = 0;
635
636 if (ivpu_hw_37xx_ip_reset(vdev)) {
637 ivpu_err(vdev, "Failed to reset NPU\n");
638 ret = -EIO;
639 }
640
641 if (ivpu_pll_disable(vdev)) {
642 ivpu_err(vdev, "Failed to disable PLL\n");
643 ret = -EIO;
644 }
645
646 return ret;
647}
648
649static int ivpu_hw_37xx_d0i3_enable(struct ivpu_device *vdev)
650{
651 int ret;
652
653 ret = ivpu_boot_d0i3_drive(vdev, true);
654 if (ret)
655 ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);
656
657 udelay(5); /* VPU requires 5 us to complete the transition */
658
659 return ret;
660}
661
662static int ivpu_hw_37xx_d0i3_disable(struct ivpu_device *vdev)
663{
664 int ret;
665
666 ret = ivpu_boot_d0i3_drive(vdev, false);
667 if (ret)
668 ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);
669
670 return ret;
671}
672
673static int ivpu_hw_37xx_power_up(struct ivpu_device *vdev)
674{
675 int ret;
676
677 /* PLL requests may fail when powering down, so issue WP 0 here */
678 ret = ivpu_pll_disable(vdev);
679 if (ret)
680 ivpu_warn(vdev, "Failed to disable PLL: %d\n", ret);
681
682 ret = ivpu_hw_37xx_d0i3_disable(vdev);
683 if (ret)
684 ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret);
685
686 ret = ivpu_pll_enable(vdev);
687 if (ret) {
688 ivpu_err(vdev, "Failed to enable PLL: %d\n", ret);
689 return ret;
690 }
691
692 ret = ivpu_boot_host_ss_configure(vdev);
693 if (ret) {
694 ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
695 return ret;
696 }
697
698 /*
699 * The control circuitry for vpu_idle indication logic powers up active.
700 * To ensure unnecessary low power mode signal from LRT during bring up,
701 * KMD disables the circuitry prior to bringing up the Main Power island.
702 */
703 ivpu_boot_vpu_idle_gen_disable(vdev);
704
705 ret = ivpu_boot_pwr_domain_enable(vdev);
706 if (ret) {
707 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
708 return ret;
709 }
710
711 ret = ivpu_boot_host_ss_axi_enable(vdev);
712 if (ret) {
713 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
714 return ret;
715 }
716
717 ret = ivpu_boot_host_ss_top_noc_enable(vdev);
718 if (ret)
719 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);
720
721 return ret;
722}
723
724static int ivpu_hw_37xx_boot_fw(struct ivpu_device *vdev)
725{
726 ivpu_boot_no_snoop_enable(vdev);
727 ivpu_boot_tbu_mmu_enable(vdev);
728 ivpu_boot_soc_cpu_boot(vdev);
729
730 return 0;
731}
732
733static bool ivpu_hw_37xx_is_idle(struct ivpu_device *vdev)
734{
735 u32 val;
736
737 if (IVPU_WA(punit_disabled))
738 return true;
739
740 val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_STATUS);
741 return REG_TEST_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, READY, val) &&
742 REG_TEST_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, IDLE, val);
743}
744
745static int ivpu_hw_37xx_wait_for_idle(struct ivpu_device *vdev)
746{
747 return REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
748}
749
750static void ivpu_hw_37xx_save_d0i3_entry_timestamp(struct ivpu_device *vdev)
751{
752 vdev->hw->d0i3_entry_host_ts = ktime_get_boottime();
753 vdev->hw->d0i3_entry_vpu_ts = REGV_RD64(VPU_37XX_CPU_SS_TIM_PERF_FREE_CNT);
754}
755
756static int ivpu_hw_37xx_power_down(struct ivpu_device *vdev)
757{
758 int ret = 0;
759
760 ivpu_hw_37xx_save_d0i3_entry_timestamp(vdev);
761
762 if (!ivpu_hw_37xx_is_idle(vdev))
763 ivpu_warn(vdev, "NPU not idle during power down\n");
764
765 if (ivpu_hw_37xx_reset(vdev)) {
766 ivpu_err(vdev, "Failed to reset NPU\n");
767 ret = -EIO;
768 }
769
770 if (ivpu_hw_37xx_d0i3_enable(vdev)) {
771 ivpu_err(vdev, "Failed to enter D0I3\n");
772 ret = -EIO;
773 }
774
775 return ret;
776}
777
778static void ivpu_hw_37xx_wdt_disable(struct ivpu_device *vdev)
779{
780 u32 val;
781
782 /* Enable writing and set non-zero WDT value */
783 REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
784 REGV_WR32(VPU_37XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);
785
786 /* Enable writing and disable watchdog timer */
787 REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
788 REGV_WR32(VPU_37XX_CPU_SS_TIM_WDOG_EN, 0);
789
790 /* Now clear the timeout interrupt */
791 val = REGV_RD32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG);
792 val = REG_CLR_FLD(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);
793 REGV_WR32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, val);
794}
795
796static u32 ivpu_hw_37xx_profiling_freq_get(struct ivpu_device *vdev)
797{
798 return PLL_PROF_CLK_FREQ;
799}
800
801static void ivpu_hw_37xx_profiling_freq_drive(struct ivpu_device *vdev, bool enable)
802{
803 /* Profiling freq - is a debug feature. Unavailable on VPU 37XX. */
804}
805
806static u32 ivpu_hw_37xx_ratio_to_freq(struct ivpu_device *vdev, u32 ratio)
807{
808 u32 pll_clock = PLL_REF_CLK_FREQ * ratio;
809 u32 cpu_clock;
810
811 if ((vdev->hw->config & 0xff) == PLL_RATIO_4_3)
812 cpu_clock = pll_clock * 2 / 4;
813 else
814 cpu_clock = pll_clock * 2 / 5;
815
816 return cpu_clock;
817}
818
819/* Register indirect accesses */
820static u32 ivpu_hw_37xx_reg_pll_freq_get(struct ivpu_device *vdev)
821{
822 u32 pll_curr_ratio;
823
824 pll_curr_ratio = REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL);
825 pll_curr_ratio &= VPU_37XX_BUTTRESS_CURRENT_PLL_RATIO_MASK;
826
827 if (!ivpu_is_silicon(vdev))
828 return PLL_SIMULATION_FREQ;
829
830 return ivpu_hw_37xx_ratio_to_freq(vdev, pll_curr_ratio);
831}
832
833static u32 ivpu_hw_37xx_reg_telemetry_offset_get(struct ivpu_device *vdev)
834{
835 return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_OFFSET);
836}
837
838static u32 ivpu_hw_37xx_reg_telemetry_size_get(struct ivpu_device *vdev)
839{
840 return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_SIZE);
841}
842
843static u32 ivpu_hw_37xx_reg_telemetry_enable_get(struct ivpu_device *vdev)
844{
845 return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_ENABLE);
846}
847
848static void ivpu_hw_37xx_reg_db_set(struct ivpu_device *vdev, u32 db_id)
849{
850 u32 reg_stride = VPU_37XX_CPU_SS_DOORBELL_1 - VPU_37XX_CPU_SS_DOORBELL_0;
851 u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET);
852
853 REGV_WR32I(VPU_37XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val);
854}
855
856static u32 ivpu_hw_37xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev)
857{
858 return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM);
859}
860
861static u32 ivpu_hw_37xx_reg_ipc_rx_count_get(struct ivpu_device *vdev)
862{
863 u32 count = REGV_RD32_SILENT(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT);
864
865 return REG_GET_FLD(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count);
866}
867
868static void ivpu_hw_37xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
869{
870 REGV_WR32(VPU_37XX_CPU_SS_TIM_IPC_FIFO, vpu_addr);
871}
872
873static void ivpu_hw_37xx_irq_clear(struct ivpu_device *vdev)
874{
875 REGV_WR64(VPU_37XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK);
876}
877
878static void ivpu_hw_37xx_irq_enable(struct ivpu_device *vdev)
879{
880 REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK);
881 REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK);
882 REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK);
883 REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
884}
885
886static void ivpu_hw_37xx_irq_disable(struct ivpu_device *vdev)
887{
888 REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
889 REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK);
890 REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull);
891 REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0);
892}
893
894static void ivpu_hw_37xx_irq_wdt_nce_handler(struct ivpu_device *vdev)
895{
896 ivpu_pm_trigger_recovery(vdev, "WDT NCE IRQ");
897}
898
899static void ivpu_hw_37xx_irq_wdt_mss_handler(struct ivpu_device *vdev)
900{
901 ivpu_hw_wdt_disable(vdev);
902 ivpu_pm_trigger_recovery(vdev, "WDT MSS IRQ");
903}
904
905static void ivpu_hw_37xx_irq_noc_firewall_handler(struct ivpu_device *vdev)
906{
907 ivpu_pm_trigger_recovery(vdev, "NOC Firewall IRQ");
908}
909
910/* Handler for IRQs from VPU core (irqV) */
911static bool ivpu_hw_37xx_irqv_handler(struct ivpu_device *vdev, int irq, bool *wake_thread)
912{
913 u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
914
915 if (!status)
916 return false;
917
918 REGV_WR32(VPU_37XX_HOST_SS_ICB_CLEAR_0, status);
919
920 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status))
921 ivpu_mmu_irq_evtq_handler(vdev);
922
923 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status))
924 ivpu_ipc_irq_handler(vdev, wake_thread);
925
926 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status))
927 ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
928
929 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status))
930 ivpu_mmu_irq_gerr_handler(vdev);
931
932 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status))
933 ivpu_hw_37xx_irq_wdt_mss_handler(vdev);
934
935 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status))
936 ivpu_hw_37xx_irq_wdt_nce_handler(vdev);
937
938 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status))
939 ivpu_hw_37xx_irq_noc_firewall_handler(vdev);
940
941 return true;
942}
943
944/* Handler for IRQs from Buttress core (irqB) */
945static bool ivpu_hw_37xx_irqb_handler(struct ivpu_device *vdev, int irq)
946{
947 u32 status = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
948 bool schedule_recovery = false;
949
950 if (!status)
951 return false;
952
953 if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status))
954 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x",
955 REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL));
956
957 if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, status)) {
958 ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0));
959 REGB_WR32(VPU_37XX_BUTTRESS_ATS_ERR_CLEAR, 0x1);
960 schedule_recovery = true;
961 }
962
963 if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR, status)) {
964 u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG);
965
966 ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
967 ufi_log, REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, OPCODE, ufi_log),
968 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, AXI_ID, ufi_log),
969 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, CQ_ID, ufi_log));
970 REGB_WR32(VPU_37XX_BUTTRESS_UFI_ERR_CLEAR, 0x1);
971 schedule_recovery = true;
972 }
973
974 /* This must be done after interrupts are cleared at the source. */
975 if (IVPU_WA(interrupt_clear_with_0))
976 /*
977 * Writing 1 triggers an interrupt, so we can't perform read update write.
978 * Clear local interrupt status by writing 0 to all bits.
979 */
980 REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0);
981 else
982 REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, status);
983
984 if (schedule_recovery)
985 ivpu_pm_trigger_recovery(vdev, "Buttress IRQ");
986
987 return true;
988}
989
990static irqreturn_t ivpu_hw_37xx_irq_handler(int irq, void *ptr)
991{
992 struct ivpu_device *vdev = ptr;
993 bool irqv_handled, irqb_handled, wake_thread = false;
994
995 REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
996
997 irqv_handled = ivpu_hw_37xx_irqv_handler(vdev, irq, &wake_thread);
998 irqb_handled = ivpu_hw_37xx_irqb_handler(vdev, irq);
999
1000 /* Re-enable global interrupts to re-trigger MSI for pending interrupts */
1001 REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
1002
1003 if (wake_thread)
1004 return IRQ_WAKE_THREAD;
1005 if (irqv_handled || irqb_handled)
1006 return IRQ_HANDLED;
1007 return IRQ_NONE;
1008}
1009
1010static void ivpu_hw_37xx_diagnose_failure(struct ivpu_device *vdev)
1011{
1012 u32 irqv = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
1013 u32 irqb = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
1014
1015 if (ivpu_hw_37xx_reg_ipc_rx_count_get(vdev))
1016 ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
1017
1018 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, irqv))
1019 ivpu_err(vdev, "WDT MSS timeout detected\n");
1020
1021 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, irqv))
1022 ivpu_err(vdev, "WDT NCE timeout detected\n");
1023
1024 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, irqv))
1025 ivpu_err(vdev, "NOC Firewall irq detected\n");
1026
1027 if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, irqb))
1028 ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0));
1029
1030 if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR, irqb)) {
1031 u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG);
1032
1033 ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
1034 ufi_log, REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, OPCODE, ufi_log),
1035 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, AXI_ID, ufi_log),
1036 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, CQ_ID, ufi_log));
1037 }
1038}
1039
1040const struct ivpu_hw_ops ivpu_hw_37xx_ops = {
1041 .info_init = ivpu_hw_37xx_info_init,
1042 .power_up = ivpu_hw_37xx_power_up,
1043 .is_idle = ivpu_hw_37xx_is_idle,
1044 .wait_for_idle = ivpu_hw_37xx_wait_for_idle,
1045 .power_down = ivpu_hw_37xx_power_down,
1046 .reset = ivpu_hw_37xx_reset,
1047 .boot_fw = ivpu_hw_37xx_boot_fw,
1048 .wdt_disable = ivpu_hw_37xx_wdt_disable,
1049 .diagnose_failure = ivpu_hw_37xx_diagnose_failure,
1050 .profiling_freq_get = ivpu_hw_37xx_profiling_freq_get,
1051 .profiling_freq_drive = ivpu_hw_37xx_profiling_freq_drive,
1052 .reg_pll_freq_get = ivpu_hw_37xx_reg_pll_freq_get,
1053 .ratio_to_freq = ivpu_hw_37xx_ratio_to_freq,
1054 .reg_telemetry_offset_get = ivpu_hw_37xx_reg_telemetry_offset_get,
1055 .reg_telemetry_size_get = ivpu_hw_37xx_reg_telemetry_size_get,
1056 .reg_telemetry_enable_get = ivpu_hw_37xx_reg_telemetry_enable_get,
1057 .reg_db_set = ivpu_hw_37xx_reg_db_set,
1058 .reg_ipc_rx_addr_get = ivpu_hw_37xx_reg_ipc_rx_addr_get,
1059 .reg_ipc_rx_count_get = ivpu_hw_37xx_reg_ipc_rx_count_get,
1060 .reg_ipc_tx_set = ivpu_hw_37xx_reg_ipc_tx_set,
1061 .irq_clear = ivpu_hw_37xx_irq_clear,
1062 .irq_enable = ivpu_hw_37xx_irq_enable,
1063 .irq_disable = ivpu_hw_37xx_irq_disable,
1064 .irq_handler = ivpu_hw_37xx_irq_handler,
1065};
drivers/accel/ivpu/ivpu_hw_37xx_reg.h+0−72
@@ -8,78 +8,6 @@ · 7 unmodified lines
8 8
9#include <linux/bits.h>9#include <linux/bits.h>
10 10
11#define VPU_37XX_BUTTRESS_INTERRUPT_TYPE 0x00000000u
12
13#define VPU_37XX_BUTTRESS_INTERRUPT_STAT 0x00000004u
14#define VPU_37XX_BUTTRESS_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
15#define VPU_37XX_BUTTRESS_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
16#define VPU_37XX_BUTTRESS_INTERRUPT_STAT_UFI_ERR_MASK BIT_MASK(2)
17
18#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0 0x00000008u
19#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
20#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
21
22#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1 0x0000000cu
23#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
24#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
25
26#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2 0x00000010u
27#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
28
29#define VPU_37XX_BUTTRESS_WP_REQ_CMD 0x00000014u
30#define VPU_37XX_BUTTRESS_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
31
32#define VPU_37XX_BUTTRESS_WP_DOWNLOAD 0x00000018u
33#define VPU_37XX_BUTTRESS_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0)
34
35#define VPU_37XX_BUTTRESS_CURRENT_PLL 0x0000001cu
36#define VPU_37XX_BUTTRESS_CURRENT_PLL_RATIO_MASK GENMASK(15, 0)
37
38#define VPU_37XX_BUTTRESS_PLL_ENABLE 0x00000020u
39
40#define VPU_37XX_BUTTRESS_FMIN_FUSE 0x00000024u
41#define VPU_37XX_BUTTRESS_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
42#define VPU_37XX_BUTTRESS_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
43
44#define VPU_37XX_BUTTRESS_FMAX_FUSE 0x00000028u
45#define VPU_37XX_BUTTRESS_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
46
47#define VPU_37XX_BUTTRESS_TILE_FUSE 0x0000002cu
48#define VPU_37XX_BUTTRESS_TILE_FUSE_VALID_MASK BIT_MASK(0)
49#define VPU_37XX_BUTTRESS_TILE_FUSE_SKU_MASK GENMASK(3, 2)
50
51#define VPU_37XX_BUTTRESS_LOCAL_INT_MASK 0x00000030u
52#define VPU_37XX_BUTTRESS_GLOBAL_INT_MASK 0x00000034u
53
54#define VPU_37XX_BUTTRESS_PLL_STATUS 0x00000040u
55#define VPU_37XX_BUTTRESS_PLL_STATUS_LOCK_MASK BIT_MASK(1)
56
57#define VPU_37XX_BUTTRESS_VPU_STATUS 0x00000044u
58#define VPU_37XX_BUTTRESS_VPU_STATUS_READY_MASK BIT_MASK(0)
59#define VPU_37XX_BUTTRESS_VPU_STATUS_IDLE_MASK BIT_MASK(1)
60
61#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL 0x00000060u
62#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
63#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL_I3_MASK BIT_MASK(2)
64
65#define VPU_37XX_BUTTRESS_VPU_IP_RESET 0x00000050u
66#define VPU_37XX_BUTTRESS_VPU_IP_RESET_TRIGGER_MASK BIT_MASK(0)
67
68#define VPU_37XX_BUTTRESS_VPU_TELEMETRY_OFFSET 0x00000080u
69#define VPU_37XX_BUTTRESS_VPU_TELEMETRY_SIZE 0x00000084u
70#define VPU_37XX_BUTTRESS_VPU_TELEMETRY_ENABLE 0x00000088u
71
72#define VPU_37XX_BUTTRESS_ATS_ERR_LOG_0 0x000000a0u
73#define VPU_37XX_BUTTRESS_ATS_ERR_LOG_1 0x000000a4u
74#define VPU_37XX_BUTTRESS_ATS_ERR_CLEAR 0x000000a8u
75
76#define VPU_37XX_BUTTRESS_UFI_ERR_LOG 0x000000b0u
77#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0)
78#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12)
79#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20)
80
81#define VPU_37XX_BUTTRESS_UFI_ERR_CLEAR 0x000000b4u
82
83#define VPU_37XX_HOST_SS_CPR_CLK_SET 0x00000084u11#define VPU_37XX_HOST_SS_CPR_CLK_SET 0x00000084u
84#define VPU_37XX_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK BIT_MASK(1)12#define VPU_37XX_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK BIT_MASK(1)
85#define VPU_37XX_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK BIT_MASK(10)13#define VPU_37XX_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK BIT_MASK(10)
drivers/accel/ivpu/ivpu_hw_40xx.c+0−1250
@@ -1,1250 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020-2023 Intel Corporation
4 */
5
6#include "ivpu_drv.h"
7#include "ivpu_fw.h"
8#include "ivpu_hw.h"
9#include "ivpu_hw_40xx_reg.h"
10#include "ivpu_hw_reg_io.h"
11#include "ivpu_ipc.h"
12#include "ivpu_mmu.h"
13#include "ivpu_pm.h"
14
15#include <linux/dmi.h>
16
17#define TILE_MAX_NUM 6
18#define TILE_MAX_MASK 0x3f
19
20#define LNL_HW_ID 0x4040
21
22#define SKU_TILE_SHIFT 0u
23#define SKU_TILE_MASK 0x0000ffffu
24#define SKU_HW_ID_SHIFT 16u
25#define SKU_HW_ID_MASK 0xffff0000u
26
27#define PLL_CONFIG_DEFAULT 0x0
28#define PLL_CDYN_DEFAULT 0x80
29#define PLL_EPP_DEFAULT 0x80
30#define PLL_REF_CLK_FREQ (50 * 1000000)
31#define PLL_RATIO_TO_FREQ(x) ((x) * PLL_REF_CLK_FREQ)
32
33#define PLL_PROFILING_FREQ_DEFAULT 38400000
34#define PLL_PROFILING_FREQ_HIGH 400000000
35
36#define TIM_SAFE_ENABLE 0xf1d0dead
37#define TIM_WATCHDOG_RESET_VALUE 0xffffffff
38
39#define TIMEOUT_US (150 * USEC_PER_MSEC)
40#define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC)
41#define PLL_TIMEOUT_US (1500 * USEC_PER_MSEC)
42#define IDLE_TIMEOUT_US (5 * USEC_PER_MSEC)
43
44#define WEIGHTS_DEFAULT 0xf711f711u
45#define WEIGHTS_ATS_DEFAULT 0x0000f711u
46
47#define ICB_0_IRQ_MASK ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \
48 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \
49 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \
50 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \
51 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \
52 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \
53 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))
54
55#define ICB_1_IRQ_MASK ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \
56 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \
57 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))
58
59#define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK)
60
61#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \
62 (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR)) | \
63 (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR)) | \
64 (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR)) | \
65 (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR)) | \
66 (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR)))
67
68#define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK)
69#define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
70
71#define ITF_FIREWALL_VIOLATION_MASK ((REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \
72 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \
73 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \
74 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \
75 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \
76 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \
77 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))
78
79static char *ivpu_platform_to_str(u32 platform)
80{
81 switch (platform) {
82 case IVPU_PLATFORM_SILICON:
83 return "SILICON";
84 case IVPU_PLATFORM_SIMICS:
85 return "SIMICS";
86 case IVPU_PLATFORM_FPGA:
87 return "FPGA";
88 default:
89 return "Invalid platform";
90 }
91}
92
93static const struct dmi_system_id ivpu_dmi_platform_simulation[] = {
94 {
95 .ident = "Intel Simics",
96 .matches = {
97 DMI_MATCH(DMI_BOARD_NAME, "lnlrvp"),
98 DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
99 DMI_MATCH(DMI_BOARD_SERIAL, "123456789"),
100 },
101 },
102 {
103 .ident = "Intel Simics",
104 .matches = {
105 DMI_MATCH(DMI_BOARD_NAME, "Simics"),
106 },
107 },
108 { }
109};
110
111static void ivpu_hw_read_platform(struct ivpu_device *vdev)
112{
113 if (dmi_check_system(ivpu_dmi_platform_simulation))
114 vdev->platform = IVPU_PLATFORM_SIMICS;
115 else
116 vdev->platform = IVPU_PLATFORM_SILICON;
117
118 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n",
119 ivpu_platform_to_str(vdev->platform), vdev->platform);
120}
121
122static void ivpu_hw_wa_init(struct ivpu_device *vdev)
123{
124 vdev->wa.punit_disabled = ivpu_is_fpga(vdev);
125 vdev->wa.clear_runtime_mem = false;
126
127 if (ivpu_hw_gen(vdev) == IVPU_HW_40XX)
128 vdev->wa.disable_clock_relinquish = true;
129
130 IVPU_PRINT_WA(punit_disabled);
131 IVPU_PRINT_WA(clear_runtime_mem);
132 IVPU_PRINT_WA(disable_clock_relinquish);
133}
134
135static void ivpu_hw_timeouts_init(struct ivpu_device *vdev)
136{
137 if (ivpu_is_fpga(vdev)) {
138 vdev->timeout.boot = 100000;
139 vdev->timeout.jsm = 50000;
140 vdev->timeout.tdr = 2000000;
141 vdev->timeout.reschedule_suspend = 1000;
142 vdev->timeout.autosuspend = -1;
143 vdev->timeout.d0i3_entry_msg = 500;
144 } else if (ivpu_is_simics(vdev)) {
145 vdev->timeout.boot = 50;
146 vdev->timeout.jsm = 500;
147 vdev->timeout.tdr = 10000;
148 vdev->timeout.reschedule_suspend = 10;
149 vdev->timeout.autosuspend = -1;
150 vdev->timeout.d0i3_entry_msg = 100;
151 } else {
152 vdev->timeout.boot = 1000;
153 vdev->timeout.jsm = 500;
154 vdev->timeout.tdr = 2000;
155 vdev->timeout.reschedule_suspend = 10;
156 vdev->timeout.autosuspend = 10;
157 vdev->timeout.d0i3_entry_msg = 5;
158 }
159}
160
161static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev)
162{
163 return REGB_POLL_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
164}
165
166static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio,
167 u16 target_ratio, u16 epp, u16 config, u16 cdyn)
168{
169 int ret;
170 u32 val;
171
172 ret = ivpu_pll_wait_for_cmd_send(vdev);
173 if (ret) {
174 ivpu_err(vdev, "Failed to sync before WP request: %d\n", ret);
175 return ret;
176 }
177
178 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0);
179 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
180 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
181 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val);
182
183 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1);
184 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
185 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, epp, val);
186 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, val);
187
188 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2);
189 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val);
190 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CDYN, cdyn, val);
191 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, val);
192
193 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_CMD);
194 val = REG_SET_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, val);
195 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_CMD, val);
196
197 ret = ivpu_pll_wait_for_cmd_send(vdev);
198 if (ret)
199 ivpu_err(vdev, "Failed to sync after WP request: %d\n", ret);
200
201 return ret;
202}
203
204static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev)
205{
206 return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, 1, PLL_TIMEOUT_US);
207}
208
209static int ivpu_wait_for_clock_own_resource_ack(struct ivpu_device *vdev)
210{
211 if (ivpu_is_simics(vdev))
212 return 0;
213
214 return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, CLOCK_RESOURCE_OWN_ACK, 1, TIMEOUT_US);
215}
216
217static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
218{
219 struct ivpu_hw_info *hw = vdev->hw;
220 u8 fuse_min_ratio, fuse_pn_ratio, fuse_max_ratio;
221 u32 fmin_fuse, fmax_fuse;
222
223 fmin_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMIN_FUSE);
224 fuse_min_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMIN_FUSE, MIN_RATIO, fmin_fuse);
225 fuse_pn_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMIN_FUSE, PN_RATIO, fmin_fuse);
226
227 fmax_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMAX_FUSE);
228 fuse_max_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMAX_FUSE, MAX_RATIO, fmax_fuse);
229
230 hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio);
231 hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio);
232 hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
233}
234
235static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)
236{
237 u16 config = enable ? PLL_CONFIG_DEFAULT : 0;
238 u16 cdyn = enable ? PLL_CDYN_DEFAULT : 0;
239 u16 epp = enable ? PLL_EPP_DEFAULT : 0;
240 struct ivpu_hw_info *hw = vdev->hw;
241 u16 target_ratio = hw->pll.pn_ratio;
242 int ret;
243
244 ivpu_dbg(vdev, PM, "PLL workpoint request: %u Hz, epp: 0x%x, config: 0x%x, cdyn: 0x%x\n",
245 PLL_RATIO_TO_FREQ(target_ratio), epp, config, cdyn);
246
247 ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio,
248 target_ratio, epp, config, cdyn);
249 if (ret) {
250 ivpu_err(vdev, "Failed to send PLL workpoint request: %d\n", ret);
251 return ret;
252 }
253
254 if (enable) {
255 ret = ivpu_pll_wait_for_status_ready(vdev);
256 if (ret) {
257 ivpu_err(vdev, "Timed out waiting for PLL ready status\n");
258 return ret;
259 }
260 }
261
262 return 0;
263}
264
265static int ivpu_pll_enable(struct ivpu_device *vdev)
266{
267 return ivpu_pll_drive(vdev, true);
268}
269
270static int ivpu_pll_disable(struct ivpu_device *vdev)
271{
272 return ivpu_pll_drive(vdev, false);
273}
274
275static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable)
276{
277 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN);
278
279 if (enable) {
280 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
281 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
282 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
283 } else {
284 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
285 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
286 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
287 }
288
289 REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val);
290}
291
292static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable)
293{
294 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN);
295
296 if (enable) {
297 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
298 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
299 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
300 } else {
301 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
302 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
303 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
304 }
305
306 REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val);
307}
308
309static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val)
310{
311 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
312
313 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val))
314 return -EIO;
315
316 return 0;
317}
318
319static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
320{
321 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN);
322
323 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val))
324 return -EIO;
325
326 return 0;
327}
328
329static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
330{
331 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY);
332
333 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val))
334 return -EIO;
335
336 return 0;
337}
338
339static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val)
340{
341 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
342
343 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) ||
344 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val))
345 return -EIO;
346
347 return 0;
348}
349
350static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
351{
352 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN);
353
354 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
355 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
356 return -EIO;
357
358 return 0;
359}
360
361static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
362{
363 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY);
364
365 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
366 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
367 return -EIO;
368
369 return 0;
370}
371
372static void ivpu_boot_idle_gen_drive(struct ivpu_device *vdev, bool enable)
373{
374 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN);
375
376 if (enable)
377 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
378 else
379 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
380
381 REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val);
382}
383
384static int ivpu_boot_host_ss_check(struct ivpu_device *vdev)
385{
386 int ret;
387
388 ret = ivpu_boot_noc_qreqn_check(vdev, 0x0);
389 if (ret) {
390 ivpu_err(vdev, "Failed qreqn check: %d\n", ret);
391 return ret;
392 }
393
394 ret = ivpu_boot_noc_qacceptn_check(vdev, 0x0);
395 if (ret) {
396 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
397 return ret;
398 }
399
400 ret = ivpu_boot_noc_qdeny_check(vdev, 0x0);
401 if (ret)
402 ivpu_err(vdev, "Failed qdeny check %d\n", ret);
403
404 return ret;
405}
406
407static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable)
408{
409 int ret;
410 u32 val;
411
412 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
413 if (enable)
414 val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
415 else
416 val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
417 REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val);
418
419 ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
420 if (ret) {
421 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
422 return ret;
423 }
424
425 ret = ivpu_boot_noc_qdeny_check(vdev, 0x0);
426 if (ret) {
427 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
428 return ret;
429 }
430
431 if (enable) {
432 REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT);
433 REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT);
434 }
435
436 return ret;
437}
438
439static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev)
440{
441 return ivpu_boot_host_ss_axi_drive(vdev, true);
442}
443
444static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable)
445{
446 int ret;
447 u32 val;
448
449 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
450 if (enable) {
451 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
452 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
453 } else {
454 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
455 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
456 }
457 REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val);
458
459 ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
460 if (ret) {
461 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
462 return ret;
463 }
464
465 ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0);
466 if (ret)
467 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
468
469 return ret;
470}
471
472static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev)
473{
474 return ivpu_boot_host_ss_top_noc_drive(vdev, true);
475}
476
477static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable)
478{
479 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
480
481 if (enable)
482 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
483 else
484 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
485
486 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
487
488 if (enable)
489 ndelay(500);
490}
491
492static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable)
493{
494 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
495
496 if (enable)
497 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
498 else
499 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
500
501 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
502
503 if (!enable)
504 ndelay(500);
505}
506
507static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val)
508{
509 if (ivpu_is_fpga(vdev))
510 return 0;
511
512 return REGV_POLL_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0, CSS_CPU,
513 exp_val, PWR_ISLAND_STATUS_TIMEOUT_US);
514}
515
516static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable)
517{
518 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0);
519
520 if (enable)
521 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
522 else
523 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
524
525 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val);
526}
527
528static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
529{
530 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);
531
532 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val);
533 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);
534 val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);
535
536 REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val);
537}
538
539static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev)
540{
541 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV);
542
543 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);
544 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);
545 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val);
546 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val);
547 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);
548 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);
549
550 REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val);
551}
552
553static int ivpu_boot_cpu_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
554{
555 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN);
556
557 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN, TOP_MMIO, exp_val, val))
558 return -EIO;
559
560 return 0;
561}
562
563static int ivpu_boot_cpu_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
564{
565 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY);
566
567 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QDENY, TOP_MMIO, exp_val, val))
568 return -EIO;
569
570 return 0;
571}
572
573static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev)
574{
575 int ret;
576
577 ret = ivpu_wait_for_clock_own_resource_ack(vdev);
578 if (ret) {
579 ivpu_err(vdev, "Timed out waiting for clock own resource ACK\n");
580 return ret;
581 }
582
583 ivpu_boot_pwr_island_trickle_drive(vdev, true);
584 ivpu_boot_pwr_island_drive(vdev, true);
585
586 ret = ivpu_boot_wait_for_pwr_island_status(vdev, 0x1);
587 if (ret) {
588 ivpu_err(vdev, "Timed out waiting for power island status\n");
589 return ret;
590 }
591
592 ret = ivpu_boot_top_noc_qrenqn_check(vdev, 0x0);
593 if (ret) {
594 ivpu_err(vdev, "Failed qrenqn check %d\n", ret);
595 return ret;
596 }
597
598 ivpu_boot_host_ss_clk_drive(vdev, true);
599 ivpu_boot_host_ss_rst_drive(vdev, true);
600 ivpu_boot_pwr_island_isolation_drive(vdev, false);
601
602 return ret;
603}
604
605static int ivpu_boot_soc_cpu_drive(struct ivpu_device *vdev, bool enable)
606{
607 int ret;
608 u32 val;
609
610 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN);
611 if (enable)
612 val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
613 else
614 val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
615 REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val);
616
617 ret = ivpu_boot_cpu_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
618 if (ret) {
619 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
620 return ret;
621 }
622
623 ret = ivpu_boot_cpu_noc_qdeny_check(vdev, 0x0);
624 if (ret)
625 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
626
627 return ret;
628}
629
630static int ivpu_boot_soc_cpu_enable(struct ivpu_device *vdev)
631{
632 return ivpu_boot_soc_cpu_drive(vdev, true);
633}
634
635static int ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev)
636{
637 int ret;
638 u32 val;
639 u64 val64;
640
641 ret = ivpu_boot_soc_cpu_enable(vdev);
642 if (ret) {
643 ivpu_err(vdev, "Failed to enable SOC CPU: %d\n", ret);
644 return ret;
645 }
646
647 val64 = vdev->fw->entry_point;
648 val64 <<= ffs(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK) - 1;
649 REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64);
650
651 val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO);
652 val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val);
653 REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val);
654
655 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
656 ivpu_fw_is_cold_boot(vdev) ? "cold boot" : "resume");
657
658 return 0;
659}
660
661static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable)
662{
663 int ret;
664 u32 val;
665
666 ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
667 if (ret) {
668 ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
669 return ret;
670 }
671
672 val = REGB_RD32(VPU_40XX_BUTTRESS_D0I3_CONTROL);
673 if (enable)
674 val = REG_SET_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
675 else
676 val = REG_CLR_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
677 REGB_WR32(VPU_40XX_BUTTRESS_D0I3_CONTROL, val);
678
679 ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
680 if (ret) {
681 ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
682 return ret;
683 }
684
685 return 0;
686}
687
688static bool ivpu_tile_disable_check(u32 config)
689{
690 /* Allowed values: 0 or one bit from range 0-5 (6 tiles) */
691 if (config == 0)
692 return true;
693
694 if (config > BIT(TILE_MAX_NUM - 1))
695 return false;
696
697 if ((config & (config - 1)) == 0)
698 return true;
699
700 return false;
701}
702
703static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev)
704{
705 struct ivpu_hw_info *hw = vdev->hw;
706 u32 tile_disable;
707 u32 fuse;
708
709 fuse = REGB_RD32(VPU_40XX_BUTTRESS_TILE_FUSE);
710 if (!REG_TEST_FLD(VPU_40XX_BUTTRESS_TILE_FUSE, VALID, fuse)) {
711 ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse);
712 return -EIO;
713 }
714
715 tile_disable = REG_GET_FLD(VPU_40XX_BUTTRESS_TILE_FUSE, CONFIG, fuse);
716 if (!ivpu_tile_disable_check(tile_disable)) {
717 ivpu_err(vdev, "Fuse: Invalid tile disable config (0x%x)\n", tile_disable);
718 return -EIO;
719 }
720
721 if (tile_disable)
722 ivpu_dbg(vdev, MISC, "Fuse: %d tiles enabled. Tile number %d disabled\n",
723 TILE_MAX_NUM - 1, ffs(tile_disable) - 1);
724 else
725 ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", TILE_MAX_NUM);
726
727 hw->tile_fuse = tile_disable;
728 hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
729
730 ivpu_pll_init_frequency_ratios(vdev);
731
732 ivpu_hw_init_range(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
733 ivpu_hw_init_range(&vdev->hw->ranges.user, 0x80000000, SZ_256M);
734 ivpu_hw_init_range(&vdev->hw->ranges.shave, 0x80000000 + SZ_256M, SZ_2G - SZ_256M);
735 ivpu_hw_init_range(&vdev->hw->ranges.dma, 0x200000000, SZ_8G);
736
737 ivpu_hw_read_platform(vdev);
738 ivpu_hw_wa_init(vdev);
739 ivpu_hw_timeouts_init(vdev);
740
741 return 0;
742}
743
744static int ivpu_hw_40xx_ip_reset(struct ivpu_device *vdev)
745{
746 int ret;
747 u32 val;
748
749 ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, 0, TIMEOUT_US);
750 if (ret) {
751 ivpu_err(vdev, "Wait for *_TRIGGER timed out\n");
752 return ret;
753 }
754
755 val = REGB_RD32(VPU_40XX_BUTTRESS_IP_RESET);
756 val = REG_SET_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, val);
757 REGB_WR32(VPU_40XX_BUTTRESS_IP_RESET, val);
758
759 ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, 0, TIMEOUT_US);
760 if (ret)
761 ivpu_err(vdev, "Timed out waiting for RESET completion\n");
762
763 return ret;
764}
765
766static int ivpu_hw_40xx_reset(struct ivpu_device *vdev)
767{
768 int ret = 0;
769
770 if (ivpu_hw_40xx_ip_reset(vdev)) {
771 ivpu_err(vdev, "Failed to reset NPU IP\n");
772 ret = -EIO;
773 }
774
775 if (ivpu_pll_disable(vdev)) {
776 ivpu_err(vdev, "Failed to disable PLL\n");
777 ret = -EIO;
778 }
779
780 return ret;
781}
782
783static int ivpu_hw_40xx_d0i3_enable(struct ivpu_device *vdev)
784{
785 int ret;
786
787 if (IVPU_WA(punit_disabled))
788 return 0;
789
790 ret = ivpu_boot_d0i3_drive(vdev, true);
791 if (ret)
792 ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);
793
794 udelay(5); /* VPU requires 5 us to complete the transition */
795
796 return ret;
797}
798
799static int ivpu_hw_40xx_d0i3_disable(struct ivpu_device *vdev)
800{
801 int ret;
802
803 if (IVPU_WA(punit_disabled))
804 return 0;
805
806 ret = ivpu_boot_d0i3_drive(vdev, false);
807 if (ret)
808 ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);
809
810 return ret;
811}
812
813static void ivpu_hw_40xx_profiling_freq_reg_set(struct ivpu_device *vdev)
814{
815 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
816
817 if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT)
818 val = REG_CLR_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
819 else
820 val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
821
822 REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
823}
824
825static void ivpu_hw_40xx_ats_print(struct ivpu_device *vdev)
826{
827 ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n",
828 REGB_RD32(VPU_40XX_BUTTRESS_HM_ATS) ? "Enable" : "Disable");
829}
830
831static void ivpu_hw_40xx_clock_relinquish_disable(struct ivpu_device *vdev)
832{
833 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
834
835 val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, DISABLE_CLK_RELINQUISH, val);
836 REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
837}
838
839static int ivpu_hw_40xx_power_up(struct ivpu_device *vdev)
840{
841 int ret;
842
843 ret = ivpu_hw_40xx_d0i3_disable(vdev);
844 if (ret)
845 ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret);
846
847 ret = ivpu_pll_enable(vdev);
848 if (ret) {
849 ivpu_err(vdev, "Failed to enable PLL: %d\n", ret);
850 return ret;
851 }
852
853 if (IVPU_WA(disable_clock_relinquish))
854 ivpu_hw_40xx_clock_relinquish_disable(vdev);
855 ivpu_hw_40xx_profiling_freq_reg_set(vdev);
856 ivpu_hw_40xx_ats_print(vdev);
857
858 ret = ivpu_boot_host_ss_check(vdev);
859 if (ret) {
860 ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
861 return ret;
862 }
863
864 ivpu_boot_idle_gen_drive(vdev, false);
865
866 ret = ivpu_boot_pwr_domain_enable(vdev);
867 if (ret) {
868 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
869 return ret;
870 }
871
872 ret = ivpu_boot_host_ss_axi_enable(vdev);
873 if (ret) {
874 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
875 return ret;
876 }
877
878 ret = ivpu_boot_host_ss_top_noc_enable(vdev);
879 if (ret)
880 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);
881
882 return ret;
883}
884
885static int ivpu_hw_40xx_boot_fw(struct ivpu_device *vdev)
886{
887 int ret;
888
889 ivpu_boot_no_snoop_enable(vdev);
890 ivpu_boot_tbu_mmu_enable(vdev);
891
892 ret = ivpu_boot_soc_cpu_boot(vdev);
893 if (ret)
894 ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret);
895
896 return ret;
897}
898
899static bool ivpu_hw_40xx_is_idle(struct ivpu_device *vdev)
900{
901 u32 val;
902
903 if (IVPU_WA(punit_disabled))
904 return true;
905
906 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
907 return REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, val) &&
908 REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, IDLE, val);
909}
910
911static int ivpu_hw_40xx_wait_for_idle(struct ivpu_device *vdev)
912{
913 return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
914}
915
916static void ivpu_hw_40xx_save_d0i3_entry_timestamp(struct ivpu_device *vdev)
917{
918 vdev->hw->d0i3_entry_host_ts = ktime_get_boottime();
919 vdev->hw->d0i3_entry_vpu_ts = REGV_RD64(VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT);
920}
921
922static int ivpu_hw_40xx_power_down(struct ivpu_device *vdev)
923{
924 int ret = 0;
925
926 ivpu_hw_40xx_save_d0i3_entry_timestamp(vdev);
927
928 if (!ivpu_hw_40xx_is_idle(vdev) && ivpu_hw_40xx_ip_reset(vdev))
929 ivpu_warn(vdev, "Failed to reset the NPU\n");
930
931 if (ivpu_pll_disable(vdev)) {
932 ivpu_err(vdev, "Failed to disable PLL\n");
933 ret = -EIO;
934 }
935
936 if (ivpu_hw_40xx_d0i3_enable(vdev)) {
937 ivpu_err(vdev, "Failed to enter D0I3\n");
938 ret = -EIO;
939 }
940
941 return ret;
942}
943
944static void ivpu_hw_40xx_wdt_disable(struct ivpu_device *vdev)
945{
946 u32 val;
947
948 REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
949 REGV_WR32(VPU_40XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);
950
951 REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
952 REGV_WR32(VPU_40XX_CPU_SS_TIM_WDOG_EN, 0);
953
954 val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG);
955 val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);
956 REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val);
957}
958
959static u32 ivpu_hw_40xx_profiling_freq_get(struct ivpu_device *vdev)
960{
961 return vdev->hw->pll.profiling_freq;
962}
963
964static void ivpu_hw_40xx_profiling_freq_drive(struct ivpu_device *vdev, bool enable)
965{
966 if (enable)
967 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_HIGH;
968 else
969 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
970}
971
972/* Register indirect accesses */
973static u32 ivpu_hw_40xx_reg_pll_freq_get(struct ivpu_device *vdev)
974{
975 u32 pll_curr_ratio;
976
977 pll_curr_ratio = REGB_RD32(VPU_40XX_BUTTRESS_PLL_FREQ);
978 pll_curr_ratio &= VPU_40XX_BUTTRESS_PLL_FREQ_RATIO_MASK;
979
980 return PLL_RATIO_TO_FREQ(pll_curr_ratio);
981}
982
983static u32 ivpu_hw_40xx_ratio_to_freq(struct ivpu_device *vdev, u32 ratio)
984{
985 return PLL_RATIO_TO_FREQ(ratio);
986}
987
988static u32 ivpu_hw_40xx_reg_telemetry_offset_get(struct ivpu_device *vdev)
989{
990 return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_OFFSET);
991}
992
993static u32 ivpu_hw_40xx_reg_telemetry_size_get(struct ivpu_device *vdev)
994{
995 return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_SIZE);
996}
997
998static u32 ivpu_hw_40xx_reg_telemetry_enable_get(struct ivpu_device *vdev)
999{
1000 return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_ENABLE);
1001}
1002
1003static void ivpu_hw_40xx_reg_db_set(struct ivpu_device *vdev, u32 db_id)
1004{
1005 u32 reg_stride = VPU_40XX_CPU_SS_DOORBELL_1 - VPU_40XX_CPU_SS_DOORBELL_0;
1006 u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET);
1007
1008 REGV_WR32I(VPU_40XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val);
1009}
1010
1011static u32 ivpu_hw_40xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev)
1012{
1013 return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM);
1014}
1015
1016static u32 ivpu_hw_40xx_reg_ipc_rx_count_get(struct ivpu_device *vdev)
1017{
1018 u32 count = REGV_RD32_SILENT(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT);
1019
1020 return REG_GET_FLD(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count);
1021}
1022
1023static void ivpu_hw_40xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
1024{
1025 REGV_WR32(VPU_40XX_CPU_SS_TIM_IPC_FIFO, vpu_addr);
1026}
1027
1028static void ivpu_hw_40xx_irq_clear(struct ivpu_device *vdev)
1029{
1030 REGV_WR64(VPU_40XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK);
1031}
1032
1033static void ivpu_hw_40xx_irq_enable(struct ivpu_device *vdev)
1034{
1035 REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK);
1036 REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK);
1037 REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK);
1038 REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
1039}
1040
1041static void ivpu_hw_40xx_irq_disable(struct ivpu_device *vdev)
1042{
1043 REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
1044 REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK);
1045 REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, 0x0ull);
1046 REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, 0x0ul);
1047}
1048
1049static void ivpu_hw_40xx_irq_wdt_nce_handler(struct ivpu_device *vdev)
1050{
1051 /* TODO: For LNN hang consider engine reset instead of full recovery */
1052 ivpu_pm_trigger_recovery(vdev, "WDT NCE IRQ");
1053}
1054
1055static void ivpu_hw_40xx_irq_wdt_mss_handler(struct ivpu_device *vdev)
1056{
1057 ivpu_hw_wdt_disable(vdev);
1058 ivpu_pm_trigger_recovery(vdev, "WDT MSS IRQ");
1059}
1060
1061static void ivpu_hw_40xx_irq_noc_firewall_handler(struct ivpu_device *vdev)
1062{
1063 ivpu_pm_trigger_recovery(vdev, "NOC Firewall IRQ");
1064}
1065
1066/* Handler for IRQs from VPU core (irqV) */
1067static bool ivpu_hw_40xx_irqv_handler(struct ivpu_device *vdev, int irq, bool *wake_thread)
1068{
1069 u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
1070
1071 if (!status)
1072 return false;
1073
1074 REGV_WR32(VPU_40XX_HOST_SS_ICB_CLEAR_0, status);
1075
1076 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status))
1077 ivpu_mmu_irq_evtq_handler(vdev);
1078
1079 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status))
1080 ivpu_ipc_irq_handler(vdev, wake_thread);
1081
1082 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status))
1083 ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
1084
1085 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status))
1086 ivpu_mmu_irq_gerr_handler(vdev);
1087
1088 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status))
1089 ivpu_hw_40xx_irq_wdt_mss_handler(vdev);
1090
1091 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status))
1092 ivpu_hw_40xx_irq_wdt_nce_handler(vdev);
1093
1094 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status))
1095 ivpu_hw_40xx_irq_noc_firewall_handler(vdev);
1096
1097 return true;
1098}
1099
1100/* Handler for IRQs from Buttress core (irqB) */
1101static bool ivpu_hw_40xx_irqb_handler(struct ivpu_device *vdev, int irq)
1102{
1103 bool schedule_recovery = false;
1104 u32 status = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
1105
1106 if (!status)
1107 return false;
1108
1109 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status))
1110 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE");
1111
1112 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, status)) {
1113 ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
1114 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1),
1115 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2));
1116 REGB_WR32(VPU_40XX_BUTTRESS_ATS_ERR_CLEAR, 0x1);
1117 schedule_recovery = true;
1118 }
1119
1120 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR, status)) {
1121 ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));
1122 REGB_WR32(VPU_40XX_BUTTRESS_CFI0_ERR_CLEAR, 0x1);
1123 schedule_recovery = true;
1124 }
1125
1126 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR, status)) {
1127 ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));
1128 REGB_WR32(VPU_40XX_BUTTRESS_CFI1_ERR_CLEAR, 0x1);
1129 schedule_recovery = true;
1130 }
1131
1132 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR, status)) {
1133 ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x",
1134 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW),
1135 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH));
1136 REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_CLEAR, 0x1);
1137 schedule_recovery = true;
1138 }
1139
1140 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR, status)) {
1141 ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x",
1142 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW),
1143 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH));
1144 REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_CLEAR, 0x1);
1145 schedule_recovery = true;
1146 }
1147
1148 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR, status)) {
1149 ivpu_err(vdev, "Survivability error detected\n");
1150 schedule_recovery = true;
1151 }
1152
1153 /* This must be done after interrupts are cleared at the source. */
1154 REGB_WR32(VPU_40XX_BUTTRESS_INTERRUPT_STAT, status);
1155
1156 if (schedule_recovery)
1157 ivpu_pm_trigger_recovery(vdev, "Buttress IRQ");
1158
1159 return true;
1160}
1161
1162static irqreturn_t ivpu_hw_40xx_irq_handler(int irq, void *ptr)
1163{
1164 bool irqv_handled, irqb_handled, wake_thread = false;
1165 struct ivpu_device *vdev = ptr;
1166
1167 REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
1168
1169 irqv_handled = ivpu_hw_40xx_irqv_handler(vdev, irq, &wake_thread);
1170 irqb_handled = ivpu_hw_40xx_irqb_handler(vdev, irq);
1171
1172 /* Re-enable global interrupts to re-trigger MSI for pending interrupts */
1173 REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
1174
1175 if (wake_thread)
1176 return IRQ_WAKE_THREAD;
1177 if (irqv_handled || irqb_handled)
1178 return IRQ_HANDLED;
1179 return IRQ_NONE;
1180}
1181
1182static void ivpu_hw_40xx_diagnose_failure(struct ivpu_device *vdev)
1183{
1184 u32 irqv = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
1185 u32 irqb = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
1186
1187 if (ivpu_hw_40xx_reg_ipc_rx_count_get(vdev))
1188 ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
1189
1190 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, irqv))
1191 ivpu_err(vdev, "WDT MSS timeout detected\n");
1192
1193 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, irqv))
1194 ivpu_err(vdev, "WDT NCE timeout detected\n");
1195
1196 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, irqv))
1197 ivpu_err(vdev, "NOC Firewall irq detected\n");
1198
1199 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, irqb)) {
1200 ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
1201 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1),
1202 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2));
1203 }
1204
1205 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR, irqb))
1206 ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));
1207
1208 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR, irqb))
1209 ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));
1210
1211 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR, irqb))
1212 ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n",
1213 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW),
1214 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH));
1215
1216 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR, irqb))
1217 ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n",
1218 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW),
1219 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH));
1220
1221 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR, irqb))
1222 ivpu_err(vdev, "Survivability error detected\n");
1223}
1224
1225const struct ivpu_hw_ops ivpu_hw_40xx_ops = {
1226 .info_init = ivpu_hw_40xx_info_init,
1227 .power_up = ivpu_hw_40xx_power_up,
1228 .is_idle = ivpu_hw_40xx_is_idle,
1229 .wait_for_idle = ivpu_hw_40xx_wait_for_idle,
1230 .power_down = ivpu_hw_40xx_power_down,
1231 .reset = ivpu_hw_40xx_reset,
1232 .boot_fw = ivpu_hw_40xx_boot_fw,
1233 .wdt_disable = ivpu_hw_40xx_wdt_disable,
1234 .diagnose_failure = ivpu_hw_40xx_diagnose_failure,
1235 .profiling_freq_get = ivpu_hw_40xx_profiling_freq_get,
1236 .profiling_freq_drive = ivpu_hw_40xx_profiling_freq_drive,
1237 .reg_pll_freq_get = ivpu_hw_40xx_reg_pll_freq_get,
1238 .ratio_to_freq = ivpu_hw_40xx_ratio_to_freq,
1239 .reg_telemetry_offset_get = ivpu_hw_40xx_reg_telemetry_offset_get,
1240 .reg_telemetry_size_get = ivpu_hw_40xx_reg_telemetry_size_get,
1241 .reg_telemetry_enable_get = ivpu_hw_40xx_reg_telemetry_enable_get,
1242 .reg_db_set = ivpu_hw_40xx_reg_db_set,
1243 .reg_ipc_rx_addr_get = ivpu_hw_40xx_reg_ipc_rx_addr_get,
1244 .reg_ipc_rx_count_get = ivpu_hw_40xx_reg_ipc_rx_count_get,
1245 .reg_ipc_tx_set = ivpu_hw_40xx_reg_ipc_tx_set,
1246 .irq_clear = ivpu_hw_40xx_irq_clear,
1247 .irq_enable = ivpu_hw_40xx_irq_enable,
1248 .irq_disable = ivpu_hw_40xx_irq_disable,
1249 .irq_handler = ivpu_hw_40xx_irq_handler,
1250};
drivers/accel/ivpu/ivpu_hw_40xx_reg.h+9−85
@@ -8,91 +8,6 @@ · 7 unmodified lines
8 8
9#include <linux/bits.h>9#include <linux/bits.h>
10 10
11#define VPU_40XX_BUTTRESS_INTERRUPT_STAT 0x00000000u
12#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
13#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
14#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_CFI0_ERR_MASK BIT_MASK(2)
15#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_CFI1_ERR_MASK BIT_MASK(3)
16#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_IMR0_ERR_MASK BIT_MASK(4)
17#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_IMR1_ERR_MASK BIT_MASK(5)
18#define VPU_40XX_BUTTRESS_INTERRUPT_STAT_SURV_ERR_MASK BIT_MASK(6)
19
20#define VPU_40XX_BUTTRESS_LOCAL_INT_MASK 0x00000004u
21#define VPU_40XX_BUTTRESS_GLOBAL_INT_MASK 0x00000008u
22
23#define VPU_40XX_BUTTRESS_HM_ATS 0x0000000cu
24
25#define VPU_40XX_BUTTRESS_ATS_ERR_LOG1 0x00000010u
26#define VPU_40XX_BUTTRESS_ATS_ERR_LOG2 0x00000014u
27#define VPU_40XX_BUTTRESS_ATS_ERR_CLEAR 0x00000018u
28
29#define VPU_40XX_BUTTRESS_CFI0_ERR_LOG 0x0000001cu
30#define VPU_40XX_BUTTRESS_CFI0_ERR_CLEAR 0x00000020u
31
32#define VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS 0x00000024u
33
34#define VPU_40XX_BUTTRESS_CFI1_ERR_LOG 0x00000040u
35#define VPU_40XX_BUTTRESS_CFI1_ERR_CLEAR 0x00000044u
36
37#define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW 0x00000048u
38#define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH 0x0000004cu
39#define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_CLEAR 0x00000050u
40
41#define VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS 0x00000054u
42
43#define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW 0x00000058u
44#define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH 0x0000005cu
45#define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_CLEAR 0x00000060u
46
47#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0 0x00000130u
48#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
49#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
50
51#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1 0x00000134u
52#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
53#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
54
55#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2 0x00000138u
56#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
57#define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2_CDYN_MASK GENMASK(31, 16)
58
59#define VPU_40XX_BUTTRESS_WP_REQ_CMD 0x0000013cu
60#define VPU_40XX_BUTTRESS_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
61
62#define VPU_40XX_BUTTRESS_PLL_FREQ 0x00000148u
63#define VPU_40XX_BUTTRESS_PLL_FREQ_RATIO_MASK GENMASK(15, 0)
64
65#define VPU_40XX_BUTTRESS_TILE_FUSE 0x00000150u
66#define VPU_40XX_BUTTRESS_TILE_FUSE_VALID_MASK BIT_MASK(0)
67#define VPU_40XX_BUTTRESS_TILE_FUSE_CONFIG_MASK GENMASK(6, 1)
68
69#define VPU_40XX_BUTTRESS_VPU_STATUS 0x00000154u
70#define VPU_40XX_BUTTRESS_VPU_STATUS_READY_MASK BIT_MASK(0)
71#define VPU_40XX_BUTTRESS_VPU_STATUS_IDLE_MASK BIT_MASK(1)
72#define VPU_40XX_BUTTRESS_VPU_STATUS_DUP_IDLE_MASK BIT_MASK(2)
73#define VPU_40XX_BUTTRESS_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK BIT_MASK(6)
74#define VPU_40XX_BUTTRESS_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK BIT_MASK(7)
75#define VPU_40XX_BUTTRESS_VPU_STATUS_PERF_CLK_MASK BIT_MASK(11)
76#define VPU_40XX_BUTTRESS_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK BIT_MASK(12)
77
78#define VPU_40XX_BUTTRESS_IP_RESET 0x00000160u
79#define VPU_40XX_BUTTRESS_IP_RESET_TRIGGER_MASK BIT_MASK(0)
80
81#define VPU_40XX_BUTTRESS_D0I3_CONTROL 0x00000164u
82#define VPU_40XX_BUTTRESS_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
83#define VPU_40XX_BUTTRESS_D0I3_CONTROL_I3_MASK BIT_MASK(2)
84
85#define VPU_40XX_BUTTRESS_VPU_TELEMETRY_OFFSET 0x00000168u
86#define VPU_40XX_BUTTRESS_VPU_TELEMETRY_SIZE 0x0000016cu
87#define VPU_40XX_BUTTRESS_VPU_TELEMETRY_ENABLE 0x00000170u
88
89#define VPU_40XX_BUTTRESS_FMIN_FUSE 0x00000174u
90#define VPU_40XX_BUTTRESS_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
91#define VPU_40XX_BUTTRESS_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
92
93#define VPU_40XX_BUTTRESS_FMAX_FUSE 0x00000178u
94#define VPU_40XX_BUTTRESS_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
95
96#define VPU_40XX_HOST_SS_CPR_CLK_EN 0x00000080u11#define VPU_40XX_HOST_SS_CPR_CLK_EN 0x00000080u
97#define VPU_40XX_HOST_SS_CPR_CLK_EN_TOP_NOC_MASK BIT_MASK(1)12#define VPU_40XX_HOST_SS_CPR_CLK_EN_TOP_NOC_MASK BIT_MASK(1)
98#define VPU_40XX_HOST_SS_CPR_CLK_EN_DSS_MAS_MASK BIT_MASK(10)13#define VPU_40XX_HOST_SS_CPR_CLK_EN_DSS_MAS_MASK BIT_MASK(10)
@@ -198,6 +113,12 @@ · 99 unmodified lines
198#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0 0x0003002cu113#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0 0x0003002cu
199#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0_CSS_CPU_MASK BIT_MASK(3)114#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0_CSS_CPU_MASK BIT_MASK(3)
200 115
116#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY 0x00030068u
117#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST_DLY_MASK GENMASK(7, 0)
118
119#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY 0x0003006cu
120#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK GENMASK(7, 0)
121
201#define VPU_40XX_HOST_SS_AON_IDLE_GEN 0x00030200u122#define VPU_40XX_HOST_SS_AON_IDLE_GEN 0x00030200u
202#define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK BIT_MASK(0)123#define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK BIT_MASK(0)
203#define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK BIT_MASK(1)124#define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK BIT_MASK(1)
@@ -205,6 +126,9 @@ · 1 unmodified line
205#define VPU_40XX_HOST_SS_AON_DPU_ACTIVE 0x00030204u126#define VPU_40XX_HOST_SS_AON_DPU_ACTIVE 0x00030204u
206#define VPU_40XX_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK BIT_MASK(0)127#define VPU_40XX_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK BIT_MASK(0)
207 128
129#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE 0x00030210u
130#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE_REQ_OVERRIDE_MASK BIT_MASK(0)
131
208#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO 0x00040040u132#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO 0x00040040u
209#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_DONE_MASK BIT_MASK(0)133#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_DONE_MASK BIT_MASK(0)
210#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IOSF_RS_ID_MASK GENMASK(2, 1)134#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IOSF_RS_ID_MASK GENMASK(2, 1)
drivers/accel/ivpu/ivpu_hw_btrs.c+905−0
@@ -0,0 +1,905 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6#include "ivpu_drv.h"
7#include "ivpu_hw.h"
8#include "ivpu_hw_btrs.h"
9#include "ivpu_hw_btrs_lnl_reg.h"
10#include "ivpu_hw_btrs_mtl_reg.h"
11#include "ivpu_hw_reg_io.h"
12#include "ivpu_pm.h"
13
14#define BTRS_MTL_IRQ_MASK ((REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR)) | \
15 (REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR)))
16
17#define BTRS_LNL_IRQ_MASK ((REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR)) | \
18 (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR)) | \
19 (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR)) | \
20 (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR)) | \
21 (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR)) | \
22 (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR)))
23
24#define BTRS_MTL_ALL_IRQ_MASK (BTRS_MTL_IRQ_MASK | (REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, \
25 FREQ_CHANGE)))
26
27#define BTRS_IRQ_DISABLE_MASK ((u32)-1)
28
29#define BTRS_LNL_ALL_IRQ_MASK ((u32)-1)
30
31#define BTRS_MTL_WP_CONFIG_1_TILE_5_3_RATIO WP_CONFIG(MTL_CONFIG_1_TILE, MTL_PLL_RATIO_5_3)
32#define BTRS_MTL_WP_CONFIG_1_TILE_4_3_RATIO WP_CONFIG(MTL_CONFIG_1_TILE, MTL_PLL_RATIO_4_3)
33#define BTRS_MTL_WP_CONFIG_2_TILE_5_3_RATIO WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_5_3)
34#define BTRS_MTL_WP_CONFIG_2_TILE_4_3_RATIO WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_4_3)
35#define BTRS_MTL_WP_CONFIG_0_TILE_PLL_OFF WP_CONFIG(0, 0)
36
37#define PLL_CDYN_DEFAULT 0x80
38#define PLL_EPP_DEFAULT 0x80
39#define PLL_CONFIG_DEFAULT 0x0
40#define PLL_SIMULATION_FREQ 10000000
41#define PLL_REF_CLK_FREQ 50000000
42#define PLL_TIMEOUT_US (1500 * USEC_PER_MSEC)
43#define IDLE_TIMEOUT_US (5 * USEC_PER_MSEC)
44#define TIMEOUT_US (150 * USEC_PER_MSEC)
45
46/* Work point configuration values */
47#define WP_CONFIG(tile, ratio) (((tile) << 8) | (ratio))
48#define MTL_CONFIG_1_TILE 0x01
49#define MTL_CONFIG_2_TILE 0x02
50#define MTL_PLL_RATIO_5_3 0x01
51#define MTL_PLL_RATIO_4_3 0x02
52#define BTRS_MTL_TILE_FUSE_ENABLE_BOTH 0x0
53#define BTRS_MTL_TILE_SKU_BOTH 0x3630
54
55#define BTRS_LNL_TILE_MAX_NUM 6
56#define BTRS_LNL_TILE_MAX_MASK 0x3f
57
58#define WEIGHTS_DEFAULT 0xf711f711u
59#define WEIGHTS_ATS_DEFAULT 0x0000f711u
60
61#define DCT_REQ 0x2
62#define DCT_ENABLE 0x1
63#define DCT_DISABLE 0x0
64
65int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev)
66{
67 REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, BTRS_MTL_ALL_IRQ_MASK);
68 if (REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) == BTRS_MTL_ALL_IRQ_MASK) {
69 /* Writing 1s does not clear the interrupt status register */
70 REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0);
71 return true;
72 }
73
74 return false;
75}
76
77static void freq_ratios_init_mtl(struct ivpu_device *vdev)
78{
79 struct ivpu_hw_info *hw = vdev->hw;
80 u32 fmin_fuse, fmax_fuse;
81
82 fmin_fuse = REGB_RD32(VPU_HW_BTRS_MTL_FMIN_FUSE);
83 hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, MIN_RATIO, fmin_fuse);
84 hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, PN_RATIO, fmin_fuse);
85
86 fmax_fuse = REGB_RD32(VPU_HW_BTRS_MTL_FMAX_FUSE);
87 hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMAX_FUSE, MAX_RATIO, fmax_fuse);
88}
89
90static void freq_ratios_init_lnl(struct ivpu_device *vdev)
91{
92 struct ivpu_hw_info *hw = vdev->hw;
93 u32 fmin_fuse, fmax_fuse;
94
95 fmin_fuse = REGB_RD32(VPU_HW_BTRS_LNL_FMIN_FUSE);
96 hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, MIN_RATIO, fmin_fuse);
97 hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, PN_RATIO, fmin_fuse);
98
99 fmax_fuse = REGB_RD32(VPU_HW_BTRS_LNL_FMAX_FUSE);
100 hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMAX_FUSE, MAX_RATIO, fmax_fuse);
101}
102
103void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev)
104{
105 struct ivpu_hw_info *hw = vdev->hw;
106
107 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
108 freq_ratios_init_mtl(vdev);
109 else
110 freq_ratios_init_lnl(vdev);
111
112 hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
113 hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
114 hw->pll.pn_ratio = clamp_t(u8, hw->pll.pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
115}
116
117static bool tile_disable_check(u32 config)
118{
119 /* Allowed values: 0 or one bit from range 0-5 (6 tiles) */
120 if (config == 0)
121 return true;
122
123 if (config > BIT(BTRS_LNL_TILE_MAX_NUM - 1))
124 return false;
125
126 if ((config & (config - 1)) == 0)
127 return true;
128
129 return false;
130}
131
132static int read_tile_config_fuse(struct ivpu_device *vdev, u32 *tile_fuse_config)
133{
134 u32 fuse;
135 u32 config;
136
137 fuse = REGB_RD32(VPU_HW_BTRS_LNL_TILE_FUSE);
138 if (!REG_TEST_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, VALID, fuse)) {
139 ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse);
140 return -EIO;
141 }
142
143 config = REG_GET_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, CONFIG, fuse);
144 if (!tile_disable_check(config)) {
145 ivpu_err(vdev, "Fuse: Invalid tile disable config (0x%x)\n", config);
146 return -EIO;
147 }
148
149 if (config)
150 ivpu_dbg(vdev, MISC, "Fuse: %d tiles enabled. Tile number %d disabled\n",
151 BTRS_LNL_TILE_MAX_NUM - 1, ffs(config) - 1);
152 else
153 ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", BTRS_LNL_TILE_MAX_NUM);
154
155 *tile_fuse_config = config;
156 return 0;
157}
158
159static int info_init_mtl(struct ivpu_device *vdev)
160{
161 struct ivpu_hw_info *hw = vdev->hw;
162
163 hw->tile_fuse = BTRS_MTL_TILE_FUSE_ENABLE_BOTH;
164 hw->sku = BTRS_MTL_TILE_SKU_BOTH;
165 hw->config = BTRS_MTL_WP_CONFIG_2_TILE_4_3_RATIO;
166 hw->sched_mode = ivpu_sched_mode;
167
168 return 0;
169}
170
171static int info_init_lnl(struct ivpu_device *vdev)
172{
173 struct ivpu_hw_info *hw = vdev->hw;
174 u32 tile_fuse_config;
175 int ret;
176
177 ret = read_tile_config_fuse(vdev, &tile_fuse_config);
178 if (ret)
179 return ret;
180
181 hw->sched_mode = ivpu_sched_mode;
182 hw->tile_fuse = tile_fuse_config;
183 hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
184
185 return 0;
186}
187
188int ivpu_hw_btrs_info_init(struct ivpu_device *vdev)
189{
190 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
191 return info_init_mtl(vdev);
192 else
193 return info_init_lnl(vdev);
194}
195
196static int wp_request_sync(struct ivpu_device *vdev)
197{
198 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
199 return REGB_POLL_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
200 else
201 return REGB_POLL_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
202}
203
204static int wait_for_status_ready(struct ivpu_device *vdev, bool enable)
205{
206 u32 exp_val = enable ? 0x1 : 0x0;
207
208 if (IVPU_WA(punit_disabled))
209 return 0;
210
211 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
212 return REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, READY, exp_val, PLL_TIMEOUT_US);
213 else
214 return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, exp_val, PLL_TIMEOUT_US);
215}
216
217struct wp_request {
218 u16 min;
219 u16 max;
220 u16 target;
221 u16 cfg;
222 u16 epp;
223 u16 cdyn;
224};
225
226static void wp_request_mtl(struct ivpu_device *vdev, struct wp_request *wp)
227{
228 u32 val;
229
230 val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0);
231 val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);
232 val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);
233 REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, val);
234
235 val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1);
236 val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);
237 val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, EPP, PLL_EPP_DEFAULT, val);
238 REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, val);
239
240 val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2);
241 val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);
242 REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, val);
243
244 val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_CMD);
245 val = REG_SET_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, val);
246 REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_CMD, val);
247}
248
249static void wp_request_lnl(struct ivpu_device *vdev, struct wp_request *wp)
250{
251 u32 val;
252
253 val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0);
254 val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);
255 val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);
256 REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, val);
257
258 val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1);
259 val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);
260 val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, EPP, wp->epp, val);
261 REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, val);
262
263 val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2);
264 val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);
265 val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CDYN, wp->cdyn, val);
266 REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, val);
267
268 val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_CMD);
269 val = REG_SET_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, val);
270 REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_CMD, val);
271}
272
273static void wp_request(struct ivpu_device *vdev, struct wp_request *wp)
274{
275 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
276 wp_request_mtl(vdev, wp);
277 else
278 wp_request_lnl(vdev, wp);
279}
280
281static int wp_request_send(struct ivpu_device *vdev, struct wp_request *wp)
282{
283 int ret;
284
285 ret = wp_request_sync(vdev);
286 if (ret) {
287 ivpu_err(vdev, "Failed to sync before workpoint request: %d\n", ret);
288 return ret;
289 }
290
291 wp_request(vdev, wp);
292
293 ret = wp_request_sync(vdev);
294 if (ret)
295 ivpu_err(vdev, "Failed to sync after workpoint request: %d\n", ret);
296
297 return ret;
298}
299
300static void prepare_wp_request(struct ivpu_device *vdev, struct wp_request *wp, bool enable)
301{
302 struct ivpu_hw_info *hw = vdev->hw;
303
304 wp->min = hw->pll.min_ratio;
305 wp->max = hw->pll.max_ratio;
306
307 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {
308 wp->target = enable ? hw->pll.pn_ratio : 0;
309 wp->cfg = enable ? hw->config : 0;
310 wp->cdyn = 0;
311 wp->epp = 0;
312 } else {
313 wp->target = hw->pll.pn_ratio;
314 wp->cfg = enable ? PLL_CONFIG_DEFAULT : 0;
315 wp->cdyn = enable ? PLL_CDYN_DEFAULT : 0;
316 wp->epp = enable ? PLL_EPP_DEFAULT : 0;
317 }
318
319 /* Simics cannot start without at least one tile */
320 if (enable && ivpu_is_simics(vdev))
321 wp->cfg = 1;
322}
323
324static int wait_for_pll_lock(struct ivpu_device *vdev, bool enable)
325{
326 u32 exp_val = enable ? 0x1 : 0x0;
327
328 if (ivpu_hw_btrs_gen(vdev) != IVPU_HW_BTRS_MTL)
329 return 0;
330
331 if (IVPU_WA(punit_disabled))
332 return 0;
333
334 return REGB_POLL_FLD(VPU_HW_BTRS_MTL_PLL_STATUS, LOCK, exp_val, PLL_TIMEOUT_US);
335}
336
337int ivpu_hw_btrs_wp_drive(struct ivpu_device *vdev, bool enable)
338{
339 struct wp_request wp;
340 int ret;
341
342 if (IVPU_WA(punit_disabled)) {
343 ivpu_dbg(vdev, PM, "Skipping workpoint request\n");
344 return 0;
345 }
346
347 prepare_wp_request(vdev, &wp, enable);
348
349 ivpu_dbg(vdev, PM, "PLL workpoint request: %u Hz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n",
350 PLL_RATIO_TO_FREQ(wp.target), wp.cfg, wp.epp, wp.cdyn);
351
352 ret = wp_request_send(vdev, &wp);
353 if (ret) {
354 ivpu_err(vdev, "Failed to send workpoint request: %d\n", ret);
355 return ret;
356 }
357
358 ret = wait_for_pll_lock(vdev, enable);
359 if (ret) {
360 ivpu_err(vdev, "Timed out waiting for PLL lock\n");
361 return ret;
362 }
363
364 ret = wait_for_status_ready(vdev, enable);
365 if (ret) {
366 ivpu_err(vdev, "Timed out waiting for NPU ready status\n");
367 return ret;
368 }
369
370 return 0;
371}
372
373static int d0i3_drive_mtl(struct ivpu_device *vdev, bool enable)
374{
375 int ret;
376 u32 val;
377
378 ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
379 if (ret) {
380 ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
381 return ret;
382 }
383
384 val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL);
385 if (enable)
386 val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val);
387 else
388 val = REG_CLR_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val);
389 REGB_WR32(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, val);
390
391 ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
392 if (ret)
393 ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
394
395 return ret;
396}
397
398static int d0i3_drive_lnl(struct ivpu_device *vdev, bool enable)
399{
400 int ret;
401 u32 val;
402
403 ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
404 if (ret) {
405 ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
406 return ret;
407 }
408
409 val = REGB_RD32(VPU_HW_BTRS_LNL_D0I3_CONTROL);
410 if (enable)
411 val = REG_SET_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val);
412 else
413 val = REG_CLR_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val);
414 REGB_WR32(VPU_HW_BTRS_LNL_D0I3_CONTROL, val);
415
416 ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
417 if (ret) {
418 ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
419 return ret;
420 }
421
422 return 0;
423}
424
425static int d0i3_drive(struct ivpu_device *vdev, bool enable)
426{
427 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
428 return d0i3_drive_mtl(vdev, enable);
429 else
430 return d0i3_drive_lnl(vdev, enable);
431}
432
433int ivpu_hw_btrs_d0i3_enable(struct ivpu_device *vdev)
434{
435 int ret;
436
437 if (IVPU_WA(punit_disabled))
438 return 0;
439
440 ret = d0i3_drive(vdev, true);
441 if (ret)
442 ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);
443
444 udelay(5); /* VPU requires 5 us to complete the transition */
445
446 return ret;
447}
448
449int ivpu_hw_btrs_d0i3_disable(struct ivpu_device *vdev)
450{
451 int ret;
452
453 if (IVPU_WA(punit_disabled))
454 return 0;
455
456 ret = d0i3_drive(vdev, false);
457 if (ret)
458 ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);
459
460 return ret;
461}
462
463int ivpu_hw_btrs_wait_for_clock_res_own_ack(struct ivpu_device *vdev)
464{
465 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
466 return 0;
467
468 if (ivpu_is_simics(vdev))
469 return 0;
470
471 return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, CLOCK_RESOURCE_OWN_ACK, 1, TIMEOUT_US);
472}
473
474void ivpu_hw_btrs_set_port_arbitration_weights_lnl(struct ivpu_device *vdev)
475{
476 REGB_WR32(VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT);
477 REGB_WR32(VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT);
478}
479
480static int ip_reset_mtl(struct ivpu_device *vdev)
481{
482 int ret;
483 u32 val;
484
485 ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US);
486 if (ret) {
487 ivpu_err(vdev, "Timed out waiting for TRIGGER bit\n");
488 return ret;
489 }
490
491 val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_IP_RESET);
492 val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, val);
493 REGB_WR32(VPU_HW_BTRS_MTL_VPU_IP_RESET, val);
494
495 ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US);
496 if (ret)
497 ivpu_err(vdev, "Timed out waiting for RESET completion\n");
498
499 return ret;
500}
501
502static int ip_reset_lnl(struct ivpu_device *vdev)
503{
504 int ret;
505 u32 val;
506
507 ivpu_hw_btrs_clock_relinquish_disable_lnl(vdev);
508
509 ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, 0, TIMEOUT_US);
510 if (ret) {
511 ivpu_err(vdev, "Wait for *_TRIGGER timed out\n");
512 return ret;
513 }
514
515 val = REGB_RD32(VPU_HW_BTRS_LNL_IP_RESET);
516 val = REG_SET_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, val);
517 REGB_WR32(VPU_HW_BTRS_LNL_IP_RESET, val);
518
519 ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, 0, TIMEOUT_US);
520 if (ret)
521 ivpu_err(vdev, "Timed out waiting for RESET completion\n");
522
523 return ret;
524}
525
526int ivpu_hw_btrs_ip_reset(struct ivpu_device *vdev)
527{
528 if (IVPU_WA(punit_disabled))
529 return 0;
530
531 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
532 return ip_reset_mtl(vdev);
533 else
534 return ip_reset_lnl(vdev);
535}
536
537void ivpu_hw_btrs_profiling_freq_reg_set_lnl(struct ivpu_device *vdev)
538{
539 u32 val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
540
541 if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT)
542 val = REG_CLR_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val);
543 else
544 val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val);
545
546 REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val);
547}
548
549void ivpu_hw_btrs_ats_print_lnl(struct ivpu_device *vdev)
550{
551 ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n",
552 REGB_RD32(VPU_HW_BTRS_LNL_HM_ATS) ? "Enable" : "Disable");
553}
554
555void ivpu_hw_btrs_clock_relinquish_disable_lnl(struct ivpu_device *vdev)
556{
557 u32 val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
558
559 val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, DISABLE_CLK_RELINQUISH, val);
560 REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val);
561}
562
563bool ivpu_hw_btrs_is_idle(struct ivpu_device *vdev)
564{
565 u32 val;
566
567 if (IVPU_WA(punit_disabled))
568 return true;
569
570 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {
571 val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_STATUS);
572
573 return REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, READY, val) &&
574 REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, IDLE, val);
575 } else {
576 val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
577
578 return REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, val) &&
579 REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, val);
580 }
581}
582
583int ivpu_hw_btrs_wait_for_idle(struct ivpu_device *vdev)
584{
585 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
586 return REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
587 else
588 return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
589}
590
591/* Handler for IRQs from Buttress core (irqB) */
592bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq)
593{
594 u32 status = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BTRS_MTL_IRQ_MASK;
595 bool schedule_recovery = false;
596
597 if (!status)
598 return false;
599
600 if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE, status))
601 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x",
602 REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL));
603
604 if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, status)) {
605 ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));
606 REGB_WR32(VPU_HW_BTRS_MTL_ATS_ERR_CLEAR, 0x1);
607 schedule_recovery = true;
608 }
609
610 if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR, status)) {
611 u32 ufi_log = REGB_RD32(VPU_HW_BTRS_MTL_UFI_ERR_LOG);
612
613 ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
614 ufi_log, REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, OPCODE, ufi_log),
615 REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, AXI_ID, ufi_log),
616 REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, CQ_ID, ufi_log));
617 REGB_WR32(VPU_HW_BTRS_MTL_UFI_ERR_CLEAR, 0x1);
618 schedule_recovery = true;
619 }
620
621 /* This must be done after interrupts are cleared at the source. */
622 if (IVPU_WA(interrupt_clear_with_0))
623 /*
624 * Writing 1 triggers an interrupt, so we can't perform read update write.
625 * Clear local interrupt status by writing 0 to all bits.
626 */
627 REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0);
628 else
629 REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, status);
630
631 if (schedule_recovery)
632 ivpu_pm_trigger_recovery(vdev, "Buttress IRQ");
633
634 return true;
635}
636
637/* Handler for IRQs from Buttress core (irqB) */
638bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq)
639{
640 u32 status = REGB_RD32(VPU_HW_BTRS_LNL_INTERRUPT_STAT) & BTRS_LNL_IRQ_MASK;
641 bool schedule_recovery = false;
642
643 if (!status)
644 return false;
645
646 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR, status)) {
647 ivpu_dbg(vdev, IRQ, "Survivability IRQ\n");
648 if (!kfifo_put(&vdev->hw->irq.fifo, IVPU_HW_IRQ_SRC_DCT))
649 ivpu_err_ratelimited(vdev, "IRQ FIFO full\n");
650 }
651
652 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, FREQ_CHANGE, status))
653 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ));
654
655 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, status)) {
656 ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
657 REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG1),
658 REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG2));
659 REGB_WR32(VPU_HW_BTRS_LNL_ATS_ERR_CLEAR, 0x1);
660 schedule_recovery = true;
661 }
662
663 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR, status)) {
664 ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));
665 REGB_WR32(VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR, 0x1);
666 schedule_recovery = true;
667 }
668
669 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR, status)) {
670 ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));
671 REGB_WR32(VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR, 0x1);
672 schedule_recovery = true;
673 }
674
675 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR, status)) {
676 ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x",
677 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW),
678 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH));
679 REGB_WR32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR, 0x1);
680 schedule_recovery = true;
681 }
682
683 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR, status)) {
684 ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x",
685 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW),
686 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH));
687 REGB_WR32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR, 0x1);
688 schedule_recovery = true;
689 }
690
691 /* This must be done after interrupts are cleared at the source. */
692 REGB_WR32(VPU_HW_BTRS_LNL_INTERRUPT_STAT, status);
693
694 if (schedule_recovery)
695 ivpu_pm_trigger_recovery(vdev, "Buttress IRQ");
696
697 return true;
698}
699
700int ivpu_hw_btrs_dct_get_request(struct ivpu_device *vdev, bool *enable)
701{
702 u32 val = REGB_RD32(VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW);
703 u32 cmd = REG_GET_FLD(VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW, CMD, val);
704 u32 param1 = REG_GET_FLD(VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW, PARAM1, val);
705
706 if (cmd != DCT_REQ) {
707 ivpu_err_ratelimited(vdev, "Unsupported PCODE command: 0x%x\n", cmd);
708 return -EBADR;
709 }
710
711 switch (param1) {
712 case DCT_ENABLE:
713 *enable = true;
714 return 0;
715 case DCT_DISABLE:
716 *enable = false;
717 return 0;
718 default:
719 ivpu_err_ratelimited(vdev, "Invalid PARAM1 value: %u\n", param1);
720 return -EINVAL;
721 }
722}
723
724void ivpu_hw_btrs_dct_set_status(struct ivpu_device *vdev, bool enable, u32 active_percent)
725{
726 u32 val = 0;
727 u32 cmd = enable ? DCT_ENABLE : DCT_DISABLE;
728
729 val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, CMD, DCT_REQ, val);
730 val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, PARAM1, cmd, val);
731 val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, PARAM2, active_percent, val);
732
733 REGB_WR32(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, val);
734}
735
736static u32 pll_ratio_to_freq_mtl(u32 ratio, u32 config)
737{
738 u32 pll_clock = PLL_REF_CLK_FREQ * ratio;
739 u32 cpu_clock;
740
741 if ((config & 0xff) == MTL_PLL_RATIO_4_3)
742 cpu_clock = pll_clock * 2 / 4;
743 else
744 cpu_clock = pll_clock * 2 / 5;
745
746 return cpu_clock;
747}
748
749u32 ivpu_hw_btrs_ratio_to_freq(struct ivpu_device *vdev, u32 ratio)
750{
751 struct ivpu_hw_info *hw = vdev->hw;
752
753 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
754 return pll_ratio_to_freq_mtl(ratio, hw->config);
755 else
756 return PLL_RATIO_TO_FREQ(ratio);
757}
758
759static u32 pll_freq_get_mtl(struct ivpu_device *vdev)
760{
761 u32 pll_curr_ratio;
762
763 pll_curr_ratio = REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL);
764 pll_curr_ratio &= VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK;
765
766 if (!ivpu_is_silicon(vdev))
767 return PLL_SIMULATION_FREQ;
768
769 return pll_ratio_to_freq_mtl(pll_curr_ratio, vdev->hw->config);
770}
771
772static u32 pll_freq_get_lnl(struct ivpu_device *vdev)
773{
774 u32 pll_curr_ratio;
775
776 pll_curr_ratio = REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ);
777 pll_curr_ratio &= VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK;
778
779 return PLL_RATIO_TO_FREQ(pll_curr_ratio);
780}
781
782u32 ivpu_hw_btrs_pll_freq_get(struct ivpu_device *vdev)
783{
784 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
785 return pll_freq_get_mtl(vdev);
786 else
787 return pll_freq_get_lnl(vdev);
788}
789
790u32 ivpu_hw_btrs_telemetry_offset_get(struct ivpu_device *vdev)
791{
792 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
793 return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET);
794 else
795 return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_OFFSET);
796}
797
798u32 ivpu_hw_btrs_telemetry_size_get(struct ivpu_device *vdev)
799{
800 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
801 return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE);
802 else
803 return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_SIZE);
804}
805
806u32 ivpu_hw_btrs_telemetry_enable_get(struct ivpu_device *vdev)
807{
808 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
809 return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE);
810 else
811 return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_ENABLE);
812}
813
814void ivpu_hw_btrs_global_int_disable(struct ivpu_device *vdev)
815{
816 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
817 REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x1);
818 else
819 REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x1);
820}
821
822void ivpu_hw_btrs_global_int_enable(struct ivpu_device *vdev)
823{
824 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
825 REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x0);
826 else
827 REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x0);
828}
829
830void ivpu_hw_btrs_irq_enable(struct ivpu_device *vdev)
831{
832 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {
833 REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, (u32)(~BTRS_MTL_IRQ_MASK));
834 REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x0);
835 } else {
836 REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, (u32)(~BTRS_LNL_IRQ_MASK));
837 REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x0);
838 }
839}
840
841void ivpu_hw_btrs_irq_disable(struct ivpu_device *vdev)
842{
843 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {
844 REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x1);
845 REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, BTRS_IRQ_DISABLE_MASK);
846 } else {
847 REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x1);
848 REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, BTRS_IRQ_DISABLE_MASK);
849 }
850}
851
852static void diagnose_failure_mtl(struct ivpu_device *vdev)
853{
854 u32 reg = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BTRS_MTL_IRQ_MASK;
855
856 if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, reg))
857 ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));
858
859 if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR, reg)) {
860 u32 log = REGB_RD32(VPU_HW_BTRS_MTL_UFI_ERR_LOG);
861
862 ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
863 log, REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, OPCODE, log),
864 REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, AXI_ID, log),
865 REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, CQ_ID, log));
866 }
867}
868
869static void diagnose_failure_lnl(struct ivpu_device *vdev)
870{
871 u32 reg = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BTRS_LNL_IRQ_MASK;
872
873 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, reg)) {
874 ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
875 REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG1),
876 REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG2));
877 }
878
879 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR, reg))
880 ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));
881
882 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR, reg))
883 ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));
884
885 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR, reg))
886 ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n",
887 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW),
888 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH));
889
890 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR, reg))
891 ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n",
892 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW),
893 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH));
894
895 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR, reg))
896 ivpu_err(vdev, "Survivability IRQ\n");
897}
898
899void ivpu_hw_btrs_diagnose_failure(struct ivpu_device *vdev)
900{
901 if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
902 return diagnose_failure_mtl(vdev);
903 else
904 return diagnose_failure_lnl(vdev);
905}
drivers/accel/ivpu/ivpu_hw_btrs.h+50−0
@@ -0,0 +1,50 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6#ifndef __IVPU_HW_BTRS_H__
7#define __IVPU_HW_BTRS_H__
8
9#include "ivpu_drv.h"
10#include "ivpu_hw_37xx_reg.h"
11#include "ivpu_hw_40xx_reg.h"
12#include "ivpu_hw_reg_io.h"
13
14#define PLL_PROFILING_FREQ_DEFAULT 38400000
15#define PLL_PROFILING_FREQ_HIGH 400000000
16#define PLL_RATIO_TO_FREQ(x) ((x) * PLL_REF_CLK_FREQ)
17
18#define DCT_DEFAULT_ACTIVE_PERCENT 15u
19#define DCT_PERIOD_US 35300u
20
21int ivpu_hw_btrs_info_init(struct ivpu_device *vdev);
22void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev);
23int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev);
24int ivpu_hw_btrs_wp_drive(struct ivpu_device *vdev, bool enable);
25int ivpu_hw_btrs_wait_for_clock_res_own_ack(struct ivpu_device *vdev);
26int ivpu_hw_btrs_d0i3_enable(struct ivpu_device *vdev);
27int ivpu_hw_btrs_d0i3_disable(struct ivpu_device *vdev);
28void ivpu_hw_btrs_set_port_arbitration_weights_lnl(struct ivpu_device *vdev);
29bool ivpu_hw_btrs_is_idle(struct ivpu_device *vdev);
30int ivpu_hw_btrs_wait_for_idle(struct ivpu_device *vdev);
31int ivpu_hw_btrs_ip_reset(struct ivpu_device *vdev);
32void ivpu_hw_btrs_profiling_freq_reg_set_lnl(struct ivpu_device *vdev);
33void ivpu_hw_btrs_ats_print_lnl(struct ivpu_device *vdev);
34void ivpu_hw_btrs_clock_relinquish_disable_lnl(struct ivpu_device *vdev);
35bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq);
36bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq);
37int ivpu_hw_btrs_dct_get_request(struct ivpu_device *vdev, bool *enable);
38void ivpu_hw_btrs_dct_set_status(struct ivpu_device *vdev, bool enable, u32 dct_percent);
39u32 ivpu_hw_btrs_pll_freq_get(struct ivpu_device *vdev);
40u32 ivpu_hw_btrs_ratio_to_freq(struct ivpu_device *vdev, u32 ratio);
41u32 ivpu_hw_btrs_telemetry_offset_get(struct ivpu_device *vdev);
42u32 ivpu_hw_btrs_telemetry_size_get(struct ivpu_device *vdev);
43u32 ivpu_hw_btrs_telemetry_enable_get(struct ivpu_device *vdev);
44void ivpu_hw_btrs_global_int_enable(struct ivpu_device *vdev);
45void ivpu_hw_btrs_global_int_disable(struct ivpu_device *vdev);
46void ivpu_hw_btrs_irq_enable(struct ivpu_device *vdev);
47void ivpu_hw_btrs_irq_disable(struct ivpu_device *vdev);
48void ivpu_hw_btrs_diagnose_failure(struct ivpu_device *vdev);
49
50#endif /* __IVPU_HW_BTRS_H__ */
drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h+108−0
@@ -0,0 +1,108 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6#ifndef __IVPU_HW_BTRS_LNL_REG_H__
7#define __IVPU_HW_BTRS_LNL_REG_H__
8
9#include <linux/bits.h>
10
11#define VPU_HW_BTRS_LNL_INTERRUPT_STAT 0x00000000u
12#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
13#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
14#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI0_ERR_MASK BIT_MASK(2)
15#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI1_ERR_MASK BIT_MASK(3)
16#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR0_ERR_MASK BIT_MASK(4)
17#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR1_ERR_MASK BIT_MASK(5)
18#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_SURV_ERR_MASK BIT_MASK(6)
19
20#define VPU_HW_BTRS_LNL_LOCAL_INT_MASK 0x00000004u
21#define VPU_HW_BTRS_LNL_GLOBAL_INT_MASK 0x00000008u
22
23#define VPU_HW_BTRS_LNL_HM_ATS 0x0000000cu
24
25#define VPU_HW_BTRS_LNL_ATS_ERR_LOG1 0x00000010u
26#define VPU_HW_BTRS_LNL_ATS_ERR_LOG2 0x00000014u
27#define VPU_HW_BTRS_LNL_ATS_ERR_CLEAR 0x00000018u
28
29#define VPU_HW_BTRS_LNL_CFI0_ERR_LOG 0x0000001cu
30#define VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR 0x00000020u
31
32#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS 0x00000024u
33
34#define VPU_HW_BTRS_LNL_CFI1_ERR_LOG 0x00000040u
35#define VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR 0x00000044u
36
37#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW 0x00000048u
38#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH 0x0000004cu
39#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR 0x00000050u
40
41#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS 0x00000054u
42
43#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW 0x00000058u
44#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH 0x0000005cu
45#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR 0x00000060u
46
47#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS 0x00000070u
48#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_CMD_MASK GENMASK(7, 0)
49#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM1_MASK GENMASK(15, 8)
50#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM2_MASK GENMASK(23, 16)
51#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM3_MASK GENMASK(31, 24)
52
53#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW 0x00000074u
54#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_CMD_MASK GENMASK(7, 0)
55#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM1_MASK GENMASK(15, 8)
56#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM2_MASK GENMASK(23, 16)
57#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM3_MASK GENMASK(31, 24)
58
59#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0 0x00000130u
60#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
61#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
62
63#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1 0x00000134u
64#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
65#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
66
67#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2 0x00000138u
68#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
69#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CDYN_MASK GENMASK(31, 16)
70
71#define VPU_HW_BTRS_LNL_WP_REQ_CMD 0x0000013cu
72#define VPU_HW_BTRS_LNL_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
73
74#define VPU_HW_BTRS_LNL_PLL_FREQ 0x00000148u
75#define VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK GENMASK(15, 0)
76
77#define VPU_HW_BTRS_LNL_TILE_FUSE 0x00000150u
78#define VPU_HW_BTRS_LNL_TILE_FUSE_VALID_MASK BIT_MASK(0)
79#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK GENMASK(6, 1)
80
81#define VPU_HW_BTRS_LNL_VPU_STATUS 0x00000154u
82#define VPU_HW_BTRS_LNL_VPU_STATUS_READY_MASK BIT_MASK(0)
83#define VPU_HW_BTRS_LNL_VPU_STATUS_IDLE_MASK BIT_MASK(1)
84#define VPU_HW_BTRS_LNL_VPU_STATUS_DUP_IDLE_MASK BIT_MASK(2)
85#define VPU_HW_BTRS_LNL_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK BIT_MASK(6)
86#define VPU_HW_BTRS_LNL_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK BIT_MASK(7)
87#define VPU_HW_BTRS_LNL_VPU_STATUS_PERF_CLK_MASK BIT_MASK(11)
88#define VPU_HW_BTRS_LNL_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK BIT_MASK(12)
89
90#define VPU_HW_BTRS_LNL_IP_RESET 0x00000160u
91#define VPU_HW_BTRS_LNL_IP_RESET_TRIGGER_MASK BIT_MASK(0)
92
93#define VPU_HW_BTRS_LNL_D0I3_CONTROL 0x00000164u
94#define VPU_HW_BTRS_LNL_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
95#define VPU_HW_BTRS_LNL_D0I3_CONTROL_I3_MASK BIT_MASK(2)
96
97#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_OFFSET 0x00000168u
98#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_SIZE 0x0000016cu
99#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_ENABLE 0x00000170u
100
101#define VPU_HW_BTRS_LNL_FMIN_FUSE 0x00000174u
102#define VPU_HW_BTRS_LNL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
103#define VPU_HW_BTRS_LNL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
104
105#define VPU_HW_BTRS_LNL_FMAX_FUSE 0x00000178u
106#define VPU_HW_BTRS_LNL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
107
108#endif /* __IVPU_HW_BTRS_LNL_REG_H__ */
drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h+83−0
@@ -0,0 +1,83 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020-2023 Intel Corporation
4 */
5
6#ifndef __IVPU_HW_BTRS_MTL_REG_H__
7#define __IVPU_HW_BTRS_MTL_REG_H__
8
9#include <linux/bits.h>
10
11#define VPU_HW_BTRS_MTL_INTERRUPT_TYPE 0x00000000u
12
13#define VPU_HW_BTRS_MTL_INTERRUPT_STAT 0x00000004u
14#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
15#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
16#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_UFI_ERR_MASK BIT_MASK(2)
17
18#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0 0x00000008u
19#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
20#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
21
22#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1 0x0000000cu
23#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
24#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
25
26#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2 0x00000010u
27#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
28
29#define VPU_HW_BTRS_MTL_WP_REQ_CMD 0x00000014u
30#define VPU_HW_BTRS_MTL_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
31
32#define VPU_HW_BTRS_MTL_WP_DOWNLOAD 0x00000018u
33#define VPU_HW_BTRS_MTL_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0)
34
35#define VPU_HW_BTRS_MTL_CURRENT_PLL 0x0000001cu
36#define VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK GENMASK(15, 0)
37
38#define VPU_HW_BTRS_MTL_PLL_ENABLE 0x00000020u
39
40#define VPU_HW_BTRS_MTL_FMIN_FUSE 0x00000024u
41#define VPU_HW_BTRS_MTL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
42#define VPU_HW_BTRS_MTL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
43
44#define VPU_HW_BTRS_MTL_FMAX_FUSE 0x00000028u
45#define VPU_HW_BTRS_MTL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
46
47#define VPU_HW_BTRS_MTL_TILE_FUSE 0x0000002cu
48#define VPU_HW_BTRS_MTL_TILE_FUSE_VALID_MASK BIT_MASK(0)
49#define VPU_HW_BTRS_MTL_TILE_FUSE_SKU_MASK GENMASK(3, 2)
50
51#define VPU_HW_BTRS_MTL_LOCAL_INT_MASK 0x00000030u
52#define VPU_HW_BTRS_MTL_GLOBAL_INT_MASK 0x00000034u
53
54#define VPU_HW_BTRS_MTL_PLL_STATUS 0x00000040u
55#define VPU_HW_BTRS_MTL_PLL_STATUS_LOCK_MASK BIT_MASK(1)
56
57#define VPU_HW_BTRS_MTL_VPU_STATUS 0x00000044u
58#define VPU_HW_BTRS_MTL_VPU_STATUS_READY_MASK BIT_MASK(0)
59#define VPU_HW_BTRS_MTL_VPU_STATUS_IDLE_MASK BIT_MASK(1)
60
61#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL 0x00000060u
62#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
63#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_I3_MASK BIT_MASK(2)
64
65#define VPU_HW_BTRS_MTL_VPU_IP_RESET 0x00000050u
66#define VPU_HW_BTRS_MTL_VPU_IP_RESET_TRIGGER_MASK BIT_MASK(0)
67
68#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET 0x00000080u
69#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE 0x00000084u
70#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE 0x00000088u
71
72#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_0 0x000000a0u
73#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_1 0x000000a4u
74#define VPU_HW_BTRS_MTL_ATS_ERR_CLEAR 0x000000a8u
75
76#define VPU_HW_BTRS_MTL_UFI_ERR_LOG 0x000000b0u
77#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0)
78#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12)
79#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20)
80
81#define VPU_HW_BTRS_MTL_UFI_ERR_CLEAR 0x000000b4u
82
83#endif /* __IVPU_HW_BTRS_MTL_REG_H__ */
drivers/accel/ivpu/ivpu_hw_ip.c+1174−0
@@ -0,0 +1,1174 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6#include "ivpu_drv.h"
7#include "ivpu_fw.h"
8#include "ivpu_hw.h"
9#include "ivpu_hw_37xx_reg.h"
10#include "ivpu_hw_40xx_reg.h"
11#include "ivpu_hw_ip.h"
12#include "ivpu_hw_reg_io.h"
13#include "ivpu_mmu.h"
14#include "ivpu_pm.h"
15
16#define PWR_ISLAND_EN_POST_DLY_FREQ_DEFAULT 0
17#define PWR_ISLAND_EN_POST_DLY_FREQ_HIGH 18
18#define PWR_ISLAND_STATUS_DLY_FREQ_DEFAULT 3
19#define PWR_ISLAND_STATUS_DLY_FREQ_HIGH 46
20#define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC)
21
22#define TIM_SAFE_ENABLE 0xf1d0dead
23#define TIM_WATCHDOG_RESET_VALUE 0xffffffff
24
25#define ICB_0_IRQ_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \
26 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \
27 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \
28 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \
29 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \
30 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \
31 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))
32
33#define ICB_1_IRQ_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \
34 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \
35 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))
36
37#define ICB_0_1_IRQ_MASK_37XX ((((u64)ICB_1_IRQ_MASK_37XX) << 32) | ICB_0_IRQ_MASK_37XX)
38
39#define ICB_0_IRQ_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \
40 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \
41 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \
42 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \
43 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \
44 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \
45 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))
46
47#define ICB_1_IRQ_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \
48 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \
49 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))
50
51#define ICB_0_1_IRQ_MASK_40XX ((((u64)ICB_1_IRQ_MASK_40XX) << 32) | ICB_0_IRQ_MASK_40XX)
52
53#define ITF_FIREWALL_VIOLATION_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \
54 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \
55 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \
56 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \
57 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \
58 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \
59 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))
60
61#define ITF_FIREWALL_VIOLATION_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \
62 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \
63 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \
64 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \
65 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \
66 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \
67 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))
68
69static int wait_for_ip_bar(struct ivpu_device *vdev)
70{
71 return REGV_POLL_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, AON, 0, 100);
72}
73
74static void host_ss_rst_clr(struct ivpu_device *vdev)
75{
76 u32 val = 0;
77
78 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val);
79 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val);
80 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val);
81
82 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val);
83}
84
85static int host_ss_noc_qreqn_check_37xx(struct ivpu_device *vdev, u32 exp_val)
86{
87 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);
88
89 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val))
90 return -EIO;
91
92 return 0;
93}
94
95static int host_ss_noc_qreqn_check_40xx(struct ivpu_device *vdev, u32 exp_val)
96{
97 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
98
99 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val))
100 return -EIO;
101
102 return 0;
103}
104
105static int host_ss_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val)
106{
107 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
108 return host_ss_noc_qreqn_check_37xx(vdev, exp_val);
109 else
110 return host_ss_noc_qreqn_check_40xx(vdev, exp_val);
111}
112
113static int host_ss_noc_qacceptn_check_37xx(struct ivpu_device *vdev, u32 exp_val)
114{
115 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN);
116
117 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val))
118 return -EIO;
119
120 return 0;
121}
122
123static int host_ss_noc_qacceptn_check_40xx(struct ivpu_device *vdev, u32 exp_val)
124{
125 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN);
126
127 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val))
128 return -EIO;
129
130 return 0;
131}
132
133static int host_ss_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
134{
135 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
136 return host_ss_noc_qacceptn_check_37xx(vdev, exp_val);
137 else
138 return host_ss_noc_qacceptn_check_40xx(vdev, exp_val);
139}
140
141static int host_ss_noc_qdeny_check_37xx(struct ivpu_device *vdev, u32 exp_val)
142{
143 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY);
144
145 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val))
146 return -EIO;
147
148 return 0;
149}
150
151static int host_ss_noc_qdeny_check_40xx(struct ivpu_device *vdev, u32 exp_val)
152{
153 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY);
154
155 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val))
156 return -EIO;
157
158 return 0;
159}
160
161static int host_ss_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
162{
163 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
164 return host_ss_noc_qdeny_check_37xx(vdev, exp_val);
165 else
166 return host_ss_noc_qdeny_check_40xx(vdev, exp_val);
167}
168
169static int top_noc_qrenqn_check_37xx(struct ivpu_device *vdev, u32 exp_val)
170{
171 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);
172
173 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) ||
174 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val))
175 return -EIO;
176
177 return 0;
178}
179
180static int top_noc_qrenqn_check_40xx(struct ivpu_device *vdev, u32 exp_val)
181{
182 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
183
184 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) ||
185 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val))
186 return -EIO;
187
188 return 0;
189}
190
191static int top_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val)
192{
193 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
194 return top_noc_qrenqn_check_37xx(vdev, exp_val);
195 else
196 return top_noc_qrenqn_check_40xx(vdev, exp_val);
197}
198
199int ivpu_hw_ip_host_ss_configure(struct ivpu_device *vdev)
200{
201 int ret;
202
203 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
204 ret = wait_for_ip_bar(vdev);
205 if (ret) {
206 ivpu_err(vdev, "Timed out waiting for NPU IP bar\n");
207 return ret;
208 }
209 host_ss_rst_clr(vdev);
210 }
211
212 ret = host_ss_noc_qreqn_check(vdev, 0x0);
213 if (ret) {
214 ivpu_err(vdev, "Failed qreqn check: %d\n", ret);
215 return ret;
216 }
217
218 ret = host_ss_noc_qacceptn_check(vdev, 0x0);
219 if (ret) {
220 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
221 return ret;
222 }
223
224 ret = host_ss_noc_qdeny_check(vdev, 0x0);
225 if (ret)
226 ivpu_err(vdev, "Failed qdeny check %d\n", ret);
227
228 return ret;
229}
230
231static void idle_gen_drive_37xx(struct ivpu_device *vdev, bool enable)
232{
233 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN);
234
235 if (enable)
236 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val);
237 else
238 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val);
239
240 REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, val);
241}
242
243static void idle_gen_drive_40xx(struct ivpu_device *vdev, bool enable)
244{
245 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN);
246
247 if (enable)
248 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
249 else
250 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
251
252 REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val);
253}
254
255void ivpu_hw_ip_idle_gen_enable(struct ivpu_device *vdev)
256{
257 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
258 idle_gen_drive_37xx(vdev, true);
259 else
260 idle_gen_drive_40xx(vdev, true);
261}
262
263void ivpu_hw_ip_idle_gen_disable(struct ivpu_device *vdev)
264{
265 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
266 idle_gen_drive_37xx(vdev, false);
267 else
268 idle_gen_drive_40xx(vdev, false);
269}
270
271static void pwr_island_delay_set_50xx(struct ivpu_device *vdev)
272{
273 u32 val, post, status;
274
275 if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT) {
276 post = PWR_ISLAND_EN_POST_DLY_FREQ_DEFAULT;
277 status = PWR_ISLAND_STATUS_DLY_FREQ_DEFAULT;
278 } else {
279 post = PWR_ISLAND_EN_POST_DLY_FREQ_HIGH;
280 status = PWR_ISLAND_STATUS_DLY_FREQ_HIGH;
281 }
282
283 val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY);
284 val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST_DLY, post, val);
285 REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, val);
286
287 val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY);
288 val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, STATUS_DLY, status, val);
289 REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, val);
290}
291
292static void pwr_island_trickle_drive_37xx(struct ivpu_device *vdev, bool enable)
293{
294 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
295
296 if (enable)
297 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val);
298 else
299 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val);
300
301 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
302}
303
304static void pwr_island_trickle_drive_40xx(struct ivpu_device *vdev, bool enable)
305{
306 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
307
308 if (enable)
309 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
310 else
311 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
312
313 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
314
315 if (enable)
316 ndelay(500);
317}
318
319static void pwr_island_drive_37xx(struct ivpu_device *vdev, bool enable)
320{
321 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
322
323 if (enable)
324 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
325 else
326 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
327
328 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
329
330 if (!enable)
331 ndelay(500);
332}
333
334static void pwr_island_drive_40xx(struct ivpu_device *vdev, bool enable)
335{
336 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0);
337
338 if (enable)
339 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
340 else
341 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
342
343 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
344}
345
346static void pwr_island_enable(struct ivpu_device *vdev)
347{
348 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
349 pwr_island_trickle_drive_37xx(vdev, true);
350 pwr_island_drive_37xx(vdev, true);
351 } else {
352 pwr_island_trickle_drive_40xx(vdev, true);
353 pwr_island_drive_40xx(vdev, true);
354 }
355}
356
357static int wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val)
358{
359 if (IVPU_WA(punit_disabled))
360 return 0;
361
362 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
363 return REGV_POLL_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0, MSS_CPU, exp_val,
364 PWR_ISLAND_STATUS_TIMEOUT_US);
365 else
366 return REGV_POLL_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0, CSS_CPU, exp_val,
367 PWR_ISLAND_STATUS_TIMEOUT_US);
368}
369
370static void pwr_island_isolation_drive_37xx(struct ivpu_device *vdev, bool enable)
371{
372 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0);
373
374 if (enable)
375 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val);
376 else
377 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val);
378
379 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val);
380}
381
382static void pwr_island_isolation_drive_40xx(struct ivpu_device *vdev, bool enable)
383{
384 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0);
385
386 if (enable)
387 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
388 else
389 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
390
391 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val);
392}
393
394static void pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable)
395{
396 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
397 pwr_island_isolation_drive_37xx(vdev, enable);
398 else
399 pwr_island_isolation_drive_40xx(vdev, enable);
400}
401
402static void pwr_island_isolation_disable(struct ivpu_device *vdev)
403{
404 pwr_island_isolation_drive(vdev, false);
405}
406
407static void host_ss_clk_drive_37xx(struct ivpu_device *vdev, bool enable)
408{
409 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET);
410
411 if (enable) {
412 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val);
413 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val);
414 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val);
415 } else {
416 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val);
417 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val);
418 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val);
419 }
420
421 REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val);
422}
423
424static void host_ss_clk_drive_40xx(struct ivpu_device *vdev, bool enable)
425{
426 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN);
427
428 if (enable) {
429 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
430 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
431 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
432 } else {
433 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
434 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
435 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
436 }
437
438 REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val);
439}
440
441static void host_ss_clk_drive(struct ivpu_device *vdev, bool enable)
442{
443 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
444 host_ss_clk_drive_37xx(vdev, enable);
445 else
446 host_ss_clk_drive_40xx(vdev, enable);
447}
448
449static void host_ss_clk_enable(struct ivpu_device *vdev)
450{
451 host_ss_clk_drive(vdev, true);
452}
453
454static void host_ss_rst_drive_37xx(struct ivpu_device *vdev, bool enable)
455{
456 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET);
457
458 if (enable) {
459 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val);
460 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val);
461 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val);
462 } else {
463 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val);
464 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val);
465 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val);
466 }
467
468 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val);
469}
470
471static void host_ss_rst_drive_40xx(struct ivpu_device *vdev, bool enable)
472{
473 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN);
474
475 if (enable) {
476 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
477 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
478 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
479 } else {
480 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
481 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
482 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
483 }
484
485 REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val);
486}
487
488static void host_ss_rst_drive(struct ivpu_device *vdev, bool enable)
489{
490 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
491 host_ss_rst_drive_37xx(vdev, enable);
492 else
493 host_ss_rst_drive_40xx(vdev, enable);
494}
495
496static void host_ss_rst_enable(struct ivpu_device *vdev)
497{
498 host_ss_rst_drive(vdev, true);
499}
500
501static void host_ss_noc_qreqn_top_socmmio_drive_37xx(struct ivpu_device *vdev, bool enable)
502{
503 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);
504
505 if (enable)
506 val = REG_SET_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
507 else
508 val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
509 REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val);
510}
511
512static void host_ss_noc_qreqn_top_socmmio_drive_40xx(struct ivpu_device *vdev, bool enable)
513{
514 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
515
516 if (enable)
517 val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
518 else
519 val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
520 REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val);
521}
522
523static void host_ss_noc_qreqn_top_socmmio_drive(struct ivpu_device *vdev, bool enable)
524{
525 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
526 host_ss_noc_qreqn_top_socmmio_drive_37xx(vdev, enable);
527 else
528 host_ss_noc_qreqn_top_socmmio_drive_40xx(vdev, enable);
529}
530
531static int host_ss_axi_drive(struct ivpu_device *vdev, bool enable)
532{
533 int ret;
534
535 host_ss_noc_qreqn_top_socmmio_drive(vdev, enable);
536
537 ret = host_ss_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
538 if (ret) {
539 ivpu_err(vdev, "Failed HOST SS NOC QACCEPTN check: %d\n", ret);
540 return ret;
541 }
542
543 ret = host_ss_noc_qdeny_check(vdev, 0x0);
544 if (ret)
545 ivpu_err(vdev, "Failed HOST SS NOC QDENY check: %d\n", ret);
546
547 return ret;
548}
549
550static void top_noc_qreqn_drive_40xx(struct ivpu_device *vdev, bool enable)
551{
552 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
553
554 if (enable) {
555 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
556 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
557 } else {
558 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
559 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
560 }
561
562 REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val);
563}
564
565static void top_noc_qreqn_drive_37xx(struct ivpu_device *vdev, bool enable)
566{
567 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);
568
569 if (enable) {
570 val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
571 val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
572 } else {
573 val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
574 val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
575 }
576
577 REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val);
578}
579
580static void top_noc_qreqn_drive(struct ivpu_device *vdev, bool enable)
581{
582 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
583 top_noc_qreqn_drive_37xx(vdev, enable);
584 else
585 top_noc_qreqn_drive_40xx(vdev, enable);
586}
587
588int ivpu_hw_ip_host_ss_axi_enable(struct ivpu_device *vdev)
589{
590 return host_ss_axi_drive(vdev, true);
591}
592
593static int top_noc_qacceptn_check_37xx(struct ivpu_device *vdev, u32 exp_val)
594{
595 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN);
596
597 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
598 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
599 return -EIO;
600
601 return 0;
602}
603
604static int top_noc_qacceptn_check_40xx(struct ivpu_device *vdev, u32 exp_val)
605{
606 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN);
607
608 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
609 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
610 return -EIO;
611
612 return 0;
613}
614
615static int top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
616{
617 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
618 return top_noc_qacceptn_check_37xx(vdev, exp_val);
619 else
620 return top_noc_qacceptn_check_40xx(vdev, exp_val);
621}
622
623static int top_noc_qdeny_check_37xx(struct ivpu_device *vdev, u32 exp_val)
624{
625 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY);
626
627 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
628 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
629 return -EIO;
630
631 return 0;
632}
633
634static int top_noc_qdeny_check_40xx(struct ivpu_device *vdev, u32 exp_val)
635{
636 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY);
637
638 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
639 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
640 return -EIO;
641
642 return 0;
643}
644
645static int top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
646{
647 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
648 return top_noc_qdeny_check_37xx(vdev, exp_val);
649 else
650 return top_noc_qdeny_check_40xx(vdev, exp_val);
651}
652
653static int top_noc_drive(struct ivpu_device *vdev, bool enable)
654{
655 int ret;
656
657 top_noc_qreqn_drive(vdev, enable);
658
659 ret = top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
660 if (ret) {
661 ivpu_err(vdev, "Failed TOP NOC QACCEPTN check: %d\n", ret);
662 return ret;
663 }
664
665 ret = top_noc_qdeny_check(vdev, 0x0);
666 if (ret)
667 ivpu_err(vdev, "Failed TOP NOC QDENY check: %d\n", ret);
668
669 return ret;
670}
671
672int ivpu_hw_ip_top_noc_enable(struct ivpu_device *vdev)
673{
674 return top_noc_drive(vdev, true);
675}
676
677static void dpu_active_drive_37xx(struct ivpu_device *vdev, bool enable)
678{
679 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE);
680
681 if (enable)
682 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val);
683 else
684 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val);
685
686 REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val);
687}
688
689int ivpu_hw_ip_pwr_domain_enable(struct ivpu_device *vdev)
690{
691 int ret;
692
693 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_50XX)
694 pwr_island_delay_set_50xx(vdev);
695
696 pwr_island_enable(vdev);
697
698 ret = wait_for_pwr_island_status(vdev, 0x1);
699 if (ret) {
700 ivpu_err(vdev, "Timed out waiting for power island status\n");
701 return ret;
702 }
703
704 ret = top_noc_qreqn_check(vdev, 0x0);
705 if (ret) {
706 ivpu_err(vdev, "Failed TOP NOC QREQN check %d\n", ret);
707 return ret;
708 }
709
710 host_ss_clk_enable(vdev);
711 pwr_island_isolation_disable(vdev);
712 host_ss_rst_enable(vdev);
713
714 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
715 dpu_active_drive_37xx(vdev, true);
716
717 return ret;
718}
719
720u64 ivpu_hw_ip_read_perf_timer_counter(struct ivpu_device *vdev)
721{
722 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
723 return REGV_RD64(VPU_37XX_CPU_SS_TIM_PERF_FREE_CNT);
724 else
725 return REGV_RD64(VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT);
726}
727
728static void ivpu_hw_ip_snoop_disable_37xx(struct ivpu_device *vdev)
729{
730 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);
731
732 val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val);
733 val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val);
734
735 if (ivpu_is_force_snoop_enabled(vdev))
736 val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val);
737 else
738 val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val);
739
740 REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val);
741}
742
743static void ivpu_hw_ip_snoop_disable_40xx(struct ivpu_device *vdev)
744{
745 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);
746
747 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val);
748 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);
749
750 if (ivpu_is_force_snoop_enabled(vdev))
751 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);
752 else
753 val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);
754
755 REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val);
756}
757
758void ivpu_hw_ip_snoop_disable(struct ivpu_device *vdev)
759{
760 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
761 return ivpu_hw_ip_snoop_disable_37xx(vdev);
762 else
763 return ivpu_hw_ip_snoop_disable_40xx(vdev);
764}
765
766static void ivpu_hw_ip_tbu_mmu_enable_37xx(struct ivpu_device *vdev)
767{
768 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV);
769
770 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);
771 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);
772 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);
773 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);
774
775 REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val);
776}
777
778static void ivpu_hw_ip_tbu_mmu_enable_40xx(struct ivpu_device *vdev)
779{
780 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV);
781
782 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);
783 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);
784 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val);
785 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val);
786 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);
787 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);
788
789 REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val);
790}
791
792void ivpu_hw_ip_tbu_mmu_enable(struct ivpu_device *vdev)
793{
794 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
795 return ivpu_hw_ip_tbu_mmu_enable_37xx(vdev);
796 else
797 return ivpu_hw_ip_tbu_mmu_enable_40xx(vdev);
798}
799
800static int soc_cpu_boot_37xx(struct ivpu_device *vdev)
801{
802 u32 val;
803
804 val = REGV_RD32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC);
805 val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTRUN0, val);
806
807 val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val);
808 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
809
810 val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val);
811 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
812
813 val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val);
814 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
815
816 val = vdev->fw->entry_point >> 9;
817 REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);
818
819 val = REG_SET_FLD(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, DONE, val);
820 REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);
821
822 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
823 vdev->fw->entry_point == vdev->fw->cold_boot_entry_point ? "cold boot" : "resume");
824
825 return 0;
826}
827
828static int cpu_noc_qacceptn_check_40xx(struct ivpu_device *vdev, u32 exp_val)
829{
830 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN);
831
832 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN, TOP_MMIO, exp_val, val))
833 return -EIO;
834
835 return 0;
836}
837
838static int cpu_noc_qdeny_check_40xx(struct ivpu_device *vdev, u32 exp_val)
839{
840 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY);
841
842 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QDENY, TOP_MMIO, exp_val, val))
843 return -EIO;
844
845 return 0;
846}
847
848static void cpu_noc_top_mmio_drive_40xx(struct ivpu_device *vdev, bool enable)
849{
850 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN);
851
852 if (enable)
853 val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
854 else
855 val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
856 REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val);
857}
858
859static int soc_cpu_drive_40xx(struct ivpu_device *vdev, bool enable)
860{
861 int ret;
862
863 cpu_noc_top_mmio_drive_40xx(vdev, enable);
864
865 ret = cpu_noc_qacceptn_check_40xx(vdev, enable ? 0x1 : 0x0);
866 if (ret) {
867 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
868 return ret;
869 }
870
871 ret = cpu_noc_qdeny_check_40xx(vdev, 0x0);
872 if (ret)
873 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
874
875 return ret;
876}
877
878static int soc_cpu_enable(struct ivpu_device *vdev)
879{
880 return soc_cpu_drive_40xx(vdev, true);
881}
882
883static int soc_cpu_boot_40xx(struct ivpu_device *vdev)
884{
885 int ret;
886 u32 val;
887 u64 val64;
888
889 ret = soc_cpu_enable(vdev);
890 if (ret) {
891 ivpu_err(vdev, "Failed to enable SOC CPU: %d\n", ret);
892 return ret;
893 }
894
895 val64 = vdev->fw->entry_point;
896 val64 <<= ffs(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK) - 1;
897 REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64);
898
899 val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO);
900 val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val);
901 REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val);
902
903 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
904 ivpu_fw_is_cold_boot(vdev) ? "cold boot" : "resume");
905
906 return 0;
907}
908
909int ivpu_hw_ip_soc_cpu_boot(struct ivpu_device *vdev)
910{
911 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
912 return soc_cpu_boot_37xx(vdev);
913 else
914 return soc_cpu_boot_40xx(vdev);
915}
916
917static void wdt_disable_37xx(struct ivpu_device *vdev)
918{
919 u32 val;
920
921 /* Enable writing and set non-zero WDT value */
922 REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
923 REGV_WR32(VPU_37XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);
924
925 /* Enable writing and disable watchdog timer */
926 REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
927 REGV_WR32(VPU_37XX_CPU_SS_TIM_WDOG_EN, 0);
928
929 /* Now clear the timeout interrupt */
930 val = REGV_RD32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG);
931 val = REG_CLR_FLD(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);
932 REGV_WR32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, val);
933}
934
935static void wdt_disable_40xx(struct ivpu_device *vdev)
936{
937 u32 val;
938
939 REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
940 REGV_WR32(VPU_40XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);
941
942 REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
943 REGV_WR32(VPU_40XX_CPU_SS_TIM_WDOG_EN, 0);
944
945 val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG);
946 val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);
947 REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val);
948}
949
950void ivpu_hw_ip_wdt_disable(struct ivpu_device *vdev)
951{
952 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
953 return wdt_disable_37xx(vdev);
954 else
955 return wdt_disable_40xx(vdev);
956}
957
958static u32 ipc_rx_count_get_37xx(struct ivpu_device *vdev)
959{
960 u32 count = REGV_RD32_SILENT(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT);
961
962 return REG_GET_FLD(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count);
963}
964
965static u32 ipc_rx_count_get_40xx(struct ivpu_device *vdev)
966{
967 u32 count = REGV_RD32_SILENT(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT);
968
969 return REG_GET_FLD(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count);
970}
971
972u32 ivpu_hw_ip_ipc_rx_count_get(struct ivpu_device *vdev)
973{
974 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
975 return ipc_rx_count_get_37xx(vdev);
976 else
977 return ipc_rx_count_get_40xx(vdev);
978}
979
980void ivpu_hw_ip_irq_enable(struct ivpu_device *vdev)
981{
982 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
983 REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK_37XX);
984 REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK_37XX);
985 } else {
986 REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK_40XX);
987 REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK_40XX);
988 }
989}
990
991void ivpu_hw_ip_irq_disable(struct ivpu_device *vdev)
992{
993 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
994 REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull);
995 REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0);
996 } else {
997 REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, 0x0ull);
998 REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, 0x0ul);
999 }
1000}
1001
1002static void diagnose_failure_37xx(struct ivpu_device *vdev)
1003{
1004 u32 reg = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX;
1005
1006 if (ipc_rx_count_get_37xx(vdev))
1007 ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
1008
1009 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, reg))
1010 ivpu_err(vdev, "WDT MSS timeout detected\n");
1011
1012 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, reg))
1013 ivpu_err(vdev, "WDT NCE timeout detected\n");
1014
1015 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, reg))
1016 ivpu_err(vdev, "NOC Firewall irq detected\n");
1017}
1018
1019static void diagnose_failure_40xx(struct ivpu_device *vdev)
1020{
1021 u32 reg = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX;
1022
1023 if (ipc_rx_count_get_40xx(vdev))
1024 ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
1025
1026 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, reg))
1027 ivpu_err(vdev, "WDT MSS timeout detected\n");
1028
1029 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, reg))
1030 ivpu_err(vdev, "WDT NCE timeout detected\n");
1031
1032 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, reg))
1033 ivpu_err(vdev, "NOC Firewall irq detected\n");
1034}
1035
1036void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev)
1037{
1038 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
1039 diagnose_failure_37xx(vdev);
1040 else
1041 diagnose_failure_40xx(vdev);
1042}
1043
1044void ivpu_hw_ip_irq_clear(struct ivpu_device *vdev)
1045{
1046 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
1047 REGV_WR64(VPU_37XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK_37XX);
1048 else
1049 REGV_WR64(VPU_40XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK_40XX);
1050}
1051
1052static void irq_wdt_nce_handler(struct ivpu_device *vdev)
1053{
1054 ivpu_pm_trigger_recovery(vdev, "WDT NCE IRQ");
1055}
1056
1057static void irq_wdt_mss_handler(struct ivpu_device *vdev)
1058{
1059 ivpu_hw_ip_wdt_disable(vdev);
1060 ivpu_pm_trigger_recovery(vdev, "WDT MSS IRQ");
1061}
1062
1063static void irq_noc_firewall_handler(struct ivpu_device *vdev)
1064{
1065 ivpu_pm_trigger_recovery(vdev, "NOC Firewall IRQ");
1066}
1067
1068/* Handler for IRQs from NPU core */
1069bool ivpu_hw_ip_irq_handler_37xx(struct ivpu_device *vdev, int irq)
1070{
1071 u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX;
1072
1073 if (!status)
1074 return false;
1075
1076 REGV_WR32(VPU_37XX_HOST_SS_ICB_CLEAR_0, status);
1077
1078 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status))
1079 ivpu_mmu_irq_evtq_handler(vdev);
1080
1081 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status))
1082 ivpu_ipc_irq_handler(vdev);
1083
1084 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status))
1085 ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
1086
1087 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status))
1088 ivpu_mmu_irq_gerr_handler(vdev);
1089
1090 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status))
1091 irq_wdt_mss_handler(vdev);
1092
1093 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status))
1094 irq_wdt_nce_handler(vdev);
1095
1096 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status))
1097 irq_noc_firewall_handler(vdev);
1098
1099 return true;
1100}
1101
1102/* Handler for IRQs from NPU core */
1103bool ivpu_hw_ip_irq_handler_40xx(struct ivpu_device *vdev, int irq)
1104{
1105 u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX;
1106
1107 if (!status)
1108 return false;
1109
1110 REGV_WR32(VPU_40XX_HOST_SS_ICB_CLEAR_0, status);
1111
1112 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status))
1113 ivpu_mmu_irq_evtq_handler(vdev);
1114
1115 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status))
1116 ivpu_ipc_irq_handler(vdev);
1117
1118 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status))
1119 ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
1120
1121 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status))
1122 ivpu_mmu_irq_gerr_handler(vdev);
1123
1124 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status))
1125 irq_wdt_mss_handler(vdev);
1126
1127 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status))
1128 irq_wdt_nce_handler(vdev);
1129
1130 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status))
1131 irq_noc_firewall_handler(vdev);
1132
1133 return true;
1134}
1135
1136static void db_set_37xx(struct ivpu_device *vdev, u32 db_id)
1137{
1138 u32 reg_stride = VPU_37XX_CPU_SS_DOORBELL_1 - VPU_37XX_CPU_SS_DOORBELL_0;
1139 u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET);
1140
1141 REGV_WR32I(VPU_37XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val);
1142}
1143
1144static void db_set_40xx(struct ivpu_device *vdev, u32 db_id)
1145{
1146 u32 reg_stride = VPU_40XX_CPU_SS_DOORBELL_1 - VPU_40XX_CPU_SS_DOORBELL_0;
1147 u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET);
1148
1149 REGV_WR32I(VPU_40XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val);
1150}
1151
1152void ivpu_hw_ip_db_set(struct ivpu_device *vdev, u32 db_id)
1153{
1154 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
1155 db_set_37xx(vdev, db_id);
1156 else
1157 db_set_40xx(vdev, db_id);
1158}
1159
1160u32 ivpu_hw_ip_ipc_rx_addr_get(struct ivpu_device *vdev)
1161{
1162 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
1163 return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM);
1164 else
1165 return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM);
1166}
1167
1168void ivpu_hw_ip_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
1169{
1170 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
1171 REGV_WR32(VPU_37XX_CPU_SS_TIM_IPC_FIFO, vpu_addr);
1172 else
1173 REGV_WR32(VPU_40XX_CPU_SS_TIM_IPC_FIFO, vpu_addr);
1174}
drivers/accel/ivpu/ivpu_hw_ip.h+36−0
@@ -0,0 +1,36 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6#ifndef __IVPU_HW_IP_H__
7#define __IVPU_HW_IP_H__
8
9#include "ivpu_drv.h"
10
11int ivpu_hw_ip_host_ss_configure(struct ivpu_device *vdev);
12void ivpu_hw_ip_idle_gen_enable(struct ivpu_device *vdev);
13void ivpu_hw_ip_idle_gen_disable(struct ivpu_device *vdev);
14int ivpu_hw_ip_pwr_domain_enable(struct ivpu_device *vdev);
15int ivpu_hw_ip_host_ss_axi_enable(struct ivpu_device *vdev);
16int ivpu_hw_ip_top_noc_enable(struct ivpu_device *vdev);
17u64 ivpu_hw_ip_read_perf_timer_counter(struct ivpu_device *vdev);
18void ivpu_hw_ip_snoop_disable(struct ivpu_device *vdev);
19void ivpu_hw_ip_tbu_mmu_enable(struct ivpu_device *vdev);
20int ivpu_hw_ip_soc_cpu_boot(struct ivpu_device *vdev);
21void ivpu_hw_ip_wdt_disable(struct ivpu_device *vdev);
22void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev);
23u32 ivpu_hw_ip_ipc_rx_count_get(struct ivpu_device *vdev);
24void ivpu_hw_ip_irq_clear(struct ivpu_device *vdev);
25bool ivpu_hw_ip_irq_handler_37xx(struct ivpu_device *vdev, int irq);
26bool ivpu_hw_ip_irq_handler_40xx(struct ivpu_device *vdev, int irq);
27void ivpu_hw_ip_db_set(struct ivpu_device *vdev, u32 db_id);
28u32 ivpu_hw_ip_ipc_rx_addr_get(struct ivpu_device *vdev);
29void ivpu_hw_ip_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr);
30void ivpu_hw_ip_irq_enable(struct ivpu_device *vdev);
31void ivpu_hw_ip_irq_disable(struct ivpu_device *vdev);
32void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev);
33void ivpu_hw_ip_fabric_req_override_enable_50xx(struct ivpu_device *vdev);
34void ivpu_hw_ip_fabric_req_override_disable_50xx(struct ivpu_device *vdev);
35
36#endif /* __IVPU_HW_IP_H__ */
drivers/accel/ivpu/ivpu_ipc.c+9−11
@@ -129,7 +129,7 @@ static void ivpu_ipc_tx_release(struct ivpu_device *vdev, u32 vpu_addr) · 128 unmodified lines
129 129
130static void ivpu_ipc_tx(struct ivpu_device *vdev, u32 vpu_addr)130static void ivpu_ipc_tx(struct ivpu_device *vdev, u32 vpu_addr)
131{131{
132 ivpu_hw_reg_ipc_tx_set(vdev, vpu_addr);132 ivpu_hw_ipc_tx_set(vdev, vpu_addr);
133}133}
134 134
135static void135static void
@@ -210,8 +210,7 @@ void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *c · 74 unmodified lines
210 ivpu_ipc_tx_release(vdev, cons->tx_vpu_addr);210 ivpu_ipc_tx_release(vdev, cons->tx_vpu_addr);
211}211}
212 212
213static int213int ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, struct vpu_jsm_msg *req)
214ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, struct vpu_jsm_msg *req)
215{214{
216 struct ivpu_ipc_info *ipc = vdev->ipc;215 struct ivpu_ipc_info *ipc = vdev->ipc;
217 int ret;216 int ret;
@@ -378,7 +377,7 @@ ivpu_ipc_match_consumer(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons · 160 unmodified lines
378 return false;377 return false;
379}378}
380 379
381void ivpu_ipc_irq_handler(struct ivpu_device *vdev, bool *wake_thread)380void ivpu_ipc_irq_handler(struct ivpu_device *vdev)
382{381{
383 struct ivpu_ipc_info *ipc = vdev->ipc;382 struct ivpu_ipc_info *ipc = vdev->ipc;
384 struct ivpu_ipc_consumer *cons;383 struct ivpu_ipc_consumer *cons;
@@ -392,8 +391,8 @@ void ivpu_ipc_irq_handler(struct ivpu_device *vdev, bool *wake_thread) · 7 unmodified lines
392 * Driver needs to purge all messages from IPC FIFO to clear IPC interrupt.391 * Driver needs to purge all messages from IPC FIFO to clear IPC interrupt.
393 * Without purge IPC FIFO to 0 next IPC interrupts won't be generated.392 * Without purge IPC FIFO to 0 next IPC interrupts won't be generated.
394 */393 */
395 while (ivpu_hw_reg_ipc_rx_count_get(vdev)) {394 while (ivpu_hw_ipc_rx_count_get(vdev)) {
396 vpu_addr = ivpu_hw_reg_ipc_rx_addr_get(vdev);395 vpu_addr = ivpu_hw_ipc_rx_addr_get(vdev);
397 if (vpu_addr == REG_IO_ERROR) {396 if (vpu_addr == REG_IO_ERROR) {
398 ivpu_err_ratelimited(vdev, "Failed to read IPC rx addr register\n");397 ivpu_err_ratelimited(vdev, "Failed to read IPC rx addr register\n");
399 return;398 return;
@@ -442,11 +441,12 @@ void ivpu_ipc_irq_handler(struct ivpu_device *vdev, bool *wake_thread) · 42 unmodified lines
442 }441 }
443 }442 }
444 443
445 if (wake_thread)444 if (!list_empty(&ipc->cb_msg_list))
446 *wake_thread = !list_empty(&ipc->cb_msg_list);445 if (!kfifo_put(&vdev->hw->irq.fifo, IVPU_HW_IRQ_SRC_IPC))
446 ivpu_err_ratelimited(vdev, "IRQ FIFO full\n");
447}447}
448 448
449irqreturn_t ivpu_ipc_irq_thread_handler(struct ivpu_device *vdev)449void ivpu_ipc_irq_thread_handler(struct ivpu_device *vdev)
450{450{
451 struct ivpu_ipc_info *ipc = vdev->ipc;451 struct ivpu_ipc_info *ipc = vdev->ipc;
452 struct ivpu_ipc_rx_msg *rx_msg, *r;452 struct ivpu_ipc_rx_msg *rx_msg, *r;
@@ -462,8 +462,6 @@ irqreturn_t ivpu_ipc_irq_thread_handler(struct ivpu_device *vdev) · 9 unmodified lines
462 rx_msg->callback(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg);462 rx_msg->callback(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg);
463 ivpu_ipc_rx_msg_del(vdev, rx_msg);463 ivpu_ipc_rx_msg_del(vdev, rx_msg);
464 }464 }
465
466 return IRQ_HANDLED;
467}465}
468 466
469int ivpu_ipc_init(struct ivpu_device *vdev)467int ivpu_ipc_init(struct ivpu_device *vdev)
drivers/accel/ivpu/ivpu_ipc.h+5−3
@@ -1,6 +1,6 @@
1/* SPDX-License-Identifier: GPL-2.0-only */1/* SPDX-License-Identifier: GPL-2.0-only */
2/*2/*
3 * Copyright (C) 2020-2023 Intel Corporation3 * Copyright (C) 2020-2024 Intel Corporation
4 */4 */
5 5
6#ifndef __IVPU_IPC_H__6#ifndef __IVPU_IPC_H__
@@ -89,13 +89,15 @@ void ivpu_ipc_enable(struct ivpu_device *vdev); · 82 unmodified lines
89void ivpu_ipc_disable(struct ivpu_device *vdev);89void ivpu_ipc_disable(struct ivpu_device *vdev);
90void ivpu_ipc_reset(struct ivpu_device *vdev);90void ivpu_ipc_reset(struct ivpu_device *vdev);
91 91
92void ivpu_ipc_irq_handler(struct ivpu_device *vdev, bool *wake_thread);92void ivpu_ipc_irq_handler(struct ivpu_device *vdev);
93irqreturn_t ivpu_ipc_irq_thread_handler(struct ivpu_device *vdev);93void ivpu_ipc_irq_thread_handler(struct ivpu_device *vdev);
94 94
95void ivpu_ipc_consumer_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,95void ivpu_ipc_consumer_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
96 u32 channel, ivpu_ipc_rx_callback_t callback);96 u32 channel, ivpu_ipc_rx_callback_t callback);
97void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons);97void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons);
98 98
99int ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
100 struct vpu_jsm_msg *req);
99int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,101int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
100 struct ivpu_ipc_hdr *ipc_buf, struct vpu_jsm_msg *jsm_msg,102 struct ivpu_ipc_hdr *ipc_buf, struct vpu_jsm_msg *jsm_msg,
101 unsigned long timeout_ms);103 unsigned long timeout_ms);
drivers/accel/ivpu/ivpu_job.c+263−61
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0-only1// SPDX-License-Identifier: GPL-2.0-only
2/*2/*
3 * Copyright (C) 2020-2023 Intel Corporation3 * Copyright (C) 2020-2024 Intel Corporation
4 */4 */
5 5
6#include <drm/drm_file.h>6#include <drm/drm_file.h>
@@ -12,11 +12,13 @@ · 5 unmodified lines
12#include <uapi/drm/ivpu_accel.h>12#include <uapi/drm/ivpu_accel.h>
13 13
14#include "ivpu_drv.h"14#include "ivpu_drv.h"
15#include "ivpu_fw.h"
15#include "ivpu_hw.h"16#include "ivpu_hw.h"
16#include "ivpu_ipc.h"17#include "ivpu_ipc.h"
17#include "ivpu_job.h"18#include "ivpu_job.h"
18#include "ivpu_jsm_msg.h"19#include "ivpu_jsm_msg.h"
19#include "ivpu_pm.h"20#include "ivpu_pm.h"
21#include "vpu_boot_api.h"
20 22
21#define CMD_BUF_IDX 023#define CMD_BUF_IDX 0
22#define JOB_ID_JOB_MASK GENMASK(7, 0)24#define JOB_ID_JOB_MASK GENMASK(7, 0)
@@ -25,14 +27,60 @@ · 2 unmodified lines
25 27
26static void ivpu_cmdq_ring_db(struct ivpu_device *vdev, struct ivpu_cmdq *cmdq)28static void ivpu_cmdq_ring_db(struct ivpu_device *vdev, struct ivpu_cmdq *cmdq)
27{29{
28 ivpu_hw_reg_db_set(vdev, cmdq->db_id);30 ivpu_hw_db_set(vdev, cmdq->db_id);
29}31}
30 32
31static struct ivpu_cmdq *ivpu_cmdq_alloc(struct ivpu_file_priv *file_priv, u16 engine)33static int ivpu_preemption_buffers_create(struct ivpu_device *vdev,
34 struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
35{
36 u64 primary_size = ALIGN(vdev->fw->primary_preempt_buf_size, PAGE_SIZE);
37 u64 secondary_size = ALIGN(vdev->fw->secondary_preempt_buf_size, PAGE_SIZE);
38 struct ivpu_addr_range range;
39
40 if (vdev->hw->sched_mode != VPU_SCHEDULING_MODE_HW)
41 return 0;
42
43 range.start = vdev->hw->ranges.user.end - (primary_size * IVPU_NUM_CMDQS_PER_CTX);
44 range.end = vdev->hw->ranges.user.end;
45 cmdq->primary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &range, primary_size,
46 DRM_IVPU_BO_WC);
47 if (!cmdq->primary_preempt_buf) {
48 ivpu_err(vdev, "Failed to create primary preemption buffer\n");
49 return -ENOMEM;
50 }
51
52 range.start = vdev->hw->ranges.shave.end - (secondary_size * IVPU_NUM_CMDQS_PER_CTX);
53 range.end = vdev->hw->ranges.shave.end;
54 cmdq->secondary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &range, secondary_size,
55 DRM_IVPU_BO_WC);
56 if (!cmdq->secondary_preempt_buf) {
57 ivpu_err(vdev, "Failed to create secondary preemption buffer\n");
58 goto err_free_primary;
59 }
60
61 return 0;
62
63err_free_primary:
64 ivpu_bo_free(cmdq->primary_preempt_buf);
65 return -ENOMEM;
66}
67
68static void ivpu_preemption_buffers_free(struct ivpu_device *vdev,
69 struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
70{
71 if (vdev->hw->sched_mode != VPU_SCHEDULING_MODE_HW)
72 return;
73
74 drm_WARN_ON(&vdev->drm, !cmdq->primary_preempt_buf);
75 drm_WARN_ON(&vdev->drm, !cmdq->secondary_preempt_buf);
76 ivpu_bo_free(cmdq->primary_preempt_buf);
77 ivpu_bo_free(cmdq->secondary_preempt_buf);
78}
79
80static struct ivpu_cmdq *ivpu_cmdq_alloc(struct ivpu_file_priv *file_priv)
32{81{
33 struct xa_limit db_xa_limit = {.max = IVPU_MAX_DB, .min = IVPU_MIN_DB};82 struct xa_limit db_xa_limit = {.max = IVPU_MAX_DB, .min = IVPU_MIN_DB};
34 struct ivpu_device *vdev = file_priv->vdev;83 struct ivpu_device *vdev = file_priv->vdev;
35 struct vpu_job_queue_header *jobq_header;
36 struct ivpu_cmdq *cmdq;84 struct ivpu_cmdq *cmdq;
37 int ret;85 int ret;
38 86
@@ -50,18 +98,14 @@ static struct ivpu_cmdq *ivpu_cmdq_alloc(struct ivpu_file_priv *file_priv, u16 e · 11 unmodified lines
50 if (!cmdq->mem)98 if (!cmdq->mem)
51 goto err_erase_xa;99 goto err_erase_xa;
52 100
53 cmdq->entry_count = (u32)((ivpu_bo_size(cmdq->mem) - sizeof(struct vpu_job_queue_header)) /101 ret = ivpu_preemption_buffers_create(vdev, file_priv, cmdq);
54 sizeof(struct vpu_job_queue_entry));102 if (ret)
55 103 goto err_free_cmdq_mem;
56 cmdq->jobq = (struct vpu_job_queue *)ivpu_bo_vaddr(cmdq->mem);
57 jobq_header = &cmdq->jobq->header;
58 jobq_header->engine_idx = engine;
59 jobq_header->head = 0;
60 jobq_header->tail = 0;
61 wmb(); /* Flush WC buffer for jobq->header */
62 104
63 return cmdq;105 return cmdq;
64 106
107err_free_cmdq_mem:
108 ivpu_bo_free(cmdq->mem);
65err_erase_xa:109err_erase_xa:
66 xa_erase(&vdev->db_xa, cmdq->db_id);110 xa_erase(&vdev->db_xa, cmdq->db_id);
67err_free_cmdq:111err_free_cmdq:
@@ -74,92 +118,183 @@ static void ivpu_cmdq_free(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *c · 6 unmodified lines
74 if (!cmdq)118 if (!cmdq)
75 return;119 return;
76 120
121 ivpu_preemption_buffers_free(file_priv->vdev, file_priv, cmdq);
77 ivpu_bo_free(cmdq->mem);122 ivpu_bo_free(cmdq->mem);
78 xa_erase(&file_priv->vdev->db_xa, cmdq->db_id);123 xa_erase(&file_priv->vdev->db_xa, cmdq->db_id);
79 kfree(cmdq);124 kfree(cmdq);
80}125}
81 126
82static struct ivpu_cmdq *ivpu_cmdq_acquire(struct ivpu_file_priv *file_priv, u16 engine)127static int ivpu_hws_cmdq_init(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq, u16 engine,
128 u8 priority)
83{129{
84 struct ivpu_device *vdev = file_priv->vdev;130 struct ivpu_device *vdev = file_priv->vdev;
85 struct ivpu_cmdq *cmdq = file_priv->cmdq[engine];131 int ret;
132
133 ret = ivpu_jsm_hws_create_cmdq(vdev, file_priv->ctx.id, file_priv->ctx.id, cmdq->db_id,
134 task_pid_nr(current), engine,
135 cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
136 if (ret)
137 return ret;
138
139 ret = ivpu_jsm_hws_set_context_sched_properties(vdev, file_priv->ctx.id, cmdq->db_id,
140 priority);
141 if (ret)
142 return ret;
143
144 return 0;
145}
146
147static int ivpu_register_db(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
148{
149 struct ivpu_device *vdev = file_priv->vdev;
150 int ret;
151
152 if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW)
153 ret = ivpu_jsm_hws_register_db(vdev, file_priv->ctx.id, cmdq->db_id, cmdq->db_id,
154 cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
155 else
156 ret = ivpu_jsm_register_db(vdev, file_priv->ctx.id, cmdq->db_id,
157 cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
158
159 if (!ret)
160 ivpu_dbg(vdev, JOB, "DB %d registered to ctx %d\n", cmdq->db_id, file_priv->ctx.id);
161
162 return ret;
163}
164
165static int
166ivpu_cmdq_init(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq, u16 engine, u8 priority)
167{
168 struct ivpu_device *vdev = file_priv->vdev;
169 struct vpu_job_queue_header *jobq_header;
170 int ret;
171
172 lockdep_assert_held(&file_priv->lock);
173
174 if (cmdq->db_registered)
175 return 0;
176
177 cmdq->entry_count = (u32)((ivpu_bo_size(cmdq->mem) - sizeof(struct vpu_job_queue_header)) /
178 sizeof(struct vpu_job_queue_entry));
179
180 cmdq->jobq = (struct vpu_job_queue *)ivpu_bo_vaddr(cmdq->mem);
181 jobq_header = &cmdq->jobq->header;
182 jobq_header->engine_idx = engine;
183 jobq_header->head = 0;
184 jobq_header->tail = 0;
185 wmb(); /* Flush WC buffer for jobq->header */
186
187 if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) {
188 ret = ivpu_hws_cmdq_init(file_priv, cmdq, engine, priority);
189 if (ret)
190 return ret;
191 }
192
193 ret = ivpu_register_db(file_priv, cmdq);
194 if (ret)
195 return ret;
196
197 cmdq->db_registered = true;
198
199 return 0;
200}
201
202static int ivpu_cmdq_fini(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
203{
204 struct ivpu_device *vdev = file_priv->vdev;
205 int ret;
206
207 lockdep_assert_held(&file_priv->lock);
208
209 if (!cmdq->db_registered)
210 return 0;
211
212 cmdq->db_registered = false;
213
214 if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) {
215 ret = ivpu_jsm_hws_destroy_cmdq(vdev, file_priv->ctx.id, cmdq->db_id);
216 if (!ret)
217 ivpu_dbg(vdev, JOB, "Command queue %d destroyed\n", cmdq->db_id);
218 }
219
220 ret = ivpu_jsm_unregister_db(vdev, cmdq->db_id);
221 if (!ret)
222 ivpu_dbg(vdev, JOB, "DB %d unregistered\n", cmdq->db_id);
223
224 return 0;
225}
226
227static struct ivpu_cmdq *ivpu_cmdq_acquire(struct ivpu_file_priv *file_priv, u16 engine,
228 u8 priority)
229{
230 int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority);
231 struct ivpu_cmdq *cmdq = file_priv->cmdq[cmdq_idx];
86 int ret;232 int ret;
87 233
88 lockdep_assert_held(&file_priv->lock);234 lockdep_assert_held(&file_priv->lock);
89 235
90 if (!cmdq) {236 if (!cmdq) {
91 cmdq = ivpu_cmdq_alloc(file_priv, engine);237 cmdq = ivpu_cmdq_alloc(file_priv);
92 if (!cmdq)238 if (!cmdq)
93 return NULL;239 return NULL;
94 file_priv->cmdq[engine] = cmdq;240 file_priv->cmdq[cmdq_idx] = cmdq;
95 }241 }
96 242
97 if (cmdq->db_registered)243 ret = ivpu_cmdq_init(file_priv, cmdq, engine, priority);
98 return cmdq;
99
100 ret = ivpu_jsm_register_db(vdev, file_priv->ctx.id, cmdq->db_id,
101 cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
102 if (ret)244 if (ret)
103 return NULL;245 return NULL;
104 246
105 cmdq->db_registered = true;
106
107 return cmdq;247 return cmdq;
108}248}
109 249
110static void ivpu_cmdq_release_locked(struct ivpu_file_priv *file_priv, u16 engine)250static void ivpu_cmdq_release_locked(struct ivpu_file_priv *file_priv, u16 engine, u8 priority)
111{251{
112 struct ivpu_cmdq *cmdq = file_priv->cmdq[engine];252 int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority);
253 struct ivpu_cmdq *cmdq = file_priv->cmdq[cmdq_idx];
113 254
114 lockdep_assert_held(&file_priv->lock);255 lockdep_assert_held(&file_priv->lock);
115 256
116 if (cmdq) {257 if (cmdq) {
117 file_priv->cmdq[engine] = NULL;258 file_priv->cmdq[cmdq_idx] = NULL;
118 if (cmdq->db_registered)259 ivpu_cmdq_fini(file_priv, cmdq);
119 ivpu_jsm_unregister_db(file_priv->vdev, cmdq->db_id);
120
121 ivpu_cmdq_free(file_priv, cmdq);260 ivpu_cmdq_free(file_priv, cmdq);
122 }261 }
123}262}
124 263
125void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv)264void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv)
126{265{
127 int i;266 u16 engine;
267 u8 priority;
128 268
129 lockdep_assert_held(&file_priv->lock);269 lockdep_assert_held(&file_priv->lock);
130 270
131 for (i = 0; i < IVPU_NUM_ENGINES; i++)271 for (engine = 0; engine < IVPU_NUM_ENGINES; engine++)
132 ivpu_cmdq_release_locked(file_priv, i);272 for (priority = 0; priority < IVPU_NUM_PRIORITIES; priority++)
273 ivpu_cmdq_release_locked(file_priv, engine, priority);
133}274}
134 275
135/*276/*
136 * Mark the doorbell as unregistered and reset job queue pointers.277 * Mark the doorbell as unregistered
137 * This function needs to be called when the VPU hardware is restarted278 * This function needs to be called when the VPU hardware is restarted
138 * and FW loses job queue state. The next time job queue is used it279 * and FW loses job queue state. The next time job queue is used it
139 * will be registered again.280 * will be registered again.
140 */281 */
141static void ivpu_cmdq_reset_locked(struct ivpu_file_priv *file_priv, u16 engine)282static void ivpu_cmdq_reset(struct ivpu_file_priv *file_priv)
142{
143 struct ivpu_cmdq *cmdq = file_priv->cmdq[engine];
144
145 lockdep_assert_held(&file_priv->lock);
146
147 if (cmdq) {
148 cmdq->db_registered = false;
149 cmdq->jobq->header.head = 0;
150 cmdq->jobq->header.tail = 0;
151 wmb(); /* Flush WC buffer for jobq header */
152 }
153}
154
155static void ivpu_cmdq_reset_all(struct ivpu_file_priv *file_priv)
156{283{
157 int i;284 u16 engine;
285 u8 priority;
158 286
159 mutex_lock(&file_priv->lock);287 mutex_lock(&file_priv->lock);
160 288
161 for (i = 0; i < IVPU_NUM_ENGINES; i++)289 for (engine = 0; engine < IVPU_NUM_ENGINES; engine++) {
162 ivpu_cmdq_reset_locked(file_priv, i);290 for (priority = 0; priority < IVPU_NUM_PRIORITIES; priority++) {
291 int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority);
292 struct ivpu_cmdq *cmdq = file_priv->cmdq[cmdq_idx];
293
294 if (cmdq)
295 cmdq->db_registered = false;
296 }
297 }
163 298
164 mutex_unlock(&file_priv->lock);299 mutex_unlock(&file_priv->lock);
165}300}
@@ -172,10 +307,36 @@ void ivpu_cmdq_reset_all_contexts(struct ivpu_device *vdev) · 6 unmodified lines
172 mutex_lock(&vdev->context_list_lock);307 mutex_lock(&vdev->context_list_lock);
173 308
174 xa_for_each(&vdev->context_xa, ctx_id, file_priv)309 xa_for_each(&vdev->context_xa, ctx_id, file_priv)
175 ivpu_cmdq_reset_all(file_priv);310 ivpu_cmdq_reset(file_priv);
176 311
177 mutex_unlock(&vdev->context_list_lock);312 mutex_unlock(&vdev->context_list_lock);
313}
314
315static void ivpu_cmdq_fini_all(struct ivpu_file_priv *file_priv)
316{
317 u16 engine;
318 u8 priority;
319
320 for (engine = 0; engine < IVPU_NUM_ENGINES; engine++) {
321 for (priority = 0; priority < IVPU_NUM_PRIORITIES; priority++) {
322 int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority);
323
324 if (file_priv->cmdq[cmdq_idx])
325 ivpu_cmdq_fini(file_priv, file_priv->cmdq[cmdq_idx]);
326 }
327 }
328}
178 329
330void ivpu_context_abort_locked(struct ivpu_file_priv *file_priv)
331{
332 struct ivpu_device *vdev = file_priv->vdev;
333
334 lockdep_assert_held(&file_priv->lock);
335
336 ivpu_cmdq_fini_all(file_priv);
337
338 if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_OS)
339 ivpu_jsm_context_release(vdev, file_priv->ctx.id);
179}340}
180 341
181static int ivpu_cmdq_push_job(struct ivpu_cmdq *cmdq, struct ivpu_job *job)342static int ivpu_cmdq_push_job(struct ivpu_cmdq *cmdq, struct ivpu_job *job)
@@ -199,6 +360,15 @@ static int ivpu_cmdq_push_job(struct ivpu_cmdq *cmdq, struct ivpu_job *job) · 17 unmodified lines
199 entry->flags = 0;360 entry->flags = 0;
200 if (unlikely(ivpu_test_mode & IVPU_TEST_MODE_NULL_SUBMISSION))361 if (unlikely(ivpu_test_mode & IVPU_TEST_MODE_NULL_SUBMISSION))
201 entry->flags = VPU_JOB_FLAGS_NULL_SUBMISSION_MASK;362 entry->flags = VPU_JOB_FLAGS_NULL_SUBMISSION_MASK;
363
364 if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW &&
365 (unlikely(!(ivpu_test_mode & IVPU_TEST_MODE_PREEMPTION_DISABLE)))) {
366 entry->primary_preempt_buf_addr = cmdq->primary_preempt_buf->vpu_addr;
367 entry->primary_preempt_buf_size = ivpu_bo_size(cmdq->primary_preempt_buf);
368 entry->secondary_preempt_buf_addr = cmdq->secondary_preempt_buf->vpu_addr;
369 entry->secondary_preempt_buf_size = ivpu_bo_size(cmdq->secondary_preempt_buf);
370 }
371
202 wmb(); /* Ensure that tail is updated after filling entry */372 wmb(); /* Ensure that tail is updated after filling entry */
203 header->tail = next_entry;373 header->tail = next_entry;
204 wmb(); /* Flush WC buffer for jobq header */374 wmb(); /* Flush WC buffer for jobq header */
@@ -295,11 +465,28 @@ err_free_job: · 90 unmodified lines
295 return NULL;465 return NULL;
296}466}
297 467
468static struct ivpu_job *ivpu_job_remove_from_submitted_jobs(struct ivpu_device *vdev, u32 job_id)
469{
470 struct ivpu_job *job;
471
472 xa_lock(&vdev->submitted_jobs_xa);
473 job = __xa_erase(&vdev->submitted_jobs_xa, job_id);
474
475 if (xa_empty(&vdev->submitted_jobs_xa) && job) {
476 vdev->busy_time = ktime_add(ktime_sub(ktime_get(), vdev->busy_start_ts),
477 vdev->busy_time);
478 }
479
480 xa_unlock(&vdev->submitted_jobs_xa);
481
482 return job;
483}
484
298static int ivpu_job_signal_and_destroy(struct ivpu_device *vdev, u32 job_id, u32 job_status)485static int ivpu_job_signal_and_destroy(struct ivpu_device *vdev, u32 job_id, u32 job_status)
299{486{
300 struct ivpu_job *job;487 struct ivpu_job *job;
301 488
302 job = xa_erase(&vdev->submitted_jobs_xa, job_id);489 job = ivpu_job_remove_from_submitted_jobs(vdev, job_id);
303 if (!job)490 if (!job)
304 return -ENOENT;491 return -ENOENT;
305 492
@@ -328,12 +515,13 @@ void ivpu_jobs_abort_all(struct ivpu_device *vdev) · 22 unmodified lines
328 ivpu_job_signal_and_destroy(vdev, id, DRM_IVPU_JOB_STATUS_ABORTED);515 ivpu_job_signal_and_destroy(vdev, id, DRM_IVPU_JOB_STATUS_ABORTED);
329}516}
330 517
331static int ivpu_job_submit(struct ivpu_job *job)518static int ivpu_job_submit(struct ivpu_job *job, u8 priority)
332{519{
333 struct ivpu_file_priv *file_priv = job->file_priv;520 struct ivpu_file_priv *file_priv = job->file_priv;
334 struct ivpu_device *vdev = job->vdev;521 struct ivpu_device *vdev = job->vdev;
335 struct xa_limit job_id_range;522 struct xa_limit job_id_range;
336 struct ivpu_cmdq *cmdq;523 struct ivpu_cmdq *cmdq;
524 bool is_first_job;
337 int ret;525 int ret;
338 526
339 ret = ivpu_rpm_get(vdev);527 ret = ivpu_rpm_get(vdev);
@@ -342,10 +530,10 @@ static int ivpu_job_submit(struct ivpu_job *job) · 2 unmodified lines
342 530
343 mutex_lock(&file_priv->lock);531 mutex_lock(&file_priv->lock);
344 532
345 cmdq = ivpu_cmdq_acquire(job->file_priv, job->engine_idx);533 cmdq = ivpu_cmdq_acquire(job->file_priv, job->engine_idx, priority);
346 if (!cmdq) {534 if (!cmdq) {
347 ivpu_warn_ratelimited(vdev, "Failed get job queue, ctx %d engine %d\n",535 ivpu_warn_ratelimited(vdev, "Failed to get job queue, ctx %d engine %d prio %d\n",
348 file_priv->ctx.id, job->engine_idx);536 file_priv->ctx.id, job->engine_idx, priority);
349 ret = -EINVAL;537 ret = -EINVAL;
350 goto err_unlock_file_priv;538 goto err_unlock_file_priv;
351 }539 }
@@ -354,6 +542,7 @@ static int ivpu_job_submit(struct ivpu_job *job) · 2 unmodified lines
354 job_id_range.max = job_id_range.min | JOB_ID_JOB_MASK;542 job_id_range.max = job_id_range.min | JOB_ID_JOB_MASK;
355 543
356 xa_lock(&vdev->submitted_jobs_xa);544 xa_lock(&vdev->submitted_jobs_xa);
545 is_first_job = xa_empty(&vdev->submitted_jobs_xa);
357 ret = __xa_alloc(&vdev->submitted_jobs_xa, &job->job_id, job, job_id_range, GFP_KERNEL);546 ret = __xa_alloc(&vdev->submitted_jobs_xa, &job->job_id, job, job_id_range, GFP_KERNEL);
358 if (ret) {547 if (ret) {
359 ivpu_dbg(vdev, JOB, "Too many active jobs in ctx %d\n",548 ivpu_dbg(vdev, JOB, "Too many active jobs in ctx %d\n",
@@ -373,10 +562,12 @@ static int ivpu_job_submit(struct ivpu_job *job) · 13 unmodified lines
373 wmb(); /* Flush WC buffer for jobq header */562 wmb(); /* Flush WC buffer for jobq header */
374 } else {563 } else {
375 ivpu_cmdq_ring_db(vdev, cmdq);564 ivpu_cmdq_ring_db(vdev, cmdq);
565 if (is_first_job)
566 vdev->busy_start_ts = ktime_get();
376 }567 }
377 568
378 ivpu_dbg(vdev, JOB, "Job submitted: id %3u ctx %2d engine %d addr 0x%llx next %d\n",569 ivpu_dbg(vdev, JOB, "Job submitted: id %3u ctx %2d engine %d prio %d addr 0x%llx next %d\n",
379 job->job_id, file_priv->ctx.id, job->engine_idx,570 job->job_id, file_priv->ctx.id, job->engine_idx, priority,
380 job->cmd_buf_vpu_addr, cmdq->jobq->header.tail);571 job->cmd_buf_vpu_addr, cmdq->jobq->header.tail);
381 572
382 xa_unlock(&vdev->submitted_jobs_xa);573 xa_unlock(&vdev->submitted_jobs_xa);
@@ -464,6 +655,14 @@ unlock_reservations: · 81 unmodified lines
464 return ret;655 return ret;
465}656}
466 657
658static inline u8 ivpu_job_to_hws_priority(struct ivpu_file_priv *file_priv, u8 priority)
659{
660 if (priority == DRM_IVPU_JOB_PRIORITY_DEFAULT)
661 return DRM_IVPU_JOB_PRIORITY_NORMAL;
662
663 return priority - 1;
664}
665
467int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file)666int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
468{667{
469 struct ivpu_file_priv *file_priv = file->driver_priv;668 struct ivpu_file_priv *file_priv = file->driver_priv;
@@ -472,6 +671,7 @@ int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file) · 2 unmodified lines
472 struct ivpu_job *job;671 struct ivpu_job *job;
473 u32 *buf_handles;672 u32 *buf_handles;
474 int idx, ret;673 int idx, ret;
674 u8 priority;
475 675
476 if (params->engine > DRM_IVPU_ENGINE_COPY)676 if (params->engine > DRM_IVPU_ENGINE_COPY)
477 return -EINVAL;677 return -EINVAL;
@@ -525,8 +725,10 @@ int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file) · 47 unmodified lines
525 goto err_destroy_job;725 goto err_destroy_job;
526 }726 }
527 727
728 priority = ivpu_job_to_hws_priority(file_priv, params->priority);
729
528 down_read(&vdev->pm->reset_lock);730 down_read(&vdev->pm->reset_lock);
529 ret = ivpu_job_submit(job);731 ret = ivpu_job_submit(job, priority);
530 up_read(&vdev->pm->reset_lock);732 up_read(&vdev->pm->reset_lock);
531 if (ret)733 if (ret)
532 goto err_signal_fence;734 goto err_signal_fence;
drivers/accel/ivpu/ivpu_job.h+5−1
@@ -1,6 +1,6 @@
1/* SPDX-License-Identifier: GPL-2.0-only */1/* SPDX-License-Identifier: GPL-2.0-only */
2/*2/*
3 * Copyright (C) 2020-2023 Intel Corporation3 * Copyright (C) 2020-2024 Intel Corporation
4 */4 */
5 5
6#ifndef __IVPU_JOB_H__6#ifndef __IVPU_JOB_H__
@@ -24,6 +24,8 @@ struct ivpu_file_priv; · 17 unmodified lines
24 */24 */
25struct ivpu_cmdq {25struct ivpu_cmdq {
26 struct vpu_job_queue *jobq;26 struct vpu_job_queue *jobq;
27 struct ivpu_bo *primary_preempt_buf;
28 struct ivpu_bo *secondary_preempt_buf;
27 struct ivpu_bo *mem;29 struct ivpu_bo *mem;
28 u32 entry_count;30 u32 entry_count;
29 u32 db_id;31 u32 db_id;
@@ -55,6 +57,8 @@ struct ivpu_job { · 25 unmodified lines
55 57
56int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file);58int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
57 59
60void ivpu_context_abort_locked(struct ivpu_file_priv *file_priv);
61
58void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv);62void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv);
59void ivpu_cmdq_reset_all_contexts(struct ivpu_device *vdev);63void ivpu_cmdq_reset_all_contexts(struct ivpu_device *vdev);
60 64
drivers/accel/ivpu/ivpu_jsm_msg.c+294−17
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0-only1// SPDX-License-Identifier: GPL-2.0-only
2/*2/*
3 * Copyright (C) 2020-2023 Intel Corporation3 * Copyright (C) 2020-2024 Intel Corporation
4 */4 */
5 5
6#include "ivpu_drv.h"6#include "ivpu_drv.h"
@@ -103,14 +103,10 @@ int ivpu_jsm_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 db_id, · 96 unmodified lines
103 103
104 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_REGISTER_DB_DONE, &resp,104 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_REGISTER_DB_DONE, &resp,
105 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);105 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
106 if (ret) {106 if (ret)
107 ivpu_err_ratelimited(vdev, "Failed to register doorbell %d: %d\n", db_id, ret);107 ivpu_err_ratelimited(vdev, "Failed to register doorbell %u: %d\n", db_id, ret);
108 return ret;
109 }
110
111 ivpu_dbg(vdev, JSM, "Doorbell %d registered to context %d\n", db_id, ctx_id);
112 108
113 return 0;109 return ret;
114}110}
115 111
116int ivpu_jsm_unregister_db(struct ivpu_device *vdev, u32 db_id)112int ivpu_jsm_unregister_db(struct ivpu_device *vdev, u32 db_id)
@@ -123,14 +119,10 @@ int ivpu_jsm_unregister_db(struct ivpu_device *vdev, u32 db_id) · 6 unmodified lines
123 119
124 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_UNREGISTER_DB_DONE, &resp,120 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_UNREGISTER_DB_DONE, &resp,
125 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);121 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
126 if (ret) {122 if (ret)
127 ivpu_warn_ratelimited(vdev, "Failed to unregister doorbell %d: %d\n", db_id, ret);123 ivpu_warn_ratelimited(vdev, "Failed to unregister doorbell %u: %d\n", db_id, ret);
128 return ret;
129 }
130
131 ivpu_dbg(vdev, JSM, "Doorbell %d unregistered\n", db_id);
132 124
133 return 0;125 return ret;
134}126}
135 127
136int ivpu_jsm_get_heartbeat(struct ivpu_device *vdev, u32 engine, u64 *heartbeat)128int ivpu_jsm_get_heartbeat(struct ivpu_device *vdev, u32 engine, u64 *heartbeat)
@@ -255,11 +247,16 @@ int ivpu_jsm_context_release(struct ivpu_device *vdev, u32 host_ssid) · 118 unmodified lines
255{247{
256 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_SSID_RELEASE };248 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_SSID_RELEASE };
257 struct vpu_jsm_msg resp;249 struct vpu_jsm_msg resp;
250 int ret;
258 251
259 req.payload.ssid_release.host_ssid = host_ssid;252 req.payload.ssid_release.host_ssid = host_ssid;
260 253
261 return ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_SSID_RELEASE_DONE, &resp,254 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_SSID_RELEASE_DONE, &resp,
262 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);255 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
256 if (ret)
257 ivpu_warn_ratelimited(vdev, "Failed to release context: %d\n", ret);
258
259 return ret;
263}260}
264 261
265int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev)262int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev)
@@ -281,3 +278,283 @@ int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev) · 15 unmodified lines
281 278
282 return ivpu_hw_wait_for_idle(vdev);279 return ivpu_hw_wait_for_idle(vdev);
283}280}
281
282int ivpu_jsm_hws_create_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_group, u32 cmdq_id,
283 u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size)
284{
285 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_CREATE_CMD_QUEUE };
286 struct vpu_jsm_msg resp;
287 int ret;
288
289 req.payload.hws_create_cmdq.host_ssid = ctx_id;
290 req.payload.hws_create_cmdq.process_id = pid;
291 req.payload.hws_create_cmdq.engine_idx = engine;
292 req.payload.hws_create_cmdq.cmdq_group = cmdq_group;
293 req.payload.hws_create_cmdq.cmdq_id = cmdq_id;
294 req.payload.hws_create_cmdq.cmdq_base = cmdq_base;
295 req.payload.hws_create_cmdq.cmdq_size = cmdq_size;
296
297 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_CREATE_CMD_QUEUE_RSP, &resp,
298 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
299 if (ret)
300 ivpu_warn_ratelimited(vdev, "Failed to create command queue: %d\n", ret);
301
302 return ret;
303}
304
305int ivpu_jsm_hws_destroy_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id)
306{
307 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_DESTROY_CMD_QUEUE };
308 struct vpu_jsm_msg resp;
309 int ret;
310
311 req.payload.hws_destroy_cmdq.host_ssid = ctx_id;
312 req.payload.hws_destroy_cmdq.cmdq_id = cmdq_id;
313
314 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_DESTROY_CMD_QUEUE_RSP, &resp,
315 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
316 if (ret)
317 ivpu_warn_ratelimited(vdev, "Failed to destroy command queue: %d\n", ret);
318
319 return ret;
320}
321
322int ivpu_jsm_hws_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id, u32 db_id,
323 u64 cmdq_base, u32 cmdq_size)
324{
325 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_HWS_REGISTER_DB };
326 struct vpu_jsm_msg resp;
327 int ret = 0;
328
329 req.payload.hws_register_db.db_id = db_id;
330 req.payload.hws_register_db.host_ssid = ctx_id;
331 req.payload.hws_register_db.cmdq_id = cmdq_id;
332 req.payload.hws_register_db.cmdq_base = cmdq_base;
333 req.payload.hws_register_db.cmdq_size = cmdq_size;
334
335 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_REGISTER_DB_DONE, &resp,
336 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
337 if (ret)
338 ivpu_err_ratelimited(vdev, "Failed to register doorbell %u: %d\n", db_id, ret);
339
340 return ret;
341}
342
343int ivpu_jsm_hws_resume_engine(struct ivpu_device *vdev, u32 engine)
344{
345 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_HWS_ENGINE_RESUME };
346 struct vpu_jsm_msg resp;
347 int ret;
348
349 if (engine >= VPU_ENGINE_NB)
350 return -EINVAL;
351
352 req.payload.hws_resume_engine.engine_idx = engine;
353
354 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_HWS_RESUME_ENGINE_DONE, &resp,
355 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
356 if (ret)
357 ivpu_err_ratelimited(vdev, "Failed to resume engine %d: %d\n", engine, ret);
358
359 return ret;
360}
361
362int ivpu_jsm_hws_set_context_sched_properties(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id,
363 u32 priority)
364{
365 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES };
366 struct vpu_jsm_msg resp;
367 int ret;
368
369 req.payload.hws_set_context_sched_properties.host_ssid = ctx_id;
370 req.payload.hws_set_context_sched_properties.cmdq_id = cmdq_id;
371 req.payload.hws_set_context_sched_properties.priority_band = priority;
372 req.payload.hws_set_context_sched_properties.realtime_priority_level = 0;
373 req.payload.hws_set_context_sched_properties.in_process_priority = 0;
374 req.payload.hws_set_context_sched_properties.context_quantum = 20000;
375 req.payload.hws_set_context_sched_properties.grace_period_same_priority = 10000;
376 req.payload.hws_set_context_sched_properties.grace_period_lower_priority = 0;
377
378 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES_RSP, &resp,
379 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
380 if (ret)
381 ivpu_warn_ratelimited(vdev, "Failed to set context sched properties: %d\n", ret);
382
383 return ret;
384}
385
386int ivpu_jsm_hws_set_scheduling_log(struct ivpu_device *vdev, u32 engine_idx, u32 host_ssid,
387 u64 vpu_log_buffer_va)
388{
389 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG };
390 struct vpu_jsm_msg resp;
391 int ret;
392
393 req.payload.hws_set_scheduling_log.engine_idx = engine_idx;
394 req.payload.hws_set_scheduling_log.host_ssid = host_ssid;
395 req.payload.hws_set_scheduling_log.vpu_log_buffer_va = vpu_log_buffer_va;
396 req.payload.hws_set_scheduling_log.notify_index = 0;
397 req.payload.hws_set_scheduling_log.enable_extra_events =
398 ivpu_test_mode & IVPU_TEST_MODE_HWS_EXTRA_EVENTS;
399
400 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG_RSP, &resp,
401 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
402 if (ret)
403 ivpu_warn_ratelimited(vdev, "Failed to set scheduling log: %d\n", ret);
404
405 return ret;
406}
407
408int ivpu_jsm_hws_setup_priority_bands(struct ivpu_device *vdev)
409{
410 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP };
411 struct vpu_jsm_msg resp;
412 int ret;
413
414 /* Idle */
415 req.payload.hws_priority_band_setup.grace_period[0] = 0;
416 req.payload.hws_priority_band_setup.process_grace_period[0] = 50000;
417 req.payload.hws_priority_band_setup.process_quantum[0] = 160000;
418 /* Normal */
419 req.payload.hws_priority_band_setup.grace_period[1] = 50000;
420 req.payload.hws_priority_band_setup.process_grace_period[1] = 50000;
421 req.payload.hws_priority_band_setup.process_quantum[1] = 300000;
422 /* Focus */
423 req.payload.hws_priority_band_setup.grace_period[2] = 50000;
424 req.payload.hws_priority_band_setup.process_grace_period[2] = 50000;
425 req.payload.hws_priority_band_setup.process_quantum[2] = 200000;
426 /* Realtime */
427 req.payload.hws_priority_band_setup.grace_period[3] = 0;
428 req.payload.hws_priority_band_setup.process_grace_period[3] = 50000;
429 req.payload.hws_priority_band_setup.process_quantum[3] = 200000;
430
431 req.payload.hws_priority_band_setup.normal_band_percentage = 10;
432
433 ret = ivpu_ipc_send_receive_active(vdev, &req, VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP_RSP,
434 &resp, VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
435 if (ret)
436 ivpu_warn_ratelimited(vdev, "Failed to set priority bands: %d\n", ret);
437
438 return ret;
439}
440
441int ivpu_jsm_metric_streamer_start(struct ivpu_device *vdev, u64 metric_group_mask,
442 u64 sampling_rate, u64 buffer_addr, u64 buffer_size)
443{
444 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_START };
445 struct vpu_jsm_msg resp;
446 int ret;
447
448 req.payload.metric_streamer_start.metric_group_mask = metric_group_mask;
449 req.payload.metric_streamer_start.sampling_rate = sampling_rate;
450 req.payload.metric_streamer_start.buffer_addr = buffer_addr;
451 req.payload.metric_streamer_start.buffer_size = buffer_size;
452
453 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_START_DONE, &resp,
454 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
455 if (ret) {
456 ivpu_warn_ratelimited(vdev, "Failed to start metric streamer: ret %d\n", ret);
457 return ret;
458 }
459
460 return ret;
461}
462
463int ivpu_jsm_metric_streamer_stop(struct ivpu_device *vdev, u64 metric_group_mask)
464{
465 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_STOP };
466 struct vpu_jsm_msg resp;
467 int ret;
468
469 req.payload.metric_streamer_stop.metric_group_mask = metric_group_mask;
470
471 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_STOP_DONE, &resp,
472 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
473 if (ret)
474 ivpu_warn_ratelimited(vdev, "Failed to stop metric streamer: ret %d\n", ret);
475
476 return ret;
477}
478
479int ivpu_jsm_metric_streamer_update(struct ivpu_device *vdev, u64 metric_group_mask,
480 u64 buffer_addr, u64 buffer_size, u64 *bytes_written)
481{
482 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_UPDATE };
483 struct vpu_jsm_msg resp;
484 int ret;
485
486 req.payload.metric_streamer_update.metric_group_mask = metric_group_mask;
487 req.payload.metric_streamer_update.buffer_addr = buffer_addr;
488 req.payload.metric_streamer_update.buffer_size = buffer_size;
489
490 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_UPDATE_DONE, &resp,
491 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
492 if (ret) {
493 ivpu_warn_ratelimited(vdev, "Failed to update metric streamer: ret %d\n", ret);
494 return ret;
495 }
496
497 if (buffer_size && resp.payload.metric_streamer_done.bytes_written > buffer_size) {
498 ivpu_warn_ratelimited(vdev, "MS buffer overflow: bytes_written %#llx > buffer_size %#llx\n",
499 resp.payload.metric_streamer_done.bytes_written, buffer_size);
500 return -EOVERFLOW;
501 }
502
503 *bytes_written = resp.payload.metric_streamer_done.bytes_written;
504
505 return ret;
506}
507
508int ivpu_jsm_metric_streamer_info(struct ivpu_device *vdev, u64 metric_group_mask, u64 buffer_addr,
509 u64 buffer_size, u32 *sample_size, u64 *info_size)
510{
511 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_INFO };
512 struct vpu_jsm_msg resp;
513 int ret;
514
515 req.payload.metric_streamer_start.metric_group_mask = metric_group_mask;
516 req.payload.metric_streamer_start.buffer_addr = buffer_addr;
517 req.payload.metric_streamer_start.buffer_size = buffer_size;
518
519 ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_INFO_DONE, &resp,
520 VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
521 if (ret) {
522 ivpu_warn_ratelimited(vdev, "Failed to get metric streamer info: ret %d\n", ret);
523 return ret;
524 }
525
526 if (!resp.payload.metric_streamer_done.sample_size) {
527 ivpu_warn_ratelimited(vdev, "Invalid sample size\n");
528 return -EBADMSG;
529 }
530
531 if (sample_size)
532 *sample_size = resp.payload.metric_streamer_done.sample_size;
533 if (info_size)
534 *info_size = resp.payload.metric_streamer_done.bytes_written;
535
536 return ret;
537}
538
539int ivpu_jsm_dct_enable(struct ivpu_device *vdev, u32 active_us, u32 inactive_us)
540{
541 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_DCT_ENABLE };
542 struct vpu_jsm_msg resp;
543
544 req.payload.pwr_dct_control.dct_active_us = active_us;
545 req.payload.pwr_dct_control.dct_inactive_us = inactive_us;
546
547 return ivpu_ipc_send_receive_active(vdev, &req, VPU_JSM_MSG_DCT_ENABLE_DONE,
548 &resp, VPU_IPC_CHAN_ASYNC_CMD,
549 vdev->timeout.jsm);
550}
551
552int ivpu_jsm_dct_disable(struct ivpu_device *vdev)
553{
554 struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_DCT_DISABLE };
555 struct vpu_jsm_msg resp;
556
557 return ivpu_ipc_send_receive_active(vdev, &req, VPU_JSM_MSG_DCT_DISABLE_DONE,
558 &resp, VPU_IPC_CHAN_ASYNC_CMD,
559 vdev->timeout.jsm);
560}
drivers/accel/ivpu/ivpu_jsm_msg.h+21−1
@@ -1,6 +1,6 @@
1/* SPDX-License-Identifier: GPL-2.0-only */1/* SPDX-License-Identifier: GPL-2.0-only */
2/*2/*
3 * Copyright (C) 2020-2023 Intel Corporation3 * Copyright (C) 2020-2024 Intel Corporation
4 */4 */
5 5
6#ifndef __IVPU_JSM_MSG_H__6#ifndef __IVPU_JSM_MSG_H__
@@ -23,4 +23,24 @@ int ivpu_jsm_trace_set_config(struct ivpu_device *vdev, u32 trace_level, u32 tra · 16 unmodified lines
23 u64 trace_hw_component_mask);23 u64 trace_hw_component_mask);
24int ivpu_jsm_context_release(struct ivpu_device *vdev, u32 host_ssid);24int ivpu_jsm_context_release(struct ivpu_device *vdev, u32 host_ssid);
25int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev);25int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev);
26int ivpu_jsm_hws_create_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_group, u32 cmdq_id,
27 u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size);
28int ivpu_jsm_hws_destroy_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id);
29int ivpu_jsm_hws_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id, u32 db_id,
30 u64 cmdq_base, u32 cmdq_size);
31int ivpu_jsm_hws_resume_engine(struct ivpu_device *vdev, u32 engine);
32int ivpu_jsm_hws_set_context_sched_properties(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id,
33 u32 priority);
34int ivpu_jsm_hws_set_scheduling_log(struct ivpu_device *vdev, u32 engine_idx, u32 host_ssid,
35 u64 vpu_log_buffer_va);
36int ivpu_jsm_hws_setup_priority_bands(struct ivpu_device *vdev);
37int ivpu_jsm_metric_streamer_start(struct ivpu_device *vdev, u64 metric_group_mask,
38 u64 sampling_rate, u64 buffer_addr, u64 buffer_size);
39int ivpu_jsm_metric_streamer_stop(struct ivpu_device *vdev, u64 metric_group_mask);
40int ivpu_jsm_metric_streamer_update(struct ivpu_device *vdev, u64 metric_group_mask,
41 u64 buffer_addr, u64 buffer_size, u64 *bytes_written);
42int ivpu_jsm_metric_streamer_info(struct ivpu_device *vdev, u64 metric_group_mask, u64 buffer_addr,
43 u64 buffer_size, u32 *sample_size, u64 *info_size);
44int ivpu_jsm_dct_enable(struct ivpu_device *vdev, u32 active_us, u32 inactive_us);
45int ivpu_jsm_dct_disable(struct ivpu_device *vdev);
26#endif46#endif
drivers/accel/ivpu/ivpu_mmu.c+15−7
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0-only1// SPDX-License-Identifier: GPL-2.0-only
2/*2/*
3 * Copyright (C) 2020-2023 Intel Corporation3 * Copyright (C) 2020-2024 Intel Corporation
4 */4 */
5 5
6#include <linux/circ_buf.h>6#include <linux/circ_buf.h>
@@ -519,7 +519,8 @@ static int ivpu_mmu_cmdq_sync(struct ivpu_device *vdev) · 512 unmodified lines
519 if (ret)519 if (ret)
520 return ret;520 return ret;
521 521
522 clflush_cache_range(q->base, IVPU_MMU_CMDQ_SIZE);522 if (!ivpu_is_force_snoop_enabled(vdev))
523 clflush_cache_range(q->base, IVPU_MMU_CMDQ_SIZE);
523 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod);524 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod);
524 525
525 ret = ivpu_mmu_cmdq_wait_for_cons(vdev);526 ret = ivpu_mmu_cmdq_wait_for_cons(vdev);
@@ -567,7 +568,8 @@ static int ivpu_mmu_reset(struct ivpu_device *vdev) · 41 unmodified lines
567 int ret;568 int ret;
568 569
569 memset(mmu->cmdq.base, 0, IVPU_MMU_CMDQ_SIZE);570 memset(mmu->cmdq.base, 0, IVPU_MMU_CMDQ_SIZE);
570 clflush_cache_range(mmu->cmdq.base, IVPU_MMU_CMDQ_SIZE);571 if (!ivpu_is_force_snoop_enabled(vdev))
572 clflush_cache_range(mmu->cmdq.base, IVPU_MMU_CMDQ_SIZE);
571 mmu->cmdq.prod = 0;573 mmu->cmdq.prod = 0;
572 mmu->cmdq.cons = 0;574 mmu->cmdq.cons = 0;
573 575
@@ -661,7 +663,8 @@ static void ivpu_mmu_strtab_link_cd(struct ivpu_device *vdev, u32 sid) · 87 unmodified lines
661 WRITE_ONCE(entry[1], str[1]);663 WRITE_ONCE(entry[1], str[1]);
662 WRITE_ONCE(entry[0], str[0]);664 WRITE_ONCE(entry[0], str[0]);
663 665
664 clflush_cache_range(entry, IVPU_MMU_STRTAB_ENT_SIZE);666 if (!ivpu_is_force_snoop_enabled(vdev))
667 clflush_cache_range(entry, IVPU_MMU_STRTAB_ENT_SIZE);
665 668
666 ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]);669 ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]);
667}670}
@@ -735,7 +738,8 @@ static int ivpu_mmu_cd_add(struct ivpu_device *vdev, u32 ssid, u64 cd_dma) · 67 unmodified lines
735 WRITE_ONCE(entry[3], cd[3]);738 WRITE_ONCE(entry[3], cd[3]);
736 WRITE_ONCE(entry[0], cd[0]);739 WRITE_ONCE(entry[0], cd[0]);
737 740
738 clflush_cache_range(entry, IVPU_MMU_CDTAB_ENT_SIZE);741 if (!ivpu_is_force_snoop_enabled(vdev))
742 clflush_cache_range(entry, IVPU_MMU_CDTAB_ENT_SIZE);
739 743
740 ivpu_dbg(vdev, MMU, "CDTAB %s entry (SSID=%u, dma=%pad): 0x%llx, 0x%llx, 0x%llx, 0x%llx\n",744 ivpu_dbg(vdev, MMU, "CDTAB %s entry (SSID=%u, dma=%pad): 0x%llx, 0x%llx, 0x%llx, 0x%llx\n",
741 cd_dma ? "write" : "clear", ssid, &cd_dma, cd[0], cd[1], cd[2], cd[3]);745 cd_dma ? "write" : "clear", ssid, &cd_dma, cd[0], cd[1], cd[2], cd[3]);
@@ -874,8 +878,9 @@ static void ivpu_mmu_dump_event(struct ivpu_device *vdev, u32 *event) · 132 unmodified lines
874 u64 in_addr = ((u64)event[5]) << 32 | event[4];878 u64 in_addr = ((u64)event[5]) << 32 | event[4];
875 u32 sid = event[1];879 u32 sid = event[1];
876 880
877 ivpu_err(vdev, "MMU EVTQ: 0x%x (%s) SSID: %d SID: %d, e[2] %08x, e[3] %08x, in addr: 0x%llx, fetch addr: 0x%llx\n",881 ivpu_err_ratelimited(vdev, "MMU EVTQ: 0x%x (%s) SSID: %d SID: %d, e[2] %08x, e[3] %08x, in addr: 0x%llx, fetch addr: 0x%llx\n",
878 op, ivpu_mmu_event_to_str(op), ssid, sid, event[2], event[3], in_addr, fetch_addr);882 op, ivpu_mmu_event_to_str(op), ssid, sid,
883 event[2], event[3], in_addr, fetch_addr);
879}884}
880 885
881static u32 *ivpu_mmu_get_event(struct ivpu_device *vdev)886static u32 *ivpu_mmu_get_event(struct ivpu_device *vdev)
@@ -911,6 +916,9 @@ void ivpu_mmu_irq_evtq_handler(struct ivpu_device *vdev) · 29 unmodified lines
911 ivpu_mmu_user_context_mark_invalid(vdev, ssid);916 ivpu_mmu_user_context_mark_invalid(vdev, ssid);
912 REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, vdev->mmu->evtq.cons);917 REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, vdev->mmu->evtq.cons);
913 }918 }
919
920 if (!kfifo_put(&vdev->hw->irq.fifo, IVPU_HW_IRQ_SRC_MMU_EVTQ))
921 ivpu_err_ratelimited(vdev, "IRQ FIFO full\n");
914}922}
915 923
916void ivpu_mmu_evtq_dump(struct ivpu_device *vdev)924void ivpu_mmu_evtq_dump(struct ivpu_device *vdev)
drivers/accel/ivpu/ivpu_mmu_context.c+86−0
@@ -24,6 +24,7 @@ · 23 unmodified lines
24#define IVPU_MMU_ENTRY_FLAG_CONT BIT(52)24#define IVPU_MMU_ENTRY_FLAG_CONT BIT(52)
25#define IVPU_MMU_ENTRY_FLAG_NG BIT(11)25#define IVPU_MMU_ENTRY_FLAG_NG BIT(11)
26#define IVPU_MMU_ENTRY_FLAG_AF BIT(10)26#define IVPU_MMU_ENTRY_FLAG_AF BIT(10)
27#define IVPU_MMU_ENTRY_FLAG_RO BIT(7)
27#define IVPU_MMU_ENTRY_FLAG_USER BIT(6)28#define IVPU_MMU_ENTRY_FLAG_USER BIT(6)
28#define IVPU_MMU_ENTRY_FLAG_LLC_COHERENT BIT(2)29#define IVPU_MMU_ENTRY_FLAG_LLC_COHERENT BIT(2)
29#define IVPU_MMU_ENTRY_FLAG_TYPE_PAGE BIT(1)30#define IVPU_MMU_ENTRY_FLAG_TYPE_PAGE BIT(1)
@@ -319,6 +320,91 @@ ivpu_mmu_context_map_pages(struct ivpu_device *vdev, struct ivpu_mmu_context *ct · 289 unmodified lines
319 return 0;320 return 0;
320}321}
321 322
323static void ivpu_mmu_context_set_page_ro(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
324 u64 vpu_addr)
325{
326 int pgd_idx = FIELD_GET(IVPU_MMU_PGD_INDEX_MASK, vpu_addr);
327 int pud_idx = FIELD_GET(IVPU_MMU_PUD_INDEX_MASK, vpu_addr);
328 int pmd_idx = FIELD_GET(IVPU_MMU_PMD_INDEX_MASK, vpu_addr);
329 int pte_idx = FIELD_GET(IVPU_MMU_PTE_INDEX_MASK, vpu_addr);
330
331 ctx->pgtable.pte_ptrs[pgd_idx][pud_idx][pmd_idx][pte_idx] |= IVPU_MMU_ENTRY_FLAG_RO;
332}
333
334static void ivpu_mmu_context_split_page(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
335 u64 vpu_addr)
336{
337 int pgd_idx = FIELD_GET(IVPU_MMU_PGD_INDEX_MASK, vpu_addr);
338 int pud_idx = FIELD_GET(IVPU_MMU_PUD_INDEX_MASK, vpu_addr);
339 int pmd_idx = FIELD_GET(IVPU_MMU_PMD_INDEX_MASK, vpu_addr);
340 int pte_idx = FIELD_GET(IVPU_MMU_PTE_INDEX_MASK, vpu_addr);
341
342 ctx->pgtable.pte_ptrs[pgd_idx][pud_idx][pmd_idx][pte_idx] &= ~IVPU_MMU_ENTRY_FLAG_CONT;
343}
344
345static void ivpu_mmu_context_split_64k_page(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
346 u64 vpu_addr)
347{
348 u64 start = ALIGN_DOWN(vpu_addr, IVPU_MMU_CONT_PAGES_SIZE);
349 u64 end = ALIGN(vpu_addr, IVPU_MMU_CONT_PAGES_SIZE);
350 u64 offset = 0;
351
352 ivpu_dbg(vdev, MMU_MAP, "Split 64K page ctx: %u vpu_addr: 0x%llx\n", ctx->id, vpu_addr);
353
354 while (start + offset < end) {
355 ivpu_mmu_context_split_page(vdev, ctx, start + offset);
356 offset += IVPU_MMU_PAGE_SIZE;
357 }
358}
359
360int
361ivpu_mmu_context_set_pages_ro(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u64 vpu_addr,
362 size_t size)
363{
364 u64 end = vpu_addr + size;
365 size_t size_left = size;
366 int ret;
367
368 if (size == 0)
369 return 0;
370
371 if (drm_WARN_ON(&vdev->drm, !IS_ALIGNED(vpu_addr | size, IVPU_MMU_PAGE_SIZE)))
372 return -EINVAL;
373
374 mutex_lock(&ctx->lock);
375
376 ivpu_dbg(vdev, MMU_MAP, "Set read-only pages ctx: %u vpu_addr: 0x%llx size: %lu\n",
377 ctx->id, vpu_addr, size);
378
379 if (!ivpu_disable_mmu_cont_pages) {
380 /* Split 64K contiguous page at the beginning if needed */
381 if (!IS_ALIGNED(vpu_addr, IVPU_MMU_CONT_PAGES_SIZE))
382 ivpu_mmu_context_split_64k_page(vdev, ctx, vpu_addr);
383
384 /* Split 64K contiguous page at the end if needed */
385 if (!IS_ALIGNED(vpu_addr + size, IVPU_MMU_CONT_PAGES_SIZE))
386 ivpu_mmu_context_split_64k_page(vdev, ctx, vpu_addr + size);
387 }
388
389 while (size_left) {
390 if (vpu_addr < end)
391 ivpu_mmu_context_set_page_ro(vdev, ctx, vpu_addr);
392
393 vpu_addr += IVPU_MMU_PAGE_SIZE;
394 size_left -= IVPU_MMU_PAGE_SIZE;
395 }
396
397 /* Ensure page table modifications are flushed from wc buffers to memory */
398 wmb();
399
400 mutex_unlock(&ctx->lock);
401 ret = ivpu_mmu_invalidate_tlb(vdev, ctx->id);
402 if (ret)
403 ivpu_err(vdev, "Failed to invalidate TLB for ctx %u: %d\n", ctx->id, ret);
404
405 return 0;
406}
407
322static void ivpu_mmu_context_unmap_pages(struct ivpu_mmu_context *ctx, u64 vpu_addr, size_t size)408static void ivpu_mmu_context_unmap_pages(struct ivpu_mmu_context *ctx, u64 vpu_addr, size_t size)
323{409{
324 while (size) {410 while (size) {
drivers/accel/ivpu/ivpu_mmu_context.h+2−0
@@ -46,5 +46,7 @@ int ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context * · 45 unmodified lines
46 u64 vpu_addr, struct sg_table *sgt, bool llc_coherent);46 u64 vpu_addr, struct sg_table *sgt, bool llc_coherent);
47void ivpu_mmu_context_unmap_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,47void ivpu_mmu_context_unmap_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
48 u64 vpu_addr, struct sg_table *sgt);48 u64 vpu_addr, struct sg_table *sgt);
49int ivpu_mmu_context_set_pages_ro(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
50 u64 vpu_addr, size_t size);
49 51
50#endif /* __IVPU_MMU_CONTEXT_H__ */52#endif /* __IVPU_MMU_CONTEXT_H__ */
drivers/accel/ivpu/ivpu_ms.c+309−0
@@ -0,0 +1,309 @@
1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6#include <drm/drm_file.h>
7
8#include "ivpu_drv.h"
9#include "ivpu_gem.h"
10#include "ivpu_jsm_msg.h"
11#include "ivpu_ms.h"
12#include "ivpu_pm.h"
13
14#define MS_INFO_BUFFER_SIZE SZ_16K
15#define MS_NUM_BUFFERS 2
16#define MS_READ_PERIOD_MULTIPLIER 2
17#define MS_MIN_SAMPLE_PERIOD_NS 1000000
18
19static struct ivpu_ms_instance *
20get_instance_by_mask(struct ivpu_file_priv *file_priv, u64 metric_mask)
21{
22 struct ivpu_ms_instance *ms;
23
24 lockdep_assert_held(&file_priv->ms_lock);
25
26 list_for_each_entry(ms, &file_priv->ms_instance_list, ms_instance_node)
27 if (ms->mask == metric_mask)
28 return ms;
29
30 return NULL;
31}
32
33int ivpu_ms_start_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
34{
35 struct ivpu_file_priv *file_priv = file->driver_priv;
36 struct drm_ivpu_metric_streamer_start *args = data;
37 struct ivpu_device *vdev = file_priv->vdev;
38 struct ivpu_ms_instance *ms;
39 u64 single_buff_size;
40 u32 sample_size;
41 int ret;
42
43 if (!args->metric_group_mask || !args->read_period_samples ||
44 args->sampling_period_ns < MS_MIN_SAMPLE_PERIOD_NS)
45 return -EINVAL;
46
47 mutex_lock(&file_priv->ms_lock);
48
49 if (get_instance_by_mask(file_priv, args->metric_group_mask)) {
50 ivpu_err(vdev, "Instance already exists (mask %#llx)\n", args->metric_group_mask);
51 ret = -EALREADY;
52 goto unlock;
53 }
54
55 ms = kzalloc(sizeof(*ms), GFP_KERNEL);
56 if (!ms) {
57 ret = -ENOMEM;
58 goto unlock;
59 }
60
61 ms->mask = args->metric_group_mask;
62
63 ret = ivpu_jsm_metric_streamer_info(vdev, ms->mask, 0, 0, &sample_size, NULL);
64 if (ret)
65 goto err_free_ms;
66
67 single_buff_size = sample_size *
68 ((u64)args->read_period_samples * MS_READ_PERIOD_MULTIPLIER);
69 ms->bo = ivpu_bo_create_global(vdev, PAGE_ALIGN(single_buff_size * MS_NUM_BUFFERS),
70 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
71 if (!ms->bo) {
72 ivpu_err(vdev, "Failed to allocate MS buffer (size %llu)\n", single_buff_size);
73 ret = -ENOMEM;
74 goto err_free_ms;
75 }
76
77 ms->buff_size = ivpu_bo_size(ms->bo) / MS_NUM_BUFFERS;
78 ms->active_buff_vpu_addr = ms->bo->vpu_addr;
79 ms->inactive_buff_vpu_addr = ms->bo->vpu_addr + ms->buff_size;
80 ms->active_buff_ptr = ivpu_bo_vaddr(ms->bo);
81 ms->inactive_buff_ptr = ivpu_bo_vaddr(ms->bo) + ms->buff_size;
82
83 ret = ivpu_jsm_metric_streamer_start(vdev, ms->mask, args->sampling_period_ns,
84 ms->active_buff_vpu_addr, ms->buff_size);
85 if (ret)
86 goto err_free_bo;
87
88 args->sample_size = sample_size;
89 args->max_data_size = ivpu_bo_size(ms->bo);
90 list_add_tail(&ms->ms_instance_node, &file_priv->ms_instance_list);
91 goto unlock;
92
93err_free_bo:
94 ivpu_bo_free(ms->bo);
95err_free_ms:
96 kfree(ms);
97unlock:
98 mutex_unlock(&file_priv->ms_lock);
99 return ret;
100}
101
102static int
103copy_leftover_bytes(struct ivpu_ms_instance *ms,
104 void __user *user_ptr, u64 user_size, u64 *user_bytes_copied)
105{
106 u64 copy_bytes;
107
108 if (ms->leftover_bytes) {
109 copy_bytes = min(user_size - *user_bytes_copied, ms->leftover_bytes);
110 if (copy_to_user(user_ptr + *user_bytes_copied, ms->leftover_addr, copy_bytes))
111 return -EFAULT;
112
113 ms->leftover_bytes -= copy_bytes;
114 ms->leftover_addr += copy_bytes;
115 *user_bytes_copied += copy_bytes;
116 }
117
118 return 0;
119}
120
121static int
122copy_samples_to_user(struct ivpu_device *vdev, struct ivpu_ms_instance *ms,
123 void __user *user_ptr, u64 user_size, u64 *user_bytes_copied)
124{
125 u64 bytes_written;
126 int ret;
127
128 *user_bytes_copied = 0;
129
130 ret = copy_leftover_bytes(ms, user_ptr, user_size, user_bytes_copied);
131 if (ret)
132 return ret;
133
134 if (*user_bytes_copied == user_size)
135 return 0;
136
137 ret = ivpu_jsm_metric_streamer_update(vdev, ms->mask, ms->inactive_buff_vpu_addr,
138 ms->buff_size, &bytes_written);
139 if (ret)
140 return ret;
141
142 swap(ms->active_buff_vpu_addr, ms->inactive_buff_vpu_addr);
143 swap(ms->active_buff_ptr, ms->inactive_buff_ptr);
144
145 ms->leftover_bytes = bytes_written;
146 ms->leftover_addr = ms->inactive_buff_ptr;
147
148 return copy_leftover_bytes(ms, user_ptr, user_size, user_bytes_copied);
149}
150
151int ivpu_ms_get_data_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
152{
153 struct drm_ivpu_metric_streamer_get_data *args = data;
154 struct ivpu_file_priv *file_priv = file->driver_priv;
155 struct ivpu_device *vdev = file_priv->vdev;
156 struct ivpu_ms_instance *ms;
157 u64 bytes_written;
158 int ret;
159
160 if (!args->metric_group_mask)
161 return -EINVAL;
162
163 mutex_lock(&file_priv->ms_lock);
164
165 ms = get_instance_by_mask(file_priv, args->metric_group_mask);
166 if (!ms) {
167 ivpu_err(vdev, "Instance doesn't exist for mask: %#llx\n", args->metric_group_mask);
168 ret = -EINVAL;
169 goto unlock;
170 }
171
172 if (!args->buffer_size) {
173 ret = ivpu_jsm_metric_streamer_update(vdev, ms->mask, 0, 0, &bytes_written);
174 if (ret)
175 goto unlock;
176 args->data_size = bytes_written + ms->leftover_bytes;
177 goto unlock;
178 }
179
180 if (!args->buffer_ptr) {
181 ret = -EINVAL;
182 goto unlock;
183 }
184
185 ret = copy_samples_to_user(vdev, ms, u64_to_user_ptr(args->buffer_ptr),
186 args->buffer_size, &args->data_size);
187unlock:
188 mutex_unlock(&file_priv->ms_lock);
189
190 return ret;
191}
192
193static void free_instance(struct ivpu_file_priv *file_priv, struct ivpu_ms_instance *ms)
194{
195 lockdep_assert_held(&file_priv->ms_lock);
196
197 list_del(&ms->ms_instance_node);
198 ivpu_jsm_metric_streamer_stop(file_priv->vdev, ms->mask);
199 ivpu_bo_free(ms->bo);
200 kfree(ms);
201}
202
203int ivpu_ms_stop_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
204{
205 struct ivpu_file_priv *file_priv = file->driver_priv;
206 struct drm_ivpu_metric_streamer_stop *args = data;
207 struct ivpu_ms_instance *ms;
208
209 if (!args->metric_group_mask)
210 return -EINVAL;
211
212 mutex_lock(&file_priv->ms_lock);
213
214 ms = get_instance_by_mask(file_priv, args->metric_group_mask);
215 if (ms)
216 free_instance(file_priv, ms);
217
218 mutex_unlock(&file_priv->ms_lock);
219
220 return ms ? 0 : -EINVAL;
221}
222
223static inline struct ivpu_bo *get_ms_info_bo(struct ivpu_file_priv *file_priv)
224{
225 lockdep_assert_held(&file_priv->ms_lock);
226
227 if (file_priv->ms_info_bo)
228 return file_priv->ms_info_bo;
229
230 file_priv->ms_info_bo = ivpu_bo_create_global(file_priv->vdev, MS_INFO_BUFFER_SIZE,
231 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
232 return file_priv->ms_info_bo;
233}
234
235int ivpu_ms_get_info_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
236{
237 struct drm_ivpu_metric_streamer_get_data *args = data;
238 struct ivpu_file_priv *file_priv = file->driver_priv;
239 struct ivpu_device *vdev = file_priv->vdev;
240 struct ivpu_bo *bo;
241 u64 info_size;
242 int ret;
243
244 if (!args->metric_group_mask)
245 return -EINVAL;
246
247 if (!args->buffer_size)
248 return ivpu_jsm_metric_streamer_info(vdev, args->metric_group_mask,
249 0, 0, NULL, &args->data_size);
250 if (!args->buffer_ptr)
251 return -EINVAL;
252
253 mutex_lock(&file_priv->ms_lock);
254
255 bo = get_ms_info_bo(file_priv);
256 if (!bo) {
257 ret = -ENOMEM;
258 goto unlock;
259 }
260
261 ret = ivpu_jsm_metric_streamer_info(vdev, args->metric_group_mask, bo->vpu_addr,
262 ivpu_bo_size(bo), NULL, &info_size);
263 if (ret)
264 goto unlock;
265
266 if (args->buffer_size < info_size) {
267 ret = -ENOSPC;
268 goto unlock;
269 }
270
271 if (copy_to_user(u64_to_user_ptr(args->buffer_ptr), ivpu_bo_vaddr(bo), info_size))
272 ret = -EFAULT;
273
274 args->data_size = info_size;
275unlock:
276 mutex_unlock(&file_priv->ms_lock);
277
278 return ret;
279}
280
281void ivpu_ms_cleanup(struct ivpu_file_priv *file_priv)
282{
283 struct ivpu_ms_instance *ms, *tmp;
284
285 mutex_lock(&file_priv->ms_lock);
286
287 if (file_priv->ms_info_bo) {
288 ivpu_bo_free(file_priv->ms_info_bo);
289 file_priv->ms_info_bo = NULL;
290 }
291
292 list_for_each_entry_safe(ms, tmp, &file_priv->ms_instance_list, ms_instance_node)
293 free_instance(file_priv, ms);
294
295 mutex_unlock(&file_priv->ms_lock);
296}
297
298void ivpu_ms_cleanup_all(struct ivpu_device *vdev)
299{
300 struct ivpu_file_priv *file_priv;
301 unsigned long ctx_id;
302
303 mutex_lock(&vdev->context_list_lock);
304
305 xa_for_each(&vdev->context_xa, ctx_id, file_priv)
306 ivpu_ms_cleanup(file_priv);
307
308 mutex_unlock(&vdev->context_list_lock);
309}
drivers/accel/ivpu/ivpu_ms.h+36−0
@@ -0,0 +1,36 @@
1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5#ifndef __IVPU_MS_H__
6#define __IVPU_MS_H__
7
8#include <linux/list.h>
9
10struct drm_device;
11struct drm_file;
12struct ivpu_bo;
13struct ivpu_device;
14struct ivpu_file_priv;
15
16struct ivpu_ms_instance {
17 struct ivpu_bo *bo;
18 struct list_head ms_instance_node;
19 u64 mask;
20 u64 buff_size;
21 u64 active_buff_vpu_addr;
22 u64 inactive_buff_vpu_addr;
23 void *active_buff_ptr;
24 void *inactive_buff_ptr;
25 u64 leftover_bytes;
26 void *leftover_addr;
27};
28
29int ivpu_ms_start_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
30int ivpu_ms_stop_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
31int ivpu_ms_get_data_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
32int ivpu_ms_get_info_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
33void ivpu_ms_cleanup(struct ivpu_file_priv *file_priv);
34void ivpu_ms_cleanup_all(struct ivpu_device *vdev);
35
36#endif /* __IVPU_MS_H__ */
drivers/accel/ivpu/ivpu_pm.c+82−29
@@ -18,6 +18,7 @@ · 17 unmodified lines
18#include "ivpu_job.h"18#include "ivpu_job.h"
19#include "ivpu_jsm_msg.h"19#include "ivpu_jsm_msg.h"
20#include "ivpu_mmu.h"20#include "ivpu_mmu.h"
21#include "ivpu_ms.h"
21#include "ivpu_pm.h"22#include "ivpu_pm.h"
22 23
23static bool ivpu_disable_recovery;24static bool ivpu_disable_recovery;
@@ -131,6 +132,7 @@ static void ivpu_pm_recovery_work(struct work_struct *work) · 107 unmodified lines
131 ivpu_suspend(vdev);132 ivpu_suspend(vdev);
132 ivpu_pm_prepare_cold_boot(vdev);133 ivpu_pm_prepare_cold_boot(vdev);
133 ivpu_jobs_abort_all(vdev);134 ivpu_jobs_abort_all(vdev);
135 ivpu_ms_cleanup_all(vdev);
134 136
135 ret = ivpu_resume(vdev);137 ret = ivpu_resume(vdev);
136 if (ret)138 if (ret)
@@ -235,41 +237,37 @@ int ivpu_pm_runtime_suspend_cb(struct device *dev) · 98 unmodified lines
235{237{
236 struct drm_device *drm = dev_get_drvdata(dev);238 struct drm_device *drm = dev_get_drvdata(dev);
237 struct ivpu_device *vdev = to_ivpu_device(drm);239 struct ivpu_device *vdev = to_ivpu_device(drm);
238 bool hw_is_idle = true;240 int ret, ret_d0i3;
239 int ret;241 bool is_idle;
240 242
241 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));243 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));
242 drm_WARN_ON(&vdev->drm, work_pending(&vdev->pm->recovery_work));244 drm_WARN_ON(&vdev->drm, work_pending(&vdev->pm->recovery_work));
243 245
244 ivpu_dbg(vdev, PM, "Runtime suspend..\n");246 ivpu_dbg(vdev, PM, "Runtime suspend..\n");
245 247
246 if (!ivpu_hw_is_idle(vdev) && vdev->pm->suspend_reschedule_counter) {248 ivpu_mmu_disable(vdev);
247 ivpu_dbg(vdev, PM, "Failed to enter idle, rescheduling suspend, retries left %d\n",249
248 vdev->pm->suspend_reschedule_counter);250 is_idle = ivpu_hw_is_idle(vdev) || vdev->pm->dct_active_percent;
249 pm_schedule_suspend(dev, vdev->timeout.reschedule_suspend);251 if (!is_idle)
250 vdev->pm->suspend_reschedule_counter--;252 ivpu_err(vdev, "NPU is not idle before autosuspend\n");
251 return -EAGAIN;
252 }
253 253
254 if (!vdev->pm->suspend_reschedule_counter)254 ret_d0i3 = ivpu_jsm_pwr_d0i3_enter(vdev);
255 hw_is_idle = false;255 if (ret_d0i3)
256 else if (ivpu_jsm_pwr_d0i3_enter(vdev))256 ivpu_err(vdev, "Failed to prepare for d0i3: %d\n", ret_d0i3);
257 hw_is_idle = false;
258 257
259 ret = ivpu_suspend(vdev);258 ret = ivpu_suspend(vdev);
260 if (ret)259 if (ret)
261 ivpu_err(vdev, "Failed to suspend NPU: %d\n", ret);260 ivpu_err(vdev, "Failed to suspend NPU: %d\n", ret);
262 261
263 if (!hw_is_idle) {262 if (!is_idle || ret_d0i3) {
264 ivpu_err(vdev, "NPU failed to enter idle, force suspended.\n");263 ivpu_err(vdev, "Forcing cold boot due to previous errors\n");
264 atomic_inc(&vdev->pm->reset_counter);
265 ivpu_fw_log_dump(vdev);265 ivpu_fw_log_dump(vdev);
266 ivpu_pm_prepare_cold_boot(vdev);266 ivpu_pm_prepare_cold_boot(vdev);
267 } else {267 } else {
268 ivpu_pm_prepare_warm_boot(vdev);268 ivpu_pm_prepare_warm_boot(vdev);
269 }269 }
270 270
271 vdev->pm->suspend_reschedule_counter = PM_RESCHEDULE_LIMIT;
272
273 ivpu_dbg(vdev, PM, "Runtime suspend done.\n");271 ivpu_dbg(vdev, PM, "Runtime suspend done.\n");
274 272
275 return 0;273 return 0;
@@ -297,17 +295,6 @@ int ivpu_rpm_get(struct ivpu_device *vdev) · 21 unmodified lines
297 int ret;295 int ret;
298 296
299 ret = pm_runtime_resume_and_get(vdev->drm.dev);297 ret = pm_runtime_resume_and_get(vdev->drm.dev);
300 if (!drm_WARN_ON(&vdev->drm, ret < 0))
301 vdev->pm->suspend_reschedule_counter = PM_RESCHEDULE_LIMIT;
302
303 return ret;
304}
305
306int ivpu_rpm_get_if_active(struct ivpu_device *vdev)
307{
308 int ret;
309
310 ret = pm_runtime_get_if_in_use(vdev->drm.dev);
311 drm_WARN_ON(&vdev->drm, ret < 0);298 drm_WARN_ON(&vdev->drm, ret < 0);
312 299
313 return ret;300 return ret;
@@ -333,6 +320,8 @@ void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev) · 19 unmodified lines
333 ivpu_hw_reset(vdev);320 ivpu_hw_reset(vdev);
334 ivpu_pm_prepare_cold_boot(vdev);321 ivpu_pm_prepare_cold_boot(vdev);
335 ivpu_jobs_abort_all(vdev);322 ivpu_jobs_abort_all(vdev);
323 ivpu_ms_cleanup_all(vdev);
324
336 ivpu_dbg(vdev, PM, "Pre-reset done.\n");325 ivpu_dbg(vdev, PM, "Pre-reset done.\n");
337}326}
338 327
@@ -360,7 +349,6 @@ void ivpu_pm_init(struct ivpu_device *vdev) · 21 unmodified lines
360 int delay;349 int delay;
361 350
362 pm->vdev = vdev;351 pm->vdev = vdev;
363 pm->suspend_reschedule_counter = PM_RESCHEDULE_LIMIT;
364 352
365 init_rwsem(&pm->reset_lock);353 init_rwsem(&pm->reset_lock);
366 atomic_set(&pm->reset_pending, 0);354 atomic_set(&pm->reset_pending, 0);
@@ -401,3 +389,68 @@ void ivpu_pm_disable(struct ivpu_device *vdev) · 34 unmodified lines
401 pm_runtime_get_noresume(vdev->drm.dev);389 pm_runtime_get_noresume(vdev->drm.dev);
402 pm_runtime_forbid(vdev->drm.dev);390 pm_runtime_forbid(vdev->drm.dev);
403}391}
392
393int ivpu_pm_dct_init(struct ivpu_device *vdev)
394{
395 if (vdev->pm->dct_active_percent)
396 return ivpu_pm_dct_enable(vdev, vdev->pm->dct_active_percent);
397
398 return 0;
399}
400
401int ivpu_pm_dct_enable(struct ivpu_device *vdev, u8 active_percent)
402{
403 u32 active_us, inactive_us;
404 int ret;
405
406 if (active_percent == 0 || active_percent > 100)
407 return -EINVAL;
408
409 active_us = (DCT_PERIOD_US * active_percent) / 100;
410 inactive_us = DCT_PERIOD_US - active_us;
411
412 ret = ivpu_jsm_dct_enable(vdev, active_us, inactive_us);
413 if (ret) {
414 ivpu_err_ratelimited(vdev, "Filed to enable DCT: %d\n", ret);
415 return ret;
416 }
417
418 vdev->pm->dct_active_percent = active_percent;
419
420 ivpu_dbg(vdev, PM, "DCT set to %u%% (D0: %uus, D0i2: %uus)\n",
421 active_percent, active_us, inactive_us);
422 return 0;
423}
424
425int ivpu_pm_dct_disable(struct ivpu_device *vdev)
426{
427 int ret;
428
429 ret = ivpu_jsm_dct_disable(vdev);
430 if (ret) {
431 ivpu_err_ratelimited(vdev, "Filed to disable DCT: %d\n", ret);
432 return ret;
433 }
434
435 vdev->pm->dct_active_percent = 0;
436
437 ivpu_dbg(vdev, PM, "DCT disabled\n");
438 return 0;
439}
440
441void ivpu_pm_dct_irq_thread_handler(struct ivpu_device *vdev)
442{
443 bool enable;
444 int ret;
445
446 if (ivpu_hw_btrs_dct_get_request(vdev, &enable))
447 return;
448
449 if (vdev->pm->dct_active_percent)
450 ret = ivpu_pm_dct_enable(vdev, DCT_DEFAULT_ACTIVE_PERCENT);
451 else
452 ret = ivpu_pm_dct_disable(vdev);
453
454 if (!ret)
455 ivpu_hw_btrs_dct_set_status(vdev, enable, vdev->pm->dct_active_percent);
456}
drivers/accel/ivpu/ivpu_pm.h+7−3
@@ -1,6 +1,6 @@
1/* SPDX-License-Identifier: GPL-2.0-only */1/* SPDX-License-Identifier: GPL-2.0-only */
2/*2/*
3 * Copyright (C) 2020-2023 Intel Corporation3 * Copyright (C) 2020-2024 Intel Corporation
4 */4 */
5 5
6#ifndef __IVPU_PM_H__6#ifndef __IVPU_PM_H__
@@ -19,7 +19,7 @@ struct ivpu_pm_info { · 12 unmodified lines
19 atomic_t reset_counter;19 atomic_t reset_counter;
20 atomic_t reset_pending;20 atomic_t reset_pending;
21 bool is_warmboot;21 bool is_warmboot;
22 u32 suspend_reschedule_counter;22 u8 dct_active_percent;
23};23};
24 24
25void ivpu_pm_init(struct ivpu_device *vdev);25void ivpu_pm_init(struct ivpu_device *vdev);
@@ -36,11 +36,15 @@ void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev); · 10 unmodified lines
36void ivpu_pm_reset_done_cb(struct pci_dev *pdev);36void ivpu_pm_reset_done_cb(struct pci_dev *pdev);
37 37
38int __must_check ivpu_rpm_get(struct ivpu_device *vdev);38int __must_check ivpu_rpm_get(struct ivpu_device *vdev);
39int __must_check ivpu_rpm_get_if_active(struct ivpu_device *vdev);
40void ivpu_rpm_put(struct ivpu_device *vdev);39void ivpu_rpm_put(struct ivpu_device *vdev);
41 40
42void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason);41void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason);
43void ivpu_start_job_timeout_detection(struct ivpu_device *vdev);42void ivpu_start_job_timeout_detection(struct ivpu_device *vdev);
44void ivpu_stop_job_timeout_detection(struct ivpu_device *vdev);43void ivpu_stop_job_timeout_detection(struct ivpu_device *vdev);
45 44
45int ivpu_pm_dct_init(struct ivpu_device *vdev);
46int ivpu_pm_dct_enable(struct ivpu_device *vdev, u8 active_percent);
47int ivpu_pm_dct_disable(struct ivpu_device *vdev);
48void ivpu_pm_dct_irq_thread_handler(struct ivpu_device *vdev);
49
46#endif /* __IVPU_PM_H__ */50#endif /* __IVPU_PM_H__ */
drivers/accel/ivpu/ivpu_sysfs.c+58−0
@@ -0,0 +1,58 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2024 Intel Corporation
4 */
5
6#include <linux/device.h>
7#include <linux/err.h>
8
9#include "ivpu_hw.h"
10#include "ivpu_sysfs.h"
11
12/*
13 * npu_busy_time_us is the time that the device spent executing jobs.
14 * The time is counted when and only when there are jobs submitted to firmware.
15 *
16 * This time can be used to measure the utilization of NPU, either by calculating
17 * npu_busy_time_us difference between two timepoints (i.e. measuring the time
18 * that the NPU was active during some workload) or monitoring utilization percentage
19 * by reading npu_busy_time_us periodically.
20 *
21 * When reading the value periodically, it shouldn't be read too often as it may have
22 * an impact on job submission performance. Recommended period is 1 second.
23 */
24static ssize_t
25npu_busy_time_us_show(struct device *dev, struct device_attribute *attr, char *buf)
26{
27 struct drm_device *drm = dev_get_drvdata(dev);
28 struct ivpu_device *vdev = to_ivpu_device(drm);
29 ktime_t total, now = 0;
30
31 xa_lock(&vdev->submitted_jobs_xa);
32 total = vdev->busy_time;
33 if (!xa_empty(&vdev->submitted_jobs_xa))
34 now = ktime_sub(ktime_get(), vdev->busy_start_ts);
35 xa_unlock(&vdev->submitted_jobs_xa);
36
37 return sysfs_emit(buf, "%lld\n", ktime_to_us(ktime_add(total, now)));
38}
39
40static DEVICE_ATTR_RO(npu_busy_time_us);
41
42static struct attribute *ivpu_dev_attrs[] = {
43 &dev_attr_npu_busy_time_us.attr,
44 NULL,
45};
46
47static struct attribute_group ivpu_dev_attr_group = {
48 .attrs = ivpu_dev_attrs,
49};
50
51void ivpu_sysfs_init(struct ivpu_device *vdev)
52{
53 int ret;
54
55 ret = devm_device_add_group(vdev->drm.dev, &ivpu_dev_attr_group);
56 if (ret)
57 ivpu_warn(vdev, "Failed to add group to device, ret %d", ret);
58}
drivers/accel/ivpu/ivpu_sysfs.h+13−0
@@ -0,0 +1,13 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2024 Intel Corporation
4 */
5
6#ifndef __IVPU_SYSFS_H__
7#define __IVPU_SYSFS_H__
8
9#include "ivpu_drv.h"
10
11void ivpu_sysfs_init(struct ivpu_device *vdev);
12
13#endif /* __IVPU_SYSFS_H__ */
drivers/accel/ivpu/vpu_boot_api.h+14−2
@@ -27,7 +27,7 @@ · 26 unmodified lines
27 * Minor version changes when API backward compatibility is preserved.27 * Minor version changes when API backward compatibility is preserved.
28 * Resets to 0 if Major version is incremented.28 * Resets to 0 if Major version is incremented.
29 */29 */
30#define VPU_BOOT_API_VER_MINOR 2230#define VPU_BOOT_API_VER_MINOR 24
31 31
32/*32/*
33 * API header changed (field names, documentation, formatting) but API itself has not been changed33 * API header changed (field names, documentation, formatting) but API itself has not been changed
@@ -80,6 +80,11 @@ struct vpu_firmware_header { · 46 unmodified lines
80 u32 preemption_buffer_2_size;80 u32 preemption_buffer_2_size;
81 /* Space reserved for future preemption-related fields. */81 /* Space reserved for future preemption-related fields. */
82 u32 preemption_reserved[6];82 u32 preemption_reserved[6];
83 /* FW image read only section start address, 4KB aligned */
84 u64 ro_section_start_address;
85 /* FW image read only section size, 4KB aligned */
86 u32 ro_section_size;
87 u32 reserved;
83};88};
84 89
85/*90/*
@@ -333,7 +338,14 @@ struct vpu_boot_params { · 247 unmodified lines
333 * The KMD is required to update this value on every VPU reset.338 * The KMD is required to update this value on every VPU reset.
334 */339 */
335 u64 system_time_us;340 u64 system_time_us;
336 u32 pad4[18];341 u32 pad4[2];
342 /*
343 * The delta between device monotonic time and the current value of the
344 * HW timestamp register, in ticks. Written by the firmware during boot.
345 * Can be used by the KMD to calculate device time.
346 */
347 u64 device_time_delta_ticks;
348 u32 pad7[14];
337 /* Warm boot information: 0x400 - 0x43F */349 /* Warm boot information: 0x400 - 0x43F */
338 u32 warm_boot_sections_count;350 u32 warm_boot_sections_count;
339 u32 warm_boot_start_address_reference;351 u32 warm_boot_start_address_reference;
drivers/accel/ivpu/vpu_jsm_api.h+11−3
@@ -1,6 +1,6 @@
1/* SPDX-License-Identifier: MIT */1/* SPDX-License-Identifier: MIT */
2/*2/*
3 * Copyright (c) 2020-2023, Intel Corporation.3 * Copyright (c) 2020-2024, Intel Corporation.
4 */4 */
5 5
6/**6/**
@@ -22,12 +22,12 @@ · 15 unmodified lines
22/*22/*
23 * Minor version changes when API backward compatibility is preserved.23 * Minor version changes when API backward compatibility is preserved.
24 */24 */
25#define VPU_JSM_API_VER_MINOR 1525#define VPU_JSM_API_VER_MINOR 16
26 26
27/*27/*
28 * API header changed (field names, documentation, formatting) but API itself has not been changed28 * API header changed (field names, documentation, formatting) but API itself has not been changed
29 */29 */
30#define VPU_JSM_API_VER_PATCH 630#define VPU_JSM_API_VER_PATCH 0
31 31
32/*32/*
33 * Index in the API version table33 * Index in the API version table
@@ -868,6 +868,14 @@ struct vpu_ipc_msg_payload_hws_set_scheduling_log { · 834 unmodified lines
868 * is generated when an event log is written to this index.868 * is generated when an event log is written to this index.
869 */869 */
870 u64 notify_index;870 u64 notify_index;
871 /*
872 * Enable extra events to be output to log for debug of scheduling algorithm.
873 * Interpreted by VPU as a boolean to enable or disable, expected values are
874 * 0 and 1.
875 */
876 u32 enable_extra_events;
877 /* Zero Padding */
878 u32 reserved_0;
871};879};
872 880
873/*881/*
drivers/char/agp/amd64-agp.c+1−0
@@ -802,4 +802,5 @@ module_exit(agp_amd64_cleanup); · 801 unmodified lines
802 802
803MODULE_AUTHOR("Dave Jones, Andi Kleen");803MODULE_AUTHOR("Dave Jones, Andi Kleen");
804module_param(agp_try_unsupported, bool, 0);804module_param(agp_try_unsupported, bool, 0);
805MODULE_DESCRIPTION("GART driver for the AMD Opteron/Athlon64 on-CPU northbridge");
805MODULE_LICENSE("GPL");806MODULE_LICENSE("GPL");
drivers/char/agp/intel-agp.c+2−1
@@ -12,7 +12,7 @@ · 11 unmodified lines
12#include <asm/smp.h>12#include <asm/smp.h>
13#include "agp.h"13#include "agp.h"
14#include "intel-agp.h"14#include "intel-agp.h"
15#include <drm/intel-gtt.h>15#include <drm/intel/intel-gtt.h>
16 16
17static int intel_fetch_size(void)17static int intel_fetch_size(void)
18{18{
@@ -920,4 +920,5 @@ module_init(agp_intel_init); · 901 unmodified lines
920module_exit(agp_intel_cleanup);920module_exit(agp_intel_cleanup);
921 921
922MODULE_AUTHOR("Dave Jones, Various @Intel");922MODULE_AUTHOR("Dave Jones, Various @Intel");
923MODULE_DESCRIPTION("Intel AGPGART routines");
923MODULE_LICENSE("GPL and additional rights");924MODULE_LICENSE("GPL and additional rights");
drivers/char/agp/intel-gtt.c+2−1
@@ -25,7 +25,7 @@ · 24 unmodified lines
25#include <asm/smp.h>25#include <asm/smp.h>
26#include "agp.h"26#include "agp.h"
27#include "intel-agp.h"27#include "intel-agp.h"
28#include <drm/intel-gtt.h>28#include <drm/intel/intel-gtt.h>
29#include <asm/set_memory.h>29#include <asm/set_memory.h>
30 30
31/*31/*
@@ -1461,4 +1461,5 @@ void intel_gmch_remove(void) · 1429 unmodified lines
1461EXPORT_SYMBOL(intel_gmch_remove);1461EXPORT_SYMBOL(intel_gmch_remove);
1462 1462
1463MODULE_AUTHOR("Dave Jones, Various @Intel");1463MODULE_AUTHOR("Dave Jones, Various @Intel");
1464MODULE_DESCRIPTION("Intel GTT (Graphics Translation Table) routines");
1464MODULE_LICENSE("GPL and additional rights");1465MODULE_LICENSE("GPL and additional rights");
drivers/char/agp/sis-agp.c+1−0
@@ -433,4 +433,5 @@ module_param(agp_sis_force_delay, bool, 0); · 432 unmodified lines
433MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack");433MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack");
434module_param(agp_sis_agp_spec, int, 0);434module_param(agp_sis_agp_spec, int, 0);
435MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect");435MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect");
436MODULE_DESCRIPTION("SiS AGPGART routines");
436MODULE_LICENSE("GPL and additional rights");437MODULE_LICENSE("GPL and additional rights");
drivers/char/agp/via-agp.c+1−0
@@ -575,5 +575,6 @@ static void __exit agp_via_cleanup(void) · 574 unmodified lines
575module_init(agp_via_init);575module_init(agp_via_init);
576module_exit(agp_via_cleanup);576module_exit(agp_via_cleanup);
577 577
578MODULE_DESCRIPTION("VIA AGPGART routines");
578MODULE_LICENSE("GPL");579MODULE_LICENSE("GPL");
579MODULE_AUTHOR("Dave Jones");580MODULE_AUTHOR("Dave Jones");
drivers/dma-buf/dma-fence-array.c+4−6
@@ -70,7 +70,7 @@ static void dma_fence_array_cb_func(struct dma_fence *f, · 69 unmodified lines
70static bool dma_fence_array_enable_signaling(struct dma_fence *fence)70static bool dma_fence_array_enable_signaling(struct dma_fence *fence)
71{71{
72 struct dma_fence_array *array = to_dma_fence_array(fence);72 struct dma_fence_array *array = to_dma_fence_array(fence);
73 struct dma_fence_array_cb *cb = (void *)(&array[1]);73 struct dma_fence_array_cb *cb = array->callbacks;
74 unsigned i;74 unsigned i;
75 75
76 for (i = 0; i < array->num_fences; ++i) {76 for (i = 0; i < array->num_fences; ++i) {
@@ -168,22 +168,20 @@ struct dma_fence_array *dma_fence_array_create(int num_fences, · 91 unmodified lines
168 bool signal_on_any)168 bool signal_on_any)
169{169{
170 struct dma_fence_array *array;170 struct dma_fence_array *array;
171 size_t size = sizeof(*array);
172 171
173 WARN_ON(!num_fences || !fences);172 WARN_ON(!num_fences || !fences);
174 173
175 /* Allocate the callback structures behind the array. */174 array = kzalloc(struct_size(array, callbacks, num_fences), GFP_KERNEL);
176 size += num_fences * sizeof(struct dma_fence_array_cb);
177 array = kzalloc(size, GFP_KERNEL);
178 if (!array)175 if (!array)
179 return NULL;176 return NULL;
180 177
178 array->num_fences = num_fences;
179
181 spin_lock_init(&array->lock);180 spin_lock_init(&array->lock);
182 dma_fence_init(&array->base, &dma_fence_array_ops, &array->lock,181 dma_fence_init(&array->base, &dma_fence_array_ops, &array->lock,
183 context, seqno);182 context, seqno);
184 init_irq_work(&array->work, irq_dma_fence_array_work);183 init_irq_work(&array->work, irq_dma_fence_array_work);
185 184
186 array->num_fences = num_fences;
187 atomic_set(&array->num_pending, signal_on_any ? 1 : num_fences);185 atomic_set(&array->num_pending, signal_on_any ? 1 : num_fences);
188 array->fences = fences;186 array->fences = fences;
189 187
drivers/dma-buf/dma-heap.c+2−2
@@ -50,8 +50,8 @@ static struct class *dma_heap_class; · 49 unmodified lines
50static DEFINE_XARRAY_ALLOC(dma_heap_minors);50static DEFINE_XARRAY_ALLOC(dma_heap_minors);
51 51
52static int dma_heap_buffer_alloc(struct dma_heap *heap, size_t len,52static int dma_heap_buffer_alloc(struct dma_heap *heap, size_t len,
53 unsigned int fd_flags,53 u32 fd_flags,
54 unsigned int heap_flags)54 u64 heap_flags)
55{55{
56 struct dma_buf *dmabuf;56 struct dma_buf *dmabuf;
57 int fd;57 int fd;
drivers/dma-buf/dma-resv.c+7−0
@@ -186,6 +186,13 @@ int dma_resv_reserve_fences(struct dma_resv *obj, unsigned int num_fences) · 185 unmodified lines
186 186
187 dma_resv_assert_held(obj);187 dma_resv_assert_held(obj);
188 188
189 /* Driver and component code should never call this function with
190 * num_fences=0. If they do it usually points to bugs when calculating
191 * the number of needed fences dynamically.
192 */
193 if (WARN_ON(!num_fences))
194 return -EINVAL;
195
189 old = dma_resv_fences_list(obj);196 old = dma_resv_fences_list(obj);
190 if (old && old->max_fences) {197 if (old && old->max_fences) {
191 if ((old->num_fences + num_fences) <= old->max_fences)198 if ((old->num_fences + num_fences) <= old->max_fences)
drivers/dma-buf/heaps/cma_heap.c+2−2
@@ -274,8 +274,8 @@ static const struct dma_buf_ops cma_heap_buf_ops = { · 273 unmodified lines
274 274
275static struct dma_buf *cma_heap_allocate(struct dma_heap *heap,275static struct dma_buf *cma_heap_allocate(struct dma_heap *heap,
276 unsigned long len,276 unsigned long len,
277 unsigned long fd_flags,277 u32 fd_flags,
278 unsigned long heap_flags)278 u64 heap_flags)
279{279{
280 struct cma_heap *cma_heap = dma_heap_get_drvdata(heap);280 struct cma_heap *cma_heap = dma_heap_get_drvdata(heap);
281 struct cma_heap_buffer *buffer;281 struct cma_heap_buffer *buffer;
drivers/dma-buf/heaps/system_heap.c+2−2
@@ -333,8 +333,8 @@ static struct page *alloc_largest_available(unsigned long size, · 332 unmodified lines
333 333
334static struct dma_buf *system_heap_allocate(struct dma_heap *heap,334static struct dma_buf *system_heap_allocate(struct dma_heap *heap,
335 unsigned long len,335 unsigned long len,
336 unsigned long fd_flags,336 u32 fd_flags,
337 unsigned long heap_flags)337 u64 heap_flags)
338{338{
339 struct system_heap_buffer *buffer;339 struct system_heap_buffer *buffer;
340 DEFINE_DMA_BUF_EXPORT_INFO(exp_info);340 DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
drivers/gpu/drm/Kconfig+15−1
@@ -79,6 +79,7 @@ config DRM_KUNIT_TEST · 78 unmodified lines
79 depends on DRM && KUNIT && MMU79 depends on DRM && KUNIT && MMU
80 select DRM_BUDDY80 select DRM_BUDDY
81 select DRM_DISPLAY_DP_HELPER81 select DRM_DISPLAY_DP_HELPER
82 select DRM_DISPLAY_HDMI_STATE_HELPER
82 select DRM_DISPLAY_HELPER83 select DRM_DISPLAY_HELPER
83 select DRM_EXEC84 select DRM_EXEC
84 select DRM_EXPORT_FOR_TESTS if m85 select DRM_EXPORT_FOR_TESTS if m
@@ -106,7 +107,7 @@ config DRM_KMS_HELPER · 21 unmodified lines
106 107
107config DRM_PANIC108config DRM_PANIC
108 bool "Display a user-friendly message when a kernel panic occurs"109 bool "Display a user-friendly message when a kernel panic occurs"
109 depends on DRM && !FRAMEBUFFER_CONSOLE110 depends on DRM && !(FRAMEBUFFER_CONSOLE && VT_CONSOLE)
110 select DRM_KMS_HELPER111 select DRM_KMS_HELPER
111 select FONT_SUPPORT112 select FONT_SUPPORT
112 help113 help
@@ -136,6 +137,19 @@ config DRM_PANIC_DEBUG · 23 unmodified lines
136 This is unsafe and should not be enabled on a production build.137 This is unsafe and should not be enabled on a production build.
137 If in doubt, say "N".138 If in doubt, say "N".
138 139
140config DRM_PANIC_SCREEN
141 string "Panic screen formater"
142 default "user"
143 depends on DRM_PANIC
144 help
145 This option enable to choose what will be displayed when a kernel
146 panic occurs. You can choose between "user", a short message telling
147 the user to reboot the system, or "kmsg" which will display the last
148 lines of kmsg.
149 This can also be overridden by drm.panic_screen=xxxx kernel parameter
150 or by writing to /sys/module/drm/parameters/panic_screen sysfs entry
151 Default is "user"
152
139config DRM_DEBUG_DP_MST_TOPOLOGY_REFS153config DRM_DEBUG_DP_MST_TOPOLOGY_REFS
140 bool "Enable refcount backtrace history in the DP MST helpers"154 bool "Enable refcount backtrace history in the DP MST helpers"
141 depends on STACKTRACE_SUPPORT155 depends on STACKTRACE_SUPPORT
drivers/gpu/drm/Makefile+3−3
@@ -108,6 +108,7 @@ drm_dma_helper-$(CONFIG_DRM_KMS_HELPER) += drm_fb_dma_helper.o · 107 unmodified lines
108obj-$(CONFIG_DRM_GEM_DMA_HELPER) += drm_dma_helper.o108obj-$(CONFIG_DRM_GEM_DMA_HELPER) += drm_dma_helper.o
109 109
110drm_shmem_helper-y := drm_gem_shmem_helper.o110drm_shmem_helper-y := drm_gem_shmem_helper.o
111drm_shmem_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fbdev_shmem.o
111obj-$(CONFIG_DRM_GEM_SHMEM_HELPER) += drm_shmem_helper.o112obj-$(CONFIG_DRM_GEM_SHMEM_HELPER) += drm_shmem_helper.o
112 113
113drm_suballoc_helper-y := drm_suballoc.o114drm_suballoc_helper-y := drm_suballoc.o
@@ -117,6 +118,7 @@ drm_vram_helper-y := drm_gem_vram_helper.o · 3 unmodified lines
117obj-$(CONFIG_DRM_VRAM_HELPER) += drm_vram_helper.o118obj-$(CONFIG_DRM_VRAM_HELPER) += drm_vram_helper.o
118 119
119drm_ttm_helper-y := drm_gem_ttm_helper.o120drm_ttm_helper-y := drm_gem_ttm_helper.o
121drm_ttm_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fbdev_ttm.o
120obj-$(CONFIG_DRM_TTM_HELPER) += drm_ttm_helper.o122obj-$(CONFIG_DRM_TTM_HELPER) += drm_ttm_helper.o
121 123
122#124#
@@ -142,9 +144,7 @@ drm_kms_helper-y := \ · 19 unmodified lines
142 drm_self_refresh_helper.o \144 drm_self_refresh_helper.o \
143 drm_simple_kms_helper.o145 drm_simple_kms_helper.o
144drm_kms_helper-$(CONFIG_DRM_PANEL_BRIDGE) += bridge/panel.o146drm_kms_helper-$(CONFIG_DRM_PANEL_BRIDGE) += bridge/panel.o
145drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += \147drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o
146 drm_fbdev_generic.o \
147 drm_fb_helper.o
148obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o148obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o
149 149
150#150#
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c+0−16
@@ -246,22 +246,6 @@ amdgpu_connector_find_encoder(struct drm_connector *connector, · 245 unmodified lines
246 return NULL;246 return NULL;
247}247}
248 248
249struct edid *amdgpu_connector_edid(struct drm_connector *connector)
250{
251 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
252 struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
253
254 if (amdgpu_connector->edid) {
255 return amdgpu_connector->edid;
256 } else if (edid_blob) {
257 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
258
259 if (edid)
260 amdgpu_connector->edid = edid;
261 }
262 return amdgpu_connector->edid;
263}
264
265static struct edid *249static struct edid *
266amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)250amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
267{251{
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h+0−1
@@ -24,7 +24,6 @@ · 23 unmodified lines
24#ifndef __AMDGPU_CONNECTORS_H__24#ifndef __AMDGPU_CONNECTORS_H__
25#define __AMDGPU_CONNECTORS_H__25#define __AMDGPU_CONNECTORS_H__
26 26
27struct edid *amdgpu_connector_edid(struct drm_connector *connector);
28void amdgpu_connector_hotplug(struct drm_connector *connector);27void amdgpu_connector_hotplug(struct drm_connector *connector);
29int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector);28int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector);
30u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);29u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+3−3
@@ -24,7 +24,7 @@ · 23 unmodified lines
24 24
25#include <drm/amdgpu_drm.h>25#include <drm/amdgpu_drm.h>
26#include <drm/drm_drv.h>26#include <drm/drm_drv.h>
27#include <drm/drm_fbdev_generic.h>27#include <drm/drm_fbdev_ttm.h>
28#include <drm/drm_gem.h>28#include <drm/drm_gem.h>
29#include <drm/drm_managed.h>29#include <drm/drm_managed.h>
30#include <drm/drm_pciids.h>30#include <drm/drm_pciids.h>
@@ -2346,9 +2346,9 @@ retry_init: · 2315 unmodified lines
2346 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {2346 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2347 /* select 8 bpp console on low vram cards */2347 /* select 8 bpp console on low vram cards */
2348 if (adev->gmc.real_vram_size <= (32*1024*1024))2348 if (adev->gmc.real_vram_size <= (32*1024*1024))
2349 drm_fbdev_generic_setup(adev_to_drm(adev), 8);2349 drm_fbdev_ttm_setup(adev_to_drm(adev), 8);
2350 else2350 else
2351 drm_fbdev_generic_setup(adev_to_drm(adev), 32);2351 drm_fbdev_ttm_setup(adev_to_drm(adev), 32);
2352 }2352 }
2353 2353
2354 ret = amdgpu_debugfs_init(adev);2354 ret = amdgpu_debugfs_init(adev);
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c+2−6
@@ -65,9 +65,7 @@ static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) · 64 unmodified lines
65 65
66static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc)66static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc)
67{67{
68 struct drm_device *dev = crtc->dev;68 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
69 unsigned int pipe = drm_crtc_index(crtc);
70 struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
71 struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc);69 struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc);
72 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);70 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
73 71
@@ -91,10 +89,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, · 17 unmodified lines
91 ktime_t *vblank_time,89 ktime_t *vblank_time,
92 bool in_vblank_irq)90 bool in_vblank_irq)
93{91{
94 struct drm_device *dev = crtc->dev;
95 unsigned int pipe = crtc->index;
96 struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc);92 struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc);
97 struct drm_vblank_crtc *vblank = &dev->vblank[pipe];93 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
98 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);94 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
99 95
100 if (!READ_ONCE(vblank->enabled)) {96 if (!READ_ONCE(vblank->enabled)) {
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c+2−2
@@ -1299,7 +1299,7 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder · 1298 unmodified lines
1299 return;1299 return;
1300 }1300 }
1301 1301
1302 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);1302 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb);
1303 if (sad_count < 0) {1303 if (sad_count < 0) {
1304 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);1304 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1305 sad_count = 0;1305 sad_count = 0;
@@ -1369,7 +1369,7 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) · 63 unmodified lines
1369 return;1369 return;
1370 }1370 }
1371 1371
1372 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);1372 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads);
1373 if (sad_count < 0)1373 if (sad_count < 0)
1374 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);1374 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1375 if (sad_count <= 0)1375 if (sad_count <= 0)
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c+2−2
@@ -1331,7 +1331,7 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder · 1330 unmodified lines
1331 return;1331 return;
1332 }1332 }
1333 1333
1334 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);1334 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb);
1335 if (sad_count < 0) {1335 if (sad_count < 0) {
1336 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);1336 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1337 sad_count = 0;1337 sad_count = 0;
@@ -1401,7 +1401,7 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) · 63 unmodified lines
1401 return;1401 return;
1402 }1402 }
1403 1403
1404 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);1404 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads);
1405 if (sad_count < 0)1405 if (sad_count < 0)
1406 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);1406 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1407 if (sad_count <= 0)1407 if (sad_count <= 0)
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c+2−2
@@ -1217,7 +1217,7 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) · 1216 unmodified lines
1217 return;1217 return;
1218 }1218 }
1219 1219
1220 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);1220 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb);
1221 if (sad_count < 0) {1221 if (sad_count < 0) {
1222 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);1222 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1223 sad_count = 0;1223 sad_count = 0;
@@ -1292,7 +1292,7 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) · 68 unmodified lines
1292 return;1292 return;
1293 }1293 }
1294 1294
1295 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);1295 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads);
1296 if (sad_count < 0)1296 if (sad_count < 0)
1297 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);1297 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1298 if (sad_count <= 0)1298 if (sad_count <= 0)
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c+2−2
@@ -1272,7 +1272,7 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) · 1271 unmodified lines
1272 return;1272 return;
1273 }1273 }
1274 1274
1275 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);1275 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb);
1276 if (sad_count < 0) {1276 if (sad_count < 0) {
1277 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);1277 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1278 sad_count = 0;1278 sad_count = 0;
@@ -1340,7 +1340,7 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) · 61 unmodified lines
1340 return;1340 return;
1341 }1341 }
1342 1342
1343 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);1343 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads);
1344 if (sad_count < 0)1344 if (sad_count < 0)
1345 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);1345 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1346 if (sad_count <= 0)1346 if (sad_count <= 0)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+1−1
@@ -534,7 +534,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) · 533 unmodified lines
534 if (acrtc) {534 if (acrtc) {
535 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);535 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
536 drm_dev = acrtc->base.dev;536 drm_dev = acrtc->base.dev;
537 vblank = &drm_dev->vblank[acrtc->base.index];537 vblank = drm_crtc_vblank_crtc(&acrtc->base);
538 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);538 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
539 frame_duration_ns = vblank->time - previous_timestamp;539 frame_duration_ns = vblank->time - previous_timestamp;
540 540
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c+35−14
@@ -5,6 +5,7 @@ · 4 unmodified lines
5 *5 *
6 */6 */
7#include <linux/clk.h>7#include <linux/clk.h>
8#include <linux/of.h>
8#include <linux/pm_runtime.h>9#include <linux/pm_runtime.h>
9#include <linux/spinlock.h>10#include <linux/spinlock.h>
10 11
@@ -294,7 +295,6 @@ komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc, · 283 unmodified lines
294 struct komeda_dev *mdev = kcrtc->master->mdev;295 struct komeda_dev *mdev = kcrtc->master->mdev;
295 struct completion *flip_done;296 struct completion *flip_done;
296 struct completion temp;297 struct completion temp;
297 int timeout;
298 298
299 /* if caller doesn't send a flip_done, use a private flip_done */299 /* if caller doesn't send a flip_done, use a private flip_done */
300 if (input_flip_done) {300 if (input_flip_done) {
@@ -308,8 +308,7 @@ komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc, · 7 unmodified lines
308 mdev->funcs->flush(mdev, kcrtc->master->id, 0);308 mdev->funcs->flush(mdev, kcrtc->master->id, 0);
309 309
310 /* wait the flip take affect.*/310 /* wait the flip take affect.*/
311 timeout = wait_for_completion_timeout(flip_done, HZ);311 if (wait_for_completion_timeout(flip_done, HZ) == 0) {
312 if (timeout == 0) {
313 DRM_ERROR("wait pipe%d flip done timeout\n", kcrtc->master->id);312 DRM_ERROR("wait pipe%d flip done timeout\n", kcrtc->master->id);
314 if (!input_flip_done) {313 if (!input_flip_done) {
315 unsigned long flags;314 unsigned long flags;
@@ -610,12 +609,34 @@ get_crtc_primary(struct komeda_kms_dev *kms, struct komeda_crtc *crtc) · 294 unmodified lines
610 return NULL;609 return NULL;
611}610}
612 611
612static int komeda_attach_bridge(struct device *dev,
613 struct komeda_pipeline *pipe,
614 struct drm_encoder *encoder)
615{
616 struct drm_bridge *bridge;
617 int err;
618
619 bridge = devm_drm_of_get_bridge(dev, pipe->of_node,
620 KOMEDA_OF_PORT_OUTPUT, 0);
621 if (IS_ERR(bridge))
622 return dev_err_probe(dev, PTR_ERR(bridge), "remote bridge not found for pipe: %s\n",
623 of_node_full_name(pipe->of_node));
624
625 err = drm_bridge_attach(encoder, bridge, NULL, 0);
626 if (err)
627 dev_err(dev, "bridge_attach() failed for pipe: %s\n",
628 of_node_full_name(pipe->of_node));
629
630 return err;
631}
632
613static int komeda_crtc_add(struct komeda_kms_dev *kms,633static int komeda_crtc_add(struct komeda_kms_dev *kms,
614 struct komeda_crtc *kcrtc)634 struct komeda_crtc *kcrtc)
615{635{
616 struct drm_crtc *crtc = &kcrtc->base;636 struct drm_crtc *crtc = &kcrtc->base;
617 struct drm_device *base = &kms->base;637 struct drm_device *base = &kms->base;
618 struct drm_bridge *bridge;638 struct komeda_pipeline *pipe = kcrtc->master;
639 struct drm_encoder *encoder = &kcrtc->encoder;
619 int err;640 int err;
620 641
621 err = drm_crtc_init_with_planes(base, crtc,642 err = drm_crtc_init_with_planes(base, crtc,
@@ -626,27 +647,27 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms, · 4 unmodified lines
626 647
627 drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs);648 drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs);
628 649
629 crtc->port = kcrtc->master->of_output_port;650 crtc->port = pipe->of_output_port;
630 651
631 /* Construct an encoder for each pipeline and attach it to the remote652 /* Construct an encoder for each pipeline and attach it to the remote
632 * bridge653 * bridge
633 */654 */
634 kcrtc->encoder.possible_crtcs = drm_crtc_mask(crtc);655 kcrtc->encoder.possible_crtcs = drm_crtc_mask(crtc);
635 err = drm_simple_encoder_init(base, &kcrtc->encoder,656 err = drm_simple_encoder_init(base, encoder, DRM_MODE_ENCODER_TMDS);
636 DRM_MODE_ENCODER_TMDS);
637 if (err)657 if (err)
638 return err;658 return err;
639 659
640 bridge = devm_drm_of_get_bridge(base->dev, kcrtc->master->of_node,660 if (pipe->of_output_links[0]) {
641 KOMEDA_OF_PORT_OUTPUT, 0);661 err = komeda_attach_bridge(base->dev, pipe, encoder);
642 if (IS_ERR(bridge))662 if (err)
643 return PTR_ERR(bridge);663 return err;
644 664 }
645 err = drm_bridge_attach(&kcrtc->encoder, bridge, NULL, 0);
646 665
647 drm_crtc_enable_color_mgmt(crtc, 0, true, KOMEDA_COLOR_LUT_SIZE);666 drm_crtc_enable_color_mgmt(crtc, 0, true, KOMEDA_COLOR_LUT_SIZE);
648 667
649 return err;668 komeda_pipeline_dump(pipe);
669
670 return 0;
650}671}
651 672
652int komeda_kms_add_crtcs(struct komeda_kms_dev *kms, struct komeda_dev *mdev)673int komeda_kms_add_crtcs(struct komeda_kms_dev *kms, struct komeda_dev *mdev)
drivers/gpu/drm/arm/display/komeda/komeda_drv.c+6−2
@@ -9,7 +9,7 @@ · 8 unmodified lines
9#include <linux/of.h>9#include <linux/of.h>
10#include <linux/platform_device.h>10#include <linux/platform_device.h>
11#include <linux/pm_runtime.h>11#include <linux/pm_runtime.h>
12#include <drm/drm_fbdev_generic.h>12#include <drm/drm_fbdev_dma.h>
13#include <drm/drm_module.h>13#include <drm/drm_module.h>
14#include <drm/drm_of.h>14#include <drm/drm_of.h>
15#include "komeda_dev.h"15#include "komeda_dev.h"
@@ -59,6 +59,10 @@ static int komeda_platform_probe(struct platform_device *pdev) · 43 unmodified lines
59 struct komeda_drv *mdrv;59 struct komeda_drv *mdrv;
60 int err;60 int err;
61 61
62 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
63 if (err)
64 return dev_err_probe(dev, err, "DMA mask error\n");
65
62 mdrv = devm_kzalloc(dev, sizeof(*mdrv), GFP_KERNEL);66 mdrv = devm_kzalloc(dev, sizeof(*mdrv), GFP_KERNEL);
63 if (!mdrv)67 if (!mdrv)
64 return -ENOMEM;68 return -ENOMEM;
@@ -80,7 +84,7 @@ static int komeda_platform_probe(struct platform_device *pdev) · 15 unmodified lines
80 }84 }
81 85
82 dev_set_drvdata(dev, mdrv);86 dev_set_drvdata(dev, mdrv);
83 drm_fbdev_generic_setup(&mdrv->kms->base, 32);87 drm_fbdev_dma_setup(&mdrv->kms->base, 32);
84 88
85 return 0;89 return 0;
86 90
drivers/gpu/drm/arm/display/komeda/komeda_kms.h+1−0
@@ -191,5 +191,6 @@ void komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc, · 190 unmodified lines
191struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev);191struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev);
192void komeda_kms_detach(struct komeda_kms_dev *kms);192void komeda_kms_detach(struct komeda_kms_dev *kms);
193void komeda_kms_shutdown(struct komeda_kms_dev *kms);193void komeda_kms_shutdown(struct komeda_kms_dev *kms);
194void komeda_pipeline_dump(struct komeda_pipeline *pipe);
194 195
195#endif /*_KOMEDA_KMS_H_*/196#endif /*_KOMEDA_KMS_H_*/
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c+2−2
@@ -10,6 +10,7 @@ · 9 unmodified lines
10#include <drm/drm_print.h>10#include <drm/drm_print.h>
11 11
12#include "komeda_dev.h"12#include "komeda_dev.h"
13#include "komeda_kms.h"
13#include "komeda_pipeline.h"14#include "komeda_pipeline.h"
14 15
15/** komeda_pipeline_add - Add a pipeline to &komeda_dev */16/** komeda_pipeline_add - Add a pipeline to &komeda_dev */
@@ -247,7 +248,7 @@ static void komeda_component_dump(struct komeda_component *c) · 231 unmodified lines
247 c->max_active_outputs, c->supported_outputs);248 c->max_active_outputs, c->supported_outputs);
248}249}
249 250
250static void komeda_pipeline_dump(struct komeda_pipeline *pipe)251void komeda_pipeline_dump(struct komeda_pipeline *pipe)
251{252{
252 struct komeda_component *c;253 struct komeda_component *c;
253 int id;254 int id;
@@ -351,7 +352,6 @@ int komeda_assemble_pipelines(struct komeda_dev *mdev) · 97 unmodified lines
351 pipe = mdev->pipelines[i];352 pipe = mdev->pipelines[i];
352 353
353 komeda_pipeline_assemble(pipe);354 komeda_pipeline_assemble(pipe);
354 komeda_pipeline_dump(pipe);
355 }355 }
356 356
357 return 0;357 return 0;
drivers/gpu/drm/ast/ast_drv.c+2−2
@@ -33,7 +33,7 @@ · 32 unmodified lines
33#include <drm/drm_aperture.h>33#include <drm/drm_aperture.h>
34#include <drm/drm_atomic_helper.h>34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_drv.h>35#include <drm/drm_drv.h>
36#include <drm/drm_fbdev_generic.h>36#include <drm/drm_fbdev_shmem.h>
37#include <drm/drm_gem_shmem_helper.h>37#include <drm/drm_gem_shmem_helper.h>
38#include <drm/drm_module.h>38#include <drm/drm_module.h>
39#include <drm/drm_probe_helper.h>39#include <drm/drm_probe_helper.h>
@@ -360,7 +360,7 @@ static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) · 320 unmodified lines
360 if (ret)360 if (ret)
361 return ret;361 return ret;
362 362
363 drm_fbdev_generic_setup(drm, 32);363 drm_fbdev_shmem_setup(drm, 32);
364 364
365 return 0;365 return 0;
366}366}
drivers/gpu/drm/atmel-hlcdc/Kconfig+1−1
@@ -1,7 +1,7 @@
1# SPDX-License-Identifier: GPL-2.0-only1# SPDX-License-Identifier: GPL-2.0-only
2config DRM_ATMEL_HLCDC2config DRM_ATMEL_HLCDC
3 tristate "DRM Support for ATMEL HLCDC Display Controller"3 tristate "DRM Support for ATMEL HLCDC Display Controller"
4 depends on DRM && OF && COMMON_CLK && MFD_ATMEL_HLCDC && ARM4 depends on DRM && OF && COMMON_CLK && ((MFD_ATMEL_HLCDC && ARM) || COMPILE_TEST)
5 select DRM_GEM_DMA_HELPER5 select DRM_GEM_DMA_HELPER
6 select DRM_KMS_HELPER6 select DRM_KMS_HELPER
7 select DRM_PANEL7 select DRM_PANEL
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c+141−31
@@ -30,10 +30,12 @@ · 29 unmodified lines
30 *30 *
31 * @base: base CRTC state31 * @base: base CRTC state
32 * @output_mode: RGBXXX output mode32 * @output_mode: RGBXXX output mode
33 * @dpi: output DPI mode
33 */34 */
34struct atmel_hlcdc_crtc_state {35struct atmel_hlcdc_crtc_state {
35 struct drm_crtc_state base;36 struct drm_crtc_state base;
36 unsigned int output_mode;37 unsigned int output_mode;
38 u8 dpi;
37};39};
38 40
39static inline struct atmel_hlcdc_crtc_state *41static inline struct atmel_hlcdc_crtc_state *
@@ -164,18 +166,24 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) · 124 unmodified lines
164 state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state);166 state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state);
165 cfg = state->output_mode << 8;167 cfg = state->output_mode << 8;
166 168
167 if (adj->flags & DRM_MODE_FLAG_NVSYNC)169 if (!crtc->dc->desc->is_xlcdc) {
168 cfg |= ATMEL_HLCDC_VSPOL;170 if (adj->flags & DRM_MODE_FLAG_NVSYNC)
171 cfg |= ATMEL_HLCDC_VSPOL;
169 172
170 if (adj->flags & DRM_MODE_FLAG_NHSYNC)173 if (adj->flags & DRM_MODE_FLAG_NHSYNC)
171 cfg |= ATMEL_HLCDC_HSPOL;174 cfg |= ATMEL_HLCDC_HSPOL;
175 } else {
176 cfg |= state->dpi << 11;
177 }
172 178
173 regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5),179 regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5),
174 ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL |180 ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL |
175 ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE |181 ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE |
176 ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY |182 ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY |
177 ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO |183 ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO |
178 ATMEL_HLCDC_GUARDTIME_MASK | ATMEL_HLCDC_MODE_MASK,184 ATMEL_HLCDC_GUARDTIME_MASK |
185 (crtc->dc->desc->is_xlcdc ? ATMEL_XLCDC_MODE_MASK |
186 ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK),
179 cfg);187 cfg);
180 188
181 clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);189 clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
@@ -202,20 +210,37 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, · 20 unmodified lines
202 210
203 pm_runtime_get_sync(dev->dev);211 pm_runtime_get_sync(dev->dev);
204 212
213 if (crtc->dc->desc->is_xlcdc) {
214 regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_CM);
215 if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
216 !(status & ATMEL_XLCDC_CM),
217 10, 1000))
218 dev_warn(dev->dev, "Atmel LCDC status register CMSTS timeout\n");
219
220 regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_SD);
221 if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
222 status & ATMEL_XLCDC_SD,
223 10, 1000))
224 dev_warn(dev->dev, "Atmel LCDC status register SDSTS timeout\n");
225 }
226
205 regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);227 regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);
206 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&228 if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
207 (status & ATMEL_HLCDC_DISP))229 !(status & ATMEL_HLCDC_DISP),
208 cpu_relax();230 10, 1000))
231 dev_warn(dev->dev, "Atmel LCDC status register DISPSTS timeout\n");
209 232
210 regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC);233 regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC);
211 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&234 if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
212 (status & ATMEL_HLCDC_SYNC))235 !(status & ATMEL_HLCDC_SYNC),
213 cpu_relax();236 10, 1000))
237 dev_warn(dev->dev, "Atmel LCDC status register LCDSTS timeout\n");
214 238
215 regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK);239 regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK);
216 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&240 if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
217 (status & ATMEL_HLCDC_PIXEL_CLK))241 !(status & ATMEL_HLCDC_PIXEL_CLK),
218 cpu_relax();242 10, 1000))
243 dev_warn(dev->dev, "Atmel LCDC status register CLKSTS timeout\n");
219 244
220 clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);245 clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
221 pinctrl_pm_select_sleep_state(dev->dev);246 pinctrl_pm_select_sleep_state(dev->dev);
@@ -241,30 +266,95 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, · 19 unmodified lines
241 clk_prepare_enable(crtc->dc->hlcdc->sys_clk);266 clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
242 267
243 regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);268 regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
244 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&269 if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
245 !(status & ATMEL_HLCDC_PIXEL_CLK))270 status & ATMEL_HLCDC_PIXEL_CLK,
246 cpu_relax();271 10, 1000))
247 272 dev_warn(dev->dev, "Atmel LCDC status register CLKSTS timeout\n");
248 273
249 regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC);274 regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC);
250 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&275 if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
251 !(status & ATMEL_HLCDC_SYNC))276 status & ATMEL_HLCDC_SYNC,
252 cpu_relax();277 10, 1000))
278 dev_warn(dev->dev, "Atmel LCDC status register LCDSTS timeout\n");
253 279
254 regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP);280 regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP);
255 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&281 if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
256 !(status & ATMEL_HLCDC_DISP))282 status & ATMEL_HLCDC_DISP,
257 cpu_relax();283 10, 1000))
284 dev_warn(dev->dev, "Atmel LCDC status register DISPSTS timeout\n");
285
286 if (crtc->dc->desc->is_xlcdc) {
287 regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_CM);
288 if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
289 status & ATMEL_XLCDC_CM,
290 10, 1000))
291 dev_warn(dev->dev, "Atmel LCDC status register CMSTS timeout\n");
292
293 regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_SD);
294 if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
295 !(status & ATMEL_XLCDC_SD),
296 10, 1000))
297 dev_warn(dev->dev, "Atmel LCDC status register SDSTS timeout\n");
298 }
258 299
259 pm_runtime_put_sync(dev->dev);300 pm_runtime_put_sync(dev->dev);
260 301
261}302}
262 303
263#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0)304#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0)
264#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1)305#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1)
265#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2)306#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2)
266#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3)307#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3)
267#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0)308#define ATMEL_HLCDC_DPI_RGB565C1_OUTPUT BIT(4)
309#define ATMEL_HLCDC_DPI_RGB565C2_OUTPUT BIT(5)
310#define ATMEL_HLCDC_DPI_RGB565C3_OUTPUT BIT(6)
311#define ATMEL_HLCDC_DPI_RGB666C1_OUTPUT BIT(7)
312#define ATMEL_HLCDC_DPI_RGB666C2_OUTPUT BIT(8)
313#define ATMEL_HLCDC_DPI_RGB888_OUTPUT BIT(9)
314#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0)
315#define ATMEL_XLCDC_OUTPUT_MODE_MASK GENMASK(9, 0)
316
317static int atmel_xlcdc_connector_output_dsi(struct drm_encoder *encoder,
318 struct drm_display_info *info)
319{
320 int j;
321 unsigned int supported_fmts = 0;
322
323 switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) {
324 case 0:
325 break;
326 case MEDIA_BUS_FMT_RGB565_1X16:
327 return ATMEL_HLCDC_DPI_RGB565C1_OUTPUT;
328 case MEDIA_BUS_FMT_RGB666_1X18:
329 return ATMEL_HLCDC_DPI_RGB666C1_OUTPUT;
330 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
331 return ATMEL_HLCDC_DPI_RGB666C2_OUTPUT;
332 case MEDIA_BUS_FMT_RGB888_1X24:
333 return ATMEL_HLCDC_DPI_RGB888_OUTPUT;
334 default:
335 return -EINVAL;
336 }
337
338 for (j = 0; j < info->num_bus_formats; j++) {
339 switch (info->bus_formats[j]) {
340 case MEDIA_BUS_FMT_RGB565_1X16:
341 supported_fmts |= ATMEL_HLCDC_DPI_RGB565C1_OUTPUT;
342 break;
343 case MEDIA_BUS_FMT_RGB666_1X18:
344 supported_fmts |= ATMEL_HLCDC_DPI_RGB666C1_OUTPUT;
345 break;
346 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
347 supported_fmts |= ATMEL_HLCDC_DPI_RGB666C2_OUTPUT;
348 break;
349 case MEDIA_BUS_FMT_RGB888_1X24:
350 supported_fmts |= ATMEL_HLCDC_DPI_RGB888_OUTPUT;
351 break;
352 default:
353 break;
354 }
355 }
356 return supported_fmts;
357}
268 358
269static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state)359static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state)
270{360{
@@ -277,6 +367,13 @@ static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state) · 6 unmodified lines
277 encoder = state->best_encoder;367 encoder = state->best_encoder;
278 if (!encoder)368 if (!encoder)
279 encoder = connector->encoder;369 encoder = connector->encoder;
370 /*
371 * atmel-hlcdc to support DSI formats with DSI video pipeline
372 * when DRM_MODE_ENCODER_DSI type is set by
373 * connector driver component.
374 */
375 if (encoder->encoder_type == DRM_MODE_ENCODER_DSI)
376 return atmel_xlcdc_connector_output_dsi(encoder, info);
280 377
281 switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) {378 switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) {
282 case 0:379 case 0:
@@ -317,7 +414,7 @@ static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state) · 34 unmodified lines
317 414
318static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state)415static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state)
319{416{
320 unsigned int output_fmts = ATMEL_HLCDC_OUTPUT_MODE_MASK;417 unsigned int output_fmts;
321 struct atmel_hlcdc_crtc_state *hstate;418 struct atmel_hlcdc_crtc_state *hstate;
322 struct drm_connector_state *cstate;419 struct drm_connector_state *cstate;
323 struct drm_connector *connector;420 struct drm_connector *connector;
@@ -325,6 +422,8 @@ static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) · 1 unmodified line
325 int i;422 int i;
326 423
327 crtc = drm_crtc_to_atmel_hlcdc_crtc(state->crtc);424 crtc = drm_crtc_to_atmel_hlcdc_crtc(state->crtc);
425 output_fmts = crtc->dc->desc->is_xlcdc ? ATMEL_XLCDC_OUTPUT_MODE_MASK :
426 ATMEL_HLCDC_OUTPUT_MODE_MASK;
328 427
329 for_each_new_connector_in_state(state->state, connector, cstate, i) {428 for_each_new_connector_in_state(state->state, connector, cstate, i) {
330 unsigned int supported_fmts = 0;429 unsigned int supported_fmts = 0;
@@ -345,7 +444,15 @@ static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) · 14 unmodified lines
345 444
346 hstate = drm_crtc_state_to_atmel_hlcdc_crtc_state(state);445 hstate = drm_crtc_state_to_atmel_hlcdc_crtc_state(state);
347 hstate->output_mode = fls(output_fmts) - 1;446 hstate->output_mode = fls(output_fmts) - 1;
348 447 if (crtc->dc->desc->is_xlcdc) {
448 /* check if MIPI DPI bit needs to be set */
449 if (fls(output_fmts) > 3) {
450 hstate->output_mode -= 4;
451 hstate->dpi = 1;
452 } else {
453 hstate->dpi = 0;
454 }
455 }
349 return 0;456 return 0;
350}457}
351 458
@@ -449,6 +556,7 @@ static struct drm_crtc_state * · 97 unmodified lines
449atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc)556atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc)
450{557{
451 struct atmel_hlcdc_crtc_state *state, *cur;558 struct atmel_hlcdc_crtc_state *state, *cur;
559 struct atmel_hlcdc_crtc *c = drm_crtc_to_atmel_hlcdc_crtc(crtc);
452 560
453 if (WARN_ON(!crtc->state))561 if (WARN_ON(!crtc->state))
454 return NULL;562 return NULL;
@@ -460,6 +568,8 @@ atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc) · 5 unmodified lines
460 568
461 cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);569 cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
462 state->output_mode = cur->output_mode;570 state->output_mode = cur->output_mode;
571 if (c->dc->desc->is_xlcdc)
572 state->dpi = cur->dpi;
463 573
464 return &state->base;574 return &state->base;
465}575}
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c+105−0
@@ -58,6 +58,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = { · 57 unmodified lines
58 .conflicting_output_formats = true,58 .conflicting_output_formats = true,
59 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),59 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
60 .layers = atmel_hlcdc_at91sam9n12_layers,60 .layers = atmel_hlcdc_at91sam9n12_layers,
61 .ops = &atmel_hlcdc_ops,
61};62};
62 63
63static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {64static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
@@ -151,6 +152,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = { · 87 unmodified lines
151 .conflicting_output_formats = true,152 .conflicting_output_formats = true,
152 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),153 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
153 .layers = atmel_hlcdc_at91sam9x5_layers,154 .layers = atmel_hlcdc_at91sam9x5_layers,
155 .ops = &atmel_hlcdc_ops,
154};156};
155 157
156static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {158static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
@@ -269,6 +271,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = { · 112 unmodified lines
269 .conflicting_output_formats = true,271 .conflicting_output_formats = true,
270 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),272 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
271 .layers = atmel_hlcdc_sama5d3_layers,273 .layers = atmel_hlcdc_sama5d3_layers,
274 .ops = &atmel_hlcdc_ops,
272};275};
273 276
274static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {277static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
@@ -364,6 +367,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = { · 89 unmodified lines
364 .max_hpw = 0x3ff,367 .max_hpw = 0x3ff,
365 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),368 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
366 .layers = atmel_hlcdc_sama5d4_layers,369 .layers = atmel_hlcdc_sama5d4_layers,
370 .ops = &atmel_hlcdc_ops,
367};371};
368 372
369static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sam9x60_layers[] = {373static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sam9x60_layers[] = {
@@ -460,6 +464,103 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sam9x60 = { · 90 unmodified lines
460 .fixed_clksrc = true,464 .fixed_clksrc = true,
461 .nlayers = ARRAY_SIZE(atmel_hlcdc_sam9x60_layers),465 .nlayers = ARRAY_SIZE(atmel_hlcdc_sam9x60_layers),
462 .layers = atmel_hlcdc_sam9x60_layers,466 .layers = atmel_hlcdc_sam9x60_layers,
467 .ops = &atmel_hlcdc_ops,
468};
469
470static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x75_layers[] = {
471 {
472 .name = "base",
473 .formats = &atmel_hlcdc_plane_rgb_formats,
474 .regs_offset = 0x60,
475 .id = 0,
476 .type = ATMEL_HLCDC_BASE_LAYER,
477 .cfgs_offset = 0x1c,
478 .layout = {
479 .xstride = { 2 },
480 .default_color = 3,
481 .general_config = 4,
482 .disc_pos = 5,
483 .disc_size = 6,
484 },
485 .clut_offset = 0x700,
486 },
487 {
488 .name = "overlay1",
489 .formats = &atmel_hlcdc_plane_rgb_formats,
490 .regs_offset = 0x160,
491 .id = 1,
492 .type = ATMEL_HLCDC_OVERLAY_LAYER,
493 .cfgs_offset = 0x1c,
494 .layout = {
495 .pos = 2,
496 .size = 3,
497 .xstride = { 4 },
498 .pstride = { 5 },
499 .default_color = 6,
500 .chroma_key = 7,
501 .chroma_key_mask = 8,
502 .general_config = 9,
503 },
504 .clut_offset = 0xb00,
505 },
506 {
507 .name = "overlay2",
508 .formats = &atmel_hlcdc_plane_rgb_formats,
509 .regs_offset = 0x260,
510 .id = 2,
511 .type = ATMEL_HLCDC_OVERLAY_LAYER,
512 .cfgs_offset = 0x1c,
513 .layout = {
514 .pos = 2,
515 .size = 3,
516 .xstride = { 4 },
517 .pstride = { 5 },
518 .default_color = 6,
519 .chroma_key = 7,
520 .chroma_key_mask = 8,
521 .general_config = 9,
522 },
523 .clut_offset = 0xf00,
524 },
525 {
526 .name = "high-end-overlay",
527 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
528 .regs_offset = 0x360,
529 .id = 3,
530 .type = ATMEL_HLCDC_OVERLAY_LAYER,
531 .cfgs_offset = 0x30,
532 .layout = {
533 .pos = 2,
534 .size = 3,
535 .memsize = 4,
536 .xstride = { 5, 7 },
537 .pstride = { 6, 8 },
538 .default_color = 9,
539 .chroma_key = 10,
540 .chroma_key_mask = 11,
541 .general_config = 12,
542 .csc = 16,
543 .scaler_config = 23,
544 .vxs_config = 30,
545 .hxs_config = 31,
546 },
547 .clut_offset = 0x1300,
548 },
549};
550
551static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_sam9x75 = {
552 .min_width = 0,
553 .min_height = 0,
554 .max_width = 2048,
555 .max_height = 2048,
556 .max_spw = 0x3ff,
557 .max_vpw = 0x3ff,
558 .max_hpw = 0x3ff,
559 .fixed_clksrc = true,
560 .is_xlcdc = true,
561 .nlayers = ARRAY_SIZE(atmel_xlcdc_sam9x75_layers),
562 .layers = atmel_xlcdc_sam9x75_layers,
563 .ops = &atmel_xlcdc_ops,
463};564};
464 565
465static const struct of_device_id atmel_hlcdc_of_match[] = {566static const struct of_device_id atmel_hlcdc_of_match[] = {
@@ -487,6 +588,10 @@ static const struct of_device_id atmel_hlcdc_of_match[] = { · 21 unmodified lines
487 .compatible = "microchip,sam9x60-hlcdc",588 .compatible = "microchip,sam9x60-hlcdc",
488 .data = &atmel_hlcdc_dc_sam9x60,589 .data = &atmel_hlcdc_dc_sam9x60,
489 },590 },
591 {
592 .compatible = "microchip,sam9x75-xlcdc",
593 .data = &atmel_xlcdc_dc_sam9x75,
594 },
490 { /* sentinel */ },595 { /* sentinel */ },
491};596};
492MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);597MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h+108−24
@@ -15,6 +15,7 @@ · 14 unmodified lines
15 15
16#include <drm/drm_plane.h>16#include <drm/drm_plane.h>
17 17
18/* LCD controller common registers */
18#define ATMEL_HLCDC_LAYER_CHER 0x019#define ATMEL_HLCDC_LAYER_CHER 0x0
19#define ATMEL_HLCDC_LAYER_CHDR 0x420#define ATMEL_HLCDC_LAYER_CHDR 0x4
20#define ATMEL_HLCDC_LAYER_CHSR 0x821#define ATMEL_HLCDC_LAYER_CHSR 0x8
@@ -128,6 +129,47 @@ · 107 unmodified lines
128 129
129#define ATMEL_HLCDC_MAX_LAYERS 6130#define ATMEL_HLCDC_MAX_LAYERS 6
130 131
132/* XLCDC controller specific registers */
133#define ATMEL_XLCDC_LAYER_ENR 0x10
134#define ATMEL_XLCDC_LAYER_EN BIT(0)
135
136#define ATMEL_XLCDC_LAYER_IER 0x0
137#define ATMEL_XLCDC_LAYER_IDR 0x4
138#define ATMEL_XLCDC_LAYER_ISR 0xc
139#define ATMEL_XLCDC_LAYER_OVR_IRQ(p) BIT(2 + (8 * (p)))
140
141#define ATMEL_XLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x4) + 0x18)
142
143#define ATMEL_XLCDC_LAYER_DMA_CFG 0
144
145#define ATMEL_XLCDC_LAYER_DMA BIT(0)
146#define ATMEL_XLCDC_LAYER_REP BIT(1)
147#define ATMEL_XLCDC_LAYER_DISCEN BIT(4)
148
149#define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS (4 << 6)
150#define ATMEL_XLCDC_LAYER_SFACTA_ONE BIT(9)
151#define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS (6 << 11)
152#define ATMEL_XLCDC_LAYER_DFACTA_ONE BIT(14)
153
154#define ATMEL_XLCDC_LAYER_A0_SHIFT 16
155#define ATMEL_XLCDC_LAYER_A0(x) \
156 ((x) << ATMEL_XLCDC_LAYER_A0_SHIFT)
157
158#define ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE BIT(0)
159#define ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE BIT(1)
160#define ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE BIT(4)
161#define ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE BIT(5)
162
163#define ATMEL_XLCDC_LAYER_VXSYCFG_ONE BIT(0)
164#define ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE BIT(4)
165#define ATMEL_XLCDC_LAYER_VXSCCFG_ONE BIT(16)
166#define ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE BIT(20)
167
168#define ATMEL_XLCDC_LAYER_HXSYCFG_ONE BIT(0)
169#define ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE BIT(4)
170#define ATMEL_XLCDC_LAYER_HXSCCFG_ONE BIT(16)
171#define ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE BIT(20)
172
131/**173/**
132 * Atmel HLCDC Layer registers layout structure174 * Atmel HLCDC Layer registers layout structure
133 *175 *
@@ -156,6 +198,8 @@ · 22 unmodified lines
156 * @disc_pos: discard area position register198 * @disc_pos: discard area position register
157 * @disc_size: discard area size register199 * @disc_size: discard area size register
158 * @csc: color space conversion register200 * @csc: color space conversion register
201 * @vxs_config: vertical scalar filter taps control register
202 * @hxs_config: horizontal scalar filter taps control register
159 */203 */
160struct atmel_hlcdc_layer_cfg_layout {204struct atmel_hlcdc_layer_cfg_layout {
161 int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];205 int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
@@ -175,6 +219,8 @@ struct atmel_hlcdc_layer_cfg_layout { · 13 unmodified lines
175 int disc_pos;219 int disc_pos;
176 int disc_size;220 int disc_size;
177 int csc;221 int csc;
222 int vxs_config;
223 int hxs_config;
178};224};
179 225
180/**226/**
@@ -288,6 +334,64 @@ atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer) · 107 unmodified lines
288 return container_of(layer, struct atmel_hlcdc_plane, layer);334 return container_of(layer, struct atmel_hlcdc_plane, layer);
289}335}
290 336
337/**
338 * struct atmel_hlcdc_dc - Atmel HLCDC Display Controller.
339 * @desc: HLCDC Display Controller description
340 * @dscrpool: DMA coherent pool used to allocate DMA descriptors
341 * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
342 * @crtc: CRTC provided by the display controller
343 * @layers: active HLCDC layers
344 * @suspend: used to store the HLCDC state when entering suspend
345 * @suspend.imr: used to read/write LCDC Interrupt Mask Register
346 * @suspend.state: Atomic commit structure
347 */
348struct atmel_hlcdc_dc {
349 const struct atmel_hlcdc_dc_desc *desc;
350 struct dma_pool *dscrpool;
351 struct atmel_hlcdc *hlcdc;
352 struct drm_crtc *crtc;
353 struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS];
354 struct {
355 u32 imr;
356 struct drm_atomic_state *state;
357 } suspend;
358};
359
360struct atmel_hlcdc_plane_state;
361
362/**
363 * struct atmel_lcdc_dc_ops - describes atmel_lcdc ops group
364 * to differentiate HLCDC and XLCDC IP code support
365 * @plane_setup_scaler: update the vertical and horizontal scaling factors
366 * @update_lcdc_buffers: update the each LCDC layers DMA registers
367 * @lcdc_atomic_disable: disable LCDC interrupts and layers
368 * @lcdc_update_general_settings: update each LCDC layers general
369 * configuration register
370 * @lcdc_atomic_update: enable the LCDC layers and interrupts
371 * @lcdc_csc_init: update the color space conversion co-efficient of
372 * High-end overlay register
373 * @lcdc_irq_dbg: to raise alert incase of interrupt overrun in any LCDC layer
374 */
375struct atmel_lcdc_dc_ops {
376 void (*plane_setup_scaler)(struct atmel_hlcdc_plane *plane,
377 struct atmel_hlcdc_plane_state *state);
378 void (*lcdc_update_buffers)(struct atmel_hlcdc_plane *plane,
379 struct atmel_hlcdc_plane_state *state,
380 u32 sr, int i);
381 void (*lcdc_atomic_disable)(struct atmel_hlcdc_plane *plane);
382 void (*lcdc_update_general_settings)(struct atmel_hlcdc_plane *plane,
383 struct atmel_hlcdc_plane_state *state);
384 void (*lcdc_atomic_update)(struct atmel_hlcdc_plane *plane,
385 struct atmel_hlcdc_dc *dc);
386 void (*lcdc_csc_init)(struct atmel_hlcdc_plane *plane,
387 const struct atmel_hlcdc_layer_desc *desc);
388 void (*lcdc_irq_dbg)(struct atmel_hlcdc_plane *plane,
389 const struct atmel_hlcdc_layer_desc *desc);
390};
391
392extern const struct atmel_lcdc_dc_ops atmel_hlcdc_ops;
393extern const struct atmel_lcdc_dc_ops atmel_xlcdc_ops;
394
291/**395/**
292 * Atmel HLCDC Display Controller description structure.396 * Atmel HLCDC Display Controller description structure.
293 *397 *
@@ -304,8 +408,10 @@ atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer) · 10 unmodified lines
304 * @conflicting_output_formats: true if RGBXXX output formats conflict with408 * @conflicting_output_formats: true if RGBXXX output formats conflict with
305 * each other.409 * each other.
306 * @fixed_clksrc: true if clock source is fixed410 * @fixed_clksrc: true if clock source is fixed
411 * @is_xlcdc: true if XLCDC IP is supported
307 * @layers: a layer description table describing available layers412 * @layers: a layer description table describing available layers
308 * @nlayers: layer description table size413 * @nlayers: layer description table size
414 * @ops: atmel lcdc dc ops
309 */415 */
310struct atmel_hlcdc_dc_desc {416struct atmel_hlcdc_dc_desc {
311 int min_width;417 int min_width;
@@ -317,32 +423,10 @@ struct atmel_hlcdc_dc_desc { · 5 unmodified lines
317 int max_hpw;423 int max_hpw;
318 bool conflicting_output_formats;424 bool conflicting_output_formats;
319 bool fixed_clksrc;425 bool fixed_clksrc;
426 bool is_xlcdc;
320 const struct atmel_hlcdc_layer_desc *layers;427 const struct atmel_hlcdc_layer_desc *layers;
321 int nlayers;428 int nlayers;
322};429 const struct atmel_lcdc_dc_ops *ops;
323
324/**
325 * Atmel HLCDC Display Controller.
326 *
327 * @desc: HLCDC Display Controller description
328 * @dscrpool: DMA coherent pool used to allocate DMA descriptors
329 * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
330 * @fbdev: framebuffer device attached to the Display Controller
331 * @crtc: CRTC provided by the display controller
332 * @planes: instantiated planes
333 * @layers: active HLCDC layers
334 * @suspend: used to store the HLCDC state when entering suspend
335 */
336struct atmel_hlcdc_dc {
337 const struct atmel_hlcdc_dc_desc *desc;
338 struct dma_pool *dscrpool;
339 struct atmel_hlcdc *hlcdc;
340 struct drm_crtc *crtc;
341 struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS];
342 struct {
343 u32 imr;
344 struct drm_atomic_state *state;
345 } suspend;
346};430};
347 431
348extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;432extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c+309−60
@@ -282,8 +282,9 @@ atmel_hlcdc_plane_scaler_set_phicoeff(struct atmel_hlcdc_plane *plane, · 281 unmodified lines
282 coeff_tab[i]);282 coeff_tab[i]);
283}283}
284 284
285static void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane,285static
286 struct atmel_hlcdc_plane_state *state)286void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane,
287 struct atmel_hlcdc_plane_state *state)
287{288{
288 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;289 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
289 u32 xfactor, yfactor;290 u32 xfactor, yfactor;
@@ -330,11 +331,61 @@ static void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, · 40 unmodified lines
330 yfactor));331 yfactor));
331}332}
332 333
334static
335void atmel_xlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane,
336 struct atmel_hlcdc_plane_state *state)
337{
338 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
339 u32 xfactor, yfactor;
340
341 if (!desc->layout.scaler_config)
342 return;
343
344 if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) {
345 atmel_hlcdc_layer_write_cfg(&plane->layer,
346 desc->layout.scaler_config, 0);
347 return;
348 }
349
350 /* xfactor = round[(2^20 * XMEMSIZE)/XSIZE)] */
351 xfactor = (u32)(((1 << 20) * state->src_w) / state->crtc_w);
352
353 /* yfactor = round[(2^20 * YMEMSIZE)/YSIZE)] */
354 yfactor = (u32)(((1 << 20) * state->src_h) / state->crtc_h);
355
356 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config,
357 ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE |
358 ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE |
359 ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE |
360 ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE);
361
362 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 1,
363 yfactor);
364 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 3,
365 xfactor);
366
367 /*
368 * With YCbCr 4:2:2 and YCbYcr 4:2:0 window resampling, configuration
369 * register LCDC_HEOCFG25.VXSCFACT and LCDC_HEOCFG27.HXSCFACT is half
370 * the value of yfactor and xfactor.
371 */
372 if (state->base.fb->format->format == DRM_FORMAT_YUV420) {
373 yfactor /= 2;
374 xfactor /= 2;
375 }
376
377 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2,
378 yfactor);
379 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4,
380 xfactor);
381}
382
333static void383static void
334atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,384atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
335 struct atmel_hlcdc_plane_state *state)385 struct atmel_hlcdc_plane_state *state)
336{386{
337 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;387 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
388 struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;
338 389
339 if (desc->layout.size)390 if (desc->layout.size)
340 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size,391 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size,
@@ -352,12 +403,12 @@ atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, · 11 unmodified lines
352 ATMEL_HLCDC_LAYER_POS(state->crtc_x,403 ATMEL_HLCDC_LAYER_POS(state->crtc_x,
353 state->crtc_y));404 state->crtc_y));
354 405
355 atmel_hlcdc_plane_setup_scaler(plane, state);406 dc->desc->ops->plane_setup_scaler(plane, state);
356}407}
357 408
358static void409static
359atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane,410void atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane,
360 struct atmel_hlcdc_plane_state *state)411 struct atmel_hlcdc_plane_state *state)
361{412{
362 unsigned int cfg = ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id;413 unsigned int cfg = ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id;
363 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;414 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
@@ -393,6 +444,40 @@ atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, · 29 unmodified lines
393 cfg);444 cfg);
394}445}
395 446
447static
448void atmel_xlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane,
449 struct atmel_hlcdc_plane_state *state)
450{
451 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
452 const struct drm_format_info *format = state->base.fb->format;
453 unsigned int cfg;
454
455 atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_XLCDC_LAYER_DMA_CFG,
456 ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id);
457
458 cfg = ATMEL_XLCDC_LAYER_DMA | ATMEL_XLCDC_LAYER_REP;
459
460 if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) {
461 /*
462 * Alpha Blending bits specific to SAM9X7 SoC
463 */
464 cfg |= ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS |
465 ATMEL_XLCDC_LAYER_SFACTA_ONE |
466 ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS |
467 ATMEL_XLCDC_LAYER_DFACTA_ONE;
468 if (format->has_alpha)
469 cfg |= ATMEL_XLCDC_LAYER_A0(0xff);
470 else
471 cfg |= ATMEL_XLCDC_LAYER_A0(state->base.alpha);
472 }
473
474 if (state->disc_h && state->disc_w)
475 cfg |= ATMEL_XLCDC_LAYER_DISCEN;
476
477 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.general_config,
478 cfg);
479}
480
396static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane,481static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane,
397 struct atmel_hlcdc_plane_state *state)482 struct atmel_hlcdc_plane_state *state)
398{483{
@@ -437,36 +522,55 @@ static void atmel_hlcdc_plane_update_clut(struct atmel_hlcdc_plane *plane, · 38 unmodified lines
437 }522 }
438}523}
439 524
525static void atmel_hlcdc_update_buffers(struct atmel_hlcdc_plane *plane,
526 struct atmel_hlcdc_plane_state *state,
527 u32 sr, int i)
528{
529 atmel_hlcdc_layer_write_reg(&plane->layer,
530 ATMEL_HLCDC_LAYER_PLANE_HEAD(i),
531 state->dscrs[i]->self);
532
533 if (sr & ATMEL_HLCDC_LAYER_EN)
534 return;
535
536 atmel_hlcdc_layer_write_reg(&plane->layer,
537 ATMEL_HLCDC_LAYER_PLANE_ADDR(i),
538 state->dscrs[i]->addr);
539 atmel_hlcdc_layer_write_reg(&plane->layer,
540 ATMEL_HLCDC_LAYER_PLANE_CTRL(i),
541 state->dscrs[i]->ctrl);
542 atmel_hlcdc_layer_write_reg(&plane->layer,
543 ATMEL_HLCDC_LAYER_PLANE_NEXT(i),
544 state->dscrs[i]->self);
545}
546
547static void atmel_xlcdc_update_buffers(struct atmel_hlcdc_plane *plane,
548 struct atmel_hlcdc_plane_state *state,
549 u32 sr, int i)
550{
551 atmel_hlcdc_layer_write_reg(&plane->layer,
552 ATMEL_XLCDC_LAYER_PLANE_ADDR(i),
553 state->dscrs[i]->addr);
554}
555
440static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane,556static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane,
441 struct atmel_hlcdc_plane_state *state)557 struct atmel_hlcdc_plane_state *state)
442{558{
443 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;559 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
560 struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;
444 struct drm_framebuffer *fb = state->base.fb;561 struct drm_framebuffer *fb = state->base.fb;
445 u32 sr;562 u32 sr;
446 int i;563 int i;
447 564
448 sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);565 if (!dc->desc->is_xlcdc)
566 sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
449 567
450 for (i = 0; i < state->nplanes; i++) {568 for (i = 0; i < state->nplanes; i++) {
451 struct drm_gem_dma_object *gem = drm_fb_dma_get_gem_obj(fb, i);569 struct drm_gem_dma_object *gem = drm_fb_dma_get_gem_obj(fb, i);
452 570
453 state->dscrs[i]->addr = gem->dma_addr + state->offsets[i];571 state->dscrs[i]->addr = gem->dma_addr + state->offsets[i];
454 572
455 atmel_hlcdc_layer_write_reg(&plane->layer,573 dc->desc->ops->lcdc_update_buffers(plane, state, sr, i);
456 ATMEL_HLCDC_LAYER_PLANE_HEAD(i),
457 state->dscrs[i]->self);
458
459 if (!(sr & ATMEL_HLCDC_LAYER_EN)) {
460 atmel_hlcdc_layer_write_reg(&plane->layer,
461 ATMEL_HLCDC_LAYER_PLANE_ADDR(i),
462 state->dscrs[i]->addr);
463 atmel_hlcdc_layer_write_reg(&plane->layer,
464 ATMEL_HLCDC_LAYER_PLANE_CTRL(i),
465 state->dscrs[i]->ctrl);
466 atmel_hlcdc_layer_write_reg(&plane->layer,
467 ATMEL_HLCDC_LAYER_PLANE_NEXT(i),
468 state->dscrs[i]->self);
469 }
470 574
471 if (desc->layout.xstride[i])575 if (desc->layout.xstride[i])
472 atmel_hlcdc_layer_write_cfg(&plane->layer,576 atmel_hlcdc_layer_write_cfg(&plane->layer,
@@ -712,11 +816,8 @@ static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p, · 239 unmodified lines
712 return 0;816 return 0;
713}817}
714 818
715static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p,819static void atmel_hlcdc_atomic_disable(struct atmel_hlcdc_plane *plane)
716 struct drm_atomic_state *state)
717{820{
718 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
719
720 /* Disable interrupts */821 /* Disable interrupts */
721 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR,822 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR,
722 0xffffffff);823 0xffffffff);
@@ -731,6 +832,70 @@ static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, · 8 unmodified lines
731 atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);832 atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
732}833}
733 834
835static void atmel_xlcdc_atomic_disable(struct atmel_hlcdc_plane *plane)
836{
837 /* Disable interrupts */
838 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IDR,
839 0xffffffff);
840
841 /* Disable the layer */
842 atmel_hlcdc_layer_write_reg(&plane->layer,
843 ATMEL_XLCDC_LAYER_ENR, 0);
844
845 /* Clear all pending interrupts */
846 atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR);
847}
848
849static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p,
850 struct drm_atomic_state *state)
851{
852 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
853 struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;
854
855 dc->desc->ops->lcdc_atomic_disable(plane);
856}
857
858static void atmel_hlcdc_atomic_update(struct atmel_hlcdc_plane *plane,
859 struct atmel_hlcdc_dc *dc)
860{
861 u32 sr;
862
863 /* Enable the overrun interrupts. */
864 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER,
865 ATMEL_HLCDC_LAYER_OVR_IRQ(0) |
866 ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
867 ATMEL_HLCDC_LAYER_OVR_IRQ(2));
868
869 /* Apply the new config at the next SOF event. */
870 sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
871 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER,
872 ATMEL_HLCDC_LAYER_UPDATE |
873 (sr & ATMEL_HLCDC_LAYER_EN ?
874 ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN));
875}
876
877static void atmel_xlcdc_atomic_update(struct atmel_hlcdc_plane *plane,
878 struct atmel_hlcdc_dc *dc)
879{
880 /* Enable the overrun interrupts. */
881 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IER,
882 ATMEL_XLCDC_LAYER_OVR_IRQ(0) |
883 ATMEL_XLCDC_LAYER_OVR_IRQ(1) |
884 ATMEL_XLCDC_LAYER_OVR_IRQ(2));
885
886 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_ENR,
887 ATMEL_XLCDC_LAYER_EN);
888
889 /*
890 * Updating XLCDC_xxxCFGx, XLCDC_xxxFBA and XLCDC_xxxEN,
891 * (where xxx indicates each layer) requires writing one to the
892 * Update Attribute field for each layer in LCDC_ATTRE register for SAM9X7.
893 */
894 regmap_write(dc->hlcdc->regmap, ATMEL_XLCDC_ATTRE, ATMEL_XLCDC_BASE_UPDATE |
895 ATMEL_XLCDC_OVR1_UPDATE | ATMEL_XLCDC_OVR3_UPDATE |
896 ATMEL_XLCDC_HEO_UPDATE);
897}
898
734static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p,899static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p,
735 struct drm_atomic_state *state)900 struct drm_atomic_state *state)
736{901{
@@ -739,7 +904,7 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, · 2 unmodified lines
739 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);904 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
740 struct atmel_hlcdc_plane_state *hstate =905 struct atmel_hlcdc_plane_state *hstate =
741 drm_plane_state_to_atmel_hlcdc_plane_state(new_s);906 drm_plane_state_to_atmel_hlcdc_plane_state(new_s);
742 u32 sr;907 struct atmel_hlcdc_dc *dc = p->dev->dev_private;
743 908
744 if (!new_s->crtc || !new_s->fb)909 if (!new_s->crtc || !new_s->fb)
745 return;910 return;
@@ -750,29 +915,83 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, · 4 unmodified lines
750 }915 }
751 916
752 atmel_hlcdc_plane_update_pos_and_size(plane, hstate);917 atmel_hlcdc_plane_update_pos_and_size(plane, hstate);
753 atmel_hlcdc_plane_update_general_settings(plane, hstate);918 dc->desc->ops->lcdc_update_general_settings(plane, hstate);
754 atmel_hlcdc_plane_update_format(plane, hstate);919 atmel_hlcdc_plane_update_format(plane, hstate);
755 atmel_hlcdc_plane_update_clut(plane, hstate);920 atmel_hlcdc_plane_update_clut(plane, hstate);
756 atmel_hlcdc_plane_update_buffers(plane, hstate);921 atmel_hlcdc_plane_update_buffers(plane, hstate);
757 atmel_hlcdc_plane_update_disc_area(plane, hstate);922 atmel_hlcdc_plane_update_disc_area(plane, hstate);
758 923
759 /* Enable the overrun interrupts. */924 dc->desc->ops->lcdc_atomic_update(plane, dc);
760 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER,925}
761 ATMEL_HLCDC_LAYER_OVR_IRQ(0) |
762 ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
763 ATMEL_HLCDC_LAYER_OVR_IRQ(2));
764 926
765 /* Apply the new config at the next SOF event. */927static void atmel_hlcdc_csc_init(struct atmel_hlcdc_plane *plane,
766 sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);928 const struct atmel_hlcdc_layer_desc *desc)
767 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER,929{
768 ATMEL_HLCDC_LAYER_UPDATE |930 /*
769 (sr & ATMEL_HLCDC_LAYER_EN ?931 * TODO: declare a "yuv-to-rgb-conv-factors" property to let
770 ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN));932 * userspace modify these factors (using a BLOB property ?).
933 */
934 static const u32 hlcdc_csc_coeffs[] = {
935 0x4c900091,
936 0x7a5f5090,
937 0x40040890
938 };
939
940 for (int i = 0; i < ARRAY_SIZE(hlcdc_csc_coeffs); i++) {
941 atmel_hlcdc_layer_write_cfg(&plane->layer,
942 desc->layout.csc + i,
943 hlcdc_csc_coeffs[i]);
944 }
945}
946
947static void atmel_xlcdc_csc_init(struct atmel_hlcdc_plane *plane,
948 const struct atmel_hlcdc_layer_desc *desc)
949{
950 /*
951 * yuv-to-rgb-conv-factors are now defined from LCDC_HEOCFG16 to
952 * LCDC_HEOCFG21 registers in SAM9X7.
953 */
954 static const u32 xlcdc_csc_coeffs[] = {
955 0x00000488,
956 0x00000648,
957 0x1EA00480,
958 0x00001D28,
959 0x08100480,
960 0x00000000,
961 0x00000007
962 };
963
964 for (int i = 0; i < ARRAY_SIZE(xlcdc_csc_coeffs); i++) {
965 atmel_hlcdc_layer_write_cfg(&plane->layer,
966 desc->layout.csc + i,
967 xlcdc_csc_coeffs[i]);
968 }
969
970 if (desc->layout.vxs_config && desc->layout.hxs_config) {
971 /*
972 * Updating vxs.config and hxs.config fixes the
973 * Green Color Issue in SAM9X7 EGT Video Player App
974 */
975 atmel_hlcdc_layer_write_cfg(&plane->layer,
976 desc->layout.vxs_config,
977 ATMEL_XLCDC_LAYER_VXSYCFG_ONE |
978 ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE |
979 ATMEL_XLCDC_LAYER_VXSCCFG_ONE |
980 ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE);
981
982 atmel_hlcdc_layer_write_cfg(&plane->layer,
983 desc->layout.hxs_config,
984 ATMEL_XLCDC_LAYER_HXSYCFG_ONE |
985 ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE |
986 ATMEL_XLCDC_LAYER_HXSCCFG_ONE |
987 ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE);
988 }
771}989}
772 990
773static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane)991static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane)
774{992{
775 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;993 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
994 struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;
776 995
777 if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||996 if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
778 desc->type == ATMEL_HLCDC_CURSOR_LAYER) {997 desc->type == ATMEL_HLCDC_CURSOR_LAYER) {
@@ -796,31 +1015,16 @@ static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane) · 17 unmodified lines
796 return ret;1015 return ret;
797 }1016 }
798 1017
799 if (desc->layout.csc) {1018 if (desc->layout.csc)
800 /*1019 dc->desc->ops->lcdc_csc_init(plane, desc);
801 * TODO: decare a "yuv-to-rgb-conv-factors" property to let
802 * userspace modify these factors (using a BLOB property ?).
803 */
804 atmel_hlcdc_layer_write_cfg(&plane->layer,
805 desc->layout.csc,
806 0x4c900091);
807 atmel_hlcdc_layer_write_cfg(&plane->layer,
808 desc->layout.csc + 1,
809 0x7a5f5090);
810 atmel_hlcdc_layer_write_cfg(&plane->layer,
811 desc->layout.csc + 2,
812 0x40040890);
813 }
814 1020
815 return 0;1021 return 0;
816}1022}
817 1023
818void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane)1024static void atmel_hlcdc_irq_dbg(struct atmel_hlcdc_plane *plane,
1025 const struct atmel_hlcdc_layer_desc *desc)
819{1026{
820 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;1027 u32 isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
821 u32 isr;
822
823 isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
824 1028
825 /*1029 /*
826 * There's not much we can do in case of overrun except informing1030 * There's not much we can do in case of overrun except informing
@@ -834,6 +1038,51 @@ void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane) · 7 unmodified lines
834 desc->name);1038 desc->name);
835}1039}
836 1040
1041static void atmel_xlcdc_irq_dbg(struct atmel_hlcdc_plane *plane,
1042 const struct atmel_hlcdc_layer_desc *desc)
1043{
1044 u32 isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR);
1045
1046 /*
1047 * There's not much we can do in case of overrun except informing
1048 * the user. However, we are in interrupt context here, hence the
1049 * use of dev_dbg().
1050 */
1051 if (isr &
1052 (ATMEL_XLCDC_LAYER_OVR_IRQ(0) | ATMEL_XLCDC_LAYER_OVR_IRQ(1) |
1053 ATMEL_XLCDC_LAYER_OVR_IRQ(2)))
1054 dev_dbg(plane->base.dev->dev, "overrun on plane %s\n",
1055 desc->name);
1056}
1057
1058void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane)
1059{
1060 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
1061 struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;
1062
1063 dc->desc->ops->lcdc_irq_dbg(plane, desc);
1064}
1065
1066const struct atmel_lcdc_dc_ops atmel_hlcdc_ops = {
1067 .plane_setup_scaler = atmel_hlcdc_plane_setup_scaler,
1068 .lcdc_update_buffers = atmel_hlcdc_update_buffers,
1069 .lcdc_atomic_disable = atmel_hlcdc_atomic_disable,
1070 .lcdc_update_general_settings = atmel_hlcdc_plane_update_general_settings,
1071 .lcdc_atomic_update = atmel_hlcdc_atomic_update,
1072 .lcdc_csc_init = atmel_hlcdc_csc_init,
1073 .lcdc_irq_dbg = atmel_hlcdc_irq_dbg,
1074};
1075
1076const struct atmel_lcdc_dc_ops atmel_xlcdc_ops = {
1077 .plane_setup_scaler = atmel_xlcdc_plane_setup_scaler,
1078 .lcdc_update_buffers = atmel_xlcdc_update_buffers,
1079 .lcdc_atomic_disable = atmel_xlcdc_atomic_disable,
1080 .lcdc_update_general_settings = atmel_xlcdc_plane_update_general_settings,
1081 .lcdc_atomic_update = atmel_xlcdc_atomic_update,
1082 .lcdc_csc_init = atmel_xlcdc_csc_init,
1083 .lcdc_irq_dbg = atmel_xlcdc_irq_dbg,
1084};
1085
837static const struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = {1086static const struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = {
838 .atomic_check = atmel_hlcdc_plane_atomic_check,1087 .atomic_check = atmel_hlcdc_plane_atomic_check,
839 .atomic_update = atmel_hlcdc_plane_atomic_update,1088 .atomic_update = atmel_hlcdc_plane_atomic_update,
drivers/gpu/drm/bridge/adv7511/adv7511_drv.c+0−5
@@ -877,11 +877,6 @@ static int adv7511_connector_init(struct adv7511 *adv) · 876 unmodified lines
877 struct drm_bridge *bridge = &adv->bridge;877 struct drm_bridge *bridge = &adv->bridge;
878 int ret;878 int ret;
879 879
880 if (!bridge->encoder) {
881 DRM_ERROR("Parent encoder object not found");
882 return -ENODEV;
883 }
884
885 if (adv->i2c_main->irq)880 if (adv->i2c_main->irq)
886 adv->connector.polled = DRM_CONNECTOR_POLL_HPD;881 adv->connector.polled = DRM_CONNECTOR_POLL_HPD;
887 else882 else
drivers/gpu/drm/bridge/analogix/analogix-anx6345.c+7−13
@@ -47,7 +47,7 @@ struct anx6345 { · 46 unmodified lines
47 struct drm_dp_aux aux;47 struct drm_dp_aux aux;
48 struct drm_bridge bridge;48 struct drm_bridge bridge;
49 struct i2c_client *client;49 struct i2c_client *client;
50 struct edid *edid;50 const struct drm_edid *drm_edid;
51 struct drm_connector connector;51 struct drm_connector connector;
52 struct drm_panel *panel;52 struct drm_panel *panel;
53 struct regulator *dvdd12;53 struct regulator *dvdd12;
@@ -458,7 +458,7 @@ static int anx6345_get_modes(struct drm_connector *connector) · 404 unmodified lines
458 458
459 mutex_lock(&anx6345->lock);459 mutex_lock(&anx6345->lock);
460 460
461 if (!anx6345->edid) {461 if (!anx6345->drm_edid) {
462 if (!anx6345->powered) {462 if (!anx6345->powered) {
463 anx6345_poweron(anx6345);463 anx6345_poweron(anx6345);
464 power_off = true;464 power_off = true;
@@ -470,19 +470,18 @@ static int anx6345_get_modes(struct drm_connector *connector) · 5 unmodified lines
470 goto unlock;470 goto unlock;
471 }471 }
472 472
473 anx6345->edid = drm_get_edid(connector, &anx6345->aux.ddc);473 anx6345->drm_edid = drm_edid_read_ddc(connector, &anx6345->aux.ddc);
474 if (!anx6345->edid)474 if (!anx6345->drm_edid)
475 DRM_ERROR("Failed to read EDID from panel\n");475 DRM_ERROR("Failed to read EDID from panel\n");
476 476
477 err = drm_connector_update_edid_property(connector,477 err = drm_edid_connector_update(connector, anx6345->drm_edid);
478 anx6345->edid);
479 if (err) {478 if (err) {
480 DRM_ERROR("Failed to update EDID property: %d\n", err);479 DRM_ERROR("Failed to update EDID property: %d\n", err);
481 goto unlock;480 goto unlock;
482 }481 }
483 }482 }
484 483
485 num_modes += drm_add_edid_modes(connector, anx6345->edid);484 num_modes += drm_edid_connector_add_modes(connector);
486 485
487 /* Driver currently supports only 6bpc */486 /* Driver currently supports only 6bpc */
488 connector->display_info.bpc = 6;487 connector->display_info.bpc = 6;
@@ -528,11 +527,6 @@ static int anx6345_bridge_attach(struct drm_bridge *bridge, · 39 unmodified lines
528 return -EINVAL;527 return -EINVAL;
529 }528 }
530 529
531 if (!bridge->encoder) {
532 DRM_ERROR("Parent encoder object not found");
533 return -ENODEV;
534 }
535
536 /* Register aux channel */530 /* Register aux channel */
537 anx6345->aux.name = "DP-AUX";531 anx6345->aux.name = "DP-AUX";
538 anx6345->aux.dev = &anx6345->client->dev;532 anx6345->aux.dev = &anx6345->client->dev;
@@ -793,7 +787,7 @@ static void anx6345_i2c_remove(struct i2c_client *client) · 254 unmodified lines
793 787
794 unregister_i2c_dummy_clients(anx6345);788 unregister_i2c_dummy_clients(anx6345);
795 789
796 kfree(anx6345->edid);790 drm_edid_free(anx6345->drm_edid);
797 791
798 mutex_destroy(&anx6345->lock);792 mutex_destroy(&anx6345->lock);
799}793}
drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c+12−16
@@ -67,7 +67,7 @@ struct anx78xx { · 66 unmodified lines
67 struct drm_dp_aux aux;67 struct drm_dp_aux aux;
68 struct drm_bridge bridge;68 struct drm_bridge bridge;
69 struct i2c_client *client;69 struct i2c_client *client;
70 struct edid *edid;70 const struct drm_edid *drm_edid;
71 struct drm_connector connector;71 struct drm_connector connector;
72 struct anx78xx_platform_data pdata;72 struct anx78xx_platform_data pdata;
73 struct mutex lock;73 struct mutex lock;
@@ -830,8 +830,8 @@ static int anx78xx_get_modes(struct drm_connector *connector) · 756 unmodified lines
830 if (WARN_ON(!anx78xx->powered))830 if (WARN_ON(!anx78xx->powered))
831 return 0;831 return 0;
832 832
833 if (anx78xx->edid)833 if (anx78xx->drm_edid)
834 return drm_add_edid_modes(connector, anx78xx->edid);834 return drm_edid_connector_add_modes(connector);
835 835
836 mutex_lock(&anx78xx->lock);836 mutex_lock(&anx78xx->lock);
837 837
@@ -841,20 +841,21 @@ static int anx78xx_get_modes(struct drm_connector *connector) · 3 unmodified lines
841 goto unlock;841 goto unlock;
842 }842 }
843 843
844 anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc);844 anx78xx->drm_edid = drm_edid_read_ddc(connector, &anx78xx->aux.ddc);
845 if (!anx78xx->edid) {845
846 err = drm_edid_connector_update(connector, anx78xx->drm_edid);
847
848 if (!anx78xx->drm_edid) {
846 DRM_ERROR("Failed to read EDID\n");849 DRM_ERROR("Failed to read EDID\n");
847 goto unlock;850 goto unlock;
848 }851 }
849 852
850 err = drm_connector_update_edid_property(connector,
851 anx78xx->edid);
852 if (err) {853 if (err) {
853 DRM_ERROR("Failed to update EDID property: %d\n", err);854 DRM_ERROR("Failed to update EDID property: %d\n", err);
854 goto unlock;855 goto unlock;
855 }856 }
856 857
857 num_modes = drm_add_edid_modes(connector, anx78xx->edid);858 num_modes = drm_edid_connector_add_modes(connector);
858 859
859unlock:860unlock:
860 mutex_unlock(&anx78xx->lock);861 mutex_unlock(&anx78xx->lock);
@@ -897,11 +898,6 @@ static int anx78xx_bridge_attach(struct drm_bridge *bridge, · 36 unmodified lines
897 return -EINVAL;898 return -EINVAL;
898 }899 }
899 900
900 if (!bridge->encoder) {
901 DRM_ERROR("Parent encoder object not found");
902 return -ENODEV;
903 }
904
905 /* Register aux channel */901 /* Register aux channel */
906 anx78xx->aux.name = "DP-AUX";902 anx78xx->aux.name = "DP-AUX";
907 anx78xx->aux.dev = &anx78xx->client->dev;903 anx78xx->aux.dev = &anx78xx->client->dev;
@@ -1091,8 +1087,8 @@ static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq) · 183 unmodified lines
1091 event = true;1087 event = true;
1092 anx78xx_poweroff(anx78xx);1088 anx78xx_poweroff(anx78xx);
1093 /* Free cached EDID */1089 /* Free cached EDID */
1094 kfree(anx78xx->edid);1090 drm_edid_free(anx78xx->drm_edid);
1095 anx78xx->edid = NULL;1091 anx78xx->drm_edid = NULL;
1096 } else if (irq & SP_HPD_PLUG) {1092 } else if (irq & SP_HPD_PLUG) {
1097 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");1093 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");
1098 event = true;1094 event = true;
@@ -1363,7 +1359,7 @@ static void anx78xx_i2c_remove(struct i2c_client *client) · 264 unmodified lines
1363 1359
1364 unregister_i2c_dummy_clients(anx78xx);1360 unregister_i2c_dummy_clients(anx78xx);
1365 1361
1366 kfree(anx78xx->edid);1362 drm_edid_free(anx78xx->drm_edid);
1367}1363}
1368 1364
1369static const struct of_device_id anx78xx_match_table[] = {1365static const struct of_device_id anx78xx_match_table[] = {
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c+44−128
@@ -234,28 +234,6 @@ static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) · 233 unmodified lines
234 return ret < 0 ? ret : 0;234 return ret < 0 ? ret : 0;
235}235}
236 236
237static void
238analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
239 int pre_emphasis, int lane)
240{
241 switch (lane) {
242 case 0:
243 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
244 break;
245 case 1:
246 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
247 break;
248
249 case 2:
250 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
251 break;
252
253 case 3:
254 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
255 break;
256 }
257}
258
259static int analogix_dp_link_start(struct analogix_dp_device *dp)237static int analogix_dp_link_start(struct analogix_dp_device *dp)
260{238{
261 u8 buf[4];239 u8 buf[4];
@@ -286,10 +264,12 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp) · 24 unmodified lines
286 return retval;264 return retval;
287 }265 }
288 266
289 /* Set TX pre-emphasis to minimum */267 /* Set TX voltage-swing and pre-emphasis to minimum */
290 for (lane = 0; lane < lane_count; lane++)268 for (lane = 0; lane < lane_count; lane++)
291 analogix_dp_set_lane_lane_pre_emphasis(dp,269 dp->link_train.training_lane[lane] =
292 PRE_EMPHASIS_LEVEL_0, lane);270 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
271 DP_TRAIN_PRE_EMPH_LEVEL_0;
272 analogix_dp_set_lane_link_training(dp);
293 273
294 /* Wait for PLL lock */274 /* Wait for PLL lock */
295 pll_tries = 0;275 pll_tries = 0;
@@ -384,54 +364,6 @@ static unsigned char analogix_dp_get_adjust_request_pre_emphasis( · 88 unmodified lines
384 return ((link_value >> shift) & 0xc) >> 2;364 return ((link_value >> shift) & 0xc) >> 2;
385}365}
386 366
387static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
388 u8 training_lane_set, int lane)
389{
390 switch (lane) {
391 case 0:
392 analogix_dp_set_lane0_link_training(dp, training_lane_set);
393 break;
394 case 1:
395 analogix_dp_set_lane1_link_training(dp, training_lane_set);
396 break;
397
398 case 2:
399 analogix_dp_set_lane2_link_training(dp, training_lane_set);
400 break;
401
402 case 3:
403 analogix_dp_set_lane3_link_training(dp, training_lane_set);
404 break;
405 }
406}
407
408static unsigned int
409analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
410 int lane)
411{
412 u32 reg;
413
414 switch (lane) {
415 case 0:
416 reg = analogix_dp_get_lane0_link_training(dp);
417 break;
418 case 1:
419 reg = analogix_dp_get_lane1_link_training(dp);
420 break;
421 case 2:
422 reg = analogix_dp_get_lane2_link_training(dp);
423 break;
424 case 3:
425 reg = analogix_dp_get_lane3_link_training(dp);
426 break;
427 default:
428 WARN_ON(1);
429 return 0;
430 }
431
432 return reg;
433}
434
435static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)367static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
436{368{
437 analogix_dp_training_pattern_dis(dp);369 analogix_dp_training_pattern_dis(dp);
@@ -478,11 +410,6 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) · 40 unmodified lines
478 if (retval < 0)410 if (retval < 0)
479 return retval;411 return retval;
480 412
481 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
482 adjust_request, 2);
483 if (retval < 0)
484 return retval;
485
486 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {413 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
487 /* set training pattern 2 for EQ */414 /* set training pattern 2 for EQ */
488 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);415 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
@@ -495,38 +422,37 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) · 6 unmodified lines
495 422
496 dev_dbg(dp->dev, "Link Training Clock Recovery success\n");423 dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
497 dp->link_train.lt_state = EQUALIZER_TRAINING;424 dp->link_train.lt_state = EQUALIZER_TRAINING;
498 } else {425
499 for (lane = 0; lane < lane_count; lane++) {426 return 0;
500 training_lane = analogix_dp_get_lane_link_training(427 }
501 dp, lane);428
502 voltage_swing = analogix_dp_get_adjust_request_voltage(429 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
503 adjust_request, lane);430 adjust_request, 2);
504 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(431 if (retval < 0)
505 adjust_request, lane);432 return retval;
506 433
507 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==434 for (lane = 0; lane < lane_count; lane++) {
508 voltage_swing &&435 training_lane = analogix_dp_get_lane_link_training(dp, lane);
509 DPCD_PRE_EMPHASIS_GET(training_lane) ==436 voltage_swing = analogix_dp_get_adjust_request_voltage(adjust_request, lane);
510 pre_emphasis)437 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(adjust_request, lane);
511 dp->link_train.cr_loop[lane]++;438
512 439 if (DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing &&
513 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||440 DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis)
514 voltage_swing == VOLTAGE_LEVEL_3 ||441 dp->link_train.cr_loop[lane]++;
515 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {442
516 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",443 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
517 dp->link_train.cr_loop[lane],444 voltage_swing == VOLTAGE_LEVEL_3 ||
518 voltage_swing, pre_emphasis);445 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
519 analogix_dp_reduce_link_rate(dp);446 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
520 return -EIO;447 dp->link_train.cr_loop[lane],
521 }448 voltage_swing, pre_emphasis);
449 analogix_dp_reduce_link_rate(dp);
450 return -EIO;
522 }451 }
523 }452 }
524 453
525 analogix_dp_get_adjust_training_lane(dp, adjust_request);454 analogix_dp_get_adjust_training_lane(dp, adjust_request);
526 455 analogix_dp_set_lane_link_training(dp);
527 for (lane = 0; lane < lane_count; lane++)
528 analogix_dp_set_lane_link_training(dp,
529 dp->link_train.training_lane[lane], lane);
530 456
531 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,457 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
532 dp->link_train.training_lane, lane_count);458 dp->link_train.training_lane, lane_count);
@@ -538,7 +464,7 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) · 5 unmodified lines
538 464
539static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)465static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
540{466{
541 int lane, lane_count, retval;467 int lane_count, retval;
542 u32 reg;468 u32 reg;
543 u8 link_align, link_status[2], adjust_request[2];469 u8 link_align, link_status[2], adjust_request[2];
544 470
@@ -598,9 +524,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) · 53 unmodified lines
598 return -EIO;524 return -EIO;
599 }525 }
600 526
601 for (lane = 0; lane < lane_count; lane++)527 analogix_dp_set_lane_link_training(dp);
602 analogix_dp_set_lane_link_training(dp,
603 dp->link_train.training_lane[lane], lane);
604 528
605 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,529 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
606 dp->link_train.training_lane, lane_count);530 dp->link_train.training_lane, lane_count);
@@ -712,7 +636,7 @@ static int analogix_dp_full_link_train(struct analogix_dp_device *dp, · 105 unmodified lines
712 636
713static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)637static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
714{638{
715 int i, ret;639 int ret;
716 u8 link_align, link_status[2];640 u8 link_align, link_status[2];
717 enum pll_status status;641 enum pll_status status;
718 642
@@ -720,11 +644,7 @@ static int analogix_dp_fast_link_train(struct analogix_dp_device *dp) · 1 unmodified line
720 644
721 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);645 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
722 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);646 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
723 647 analogix_dp_set_lane_link_training(dp);
724 for (i = 0; i < dp->link_train.lane_count; i++) {
725 analogix_dp_set_lane_link_training(dp,
726 dp->link_train.training_lane[i], i);
727 }
728 648
729 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,649 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
730 status != PLL_UNLOCKED, 120,650 status != PLL_UNLOCKED, 120,
@@ -1108,7 +1028,7 @@ out: · 377 unmodified lines
1108static int analogix_dp_get_modes(struct drm_connector *connector)1028static int analogix_dp_get_modes(struct drm_connector *connector)
1109{1029{
1110 struct analogix_dp_device *dp = to_dp(connector);1030 struct analogix_dp_device *dp = to_dp(connector);
1111 struct edid *edid;1031 const struct drm_edid *drm_edid;
1112 int ret, num_modes = 0;1032 int ret, num_modes = 0;
1113 1033
1114 if (dp->plat_data->panel) {1034 if (dp->plat_data->panel) {
@@ -1120,12 +1040,13 @@ static int analogix_dp_get_modes(struct drm_connector *connector) · 5 unmodified lines
1120 return 0;1040 return 0;
1121 }1041 }
1122 1042
1123 edid = drm_get_edid(connector, &dp->aux.ddc);1043 drm_edid = drm_edid_read_ddc(connector, &dp->aux.ddc);
1124 if (edid) {1044
1125 drm_connector_update_edid_property(&dp->connector,1045 drm_edid_connector_update(&dp->connector, drm_edid);
1126 edid);1046
1127 num_modes += drm_add_edid_modes(&dp->connector, edid);1047 if (drm_edid) {
1128 kfree(edid);1048 num_modes += drm_edid_connector_add_modes(&dp->connector);
1049 drm_edid_free(drm_edid);
1129 }1050 }
1130 1051
1131 ret = analogix_dp_prepare_panel(dp, false, false);1052 ret = analogix_dp_prepare_panel(dp, false, false);
@@ -1228,11 +1149,6 @@ static int analogix_dp_bridge_attach(struct drm_bridge *bridge, · 96 unmodified lines
1228 return -EINVAL;1149 return -EINVAL;
1229 }1150 }
1230 1151
1231 if (!bridge->encoder) {
1232 DRM_ERROR("Parent encoder object not found");
1233 return -ENODEV;
1234 }
1235
1236 if (!dp->plat_data->skip_connector) {1152 if (!dp->plat_data->skip_connector) {
1237 connector = &dp->connector;1153 connector = &dp->connector;
1238 connector->polled = DRM_CONNECTOR_POLL_HPD;1154 connector->polled = DRM_CONNECTOR_POLL_HPD;
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h+2−20
@@ -213,26 +213,8 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, · 212 unmodified lines
213 bool enable);213 bool enable);
214void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,214void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
215 enum pattern_set pattern);215 enum pattern_set pattern);
216void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,216void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp);
217 u32 level);217u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane);
218void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
219 u32 level);
220void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
221 u32 level);
222void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
223 u32 level);
224void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
225 u32 training_lane);
226void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
227 u32 training_lane);
228void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
229 u32 training_lane);
230void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
231 u32 training_lane);
232u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
233u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
234u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
235u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
236void analogix_dp_reset_macro(struct analogix_dp_device *dp);218void analogix_dp_reset_macro(struct analogix_dp_device *dp);
237void analogix_dp_init_video(struct analogix_dp_device *dp);219void analogix_dp_init_video(struct analogix_dp_device *dp);
238 220
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c+15−104
@@ -557,6 +557,20 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) · 556 unmodified lines
557 *count = reg;557 *count = reg;
558}558}
559 559
560void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp)
561{
562 u8 lane;
563
564 for (lane = 0; lane < dp->link_train.lane_count; lane++)
565 writel(dp->link_train.training_lane[lane],
566 dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane);
567}
568
569u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane)
570{
571 return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane);
572}
573
560void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,574void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
561 bool enable)575 bool enable)
562{576{
@@ -606,106 +620,6 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, · 43 unmodified lines
606 }620 }
607}621}
608 622
609void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
610 u32 level)
611{
612 u32 reg;
613
614 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
615 reg &= ~PRE_EMPHASIS_SET_MASK;
616 reg |= level << PRE_EMPHASIS_SET_SHIFT;
617 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
618}
619
620void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
621 u32 level)
622{
623 u32 reg;
624
625 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
626 reg &= ~PRE_EMPHASIS_SET_MASK;
627 reg |= level << PRE_EMPHASIS_SET_SHIFT;
628 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
629}
630
631void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
632 u32 level)
633{
634 u32 reg;
635
636 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
637 reg &= ~PRE_EMPHASIS_SET_MASK;
638 reg |= level << PRE_EMPHASIS_SET_SHIFT;
639 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
640}
641
642void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
643 u32 level)
644{
645 u32 reg;
646
647 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
648 reg &= ~PRE_EMPHASIS_SET_MASK;
649 reg |= level << PRE_EMPHASIS_SET_SHIFT;
650 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
651}
652
653void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
654 u32 training_lane)
655{
656 u32 reg;
657
658 reg = training_lane;
659 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
660}
661
662void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
663 u32 training_lane)
664{
665 u32 reg;
666
667 reg = training_lane;
668 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
669}
670
671void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
672 u32 training_lane)
673{
674 u32 reg;
675
676 reg = training_lane;
677 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
678}
679
680void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
681 u32 training_lane)
682{
683 u32 reg;
684
685 reg = training_lane;
686 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
687}
688
689u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
690{
691 return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
692}
693
694u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
695{
696 return readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
697}
698
699u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
700{
701 return readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
702}
703
704u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
705{
706 return readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
707}
708
709void analogix_dp_reset_macro(struct analogix_dp_device *dp)623void analogix_dp_reset_macro(struct analogix_dp_device *dp)
710{624{
711 u32 reg;625 u32 reg;
@@ -1027,7 +941,6 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, · 315 unmodified lines
1027 u32 status_reg;941 u32 status_reg;
1028 u8 *buffer = msg->buffer;942 u8 *buffer = msg->buffer;
1029 unsigned int i;943 unsigned int i;
1030 int num_transferred = 0;
1031 int ret;944 int ret;
1032 945
1033 /* Buffer size of AUX CH is 16 bytes */946 /* Buffer size of AUX CH is 16 bytes */
@@ -1079,7 +992,6 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, · 45 unmodified lines
1079 reg = buffer[i];992 reg = buffer[i];
1080 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +993 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
1081 4 * i);994 4 * i);
1082 num_transferred++;
1083 }995 }
1084 }996 }
1085 997
@@ -1127,7 +1039,6 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, · 41 unmodified lines
1127 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +1039 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
1128 4 * i);1040 4 * i);
1129 buffer[i] = (unsigned char)reg;1041 buffer[i] = (unsigned char)reg;
1130 num_transferred++;
1131 }1042 }
1132 }1043 }
1133 1044
@@ -1144,7 +1055,7 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, · 10 unmodified lines
1144 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ)1055 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ)
1145 msg->reply = DP_AUX_NATIVE_REPLY_ACK;1056 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1146 1057
1147 return num_transferred > 0 ? num_transferred : -EBUSY;1058 return msg->size;
1148 1059
1149aux_error:1060aux_error:
1150 /* if aux err happen, reset aux */1061 /* if aux err happen, reset aux */
drivers/gpu/drm/bridge/analogix/anx7625.c+17−19
@@ -464,9 +464,11 @@ static int anx7625_odfc_config(struct anx7625_data *ctx, · 463 unmodified lines
464 */464 */
465static int anx7625_set_k_value(struct anx7625_data *ctx)465static int anx7625_set_k_value(struct anx7625_data *ctx)
466{466{
467 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data;467 struct drm_edid_product_id id;
468 468
469 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1)469 drm_edid_get_product_id(ctx->cached_drm_edid, &id);
470
471 if (be16_to_cpu(id.manufacturer_name) == IVO_MID)
470 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,472 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
471 MIPI_DIGITAL_ADJ_1, 0x3B);473 MIPI_DIGITAL_ADJ_1, 0x3B);
472 474
@@ -1526,7 +1528,8 @@ static int anx7625_wait_hpd_asserted(struct drm_dp_aux *aux, · 1053 unmodified lines
1526 1528
1527static void anx7625_remove_edid(struct anx7625_data *ctx)1529static void anx7625_remove_edid(struct anx7625_data *ctx)
1528{1530{
1529 ctx->slimport_edid_p.edid_block_num = -1;1531 drm_edid_free(ctx->cached_drm_edid);
1532 ctx->cached_drm_edid = NULL;
1530}1533}
1531 1534
1532static void anx7625_dp_adjust_swing(struct anx7625_data *ctx)1535static void anx7625_dp_adjust_swing(struct anx7625_data *ctx)
@@ -1787,27 +1790,32 @@ static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux, · 254 unmodified lines
1787static const struct drm_edid *anx7625_edid_read(struct anx7625_data *ctx)1790static const struct drm_edid *anx7625_edid_read(struct anx7625_data *ctx)
1788{1791{
1789 struct device *dev = ctx->dev;1792 struct device *dev = ctx->dev;
1790 struct s_edid_data *p_edid = &ctx->slimport_edid_p;1793 u8 *edid_buf;
1791 int edid_num;1794 int edid_num;
1792 1795
1793 if (ctx->slimport_edid_p.edid_block_num > 0)1796 if (ctx->cached_drm_edid)
1794 goto out;1797 goto out;
1795 1798
1799 edid_buf = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL);
1800 if (!edid_buf)
1801 return NULL;
1802
1796 pm_runtime_get_sync(dev);1803 pm_runtime_get_sync(dev);
1797 _anx7625_hpd_polling(ctx, 5000 * 100);1804 _anx7625_hpd_polling(ctx, 5000 * 100);
1798 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data);1805 edid_num = sp_tx_edid_read(ctx, edid_buf);
1799 pm_runtime_put_sync(dev);1806 pm_runtime_put_sync(dev);
1800 1807
1801 if (edid_num < 1) {1808 if (edid_num < 1) {
1802 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num);1809 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num);
1810 kfree(edid_buf);
1803 return NULL;1811 return NULL;
1804 }1812 }
1805 1813
1806 p_edid->edid_block_num = edid_num;1814 ctx->cached_drm_edid = drm_edid_alloc(edid_buf, FOUR_BLOCK_SIZE);
1815 kfree(edid_buf);
1807 1816
1808out:1817out:
1809 return drm_edid_alloc(ctx->slimport_edid_p.edid_raw_data,1818 return drm_edid_dup(ctx->cached_drm_edid);
1810 FOUR_BLOCK_SIZE);
1811}1819}
1812 1820
1813static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx)1821static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx)
@@ -2193,11 +2201,6 @@ static int anx7625_bridge_attach(struct drm_bridge *bridge, · 379 unmodified lines
2193 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))2201 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
2194 return -EINVAL;2202 return -EINVAL;
2195 2203
2196 if (!bridge->encoder) {
2197 DRM_DEV_ERROR(dev, "Parent encoder object not found");
2198 return -ENODEV;
2199 }
2200
2201 ctx->aux.drm_dev = bridge->dev;2204 ctx->aux.drm_dev = bridge->dev;
2202 err = drm_dp_aux_register(&ctx->aux);2205 err = drm_dp_aux_register(&ctx->aux);
2203 if (err) {2206 if (err) {
@@ -2435,11 +2438,6 @@ static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, · 231 unmodified lines
2435 2438
2436 dev_dbg(dev, "drm atomic enable\n");2439 dev_dbg(dev, "drm atomic enable\n");
2437 2440
2438 if (!bridge->encoder) {
2439 dev_err(dev, "Parent encoder object not found");
2440 return;
2441 }
2442
2443 connector = drm_atomic_get_new_connector_for_encoder(state->base.state,2441 connector = drm_atomic_get_new_connector_for_encoder(state->base.state,
2444 bridge->encoder);2442 bridge->encoder);
2445 if (!connector)2443 if (!connector)
drivers/gpu/drm/bridge/analogix/anx7625.h+2−8
@@ -286,8 +286,7 @@ · 285 unmodified lines
286 286
287#define MIPI_LANE_CTRL_10 0x0F287#define MIPI_LANE_CTRL_10 0x0F
288#define MIPI_DIGITAL_ADJ_1 0x1B288#define MIPI_DIGITAL_ADJ_1 0x1B
289#define IVO_MID0 0x26289#define IVO_MID 0x26CF
290#define IVO_MID1 0xCF
291 290
292#define MIPI_PLL_M_NUM_23_16 0x1E291#define MIPI_PLL_M_NUM_23_16 0x1E
293#define MIPI_PLL_M_NUM_15_8 0x1F292#define MIPI_PLL_M_NUM_15_8 0x1F
@@ -417,11 +416,6 @@ enum audio_wd_len { · 123 unmodified lines
417#define EDID_TRY_CNT 3416#define EDID_TRY_CNT 3
418#define SUPPORT_PIXEL_CLOCK 300000417#define SUPPORT_PIXEL_CLOCK 300000
419 418
420struct s_edid_data {
421 int edid_block_num;
422 u8 edid_raw_data[FOUR_BLOCK_SIZE];
423};
424
425/***************** Display End *****************/419/***************** Display End *****************/
426 420
427#define MAX_LANES_SUPPORT 4421#define MAX_LANES_SUPPORT 4
@@ -466,7 +460,7 @@ struct anx7625_data { · 38 unmodified lines
466 struct anx7625_i2c_client i2c;460 struct anx7625_i2c_client i2c;
467 struct i2c_client *last_client;461 struct i2c_client *last_client;
468 struct timer_list hdcp_timer;462 struct timer_list hdcp_timer;
469 struct s_edid_data slimport_edid_p;463 const struct drm_edid *cached_drm_edid;
470 struct device *codec_dev;464 struct device *codec_dev;
471 hdmi_codec_plugged_cb plugged_cb;465 hdmi_codec_plugged_cb plugged_cb;
472 struct work_struct work;466 struct work_struct work;
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c+0−5
@@ -1697,11 +1697,6 @@ static int cdns_mhdp_connector_init(struct cdns_mhdp_device *mhdp) · 1696 unmodified lines
1697 struct drm_bridge *bridge = &mhdp->bridge;1697 struct drm_bridge *bridge = &mhdp->bridge;
1698 int ret;1698 int ret;
1699 1699
1700 if (!bridge->encoder) {
1701 dev_err(mhdp->dev, "Parent encoder object not found");
1702 return -ENODEV;
1703 }
1704
1705 conn->polled = DRM_CONNECTOR_POLL_HPD;1700 conn->polled = DRM_CONNECTOR_POLL_HPD;
1706 1701
1707 ret = drm_connector_init(bridge->dev, conn, &cdns_mhdp_conn_funcs,1702 ret = drm_connector_init(bridge->dev, conn, &cdns_mhdp_conn_funcs,
drivers/gpu/drm/bridge/imx/imx-ldb-helper.c+0−5
@@ -116,11 +116,6 @@ int ldb_bridge_attach_helper(struct drm_bridge *bridge, · 115 unmodified lines
116 return -EINVAL;116 return -EINVAL;
117 }117 }
118 118
119 if (!bridge->encoder) {
120 DRM_DEV_ERROR(ldb->dev, "missing encoder\n");
121 return -ENODEV;
122 }
123
124 return drm_bridge_attach(bridge->encoder,119 return drm_bridge_attach(bridge->encoder,
125 ldb_ch->next_bridge, bridge,120 ldb_ch->next_bridge, bridge,
126 DRM_BRIDGE_ATTACH_NO_CONNECTOR);121 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c+0−5
@@ -119,11 +119,6 @@ static int imx8qxp_pc_bridge_attach(struct drm_bridge *bridge, · 118 unmodified lines
119 return -EINVAL;119 return -EINVAL;
120 }120 }
121 121
122 if (!bridge->encoder) {
123 DRM_DEV_ERROR(pc->dev, "missing encoder\n");
124 return -ENODEV;
125 }
126
127 return drm_bridge_attach(bridge->encoder,122 return drm_bridge_attach(bridge->encoder,
128 ch->next_bridge, bridge,123 ch->next_bridge, bridge,
129 DRM_BRIDGE_ATTACH_NO_CONNECTOR);124 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c+0−5
@@ -138,11 +138,6 @@ static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge, · 137 unmodified lines
138 return -EINVAL;138 return -EINVAL;
139 }139 }
140 140
141 if (!bridge->encoder) {
142 DRM_DEV_ERROR(pl->dev, "missing encoder\n");
143 return -ENODEV;
144 }
145
146 return drm_bridge_attach(bridge->encoder,141 return drm_bridge_attach(bridge->encoder,
147 pl->next_bridge, bridge,142 pl->next_bridge, bridge,
148 DRM_BRIDGE_ATTACH_NO_CONNECTOR);143 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c+0−5
@@ -58,11 +58,6 @@ static int imx8qxp_pxl2dpi_bridge_attach(struct drm_bridge *bridge, · 57 unmodified lines
58 return -EINVAL;58 return -EINVAL;
59 }59 }
60 60
61 if (!bridge->encoder) {
62 DRM_DEV_ERROR(p2d->dev, "missing encoder\n");
63 return -ENODEV;
64 }
65
66 return drm_bridge_attach(bridge->encoder,61 return drm_bridge_attach(bridge->encoder,
67 p2d->next_bridge, bridge,62 p2d->next_bridge, bridge,
68 DRM_BRIDGE_ATTACH_NO_CONNECTOR);63 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
drivers/gpu/drm/bridge/ite-it6505.c+50−30
@@ -1307,9 +1307,15 @@ static void it6505_video_reset(struct it6505 *it6505) · 1306 unmodified lines
1307 it6505_link_reset_step_train(it6505);1307 it6505_link_reset_step_train(it6505);
1308 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);1308 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1309 it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);1309 it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1310 it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);1310
1311 it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, TX_FIFO_RESET);
1312 it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x00);
1313
1311 it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO);1314 it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO);
1312 it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00);1315 it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00);
1316
1317 it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1318 usleep_range(1000, 2000);
1313 it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00);1319 it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00);
1314}1320}
1315 1321
@@ -2245,12 +2251,11 @@ static void it6505_link_training_work(struct work_struct *work) · 929 unmodified lines
2245 if (ret) {2251 if (ret) {
2246 it6505->auto_train_retry = AUTO_TRAIN_RETRY;2252 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2247 it6505_link_train_ok(it6505);2253 it6505_link_train_ok(it6505);
2248 return;
2249 } else {2254 } else {
2250 it6505->auto_train_retry--;2255 it6505->auto_train_retry--;
2256 it6505_dump(it6505);
2251 }2257 }
2252 2258
2253 it6505_dump(it6505);
2254}2259}
2255 2260
2256static void it6505_plugged_status_to_codec(struct it6505 *it6505)2261static void it6505_plugged_status_to_codec(struct it6505 *it6505)
@@ -2471,31 +2476,53 @@ static void it6505_irq_link_train_fail(struct it6505 *it6505) · 214 unmodified lines
2471 schedule_work(&it6505->link_works);2476 schedule_work(&it6505->link_works);
2472}2477}
2473 2478
2474static void it6505_irq_video_fifo_error(struct it6505 *it6505)2479static bool it6505_test_bit(unsigned int bit, const unsigned int *addr)
2475{2480{
2476 struct device *dev = it6505->dev;2481 return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE));
2477
2478 DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt");
2479 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2480 flush_work(&it6505->link_works);
2481 it6505_stop_hdcp(it6505);
2482 it6505_video_reset(it6505);
2483}2482}
2484 2483
2485static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505)2484static void it6505_irq_video_handler(struct it6505 *it6505, const int *int_status)
2486{2485{
2487 struct device *dev = it6505->dev;2486 struct device *dev = it6505->dev;
2487 int reg_0d, reg_int03;
2488 2488
2489 DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt");2489 /*
2490 it6505->auto_train_retry = AUTO_TRAIN_RETRY;2490 * When video SCDT change with video not stable,
2491 flush_work(&it6505->link_works);2491 * Or video FIFO error, need video reset
2492 it6505_stop_hdcp(it6505);2492 */
2493 it6505_video_reset(it6505);
2494}
2495 2493
2496static bool it6505_test_bit(unsigned int bit, const unsigned int *addr)2494 if ((!it6505_get_video_status(it6505) &&
2497{2495 (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *)int_status))) ||
2498 return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE));2496 (it6505_test_bit(BIT_INT_IO_FIFO_OVERFLOW,
2497 (unsigned int *)int_status)) ||
2498 (it6505_test_bit(BIT_INT_VID_FIFO_ERROR,
2499 (unsigned int *)int_status))) {
2500 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2501 flush_work(&it6505->link_works);
2502 it6505_stop_hdcp(it6505);
2503 it6505_video_reset(it6505);
2504
2505 usleep_range(10000, 11000);
2506
2507 /*
2508 * Clear FIFO error IRQ to prevent fifo error -> reset loop
2509 * HW will trigger SCDT change IRQ again when video stable
2510 */
2511
2512 reg_int03 = it6505_read(it6505, INT_STATUS_03);
2513 reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
2514
2515 reg_int03 &= (BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
2516 it6505_write(it6505, INT_STATUS_03, reg_int03);
2517
2518 DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", reg_int03);
2519 DRM_DEV_DEBUG_DRIVER(dev, "reg0D = 0x%02x", reg_0d);
2520
2521 return;
2522 }
2523
2524 if (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *)int_status))
2525 it6505_irq_scdt(it6505);
2499}2526}
2500 2527
2501static irqreturn_t it6505_int_threaded_handler(int unused, void *data)2528static irqreturn_t it6505_int_threaded_handler(int unused, void *data)
@@ -2508,15 +2535,12 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) · 6 unmodified lines
2508 } irq_vec[] = {2535 } irq_vec[] = {
2509 { BIT_INT_HPD, it6505_irq_hpd },2536 { BIT_INT_HPD, it6505_irq_hpd },
2510 { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq },2537 { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq },
2511 { BIT_INT_SCDT, it6505_irq_scdt },
2512 { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail },2538 { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail },
2513 { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done },2539 { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done },
2514 { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail },2540 { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail },
2515 { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check },2541 { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check },
2516 { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error },2542 { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error },
2517 { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail },2543 { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail },
2518 { BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error },
2519 { BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow },
2520 };2544 };
2521 int int_status[3], i;2545 int int_status[3], i;
2522 2546
@@ -2546,6 +2570,7 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) · 23 unmodified lines
2546 if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status))2570 if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status))
2547 irq_vec[i].handler(it6505);2571 irq_vec[i].handler(it6505);
2548 }2572 }
2573 it6505_irq_video_handler(it6505, (unsigned int *)int_status);
2549 }2574 }
2550 2575
2551 pm_runtime_put_sync(dev);2576 pm_runtime_put_sync(dev);
@@ -2590,7 +2615,7 @@ static int it6505_poweron(struct it6505 *it6505) · 38 unmodified lines
2590 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);2615 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2591 usleep_range(1000, 2000);2616 usleep_range(1000, 2000);
2592 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);2617 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
2593 usleep_range(10000, 20000);2618 usleep_range(25000, 35000);
2594 }2619 }
2595 2620
2596 it6505->powered = true;2621 it6505->powered = true;
@@ -2882,11 +2907,6 @@ static int it6505_bridge_attach(struct drm_bridge *bridge, · 285 unmodified lines
2882 return -EINVAL;2907 return -EINVAL;
2883 }2908 }
2884 2909
2885 if (!bridge->encoder) {
2886 dev_err(dev, "Parent encoder object not found");
2887 return -ENODEV;
2888 }
2889
2890 /* Register aux channel */2910 /* Register aux channel */
2891 it6505->aux.drm_dev = bridge->dev;2911 it6505->aux.drm_dev = bridge->dev;
2892 2912
drivers/gpu/drm/bridge/lontium-lt9611.c+1−0
@@ -1195,4 +1195,5 @@ static struct i2c_driver lt9611_driver = { · 1194 unmodified lines
1195};1195};
1196module_i2c_driver(lt9611_driver);1196module_i2c_driver(lt9611_driver);
1197 1197
1198MODULE_DESCRIPTION("Lontium LT9611 DSI/HDMI bridge driver");
1198MODULE_LICENSE("GPL v2");1199MODULE_LICENSE("GPL v2");
drivers/gpu/drm/bridge/lontium-lt9611uxc.c+1−5
@@ -337,11 +337,6 @@ static int lt9611uxc_connector_init(struct drm_bridge *bridge, struct lt9611uxc · 336 unmodified lines
337{337{
338 int ret;338 int ret;
339 339
340 if (!bridge->encoder) {
341 DRM_ERROR("Parent encoder object not found");
342 return -ENODEV;
343 }
344
345 lt9611uxc->connector.polled = DRM_CONNECTOR_POLL_HPD;340 lt9611uxc->connector.polled = DRM_CONNECTOR_POLL_HPD;
346 341
347 drm_connector_helper_add(&lt9611uxc->connector,342 drm_connector_helper_add(&lt9611uxc->connector,
@@ -1021,6 +1016,7 @@ static struct i2c_driver lt9611uxc_driver = { · 673 unmodified lines
1021module_i2c_driver(lt9611uxc_driver);1016module_i2c_driver(lt9611uxc_driver);
1022 1017
1023MODULE_AUTHOR("Dmitry Baryshkov <dmitry.baryshkov@linaro.org>");1018MODULE_AUTHOR("Dmitry Baryshkov <dmitry.baryshkov@linaro.org>");
1019MODULE_DESCRIPTION("Lontium LT9611UXC DSI/HDMI bridge driver");
1024MODULE_LICENSE("GPL v2");1020MODULE_LICENSE("GPL v2");
1025 1021
1026MODULE_FIRMWARE(FW_FILE);1022MODULE_FIRMWARE(FW_FILE);
drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c+0−5
@@ -165,11 +165,6 @@ static int ge_b850v3_lvds_create_connector(struct drm_bridge *bridge) · 164 unmodified lines
165 struct drm_connector *connector = &ge_b850v3_lvds_ptr->connector;165 struct drm_connector *connector = &ge_b850v3_lvds_ptr->connector;
166 int ret;166 int ret;
167 167
168 if (!bridge->encoder) {
169 DRM_ERROR("Parent encoder object not found");
170 return -ENODEV;
171 }
172
173 connector->polled = DRM_CONNECTOR_POLL_HPD;168 connector->polled = DRM_CONNECTOR_POLL_HPD;
174 169
175 drm_connector_helper_add(connector,170 drm_connector_helper_add(connector,
drivers/gpu/drm/bridge/nxp-ptn3460.c+0−5
@@ -229,11 +229,6 @@ static int ptn3460_bridge_attach(struct drm_bridge *bridge, · 228 unmodified lines
229 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)229 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
230 return 0;230 return 0;
231 231
232 if (!bridge->encoder) {
233 DRM_ERROR("Parent encoder object not found");
234 return -ENODEV;
235 }
236
237 ptn_bridge->connector.polled = DRM_CONNECTOR_POLL_HPD;232 ptn_bridge->connector.polled = DRM_CONNECTOR_POLL_HPD;
238 ret = drm_connector_init(bridge->dev, &ptn_bridge->connector,233 ret = drm_connector_init(bridge->dev, &ptn_bridge->connector,
239 &ptn3460_connector_funcs, DRM_MODE_CONNECTOR_LVDS);234 &ptn3460_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
drivers/gpu/drm/bridge/panel.c+0−5
@@ -67,11 +67,6 @@ static int panel_bridge_attach(struct drm_bridge *bridge, · 66 unmodified lines
67 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)67 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
68 return 0;68 return 0;
69 69
70 if (!bridge->encoder) {
71 DRM_ERROR("Missing encoder\n");
72 return -ENODEV;
73 }
74
75 drm_connector_helper_add(connector,70 drm_connector_helper_add(connector,
76 &panel_bridge_connector_helper_funcs);71 &panel_bridge_connector_helper_funcs);
77 72
drivers/gpu/drm/bridge/samsung-dsim.c+23−2
@@ -574,8 +574,8 @@ static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi, · 573 unmodified lines
574 u16 _m, best_m;574 u16 _m, best_m;
575 u8 _s, best_s;575 u8 _s, best_s;
576 576
577 p_min = DIV_ROUND_UP(fin, (12 * MHZ));577 p_min = DIV_ROUND_UP(fin, (driver_data->pll_fin_max * MHZ));
578 p_max = fin / (6 * MHZ);578 p_max = fin / (driver_data->pll_fin_min * MHZ);
579 579
580 for (_p = p_min; _p <= p_max; ++_p) {580 for (_p = p_min; _p <= p_max; ++_p) {
581 for (_s = 0; _s <= 5; ++_s) {581 for (_s = 0; _s <= 5; ++_s) {
@@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge, · 1024 unmodified lines
1606 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);1606 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1607 }1607 }
1608 1608
1609 /*
1610 * When using video sync pulses, the HFP, HBP, and HSA are divided between
1611 * the available lanes if there is more than one lane. For certain
1612 * timings and lane configurations, the HFP may not be evenly divisible.
1613 * If the HFP is rounded down, it ends up being too small which can cause
1614 * some monitors to not sync properly. In these instances, adjust htotal
1615 * and hsync to round the HFP up, and recalculate the htotal. Through trial
1616 * and error, it appears that the HBP and HSA do not appearto need the same
1617 * correction that HFP does.
1618 */
1619 if (dsi->lanes > 1) {
1620 int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay;
1621 int remainder = hfp % dsi->lanes;
1622
1623 if (remainder) {
1624 adjusted_mode->hsync_start += remainder;
1625 adjusted_mode->hsync_end += remainder;
1626 adjusted_mode->htotal += remainder;
1627 }
1628 }
1629
1609 return 0;1630 return 0;
1610}1631}
1611 1632
drivers/gpu/drm/bridge/sii902x.c+33−13
@@ -163,6 +163,14 @@ · 162 unmodified lines
163 163
164#define SII902X_AUDIO_PORT_INDEX 3164#define SII902X_AUDIO_PORT_INDEX 3
165 165
166/*
167 * The maximum resolution supported by the HDMI bridge is 1080p@60Hz
168 * and 1920x1200 requiring a pixel clock of 165MHz and the minimum
169 * resolution supported is 480p@60Hz requiring a pixel clock of 25MHz
170 */
171#define SII902X_MIN_PIXEL_CLOCK_KHZ 25000
172#define SII902X_MAX_PIXEL_CLOCK_KHZ 165000
173
166struct sii902x {174struct sii902x {
167 struct i2c_client *i2c;175 struct i2c_client *i2c;
168 struct regmap *regmap;176 struct regmap *regmap;
@@ -310,20 +318,12 @@ static int sii902x_get_modes(struct drm_connector *connector) · 141 unmodified lines
310 return num;318 return num;
311}319}
312 320
313static enum drm_mode_status sii902x_mode_valid(struct drm_connector *connector,
314 struct drm_display_mode *mode)
315{
316 /* TODO: check mode */
317
318 return MODE_OK;
319}
320
321static const struct drm_connector_helper_funcs sii902x_connector_helper_funcs = {321static const struct drm_connector_helper_funcs sii902x_connector_helper_funcs = {
322 .get_modes = sii902x_get_modes,322 .get_modes = sii902x_get_modes,
323 .mode_valid = sii902x_mode_valid,
324};323};
325 324
326static void sii902x_bridge_disable(struct drm_bridge *bridge)325static void sii902x_bridge_atomic_disable(struct drm_bridge *bridge,
326 struct drm_bridge_state *old_bridge_state)
327{327{
328 struct sii902x *sii902x = bridge_to_sii902x(bridge);328 struct sii902x *sii902x = bridge_to_sii902x(bridge);
329 329
@@ -336,7 +336,8 @@ static void sii902x_bridge_disable(struct drm_bridge *bridge) · 6 unmodified lines
336 mutex_unlock(&sii902x->mutex);336 mutex_unlock(&sii902x->mutex);
337}337}
338 338
339static void sii902x_bridge_enable(struct drm_bridge *bridge)339static void sii902x_bridge_atomic_enable(struct drm_bridge *bridge,
340 struct drm_bridge_state *old_bridge_state)
340{341{
341 struct sii902x *sii902x = bridge_to_sii902x(bridge);342 struct sii902x *sii902x = bridge_to_sii902x(bridge);
342 343
@@ -495,6 +496,10 @@ static int sii902x_bridge_atomic_check(struct drm_bridge *bridge, · 152 unmodified lines
495 struct drm_crtc_state *crtc_state,496 struct drm_crtc_state *crtc_state,
496 struct drm_connector_state *conn_state)497 struct drm_connector_state *conn_state)
497{498{
499 if (crtc_state->mode.clock < SII902X_MIN_PIXEL_CLOCK_KHZ ||
500 crtc_state->mode.clock > SII902X_MAX_PIXEL_CLOCK_KHZ)
501 return -EINVAL;
502
498 /*503 /*
499 * There might be flags negotiation supported in future but504 * There might be flags negotiation supported in future but
500 * set the bus flags in atomic_check statically for now.505 * set the bus flags in atomic_check statically for now.
@@ -504,11 +509,25 @@ static int sii902x_bridge_atomic_check(struct drm_bridge *bridge, · 3 unmodified lines
504 return 0;509 return 0;
505}510}
506 511
512static enum drm_mode_status
513sii902x_bridge_mode_valid(struct drm_bridge *bridge,
514 const struct drm_display_info *info,
515 const struct drm_display_mode *mode)
516{
517 if (mode->clock < SII902X_MIN_PIXEL_CLOCK_KHZ)
518 return MODE_CLOCK_LOW;
519
520 if (mode->clock > SII902X_MAX_PIXEL_CLOCK_KHZ)
521 return MODE_CLOCK_HIGH;
522
523 return MODE_OK;
524}
525
507static const struct drm_bridge_funcs sii902x_bridge_funcs = {526static const struct drm_bridge_funcs sii902x_bridge_funcs = {
508 .attach = sii902x_bridge_attach,527 .attach = sii902x_bridge_attach,
509 .mode_set = sii902x_bridge_mode_set,528 .mode_set = sii902x_bridge_mode_set,
510 .disable = sii902x_bridge_disable,529 .atomic_disable = sii902x_bridge_atomic_disable,
511 .enable = sii902x_bridge_enable,530 .atomic_enable = sii902x_bridge_atomic_enable,
512 .detect = sii902x_bridge_detect,531 .detect = sii902x_bridge_detect,
513 .edid_read = sii902x_bridge_edid_read,532 .edid_read = sii902x_bridge_edid_read,
514 .atomic_reset = drm_atomic_helper_bridge_reset,533 .atomic_reset = drm_atomic_helper_bridge_reset,
@@ -516,6 +535,7 @@ static const struct drm_bridge_funcs sii902x_bridge_funcs = { · 1 unmodified line
516 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,535 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
517 .atomic_get_input_bus_fmts = sii902x_bridge_atomic_get_input_bus_fmts,536 .atomic_get_input_bus_fmts = sii902x_bridge_atomic_get_input_bus_fmts,
518 .atomic_check = sii902x_bridge_atomic_check,537 .atomic_check = sii902x_bridge_atomic_check,
538 .mode_valid = sii902x_bridge_mode_valid,
519};539};
520 540
521static int sii902x_mute(struct sii902x *sii902x, bool mute)541static int sii902x_mute(struct sii902x *sii902x, bool mute)
drivers/gpu/drm/bridge/sii9234.c+1−0
@@ -961,4 +961,5 @@ static struct i2c_driver sii9234_driver = { · 960 unmodified lines
961};961};
962 962
963module_i2c_driver(sii9234_driver);963module_i2c_driver(sii9234_driver);
964MODULE_DESCRIPTION("Silicon Image SII9234 HDMI/MHL bridge driver");
964MODULE_LICENSE("GPL");965MODULE_LICENSE("GPL");
drivers/gpu/drm/bridge/sil-sii8620.c+1−0
@@ -2384,4 +2384,5 @@ static struct i2c_driver sii8620_driver = { · 2383 unmodified lines
2384};2384};
2385 2385
2386module_i2c_driver(sii8620_driver);2386module_i2c_driver(sii8620_driver);
2387MODULE_DESCRIPTION("Silicon Image SiI8620 HDMI/MHL bridge driver");
2387MODULE_LICENSE("GPL v2");2388MODULE_LICENSE("GPL v2");
drivers/gpu/drm/bridge/simple-bridge.c+1−17
@@ -116,11 +116,6 @@ static int simple_bridge_attach(struct drm_bridge *bridge, · 115 unmodified lines
116 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)116 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
117 return 0;117 return 0;
118 118
119 if (!bridge->encoder) {
120 DRM_ERROR("Missing encoder\n");
121 return -ENODEV;
122 }
123
124 drm_connector_helper_add(&sbridge->connector,119 drm_connector_helper_add(&sbridge->connector,
125 &simple_bridge_con_helper_funcs);120 &simple_bridge_con_helper_funcs);
126 ret = drm_connector_init_with_ddc(bridge->dev, &sbridge->connector,121 ret = drm_connector_init_with_ddc(bridge->dev, &sbridge->connector,
@@ -175,7 +170,6 @@ static int simple_bridge_probe(struct platform_device *pdev) · 48 unmodified lines
175 sbridge = devm_kzalloc(&pdev->dev, sizeof(*sbridge), GFP_KERNEL);170 sbridge = devm_kzalloc(&pdev->dev, sizeof(*sbridge), GFP_KERNEL);
176 if (!sbridge)171 if (!sbridge)
177 return -ENOMEM;172 return -ENOMEM;
178 platform_set_drvdata(pdev, sbridge);
179 173
180 sbridge->info = of_device_get_match_data(&pdev->dev);174 sbridge->info = of_device_get_match_data(&pdev->dev);
181 175
@@ -213,16 +207,7 @@ static int simple_bridge_probe(struct platform_device *pdev) · 31 unmodified lines
213 sbridge->bridge.of_node = pdev->dev.of_node;207 sbridge->bridge.of_node = pdev->dev.of_node;
214 sbridge->bridge.timings = sbridge->info->timings;208 sbridge->bridge.timings = sbridge->info->timings;
215 209
216 drm_bridge_add(&sbridge->bridge);210 return devm_drm_bridge_add(&pdev->dev, &sbridge->bridge);
217
218 return 0;
219}
220
221static void simple_bridge_remove(struct platform_device *pdev)
222{
223 struct simple_bridge *sbridge = platform_get_drvdata(pdev);
224
225 drm_bridge_remove(&sbridge->bridge);
226}211}
227 212
228/*213/*
@@ -299,7 +284,6 @@ MODULE_DEVICE_TABLE(of, simple_bridge_match); · 70 unmodified lines
299 284
300static struct platform_driver simple_bridge_driver = {285static struct platform_driver simple_bridge_driver = {
301 .probe = simple_bridge_probe,286 .probe = simple_bridge_probe,
302 .remove_new = simple_bridge_remove,
303 .driver = {287 .driver = {
304 .name = "simple-bridge",288 .name = "simple-bridge",
305 .of_match_table = simple_bridge_match,289 .of_match_table = simple_bridge_match,
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c+0−5
@@ -1071,11 +1071,6 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge, · 1070 unmodified lines
1071{1071{
1072 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);1072 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
1073 1073
1074 if (!bridge->encoder) {
1075 DRM_ERROR("Parent encoder object not found\n");
1076 return -ENODEV;
1077 }
1078
1079 /* Set the encoder type as caller does not know it */1074 /* Set the encoder type as caller does not know it */
1080 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;1075 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
1081 1076
drivers/gpu/drm/bridge/tc358767.c+22−5
@@ -382,6 +382,9 @@ struct tc_data { · 381 unmodified lines
382 382
383 /* HPD pin number (0 or 1) or -ENODEV */383 /* HPD pin number (0 or 1) or -ENODEV */
384 int hpd_pin;384 int hpd_pin;
385
386 /* Number of pixels to subtract from a line due to pixel clock delta */
387 u32 line_pixel_subtract;
385};388};
386 389
387static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)390static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
@@ -577,6 +580,11 @@ static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) · 189 unmodified lines
577 return 0;580 return 0;
578}581}
579 582
583static u32 div64_round_up(u64 v, u32 d)
584{
585 return div_u64(v + d - 1, d);
586}
587
580static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)588static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
581{589{
582 int ret;590 int ret;
@@ -658,8 +666,11 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) · 75 unmodified lines
658 return -EINVAL;666 return -EINVAL;
659 }667 }
660 668
661 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,669 tc->line_pixel_subtract = tc->mode.htotal -
662 best_delta);670 div64_round_up(tc->mode.htotal * (u64)best_pixelclock, pixelclock);
671
672 dev_dbg(tc->dev, "PLL: got %d, delta %d (subtract %d px)\n", best_pixelclock,
673 best_delta, tc->line_pixel_subtract);
663 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,674 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
664 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);675 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
665 676
@@ -885,6 +896,12 @@ static int tc_set_common_video_mode(struct tc_data *tc, · 219 unmodified lines
885 upper_margin, lower_margin, vsync_len);896 upper_margin, lower_margin, vsync_len);
886 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);897 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
887 898
899 if (right_margin > tc->line_pixel_subtract) {
900 right_margin -= tc->line_pixel_subtract;
901 } else {
902 dev_err(tc->dev, "Bridge pixel clock too slow for mode\n");
903 right_margin = 0;
904 }
888 905
889 /*906 /*
890 * LCD Ctl Frame Size907 * LCD Ctl Frame Size
@@ -894,7 +911,7 @@ static int tc_set_common_video_mode(struct tc_data *tc, · 3 unmodified lines
894 */911 */
895 ret = regmap_write(tc->regmap, VPCTRL0,912 ret = regmap_write(tc->regmap, VPCTRL0,
896 FIELD_PREP(VSDELAY, right_margin + 10) |913 FIELD_PREP(VSDELAY, right_margin + 10) |
897 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);914 OPXLFMT_RGB888 | FRMSYNC_ENABLED | MSF_DISABLED);
898 if (ret)915 if (ret)
899 return ret;916 return ret;
900 917
@@ -1629,7 +1646,7 @@ tc_edp_mode_valid(struct drm_bridge *bridge, · 728 unmodified lines
1629 u32 req, avail;1646 u32 req, avail;
1630 u32 bits_per_pixel = 24;1647 u32 bits_per_pixel = 24;
1631 1648
1632 /* DPI interface clock limitation: upto 154 MHz */1649 /* DPI->(e)DP interface clock limitation: up to 154 MHz */
1633 if (mode->clock > 154000)1650 if (mode->clock > 154000)
1634 return MODE_CLOCK_HIGH;1651 return MODE_CLOCK_HIGH;
1635 1652
@@ -2135,7 +2152,7 @@ static irqreturn_t tc_irq_handler(int irq, void *arg) · 499 unmodified lines
2135 dev_err(tc->dev, "syserr %x\n", stat);2152 dev_err(tc->dev, "syserr %x\n", stat);
2136 }2153 }
2137 2154
2138 if (tc->hpd_pin >= 0 && tc->bridge.dev) {2155 if (tc->hpd_pin >= 0 && tc->bridge.dev && tc->aux.drm_dev) {
2139 /*2156 /*
2140 * H is triggered when the GPIO goes high.2157 * H is triggered when the GPIO goes high.
2141 *2158 *
drivers/gpu/drm/bridge/ti-tfp410.c+0−5
@@ -133,11 +133,6 @@ static int tfp410_attach(struct drm_bridge *bridge, · 132 unmodified lines
133 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)133 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
134 return 0;134 return 0;
135 135
136 if (!bridge->encoder) {
137 dev_err(dvi->dev, "Missing encoder\n");
138 return -ENODEV;
139 }
140
141 if (dvi->next_bridge->ops & DRM_BRIDGE_OP_DETECT)136 if (dvi->next_bridge->ops & DRM_BRIDGE_OP_DETECT)
142 dvi->connector.polled = DRM_CONNECTOR_POLL_HPD;137 dvi->connector.polled = DRM_CONNECTOR_POLL_HPD;
143 else138 else
drivers/gpu/drm/ci/build-igt.sh+40−1
@@ -3,6 +3,30 @@ · 2 unmodified lines
3 3
4set -ex4set -ex
5 5
6function generate_testlist {
7 set +x
8 while read -r line; do
9 if [ "$line" = "TESTLIST" ] || [ "$line" = "END TESTLIST" ]; then
10 continue
11 fi
12
13 tests=$(echo "$line" | tr ' ' '\n')
14
15 for test in $tests; do
16 output=$(/igt/libexec/igt-gpu-tools/"$test" --list-subtests || true)
17
18 if [ -z "$output" ]; then
19 echo "$test"
20 else
21 echo "$output" | while read -r subtest; do
22 echo "$test@$subtest"
23 done
24 fi
25 done
26 done < /igt/libexec/igt-gpu-tools/test-list.txt > /igt/libexec/igt-gpu-tools/ci-testlist.txt
27 set -x
28}
29
6git clone https://gitlab.freedesktop.org/drm/igt-gpu-tools.git --single-branch --no-checkout30git clone https://gitlab.freedesktop.org/drm/igt-gpu-tools.git --single-branch --no-checkout
7cd igt-gpu-tools31cd igt-gpu-tools
8git checkout $IGT_VERSION32git checkout $IGT_VERSION
@@ -21,15 +45,30 @@ MESON_OPTIONS="-Doverlay=disabled \ · 12 unmodified lines
21 -Dlibunwind=enabled \45 -Dlibunwind=enabled \
22 -Dprefix=/igt"46 -Dprefix=/igt"
23 47
48if [[ "$KERNEL_ARCH" = "arm64" ]] || [[ "$KERNEL_ARCH" = "arm" ]]; then
49 MESON_OPTIONS="$MESON_OPTIONS -Dxe_driver=disabled"
50fi
51
24mkdir -p /igt52mkdir -p /igt
25meson build $MESON_OPTIONS $EXTRA_MESON_ARGS53meson build $MESON_OPTIONS $EXTRA_MESON_ARGS
26ninja -C build -j${FDO_CI_CONCURRENT:-4} || ninja -C build -j 154ninja -C build -j${FDO_CI_CONCURRENT:-4} || ninja -C build -j 1
27ninja -C build install55ninja -C build install
28 56
57if [[ "$KERNEL_ARCH" = "arm64" ]]; then
58 export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib/aarch64-linux-gnu
59elif [[ "$KERNEL_ARCH" = "arm" ]]; then
60 export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib
61else
62 export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib64
63fi
64
65echo "Generating ci-testlist.txt"
66generate_testlist
67
29mkdir -p artifacts/68mkdir -p artifacts/
30tar -cf artifacts/igt.tar /igt69tar -cf artifacts/igt.tar /igt
31 70
32# Pass needed files to the test stage71# Pass needed files to the test stage
33S3_ARTIFACT_NAME="igt.tar.gz"72S3_ARTIFACT_NAME="igt.tar.gz"
34gzip -c artifacts/igt.tar > ${S3_ARTIFACT_NAME}73gzip -c artifacts/igt.tar > ${S3_ARTIFACT_NAME}
35ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" ${S3_ARTIFACT_NAME} https://${PIPELINE_ARTIFACTS_BASE}/${KERNEL_ARCH}/${S3_ARTIFACT_NAME}74ci-fairy s3cp --token-file "${S3_JWT_FILE}" ${S3_ARTIFACT_NAME} https://${PIPELINE_ARTIFACTS_BASE}/${KERNEL_ARCH}/${S3_ARTIFACT_NAME}
drivers/gpu/drm/ci/build.sh+7−3
@@ -12,6 +12,9 @@ rm -rf .git/rebase-apply · 11 unmodified lines
12apt-get update12apt-get update
13apt-get install -y libssl-dev13apt-get install -y libssl-dev
14 14
15# for msm header validation
16apt-get install -y python3-lxml
17
15if [[ "$KERNEL_ARCH" = "arm64" ]]; then18if [[ "$KERNEL_ARCH" = "arm64" ]]; then
16 GCC_ARCH="aarch64-linux-gnu"19 GCC_ARCH="aarch64-linux-gnu"
17 DEBIAN_ARCH="arm64"20 DEBIAN_ARCH="arm64"
@@ -128,6 +131,7 @@ fi · 110 unmodified lines
128# Pass needed files to the test stage131# Pass needed files to the test stage
129mkdir -p install132mkdir -p install
130cp -rfv .gitlab-ci/* install/.133cp -rfv .gitlab-ci/* install/.
134cp -rfv ci/* install/.
131cp -rfv install/common install/ci-common135cp -rfv install/common install/ci-common
132cp -rfv drivers/gpu/drm/ci/* install/.136cp -rfv drivers/gpu/drm/ci/* install/.
133 137
@@ -141,21 +145,21 @@ if [[ "$UPLOAD_TO_MINIO" = "1" ]]; then · 7 unmodified lines
141 FILES_TO_UPLOAD="$FILES_TO_UPLOAD $(basename -a $DEVICE_TREES)"145 FILES_TO_UPLOAD="$FILES_TO_UPLOAD $(basename -a $DEVICE_TREES)"
142 fi146 fi
143 147
148 ls -l "${S3_JWT_FILE}"
144 for f in $FILES_TO_UPLOAD; do149 for f in $FILES_TO_UPLOAD; do
145 ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" /lava-files/$f \150 ci-fairy s3cp --token-file "${S3_JWT_FILE}" /lava-files/$f \
146 https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/$f151 https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/$f
147 done152 done
148 153
149 S3_ARTIFACT_NAME="kernel-files.tar.zst"154 S3_ARTIFACT_NAME="kernel-files.tar.zst"
150 tar --zstd -cf $S3_ARTIFACT_NAME install155 tar --zstd -cf $S3_ARTIFACT_NAME install
151 ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" ${S3_ARTIFACT_NAME} https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/${S3_ARTIFACT_NAME}156 ci-fairy s3cp --token-file "${S3_JWT_FILE}" ${S3_ARTIFACT_NAME} https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/${S3_ARTIFACT_NAME}
152 157
153 echo "Download vmlinux.xz from https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/vmlinux.xz"158 echo "Download vmlinux.xz from https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/vmlinux.xz"
154fi159fi
155 160
156mkdir -p artifacts/install/lib161mkdir -p artifacts/install/lib
157mv install/* artifacts/install/.162mv install/* artifacts/install/.
158rm -rf artifacts/install/modules
159ln -s common artifacts/install/ci-common163ln -s common artifacts/install/ci-common
160cp .config artifacts/${CI_JOB_NAME}_config164cp .config artifacts/${CI_JOB_NAME}_config
161 165
drivers/gpu/drm/ci/build.yml+1−0
@@ -106,6 +106,7 @@ build-nodebugfs:arm64: · 105 unmodified lines
106 extends: .build:arm64106 extends: .build:arm64
107 variables:107 variables:
108 DISABLE_KCONFIGS: "DEBUG_FS"108 DISABLE_KCONFIGS: "DEBUG_FS"
109 ENABLE_KCONFIGS: "EXPERT DRM_MSM_VALIDATE_XML"
109 110
110build:x86_64:111build:x86_64:
111 extends: .build:x86_64112 extends: .build:x86_64
drivers/gpu/drm/ci/container.yml+4−8
@@ -36,15 +36,15 @@ debian/android_build: · 35 unmodified lines
36 rules:36 rules:
37 - when: never37 - when: never
38 38
39debian/x86_64_test-android:39.debian/x86_64_test-android:
40 rules:40 rules:
41 - when: never41 - when: never
42 42
43windows_build_vs2019:43windows_build_msvc:
44 rules:44 rules:
45 - when: never45 - when: never
46 46
47windows_test_vs2019:47windows_test_msvc:
48 rules:48 rules:
49 - when: never49 - when: never
50 50
@@ -56,10 +56,6 @@ rustfmt: · 5 unmodified lines
56 rules:56 rules:
57 - when: never57 - when: never
58 58
59windows_vs2019:59windows_msvc:
60 rules:
61 - when: never
62
63clang-format:
64 rules:60 rules:
65 - when: never61 - when: never
drivers/gpu/drm/ci/gitlab-ci.yml+32−15
@@ -1,11 +1,11 @@
1variables:1variables:
2 DRM_CI_PROJECT_PATH: &drm-ci-project-path mesa/mesa2 DRM_CI_PROJECT_PATH: &drm-ci-project-path mesa/mesa
3 DRM_CI_COMMIT_SHA: &drm-ci-commit-sha 9d162de9a05155e1c4041857a5848842749164cf3 DRM_CI_COMMIT_SHA: &drm-ci-commit-sha e2b9c5a9e3e4f9b532067af8022eaef8d6fc6c00
4 4
5 UPSTREAM_REPO: git://anongit.freedesktop.org/drm/drm5 UPSTREAM_REPO: git://anongit.freedesktop.org/drm/drm
6 TARGET_BRANCH: drm-next6 TARGET_BRANCH: drm-next
7 7
8 IGT_VERSION: d2af13d9f5be5ce23d996e4afd3e45990f5ab9778 IGT_VERSION: 0df7b9b97f9da0e364f5ee30fe331004b8c86b56
9 9
10 DEQP_RUNNER_GIT_URL: https://gitlab.freedesktop.org/anholt/deqp-runner.git10 DEQP_RUNNER_GIT_URL: https://gitlab.freedesktop.org/anholt/deqp-runner.git
11 DEQP_RUNNER_GIT_TAG: v0.15.011 DEQP_RUNNER_GIT_TAG: v0.15.0
@@ -19,33 +19,47 @@ variables: · 7 unmodified lines
19 bash download-git-cache.sh19 bash download-git-cache.sh
20 rm download-git-cache.sh20 rm download-git-cache.sh
21 set +o xtrace21 set +o xtrace
22 S3_JWT_FILE: /s3_jwt
22 S3_HOST: s3.freedesktop.org23 S3_HOST: s3.freedesktop.org
24 # This bucket is used to fetch the kernel image
25 S3_KERNEL_BUCKET: mesa-rootfs
26 # Bucket for git cache
27 S3_GITCACHE_BUCKET: git-cache
28 # Bucket for the pipeline artifacts pushed to S3
29 S3_ARTIFACTS_BUCKET: artifacts
23 # per-pipeline artifact storage on MinIO30 # per-pipeline artifact storage on MinIO
24 PIPELINE_ARTIFACTS_BASE: ${S3_HOST}/artifacts/${CI_PROJECT_PATH}/${CI_PIPELINE_ID}31 PIPELINE_ARTIFACTS_BASE: ${S3_HOST}/${S3_ARTIFACTS_BUCKET}/${CI_PROJECT_PATH}/${CI_PIPELINE_ID}
25 # per-job artifact storage on MinIO32 # per-job artifact storage on MinIO
26 JOB_ARTIFACTS_BASE: ${PIPELINE_ARTIFACTS_BASE}/${CI_JOB_ID}33 JOB_ARTIFACTS_BASE: ${PIPELINE_ARTIFACTS_BASE}/${CI_JOB_ID}
27 # default kernel for rootfs before injecting the current kernel tree34 # default kernel for rootfs before injecting the current kernel tree
28 KERNEL_REPO: "gfx-ci/linux"35 KERNEL_REPO: "gfx-ci/linux"
29 KERNEL_TAG: "v6.6.4-for-mesa-ci-e4f4c500f7fb"36 KERNEL_TAG: "v6.6.21-mesa-f8ea"
30 KERNEL_IMAGE_BASE: https://${S3_HOST}/mesa-lava/${KERNEL_REPO}/${KERNEL_TAG}37 KERNEL_IMAGE_BASE: https://${S3_HOST}/${S3_KERNEL_BUCKET}/${KERNEL_REPO}/${KERNEL_TAG}
38 PKG_REPO_REV: "3cc12a2a"
31 LAVA_TAGS: subset-1-gfx39 LAVA_TAGS: subset-1-gfx
32 LAVA_JOB_PRIORITY: 3040 LAVA_JOB_PRIORITY: 30
41 ARTIFACTS_BASE_URL: https://${CI_PROJECT_ROOT_NAMESPACE}.${CI_PAGES_DOMAIN}/-/${CI_PROJECT_NAME}/-/jobs/${CI_JOB_ID}/artifacts
42 # Python scripts for structured logger
43 PYTHONPATH: "$PYTHONPATH:$CI_PROJECT_DIR/install"
33 44
34default:45default:
46 id_tokens:
47 S3_JWT:
48 aud: https://s3.freedesktop.org
35 before_script:49 before_script:
36 - export SCRIPTS_DIR=$(mktemp -d)50 - export SCRIPTS_DIR=$(mktemp -d)
37 - curl -L -s --retry 4 -f --retry-all-errors --retry-delay 60 -O --output-dir "${SCRIPTS_DIR}" "${DRM_CI_PROJECT_URL}/-/raw/${DRM_CI_COMMIT_SHA}/.gitlab-ci/setup-test-env.sh"51 - curl -L -s --retry 4 -f --retry-all-errors --retry-delay 60 -O --output-dir "${SCRIPTS_DIR}" "${DRM_CI_PROJECT_URL}/-/raw/${DRM_CI_COMMIT_SHA}/.gitlab-ci/setup-test-env.sh"
38 - source ${SCRIPTS_DIR}/setup-test-env.sh52 - source ${SCRIPTS_DIR}/setup-test-env.sh
39 - echo -e "\e[0Ksection_start:$(date +%s):unset_env_vars_section[collapsed=true]\r\e[0KUnsetting vulnerable environment variables"53 - echo -e "\e[0Ksection_start:$(date +%s):unset_env_vars_section[collapsed=true]\r\e[0KUnsetting vulnerable environment variables"
40 - export CI_JOB_JWT_FILE="${CI_JOB_JWT_FILE:-$(mktemp)}"54 - echo -n "${S3_JWT}" > "${S3_JWT_FILE}"
41 - echo -n "${CI_JOB_JWT}" > "${CI_JOB_JWT_FILE}"55 - unset CI_JOB_JWT S3_JWT
42 - unset CI_JOB_JWT
43 - echo -e "\e[0Ksection_end:$(date +%s):unset_env_vars_section\r\e[0K"56 - echo -e "\e[0Ksection_end:$(date +%s):unset_env_vars_section\r\e[0K"
44 57
45 - echo -e "\e[0Ksection_start:$(date +%s):drm_ci_download_section[collapsed=true]\r\e[0KDownloading mesa from $DRM_CI_PROJECT_URL/-/archive/$DRM_CI_COMMIT_SHA/mesa-$DRM_CI_COMMIT_SHA.tar.gz"58 - echo -e "\e[0Ksection_start:$(date +%s):drm_ci_download_section[collapsed=true]\r\e[0KDownloading mesa from $DRM_CI_PROJECT_URL/-/archive/$DRM_CI_COMMIT_SHA/mesa-$DRM_CI_COMMIT_SHA.tar.gz"
46 - cd $CI_PROJECT_DIR59 - cd $CI_PROJECT_DIR
47 - curl --output - $DRM_CI_PROJECT_URL/-/archive/$DRM_CI_COMMIT_SHA/mesa-$DRM_CI_COMMIT_SHA.tar.gz | tar -xz60 - curl --output - $DRM_CI_PROJECT_URL/-/archive/$DRM_CI_COMMIT_SHA/mesa-$DRM_CI_COMMIT_SHA.tar.gz | tar -xz
48 - mv mesa-$DRM_CI_COMMIT_SHA/.gitlab-ci* .61 - mv mesa-$DRM_CI_COMMIT_SHA/.gitlab-ci* .
62 - mv mesa-$DRM_CI_COMMIT_SHA/bin/ci .
49 - rm -rf mesa-$DRM_CI_COMMIT_SHA/63 - rm -rf mesa-$DRM_CI_COMMIT_SHA/
50 - echo -e "\e[0Ksection_end:$(date +%s):drm_ci_download_section\r\e[0K"64 - echo -e "\e[0Ksection_end:$(date +%s):drm_ci_download_section\r\e[0K"
51 65
@@ -53,9 +67,9 @@ default: · 1 unmodified line
53 - >67 - >
54 set +x68 set +x
55 69
56 test -e "${CI_JOB_JWT_FILE}" &&70 test -e "${S3_JWT_FILE}" &&
57 export CI_JOB_JWT="$(<${CI_JOB_JWT_FILE})" &&71 export S3_JWT="$(<${S3_JWT_FILE})" &&
58 rm "${CI_JOB_JWT_FILE}"72 rm "${S3_JWT_FILE}"
59 73
60include:74include:
61 - project: 'freedesktop/ci-templates'75 - project: 'freedesktop/ci-templates'
@@ -87,6 +101,7 @@ include: · 25 unmodified lines
87 - '/src/intel/ci/gitlab-ci-inc.yml'101 - '/src/intel/ci/gitlab-ci-inc.yml'
88 - '/src/freedreno/ci/gitlab-ci-inc.yml'102 - '/src/freedreno/ci/gitlab-ci-inc.yml'
89 - '/src/amd/ci/gitlab-ci-inc.yml'103 - '/src/amd/ci/gitlab-ci-inc.yml'
104 - '/src/virtio/ci/gitlab-ci-inc.yml'
90 - drivers/gpu/drm/ci/image-tags.yml105 - drivers/gpu/drm/ci/image-tags.yml
91 - drivers/gpu/drm/ci/container.yml106 - drivers/gpu/drm/ci/container.yml
92 - drivers/gpu/drm/ci/static-checks.yml107 - drivers/gpu/drm/ci/static-checks.yml
@@ -98,6 +113,7 @@ include: · 5 unmodified lines
98stages:113stages:
99 - sanity114 - sanity
100 - container115 - container
116 - code-validation
101 - git-archive117 - git-archive
102 - build118 - build
103 - amdgpu119 - amdgpu
@@ -107,7 +123,7 @@ stages: · 3 unmodified lines
107 - msm123 - msm
108 - rockchip124 - rockchip
109 - virtio-gpu125 - virtio-gpu
110 - lint126 - software-driver
111 127
112# YAML anchors for rule conditions128# YAML anchors for rule conditions
113# --------------------------------129# --------------------------------
@@ -218,14 +234,15 @@ make git archive: · 104 unmodified lines
218 script:234 script:
219 # Remove drm-ci files we just added235 # Remove drm-ci files we just added
220 - rm -rf .gitlab-ci.*236 - rm -rf .gitlab-ci.*
237 - rm -rf ci
221 238
222 # Compactify the .git directory239 # Compactify the .git directory
223 - git gc --aggressive240 - git gc --aggressive
224 # compress the current folder241 # compress the current folder
225 - tar -cvzf ../$CI_PROJECT_NAME.tar.gz .242 - tar -cvzf ../$CI_PROJECT_NAME.tar.gz .
226 243
227 # login with the JWT token file244 # Use id_tokens for JWT auth
228 - ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" ../$CI_PROJECT_NAME.tar.gz https://$S3_HOST/git-cache/$CI_PROJECT_NAMESPACE/$CI_PROJECT_NAME/$CI_PROJECT_NAME.tar.gz245 - ci-fairy s3cp --token-file "${S3_JWT_FILE}" ../$CI_PROJECT_NAME.tar.gz https://$S3_HOST/${S3_GITCACHE_BUCKET}/$CI_PROJECT_NAMESPACE/$CI_PROJECT_NAME/$CI_PROJECT_NAME.tar.gz
229 246
230 247
231# Sanity checks of MR settings and commit logs248# Sanity checks of MR settings and commit logs
@@ -262,4 +279,4 @@ sanity: · 30 unmodified lines
262 279
263# Jobs that need to pass before spending hardware resources on further testing280# Jobs that need to pass before spending hardware resources on further testing
264.required-for-hardware-jobs:281.required-for-hardware-jobs:
265 needs: []282 needs: []
drivers/gpu/drm/ci/igt_runner.sh+8−7
@@ -30,10 +30,10 @@ case "$DRIVER_NAME" in · 29 unmodified lines
30 export IGT_FORCE_DRIVER="panfrost"30 export IGT_FORCE_DRIVER="panfrost"
31 fi31 fi
32 ;;32 ;;
33 amdgpu)33 amdgpu|vkms)
34 # Cannot use HWCI_KERNEL_MODULES as at that point we don't have the module in /lib34 # Cannot use HWCI_KERNEL_MODULES as at that point we don't have the module in /lib
35 mv /install/modules/lib/modules/* /lib/modules/.35 mv /install/modules/lib/modules/* /lib/modules/. || true
36 modprobe amdgpu36 modprobe --first-time $DRIVER_NAME
37 ;;37 ;;
38esac38esac
39 39
@@ -59,25 +59,26 @@ fi · 19 unmodified lines
59 59
60curl -L --retry 4 -f --retry-all-errors --retry-delay 60 -s ${FDO_HTTP_CACHE_URI:-}$PIPELINE_ARTIFACTS_BASE/$ARCH/igt.tar.gz | tar --zstd -v -x -C /60curl -L --retry 4 -f --retry-all-errors --retry-delay 60 -s ${FDO_HTTP_CACHE_URI:-}$PIPELINE_ARTIFACTS_BASE/$ARCH/igt.tar.gz | tar --zstd -v -x -C /
61 61
62TESTLIST="/igt/libexec/igt-gpu-tools/ci-testlist.txt"
62 63
63# If the job is parallel at the gitab job level, take the corresponding fraction64# If the job is parallel at the gitab job level, take the corresponding fraction
64# of the caselist.65# of the caselist.
65if [ -n "$CI_NODE_INDEX" ]; then66if [ -n "$CI_NODE_INDEX" ]; then
66 sed -ni $CI_NODE_INDEX~$CI_NODE_TOTAL"p" /install/testlist.txt67 sed -ni $CI_NODE_INDEX~$CI_NODE_TOTAL"p" $TESTLIST
67fi68fi
68 69
69# core_getversion checks if the driver is loaded and probed correctly70# core_getversion checks if the driver is loaded and probed correctly
70# so run it in all shards71# so run it in all shards
71if ! grep -q "core_getversion" /install/testlist.txt; then72if ! grep -q "core_getversion" $TESTLIST; then
72 # Add the line to the file73 # Add the line to the file
73 echo "core_getversion" >> /install/testlist.txt74 echo "core_getversion" >> $TESTLIST
74fi75fi
75 76
76set +e77set +e
77igt-runner \78igt-runner \
78 run \79 run \
79 --igt-folder /igt/libexec/igt-gpu-tools \80 --igt-folder /igt/libexec/igt-gpu-tools \
80 --caselist /install/testlist.txt \81 --caselist $TESTLIST \
81 --output /results \82 --output /results \
82 $IGT_SKIPS \83 $IGT_SKIPS \
83 $IGT_FLAKES \84 $IGT_FLAKES \
drivers/gpu/drm/ci/image-tags.yml+2−2
@@ -1,10 +1,10 @@
1variables:1variables:
2 CONTAINER_TAG: "2023-10-11-mesa-uprev"2 CONTAINER_TAG: "2024-05-09-mesa-uprev"
3 DEBIAN_X86_64_BUILD_BASE_IMAGE: "debian/x86_64_build-base"3 DEBIAN_X86_64_BUILD_BASE_IMAGE: "debian/x86_64_build-base"
4 DEBIAN_BASE_TAG: "${CONTAINER_TAG}"4 DEBIAN_BASE_TAG: "${CONTAINER_TAG}"
5 5
6 DEBIAN_X86_64_BUILD_IMAGE_PATH: "debian/x86_64_build"6 DEBIAN_X86_64_BUILD_IMAGE_PATH: "debian/x86_64_build"
7 DEBIAN_BUILD_TAG: "2023-10-08-config"7 DEBIAN_BUILD_TAG: "2024-06-10-vkms"
8 8
9 KERNEL_ROOTFS_TAG: "2023-10-06-amd"9 KERNEL_ROOTFS_TAG: "2023-10-06-amd"
10 10
drivers/gpu/drm/ci/lava-submit.sh+2−2
@@ -27,7 +27,7 @@ KERNEL_IMAGE_BASE="https://${BASE_SYSTEM_HOST_PATH}" \ · 26 unmodified lines
27section_end variables27section_end variables
28 28
29tar zcf job-rootfs-overlay.tar.gz -C results/job-rootfs-overlay/ .29tar zcf job-rootfs-overlay.tar.gz -C results/job-rootfs-overlay/ .
30ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" job-rootfs-overlay.tar.gz "https://${JOB_ROOTFS_OVERLAY_PATH}"30ci-fairy s3cp --token-file "${S3_JWT_FILE}" job-rootfs-overlay.tar.gz "https://${JOB_ROOTFS_OVERLAY_PATH}"
31 31
32touch results/lava.log32touch results/lava.log
33tail -f results/lava.log &33tail -f results/lava.log &
@@ -45,7 +45,7 @@ PYTHONPATH=artifacts/ artifacts/lava/lava_job_submitter.py \ · 11 unmodified lines
45 --ci-project-dir "${CI_PROJECT_DIR}" \45 --ci-project-dir "${CI_PROJECT_DIR}" \
46 --device-type "${DEVICE_TYPE}" \46 --device-type "${DEVICE_TYPE}" \
47 --dtb-filename "${DTB}" \47 --dtb-filename "${DTB}" \
48 --jwt-file "${CI_JOB_JWT_FILE}" \48 --jwt-file "${S3_JWT_FILE}" \
49 --kernel-image-name "${KERNEL_IMAGE_NAME}" \49 --kernel-image-name "${KERNEL_IMAGE_NAME}" \
50 --kernel-image-type "${KERNEL_IMAGE_TYPE}" \50 --kernel-image-type "${KERNEL_IMAGE_TYPE}" \
51 --boot-method "${BOOT_METHOD}" \51 --boot-method "${BOOT_METHOD}" \
drivers/gpu/drm/ci/test.yml+33−8
@@ -24,6 +24,7 @@ · 23 unmodified lines
24 variables:24 variables:
25 HWCI_TEST_SCRIPT: "/install/igt_runner.sh"25 HWCI_TEST_SCRIPT: "/install/igt_runner.sh"
26 DEBIAN_ARCH: "armhf"26 DEBIAN_ARCH: "armhf"
27 FARM: collabora
27 dependencies:28 dependencies:
28 - testing:arm3229 - testing:arm32
29 needs:30 needs:
@@ -39,6 +40,7 @@ · 9 unmodified lines
39 variables:40 variables:
40 HWCI_TEST_SCRIPT: "/install/igt_runner.sh"41 HWCI_TEST_SCRIPT: "/install/igt_runner.sh"
41 DEBIAN_ARCH: "arm64"42 DEBIAN_ARCH: "arm64"
43 FARM: collabora
42 dependencies:44 dependencies:
43 - testing:arm6445 - testing:arm64
44 needs:46 needs:
@@ -54,6 +56,7 @@ · 9 unmodified lines
54 variables:56 variables:
55 HWCI_TEST_SCRIPT: "/install/igt_runner.sh"57 HWCI_TEST_SCRIPT: "/install/igt_runner.sh"
56 DEBIAN_ARCH: "amd64"58 DEBIAN_ARCH: "amd64"
59 FARM: collabora
57 dependencies:60 dependencies:
58 - testing:x86_6461 - testing:x86_64
59 needs:62 needs:
@@ -74,6 +77,7 @@ · 14 unmodified lines
74 S3_ARTIFACT_NAME: "arm64/kernel-files"77 S3_ARTIFACT_NAME: "arm64/kernel-files"
75 BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/Image.gz78 BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/Image.gz
76 BM_CMDLINE: "ip=dhcp console=ttyMSM0,115200n8 $BM_KERNEL_EXTRA_ARGS root=/dev/nfs rw nfsrootdebug nfsroot=,tcp,nfsvers=4.2 init=/init $BM_KERNELARGS"79 BM_CMDLINE: "ip=dhcp console=ttyMSM0,115200n8 $BM_KERNEL_EXTRA_ARGS root=/dev/nfs rw nfsrootdebug nfsroot=,tcp,nfsvers=4.2 init=/init $BM_KERNELARGS"
80 FARM: google
77 needs:81 needs:
78 - debian/arm64_test82 - debian/arm64_test
79 - job: testing:arm6483 - job: testing:arm64
@@ -116,8 +120,9 @@ msm:apq8016: · 36 unmodified lines
116 - .baremetal-igt-arm64120 - .baremetal-igt-arm64
117 stage: msm121 stage: msm
118 variables:122 variables:
123 DEVICE_TYPE: apq8016-sbc-usb-host
119 DRIVER_NAME: msm124 DRIVER_NAME: msm
120 BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/apq8016-sbc-usb-host.dtb125 BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/${DEVICE_TYPE}.dtb
121 GPU_VERSION: apq8016126 GPU_VERSION: apq8016
122 # disabling unused clocks congests with the MDSS runtime PM trying to127 # disabling unused clocks congests with the MDSS runtime PM trying to
123 # disable those clocks and causes boot to fail.128 # disable those clocks and causes boot to fail.
@@ -132,9 +137,10 @@ msm:apq8096: · 8 unmodified lines
132 - .baremetal-igt-arm64137 - .baremetal-igt-arm64
133 stage: msm138 stage: msm
134 variables:139 variables:
140 DEVICE_TYPE: apq8096-db820c
135 DRIVER_NAME: msm141 DRIVER_NAME: msm
136 BM_KERNEL_EXTRA_ARGS: maxcpus=2142 BM_KERNEL_EXTRA_ARGS: maxcpus=2
137 BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/apq8096-db820c.dtb143 BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/${DEVICE_TYPE}.dtb
138 GPU_VERSION: apq8096144 GPU_VERSION: apq8096
139 RUNNER_TAG: google-freedreno-db820c145 RUNNER_TAG: google-freedreno-db820c
140 script:146 script:
@@ -146,6 +152,7 @@ msm:sdm845: · 5 unmodified lines
146 stage: msm152 stage: msm
147 parallel: 6153 parallel: 6
148 variables:154 variables:
155 DEVICE_TYPE: sdm845-cheza-r3
149 DRIVER_NAME: msm156 DRIVER_NAME: msm
150 BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/cheza-kernel157 BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/cheza-kernel
151 GPU_VERSION: sdm845158 GPU_VERSION: sdm845
@@ -184,6 +191,7 @@ rockchip:rk3399: · 32 unmodified lines
184 extends:191 extends:
185 - .lava-igt:x86_64192 - .lava-igt:x86_64
186 stage: i915193 stage: i915
194 timeout: "1h30m"
187 variables:195 variables:
188 DRIVER_NAME: i915196 DRIVER_NAME: i915
189 DTB: ""197 DTB: ""
@@ -194,7 +202,6 @@ i915:apl: · 4 unmodified lines
194 extends:202 extends:
195 - .i915203 - .i915
196 parallel: 3204 parallel: 3
197 timeout: "1h30m"
198 variables:205 variables:
199 DEVICE_TYPE: asus-C523NA-A20057-coral206 DEVICE_TYPE: asus-C523NA-A20057-coral
200 GPU_VERSION: apl207 GPU_VERSION: apl
@@ -204,7 +211,6 @@ i915:glk: · 3 unmodified lines
204 extends:211 extends:
205 - .i915212 - .i915
206 parallel: 2213 parallel: 2
207 timeout: "1h30m"
208 variables:214 variables:
209 DEVICE_TYPE: hp-x360-12b-ca0010nr-n4020-octopus215 DEVICE_TYPE: hp-x360-12b-ca0010nr-n4020-octopus
210 GPU_VERSION: glk216 GPU_VERSION: glk
@@ -214,7 +220,6 @@ i915:amly: · 3 unmodified lines
214 extends:220 extends:
215 - .i915221 - .i915
216 parallel: 2222 parallel: 2
217 timeout: "1h30m"
218 variables:223 variables:
219 DEVICE_TYPE: asus-C433TA-AJ0005-rammus224 DEVICE_TYPE: asus-C433TA-AJ0005-rammus
220 GPU_VERSION: amly225 GPU_VERSION: amly
@@ -233,7 +238,6 @@ i915:whl: · 12 unmodified lines
233 extends:238 extends:
234 - .i915239 - .i915
235 parallel: 2240 parallel: 2
236 timeout: "1h30m"
237 variables:241 variables:
238 DEVICE_TYPE: dell-latitude-5400-8665U-sarien242 DEVICE_TYPE: dell-latitude-5400-8665U-sarien
239 GPU_VERSION: whl243 GPU_VERSION: whl
@@ -243,7 +247,6 @@ i915:cml: · 3 unmodified lines
243 extends:247 extends:
244 - .i915248 - .i915
245 parallel: 2249 parallel: 2
246 timeout: "1h30m"
247 variables:250 variables:
248 DEVICE_TYPE: asus-C436FA-Flip-hatch251 DEVICE_TYPE: asus-C436FA-Flip-hatch
249 GPU_VERSION: cml252 GPU_VERSION: cml
@@ -335,7 +338,7 @@ meson:g12b: · 85 unmodified lines
335 RUNNER_TAG: mesa-ci-x86-64-lava-meson-g12b-a311d-khadas-vim3338 RUNNER_TAG: mesa-ci-x86-64-lava-meson-g12b-a311d-khadas-vim3
336 339
337virtio_gpu:none:340virtio_gpu:none:
338 stage: virtio-gpu341 stage: software-driver
339 variables:342 variables:
340 CROSVM_GALLIUM_DRIVER: llvmpipe343 CROSVM_GALLIUM_DRIVER: llvmpipe
341 DRIVER_NAME: virtio_gpu344 DRIVER_NAME: virtio_gpu
@@ -355,3 +358,25 @@ virtio_gpu:none: · 13 unmodified lines
355 - debian/x86_64_test-gl358 - debian/x86_64_test-gl
356 - testing:x86_64359 - testing:x86_64
357 - igt:x86_64360 - igt:x86_64
361
362vkms:none:
363 stage: software-driver
364 variables:
365 DRIVER_NAME: vkms
366 GPU_VERSION: none
367 extends:
368 - .test-gl
369 - .test-rules
370 tags:
371 - kvm
372 script:
373 - ln -sf $CI_PROJECT_DIR/install /install
374 - mv install/bzImage /lava-files/bzImage
375 - mkdir -p /lib/modules
376 - mkdir -p $CI_PROJECT_DIR/results
377 - ln -sf $CI_PROJECT_DIR/results /results
378 - ./install/crosvm-runner.sh ./install/igt_runner.sh
379 needs:
380 - debian/x86_64_test-gl
381 - testing:x86_64
382 - igt:x86_64
drivers/gpu/drm/ci/testlist.txt+0−2761
@@ -1,2761 +0,0 @@
1core_auth@getclient-simple
2core_auth@getclient-master-drop
3core_auth@basic-auth
4core_auth@many-magics
5core_getclient
6core_getstats
7core_getversion
8core_setmaster_vs_auth
9drm_read@invalid-buffer
10drm_read@fault-buffer
11drm_read@empty-block
12drm_read@empty-nonblock
13drm_read@short-buffer-block
14drm_read@short-buffer-nonblock
15drm_read@short-buffer-wakeup
16gem_eio@throttle
17gem_eio@create
18gem_eio@create-ext
19gem_eio@context-create
20gem_eio@execbuf
21gem_eio@banned
22gem_eio@suspend
23gem_eio@hibernate
24gem_eio@in-flight-external
25gem_eio@in-flight-suspend
26gem_eio@reset-stress
27gem_eio@unwedge-stress
28gem_eio@wait-immediate
29gem_eio@wait-wedge-immediate
30gem_eio@in-flight-immediate
31gem_eio@in-flight-contexts-immediate
32gem_eio@in-flight-internal-immediate
33gem_eio@wait-1us
34gem_eio@wait-wedge-1us
35gem_eio@in-flight-1us
36gem_eio@in-flight-contexts-1us
37gem_eio@in-flight-internal-1us
38gem_eio@wait-10ms
39gem_eio@wait-wedge-10ms
40gem_eio@in-flight-10ms
41gem_eio@in-flight-contexts-10ms
42gem_eio@in-flight-internal-10ms
43gem_eio@kms
44kms_3d
45kms_addfb_basic@unused-handle
46kms_addfb_basic@unused-pitches
47kms_addfb_basic@unused-offsets
48kms_addfb_basic@unused-modifier
49kms_addfb_basic@clobberred-modifier
50kms_addfb_basic@invalid-smem-bo-on-discrete
51kms_addfb_basic@legacy-format
52kms_addfb_basic@no-handle
53kms_addfb_basic@basic
54kms_addfb_basic@bad-pitch-0
55kms_addfb_basic@bad-pitch-32
56kms_addfb_basic@bad-pitch-63
57kms_addfb_basic@bad-pitch-128
58kms_addfb_basic@bad-pitch-256
59kms_addfb_basic@bad-pitch-1024
60kms_addfb_basic@bad-pitch-999
61kms_addfb_basic@bad-pitch-65536
62kms_addfb_basic@invalid-get-prop-any
63kms_addfb_basic@invalid-get-prop
64kms_addfb_basic@invalid-set-prop-any
65kms_addfb_basic@invalid-set-prop
66kms_addfb_basic@master-rmfb
67kms_addfb_basic@addfb25-modifier-no-flag
68kms_addfb_basic@addfb25-bad-modifier
69kms_addfb_basic@addfb25-x-tiled-mismatch-legacy
70kms_addfb_basic@addfb25-x-tiled-legacy
71kms_addfb_basic@addfb25-framebuffer-vs-set-tiling
72kms_addfb_basic@basic-x-tiled-legacy
73kms_addfb_basic@framebuffer-vs-set-tiling
74kms_addfb_basic@tile-pitch-mismatch
75kms_addfb_basic@basic-y-tiled-legacy
76kms_addfb_basic@size-max
77kms_addfb_basic@too-wide
78kms_addfb_basic@too-high
79kms_addfb_basic@bo-too-small
80kms_addfb_basic@small-bo
81kms_addfb_basic@bo-too-small-due-to-tiling
82kms_addfb_basic@addfb25-y-tiled-legacy
83kms_addfb_basic@addfb25-yf-tiled-legacy
84kms_addfb_basic@addfb25-y-tiled-small-legacy
85kms_addfb_basic@addfb25-4-tiled
86kms_async_flips@async-flip-with-page-flip-events
87kms_async_flips@alternate-sync-async-flip
88kms_async_flips@test-time-stamp
89kms_async_flips@test-cursor
90kms_async_flips@invalid-async-flip
91kms_async_flips@crc
92kms_atomic@plane-overlay-legacy
93kms_atomic@plane-primary-legacy
94kms_atomic@plane-primary-overlay-mutable-zpos
95kms_atomic@plane-immutable-zpos
96kms_atomic@test-only
97kms_atomic@plane-cursor-legacy
98kms_atomic@plane-invalid-params
99kms_atomic@plane-invalid-params-fence
100kms_atomic@crtc-invalid-params
101kms_atomic@crtc-invalid-params-fence
102kms_atomic@atomic-invalid-params
103kms_atomic@atomic-plane-damage
104kms_atomic_interruptible@legacy-setmode
105kms_atomic_interruptible@atomic-setmode
106kms_atomic_interruptible@legacy-dpms
107kms_atomic_interruptible@legacy-pageflip
108kms_atomic_interruptible@legacy-cursor
109kms_atomic_interruptible@universal-setplane-primary
110kms_atomic_interruptible@universal-setplane-cursor
111kms_atomic_transition@plane-primary-toggle-with-vblank-wait
112kms_atomic_transition@plane-all-transition
113kms_atomic_transition@plane-all-transition-fencing
114kms_atomic_transition@plane-all-transition-nonblocking
115kms_atomic_transition@plane-all-transition-nonblocking-fencing
116kms_atomic_transition@plane-use-after-nonblocking-unbind
117kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing
118kms_atomic_transition@plane-all-modeset-transition
119kms_atomic_transition@plane-all-modeset-transition-fencing
120kms_atomic_transition@plane-all-modeset-transition-internal-panels
121kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels
122kms_atomic_transition@plane-toggle-modeset-transition
123kms_atomic_transition@modeset-transition
124kms_atomic_transition@modeset-transition-fencing
125kms_atomic_transition@modeset-transition-nonblocking
126kms_atomic_transition@modeset-transition-nonblocking-fencing
127kms_big_fb@x-tiled-addfb-size-overflow
128kms_big_fb@y-tiled-addfb-size-overflow
129kms_big_fb@yf-tiled-addfb-size-overflow
130kms_big_fb@4-tiled-addfb-size-overflow
131kms_big_fb@x-tiled-addfb-size-offset-overflow
132kms_big_fb@y-tiled-addfb-size-offset-overflow
133kms_big_fb@yf-tiled-addfb-size-offset-overflow
134kms_big_fb@4-tiled-addfb-size-offset-overflow
135kms_big_fb@linear-addfb
136kms_big_fb@x-tiled-addfb
137kms_big_fb@y-tiled-addfb
138kms_big_fb@yf-tiled-addfb
139kms_big_fb@4-tiled-addfb
140kms_big_fb@linear-8bpp-rotate-0
141kms_big_fb@linear-8bpp-rotate-90
142kms_big_fb@linear-8bpp-rotate-180
143kms_big_fb@linear-8bpp-rotate-270
144kms_big_fb@linear-16bpp-rotate-0
145kms_big_fb@linear-16bpp-rotate-90
146kms_big_fb@linear-16bpp-rotate-180
147kms_big_fb@linear-16bpp-rotate-270
148kms_big_fb@linear-32bpp-rotate-0
149kms_big_fb@linear-32bpp-rotate-90
150kms_big_fb@linear-32bpp-rotate-180
151kms_big_fb@linear-32bpp-rotate-270
152kms_big_fb@linear-64bpp-rotate-0
153kms_big_fb@linear-64bpp-rotate-90
154kms_big_fb@linear-64bpp-rotate-180
155kms_big_fb@linear-64bpp-rotate-270
156kms_big_fb@x-tiled-8bpp-rotate-0
157kms_big_fb@x-tiled-8bpp-rotate-90
158kms_big_fb@x-tiled-8bpp-rotate-180
159kms_big_fb@x-tiled-8bpp-rotate-270
160kms_big_fb@x-tiled-16bpp-rotate-0
161kms_big_fb@x-tiled-16bpp-rotate-90
162kms_big_fb@x-tiled-16bpp-rotate-180
163kms_big_fb@x-tiled-16bpp-rotate-270
164kms_big_fb@x-tiled-32bpp-rotate-0
165kms_big_fb@x-tiled-32bpp-rotate-90
166kms_big_fb@x-tiled-32bpp-rotate-180
167kms_big_fb@x-tiled-32bpp-rotate-270
168kms_big_fb@x-tiled-64bpp-rotate-0
169kms_big_fb@x-tiled-64bpp-rotate-90
170kms_big_fb@x-tiled-64bpp-rotate-180
171kms_big_fb@x-tiled-64bpp-rotate-270
172kms_big_fb@y-tiled-8bpp-rotate-0
173kms_big_fb@y-tiled-8bpp-rotate-90
174kms_big_fb@y-tiled-8bpp-rotate-180
175kms_big_fb@y-tiled-8bpp-rotate-270
176kms_big_fb@y-tiled-16bpp-rotate-0
177kms_big_fb@y-tiled-16bpp-rotate-90
178kms_big_fb@y-tiled-16bpp-rotate-180
179kms_big_fb@y-tiled-16bpp-rotate-270
180kms_big_fb@y-tiled-32bpp-rotate-0
181kms_big_fb@y-tiled-32bpp-rotate-90
182kms_big_fb@y-tiled-32bpp-rotate-180
183kms_big_fb@y-tiled-32bpp-rotate-270
184kms_big_fb@y-tiled-64bpp-rotate-0
185kms_big_fb@y-tiled-64bpp-rotate-90
186kms_big_fb@y-tiled-64bpp-rotate-180
187kms_big_fb@y-tiled-64bpp-rotate-270
188kms_big_fb@yf-tiled-8bpp-rotate-0
189kms_big_fb@yf-tiled-8bpp-rotate-90
190kms_big_fb@yf-tiled-8bpp-rotate-180
191kms_big_fb@yf-tiled-8bpp-rotate-270
192kms_big_fb@yf-tiled-16bpp-rotate-0
193kms_big_fb@yf-tiled-16bpp-rotate-90
194kms_big_fb@yf-tiled-16bpp-rotate-180
195kms_big_fb@yf-tiled-16bpp-rotate-270
196kms_big_fb@yf-tiled-32bpp-rotate-0
197kms_big_fb@yf-tiled-32bpp-rotate-90
198kms_big_fb@yf-tiled-32bpp-rotate-180
199kms_big_fb@yf-tiled-32bpp-rotate-270
200kms_big_fb@yf-tiled-64bpp-rotate-0
201kms_big_fb@yf-tiled-64bpp-rotate-90
202kms_big_fb@yf-tiled-64bpp-rotate-180
203kms_big_fb@yf-tiled-64bpp-rotate-270
204kms_big_fb@4-tiled-8bpp-rotate-0
205kms_big_fb@4-tiled-8bpp-rotate-90
206kms_big_fb@4-tiled-8bpp-rotate-180
207kms_big_fb@4-tiled-8bpp-rotate-270
208kms_big_fb@4-tiled-16bpp-rotate-0
209kms_big_fb@4-tiled-16bpp-rotate-90
210kms_big_fb@4-tiled-16bpp-rotate-180
211kms_big_fb@4-tiled-16bpp-rotate-270
212kms_big_fb@4-tiled-32bpp-rotate-0
213kms_big_fb@4-tiled-32bpp-rotate-90
214kms_big_fb@4-tiled-32bpp-rotate-180
215kms_big_fb@4-tiled-32bpp-rotate-270
216kms_big_fb@4-tiled-64bpp-rotate-0
217kms_big_fb@4-tiled-64bpp-rotate-90
218kms_big_fb@4-tiled-64bpp-rotate-180
219kms_big_fb@4-tiled-64bpp-rotate-270
220kms_big_fb@linear-max-hw-stride-32bpp-rotate-0
221kms_big_fb@linear-max-hw-stride-32bpp-rotate-180
222kms_big_fb@linear-max-hw-stride-64bpp-rotate-0
223kms_big_fb@linear-max-hw-stride-64bpp-rotate-180
224kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0
225kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip
226kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180
227kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip
228kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0
229kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip
230kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180
231kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip
232kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip
233kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip
234kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip
235kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip
236kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip
237kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip
238kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip
239kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip
240kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0
241kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip
242kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180
243kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip
244kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0
245kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip
246kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180
247kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip
248kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip
249kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip
250kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip
251kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip
252kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip
253kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip
254kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip
255kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip
256kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0
257kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip
258kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180
259kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip
260kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0
261kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip
262kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180
263kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip
264kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip
265kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip
266kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip
267kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip
268kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip
269kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip
270kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip
271kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip
272kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0
273kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip
274kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180
275kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip
276kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0
277kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip
278kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180
279kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip
280kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip
281kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip
282kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip
283kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip
284kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip
285kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip
286kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip
287kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip
288kms_big_joiner@basic
289kms_big_joiner@invalid-modeset
290kms_big_joiner@2x-modeset
291kms_busy@basic
292kms_busy@basic-hang
293kms_busy@extended-pageflip-modeset-hang-oldfb
294kms_busy@extended-pageflip-hang-oldfb
295kms_busy@extended-pageflip-hang-newfb
296kms_busy@extended-modeset-hang-oldfb
297kms_busy@extended-modeset-hang-newfb
298kms_busy@extended-modeset-hang-oldfb-with-reset
299kms_busy@extended-modeset-hang-newfb-with-reset
300kms_bw@linear-tiling-1-displays-1920x1080p
301kms_bw@linear-tiling-1-displays-2560x1440p
302kms_bw@linear-tiling-1-displays-3840x2160p
303kms_bw@linear-tiling-2-displays-1920x1080p
304kms_bw@linear-tiling-2-displays-2560x1440p
305kms_bw@linear-tiling-2-displays-3840x2160p
306kms_bw@linear-tiling-3-displays-1920x1080p
307kms_bw@linear-tiling-3-displays-2560x1440p
308kms_bw@linear-tiling-3-displays-3840x2160p
309kms_bw@linear-tiling-4-displays-1920x1080p
310kms_bw@linear-tiling-4-displays-2560x1440p
311kms_bw@linear-tiling-4-displays-3840x2160p
312kms_bw@linear-tiling-5-displays-1920x1080p
313kms_bw@linear-tiling-5-displays-2560x1440p
314kms_bw@linear-tiling-5-displays-3840x2160p
315kms_bw@linear-tiling-6-displays-1920x1080p
316kms_bw@linear-tiling-6-displays-2560x1440p
317kms_bw@linear-tiling-6-displays-3840x2160p
318kms_bw@linear-tiling-7-displays-1920x1080p
319kms_bw@linear-tiling-7-displays-2560x1440p
320kms_bw@linear-tiling-7-displays-3840x2160p
321kms_bw@linear-tiling-8-displays-1920x1080p
322kms_bw@linear-tiling-8-displays-2560x1440p
323kms_bw@linear-tiling-8-displays-3840x2160p
324kms_ccs@pipe-A-bad-pixel-format-y-tiled-ccs
325kms_ccs@pipe-A-bad-pixel-format-yf-tiled-ccs
326kms_ccs@pipe-A-bad-pixel-format-y-tiled-gen12-rc-ccs
327kms_ccs@pipe-A-bad-pixel-format-y-tiled-gen12-rc-ccs-cc
328kms_ccs@pipe-A-bad-pixel-format-y-tiled-gen12-mc-ccs
329kms_ccs@pipe-A-bad-pixel-format-4-tiled-dg2-rc-ccs
330kms_ccs@pipe-A-bad-pixel-format-4-tiled-dg2-mc-ccs
331kms_ccs@pipe-A-bad-pixel-format-4-tiled-dg2-rc-ccs-cc
332kms_ccs@pipe-A-bad-pixel-format-4-tiled-mtl-rc-ccs
333kms_ccs@pipe-A-bad-pixel-format-4-tiled-mtl-mc-ccs
334kms_ccs@pipe-A-bad-pixel-format-4-tiled-mtl-rc-ccs-cc
335kms_ccs@pipe-A-bad-rotation-90-y-tiled-ccs
336kms_ccs@pipe-A-bad-rotation-90-yf-tiled-ccs
337kms_ccs@pipe-A-bad-rotation-90-y-tiled-gen12-rc-ccs
338kms_ccs@pipe-A-bad-rotation-90-y-tiled-gen12-rc-ccs-cc
339kms_ccs@pipe-A-bad-rotation-90-y-tiled-gen12-mc-ccs
340kms_ccs@pipe-A-bad-rotation-90-4-tiled-dg2-rc-ccs
341kms_ccs@pipe-A-bad-rotation-90-4-tiled-dg2-mc-ccs
342kms_ccs@pipe-A-bad-rotation-90-4-tiled-dg2-rc-ccs-cc
343kms_ccs@pipe-A-bad-rotation-90-4-tiled-mtl-rc-ccs
344kms_ccs@pipe-A-bad-rotation-90-4-tiled-mtl-mc-ccs
345kms_ccs@pipe-A-bad-rotation-90-4-tiled-mtl-rc-ccs-cc
346kms_ccs@pipe-A-crc-primary-basic-y-tiled-ccs
347kms_ccs@pipe-A-crc-primary-basic-yf-tiled-ccs
348kms_ccs@pipe-A-crc-primary-basic-y-tiled-gen12-rc-ccs
349kms_ccs@pipe-A-crc-primary-basic-y-tiled-gen12-rc-ccs-cc
350kms_ccs@pipe-A-crc-primary-basic-y-tiled-gen12-mc-ccs
351kms_ccs@pipe-A-crc-primary-basic-4-tiled-dg2-rc-ccs
352kms_ccs@pipe-A-crc-primary-basic-4-tiled-dg2-mc-ccs
353kms_ccs@pipe-A-crc-primary-basic-4-tiled-dg2-rc-ccs-cc
354kms_ccs@pipe-A-crc-primary-basic-4-tiled-mtl-rc-ccs
355kms_ccs@pipe-A-crc-primary-basic-4-tiled-mtl-mc-ccs
356kms_ccs@pipe-A-crc-primary-basic-4-tiled-mtl-rc-ccs-cc
357kms_ccs@pipe-A-crc-primary-rotation-180-y-tiled-ccs
358kms_ccs@pipe-A-crc-primary-rotation-180-yf-tiled-ccs
359kms_ccs@pipe-A-crc-primary-rotation-180-y-tiled-gen12-rc-ccs
360kms_ccs@pipe-A-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc
361kms_ccs@pipe-A-crc-primary-rotation-180-y-tiled-gen12-mc-ccs
362kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-dg2-rc-ccs
363kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-dg2-mc-ccs
364kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc
365kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-mtl-rc-ccs
366kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-mtl-mc-ccs
367kms_ccs@pipe-A-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc
368kms_ccs@pipe-A-random-ccs-data-y-tiled-ccs
369kms_ccs@pipe-A-random-ccs-data-yf-tiled-ccs
370kms_ccs@pipe-A-random-ccs-data-y-tiled-gen12-rc-ccs
371kms_ccs@pipe-A-random-ccs-data-y-tiled-gen12-rc-ccs-cc
372kms_ccs@pipe-A-random-ccs-data-y-tiled-gen12-mc-ccs
373kms_ccs@pipe-A-random-ccs-data-4-tiled-dg2-rc-ccs
374kms_ccs@pipe-A-random-ccs-data-4-tiled-dg2-mc-ccs
375kms_ccs@pipe-A-random-ccs-data-4-tiled-dg2-rc-ccs-cc
376kms_ccs@pipe-A-random-ccs-data-4-tiled-mtl-rc-ccs
377kms_ccs@pipe-A-random-ccs-data-4-tiled-mtl-mc-ccs
378kms_ccs@pipe-A-random-ccs-data-4-tiled-mtl-rc-ccs-cc
379kms_ccs@pipe-A-missing-ccs-buffer-y-tiled-ccs
380kms_ccs@pipe-A-missing-ccs-buffer-yf-tiled-ccs
381kms_ccs@pipe-A-missing-ccs-buffer-y-tiled-gen12-rc-ccs
382kms_ccs@pipe-A-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc
383kms_ccs@pipe-A-missing-ccs-buffer-y-tiled-gen12-mc-ccs
384kms_ccs@pipe-A-missing-ccs-buffer-4-tiled-mtl-rc-ccs
385kms_ccs@pipe-A-missing-ccs-buffer-4-tiled-mtl-mc-ccs
386kms_ccs@pipe-A-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc
387kms_ccs@pipe-A-ccs-on-another-bo-y-tiled-ccs
388kms_ccs@pipe-A-ccs-on-another-bo-yf-tiled-ccs
389kms_ccs@pipe-A-ccs-on-another-bo-y-tiled-gen12-rc-ccs
390kms_ccs@pipe-A-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc
391kms_ccs@pipe-A-ccs-on-another-bo-y-tiled-gen12-mc-ccs
392kms_ccs@pipe-A-ccs-on-another-bo-4-tiled-mtl-rc-ccs
393kms_ccs@pipe-A-ccs-on-another-bo-4-tiled-mtl-mc-ccs
394kms_ccs@pipe-A-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc
395kms_ccs@pipe-A-bad-aux-stride-y-tiled-ccs
396kms_ccs@pipe-A-bad-aux-stride-yf-tiled-ccs
397kms_ccs@pipe-A-bad-aux-stride-y-tiled-gen12-rc-ccs
398kms_ccs@pipe-A-bad-aux-stride-y-tiled-gen12-rc-ccs-cc
399kms_ccs@pipe-A-bad-aux-stride-y-tiled-gen12-mc-ccs
400kms_ccs@pipe-A-bad-aux-stride-4-tiled-mtl-rc-ccs
401kms_ccs@pipe-A-bad-aux-stride-4-tiled-mtl-mc-ccs
402kms_ccs@pipe-A-bad-aux-stride-4-tiled-mtl-rc-ccs-cc
403kms_ccs@pipe-A-crc-sprite-planes-basic-y-tiled-ccs
404kms_ccs@pipe-A-crc-sprite-planes-basic-yf-tiled-ccs
405kms_ccs@pipe-A-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs
406kms_ccs@pipe-A-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc
407kms_ccs@pipe-A-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs
408kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs
409kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs
410kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc
411kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs
412kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs
413kms_ccs@pipe-A-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc
414kms_ccs@pipe-B-bad-pixel-format-y-tiled-ccs
415kms_ccs@pipe-B-bad-pixel-format-yf-tiled-ccs
416kms_ccs@pipe-B-bad-pixel-format-y-tiled-gen12-rc-ccs
417kms_ccs@pipe-B-bad-pixel-format-y-tiled-gen12-rc-ccs-cc
418kms_ccs@pipe-B-bad-pixel-format-y-tiled-gen12-mc-ccs
419kms_ccs@pipe-B-bad-pixel-format-4-tiled-dg2-rc-ccs
420kms_ccs@pipe-B-bad-pixel-format-4-tiled-dg2-mc-ccs
421kms_ccs@pipe-B-bad-pixel-format-4-tiled-dg2-rc-ccs-cc
422kms_ccs@pipe-B-bad-pixel-format-4-tiled-mtl-rc-ccs
423kms_ccs@pipe-B-bad-pixel-format-4-tiled-mtl-mc-ccs
424kms_ccs@pipe-B-bad-pixel-format-4-tiled-mtl-rc-ccs-cc
425kms_ccs@pipe-B-bad-rotation-90-y-tiled-ccs
426kms_ccs@pipe-B-bad-rotation-90-yf-tiled-ccs
427kms_ccs@pipe-B-bad-rotation-90-y-tiled-gen12-rc-ccs
428kms_ccs@pipe-B-bad-rotation-90-y-tiled-gen12-rc-ccs-cc
429kms_ccs@pipe-B-bad-rotation-90-y-tiled-gen12-mc-ccs
430kms_ccs@pipe-B-bad-rotation-90-4-tiled-dg2-rc-ccs
431kms_ccs@pipe-B-bad-rotation-90-4-tiled-dg2-mc-ccs
432kms_ccs@pipe-B-bad-rotation-90-4-tiled-dg2-rc-ccs-cc
433kms_ccs@pipe-B-bad-rotation-90-4-tiled-mtl-rc-ccs
434kms_ccs@pipe-B-bad-rotation-90-4-tiled-mtl-mc-ccs
435kms_ccs@pipe-B-bad-rotation-90-4-tiled-mtl-rc-ccs-cc
436kms_ccs@pipe-B-crc-primary-basic-y-tiled-ccs
437kms_ccs@pipe-B-crc-primary-basic-yf-tiled-ccs
438kms_ccs@pipe-B-crc-primary-basic-y-tiled-gen12-rc-ccs
439kms_ccs@pipe-B-crc-primary-basic-y-tiled-gen12-rc-ccs-cc
440kms_ccs@pipe-B-crc-primary-basic-y-tiled-gen12-mc-ccs
441kms_ccs@pipe-B-crc-primary-basic-4-tiled-dg2-rc-ccs
442kms_ccs@pipe-B-crc-primary-basic-4-tiled-dg2-mc-ccs
443kms_ccs@pipe-B-crc-primary-basic-4-tiled-dg2-rc-ccs-cc
444kms_ccs@pipe-B-crc-primary-basic-4-tiled-mtl-rc-ccs
445kms_ccs@pipe-B-crc-primary-basic-4-tiled-mtl-mc-ccs
446kms_ccs@pipe-B-crc-primary-basic-4-tiled-mtl-rc-ccs-cc
447kms_ccs@pipe-B-crc-primary-rotation-180-y-tiled-ccs
448kms_ccs@pipe-B-crc-primary-rotation-180-yf-tiled-ccs
449kms_ccs@pipe-B-crc-primary-rotation-180-y-tiled-gen12-rc-ccs
450kms_ccs@pipe-B-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc
451kms_ccs@pipe-B-crc-primary-rotation-180-y-tiled-gen12-mc-ccs
452kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-dg2-rc-ccs
453kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-dg2-mc-ccs
454kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc
455kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-mtl-rc-ccs
456kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-mtl-mc-ccs
457kms_ccs@pipe-B-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc
458kms_ccs@pipe-B-random-ccs-data-y-tiled-ccs
459kms_ccs@pipe-B-random-ccs-data-yf-tiled-ccs
460kms_ccs@pipe-B-random-ccs-data-y-tiled-gen12-rc-ccs
461kms_ccs@pipe-B-random-ccs-data-y-tiled-gen12-rc-ccs-cc
462kms_ccs@pipe-B-random-ccs-data-y-tiled-gen12-mc-ccs
463kms_ccs@pipe-B-random-ccs-data-4-tiled-dg2-rc-ccs
464kms_ccs@pipe-B-random-ccs-data-4-tiled-dg2-mc-ccs
465kms_ccs@pipe-B-random-ccs-data-4-tiled-dg2-rc-ccs-cc
466kms_ccs@pipe-B-random-ccs-data-4-tiled-mtl-rc-ccs
467kms_ccs@pipe-B-random-ccs-data-4-tiled-mtl-mc-ccs
468kms_ccs@pipe-B-random-ccs-data-4-tiled-mtl-rc-ccs-cc
469kms_ccs@pipe-B-missing-ccs-buffer-y-tiled-ccs
470kms_ccs@pipe-B-missing-ccs-buffer-yf-tiled-ccs
471kms_ccs@pipe-B-missing-ccs-buffer-y-tiled-gen12-rc-ccs
472kms_ccs@pipe-B-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc
473kms_ccs@pipe-B-missing-ccs-buffer-y-tiled-gen12-mc-ccs
474kms_ccs@pipe-B-missing-ccs-buffer-4-tiled-mtl-rc-ccs
475kms_ccs@pipe-B-missing-ccs-buffer-4-tiled-mtl-mc-ccs
476kms_ccs@pipe-B-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc
477kms_ccs@pipe-B-ccs-on-another-bo-y-tiled-ccs
478kms_ccs@pipe-B-ccs-on-another-bo-yf-tiled-ccs
479kms_ccs@pipe-B-ccs-on-another-bo-y-tiled-gen12-rc-ccs
480kms_ccs@pipe-B-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc
481kms_ccs@pipe-B-ccs-on-another-bo-y-tiled-gen12-mc-ccs
482kms_ccs@pipe-B-ccs-on-another-bo-4-tiled-mtl-rc-ccs
483kms_ccs@pipe-B-ccs-on-another-bo-4-tiled-mtl-mc-ccs
484kms_ccs@pipe-B-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc
485kms_ccs@pipe-B-bad-aux-stride-y-tiled-ccs
486kms_ccs@pipe-B-bad-aux-stride-yf-tiled-ccs
487kms_ccs@pipe-B-bad-aux-stride-y-tiled-gen12-rc-ccs
488kms_ccs@pipe-B-bad-aux-stride-y-tiled-gen12-rc-ccs-cc
489kms_ccs@pipe-B-bad-aux-stride-y-tiled-gen12-mc-ccs
490kms_ccs@pipe-B-bad-aux-stride-4-tiled-mtl-rc-ccs
491kms_ccs@pipe-B-bad-aux-stride-4-tiled-mtl-mc-ccs
492kms_ccs@pipe-B-bad-aux-stride-4-tiled-mtl-rc-ccs-cc
493kms_ccs@pipe-B-crc-sprite-planes-basic-y-tiled-ccs
494kms_ccs@pipe-B-crc-sprite-planes-basic-yf-tiled-ccs
495kms_ccs@pipe-B-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs
496kms_ccs@pipe-B-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc
497kms_ccs@pipe-B-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs
498kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs
499kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs
500kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc
501kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs
502kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs
503kms_ccs@pipe-B-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc
504kms_ccs@pipe-C-bad-pixel-format-y-tiled-ccs
505kms_ccs@pipe-C-bad-pixel-format-yf-tiled-ccs
506kms_ccs@pipe-C-bad-pixel-format-y-tiled-gen12-rc-ccs
507kms_ccs@pipe-C-bad-pixel-format-y-tiled-gen12-rc-ccs-cc
508kms_ccs@pipe-C-bad-pixel-format-y-tiled-gen12-mc-ccs
509kms_ccs@pipe-C-bad-pixel-format-4-tiled-dg2-rc-ccs
510kms_ccs@pipe-C-bad-pixel-format-4-tiled-dg2-mc-ccs
511kms_ccs@pipe-C-bad-pixel-format-4-tiled-dg2-rc-ccs-cc
512kms_ccs@pipe-C-bad-pixel-format-4-tiled-mtl-rc-ccs
513kms_ccs@pipe-C-bad-pixel-format-4-tiled-mtl-mc-ccs
514kms_ccs@pipe-C-bad-pixel-format-4-tiled-mtl-rc-ccs-cc
515kms_ccs@pipe-C-bad-rotation-90-y-tiled-ccs
516kms_ccs@pipe-C-bad-rotation-90-yf-tiled-ccs
517kms_ccs@pipe-C-bad-rotation-90-y-tiled-gen12-rc-ccs
518kms_ccs@pipe-C-bad-rotation-90-y-tiled-gen12-rc-ccs-cc
519kms_ccs@pipe-C-bad-rotation-90-y-tiled-gen12-mc-ccs
520kms_ccs@pipe-C-bad-rotation-90-4-tiled-dg2-rc-ccs
521kms_ccs@pipe-C-bad-rotation-90-4-tiled-dg2-mc-ccs
522kms_ccs@pipe-C-bad-rotation-90-4-tiled-dg2-rc-ccs-cc
523kms_ccs@pipe-C-bad-rotation-90-4-tiled-mtl-rc-ccs
524kms_ccs@pipe-C-bad-rotation-90-4-tiled-mtl-mc-ccs
525kms_ccs@pipe-C-bad-rotation-90-4-tiled-mtl-rc-ccs-cc
526kms_ccs@pipe-C-crc-primary-basic-y-tiled-ccs
527kms_ccs@pipe-C-crc-primary-basic-yf-tiled-ccs
528kms_ccs@pipe-C-crc-primary-basic-y-tiled-gen12-rc-ccs
529kms_ccs@pipe-C-crc-primary-basic-y-tiled-gen12-rc-ccs-cc
530kms_ccs@pipe-C-crc-primary-basic-y-tiled-gen12-mc-ccs
531kms_ccs@pipe-C-crc-primary-basic-4-tiled-dg2-rc-ccs
532kms_ccs@pipe-C-crc-primary-basic-4-tiled-dg2-mc-ccs
533kms_ccs@pipe-C-crc-primary-basic-4-tiled-dg2-rc-ccs-cc
534kms_ccs@pipe-C-crc-primary-basic-4-tiled-mtl-rc-ccs
535kms_ccs@pipe-C-crc-primary-basic-4-tiled-mtl-mc-ccs
536kms_ccs@pipe-C-crc-primary-basic-4-tiled-mtl-rc-ccs-cc
537kms_ccs@pipe-C-crc-primary-rotation-180-y-tiled-ccs
538kms_ccs@pipe-C-crc-primary-rotation-180-yf-tiled-ccs
539kms_ccs@pipe-C-crc-primary-rotation-180-y-tiled-gen12-rc-ccs
540kms_ccs@pipe-C-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc
541kms_ccs@pipe-C-crc-primary-rotation-180-y-tiled-gen12-mc-ccs
542kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-dg2-rc-ccs
543kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-dg2-mc-ccs
544kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc
545kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-mtl-rc-ccs
546kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-mtl-mc-ccs
547kms_ccs@pipe-C-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc
548kms_ccs@pipe-C-random-ccs-data-y-tiled-ccs
549kms_ccs@pipe-C-random-ccs-data-yf-tiled-ccs
550kms_ccs@pipe-C-random-ccs-data-y-tiled-gen12-rc-ccs
551kms_ccs@pipe-C-random-ccs-data-y-tiled-gen12-rc-ccs-cc
552kms_ccs@pipe-C-random-ccs-data-y-tiled-gen12-mc-ccs
553kms_ccs@pipe-C-random-ccs-data-4-tiled-dg2-rc-ccs
554kms_ccs@pipe-C-random-ccs-data-4-tiled-dg2-mc-ccs
555kms_ccs@pipe-C-random-ccs-data-4-tiled-dg2-rc-ccs-cc
556kms_ccs@pipe-C-random-ccs-data-4-tiled-mtl-rc-ccs
557kms_ccs@pipe-C-random-ccs-data-4-tiled-mtl-mc-ccs
558kms_ccs@pipe-C-random-ccs-data-4-tiled-mtl-rc-ccs-cc
559kms_ccs@pipe-C-missing-ccs-buffer-y-tiled-ccs
560kms_ccs@pipe-C-missing-ccs-buffer-yf-tiled-ccs
561kms_ccs@pipe-C-missing-ccs-buffer-y-tiled-gen12-rc-ccs
562kms_ccs@pipe-C-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc
563kms_ccs@pipe-C-missing-ccs-buffer-y-tiled-gen12-mc-ccs
564kms_ccs@pipe-C-missing-ccs-buffer-4-tiled-mtl-rc-ccs
565kms_ccs@pipe-C-missing-ccs-buffer-4-tiled-mtl-mc-ccs
566kms_ccs@pipe-C-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc
567kms_ccs@pipe-C-ccs-on-another-bo-y-tiled-ccs
568kms_ccs@pipe-C-ccs-on-another-bo-yf-tiled-ccs
569kms_ccs@pipe-C-ccs-on-another-bo-y-tiled-gen12-rc-ccs
570kms_ccs@pipe-C-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc
571kms_ccs@pipe-C-ccs-on-another-bo-y-tiled-gen12-mc-ccs
572kms_ccs@pipe-C-ccs-on-another-bo-4-tiled-mtl-rc-ccs
573kms_ccs@pipe-C-ccs-on-another-bo-4-tiled-mtl-mc-ccs
574kms_ccs@pipe-C-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc
575kms_ccs@pipe-C-bad-aux-stride-y-tiled-ccs
576kms_ccs@pipe-C-bad-aux-stride-yf-tiled-ccs
577kms_ccs@pipe-C-bad-aux-stride-y-tiled-gen12-rc-ccs
578kms_ccs@pipe-C-bad-aux-stride-y-tiled-gen12-rc-ccs-cc
579kms_ccs@pipe-C-bad-aux-stride-y-tiled-gen12-mc-ccs
580kms_ccs@pipe-C-bad-aux-stride-4-tiled-mtl-rc-ccs
581kms_ccs@pipe-C-bad-aux-stride-4-tiled-mtl-mc-ccs
582kms_ccs@pipe-C-bad-aux-stride-4-tiled-mtl-rc-ccs-cc
583kms_ccs@pipe-C-crc-sprite-planes-basic-y-tiled-ccs
584kms_ccs@pipe-C-crc-sprite-planes-basic-yf-tiled-ccs
585kms_ccs@pipe-C-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs
586kms_ccs@pipe-C-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc
587kms_ccs@pipe-C-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs
588kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs
589kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs
590kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc
591kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs
592kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs
593kms_ccs@pipe-C-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc
594kms_ccs@pipe-D-bad-pixel-format-y-tiled-ccs
595kms_ccs@pipe-D-bad-pixel-format-yf-tiled-ccs
596kms_ccs@pipe-D-bad-pixel-format-y-tiled-gen12-rc-ccs
597kms_ccs@pipe-D-bad-pixel-format-y-tiled-gen12-rc-ccs-cc
598kms_ccs@pipe-D-bad-pixel-format-y-tiled-gen12-mc-ccs
599kms_ccs@pipe-D-bad-pixel-format-4-tiled-dg2-rc-ccs
600kms_ccs@pipe-D-bad-pixel-format-4-tiled-dg2-mc-ccs
601kms_ccs@pipe-D-bad-pixel-format-4-tiled-dg2-rc-ccs-cc
602kms_ccs@pipe-D-bad-pixel-format-4-tiled-mtl-rc-ccs
603kms_ccs@pipe-D-bad-pixel-format-4-tiled-mtl-mc-ccs
604kms_ccs@pipe-D-bad-pixel-format-4-tiled-mtl-rc-ccs-cc
605kms_ccs@pipe-D-bad-rotation-90-y-tiled-ccs
606kms_ccs@pipe-D-bad-rotation-90-yf-tiled-ccs
607kms_ccs@pipe-D-bad-rotation-90-y-tiled-gen12-rc-ccs
608kms_ccs@pipe-D-bad-rotation-90-y-tiled-gen12-rc-ccs-cc
609kms_ccs@pipe-D-bad-rotation-90-y-tiled-gen12-mc-ccs
610kms_ccs@pipe-D-bad-rotation-90-4-tiled-dg2-rc-ccs
611kms_ccs@pipe-D-bad-rotation-90-4-tiled-dg2-mc-ccs
612kms_ccs@pipe-D-bad-rotation-90-4-tiled-dg2-rc-ccs-cc
613kms_ccs@pipe-D-bad-rotation-90-4-tiled-mtl-rc-ccs
614kms_ccs@pipe-D-bad-rotation-90-4-tiled-mtl-mc-ccs
615kms_ccs@pipe-D-bad-rotation-90-4-tiled-mtl-rc-ccs-cc
616kms_ccs@pipe-D-crc-primary-basic-y-tiled-ccs
617kms_ccs@pipe-D-crc-primary-basic-yf-tiled-ccs
618kms_ccs@pipe-D-crc-primary-basic-y-tiled-gen12-rc-ccs
619kms_ccs@pipe-D-crc-primary-basic-y-tiled-gen12-rc-ccs-cc
620kms_ccs@pipe-D-crc-primary-basic-y-tiled-gen12-mc-ccs
621kms_ccs@pipe-D-crc-primary-basic-4-tiled-dg2-rc-ccs
622kms_ccs@pipe-D-crc-primary-basic-4-tiled-dg2-mc-ccs
623kms_ccs@pipe-D-crc-primary-basic-4-tiled-dg2-rc-ccs-cc
624kms_ccs@pipe-D-crc-primary-basic-4-tiled-mtl-rc-ccs
625kms_ccs@pipe-D-crc-primary-basic-4-tiled-mtl-mc-ccs
626kms_ccs@pipe-D-crc-primary-basic-4-tiled-mtl-rc-ccs-cc
627kms_ccs@pipe-D-crc-primary-rotation-180-y-tiled-ccs
628kms_ccs@pipe-D-crc-primary-rotation-180-yf-tiled-ccs
629kms_ccs@pipe-D-crc-primary-rotation-180-y-tiled-gen12-rc-ccs
630kms_ccs@pipe-D-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc
631kms_ccs@pipe-D-crc-primary-rotation-180-y-tiled-gen12-mc-ccs
632kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-dg2-rc-ccs
633kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-dg2-mc-ccs
634kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc
635kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-mtl-rc-ccs
636kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-mtl-mc-ccs
637kms_ccs@pipe-D-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc
638kms_ccs@pipe-D-random-ccs-data-y-tiled-ccs
639kms_ccs@pipe-D-random-ccs-data-yf-tiled-ccs
640kms_ccs@pipe-D-random-ccs-data-y-tiled-gen12-rc-ccs
641kms_ccs@pipe-D-random-ccs-data-y-tiled-gen12-rc-ccs-cc
642kms_ccs@pipe-D-random-ccs-data-y-tiled-gen12-mc-ccs
643kms_ccs@pipe-D-random-ccs-data-4-tiled-dg2-rc-ccs
644kms_ccs@pipe-D-random-ccs-data-4-tiled-dg2-mc-ccs
645kms_ccs@pipe-D-random-ccs-data-4-tiled-dg2-rc-ccs-cc
646kms_ccs@pipe-D-random-ccs-data-4-tiled-mtl-rc-ccs
647kms_ccs@pipe-D-random-ccs-data-4-tiled-mtl-mc-ccs
648kms_ccs@pipe-D-random-ccs-data-4-tiled-mtl-rc-ccs-cc
649kms_ccs@pipe-D-missing-ccs-buffer-y-tiled-ccs
650kms_ccs@pipe-D-missing-ccs-buffer-yf-tiled-ccs
651kms_ccs@pipe-D-missing-ccs-buffer-y-tiled-gen12-rc-ccs
652kms_ccs@pipe-D-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc
653kms_ccs@pipe-D-missing-ccs-buffer-y-tiled-gen12-mc-ccs
654kms_ccs@pipe-D-missing-ccs-buffer-4-tiled-mtl-rc-ccs
655kms_ccs@pipe-D-missing-ccs-buffer-4-tiled-mtl-mc-ccs
656kms_ccs@pipe-D-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc
657kms_ccs@pipe-D-ccs-on-another-bo-y-tiled-ccs
658kms_ccs@pipe-D-ccs-on-another-bo-yf-tiled-ccs
659kms_ccs@pipe-D-ccs-on-another-bo-y-tiled-gen12-rc-ccs
660kms_ccs@pipe-D-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc
661kms_ccs@pipe-D-ccs-on-another-bo-y-tiled-gen12-mc-ccs
662kms_ccs@pipe-D-ccs-on-another-bo-4-tiled-mtl-rc-ccs
663kms_ccs@pipe-D-ccs-on-another-bo-4-tiled-mtl-mc-ccs
664kms_ccs@pipe-D-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc
665kms_ccs@pipe-D-bad-aux-stride-y-tiled-ccs
666kms_ccs@pipe-D-bad-aux-stride-yf-tiled-ccs
667kms_ccs@pipe-D-bad-aux-stride-y-tiled-gen12-rc-ccs
668kms_ccs@pipe-D-bad-aux-stride-y-tiled-gen12-rc-ccs-cc
669kms_ccs@pipe-D-bad-aux-stride-y-tiled-gen12-mc-ccs
670kms_ccs@pipe-D-bad-aux-stride-4-tiled-mtl-rc-ccs
671kms_ccs@pipe-D-bad-aux-stride-4-tiled-mtl-mc-ccs
672kms_ccs@pipe-D-bad-aux-stride-4-tiled-mtl-rc-ccs-cc
673kms_ccs@pipe-D-crc-sprite-planes-basic-y-tiled-ccs
674kms_ccs@pipe-D-crc-sprite-planes-basic-yf-tiled-ccs
675kms_ccs@pipe-D-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs
676kms_ccs@pipe-D-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc
677kms_ccs@pipe-D-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs
678kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs
679kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs
680kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc
681kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs
682kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs
683kms_ccs@pipe-D-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc
684kms_ccs@pipe-E-bad-pixel-format-y-tiled-ccs
685kms_ccs@pipe-E-bad-pixel-format-yf-tiled-ccs
686kms_ccs@pipe-E-bad-pixel-format-y-tiled-gen12-rc-ccs
687kms_ccs@pipe-E-bad-pixel-format-y-tiled-gen12-rc-ccs-cc
688kms_ccs@pipe-E-bad-pixel-format-y-tiled-gen12-mc-ccs
689kms_ccs@pipe-E-bad-pixel-format-4-tiled-dg2-rc-ccs
690kms_ccs@pipe-E-bad-pixel-format-4-tiled-dg2-mc-ccs
691kms_ccs@pipe-E-bad-pixel-format-4-tiled-dg2-rc-ccs-cc
692kms_ccs@pipe-E-bad-pixel-format-4-tiled-mtl-rc-ccs
693kms_ccs@pipe-E-bad-pixel-format-4-tiled-mtl-mc-ccs
694kms_ccs@pipe-E-bad-pixel-format-4-tiled-mtl-rc-ccs-cc
695kms_ccs@pipe-E-bad-rotation-90-y-tiled-ccs
696kms_ccs@pipe-E-bad-rotation-90-yf-tiled-ccs
697kms_ccs@pipe-E-bad-rotation-90-y-tiled-gen12-rc-ccs
698kms_ccs@pipe-E-bad-rotation-90-y-tiled-gen12-rc-ccs-cc
699kms_ccs@pipe-E-bad-rotation-90-y-tiled-gen12-mc-ccs
700kms_ccs@pipe-E-bad-rotation-90-4-tiled-dg2-rc-ccs
701kms_ccs@pipe-E-bad-rotation-90-4-tiled-dg2-mc-ccs
702kms_ccs@pipe-E-bad-rotation-90-4-tiled-dg2-rc-ccs-cc
703kms_ccs@pipe-E-bad-rotation-90-4-tiled-mtl-rc-ccs
704kms_ccs@pipe-E-bad-rotation-90-4-tiled-mtl-mc-ccs
705kms_ccs@pipe-E-bad-rotation-90-4-tiled-mtl-rc-ccs-cc
706kms_ccs@pipe-E-crc-primary-basic-y-tiled-ccs
707kms_ccs@pipe-E-crc-primary-basic-yf-tiled-ccs
708kms_ccs@pipe-E-crc-primary-basic-y-tiled-gen12-rc-ccs
709kms_ccs@pipe-E-crc-primary-basic-y-tiled-gen12-rc-ccs-cc
710kms_ccs@pipe-E-crc-primary-basic-y-tiled-gen12-mc-ccs
711kms_ccs@pipe-E-crc-primary-basic-4-tiled-dg2-rc-ccs
712kms_ccs@pipe-E-crc-primary-basic-4-tiled-dg2-mc-ccs
713kms_ccs@pipe-E-crc-primary-basic-4-tiled-dg2-rc-ccs-cc
714kms_ccs@pipe-E-crc-primary-basic-4-tiled-mtl-rc-ccs
715kms_ccs@pipe-E-crc-primary-basic-4-tiled-mtl-mc-ccs
716kms_ccs@pipe-E-crc-primary-basic-4-tiled-mtl-rc-ccs-cc
717kms_ccs@pipe-E-crc-primary-rotation-180-y-tiled-ccs
718kms_ccs@pipe-E-crc-primary-rotation-180-yf-tiled-ccs
719kms_ccs@pipe-E-crc-primary-rotation-180-y-tiled-gen12-rc-ccs
720kms_ccs@pipe-E-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc
721kms_ccs@pipe-E-crc-primary-rotation-180-y-tiled-gen12-mc-ccs
722kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-dg2-rc-ccs
723kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-dg2-mc-ccs
724kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc
725kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-mtl-rc-ccs
726kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-mtl-mc-ccs
727kms_ccs@pipe-E-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc
728kms_ccs@pipe-E-random-ccs-data-y-tiled-ccs
729kms_ccs@pipe-E-random-ccs-data-yf-tiled-ccs
730kms_ccs@pipe-E-random-ccs-data-y-tiled-gen12-rc-ccs
731kms_ccs@pipe-E-random-ccs-data-y-tiled-gen12-rc-ccs-cc
732kms_ccs@pipe-E-random-ccs-data-y-tiled-gen12-mc-ccs
733kms_ccs@pipe-E-random-ccs-data-4-tiled-dg2-rc-ccs
734kms_ccs@pipe-E-random-ccs-data-4-tiled-dg2-mc-ccs
735kms_ccs@pipe-E-random-ccs-data-4-tiled-dg2-rc-ccs-cc
736kms_ccs@pipe-E-random-ccs-data-4-tiled-mtl-rc-ccs
737kms_ccs@pipe-E-random-ccs-data-4-tiled-mtl-mc-ccs
738kms_ccs@pipe-E-random-ccs-data-4-tiled-mtl-rc-ccs-cc
739kms_ccs@pipe-E-missing-ccs-buffer-y-tiled-ccs
740kms_ccs@pipe-E-missing-ccs-buffer-yf-tiled-ccs
741kms_ccs@pipe-E-missing-ccs-buffer-y-tiled-gen12-rc-ccs
742kms_ccs@pipe-E-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc
743kms_ccs@pipe-E-missing-ccs-buffer-y-tiled-gen12-mc-ccs
744kms_ccs@pipe-E-missing-ccs-buffer-4-tiled-mtl-rc-ccs
745kms_ccs@pipe-E-missing-ccs-buffer-4-tiled-mtl-mc-ccs
746kms_ccs@pipe-E-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc
747kms_ccs@pipe-E-ccs-on-another-bo-y-tiled-ccs
748kms_ccs@pipe-E-ccs-on-another-bo-yf-tiled-ccs
749kms_ccs@pipe-E-ccs-on-another-bo-y-tiled-gen12-rc-ccs
750kms_ccs@pipe-E-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc
751kms_ccs@pipe-E-ccs-on-another-bo-y-tiled-gen12-mc-ccs
752kms_ccs@pipe-E-ccs-on-another-bo-4-tiled-mtl-rc-ccs
753kms_ccs@pipe-E-ccs-on-another-bo-4-tiled-mtl-mc-ccs
754kms_ccs@pipe-E-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc
755kms_ccs@pipe-E-bad-aux-stride-y-tiled-ccs
756kms_ccs@pipe-E-bad-aux-stride-yf-tiled-ccs
757kms_ccs@pipe-E-bad-aux-stride-y-tiled-gen12-rc-ccs
758kms_ccs@pipe-E-bad-aux-stride-y-tiled-gen12-rc-ccs-cc
759kms_ccs@pipe-E-bad-aux-stride-y-tiled-gen12-mc-ccs
760kms_ccs@pipe-E-bad-aux-stride-4-tiled-mtl-rc-ccs
761kms_ccs@pipe-E-bad-aux-stride-4-tiled-mtl-mc-ccs
762kms_ccs@pipe-E-bad-aux-stride-4-tiled-mtl-rc-ccs-cc
763kms_ccs@pipe-E-crc-sprite-planes-basic-y-tiled-ccs
764kms_ccs@pipe-E-crc-sprite-planes-basic-yf-tiled-ccs
765kms_ccs@pipe-E-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs
766kms_ccs@pipe-E-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc
767kms_ccs@pipe-E-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs
768kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs
769kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs
770kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc
771kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs
772kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs
773kms_ccs@pipe-E-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc
774kms_ccs@pipe-F-bad-pixel-format-y-tiled-ccs
775kms_ccs@pipe-F-bad-pixel-format-yf-tiled-ccs
776kms_ccs@pipe-F-bad-pixel-format-y-tiled-gen12-rc-ccs
777kms_ccs@pipe-F-bad-pixel-format-y-tiled-gen12-rc-ccs-cc
778kms_ccs@pipe-F-bad-pixel-format-y-tiled-gen12-mc-ccs
779kms_ccs@pipe-F-bad-pixel-format-4-tiled-dg2-rc-ccs
780kms_ccs@pipe-F-bad-pixel-format-4-tiled-dg2-mc-ccs
781kms_ccs@pipe-F-bad-pixel-format-4-tiled-dg2-rc-ccs-cc
782kms_ccs@pipe-F-bad-pixel-format-4-tiled-mtl-rc-ccs
783kms_ccs@pipe-F-bad-pixel-format-4-tiled-mtl-mc-ccs
784kms_ccs@pipe-F-bad-pixel-format-4-tiled-mtl-rc-ccs-cc
785kms_ccs@pipe-F-bad-rotation-90-y-tiled-ccs
786kms_ccs@pipe-F-bad-rotation-90-yf-tiled-ccs
787kms_ccs@pipe-F-bad-rotation-90-y-tiled-gen12-rc-ccs
788kms_ccs@pipe-F-bad-rotation-90-y-tiled-gen12-rc-ccs-cc
789kms_ccs@pipe-F-bad-rotation-90-y-tiled-gen12-mc-ccs
790kms_ccs@pipe-F-bad-rotation-90-4-tiled-dg2-rc-ccs
791kms_ccs@pipe-F-bad-rotation-90-4-tiled-dg2-mc-ccs
792kms_ccs@pipe-F-bad-rotation-90-4-tiled-dg2-rc-ccs-cc
793kms_ccs@pipe-F-bad-rotation-90-4-tiled-mtl-rc-ccs
794kms_ccs@pipe-F-bad-rotation-90-4-tiled-mtl-mc-ccs
795kms_ccs@pipe-F-bad-rotation-90-4-tiled-mtl-rc-ccs-cc
796kms_ccs@pipe-F-crc-primary-basic-y-tiled-ccs
797kms_ccs@pipe-F-crc-primary-basic-yf-tiled-ccs
798kms_ccs@pipe-F-crc-primary-basic-y-tiled-gen12-rc-ccs
799kms_ccs@pipe-F-crc-primary-basic-y-tiled-gen12-rc-ccs-cc
800kms_ccs@pipe-F-crc-primary-basic-y-tiled-gen12-mc-ccs
801kms_ccs@pipe-F-crc-primary-basic-4-tiled-dg2-rc-ccs
802kms_ccs@pipe-F-crc-primary-basic-4-tiled-dg2-mc-ccs
803kms_ccs@pipe-F-crc-primary-basic-4-tiled-dg2-rc-ccs-cc
804kms_ccs@pipe-F-crc-primary-basic-4-tiled-mtl-rc-ccs
805kms_ccs@pipe-F-crc-primary-basic-4-tiled-mtl-mc-ccs
806kms_ccs@pipe-F-crc-primary-basic-4-tiled-mtl-rc-ccs-cc
807kms_ccs@pipe-F-crc-primary-rotation-180-y-tiled-ccs
808kms_ccs@pipe-F-crc-primary-rotation-180-yf-tiled-ccs
809kms_ccs@pipe-F-crc-primary-rotation-180-y-tiled-gen12-rc-ccs
810kms_ccs@pipe-F-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc
811kms_ccs@pipe-F-crc-primary-rotation-180-y-tiled-gen12-mc-ccs
812kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-dg2-rc-ccs
813kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-dg2-mc-ccs
814kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc
815kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-mtl-rc-ccs
816kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-mtl-mc-ccs
817kms_ccs@pipe-F-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc
818kms_ccs@pipe-F-random-ccs-data-y-tiled-ccs
819kms_ccs@pipe-F-random-ccs-data-yf-tiled-ccs
820kms_ccs@pipe-F-random-ccs-data-y-tiled-gen12-rc-ccs
821kms_ccs@pipe-F-random-ccs-data-y-tiled-gen12-rc-ccs-cc
822kms_ccs@pipe-F-random-ccs-data-y-tiled-gen12-mc-ccs
823kms_ccs@pipe-F-random-ccs-data-4-tiled-dg2-rc-ccs
824kms_ccs@pipe-F-random-ccs-data-4-tiled-dg2-mc-ccs
825kms_ccs@pipe-F-random-ccs-data-4-tiled-dg2-rc-ccs-cc
826kms_ccs@pipe-F-random-ccs-data-4-tiled-mtl-rc-ccs
827kms_ccs@pipe-F-random-ccs-data-4-tiled-mtl-mc-ccs
828kms_ccs@pipe-F-random-ccs-data-4-tiled-mtl-rc-ccs-cc
829kms_ccs@pipe-F-missing-ccs-buffer-y-tiled-ccs
830kms_ccs@pipe-F-missing-ccs-buffer-yf-tiled-ccs
831kms_ccs@pipe-F-missing-ccs-buffer-y-tiled-gen12-rc-ccs
832kms_ccs@pipe-F-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc
833kms_ccs@pipe-F-missing-ccs-buffer-y-tiled-gen12-mc-ccs
834kms_ccs@pipe-F-missing-ccs-buffer-4-tiled-mtl-rc-ccs
835kms_ccs@pipe-F-missing-ccs-buffer-4-tiled-mtl-mc-ccs
836kms_ccs@pipe-F-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc
837kms_ccs@pipe-F-ccs-on-another-bo-y-tiled-ccs
838kms_ccs@pipe-F-ccs-on-another-bo-yf-tiled-ccs
839kms_ccs@pipe-F-ccs-on-another-bo-y-tiled-gen12-rc-ccs
840kms_ccs@pipe-F-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc
841kms_ccs@pipe-F-ccs-on-another-bo-y-tiled-gen12-mc-ccs
842kms_ccs@pipe-F-ccs-on-another-bo-4-tiled-mtl-rc-ccs
843kms_ccs@pipe-F-ccs-on-another-bo-4-tiled-mtl-mc-ccs
844kms_ccs@pipe-F-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc
845kms_ccs@pipe-F-bad-aux-stride-y-tiled-ccs
846kms_ccs@pipe-F-bad-aux-stride-yf-tiled-ccs
847kms_ccs@pipe-F-bad-aux-stride-y-tiled-gen12-rc-ccs
848kms_ccs@pipe-F-bad-aux-stride-y-tiled-gen12-rc-ccs-cc
849kms_ccs@pipe-F-bad-aux-stride-y-tiled-gen12-mc-ccs
850kms_ccs@pipe-F-bad-aux-stride-4-tiled-mtl-rc-ccs
851kms_ccs@pipe-F-bad-aux-stride-4-tiled-mtl-mc-ccs
852kms_ccs@pipe-F-bad-aux-stride-4-tiled-mtl-rc-ccs-cc
853kms_ccs@pipe-F-crc-sprite-planes-basic-y-tiled-ccs
854kms_ccs@pipe-F-crc-sprite-planes-basic-yf-tiled-ccs
855kms_ccs@pipe-F-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs
856kms_ccs@pipe-F-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc
857kms_ccs@pipe-F-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs
858kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs
859kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs
860kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc
861kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs
862kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs
863kms_ccs@pipe-F-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc
864kms_ccs@pipe-G-bad-pixel-format-y-tiled-ccs
865kms_ccs@pipe-G-bad-pixel-format-yf-tiled-ccs
866kms_ccs@pipe-G-bad-pixel-format-y-tiled-gen12-rc-ccs
867kms_ccs@pipe-G-bad-pixel-format-y-tiled-gen12-rc-ccs-cc
868kms_ccs@pipe-G-bad-pixel-format-y-tiled-gen12-mc-ccs
869kms_ccs@pipe-G-bad-pixel-format-4-tiled-dg2-rc-ccs
870kms_ccs@pipe-G-bad-pixel-format-4-tiled-dg2-mc-ccs
871kms_ccs@pipe-G-bad-pixel-format-4-tiled-dg2-rc-ccs-cc
872kms_ccs@pipe-G-bad-pixel-format-4-tiled-mtl-rc-ccs
873kms_ccs@pipe-G-bad-pixel-format-4-tiled-mtl-mc-ccs
874kms_ccs@pipe-G-bad-pixel-format-4-tiled-mtl-rc-ccs-cc
875kms_ccs@pipe-G-bad-rotation-90-y-tiled-ccs
876kms_ccs@pipe-G-bad-rotation-90-yf-tiled-ccs
877kms_ccs@pipe-G-bad-rotation-90-y-tiled-gen12-rc-ccs
878kms_ccs@pipe-G-bad-rotation-90-y-tiled-gen12-rc-ccs-cc
879kms_ccs@pipe-G-bad-rotation-90-y-tiled-gen12-mc-ccs
880kms_ccs@pipe-G-bad-rotation-90-4-tiled-dg2-rc-ccs
881kms_ccs@pipe-G-bad-rotation-90-4-tiled-dg2-mc-ccs
882kms_ccs@pipe-G-bad-rotation-90-4-tiled-dg2-rc-ccs-cc
883kms_ccs@pipe-G-bad-rotation-90-4-tiled-mtl-rc-ccs
884kms_ccs@pipe-G-bad-rotation-90-4-tiled-mtl-mc-ccs
885kms_ccs@pipe-G-bad-rotation-90-4-tiled-mtl-rc-ccs-cc
886kms_ccs@pipe-G-crc-primary-basic-y-tiled-ccs
887kms_ccs@pipe-G-crc-primary-basic-yf-tiled-ccs
888kms_ccs@pipe-G-crc-primary-basic-y-tiled-gen12-rc-ccs
889kms_ccs@pipe-G-crc-primary-basic-y-tiled-gen12-rc-ccs-cc
890kms_ccs@pipe-G-crc-primary-basic-y-tiled-gen12-mc-ccs
891kms_ccs@pipe-G-crc-primary-basic-4-tiled-dg2-rc-ccs
892kms_ccs@pipe-G-crc-primary-basic-4-tiled-dg2-mc-ccs
893kms_ccs@pipe-G-crc-primary-basic-4-tiled-dg2-rc-ccs-cc
894kms_ccs@pipe-G-crc-primary-basic-4-tiled-mtl-rc-ccs
895kms_ccs@pipe-G-crc-primary-basic-4-tiled-mtl-mc-ccs
896kms_ccs@pipe-G-crc-primary-basic-4-tiled-mtl-rc-ccs-cc
897kms_ccs@pipe-G-crc-primary-rotation-180-y-tiled-ccs
898kms_ccs@pipe-G-crc-primary-rotation-180-yf-tiled-ccs
899kms_ccs@pipe-G-crc-primary-rotation-180-y-tiled-gen12-rc-ccs
900kms_ccs@pipe-G-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc
901kms_ccs@pipe-G-crc-primary-rotation-180-y-tiled-gen12-mc-ccs
902kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-dg2-rc-ccs
903kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-dg2-mc-ccs
904kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc
905kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-mtl-rc-ccs
906kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-mtl-mc-ccs
907kms_ccs@pipe-G-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc
908kms_ccs@pipe-G-random-ccs-data-y-tiled-ccs
909kms_ccs@pipe-G-random-ccs-data-yf-tiled-ccs
910kms_ccs@pipe-G-random-ccs-data-y-tiled-gen12-rc-ccs
911kms_ccs@pipe-G-random-ccs-data-y-tiled-gen12-rc-ccs-cc
912kms_ccs@pipe-G-random-ccs-data-y-tiled-gen12-mc-ccs
913kms_ccs@pipe-G-random-ccs-data-4-tiled-dg2-rc-ccs
914kms_ccs@pipe-G-random-ccs-data-4-tiled-dg2-mc-ccs
915kms_ccs@pipe-G-random-ccs-data-4-tiled-dg2-rc-ccs-cc
916kms_ccs@pipe-G-random-ccs-data-4-tiled-mtl-rc-ccs
917kms_ccs@pipe-G-random-ccs-data-4-tiled-mtl-mc-ccs
918kms_ccs@pipe-G-random-ccs-data-4-tiled-mtl-rc-ccs-cc
919kms_ccs@pipe-G-missing-ccs-buffer-y-tiled-ccs
920kms_ccs@pipe-G-missing-ccs-buffer-yf-tiled-ccs
921kms_ccs@pipe-G-missing-ccs-buffer-y-tiled-gen12-rc-ccs
922kms_ccs@pipe-G-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc
923kms_ccs@pipe-G-missing-ccs-buffer-y-tiled-gen12-mc-ccs
924kms_ccs@pipe-G-missing-ccs-buffer-4-tiled-mtl-rc-ccs
925kms_ccs@pipe-G-missing-ccs-buffer-4-tiled-mtl-mc-ccs
926kms_ccs@pipe-G-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc
927kms_ccs@pipe-G-ccs-on-another-bo-y-tiled-ccs
928kms_ccs@pipe-G-ccs-on-another-bo-yf-tiled-ccs
929kms_ccs@pipe-G-ccs-on-another-bo-y-tiled-gen12-rc-ccs
930kms_ccs@pipe-G-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc
931kms_ccs@pipe-G-ccs-on-another-bo-y-tiled-gen12-mc-ccs
932kms_ccs@pipe-G-ccs-on-another-bo-4-tiled-mtl-rc-ccs
933kms_ccs@pipe-G-ccs-on-another-bo-4-tiled-mtl-mc-ccs
934kms_ccs@pipe-G-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc
935kms_ccs@pipe-G-bad-aux-stride-y-tiled-ccs
936kms_ccs@pipe-G-bad-aux-stride-yf-tiled-ccs
937kms_ccs@pipe-G-bad-aux-stride-y-tiled-gen12-rc-ccs
938kms_ccs@pipe-G-bad-aux-stride-y-tiled-gen12-rc-ccs-cc
939kms_ccs@pipe-G-bad-aux-stride-y-tiled-gen12-mc-ccs
940kms_ccs@pipe-G-bad-aux-stride-4-tiled-mtl-rc-ccs
941kms_ccs@pipe-G-bad-aux-stride-4-tiled-mtl-mc-ccs
942kms_ccs@pipe-G-bad-aux-stride-4-tiled-mtl-rc-ccs-cc
943kms_ccs@pipe-G-crc-sprite-planes-basic-y-tiled-ccs
944kms_ccs@pipe-G-crc-sprite-planes-basic-yf-tiled-ccs
945kms_ccs@pipe-G-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs
946kms_ccs@pipe-G-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc
947kms_ccs@pipe-G-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs
948kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs
949kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs
950kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc
951kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs
952kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs
953kms_ccs@pipe-G-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc
954kms_ccs@pipe-H-bad-pixel-format-y-tiled-ccs
955kms_ccs@pipe-H-bad-pixel-format-yf-tiled-ccs
956kms_ccs@pipe-H-bad-pixel-format-y-tiled-gen12-rc-ccs
957kms_ccs@pipe-H-bad-pixel-format-y-tiled-gen12-rc-ccs-cc
958kms_ccs@pipe-H-bad-pixel-format-y-tiled-gen12-mc-ccs
959kms_ccs@pipe-H-bad-pixel-format-4-tiled-dg2-rc-ccs
960kms_ccs@pipe-H-bad-pixel-format-4-tiled-dg2-mc-ccs
961kms_ccs@pipe-H-bad-pixel-format-4-tiled-dg2-rc-ccs-cc
962kms_ccs@pipe-H-bad-pixel-format-4-tiled-mtl-rc-ccs
963kms_ccs@pipe-H-bad-pixel-format-4-tiled-mtl-mc-ccs
964kms_ccs@pipe-H-bad-pixel-format-4-tiled-mtl-rc-ccs-cc
965kms_ccs@pipe-H-bad-rotation-90-y-tiled-ccs
966kms_ccs@pipe-H-bad-rotation-90-yf-tiled-ccs
967kms_ccs@pipe-H-bad-rotation-90-y-tiled-gen12-rc-ccs
968kms_ccs@pipe-H-bad-rotation-90-y-tiled-gen12-rc-ccs-cc
969kms_ccs@pipe-H-bad-rotation-90-y-tiled-gen12-mc-ccs
970kms_ccs@pipe-H-bad-rotation-90-4-tiled-dg2-rc-ccs
971kms_ccs@pipe-H-bad-rotation-90-4-tiled-dg2-mc-ccs
972kms_ccs@pipe-H-bad-rotation-90-4-tiled-dg2-rc-ccs-cc
973kms_ccs@pipe-H-bad-rotation-90-4-tiled-mtl-rc-ccs
974kms_ccs@pipe-H-bad-rotation-90-4-tiled-mtl-mc-ccs
975kms_ccs@pipe-H-bad-rotation-90-4-tiled-mtl-rc-ccs-cc
976kms_ccs@pipe-H-crc-primary-basic-y-tiled-ccs
977kms_ccs@pipe-H-crc-primary-basic-yf-tiled-ccs
978kms_ccs@pipe-H-crc-primary-basic-y-tiled-gen12-rc-ccs
979kms_ccs@pipe-H-crc-primary-basic-y-tiled-gen12-rc-ccs-cc
980kms_ccs@pipe-H-crc-primary-basic-y-tiled-gen12-mc-ccs
981kms_ccs@pipe-H-crc-primary-basic-4-tiled-dg2-rc-ccs
982kms_ccs@pipe-H-crc-primary-basic-4-tiled-dg2-mc-ccs
983kms_ccs@pipe-H-crc-primary-basic-4-tiled-dg2-rc-ccs-cc
984kms_ccs@pipe-H-crc-primary-basic-4-tiled-mtl-rc-ccs
985kms_ccs@pipe-H-crc-primary-basic-4-tiled-mtl-mc-ccs
986kms_ccs@pipe-H-crc-primary-basic-4-tiled-mtl-rc-ccs-cc
987kms_ccs@pipe-H-crc-primary-rotation-180-y-tiled-ccs
988kms_ccs@pipe-H-crc-primary-rotation-180-yf-tiled-ccs
989kms_ccs@pipe-H-crc-primary-rotation-180-y-tiled-gen12-rc-ccs
990kms_ccs@pipe-H-crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc
991kms_ccs@pipe-H-crc-primary-rotation-180-y-tiled-gen12-mc-ccs
992kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-dg2-rc-ccs
993kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-dg2-mc-ccs
994kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc
995kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-mtl-rc-ccs
996kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-mtl-mc-ccs
997kms_ccs@pipe-H-crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc
998kms_ccs@pipe-H-random-ccs-data-y-tiled-ccs
999kms_ccs@pipe-H-random-ccs-data-yf-tiled-ccs
1000kms_ccs@pipe-H-random-ccs-data-y-tiled-gen12-rc-ccs
1001kms_ccs@pipe-H-random-ccs-data-y-tiled-gen12-rc-ccs-cc
1002kms_ccs@pipe-H-random-ccs-data-y-tiled-gen12-mc-ccs
1003kms_ccs@pipe-H-random-ccs-data-4-tiled-dg2-rc-ccs
1004kms_ccs@pipe-H-random-ccs-data-4-tiled-dg2-mc-ccs
1005kms_ccs@pipe-H-random-ccs-data-4-tiled-dg2-rc-ccs-cc
1006kms_ccs@pipe-H-random-ccs-data-4-tiled-mtl-rc-ccs
1007kms_ccs@pipe-H-random-ccs-data-4-tiled-mtl-mc-ccs
1008kms_ccs@pipe-H-random-ccs-data-4-tiled-mtl-rc-ccs-cc
1009kms_ccs@pipe-H-missing-ccs-buffer-y-tiled-ccs
1010kms_ccs@pipe-H-missing-ccs-buffer-yf-tiled-ccs
1011kms_ccs@pipe-H-missing-ccs-buffer-y-tiled-gen12-rc-ccs
1012kms_ccs@pipe-H-missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc
1013kms_ccs@pipe-H-missing-ccs-buffer-y-tiled-gen12-mc-ccs
1014kms_ccs@pipe-H-missing-ccs-buffer-4-tiled-mtl-rc-ccs
1015kms_ccs@pipe-H-missing-ccs-buffer-4-tiled-mtl-mc-ccs
1016kms_ccs@pipe-H-missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc
1017kms_ccs@pipe-H-ccs-on-another-bo-y-tiled-ccs
1018kms_ccs@pipe-H-ccs-on-another-bo-yf-tiled-ccs
1019kms_ccs@pipe-H-ccs-on-another-bo-y-tiled-gen12-rc-ccs
1020kms_ccs@pipe-H-ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc
1021kms_ccs@pipe-H-ccs-on-another-bo-y-tiled-gen12-mc-ccs
1022kms_ccs@pipe-H-ccs-on-another-bo-4-tiled-mtl-rc-ccs
1023kms_ccs@pipe-H-ccs-on-another-bo-4-tiled-mtl-mc-ccs
1024kms_ccs@pipe-H-ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc
1025kms_ccs@pipe-H-bad-aux-stride-y-tiled-ccs
1026kms_ccs@pipe-H-bad-aux-stride-yf-tiled-ccs
1027kms_ccs@pipe-H-bad-aux-stride-y-tiled-gen12-rc-ccs
1028kms_ccs@pipe-H-bad-aux-stride-y-tiled-gen12-rc-ccs-cc
1029kms_ccs@pipe-H-bad-aux-stride-y-tiled-gen12-mc-ccs
1030kms_ccs@pipe-H-bad-aux-stride-4-tiled-mtl-rc-ccs
1031kms_ccs@pipe-H-bad-aux-stride-4-tiled-mtl-mc-ccs
1032kms_ccs@pipe-H-bad-aux-stride-4-tiled-mtl-rc-ccs-cc
1033kms_ccs@pipe-H-crc-sprite-planes-basic-y-tiled-ccs
1034kms_ccs@pipe-H-crc-sprite-planes-basic-yf-tiled-ccs
1035kms_ccs@pipe-H-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs
1036kms_ccs@pipe-H-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc
1037kms_ccs@pipe-H-crc-sprite-planes-basic-y-tiled-gen12-mc-ccs
1038kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs
1039kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-dg2-mc-ccs
1040kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc
1041kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs
1042kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-mtl-mc-ccs
1043kms_ccs@pipe-H-crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc
1044kms_cdclk@plane-scaling
1045kms_cdclk@mode-transition
1046kms_cdclk@mode-transition-all-outputs
1047kms_color@degamma
1048kms_color@gamma
1049kms_color@legacy-gamma
1050kms_color@legacy-gamma-reset
1051kms_color@ctm-red-to-blue
1052kms_color@ctm-green-to-red
1053kms_color@ctm-blue-to-red
1054kms_color@ctm-max
1055kms_color@ctm-negative
1056kms_color@ctm-0-25
1057kms_color@ctm-0-50
1058kms_color@ctm-0-75
1059kms_color@ctm-signed
1060kms_color@deep-color
1061kms_color@invalid-gamma-lut-sizes
1062kms_color@invalid-degamma-lut-sizes
1063kms_color@invalid-ctm-matrix-sizes
1064kms_concurrent@multi-plane-atomic-lowres
1065kms_content_protection@legacy
1066kms_content_protection@atomic
1067kms_content_protection@atomic-dpms
1068kms_content_protection@lic
1069kms_content_protection@type1
1070kms_content_protection@mei-interface
1071kms_content_protection@content-type-change
1072kms_content_protection@uevent
1073kms_content_protection@srm
1074kms_content_protection@dp-mst-type-0
1075kms_content_protection@dp-mst-lic-type-0
1076kms_content_protection@dp-mst-type-1
1077kms_content_protection@dp-mst-lic-type-1
1078kms_cursor_crc@cursor-size-change
1079kms_cursor_crc@cursor-alpha-opaque
1080kms_cursor_crc@cursor-alpha-transparent
1081kms_cursor_crc@cursor-dpms
1082kms_cursor_crc@cursor-suspend
1083kms_cursor_crc@cursor-onscreen-32x32
1084kms_cursor_crc@cursor-offscreen-32x32
1085kms_cursor_crc@cursor-sliding-32x32
1086kms_cursor_crc@cursor-random-32x32
1087kms_cursor_crc@cursor-rapid-movement-32x32
1088kms_cursor_crc@cursor-onscreen-32x10
1089kms_cursor_crc@cursor-offscreen-32x10
1090kms_cursor_crc@cursor-sliding-32x10
1091kms_cursor_crc@cursor-random-32x10
1092kms_cursor_crc@cursor-rapid-movement-32x10
1093kms_cursor_crc@cursor-onscreen-64x64
1094kms_cursor_crc@cursor-offscreen-64x64
1095kms_cursor_crc@cursor-sliding-64x64
1096kms_cursor_crc@cursor-random-64x64
1097kms_cursor_crc@cursor-rapid-movement-64x64
1098kms_cursor_crc@cursor-onscreen-64x21
1099kms_cursor_crc@cursor-offscreen-64x21
1100kms_cursor_crc@cursor-sliding-64x21
1101kms_cursor_crc@cursor-random-64x21
1102kms_cursor_crc@cursor-rapid-movement-64x21
1103kms_cursor_crc@cursor-onscreen-128x128
1104kms_cursor_crc@cursor-offscreen-128x128
1105kms_cursor_crc@cursor-sliding-128x128
1106kms_cursor_crc@cursor-random-128x128
1107kms_cursor_crc@cursor-rapid-movement-128x128
1108kms_cursor_crc@cursor-onscreen-128x42
1109kms_cursor_crc@cursor-offscreen-128x42
1110kms_cursor_crc@cursor-sliding-128x42
1111kms_cursor_crc@cursor-random-128x42
1112kms_cursor_crc@cursor-rapid-movement-128x42
1113kms_cursor_crc@cursor-onscreen-256x256
1114kms_cursor_crc@cursor-offscreen-256x256
1115kms_cursor_crc@cursor-sliding-256x256
1116kms_cursor_crc@cursor-random-256x256
1117kms_cursor_crc@cursor-rapid-movement-256x256
1118kms_cursor_crc@cursor-onscreen-256x85
1119kms_cursor_crc@cursor-offscreen-256x85
1120kms_cursor_crc@cursor-sliding-256x85
1121kms_cursor_crc@cursor-random-256x85
1122kms_cursor_crc@cursor-rapid-movement-256x85
1123kms_cursor_crc@cursor-onscreen-512x512
1124kms_cursor_crc@cursor-offscreen-512x512
1125kms_cursor_crc@cursor-sliding-512x512
1126kms_cursor_crc@cursor-random-512x512
1127kms_cursor_crc@cursor-rapid-movement-512x512
1128kms_cursor_crc@cursor-onscreen-512x170
1129kms_cursor_crc@cursor-offscreen-512x170
1130kms_cursor_crc@cursor-sliding-512x170
1131kms_cursor_crc@cursor-random-512x170
1132kms_cursor_crc@cursor-rapid-movement-512x170
1133kms_cursor_crc@cursor-onscreen-max-size
1134kms_cursor_crc@cursor-offscreen-max-size
1135kms_cursor_crc@cursor-sliding-max-size
1136kms_cursor_crc@cursor-random-max-size
1137kms_cursor_crc@cursor-rapid-movement-max-size
1138kms_cursor_legacy@single-bo
1139kms_cursor_legacy@single-move
1140kms_cursor_legacy@forked-bo
1141kms_cursor_legacy@forked-move
1142kms_cursor_legacy@torture-bo
1143kms_cursor_legacy@torture-move
1144kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic
1145kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic
1146kms_cursor_legacy@2x-flip-vs-cursor-legacy
1147kms_cursor_legacy@2x-flip-vs-cursor-atomic
1148kms_cursor_legacy@2x-long-flip-vs-cursor-legacy
1149kms_cursor_legacy@2x-long-flip-vs-cursor-atomic
1150kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic
1151kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic
1152kms_cursor_legacy@2x-cursor-vs-flip-legacy
1153kms_cursor_legacy@2x-long-cursor-vs-flip-legacy
1154kms_cursor_legacy@2x-cursor-vs-flip-atomic
1155kms_cursor_legacy@2x-long-cursor-vs-flip-atomic
1156kms_cursor_legacy@flip-vs-cursor-crc-legacy
1157kms_cursor_legacy@flip-vs-cursor-crc-atomic
1158kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy
1159kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic
1160kms_cursor_legacy@basic-flip-before-cursor-legacy
1161kms_cursor_legacy@basic-busy-flip-before-cursor-legacy
1162kms_cursor_legacy@basic-flip-after-cursor-legacy
1163kms_cursor_legacy@basic-flip-before-cursor-varying-size
1164kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size
1165kms_cursor_legacy@basic-flip-after-cursor-varying-size
1166kms_cursor_legacy@short-flip-before-cursor-toggle
1167kms_cursor_legacy@short-busy-flip-before-cursor-toggle
1168kms_cursor_legacy@short-flip-after-cursor-toggle
1169kms_cursor_legacy@basic-flip-before-cursor-atomic
1170kms_cursor_legacy@basic-busy-flip-before-cursor-atomic
1171kms_cursor_legacy@basic-flip-after-cursor-atomic
1172kms_cursor_legacy@short-flip-before-cursor-atomic-transitions
1173kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions
1174kms_cursor_legacy@short-flip-after-cursor-atomic-transitions
1175kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size
1176kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size
1177kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size
1178kms_cursor_legacy@cursor-vs-flip-legacy
1179kms_cursor_legacy@flip-vs-cursor-legacy
1180kms_cursor_legacy@cursorA-vs-flipA-legacy
1181kms_cursor_legacy@cursorA-vs-flipB-legacy
1182kms_cursor_legacy@cursorB-vs-flipA-legacy
1183kms_cursor_legacy@cursorB-vs-flipB-legacy
1184kms_cursor_legacy@cursor-vs-flip-varying-size
1185kms_cursor_legacy@flip-vs-cursor-varying-size
1186kms_cursor_legacy@cursorA-vs-flipA-varying-size
1187kms_cursor_legacy@cursorA-vs-flipB-varying-size
1188kms_cursor_legacy@cursorB-vs-flipA-varying-size
1189kms_cursor_legacy@cursorB-vs-flipB-varying-size
1190kms_cursor_legacy@cursor-vs-flip-toggle
1191kms_cursor_legacy@flip-vs-cursor-toggle
1192kms_cursor_legacy@cursorA-vs-flipA-toggle
1193kms_cursor_legacy@cursorA-vs-flipB-toggle
1194kms_cursor_legacy@cursorB-vs-flipA-toggle
1195kms_cursor_legacy@cursorB-vs-flipB-toggle
1196kms_cursor_legacy@cursor-vs-flip-atomic
1197kms_cursor_legacy@flip-vs-cursor-atomic
1198kms_cursor_legacy@cursorA-vs-flipA-atomic
1199kms_cursor_legacy@cursorA-vs-flipB-atomic
1200kms_cursor_legacy@cursorB-vs-flipA-atomic
1201kms_cursor_legacy@cursorB-vs-flipB-atomic
1202kms_cursor_legacy@cursor-vs-flip-atomic-transitions
1203kms_cursor_legacy@flip-vs-cursor-atomic-transitions
1204kms_cursor_legacy@cursorA-vs-flipA-atomic-transitions
1205kms_cursor_legacy@cursorA-vs-flipB-atomic-transitions
1206kms_cursor_legacy@cursorB-vs-flipA-atomic-transitions
1207kms_cursor_legacy@cursorB-vs-flipB-atomic-transitions
1208kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size
1209kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size
1210kms_cursor_legacy@cursorA-vs-flipA-atomic-transitions-varying-size
1211kms_cursor_legacy@cursorA-vs-flipB-atomic-transitions-varying-size
1212kms_cursor_legacy@cursorB-vs-flipA-atomic-transitions-varying-size
1213kms_cursor_legacy@cursorB-vs-flipB-atomic-transitions-varying-size
1214kms_dither@fb-8bpc-vs-panel-6bpc
1215kms_dither@fb-8bpc-vs-panel-8bpc
1216kms_dp_aux_dev
1217kms_tiled_display@basic-test-pattern
1218kms_tiled_display@basic-test-pattern-with-chamelium
1219kms_draw_crc@draw-method-mmap-cpu
1220kms_draw_crc@draw-method-mmap-gtt
1221kms_draw_crc@draw-method-mmap-wc
1222kms_draw_crc@draw-method-pwrite
1223kms_draw_crc@draw-method-blt
1224kms_draw_crc@draw-method-render
1225kms_draw_crc@fill-fb
1226kms_dsc@dsc-basic
1227kms_dsc@dsc-with-formats
1228kms_dsc@dsc-with-bpc
1229kms_dsc@dsc-with-bpc-formats
1230kms_dsc@dsc-with-output-formats
1231kms_fbcon_fbt@fbc
1232kms_fbcon_fbt@psr
1233kms_fbcon_fbt@fbc-suspend
1234kms_fbcon_fbt@psr-suspend
1235kms_fence_pin_leak
1236kms_flip@nonblocking-read
1237kms_flip@wf_vblank-ts-check
1238kms_flip@2x-wf_vblank-ts-check
1239kms_flip@blocking-wf_vblank
1240kms_flip@2x-blocking-wf_vblank
1241kms_flip@absolute-wf_vblank
1242kms_flip@2x-absolute-wf_vblank
1243kms_flip@blocking-absolute-wf_vblank
1244kms_flip@2x-blocking-absolute-wf_vblank
1245kms_flip@basic-plain-flip
1246kms_flip@2x-plain-flip
1247kms_flip@busy-flip
1248kms_flip@2x-busy-flip
1249kms_flip@flip-vs-fences
1250kms_flip@2x-flip-vs-fences
1251kms_flip@plain-flip-ts-check
1252kms_flip@2x-plain-flip-ts-check
1253kms_flip@plain-flip-fb-recreate
1254kms_flip@2x-plain-flip-fb-recreate
1255kms_flip@flip-vs-rmfb
1256kms_flip@2x-flip-vs-rmfb
1257kms_flip@basic-flip-vs-dpms
1258kms_flip@2x-flip-vs-dpms
1259kms_flip@flip-vs-panning
1260kms_flip@2x-flip-vs-panning
1261kms_flip@basic-flip-vs-modeset
1262kms_flip@2x-flip-vs-modeset
1263kms_flip@flip-vs-expired-vblank
1264kms_flip@2x-flip-vs-expired-vblank
1265kms_flip@flip-vs-absolute-wf_vblank
1266kms_flip@2x-flip-vs-absolute-wf_vblank
1267kms_flip@basic-flip-vs-wf_vblank
1268kms_flip@2x-flip-vs-wf_vblank
1269kms_flip@flip-vs-blocking-wf-vblank
1270kms_flip@2x-flip-vs-blocking-wf-vblank
1271kms_flip@flip-vs-modeset-vs-hang
1272kms_flip@2x-flip-vs-modeset-vs-hang
1273kms_flip@flip-vs-panning-vs-hang
1274kms_flip@2x-flip-vs-panning-vs-hang
1275kms_flip@flip-vs-dpms-off-vs-modeset
1276kms_flip@2x-flip-vs-dpms-off-vs-modeset
1277kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset
1278kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset
1279kms_flip@dpms-off-confusion
1280kms_flip@nonexisting-fb
1281kms_flip@2x-nonexisting-fb
1282kms_flip@dpms-vs-vblank-race
1283kms_flip@2x-dpms-vs-vblank-race
1284kms_flip@modeset-vs-vblank-race
1285kms_flip@2x-modeset-vs-vblank-race
1286kms_flip@bo-too-big
1287kms_flip@flip-vs-suspend
1288kms_flip@2x-flip-vs-suspend
1289kms_flip@wf_vblank-ts-check-interruptible
1290kms_flip@2x-wf_vblank-ts-check-interruptible
1291kms_flip@absolute-wf_vblank-interruptible
1292kms_flip@2x-absolute-wf_vblank-interruptible
1293kms_flip@blocking-absolute-wf_vblank-interruptible
1294kms_flip@2x-blocking-absolute-wf_vblank-interruptible
1295kms_flip@plain-flip-interruptible
1296kms_flip@2x-plain-flip-interruptible
1297kms_flip@flip-vs-fences-interruptible
1298kms_flip@2x-flip-vs-fences-interruptible
1299kms_flip@plain-flip-ts-check-interruptible
1300kms_flip@2x-plain-flip-ts-check-interruptible
1301kms_flip@plain-flip-fb-recreate-interruptible
1302kms_flip@2x-plain-flip-fb-recreate-interruptible
1303kms_flip@flip-vs-rmfb-interruptible
1304kms_flip@2x-flip-vs-rmfb-interruptible
1305kms_flip@flip-vs-panning-interruptible
1306kms_flip@2x-flip-vs-panning-interruptible
1307kms_flip@flip-vs-expired-vblank-interruptible
1308kms_flip@2x-flip-vs-expired-vblank-interruptible
1309kms_flip@flip-vs-absolute-wf_vblank-interruptible
1310kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible
1311kms_flip@flip-vs-wf_vblank-interruptible
1312kms_flip@2x-flip-vs-wf_vblank-interruptible
1313kms_flip@flip-vs-dpms-off-vs-modeset-interruptible
1314kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible
1315kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible
1316kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible
1317kms_flip@dpms-off-confusion-interruptible
1318kms_flip@nonexisting-fb-interruptible
1319kms_flip@2x-nonexisting-fb-interruptible
1320kms_flip@dpms-vs-vblank-race-interruptible
1321kms_flip@2x-dpms-vs-vblank-race-interruptible
1322kms_flip@modeset-vs-vblank-race-interruptible
1323kms_flip@2x-modeset-vs-vblank-race-interruptible
1324kms_flip@bo-too-big-interruptible
1325kms_flip@flip-vs-suspend-interruptible
1326kms_flip@2x-flip-vs-suspend-interruptible
1327kms_flip_event_leak@basic
1328kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling
1329kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling
1330kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling
1331kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling
1332kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling
1333kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling
1334kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling
1335kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling
1336kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling
1337kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling
1338kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling
1339kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling
1340kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling
1341kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling
1342kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling
1343kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling
1344kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling
1345kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling
1346kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling
1347kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling
1348kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling
1349kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling
1350kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling
1351kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling
1352kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling
1353kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling
1354kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling
1355kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling
1356kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling
1357kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling
1358kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling
1359kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling
1360kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling
1361kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling
1362kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling
1363kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling
1364kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling
1365kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling
1366kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling
1367kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling
1368kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling
1369kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling
1370kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling
1371kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling
1372kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling
1373kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling
1374kms_force_connector_basic@force-load-detect
1375kms_force_connector_basic@force-connector-state
1376kms_force_connector_basic@force-edid
1377kms_force_connector_basic@prune-stale-modes
1378kms_frontbuffer_tracking@fbc-1p-rte
1379kms_frontbuffer_tracking@fbc-2p-rte
1380kms_frontbuffer_tracking@psr-1p-rte
1381kms_frontbuffer_tracking@psr-2p-rte
1382kms_frontbuffer_tracking@fbcpsr-1p-rte
1383kms_frontbuffer_tracking@fbcpsr-2p-rte
1384kms_frontbuffer_tracking@drrs-1p-rte
1385kms_frontbuffer_tracking@drrs-2p-rte
1386kms_frontbuffer_tracking@fbcdrrs-1p-rte
1387kms_frontbuffer_tracking@fbcdrrs-2p-rte
1388kms_frontbuffer_tracking@psrdrrs-1p-rte
1389kms_frontbuffer_tracking@psrdrrs-2p-rte
1390kms_frontbuffer_tracking@fbcpsrdrrs-1p-rte
1391kms_frontbuffer_tracking@fbcpsrdrrs-2p-rte
1392kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu
1393kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt
1394kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc
1395kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite
1396kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt
1397kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render
1398kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu
1399kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt
1400kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc
1401kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite
1402kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt
1403kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render
1404kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu
1405kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt
1406kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc
1407kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite
1408kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt
1409kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render
1410kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu
1411kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt
1412kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc
1413kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite
1414kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt
1415kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render
1416kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu
1417kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt
1418kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc
1419kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite
1420kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt
1421kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render
1422kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu
1423kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt
1424kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc
1425kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite
1426kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt
1427kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render
1428kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-cpu
1429kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt
1430kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc
1431kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite
1432kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt
1433kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render
1434kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu
1435kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt
1436kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc
1437kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-pwrite
1438kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt
1439kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render
1440kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu
1441kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt
1442kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc
1443kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite
1444kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt
1445kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render
1446kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu
1447kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt
1448kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc
1449kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite
1450kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt
1451kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render
1452kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu
1453kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt
1454kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc
1455kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite
1456kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt
1457kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render
1458kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-cpu
1459kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt
1460kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc
1461kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-pwrite
1462kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt
1463kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render
1464kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu
1465kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt
1466kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc
1467kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite
1468kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt
1469kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render
1470kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu
1471kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt
1472kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc
1473kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite
1474kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt
1475kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render
1476kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu
1477kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt
1478kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc
1479kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite
1480kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt
1481kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render
1482kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-cpu
1483kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt
1484kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc
1485kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite
1486kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt
1487kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render
1488kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu
1489kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt
1490kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc
1491kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite
1492kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt
1493kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render
1494kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu
1495kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt
1496kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc
1497kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite
1498kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt
1499kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render
1500kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu
1501kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt
1502kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc
1503kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite
1504kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt
1505kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render
1506kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu
1507kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt
1508kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc
1509kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite
1510kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt
1511kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render
1512kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu
1513kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt
1514kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc
1515kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-pwrite
1516kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt
1517kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render
1518kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu
1519kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt
1520kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc
1521kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-pwrite
1522kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt
1523kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render
1524kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu
1525kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt
1526kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc
1527kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-pwrite
1528kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt
1529kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render
1530kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-cpu
1531kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt
1532kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc
1533kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-pwrite
1534kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-blt
1535kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render
1536kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-cpu
1537kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-gtt
1538kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc
1539kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite
1540kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt
1541kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render
1542kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu
1543kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt
1544kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc
1545kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite
1546kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt
1547kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render
1548kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-cpu
1549kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt
1550kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc
1551kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite
1552kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt
1553kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render
1554kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-cpu
1555kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-gtt
1556kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc
1557kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite
1558kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt
1559kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render
1560kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu
1561kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt
1562kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc
1563kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite
1564kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt
1565kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render
1566kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu
1567kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt
1568kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc
1569kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite
1570kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt
1571kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render
1572kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu
1573kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt
1574kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc
1575kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite
1576kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt
1577kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render
1578kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-cpu
1579kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt
1580kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc
1581kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite
1582kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt
1583kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render
1584kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu
1585kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt
1586kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc
1587kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite
1588kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt
1589kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render
1590kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu
1591kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt
1592kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc
1593kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite
1594kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt
1595kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render
1596kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-cpu
1597kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt
1598kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc
1599kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite
1600kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt
1601kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render
1602kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu
1603kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt
1604kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc
1605kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-pwrite
1606kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt
1607kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render
1608kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu
1609kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt
1610kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc
1611kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-pwrite
1612kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt
1613kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render
1614kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu
1615kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt
1616kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc
1617kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite
1618kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt
1619kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-render
1620kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-cpu
1621kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt
1622kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc
1623kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite
1624kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt
1625kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render
1626kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu
1627kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt
1628kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc
1629kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite
1630kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt
1631kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-render
1632kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu
1633kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt
1634kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc
1635kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-pwrite
1636kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt
1637kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-render
1638kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-cpu
1639kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt
1640kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc
1641kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite
1642kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt
1643kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render
1644kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-cpu
1645kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-gtt
1646kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-wc
1647kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-pwrite
1648kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-blt
1649kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render
1650kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-cpu
1651kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-gtt
1652kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-wc
1653kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-pwrite
1654kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-blt
1655kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render
1656kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-cpu
1657kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-gtt
1658kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-wc
1659kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-pwrite
1660kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt
1661kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render
1662kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-cpu
1663kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-gtt
1664kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-wc
1665kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-pwrite
1666kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt
1667kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-render
1668kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-cpu
1669kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-gtt
1670kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-wc
1671kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-pwrite
1672kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt
1673kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-render
1674kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-cpu
1675kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-gtt
1676kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-wc
1677kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-pwrite
1678kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-blt
1679kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-render
1680kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-cpu
1681kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-gtt
1682kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc
1683kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-pwrite
1684kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt
1685kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-render
1686kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-mmap-cpu
1687kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-mmap-gtt
1688kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-mmap-wc
1689kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-pwrite
1690kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt
1691kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-render
1692kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-cpu
1693kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-gtt
1694kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc
1695kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-pwrite
1696kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt
1697kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render
1698kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-cpu
1699kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-gtt
1700kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-wc
1701kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-pwrite
1702kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt
1703kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render
1704kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-cpu
1705kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-gtt
1706kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc
1707kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-pwrite
1708kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt
1709kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-render
1710kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu
1711kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt
1712kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc
1713kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-pwrite
1714kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-blt
1715kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render
1716kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-cpu
1717kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-gtt
1718kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-wc
1719kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-pwrite
1720kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-blt
1721kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-render
1722kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-cpu
1723kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-gtt
1724kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-wc
1725kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-pwrite
1726kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt
1727kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-render
1728kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-mmap-cpu
1729kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-mmap-gtt
1730kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-mmap-wc
1731kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-pwrite
1732kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-blt
1733kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-render
1734kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-cpu
1735kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-gtt
1736kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc
1737kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-pwrite
1738kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-blt
1739kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-render
1740kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-mmap-cpu
1741kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-mmap-gtt
1742kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-mmap-wc
1743kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-pwrite
1744kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-blt
1745kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render
1746kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-mmap-cpu
1747kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-mmap-gtt
1748kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-mmap-wc
1749kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-pwrite
1750kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-blt
1751kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-render
1752kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-mmap-cpu
1753kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-mmap-gtt
1754kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-mmap-wc
1755kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-pwrite
1756kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-blt
1757kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-render
1758kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-mmap-cpu
1759kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-mmap-gtt
1760kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-mmap-wc
1761kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-pwrite
1762kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-blt
1763kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-render
1764kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-cpu
1765kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-gtt
1766kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc
1767kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-pwrite
1768kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt
1769kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-render
1770kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-mmap-cpu
1771kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-mmap-gtt
1772kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-mmap-wc
1773kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-pwrite
1774kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt
1775kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render
1776kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-cpu
1777kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-gtt
1778kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-wc
1779kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-pwrite
1780kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-blt
1781kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-render
1782kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-mmap-cpu
1783kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-mmap-gtt
1784kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-mmap-wc
1785kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-pwrite
1786kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-blt
1787kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render
1788kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-mmap-cpu
1789kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-mmap-gtt
1790kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-mmap-wc
1791kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-pwrite
1792kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-blt
1793kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-render
1794kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu
1795kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt
1796kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc
1797kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-pwrite
1798kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-blt
1799kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render
1800kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-cpu
1801kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-gtt
1802kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc
1803kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-pwrite
1804kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt
1805kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-render
1806kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-cpu
1807kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-gtt
1808kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc
1809kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-pwrite
1810kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt
1811kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-render
1812kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-mmap-cpu
1813kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-mmap-gtt
1814kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-mmap-wc
1815kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-pwrite
1816kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-blt
1817kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-render
1818kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-mmap-cpu
1819kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-mmap-gtt
1820kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc
1821kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-pwrite
1822kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-blt
1823kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-render
1824kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-mmap-cpu
1825kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-mmap-gtt
1826kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-mmap-wc
1827kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-pwrite
1828kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-blt
1829kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-render
1830kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-mmap-cpu
1831kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-mmap-gtt
1832kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-mmap-wc
1833kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-pwrite
1834kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-blt
1835kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-render
1836kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-mmap-cpu
1837kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-mmap-gtt
1838kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-mmap-wc
1839kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-pwrite
1840kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-blt
1841kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-render
1842kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-mmap-cpu
1843kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-mmap-gtt
1844kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-mmap-wc
1845kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-pwrite
1846kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-blt
1847kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-render
1848kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-mmap-cpu
1849kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-mmap-gtt
1850kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-mmap-wc
1851kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-pwrite
1852kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-blt
1853kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-render
1854kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-mmap-cpu
1855kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-mmap-gtt
1856kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-mmap-wc
1857kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-pwrite
1858kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-blt
1859kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-render
1860kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-mmap-cpu
1861kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-mmap-gtt
1862kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-mmap-wc
1863kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-pwrite
1864kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-blt
1865kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-render
1866kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-mmap-cpu
1867kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-mmap-gtt
1868kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-mmap-wc
1869kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-pwrite
1870kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-blt
1871kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-render
1872kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-mmap-cpu
1873kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-mmap-gtt
1874kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-mmap-wc
1875kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-pwrite
1876kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-blt
1877kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-render
1878kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu
1879kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt
1880kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc
1881kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-pwrite
1882kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-blt
1883kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-render
1884kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-mmap-cpu
1885kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-mmap-gtt
1886kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc
1887kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-pwrite
1888kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-blt
1889kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-render
1890kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-mmap-cpu
1891kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-mmap-gtt
1892kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc
1893kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-pwrite
1894kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-blt
1895kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-render
1896kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-mmap-cpu
1897kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-mmap-gtt
1898kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-mmap-wc
1899kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-pwrite
1900kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-blt
1901kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-render
1902kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-mmap-cpu
1903kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-mmap-gtt
1904kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc
1905kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-pwrite
1906kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-blt
1907kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-render
1908kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-mmap-cpu
1909kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-mmap-gtt
1910kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-mmap-wc
1911kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-pwrite
1912kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-blt
1913kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-render
1914kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-mmap-cpu
1915kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-mmap-gtt
1916kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-mmap-wc
1917kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-pwrite
1918kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-blt
1919kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-render
1920kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-mmap-cpu
1921kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-mmap-gtt
1922kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-mmap-wc
1923kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-pwrite
1924kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-blt
1925kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-render
1926kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-mmap-cpu
1927kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-mmap-gtt
1928kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-mmap-wc
1929kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-pwrite
1930kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-blt
1931kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-render
1932kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-mmap-cpu
1933kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-mmap-gtt
1934kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-mmap-wc
1935kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-pwrite
1936kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-blt
1937kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-render
1938kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-mmap-cpu
1939kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-mmap-gtt
1940kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-mmap-wc
1941kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-pwrite
1942kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-blt
1943kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-render
1944kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-mmap-cpu
1945kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-mmap-gtt
1946kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-mmap-wc
1947kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-pwrite
1948kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-blt
1949kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-render
1950kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-mmap-cpu
1951kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-mmap-gtt
1952kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-mmap-wc
1953kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-pwrite
1954kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-blt
1955kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-render
1956kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-mmap-cpu
1957kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-mmap-gtt
1958kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-mmap-wc
1959kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-pwrite
1960kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-blt
1961kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-render
1962kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu
1963kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt
1964kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc
1965kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-pwrite
1966kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-blt
1967kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-render
1968kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-mmap-cpu
1969kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-mmap-gtt
1970kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc
1971kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-pwrite
1972kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-blt
1973kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-render
1974kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-mmap-cpu
1975kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-mmap-gtt
1976kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc
1977kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-pwrite
1978kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-blt
1979kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-render
1980kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt
1981kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt
1982kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt
1983kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt
1984kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt
1985kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt
1986kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt
1987kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt
1988kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt
1989kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt
1990kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt
1991kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt
1992kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt
1993kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt
1994kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt
1995kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt
1996kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt
1997kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt
1998kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt
1999kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt
2000kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt
2001kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt
2002kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt
2003kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt
2004kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt
2005kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt
2006kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt
2007kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt
2008kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt
2009kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt
2010kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-pgflip-blt
2011kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt
2012kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt
2013kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt
2014kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt
2015kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt
2016kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt
2017kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt
2018kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt
2019kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt
2020kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt
2021kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt
2022kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt
2023kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-msflip-blt
2024kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt
2025kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt
2026kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt
2027kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt
2028kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt
2029kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt
2030kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt
2031kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt
2032kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt
2033kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt
2034kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-pgflip-blt
2035kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-msflip-blt
2036kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-plflip-blt
2037kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-pgflip-blt
2038kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt
2039kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-plflip-blt
2040kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt
2041kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-msflip-blt
2042kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt
2043kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-pgflip-blt
2044kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt
2045kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-plflip-blt
2046kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt
2047kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-msflip-blt
2048kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-plflip-blt
2049kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-pgflip-blt
2050kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt
2051kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt
2052kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-pgflip-blt
2053kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt
2054kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-plflip-blt
2055kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-pgflip-blt
2056kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-msflip-blt
2057kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-plflip-blt
2058kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-pgflip-blt
2059kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-msflip-blt
2060kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt
2061kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-pgflip-blt
2062kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-msflip-blt
2063kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt
2064kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt
2065kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-msflip-blt
2066kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-plflip-blt
2067kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt
2068kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt
2069kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt
2070kms_frontbuffer_tracking@psrdrrs-1p-primscrn-indfb-pgflip-blt
2071kms_frontbuffer_tracking@psrdrrs-1p-primscrn-indfb-msflip-blt
2072kms_frontbuffer_tracking@psrdrrs-1p-primscrn-indfb-plflip-blt
2073kms_frontbuffer_tracking@psrdrrs-1p-primscrn-shrfb-pgflip-blt
2074kms_frontbuffer_tracking@psrdrrs-1p-primscrn-shrfb-msflip-blt
2075kms_frontbuffer_tracking@psrdrrs-1p-primscrn-shrfb-plflip-blt
2076kms_frontbuffer_tracking@psrdrrs-2p-primscrn-indfb-pgflip-blt
2077kms_frontbuffer_tracking@psrdrrs-2p-primscrn-indfb-msflip-blt
2078kms_frontbuffer_tracking@psrdrrs-2p-primscrn-indfb-plflip-blt
2079kms_frontbuffer_tracking@psrdrrs-2p-primscrn-shrfb-pgflip-blt
2080kms_frontbuffer_tracking@psrdrrs-2p-primscrn-shrfb-msflip-blt
2081kms_frontbuffer_tracking@psrdrrs-2p-primscrn-shrfb-plflip-blt
2082kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-indfb-pgflip-blt
2083kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-indfb-msflip-blt
2084kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-indfb-plflip-blt
2085kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-shrfb-pgflip-blt
2086kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-shrfb-msflip-blt
2087kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-shrfb-plflip-blt
2088kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-indfb-pgflip-blt
2089kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-indfb-msflip-blt
2090kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-indfb-plflip-blt
2091kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-shrfb-pgflip-blt
2092kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-shrfb-msflip-blt
2093kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-shrfb-plflip-blt
2094kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-indfb-pgflip-blt
2095kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-indfb-msflip-blt
2096kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-indfb-plflip-blt
2097kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-shrfb-pgflip-blt
2098kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-shrfb-msflip-blt
2099kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-shrfb-plflip-blt
2100kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-indfb-pgflip-blt
2101kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-indfb-msflip-blt
2102kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-indfb-plflip-blt
2103kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-shrfb-pgflip-blt
2104kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-shrfb-msflip-blt
2105kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-shrfb-plflip-blt
2106kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt
2107kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt
2108kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt
2109kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt
2110kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt
2111kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt
2112kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt
2113kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt
2114kms_frontbuffer_tracking@fbcdrrs-1p-indfb-fliptrack-mmap-gtt
2115kms_frontbuffer_tracking@fbcdrrs-1p-shrfb-fliptrack-mmap-gtt
2116kms_frontbuffer_tracking@fbcdrrs-2p-indfb-fliptrack-mmap-gtt
2117kms_frontbuffer_tracking@fbcdrrs-2p-shrfb-fliptrack-mmap-gtt
2118kms_frontbuffer_tracking@fbcpsrdrrs-1p-indfb-fliptrack-mmap-gtt
2119kms_frontbuffer_tracking@fbcpsrdrrs-1p-shrfb-fliptrack-mmap-gtt
2120kms_frontbuffer_tracking@fbcpsrdrrs-2p-indfb-fliptrack-mmap-gtt
2121kms_frontbuffer_tracking@fbcpsrdrrs-2p-shrfb-fliptrack-mmap-gtt
2122kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move
2123kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff
2124kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move
2125kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff
2126kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move
2127kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff
2128kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move
2129kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff
2130kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move
2131kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff
2132kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move
2133kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff
2134kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move
2135kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff
2136kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move
2137kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff
2138kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move
2139kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff
2140kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move
2141kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff
2142kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move
2143kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-onoff
2144kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move
2145kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-onoff
2146kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move
2147kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff
2148kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move
2149kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff
2150kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move
2151kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff
2152kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move
2153kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff
2154kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move
2155kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff
2156kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move
2157kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff
2158kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-move
2159kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff
2160kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-move
2161kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff
2162kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-move
2163kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff
2164kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move
2165kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-onoff
2166kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-move
2167kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff
2168kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move
2169kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-onoff
2170kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-move
2171kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-onoff
2172kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-move
2173kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff
2174kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move
2175kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-onoff
2176kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-move
2177kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-onoff
2178kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-move
2179kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff
2180kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-move
2181kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-onoff
2182kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-move
2183kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-onoff
2184kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-move
2185kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-onoff
2186kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-move
2187kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-onoff
2188kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-move
2189kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-onoff
2190kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-move
2191kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-onoff
2192kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-move
2193kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-onoff
2194kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-move
2195kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-onoff
2196kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-move
2197kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-onoff
2198kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-move
2199kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-onoff
2200kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-move
2201kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-onoff
2202kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-move
2203kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-onoff
2204kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-move
2205kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-onoff
2206kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen
2207kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen
2208kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen
2209kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen
2210kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen
2211kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-fullscreen
2212kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen
2213kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-fullscreen
2214kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen
2215kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen
2216kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-fullscreen
2217kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen
2218kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen
2219kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-fullscreen
2220kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-fullscreen
2221kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-fullscreen
2222kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-fullscreen
2223kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-fullscreen
2224kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-fullscreen
2225kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-fullscreen
2226kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-fullscreen
2227kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw
2228kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw
2229kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw
2230kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw
2231kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw
2232kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw
2233kms_frontbuffer_tracking@drrs-1p-pri-indfb-multidraw
2234kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw
2235kms_frontbuffer_tracking@fbcdrrs-1p-pri-indfb-multidraw
2236kms_frontbuffer_tracking@fbcdrrs-2p-pri-indfb-multidraw
2237kms_frontbuffer_tracking@psrdrrs-1p-pri-indfb-multidraw
2238kms_frontbuffer_tracking@psrdrrs-2p-pri-indfb-multidraw
2239kms_frontbuffer_tracking@fbcpsrdrrs-1p-pri-indfb-multidraw
2240kms_frontbuffer_tracking@fbcpsrdrrs-2p-pri-indfb-multidraw
2241kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt
2242kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt
2243kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt
2244kms_frontbuffer_tracking@drrs-farfromfence-mmap-gtt
2245kms_frontbuffer_tracking@fbcdrrs-farfromfence-mmap-gtt
2246kms_frontbuffer_tracking@psrdrrs-farfromfence-mmap-gtt
2247kms_frontbuffer_tracking@fbcpsrdrrs-farfromfence-mmap-gtt
2248kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu
2249kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu
2250kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt
2251kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt
2252kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc
2253kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc
2254kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite
2255kms_frontbuffer_tracking@fbc-rgb101010-draw-pwrite
2256kms_frontbuffer_tracking@fbc-rgb565-draw-blt
2257kms_frontbuffer_tracking@fbc-rgb101010-draw-blt
2258kms_frontbuffer_tracking@fbc-rgb565-draw-render
2259kms_frontbuffer_tracking@fbc-rgb101010-draw-render
2260kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu
2261kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu
2262kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt
2263kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt
2264kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc
2265kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc
2266kms_frontbuffer_tracking@psr-rgb565-draw-pwrite
2267kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite
2268kms_frontbuffer_tracking@psr-rgb565-draw-blt
2269kms_frontbuffer_tracking@psr-rgb101010-draw-blt
2270kms_frontbuffer_tracking@psr-rgb565-draw-render
2271kms_frontbuffer_tracking@psr-rgb101010-draw-render
2272kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu
2273kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu
2274kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt
2275kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt
2276kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc
2277kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc
2278kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite
2279kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite
2280kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt
2281kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt
2282kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render
2283kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render
2284kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-cpu
2285kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-cpu
2286kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-gtt
2287kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-gtt
2288kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-wc
2289kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc
2290kms_frontbuffer_tracking@drrs-rgb565-draw-pwrite
2291kms_frontbuffer_tracking@drrs-rgb101010-draw-pwrite
2292kms_frontbuffer_tracking@drrs-rgb565-draw-blt
2293kms_frontbuffer_tracking@drrs-rgb101010-draw-blt
2294kms_frontbuffer_tracking@drrs-rgb565-draw-render
2295kms_frontbuffer_tracking@drrs-rgb101010-draw-render
2296kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-mmap-cpu
2297kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-cpu
2298kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-mmap-gtt
2299kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-gtt
2300kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-mmap-wc
2301kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc
2302kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-pwrite
2303kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-pwrite
2304kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-blt
2305kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt
2306kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-render
2307kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-render
2308kms_frontbuffer_tracking@psrdrrs-rgb565-draw-mmap-cpu
2309kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-mmap-cpu
2310kms_frontbuffer_tracking@psrdrrs-rgb565-draw-mmap-gtt
2311kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-mmap-gtt
2312kms_frontbuffer_tracking@psrdrrs-rgb565-draw-mmap-wc
2313kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-mmap-wc
2314kms_frontbuffer_tracking@psrdrrs-rgb565-draw-pwrite
2315kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-pwrite
2316kms_frontbuffer_tracking@psrdrrs-rgb565-draw-blt
2317kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-blt
2318kms_frontbuffer_tracking@psrdrrs-rgb565-draw-render
2319kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-render
2320kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-mmap-cpu
2321kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-mmap-cpu
2322kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-mmap-gtt
2323kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-mmap-gtt
2324kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-mmap-wc
2325kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-mmap-wc
2326kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-pwrite
2327kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-pwrite
2328kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-blt
2329kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-blt
2330kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-render
2331kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-render
2332kms_frontbuffer_tracking@fbc-indfb-scaledprimary
2333kms_frontbuffer_tracking@fbc-shrfb-scaledprimary
2334kms_frontbuffer_tracking@psr-indfb-scaledprimary
2335kms_frontbuffer_tracking@psr-shrfb-scaledprimary
2336kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary
2337kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary
2338kms_frontbuffer_tracking@drrs-indfb-scaledprimary
2339kms_frontbuffer_tracking@drrs-shrfb-scaledprimary
2340kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary
2341kms_frontbuffer_tracking@fbcdrrs-shrfb-scaledprimary
2342kms_frontbuffer_tracking@psrdrrs-indfb-scaledprimary
2343kms_frontbuffer_tracking@psrdrrs-shrfb-scaledprimary
2344kms_frontbuffer_tracking@fbcpsrdrrs-indfb-scaledprimary
2345kms_frontbuffer_tracking@fbcpsrdrrs-shrfb-scaledprimary
2346kms_frontbuffer_tracking@fbc-modesetfrombusy
2347kms_frontbuffer_tracking@fbc-stridechange
2348kms_frontbuffer_tracking@fbc-tiling-linear
2349kms_frontbuffer_tracking@fbc-tiling-y
2350kms_frontbuffer_tracking@fbc-tiling-4
2351kms_frontbuffer_tracking@fbc-suspend
2352kms_frontbuffer_tracking@psr-modesetfrombusy
2353kms_frontbuffer_tracking@psr-slowdraw
2354kms_frontbuffer_tracking@psr-suspend
2355kms_frontbuffer_tracking@fbcpsr-modesetfrombusy
2356kms_frontbuffer_tracking@fbcpsr-stridechange
2357kms_frontbuffer_tracking@fbcpsr-tiling-linear
2358kms_frontbuffer_tracking@fbcpsr-tiling-y
2359kms_frontbuffer_tracking@fbcpsr-tiling-4
2360kms_frontbuffer_tracking@fbcpsr-slowdraw
2361kms_frontbuffer_tracking@fbcpsr-suspend
2362kms_frontbuffer_tracking@drrs-modesetfrombusy
2363kms_frontbuffer_tracking@drrs-slowdraw
2364kms_frontbuffer_tracking@drrs-suspend
2365kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy
2366kms_frontbuffer_tracking@fbcdrrs-stridechange
2367kms_frontbuffer_tracking@fbcdrrs-tiling-linear
2368kms_frontbuffer_tracking@fbcdrrs-tiling-y
2369kms_frontbuffer_tracking@fbcdrrs-tiling-4
2370kms_frontbuffer_tracking@fbcdrrs-slowdraw
2371kms_frontbuffer_tracking@fbcdrrs-suspend
2372kms_frontbuffer_tracking@psrdrrs-modesetfrombusy
2373kms_frontbuffer_tracking@psrdrrs-slowdraw
2374kms_frontbuffer_tracking@psrdrrs-suspend
2375kms_frontbuffer_tracking@fbcpsrdrrs-modesetfrombusy
2376kms_frontbuffer_tracking@fbcpsrdrrs-stridechange
2377kms_frontbuffer_tracking@fbcpsrdrrs-tiling-linear
2378kms_frontbuffer_tracking@fbcpsrdrrs-tiling-y
2379kms_frontbuffer_tracking@fbcpsrdrrs-tiling-4
2380kms_frontbuffer_tracking@fbcpsrdrrs-slowdraw
2381kms_frontbuffer_tracking@fbcpsrdrrs-suspend
2382kms_frontbuffer_tracking@basic
2383kms_getfb@getfb-handle-zero
2384kms_getfb@getfb-handle-valid
2385kms_getfb@getfb-handle-closed
2386kms_getfb@getfb-handle-not-fb
2387kms_getfb@getfb-addfb-different-handles
2388kms_getfb@getfb-repeated-different-handles
2389kms_getfb@getfb-reject-ccs
2390kms_getfb@getfb2-handle-zero
2391kms_getfb@getfb2-handle-closed
2392kms_getfb@getfb2-handle-not-fb
2393kms_getfb@getfb2-accept-ccs
2394kms_getfb@getfb2-into-addfb2
2395kms_getfb@getfb-handle-protection
2396kms_getfb@getfb2-handle-protection
2397kms_hdmi_inject@inject-4k
2398kms_hdmi_inject@inject-audio
2399kms_hdr@bpc-switch
2400kms_hdr@bpc-switch-dpms
2401kms_hdr@bpc-switch-suspend
2402kms_hdr@static-toggle
2403kms_hdr@static-toggle-dpms
2404kms_hdr@static-toggle-suspend
2405kms_hdr@static-swap
2406kms_hdr@invalid-metadata-sizes
2407kms_hdr@invalid-hdr
2408kms_invalid_mode@clock-too-high
2409kms_invalid_mode@zero-clock
2410kms_invalid_mode@int-max-clock
2411kms_invalid_mode@uint-max-clock
2412kms_invalid_mode@zero-hdisplay
2413kms_invalid_mode@zero-vdisplay
2414kms_invalid_mode@bad-hsync-start
2415kms_invalid_mode@bad-vsync-start
2416kms_invalid_mode@bad-hsync-end
2417kms_invalid_mode@bad-vsync-end
2418kms_invalid_mode@bad-htotal
2419kms_invalid_mode@bad-vtotal
2420kms_legacy_colorkey@basic
2421kms_legacy_colorkey@invalid-plane
2422kms_multipipe_modeset@basic-max-pipe-crc-check
2423kms_panel_fitting@legacy
2424kms_panel_fitting@atomic-fastset
2425kms_pipe_b_c_ivb@pipe-B-dpms-off-modeset-pipe-C
2426kms_pipe_b_c_ivb@pipe-B-double-modeset-then-modeset-pipe-C
2427kms_pipe_b_c_ivb@disable-pipe-B-enable-pipe-C
2428kms_pipe_b_c_ivb@from-pipe-C-to-B-with-3-lanes
2429kms_pipe_b_c_ivb@enable-pipe-C-while-B-has-3-lanes
2430kms_pipe_crc_basic@bad-source
2431kms_pipe_crc_basic@read-crc
2432kms_pipe_crc_basic@read-crc-frame-sequence
2433kms_pipe_crc_basic@nonblocking-crc
2434kms_pipe_crc_basic@nonblocking-crc-frame-sequence
2435kms_pipe_crc_basic@suspend-read-crc
2436kms_pipe_crc_basic@hang-read-crc
2437kms_pipe_crc_basic@disable-crc-after-crtc
2438kms_pipe_crc_basic@compare-crc-sanitycheck-xr24
2439kms_pipe_crc_basic@compare-crc-sanitycheck-nv12
2440kms_plane@pixel-format
2441kms_plane@pixel-format-source-clamping
2442kms_plane@plane-position-covered
2443kms_plane@plane-position-hole
2444kms_plane@plane-position-hole-dpms
2445kms_plane@plane-panning-top-left
2446kms_plane@plane-panning-bottom-right
2447kms_plane@plane-panning-bottom-right-suspend
2448kms_plane@planar-pixel-format-settings
2449kms_plane_alpha_blend@alpha-basic
2450kms_plane_alpha_blend@alpha-7efc
2451kms_plane_alpha_blend@coverage-7efc
2452kms_plane_alpha_blend@coverage-vs-premult-vs-constant
2453kms_plane_alpha_blend@alpha-transparent-fb
2454kms_plane_alpha_blend@alpha-opaque-fb
2455kms_plane_alpha_blend@constant-alpha-min
2456kms_plane_alpha_blend@constant-alpha-mid
2457kms_plane_alpha_blend@constant-alpha-max
2458kms_plane_cursor@primary
2459kms_plane_cursor@overlay
2460kms_plane_cursor@viewport
2461kms_plane_lowres@tiling-none
2462kms_plane_lowres@tiling-x
2463kms_plane_lowres@tiling-y
2464kms_plane_lowres@tiling-yf
2465kms_plane_lowres@tiling-4
2466kms_plane_multiple@tiling-none
2467kms_plane_multiple@tiling-x
2468kms_plane_multiple@tiling-y
2469kms_plane_multiple@tiling-yf
2470kms_plane_multiple@tiling-4
2471kms_plane_scaling@plane-upscale-20x20-with-pixel-format
2472kms_plane_scaling@plane-upscale-factor-0-25-with-pixel-format
2473kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format
2474kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format
2475kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format
2476kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format
2477kms_plane_scaling@plane-upscale-20x20-with-rotation
2478kms_plane_scaling@plane-upscale-factor-0-25-with-rotation
2479kms_plane_scaling@plane-downscale-factor-0-25-with-rotation
2480kms_plane_scaling@plane-downscale-factor-0-5-with-rotation
2481kms_plane_scaling@plane-downscale-factor-0-75-with-rotation
2482kms_plane_scaling@plane-scaler-unity-scaling-with-rotation
2483kms_plane_scaling@plane-upscale-20x20-with-modifiers
2484kms_plane_scaling@plane-upscale-factor-0-25-with-modifiers
2485kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers
2486kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers
2487kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers
2488kms_plane_scaling@plane-scaler-unity-scaling-with-modifiers
2489kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats
2490kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation
2491kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers
2492kms_plane_scaling@planes-upscale-20x20
2493kms_plane_scaling@planes-upscale-factor-0-25
2494kms_plane_scaling@planes-scaler-unity-scaling
2495kms_plane_scaling@planes-downscale-factor-0-25
2496kms_plane_scaling@planes-downscale-factor-0-5
2497kms_plane_scaling@planes-downscale-factor-0-75
2498kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25
2499kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5
2500kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75
2501kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25
2502kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5
2503kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75
2504kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25
2505kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5
2506kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75
2507kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20
2508kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25
2509kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling
2510kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20
2511kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25
2512kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling
2513kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20
2514kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25
2515kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling
2516kms_plane_scaling@intel-max-src-size
2517kms_plane_scaling@invalid-num-scalers
2518kms_plane_scaling@invalid-parameters
2519kms_plane_scaling@2x-scaler-multi-pipe
2520kms_prime@basic-crc-hybrid
2521kms_prime@basic-modeset-hybrid
2522kms_prime@D3hot
2523kms_prime@basic-crc-vgem
2524kms_prop_blob@basic
2525kms_prop_blob@blob-prop-core
2526kms_prop_blob@blob-prop-validate
2527kms_prop_blob@blob-prop-lifetime
2528kms_prop_blob@blob-multiple
2529kms_prop_blob@invalid-get-prop-any
2530kms_prop_blob@invalid-get-prop
2531kms_prop_blob@invalid-set-prop-any
2532kms_prop_blob@invalid-set-prop
2533kms_properties@plane-properties-legacy
2534kms_properties@plane-properties-atomic
2535kms_properties@crtc-properties-legacy
2536kms_properties@crtc-properties-atomic
2537kms_properties@connector-properties-legacy
2538kms_properties@connector-properties-atomic
2539kms_properties@invalid-properties-legacy
2540kms_properties@invalid-properties-atomic
2541kms_properties@get_properties-sanity-atomic
2542kms_properties@get_properties-sanity-non-atomic
2543kms_psr@pr-basic
2544kms_psr@pr-no-drrs
2545kms_psr@pr-primary-page-flip
2546kms_psr@pr-primary-mmap-gtt
2547kms_psr@pr-primary-mmap-cpu
2548kms_psr@pr-primary-blt
2549kms_psr@pr-primary-render
2550kms_psr@pr-sprite-mmap-gtt
2551kms_psr@pr-cursor-mmap-gtt
2552kms_psr@pr-sprite-mmap-cpu
2553kms_psr@pr-cursor-mmap-cpu
2554kms_psr@pr-sprite-blt
2555kms_psr@pr-cursor-blt
2556kms_psr@pr-sprite-render
2557kms_psr@pr-cursor-render
2558kms_psr@pr-sprite-plane-move
2559kms_psr@pr-cursor-plane-move
2560kms_psr@pr-sprite-plane-onoff
2561kms_psr@pr-cursor-plane-onoff
2562kms_psr@pr-dpms
2563kms_psr@pr-suspend
2564kms_psr@psr-basic
2565kms_psr@psr-no-drrs
2566kms_psr@psr-primary-page-flip
2567kms_psr@psr-primary-mmap-gtt
2568kms_psr@psr-primary-mmap-cpu
2569kms_psr@psr-primary-blt
2570kms_psr@psr-primary-render
2571kms_psr@psr-sprite-mmap-gtt
2572kms_psr@psr-cursor-mmap-gtt
2573kms_psr@psr-sprite-mmap-cpu
2574kms_psr@psr-cursor-mmap-cpu
2575kms_psr@psr-sprite-blt
2576kms_psr@psr-cursor-blt
2577kms_psr@psr-sprite-render
2578kms_psr@psr-cursor-render
2579kms_psr@psr-sprite-plane-move
2580kms_psr@psr-cursor-plane-move
2581kms_psr@psr-sprite-plane-onoff
2582kms_psr@psr-cursor-plane-onoff
2583kms_psr@psr-dpms
2584kms_psr@psr-suspend
2585kms_psr@psr2-basic
2586kms_psr@psr2-no-drrs
2587kms_psr@psr2-primary-page-flip
2588kms_psr@psr2-primary-mmap-gtt
2589kms_psr@psr2-primary-mmap-cpu
2590kms_psr@psr2-primary-blt
2591kms_psr@psr2-primary-render
2592kms_psr@psr2-sprite-mmap-gtt
2593kms_psr@psr2-cursor-mmap-gtt
2594kms_psr@psr2-sprite-mmap-cpu
2595kms_psr@psr2-cursor-mmap-cpu
2596kms_psr@psr2-sprite-blt
2597kms_psr@psr2-cursor-blt
2598kms_psr@psr2-sprite-render
2599kms_psr@psr2-cursor-render
2600kms_psr@psr2-sprite-plane-move
2601kms_psr@psr2-cursor-plane-move
2602kms_psr@psr2-sprite-plane-onoff
2603kms_psr@psr2-cursor-plane-onoff
2604kms_psr@psr2-dpms
2605kms_psr@psr2-suspend
2606kms_psr2_sf@primary-plane-update-sf-dmg-area
2607kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb
2608kms_psr2_sf@overlay-plane-update-sf-dmg-area
2609kms_psr2_sf@cursor-plane-update-sf
2610kms_psr2_sf@cursor-plane-move-continuous-sf
2611kms_psr2_sf@cursor-plane-move-continuous-exceed-sf
2612kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf
2613kms_psr2_sf@plane-move-sf-dmg-area
2614kms_psr2_sf@overlay-plane-move-continuous-sf
2615kms_psr2_sf@overlay-plane-move-continuous-exceed-sf
2616kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf
2617kms_psr2_sf@overlay-primary-update-sf-dmg-area
2618kms_psr2_sf@overlay-plane-update-continuous-sf
2619kms_psr2_su@page_flip-XRGB8888
2620kms_psr2_su@page_flip-NV12
2621kms_psr2_su@page_flip-P010
2622kms_psr2_su@frontbuffer-XRGB8888
2623kms_pwrite_crc
2624kms_rmfb@rmfb-ioctl
2625kms_rmfb@close-fd
2626kms_rotation_crc@primary-rotation-90
2627kms_rotation_crc@primary-rotation-180
2628kms_rotation_crc@primary-rotation-270
2629kms_rotation_crc@sprite-rotation-90
2630kms_rotation_crc@sprite-rotation-180
2631kms_rotation_crc@sprite-rotation-270
2632kms_rotation_crc@cursor-rotation-180
2633kms_rotation_crc@sprite-rotation-90-pos-100-0
2634kms_rotation_crc@bad-pixel-format
2635kms_rotation_crc@bad-tiling
2636kms_rotation_crc@primary-x-tiled-reflect-x-0
2637kms_rotation_crc@primary-x-tiled-reflect-x-180
2638kms_rotation_crc@primary-y-tiled-reflect-x-0
2639kms_rotation_crc@primary-y-tiled-reflect-x-90
2640kms_rotation_crc@primary-y-tiled-reflect-x-180
2641kms_rotation_crc@primary-y-tiled-reflect-x-270
2642kms_rotation_crc@primary-yf-tiled-reflect-x-0
2643kms_rotation_crc@primary-yf-tiled-reflect-x-90
2644kms_rotation_crc@primary-yf-tiled-reflect-x-180
2645kms_rotation_crc@primary-yf-tiled-reflect-x-270
2646kms_rotation_crc@primary-4-tiled-reflect-x-0
2647kms_rotation_crc@primary-4-tiled-reflect-x-180
2648kms_rotation_crc@multiplane-rotation
2649kms_rotation_crc@multiplane-rotation-cropping-top
2650kms_rotation_crc@multiplane-rotation-cropping-bottom
2651kms_rotation_crc@exhaust-fences
2652kms_scaling_modes@scaling-mode-full
2653kms_scaling_modes@scaling-mode-center
2654kms_scaling_modes@scaling-mode-full-aspect
2655kms_scaling_modes@scaling-mode-none
2656kms_selftest@drm_cmdline_parser
2657kms_selftest@drm_damage_helper
2658kms_selftest@drm_dp_mst_helper
2659kms_selftest@drm_format_helper
2660kms_selftest@drm_format
2661kms_selftest@drm_framebuffer
2662kms_selftest@drm_plane_helper
2663kms_setmode@basic
2664kms_setmode@basic-clone-single-crtc
2665kms_setmode@invalid-clone-single-crtc
2666kms_setmode@invalid-clone-exclusive-crtc
2667kms_setmode@clone-exclusive-crtc
2668kms_setmode@invalid-clone-single-crtc-stealing
2669kms_sysfs_edid_timing
2670kms_tv_load_detect@load-detect
2671kms_universal_plane@universal-plane-functional
2672kms_universal_plane@universal-plane-sanity
2673kms_universal_plane@disable-primary-vs-flip
2674kms_universal_plane@cursor-fb-leak
2675kms_universal_plane@universal-plane-pageflip-windowed
2676kms_vblank@invalid
2677kms_vblank@crtc-id
2678kms_vblank@accuracy-idle
2679kms_vblank@query-idle
2680kms_vblank@query-idle-hang
2681kms_vblank@query-forked
2682kms_vblank@query-forked-hang
2683kms_vblank@query-busy
2684kms_vblank@query-busy-hang
2685kms_vblank@query-forked-busy
2686kms_vblank@query-forked-busy-hang
2687kms_vblank@wait-idle
2688kms_vblank@wait-idle-hang
2689kms_vblank@wait-forked
2690kms_vblank@wait-forked-hang
2691kms_vblank@wait-busy
2692kms_vblank@wait-busy-hang
2693kms_vblank@wait-forked-busy
2694kms_vblank@wait-forked-busy-hang
2695kms_vblank@ts-continuation-idle
2696kms_vblank@ts-continuation-idle-hang
2697kms_vblank@ts-continuation-dpms-rpm
2698kms_vblank@ts-continuation-dpms-suspend
2699kms_vblank@ts-continuation-suspend
2700kms_vblank@ts-continuation-modeset
2701kms_vblank@ts-continuation-modeset-hang
2702kms_vblank@ts-continuation-modeset-rpm
2703kms_vrr@flip-basic
2704kms_vrr@flip-dpms
2705kms_vrr@flip-suspend
2706kms_vrr@flipline
2707kms_vrr@negative-basic
2708kms_writeback@writeback-pixel-formats
2709kms_writeback@writeback-invalid-parameters
2710kms_writeback@writeback-fb-id
2711kms_writeback@writeback-check-output
2712prime_mmap_kms@buffer-sharing
2713msm_shrink@copy-gpu-sanitycheck-8
2714msm_shrink@copy-gpu-sanitycheck-32
2715msm_shrink@copy-gpu-8
2716msm_shrink@copy-gpu-32
2717msm_shrink@copy-gpu-madvise-8
2718msm_shrink@copy-gpu-madvise-32
2719msm_shrink@copy-gpu-oom-8
2720msm_shrink@copy-gpu-oom-32
2721msm_shrink@copy-mmap-sanitycheck-8
2722msm_shrink@copy-mmap-sanitycheck-32
2723msm_shrink@copy-mmap-8
2724msm_shrink@copy-mmap-32
2725msm_shrink@copy-mmap-madvise-8
2726msm_shrink@copy-mmap-madvise-32
2727msm_shrink@copy-mmap-oom-8
2728msm_shrink@copy-mmap-oom-32
2729msm_shrink@copy-mmap-dmabuf-sanitycheck-8
2730msm_shrink@copy-mmap-dmabuf-sanitycheck-32
2731msm_shrink@copy-mmap-dmabuf-8
2732msm_shrink@copy-mmap-dmabuf-32
2733msm_shrink@copy-mmap-dmabuf-madvise-8
2734msm_shrink@copy-mmap-dmabuf-madvise-32
2735msm_shrink@copy-mmap-dmabuf-oom-8
2736msm_shrink@copy-mmap-dmabuf-oom-32
2737msm_mapping@ring
2738msm_mapping@sqefw
2739msm_mapping@shadow
2740msm_submitoverhead@submitbench-10-bos
2741msm_submitoverhead@submitbench-10-bos-no-implicit-sync
2742msm_submitoverhead@submitbench-100-bos
2743msm_submitoverhead@submitbench-100-bos-no-implicit-sync
2744msm_submitoverhead@submitbench-250-bos
2745msm_submitoverhead@submitbench-250-bos-no-implicit-sync
2746msm_submitoverhead@submitbench-500-bos
2747msm_submitoverhead@submitbench-500-bos-no-implicit-sync
2748msm_submitoverhead@submitbench-1000-bos
2749msm_submitoverhead@submitbench-1000-bos-no-implicit-sync
2750msm_recovery@hangcheck
2751msm_recovery@gpu-fault
2752msm_recovery@gpu-fault-parallel
2753msm_recovery@iova-fault
2754msm_submit@empty-submit
2755msm_submit@invalid-queue-submit
2756msm_submit@invalid-flags-submit
2757msm_submit@invalid-in-fence-submit
2758msm_submit@invalid-duplicate-bo-submit
2759msm_submit@invalid-cmd-idx-submit
2760msm_submit@invalid-cmd-type-submit
2761msm_submit@valid-submit
drivers/gpu/drm/ci/x86_64.config+1−0
@@ -24,6 +24,7 @@ CONFIG_DRM=y · 23 unmodified lines
24CONFIG_DRM_PANEL_SIMPLE=y24CONFIG_DRM_PANEL_SIMPLE=y
25CONFIG_PWM_CROS_EC=y25CONFIG_PWM_CROS_EC=y
26CONFIG_BACKLIGHT_PWM=y26CONFIG_BACKLIGHT_PWM=y
27CONFIG_DRM_VKMS=m
27 28
28# Strip out some stuff we don't need for graphics testing, to reduce29# Strip out some stuff we don't need for graphics testing, to reduce
29# the build.30# the build.
drivers/gpu/drm/ci/xfails/amdgpu-stoney-fails.txt+27−14
@@ -1,27 +1,40 @@
1amdgpu/amd_abm@abm_enabled,Fail
2amdgpu/amd_abm@abm_gradual,Fail
3amdgpu/amd_abm@backlight_monotonic_abm,Fail
4amdgpu/amd_abm@backlight_monotonic_basic,Fail
5amdgpu/amd_assr@assr-links,Fail
6amdgpu/amd_assr@assr-links-dpms,Fail
7amdgpu/amd_mall@static-screen,Crash
8amdgpu/amd_mode_switch@mode-switch-first-last-pipe-2,Crash
9amdgpu/amd_plane@mpo-pan-nv12,Fail
10amdgpu/amd_plane@mpo-pan-p010,Fail
11amdgpu/amd_plane@mpo-pan-rgb,Crash
12amdgpu/amd_plane@mpo-scale-nv12,Fail
13amdgpu/amd_plane@mpo-scale-p010,Fail
14amdgpu/amd_plane@mpo-scale-rgb,Crash
15amdgpu/amd_plane@mpo-swizzle-toggle,Fail
16amdgpu/amd_uvd_dec@amdgpu_uvd_decode,Fail
17dumb_buffer@invalid-bpp,Fail
1kms_addfb_basic@bad-pitch-65536,Fail18kms_addfb_basic@bad-pitch-65536,Fail
2kms_addfb_basic@bo-too-small,Fail19kms_addfb_basic@bo-too-small,Fail
3kms_addfb_basic@too-high,Fail20kms_addfb_basic@too-high,Fail
4kms_async_flips@async-flip-with-page-flip-events,Fail
5kms_async_flips@crc,Fail
6kms_async_flips@invalid-async-flip,Fail
7kms_atomic_transition@plane-all-modeset-transition-internal-panels,Fail21kms_atomic_transition@plane-all-modeset-transition-internal-panels,Fail
8kms_atomic_transition@plane-all-transition,Fail22kms_atomic_transition@plane-all-transition,Fail
9kms_atomic_transition@plane-all-transition-nonblocking,Fail23kms_atomic_transition@plane-all-transition-nonblocking,Fail
10kms_atomic_transition@plane-toggle-modeset-transition,Fail24kms_atomic_transition@plane-toggle-modeset-transition,Fail
11kms_atomic_transition@plane-use-after-nonblocking-unbind,Fail25kms_atomic_transition@plane-use-after-nonblocking-unbind,Fail
12kms_bw@linear-tiling-1-displays-2560x1440p,Fail26kms_cursor_crc@cursor-onscreen-64x21,Fail
13kms_bw@linear-tiling-1-displays-3840x2160p,Fail27kms_cursor_crc@cursor-onscreen-64x64,Fail
14kms_bw@linear-tiling-2-displays-3840x2160p,Fail28kms_cursor_crc@cursor-random-64x21,Fail
15kms_bw@linear-tiling-3-displays-1920x1080p,Fail29kms_cursor_crc@cursor-random-64x64,Fail
16kms_color@degamma,Fail
17kms_cursor_crc@cursor-size-change,Fail30kms_cursor_crc@cursor-size-change,Fail
18kms_cursor_crc@pipe-A-cursor-size-change,Fail31kms_cursor_crc@cursor-sliding-64x21,Fail
19kms_cursor_crc@pipe-B-cursor-size-change,Fail32kms_cursor_crc@cursor-sliding-64x64,Fail
20kms_flip@flip-vs-modeset-vs-hang,Fail33kms_flip@flip-vs-modeset-vs-hang,Fail
21kms_flip@flip-vs-panning-vs-hang,Fail34kms_flip@flip-vs-panning-vs-hang,Fail
22kms_hdr@bpc-switch,Fail35kms_lease@lease-uevent,Fail
23kms_hdr@bpc-switch-dpms,Fail
24kms_plane@pixel-format,Fail36kms_plane@pixel-format,Fail
25kms_plane_multiple@atomic-pipe-A-tiling-none,Fail37kms_plane_cursor@primary,Fail
26kms_rmfb@close-fd,Fail
27kms_rotation_crc@primary-rotation-180,Fail38kms_rotation_crc@primary-rotation-180,Fail
39perf@i915-ref-count,Fail
40tools_test@tools_test,Fail
drivers/gpu/drm/ci/xfails/amdgpu-stoney-flakes.txt+7−0
@@ -1 +1,8 @@
1# Board Name: hp-11A-G6-EE-grunt
2# Bug Report: https://lore.kernel.org/amd-gfx/3542730f-b8d7-404d-a947-b7a5e95d661c@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
5# Failure Rate: 50
1kms_async_flips@async-flip-with-page-flip-events6kms_async_flips@async-flip-with-page-flip-events
7kms_async_flips@crc
8kms_plane@pixel-format-source-clamping
drivers/gpu/drm/ci/xfails/amdgpu-stoney-skips.txt+32−1
@@ -1,2 +1,33 @@
1# Suspend to RAM seems to be broken on this machine1# Suspend to RAM seems to be broken on this machine
2.*suspend.*2.*suspend.*
3
4# Skip driver specific tests
5msm_.*
6nouveau_.*
7panfrost_.*
8^v3d.*
9^vc4.*
10^vmwgfx*
11
12# Skip intel specific tests
13gem_.*
14i915_.*
15xe_.*
16
17# Currently fails and causes coverage loss for other tests
18# since core_getversion also fails.
19amdgpu/amd_module_load@reload
20core_hotunplug.*
21
22# GPU reset seen and it hangs the machine
23amdgpu/amd_deadlock@amdgpu-deadlock-sdma
24amdgpu/amd_deadlock@amdgpu-gfx-illegal-reg-access
25amdgpu/amd_dispatch@amdgpu-reset-test-gfx-with-IP-GFX-and-COMPUTE
26
27# Hangs the machine and timeout occurs
28amdgpu/amd_pci_unplug@amdgpu_hotunplug_simple
29amdgpu/amd_pci_unplug@amdgpu_hotunplug_with_cs
30amdgpu/amd_pci_unplug@amdgpu_hotunplug_with_exported_bo
31amdgpu/amd_pci_unplug@amdgpu_hotunplug_with_exported_fence
32amdgpu/amd_vrr_range@freesync-parsing
33device_reset.*
drivers/gpu/drm/ci/xfails/i915-amly-fails.txt+31−0
@@ -1,3 +1,16 @@
1core_setmaster@master-drop-set-user,Fail
2core_setmaster_vs_auth,Fail
3i915_module_load@load,Fail
4i915_module_load@reload,Fail
5i915_module_load@reload-no-display,Fail
6i915_module_load@resize-bar,Fail
7i915_pm_rpm@gem-execbuf-stress,Timeout
8i915_pm_rpm@module-reload,Fail
9kms_async_flips@invalid-async-flip,Timeout
10kms_atomic_transition@modeset-transition-fencing,Timeout
11kms_ccs@crc-primary-rotation-180-yf-tiled-ccs,Timeout
12kms_fb_coherency@memset-crc,Crash
13kms_flip@flip-vs-dpms-off-vs-modeset,Timeout
1kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail14kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail
2kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail15kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail
3kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail16kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail
@@ -20,7 +33,25 @@ kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail · 16 unmodified lines
20kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail33kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
21kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail34kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
22kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail35kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
36kms_lease@lease-uevent,Fail
23kms_plane_alpha_blend@alpha-basic,Fail37kms_plane_alpha_blend@alpha-basic,Fail
24kms_plane_alpha_blend@alpha-opaque-fb,Fail38kms_plane_alpha_blend@alpha-opaque-fb,Fail
25kms_plane_alpha_blend@alpha-transparent-fb,Fail39kms_plane_alpha_blend@alpha-transparent-fb,Fail
26kms_plane_alpha_blend@constant-alpha-max,Fail40kms_plane_alpha_blend@constant-alpha-max,Fail
41kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation,Timeout
42kms_pm_rpm@modeset-lpsp-stress,Timeout
43kms_pm_rpm@modeset-stress-extra-wait,Timeout
44kms_pm_rpm@universal-planes,Timeout
45kms_pm_rpm@universal-planes-dpms,Timeout
46perf@i915-ref-count,Fail
47perf_pmu@module-unload,Fail
48perf_pmu@rc6,Crash
49sysfs_heartbeat_interval@long,Timeout
50sysfs_heartbeat_interval@off,Timeout
51sysfs_preempt_timeout@off,Timeout
52sysfs_timeslice_duration@off,Timeout
53xe_module_load@force-load,Fail
54xe_module_load@load,Fail
55xe_module_load@many-reload,Fail
56xe_module_load@reload,Fail
57xe_module_load@reload-no-display,Fail
drivers/gpu/drm/ci/xfails/i915-amly-flakes.txt+9−0
@@ -0,0 +1,9 @@
1# Board Name: asus-C433TA-AJ0005-rammus
2# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
5# Failure Rate: 50
6i915_hangman@engine-engine-error
7i915_hangman@gt-engine-hang
8kms_async_flips@crc
9kms_universal_plane@cursor-fb-leak
drivers/gpu/drm/ci/xfails/i915-amly-skips.txt+21−1
@@ -1,4 +1,24 @@
1# Suspend to RAM seems to be broken on this machine1# Suspend to RAM seems to be broken on this machine
2.*suspend.*2.*suspend.*
3# This is generating kernel oops with divide error3# This is generating kernel oops with divide error
4kms_plane_scaling@invalid-parameters4kms_plane_scaling@invalid-parameters
5
6# Skip driver specific tests
7^amdgpu.*
8msm_.*
9nouveau_.*
10panfrost_.*
11^v3d.*
12^vc4.*
13^vmwgfx*
14
15# GEM tests takes ~1000 hours, so skip it
16gem_.*
17
18# Hangs the machine and timeout occurs
19i915_pm_rc6_residency.*
20i915_suspend.*
21kms_scaling_modes.*
22
23# Kernel panic
24drm_fdinfo.*
drivers/gpu/drm/ci/xfails/i915-apl-fails.txt+26−20
@@ -1,13 +1,7 @@
1kms_3d,Timeout1i915_module_load@load,Fail
2kms_bw@linear-tiling-2-displays-1920x1080p,Fail2i915_module_load@reload,Fail
3kms_bw@linear-tiling-2-displays-2560x1440p,Fail3i915_module_load@reload-no-display,Fail
4kms_bw@linear-tiling-2-displays-3840x2160p,Fail4i915_module_load@resize-bar,Fail
5kms_bw@linear-tiling-3-displays-1920x1080p,Fail
6kms_bw@linear-tiling-3-displays-2560x1440p,Fail
7kms_bw@linear-tiling-3-displays-3840x2160p,Fail
8kms_bw@linear-tiling-4-displays-1920x1080p,Fail
9kms_bw@linear-tiling-4-displays-2560x1440p,Fail
10kms_bw@linear-tiling-4-displays-3840x2160p,Fail
11kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail5kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail
12kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail6kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail
13kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail7kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail
@@ -30,18 +24,30 @@ kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail · 16 unmodified lines
30kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail24kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
31kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail25kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
32kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail26kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
33kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail27kms_lease@lease-uevent,Fail
34kms_plane_alpha_blend@alpha-basic,Fail28kms_plane_alpha_blend@alpha-basic,Fail
35kms_plane_alpha_blend@alpha-opaque-fb,Fail29kms_plane_alpha_blend@alpha-opaque-fb,Fail
36kms_plane_alpha_blend@alpha-transparent-fb,Fail30kms_plane_alpha_blend@alpha-transparent-fb,Fail
37kms_plane_alpha_blend@constant-alpha-max,Fail31kms_plane_alpha_blend@constant-alpha-max,Fail
38kms_plane_alpha_blend@pipe-A-alpha-opaque-fb,Fail32kms_pm_backlight@basic-brightness,Fail
39kms_plane_alpha_blend@pipe-A-alpha-transparent-fb,Fail33kms_pm_backlight@fade,Fail
40kms_plane_alpha_blend@pipe-A-constant-alpha-max,Fail34kms_pm_backlight@fade-with-dpms,Fail
41kms_plane_alpha_blend@pipe-B-alpha-opaque-fb,Fail35kms_pm_rpm@legacy-planes,Timeout
42kms_plane_alpha_blend@pipe-B-alpha-transparent-fb,Fail36kms_pm_rpm@legacy-planes-dpms,Timeout
43kms_plane_alpha_blend@pipe-B-constant-alpha-max,Fail37kms_pm_rpm@modeset-stress-extra-wait,Timeout
44kms_plane_alpha_blend@pipe-C-alpha-opaque-fb,Fail38kms_pm_rpm@universal-planes,Timeout
45kms_plane_alpha_blend@pipe-C-alpha-transparent-fb,Fail39kms_pm_rpm@universal-planes-dpms,Timeout
46kms_plane_alpha_blend@pipe-C-constant-alpha-max,Fail
47kms_sysfs_edid_timing,Fail40kms_sysfs_edid_timing,Fail
41perf@i915-ref-count,Fail
42perf@non-zero-reason,Timeout
43perf_pmu@module-unload,Fail
44perf_pmu@rc6,Crash
45sysfs_heartbeat_interval@long,Timeout
46sysfs_heartbeat_interval@off,Timeout
47sysfs_preempt_timeout@off,Timeout
48sysfs_timeslice_duration@off,Timeout
49xe_module_load@force-load,Fail
50xe_module_load@load,Fail
51xe_module_load@many-reload,Fail
52xe_module_load@reload,Fail
53xe_module_load@reload-no-display,Fail
drivers/gpu/drm/ci/xfails/i915-apl-flakes.txt+6−0
@@ -0,0 +1,6 @@
1# Board Name: asus-C523NA-A20057-coral
2# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
5# Failure Rate: 50
6kms_fb_coherency@memset-crc
drivers/gpu/drm/ci/xfails/i915-apl-skips.txt+25−1
@@ -3,4 +3,28 @@ · 2 unmodified lines
3# This is generating kernel oops with divide error3# This is generating kernel oops with divide error
4kms_plane_scaling@invalid-parameters4kms_plane_scaling@invalid-parameters
5# This is cascading issues5# This is cascading issues
6kms_3d6kms_3d
7
8# Skip driver specific tests
9^amdgpu.*
10msm_.*
11nouveau_.*
12panfrost_.*
13^v3d.*
14^vc4.*
15^vmwgfx*
16
17# GEM tests takes ~1000 hours, so skip it
18gem_.*
19
20# Hangs the machine and timeout occurs
21i915_pm_rc6_residency.*
22i915_suspend.*
23i915_pm_rpm.*
24device_reset.*
25api_intel_allocator.*
26kms_frontbuffer_tracking.*
27kms_ccs.*
28
29# Kernel panic
30drm_fdinfo.*
drivers/gpu/drm/ci/xfails/i915-cml-fails.txt+38−0
@@ -1,3 +1,19 @@
1core_setmaster@master-drop-set-user,Fail
2core_setmaster_vs_auth,Fail
3i915_module_load@load,Fail
4i915_module_load@reload,Fail
5i915_module_load@reload-no-display,Fail
6i915_module_load@resize-bar,Fail
7i915_pipe_stress@stress-xrgb8888-untiled,Fail
8i915_pipe_stress@stress-xrgb8888-ytiled,Fail
9i915_pm_rpm@gem-execbuf-stress,Timeout
10i915_pm_rpm@module-reload,Fail
11i915_pm_rpm@system-suspend-execbuf,Timeout
12kms_async_flips@invalid-async-flip,Timeout
13kms_atomic_transition@modeset-transition-fencing,Timeout
14kms_ccs@crc-primary-rotation-180-yf-tiled-ccs,Timeout
15kms_fb_coherency@memset-crc,Crash
16kms_flip@flip-vs-dpms-off-vs-modeset,Timeout
1kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail17kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail
2kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail18kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail
3kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail19kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail
@@ -20,11 +36,33 @@ kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail · 16 unmodified lines
20kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail36kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
21kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail37kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
22kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail38kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
39kms_lease@lease-uevent,Fail
23kms_plane_alpha_blend@alpha-basic,Fail40kms_plane_alpha_blend@alpha-basic,Fail
24kms_plane_alpha_blend@alpha-opaque-fb,Fail41kms_plane_alpha_blend@alpha-opaque-fb,Fail
25kms_plane_alpha_blend@alpha-transparent-fb,Fail42kms_plane_alpha_blend@alpha-transparent-fb,Fail
26kms_plane_alpha_blend@constant-alpha-max,Fail43kms_plane_alpha_blend@constant-alpha-max,Fail
27kms_plane_alpha_blend@constant-alpha-min,Fail44kms_plane_alpha_blend@constant-alpha-min,Fail
45kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation,Timeout
46kms_pm_rpm@modeset-stress-extra-wait,Timeout
47kms_pm_rpm@universal-planes,Timeout
48kms_pm_rpm@universal-planes-dpms,Timeout
49kms_psr2_sf@fbc-plane-move-sf-dmg-area,Timeout
50kms_psr2_sf@overlay-plane-update-continuous-sf,Fail
51kms_psr2_sf@overlay-plane-update-sf-dmg-area,Fail
52kms_psr2_sf@primary-plane-update-sf-dmg-area,Fail
53kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb,Fail
28kms_psr2_su@page_flip-NV12,Fail54kms_psr2_su@page_flip-NV12,Fail
29kms_psr2_su@page_flip-P010,Fail55kms_psr2_su@page_flip-P010,Fail
56kms_psr@psr-sprite-render,Timeout
30kms_setmode@basic,Fail57kms_setmode@basic,Fail
58perf@i915-ref-count,Fail
59perf_pmu@module-unload,Fail
60perf_pmu@rc6,Crash
61perf_pmu@rc6-suspend,Crash
62sysfs_heartbeat_interval@long,Timeout
63sysfs_heartbeat_interval@off,Timeout
64sysfs_preempt_timeout@off,Timeout
65sysfs_timeslice_duration@off,Timeout
66xe_module_load@force-load,Fail
67xe_module_load@load,Fail
68xe_module_load@many-reload,Fail
drivers/gpu/drm/ci/xfails/i915-cml-flakes.txt+6−0
@@ -0,0 +1,6 @@
1# Board Name: asus-C436FA-Flip-hatch
2# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
5# Failure Rate: 50
6kms_plane_alpha_blend@constant-alpha-min
drivers/gpu/drm/ci/xfails/i915-cml-skips.txt+23−0
@@ -1,2 +1,25 @@
1# This is generating kernel oops with divide error1# This is generating kernel oops with divide error
2kms_plane_scaling@invalid-parameters2kms_plane_scaling@invalid-parameters
3
4# Skip driver specific tests
5^amdgpu.*
6msm_.*
7nouveau_.*
8panfrost_.*
9^v3d.*
10^vc4.*
11^vmwgfx*
12
13# GEM tests takes ~1000 hours, so skip it
14gem_.*
15
16# Hangs the machine and timeout occurs
17i915_pm_rc6_residency.*
18i915_suspend.*
19xe_module_load.*
20api_intel_allocator.*
21kms_cursor_legacy.*
22
23# Kernel panic
24drm_fdinfo.*
25kms_frontbuffer_tracking.*
drivers/gpu/drm/ci/xfails/i915-glk-fails.txt+34−7
@@ -1,5 +1,20 @@
1kms_fbcon_fbt@fbc,Fail1core_setmaster@master-drop-set-user,Fail
2kms_flip@blocking-wf_vblank,Fail2i915_module_load@load,Fail
3i915_module_load@reload,Fail
4i915_module_load@reload-no-display,Fail
5i915_module_load@resize-bar,Fail
6kms_async_flips@invalid-async-flip,Timeout
7kms_atomic_transition@modeset-transition-fencing,Timeout
8kms_big_fb@linear-16bpp-rotate-0,Fail
9kms_big_fb@linear-16bpp-rotate-180,Fail
10kms_big_fb@linear-32bpp-rotate-0,Fail
11kms_big_fb@linear-32bpp-rotate-180,Fail
12kms_big_fb@linear-8bpp-rotate-0,Fail
13kms_big_fb@linear-8bpp-rotate-180,Fail
14kms_big_fb@linear-max-hw-stride-32bpp-rotate-0,Fail
15kms_dirtyfb@default-dirtyfb-ioctl,Fail
16kms_draw_crc@draw-method-render,Fail
17kms_flip@flip-vs-dpms-off-vs-modeset,Timeout
3kms_flip@wf_vblank-ts-check,Fail18kms_flip@wf_vblank-ts-check,Fail
4kms_flip@wf_vblank-ts-check-interruptible,Fail19kms_flip@wf_vblank-ts-check-interruptible,Fail
5kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail20kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail
@@ -11,7 +26,6 @@ kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail · 5 unmodified lines
11kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail26kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail
12kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail27kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail
13kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail28kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail
14kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail
15kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail29kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail
16kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail30kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail
17kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail31kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail
@@ -26,11 +40,24 @@ kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail · 8 unmodified lines
26kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail40kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
27kms_frontbuffer_tracking@fbc-tiling-linear,Fail41kms_frontbuffer_tracking@fbc-tiling-linear,Fail
28kms_frontbuffer_tracking@fbcdrrs-tiling-linear,Fail42kms_frontbuffer_tracking@fbcdrrs-tiling-linear,Fail
29kms_plane_alpha_blend@alpha-basic,Fail43kms_lease@lease-uevent,Fail
30kms_plane_alpha_blend@alpha-opaque-fb,Fail44kms_plane_alpha_blend@alpha-opaque-fb,Fail
31kms_plane_alpha_blend@alpha-transparent-fb,Fail45kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation,Timeout
32kms_plane_alpha_blend@constant-alpha-max,Fail46kms_pm_rpm@legacy-planes,Timeout
47kms_pm_rpm@legacy-planes-dpms,Timeout
48kms_pm_rpm@modeset-stress-extra-wait,Timeout
49kms_pm_rpm@universal-planes,Timeout
50kms_pm_rpm@universal-planes-dpms,Timeout
33kms_rotation_crc@multiplane-rotation,Fail51kms_rotation_crc@multiplane-rotation,Fail
34kms_rotation_crc@multiplane-rotation-cropping-bottom,Fail52kms_rotation_crc@multiplane-rotation-cropping-bottom,Fail
35kms_rotation_crc@multiplane-rotation-cropping-top,Fail53kms_rotation_crc@multiplane-rotation-cropping-top,Fail
36kms_setmode@basic,Fail54perf@non-zero-reason,Timeout
55sysfs_heartbeat_interval@long,Timeout
56sysfs_heartbeat_interval@off,Timeout
57sysfs_preempt_timeout@off,Timeout
58sysfs_timeslice_duration@off,Timeout
59xe_module_load@force-load,Fail
60xe_module_load@load,Fail
61xe_module_load@many-reload,Fail
62xe_module_load@reload,Fail
63xe_module_load@reload-no-display,Fail
drivers/gpu/drm/ci/xfails/i915-glk-flakes.txt+7−0
@@ -0,0 +1,7 @@
1# Board Name: hp-x360-12b-ca0010nr-n4020-octopus
2# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
5# Failure Rate: 50
6core_hotunplug@unplug-rescan
7kms_fb_coherency@memset-crc
drivers/gpu/drm/ci/xfails/i915-glk-skips.txt+25−1
@@ -2,4 +2,28 @@ · 1 unmodified line
2.*suspend.*2.*suspend.*
3 3
4# This is generating kernel oops with divide error4# This is generating kernel oops with divide error
5kms_plane_scaling@invalid-parameters5kms_plane_scaling@invalid-parameters
6
7# Skip driver specific tests
8^amdgpu.*
9msm_.*
10nouveau_.*
11panfrost_.*
12^v3d.*
13^vc4.*
14^vmwgfx*
15
16# GEM tests takes ~1000 hours, so skip it
17gem_.*
18
19# Hangs the machine and timeout occurs
20i915_pm_rc6_residency.*
21i915_suspend.*
22i915_pm_rpm.*
23kms_ccs.*
24kms_plane_multiple.*
25perf.*
26
27# Kernel panic
28drm_fdinfo.*
29kms_plane_alpha_blend.*
drivers/gpu/drm/ci/xfails/i915-kbl-fails.txt+19−23
@@ -1,32 +1,28 @@
1kms_bw@linear-tiling-2-displays-2560x1440p,Fail1i915_module_load@load,Fail
2kms_bw@linear-tiling-4-displays-2560x1440p,Fail2i915_module_load@reload,Fail
3kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail3i915_module_load@reload-no-display,Fail
4kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail4i915_module_load@resize-bar,Fail
5i915_pm_rpm@gem-execbuf-stress,Timeout
5kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail6kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail
6kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail
7kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail
8kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail7kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
9kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail
10kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail8kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail
11kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail9kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail
12kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail
13kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail
14kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail10kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail
15kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail
16kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail11kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail
17kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail
18kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail
19kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail
20kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail
21kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail12kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail
22kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
23kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail13kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
24kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail14kms_lease@lease-uevent,Fail
25kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail
26kms_plane_alpha_blend@alpha-basic,Fail
27kms_plane_alpha_blend@alpha-opaque-fb,Fail
28kms_plane_alpha_blend@alpha-transparent-fb,Fail15kms_plane_alpha_blend@alpha-transparent-fb,Fail
29kms_plane_alpha_blend@constant-alpha-max,Fail16perf@i915-ref-count,Fail
30kms_plane_alpha_blend@pipe-A-constant-alpha-max,Fail17perf_pmu@busy-accuracy-50,Fail
31kms_plane_alpha_blend@pipe-B-alpha-opaque-fb,Fail18perf_pmu@module-unload,Fail
32kms_plane_alpha_blend@pipe-C-constant-alpha-max,Fail19perf_pmu@rc6,Crash
20sysfs_heartbeat_interval@long,Timeout
21sysfs_heartbeat_interval@off,Timeout
22sysfs_preempt_timeout@off,Timeout
23sysfs_timeslice_duration@off,Timeout
24xe_module_load@force-load,Fail
25xe_module_load@load,Fail
26xe_module_load@many-reload,Fail
27xe_module_load@reload,Fail
28xe_module_load@reload-no-display,Fail
drivers/gpu/drm/ci/xfails/i915-kbl-flakes.txt+6−1
@@ -1 +1,6 @@
1kms_async_flips@crc1# Board Name: hp-x360-14-G1-sona
2# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
5# Failure Rate: 50
6prime_busy@hang
drivers/gpu/drm/ci/xfails/i915-kbl-skips.txt+35−1
@@ -2,4 +2,38 @@ · 1 unmodified line
2.*suspend.*2.*suspend.*
3 3
4# This is generating kernel oops with divide error4# This is generating kernel oops with divide error
5kms_plane_scaling@invalid-parameters5kms_plane_scaling@invalid-parameters
6
7# Skip driver specific tests
8^amdgpu.*
9msm_.*
10nouveau_.*
11panfrost_.*
12^v3d.*
13^vc4.*
14^vmwgfx*
15
16# GEM tests takes ~1000 hours, so skip it
17gem_.*
18
19# Hangs the machine and timeout occurs
20i915_.*
21api_intel_bb.*
22
23# Kernel panic
24drm_fdinfo.*
25kms_.*
26prime_mmap_coherency.*
27perf.*
28drm_read.*
29api_intel_allocator.*
30sysfs_preempt_timeout.*
31dumb_buffer.*
32gen9_exec_parse.*
33debugfs_test.*
34core_hotunplug.*
35tools_test.*
36
37# GPU hang
38sysfs_timeslice_.*
39sysfs_heartbeat_.*
drivers/gpu/drm/ci/xfails/i915-tgl-fails.txt+42−35
@@ -1,36 +1,43 @@
1kms_bw@linear-tiling-2-displays-3840x2160p,Fail1api_intel_bb@blit-noreloc-keep-cache,Timeout
2kms_bw@linear-tiling-3-displays-1920x1080p,Fail2api_intel_bb@offset-control,Timeout
3kms_bw@linear-tiling-3-displays-2560x1440p,Fail3api_intel_bb@render-ccs,Timeout
4kms_bw@linear-tiling-3-displays-3840x2160p,Fail4core_getclient,Timeout
5kms_bw@linear-tiling-4-displays-1920x1080p,Fail5core_hotunplug@hotreplug-lateclose,Timeout
6kms_bw@linear-tiling-4-displays-2560x1440p,Fail6drm_read@short-buffer-block,Timeout
7kms_bw@linear-tiling-4-displays-3840x2160p,Fail7drm_read@short-buffer-nonblock,Timeout
8kms_bw@linear-tiling-5-displays-1920x1080p,Fail8dumb_buffer@map-uaf,Timeout
9kms_bw@linear-tiling-5-displays-2560x1440p,Fail9gen3_render_tiledx_blits,Timeout
10kms_bw@linear-tiling-5-displays-3840x2160p,Fail10gen7_exec_parse@basic-allocation,Timeout
11kms_flip@flip-vs-panning-vs-hang,Timeout11gen7_exec_parse@batch-without-end,Timeout
12kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail12gen9_exec_parse@batch-invalid-length,Timeout
13kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail13gen9_exec_parse@bb-secure,Timeout
14kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail14i915_module_load@load,Fail
15kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail15i915_module_load@reload,Fail
16kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail16i915_module_load@reload-no-display,Fail
17kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail17i915_module_load@resize-bar,Fail
18kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail18i915_pciid,Timeout
19kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail19i915_query@engine-info,Timeout
20kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail20kms_lease@lease-uevent,Fail
21kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail
22kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail
23kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail
24kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail
25kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail
26kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail
27kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail
28kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail
29kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
30kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
31kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
32kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail
33kms_rotation_crc@bad-pixel-format,Fail
34kms_rotation_crc@multiplane-rotation,Fail21kms_rotation_crc@multiplane-rotation,Fail
35kms_rotation_crc@multiplane-rotation-cropping-bottom,Fail22perf@i915-ref-count,Fail
36kms_rotation_crc@multiplane-rotation-cropping-top,Fail23perf_pmu@busy,Timeout
24perf_pmu@enable-race,Timeout
25perf_pmu@event-wait,Timeout
26perf_pmu@gt-awake,Timeout
27perf_pmu@module-unload,Fail
28perf_pmu@rc6,Crash
29prime_mmap@test_map_unmap,Timeout
30prime_self_import@basic-with_one_bo,Timeout
31syncobj_basic@bad-destroy,Timeout
32syncobj_eventfd@invalid-bad-pad,Timeout
33syncobj_wait@invalid-multi-wait-unsubmitted-signaled,Timeout
34syncobj_wait@invalid-signal-illegal-handle,Timeout
35syncobj_wait@invalid-single-wait-all-unsubmitted,Timeout
36syncobj_wait@multi-wait-all-submitted,Timeout
37syncobj_wait@multi-wait-for-submit-submitted-signaled,Timeout
38syncobj_wait@wait-any-complex,Timeout
39syncobj_wait@wait-delayed-signal,Timeout
40xe_module_load@force-load,Fail
41xe_module_load@load,Fail
42xe_module_load@reload,Fail
43xe_module_load@reload-no-display,Fail
drivers/gpu/drm/ci/xfails/i915-tgl-skips.txt+27−1
@@ -8,4 +8,30 @@ gem_eio.* · 7 unmodified lines
8kms_flip@absolute-wf_vblank@a-edp18kms_flip@absolute-wf_vblank@a-edp1
9 9
10# This is generating kernel oops with divide error10# This is generating kernel oops with divide error
11kms_plane_scaling@invalid-parameters11kms_plane_scaling@invalid-parameters
12
13# Skip driver specific tests
14^amdgpu.*
15msm_.*
16nouveau_.*
17panfrost_.*
18^v3d.*
19^vc4.*
20^vmwgfx*
21
22# GEM tests takes ~1000 hours, so skip it
23gem_.*
24
25# Kernel panic
26drm_fdinfo.*
27
28# Hangs the machine and timeout occurs
29i915_pm_rc6_residency.*
30i915_suspend.*
31sysfs_heartbeat_interval.*
32syncobj_timeline.*
33sysfs_timeslice_duration.*
34syncobj_wait.*
35
36# Kernel panic and test hangs with multiple kms tests
37kms_.*
drivers/gpu/drm/ci/xfails/i915-whl-fails.txt+40−23
@@ -1,14 +1,25 @@
1kms_bw@linear-tiling-2-displays-1920x1080p,Fail1core_setmaster@master-drop-set-user,Fail
2kms_bw@linear-tiling-2-displays-2560x1440p,Fail2core_setmaster_vs_auth,Fail
3kms_bw@linear-tiling-2-displays-3840x2160p,Fail3i915_module_load@load,Fail
4kms_bw@linear-tiling-3-displays-1920x1080p,Fail4i915_module_load@reload,Fail
5kms_bw@linear-tiling-3-displays-2560x1440p,Fail5i915_module_load@reload-no-display,Fail
6kms_bw@linear-tiling-3-displays-3840x2160p,Fail6i915_module_load@resize-bar,Fail
7kms_bw@linear-tiling-4-displays-1920x1080p,Fail7i915_pm_rpm@gem-execbuf-stress,Timeout
8kms_bw@linear-tiling-4-displays-2560x1440p,Fail8i915_pm_rpm@module-reload,Fail
9kms_bw@linear-tiling-4-displays-3840x2160p,Fail9i915_pm_rpm@system-suspend-execbuf,Timeout
10kms_fbcon_fbt@fbc,Fail10kms_async_flips@invalid-async-flip,Timeout
11kms_fbcon_fbt@fbc-suspend,Fail11kms_atomic_transition@modeset-transition-fencing,Timeout
12kms_big_fb@linear-16bpp-rotate-0,Fail
13kms_big_fb@linear-16bpp-rotate-180,Fail
14kms_big_fb@linear-32bpp-rotate-0,Fail
15kms_big_fb@linear-32bpp-rotate-180,Fail
16kms_big_fb@linear-8bpp-rotate-0,Fail
17kms_big_fb@linear-8bpp-rotate-180,Fail
18kms_big_fb@linear-max-hw-stride-32bpp-rotate-0,Fail
19kms_ccs@crc-primary-rotation-180-yf-tiled-ccs,Timeout
20kms_dirtyfb@default-dirtyfb-ioctl,Fail
21kms_draw_crc@draw-method-render,Fail
22kms_fb_coherency@memset-crc,Crash
12kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail23kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail
13kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail24kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail
14kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail25kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail
@@ -18,8 +29,6 @@ kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail · 3 unmodified lines
18kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail29kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail
19kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail30kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail
20kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail31kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail
21kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail
22kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail
23kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail32kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail
24kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail33kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail
25kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail34kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail
@@ -31,18 +40,26 @@ kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail · 5 unmodified lines
31kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail40kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
32kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail41kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
33kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail42kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
34kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail
35kms_frontbuffer_tracking@fbc-tiling-linear,Fail43kms_frontbuffer_tracking@fbc-tiling-linear,Fail
44kms_lease@lease-uevent,Fail
36kms_plane_alpha_blend@alpha-basic,Fail45kms_plane_alpha_blend@alpha-basic,Fail
37kms_plane_alpha_blend@alpha-opaque-fb,Fail46kms_plane_alpha_blend@alpha-opaque-fb,Fail
38kms_plane_alpha_blend@alpha-transparent-fb,Fail47kms_plane_alpha_blend@alpha-transparent-fb,Fail
39kms_plane_alpha_blend@constant-alpha-max,Fail48kms_plane_alpha_blend@constant-alpha-max,Fail
40kms_plane_alpha_blend@pipe-A-alpha-opaque-fb,Fail49kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation,Timeout
41kms_plane_alpha_blend@pipe-A-alpha-transparent-fb,Fail50kms_pm_rpm@modeset-stress-extra-wait,Timeout
42kms_plane_alpha_blend@pipe-A-constant-alpha-max,Fail51kms_pm_rpm@universal-planes,Timeout
43kms_plane_alpha_blend@pipe-B-alpha-opaque-fb,Fail52kms_pm_rpm@universal-planes-dpms,Timeout
44kms_plane_alpha_blend@pipe-B-alpha-transparent-fb,Fail53perf@i915-ref-count,Fail
45kms_plane_alpha_blend@pipe-B-constant-alpha-max,Fail54perf_pmu@module-unload,Fail
46kms_plane_alpha_blend@pipe-C-alpha-opaque-fb,Fail55perf_pmu@rc6,Crash
47kms_plane_alpha_blend@pipe-C-alpha-transparent-fb,Fail56perf_pmu@rc6-suspend,Crash
48kms_plane_alpha_blend@pipe-C-constant-alpha-max,Fail57sysfs_heartbeat_interval@long,Timeout
58sysfs_heartbeat_interval@off,Timeout
59sysfs_preempt_timeout@off,Timeout
60sysfs_timeslice_duration@off,Timeout
61xe_module_load@force-load,Fail
62xe_module_load@load,Fail
63xe_module_load@many-reload,Fail
64xe_module_load@reload,Fail
65xe_module_load@reload-no-display,Fail
drivers/gpu/drm/ci/xfails/i915-whl-flakes.txt+6−0
@@ -0,0 +1,6 @@
1# Board Name: dell-latitude-5400-8665U-sarien
2# Bug Report: https://lore.kernel.org/intel-gfx/af4ca4df-a3ef-4943-bdbf-4c3af2c333af@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
5# Failure Rate: 50
6kms_pm_rpm@modeset-lpsp-stress
drivers/gpu/drm/ci/xfails/i915-whl-skips.txt+21−1
@@ -1,2 +1,22 @@
1# This is generating kernel oops with divide error1# This is generating kernel oops with divide error
2kms_plane_scaling@invalid-parameters2kms_plane_scaling@invalid-parameters
3
4# Skip driver specific tests
5^amdgpu.*
6msm_.*
7nouveau_.*
8panfrost_.*
9^v3d.*
10^vc4.*
11^vmwgfx*
12
13# GEM tests takes ~1000 hours, so skip it
14gem_.*
15
16# Hangs the machine and timeout occurs
17i915_pm_rc6_residency.*
18i915_suspend.*
19kms_flip.*
20
21# Kernel panic
22drm_fdinfo.*
drivers/gpu/drm/ci/xfails/mediatek-mt8173-fails.txt+12−18
@@ -1,36 +1,30 @@
1device_reset@cold-reset-bound,Fail
2device_reset@reset-bound,Fail
3device_reset@unbind-cold-reset-rebind,Fail
4device_reset@unbind-reset-rebind,Fail
5dumb_buffer@invalid-bpp,Fail
6fbdev@eof,Fail
7fbdev@read,Fail
8fbdev@unaligned-write,Fail
1kms_3d,Fail9kms_3d,Fail
2kms_bw@linear-tiling-1-displays-1920x1080p,Fail10kms_bw@linear-tiling-1-displays-1920x1080p,Fail
11kms_bw@linear-tiling-1-displays-2160x1440p,Fail
3kms_bw@linear-tiling-1-displays-2560x1440p,Fail12kms_bw@linear-tiling-1-displays-2560x1440p,Fail
4kms_bw@linear-tiling-1-displays-3840x2160p,Fail13kms_bw@linear-tiling-1-displays-3840x2160p,Fail
5kms_bw@linear-tiling-2-displays-1920x1080p,Fail14kms_bw@linear-tiling-2-displays-1920x1080p,Fail
15kms_bw@linear-tiling-2-displays-2160x1440p,Fail
6kms_bw@linear-tiling-2-displays-2560x1440p,Fail16kms_bw@linear-tiling-2-displays-2560x1440p,Fail
7kms_bw@linear-tiling-2-displays-3840x2160p,Fail17kms_bw@linear-tiling-2-displays-3840x2160p,Fail
8kms_bw@linear-tiling-3-displays-1920x1080p,Fail
9kms_bw@linear-tiling-3-displays-2560x1440p,Fail
10kms_bw@linear-tiling-3-displays-3840x2160p,Fail
11kms_color@invalid-gamma-lut-sizes,Fail18kms_color@invalid-gamma-lut-sizes,Fail
12kms_color@pipe-A-invalid-gamma-lut-sizes,Fail
13kms_color@pipe-B-invalid-gamma-lut-sizes,Fail
14kms_cursor_legacy@cursor-vs-flip-atomic,Fail19kms_cursor_legacy@cursor-vs-flip-atomic,Fail
15kms_cursor_legacy@cursor-vs-flip-legacy,Fail20kms_cursor_legacy@cursor-vs-flip-legacy,Fail
16kms_flip@flip-vs-modeset-vs-hang,Fail21kms_flip@flip-vs-modeset-vs-hang,Fail
17kms_flip@flip-vs-panning-vs-hang,Fail22kms_flip@flip-vs-panning-vs-hang,Fail
18kms_flip@flip-vs-suspend,Fail23kms_flip@flip-vs-suspend,Fail
19kms_flip@flip-vs-suspend-interruptible,Fail24kms_flip@flip-vs-suspend-interruptible,Fail
20kms_force_connector_basic@force-edid,Fail25kms_lease@lease-uevent,Fail
21kms_force_connector_basic@force-load-detect,Fail
22kms_force_connector_basic@prune-stale-modes,Fail
23kms_hdmi_inject@inject-4k,Fail
24kms_plane_scaling@planes-upscale-20x20,Fail
25kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25,Fail
26kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5,Fail
27kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75,Fail
28kms_plane_scaling@upscale-with-modifier-20x20,Fail
29kms_plane_scaling@upscale-with-pixel-format-20x20,Fail
30kms_plane_scaling@upscale-with-rotation-20x20,Fail
31kms_properties@get_properties-sanity-atomic,Fail26kms_properties@get_properties-sanity-atomic,Fail
32kms_properties@plane-properties-atomic,Fail27kms_properties@plane-properties-atomic,Fail
33kms_properties@plane-properties-legacy,Fail28kms_properties@plane-properties-legacy,Fail
34kms_rmfb@close-fd,Fail29kms_rmfb@close-fd,Fail
35kms_selftest@drm_format,Timeout30tools_test@tools_test,Fail
36kms_selftest@drm_format_helper,Timeout
drivers/gpu/drm/ci/xfails/mediatek-mt8173-flakes.txt+11−0
@@ -0,0 +1,11 @@
1# Board Name: mt8173-elm-hana
2# Bug Report: https://lore.kernel.org/linux-mediatek/0b2a1899-15dd-42fa-8f63-ea0ca28dbb17@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
5# Failure Rate: 50
6core_setmaster_vs_auth
7dumb_buffer@create-clear
8fbdev@unaligned-write
9fbdev@write
10kms_cursor_legacy@cursor-vs-flip-atomic-transitions
11kms_prop_blob@invalid-set-prop
drivers/gpu/drm/ci/xfails/mediatek-mt8173-skips.txt+16−0
@@ -0,0 +1,16 @@
1# Skip driver specific tests
2^amdgpu.*
3msm_.*
4nouveau_.*
5panfrost_.*
6^v3d.*
7^vc4.*
8^vmwgfx*
9
10# Skip intel specific tests
11gem_.*
12i915_.*
13
14# Currently fails and causes coverage loss for other tests
15# since core_getversion also fails.
16core_hotunplug.*
drivers/gpu/drm/ci/xfails/mediatek-mt8183-fails.txt+8−13
@@ -1,13 +1,8 @@
1kms_addfb_basic@addfb25-bad-modifier,Fail1dumb_buffer@create-clear,Fail
2kms_bw@linear-tiling-1-displays-2560x1440p,Fail2dumb_buffer@create-valid-dumb,Fail
3kms_bw@linear-tiling-2-displays-1920x1080p,Fail3dumb_buffer@invalid-bpp,Fail
4kms_bw@linear-tiling-2-displays-2560x1440p,Fail4dumb_buffer@map-invalid-size,Fail
5kms_bw@linear-tiling-2-displays-3840x2160p,Fail5dumb_buffer@map-uaf,Fail
6kms_bw@linear-tiling-3-displays-2560x1440p,Fail6dumb_buffer@map-valid,Fail
7kms_bw@linear-tiling-3-displays-3840x2160p,Fail7panfrost_prime@gem-prime-import,Fail
8kms_color@pipe-A-invalid-gamma-lut-sizes,Fail8tools_test@tools_test,Fail
9kms_plane_cursor@overlay,Fail
10kms_plane_cursor@primary,Fail
11kms_plane_cursor@viewport,Fail
12kms_plane_scaling@upscale-with-rotation-20x20,Fail
13kms_rmfb@close-fd,Fail
drivers/gpu/drm/ci/xfails/mediatek-mt8183-skips.txt+18−0
@@ -0,0 +1,18 @@
1# Skip driver specific tests
2^amdgpu.*
3msm_.*
4nouveau_.*
5^v3d.*
6^vc4.*
7^vmwgfx*
8
9# Skip intel specific tests
10gem_.*
11i915_.*
12
13# Panfrost is not a KMS driver, so skip the KMS tests
14kms_.*
15
16# Currently fails and causes coverage loss for other tests
17# since core_getversion also fails.
18core_hotunplug.*
drivers/gpu/drm/ci/xfails/meson-g12b-fails.txt+8−16
@@ -1,16 +1,8 @@
1kms_3d,Fail1dumb_buffer@create-clear,Fail
2kms_cursor_legacy@forked-bo,Fail2dumb_buffer@create-valid-dumb,Fail
3kms_cursor_legacy@forked-move,Fail3dumb_buffer@invalid-bpp,Fail
4kms_cursor_legacy@single-bo,Fail4dumb_buffer@map-invalid-size,Fail
5kms_cursor_legacy@single-move,Fail5dumb_buffer@map-uaf,Fail
6kms_cursor_legacy@torture-bo,Fail6dumb_buffer@map-valid,Fail
7kms_cursor_legacy@torture-move,Fail7panfrost_prime@gem-prime-import,Fail
8kms_force_connector_basic@force-edid,Fail8tools_test@tools_test,Fail
9kms_hdmi_inject@inject-4k,Fail
10kms_plane_cursor@overlay,Fail
11kms_plane_cursor@primary,Fail
12kms_plane_cursor@viewport,Fail
13kms_properties@connector-properties-atomic,Fail
14kms_properties@connector-properties-legacy,Fail
15kms_properties@get_properties-sanity-atomic,Fail
16kms_properties@get_properties-sanity-non-atomic,Fail
drivers/gpu/drm/ci/xfails/meson-g12b-skips.txt+18−0
@@ -0,0 +1,18 @@
1# Skip driver specific tests
2^amdgpu.*
3msm_.*
4nouveau_.*
5^v3d.*
6^vc4.*
7^vmwgfx*
8
9# Skip intel specific tests
10gem_.*
11i915_.*
12
13# Panfrost is not a KMS driver, so skip the KMS tests
14kms_.*
15
16# Currently fails and causes coverage loss for other tests
17# since core_getversion also fails.
18core_hotunplug.*
drivers/gpu/drm/ci/xfails/msm-apq8016-fails.txt+11−15
@@ -1,19 +1,15 @@
1device_reset@cold-reset-bound,Fail
2device_reset@reset-bound,Fail
3device_reset@unbind-cold-reset-rebind,Fail
4device_reset@unbind-reset-rebind,Fail
5dumb_buffer@invalid-bpp,Fail
1kms_3d,Fail6kms_3d,Fail
2kms_addfb_basic@addfb25-bad-modifier,Fail7kms_cursor_legacy@forked-move,Fail
3kms_cursor_legacy@all-pipes-forked-bo,Fail8kms_cursor_legacy@single-bo,Fail
4kms_cursor_legacy@all-pipes-forked-move,Fail9kms_cursor_legacy@torture-bo,Fail
5kms_cursor_legacy@all-pipes-single-bo,Fail10kms_cursor_legacy@torture-move,Fail
6kms_cursor_legacy@all-pipes-single-move,Fail
7kms_cursor_legacy@all-pipes-torture-bo,Fail
8kms_cursor_legacy@all-pipes-torture-move,Fail
9kms_cursor_legacy@pipe-A-forked-bo,Fail
10kms_cursor_legacy@pipe-A-forked-move,Fail
11kms_cursor_legacy@pipe-A-single-bo,Fail
12kms_cursor_legacy@pipe-A-single-move,Fail
13kms_cursor_legacy@pipe-A-torture-bo,Fail
14kms_cursor_legacy@pipe-A-torture-move,Fail
15kms_force_connector_basic@force-edid,Fail11kms_force_connector_basic@force-edid,Fail
16kms_hdmi_inject@inject-4k,Fail12kms_hdmi_inject@inject-4k,Fail
17kms_selftest@drm_format,Timeout13kms_lease@lease-uevent,Fail
18kms_selftest@drm_format_helper,Timeout
19msm_mapping@ring,Fail14msm_mapping@ring,Fail
15tools_test@tools_test,Fail
drivers/gpu/drm/ci/xfails/msm-apq8016-skips.txt+15−0
@@ -0,0 +1,15 @@
1# Skip driver specific tests
2^amdgpu.*
3nouveau_.*
4panfrost_.*
5^v3d.*
6^vc4.*
7^vmwgfx*
8
9# Skip intel specific tests
10gem_.*
11i915_.*
12
13# Currently fails and causes coverage loss for other tests
14# since core_getversion also fails.
15core_hotunplug.*
drivers/gpu/drm/ci/xfails/msm-apq8096-fails.txt+7−1
@@ -1,2 +1,8 @@
1device_reset@cold-reset-bound,Fail
2device_reset@reset-bound,Fail
3device_reset@unbind-cold-reset-rebind,Fail
4device_reset@unbind-reset-rebind,Fail
5dumb_buffer@invalid-bpp,Fail
1kms_3d,Fail6kms_3d,Fail
2kms_addfb_basic@addfb25-bad-modifier,Fail7kms_lease@lease-uevent,Fail
8tools_test@tools_test,Fail
drivers/gpu/drm/ci/xfails/msm-apq8096-flakes.txt+6−0
@@ -0,0 +1,6 @@
1# Board Name: apq8096-db820c
2# Bug Report: https://lore.kernel.org/linux-arm-msm/661483c8-ad82-400d-bcd8-e94986d20d7d@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
5# Failure Rate: 50
6dumb_buffer@create-clear
drivers/gpu/drm/ci/xfails/msm-apq8096-skips.txt+25−1
@@ -1,2 +1,26 @@
1# Whole machine hangs1# Whole machine hangs
2kms_cursor_legacy@all-pipes-torture-move2kms_cursor_legacy@all-pipes-torture-move
3
4# Skip driver specific tests
5^amdgpu.*
6nouveau_.*
7panfrost_.*
8^v3d.*
9^vc4.*
10^vmwgfx*
11
12# Skip intel specific tests
13gem_.*
14i915_.*
15
16# Currently fails and causes coverage loss for other tests
17# since core_getversion also fails.
18core_hotunplug.*
19
20# gpu fault
21# [IGT] msm_mapping: executing
22# [IGT] msm_mapping: starting subtest shadow
23# *** gpu fault: ttbr0=00000001030ea000 iova=0000000001074000 dir=WRITE type=PERMISSION source=1f030000 (0,0,0,0)
24# msm_mdp 901000.display-controller: RBBM | ME master split | status=0x701000B0
25# watchdog: BUG: soft lockup - CPU#0 stuck for 26s! [kworker/u16:3:46]
26msm_mapping@shadow
drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-fails.txt+174−1
@@ -1,18 +1,191 @@
1device_reset@cold-reset-bound,Fail
2device_reset@reset-bound,Fail
3device_reset@unbind-cold-reset-rebind,Fail
4device_reset@unbind-reset-rebind,Fail
5dumb_buffer@invalid-bpp,Fail
6kms_atomic_transition@plane-primary-toggle-with-vblank-wait,Fail
1kms_color@ctm-0-25,Fail7kms_color@ctm-0-25,Fail
2kms_color@ctm-0-50,Fail8kms_color@ctm-0-50,Fail
3kms_color@ctm-0-75,Fail9kms_color@ctm-0-75,Fail
4kms_color@ctm-blue-to-red,Fail10kms_color@ctm-blue-to-red,Fail
5kms_color@ctm-green-to-red,Fail11kms_color@ctm-green-to-red,Fail
12kms_color@ctm-max,Fail
6kms_color@ctm-negative,Fail13kms_color@ctm-negative,Fail
7kms_color@ctm-red-to-blue,Fail14kms_color@ctm-red-to-blue,Fail
8kms_color@ctm-signed,Fail15kms_color@ctm-signed,Fail
16kms_content_protection@atomic,Crash
17kms_content_protection@atomic-dpms,Crash
18kms_content_protection@content-type-change,Crash
19kms_content_protection@lic-type-0,Crash
20kms_content_protection@lic-type-1,Crash
21kms_content_protection@srm,Crash
22kms_content_protection@type1,Crash
23kms_content_protection@uevent,Crash
24kms_cursor_crc@cursor-alpha-opaque,Fail
25kms_cursor_crc@cursor-alpha-transparent,Fail
26kms_cursor_crc@cursor-dpms,Fail
27kms_cursor_crc@cursor-offscreen-128x128,Fail
28kms_cursor_crc@cursor-offscreen-128x42,Fail
29kms_cursor_crc@cursor-offscreen-256x256,Fail
30kms_cursor_crc@cursor-offscreen-256x85,Fail
31kms_cursor_crc@cursor-offscreen-32x10,Fail
32kms_cursor_crc@cursor-offscreen-32x32,Fail
33kms_cursor_crc@cursor-offscreen-512x170,Fail
34kms_cursor_crc@cursor-offscreen-512x512,Fail
35kms_cursor_crc@cursor-offscreen-64x21,Fail
36kms_cursor_crc@cursor-offscreen-64x64,Fail
37kms_cursor_crc@cursor-onscreen-128x128,Fail
38kms_cursor_crc@cursor-onscreen-128x42,Fail
39kms_cursor_crc@cursor-onscreen-256x256,Fail
40kms_cursor_crc@cursor-onscreen-256x85,Fail
41kms_cursor_crc@cursor-onscreen-32x10,Fail
42kms_cursor_crc@cursor-onscreen-32x32,Fail
43kms_cursor_crc@cursor-onscreen-512x170,Fail
44kms_cursor_crc@cursor-onscreen-512x512,Fail
45kms_cursor_crc@cursor-onscreen-64x21,Fail
46kms_cursor_crc@cursor-onscreen-64x64,Fail
47kms_cursor_crc@cursor-random-128x128,Fail
48kms_cursor_crc@cursor-random-128x42,Fail
49kms_cursor_crc@cursor-random-256x256,Fail
50kms_cursor_crc@cursor-random-256x85,Fail
51kms_cursor_crc@cursor-random-32x10,Fail
52kms_cursor_crc@cursor-random-32x32,Fail
53kms_cursor_crc@cursor-random-512x170,Fail
54kms_cursor_crc@cursor-random-512x512,Fail
55kms_cursor_crc@cursor-random-64x21,Fail
56kms_cursor_crc@cursor-random-64x64,Fail
57kms_cursor_crc@cursor-rapid-movement-128x128,Fail
58kms_cursor_crc@cursor-rapid-movement-128x42,Fail
59kms_cursor_crc@cursor-rapid-movement-256x256,Fail
60kms_cursor_crc@cursor-rapid-movement-256x85,Fail
61kms_cursor_crc@cursor-rapid-movement-32x10,Fail
62kms_cursor_crc@cursor-rapid-movement-32x32,Fail
63kms_cursor_crc@cursor-rapid-movement-512x170,Fail
64kms_cursor_crc@cursor-rapid-movement-512x512,Fail
65kms_cursor_crc@cursor-rapid-movement-64x21,Fail
66kms_cursor_crc@cursor-rapid-movement-64x64,Fail
67kms_cursor_crc@cursor-size-change,Fail
68kms_cursor_crc@cursor-sliding-128x128,Fail
69kms_cursor_crc@cursor-sliding-128x42,Fail
70kms_cursor_crc@cursor-sliding-256x256,Fail
71kms_cursor_crc@cursor-sliding-256x85,Fail
72kms_cursor_crc@cursor-sliding-32x10,Fail
73kms_cursor_crc@cursor-sliding-32x32,Fail
74kms_cursor_crc@cursor-sliding-512x170,Fail
75kms_cursor_crc@cursor-sliding-512x512,Fail
76kms_cursor_crc@cursor-sliding-64x21,Fail
77kms_cursor_crc@cursor-sliding-64x64,Fail
78kms_cursor_edge_walk@128x128-left-edge,Fail
79kms_cursor_edge_walk@128x128-right-edge,Fail
80kms_cursor_edge_walk@128x128-top-bottom,Fail
81kms_cursor_edge_walk@128x128-top-edge,Fail
82kms_cursor_edge_walk@256x256-left-edge,Fail
83kms_cursor_edge_walk@256x256-right-edge,Fail
84kms_cursor_edge_walk@256x256-top-bottom,Fail
85kms_cursor_edge_walk@256x256-top-edge,Fail
86kms_cursor_edge_walk@64x64-left-edge,Fail
87kms_cursor_edge_walk@64x64-right-edge,Fail
88kms_cursor_edge_walk@64x64-top-bottom,Fail
89kms_cursor_edge_walk@64x64-top-edge,Fail
90kms_cursor_legacy@2x-cursor-vs-flip-atomic,Fail
91kms_cursor_legacy@2x-cursor-vs-flip-legacy,Fail
92kms_cursor_legacy@2x-flip-vs-cursor-atomic,Fail
93kms_cursor_legacy@2x-flip-vs-cursor-legacy,Fail
94kms_cursor_legacy@2x-long-cursor-vs-flip-atomic,Fail
95kms_cursor_legacy@2x-long-cursor-vs-flip-legacy,Fail
96kms_cursor_legacy@2x-long-flip-vs-cursor-atomic,Fail
97kms_cursor_legacy@2x-long-flip-vs-cursor-legacy,Fail
9kms_cursor_legacy@cursor-vs-flip-toggle,Fail98kms_cursor_legacy@cursor-vs-flip-toggle,Fail
10kms_cursor_legacy@cursor-vs-flip-varying-size,Fail99kms_cursor_legacy@cursor-vs-flip-varying-size,Fail
100kms_display_modes@extended-mode-basic,Fail
101kms_flip@2x-flip-vs-modeset-vs-hang,Fail
102kms_flip@2x-flip-vs-panning-vs-hang,Fail
103kms_flip@absolute-wf_vblank,Fail
104kms_flip@absolute-wf_vblank-interruptible,Fail
105kms_flip@basic-flip-vs-wf_vblank,Fail
106kms_flip@basic-plain-flip,Fail
107kms_flip@blocking-absolute-wf_vblank,Fail
108kms_flip@blocking-absolute-wf_vblank-interruptible,Fail
109kms_flip@blocking-wf_vblank,Fail
110kms_flip@busy-flip,Fail
111kms_flip@dpms-off-confusion,Fail
112kms_flip@dpms-off-confusion-interruptible,Fail
113kms_flip@dpms-vs-vblank-race,Fail
114kms_flip@dpms-vs-vblank-race-interruptible,Fail
115kms_flip@flip-vs-absolute-wf_vblank,Fail
116kms_flip@flip-vs-absolute-wf_vblank-interruptible,Fail
117kms_flip@flip-vs-blocking-wf-vblank,Fail
118kms_flip@flip-vs-expired-vblank,Fail
119kms_flip@flip-vs-expired-vblank-interruptible,Fail
11kms_flip@flip-vs-modeset-vs-hang,Fail120kms_flip@flip-vs-modeset-vs-hang,Fail
121kms_flip@flip-vs-panning,Fail
122kms_flip@flip-vs-panning-interruptible,Fail
12kms_flip@flip-vs-panning-vs-hang,Fail123kms_flip@flip-vs-panning-vs-hang,Fail
124kms_flip@flip-vs-rmfb,Fail
125kms_flip@flip-vs-rmfb-interruptible,Fail
126kms_flip@flip-vs-wf_vblank-interruptible,Fail
127kms_flip@modeset-vs-vblank-race,Fail
128kms_flip@modeset-vs-vblank-race-interruptible,Fail
129kms_flip@plain-flip-fb-recreate,Fail
130kms_flip@plain-flip-fb-recreate-interruptible,Fail
131kms_flip@plain-flip-interruptible,Fail
132kms_flip@plain-flip-ts-check,Fail
133kms_flip@plain-flip-ts-check-interruptible,Fail
134kms_flip@wf_vblank-ts-check,Fail
135kms_flip@wf_vblank-ts-check-interruptible,Fail
136kms_lease@cursor-implicit-plane,Fail
137kms_lease@lease-uevent,Fail
138kms_lease@page-flip-implicit-plane,Fail
139kms_lease@setcrtc-implicit-plane,Fail
140kms_lease@simple-lease,Fail
141kms_multipipe_modeset@basic-max-pipe-crc-check,Fail
13kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail142kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail
143kms_pipe_crc_basic@compare-crc-sanitycheck-xr24,Fail
144kms_pipe_crc_basic@disable-crc-after-crtc,Fail
145kms_pipe_crc_basic@nonblocking-crc,Fail
146kms_pipe_crc_basic@nonblocking-crc-frame-sequence,Fail
147kms_pipe_crc_basic@read-crc,Fail
148kms_pipe_crc_basic@read-crc-frame-sequence,Fail
149kms_plane@pixel-format,Fail
150kms_plane@pixel-format-source-clamping,Fail
151kms_plane@plane-panning-bottom-right,Fail
152kms_plane@plane-panning-top-left,Fail
153kms_plane@plane-position-covered,Fail
154kms_plane@plane-position-hole,Fail
155kms_plane@plane-position-hole-dpms,Fail
14kms_plane_alpha_blend@alpha-7efc,Fail156kms_plane_alpha_blend@alpha-7efc,Fail
157kms_plane_alpha_blend@alpha-basic,Fail
158kms_plane_alpha_blend@alpha-opaque-fb,Fail
159kms_plane_alpha_blend@alpha-transparent-fb,Fail
160kms_plane_alpha_blend@constant-alpha-max,Fail
161kms_plane_alpha_blend@constant-alpha-mid,Fail
162kms_plane_alpha_blend@constant-alpha-min,Fail
15kms_plane_alpha_blend@coverage-7efc,Fail163kms_plane_alpha_blend@coverage-7efc,Fail
16kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail164kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail
165kms_plane_cursor@primary,Fail
166kms_plane_lowres@tiling-none,Fail
167kms_plane_multiple@tiling-none,Fail
17kms_rmfb@close-fd,Fail168kms_rmfb@close-fd,Fail
18kms_universal_plane@universal-plane-sanity,Fail169kms_rotation_crc@cursor-rotation-180,Fail
170kms_rotation_crc@primary-rotation-180,Fail
171kms_sequence@get-busy,Fail
172kms_sequence@get-forked,Fail
173kms_sequence@get-forked-busy,Fail
174kms_sequence@get-idle,Fail
175kms_sequence@queue-busy,Fail
176kms_sequence@queue-idle,Fail
177kms_vblank@accuracy-idle,Fail
178kms_vblank@crtc-id,Fail
179kms_vblank@query-busy,Fail
180kms_vblank@query-forked,Fail
181kms_vblank@query-forked-busy,Fail
182kms_vblank@query-idle,Fail
183kms_vblank@ts-continuation-dpms-rpm,Fail
184kms_vblank@ts-continuation-idle,Fail
185kms_vblank@ts-continuation-modeset,Fail
186kms_vblank@ts-continuation-modeset-rpm,Fail
187kms_vblank@wait-busy,Fail
188kms_vblank@wait-forked,Fail
189kms_vblank@wait-forked-busy,Fail
190kms_vblank@wait-idle,Fail
191tools_test@tools_test,Fail
drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-flakes.txt+8−0
@@ -0,0 +1,8 @@
1# Board Name: sc7180-trogdor-kingoftown
2# Bug Report: https://lore.kernel.org/linux-arm-msm/661483c8-ad82-400d-bcd8-e94986d20d7d@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
5# Failure Rate: 50
6msm_mapping@shadow
7msm_shrink@copy-gpu-oom-32
8msm_shrink@copy-gpu-oom-8
drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-skips.txt+19−0
@@ -1,2 +1,21 @@
1# Suspend to RAM seems to be broken on this machine1# Suspend to RAM seems to be broken on this machine
2.*suspend.*2.*suspend.*
3
4# Skip driver specific tests
5^amdgpu.*
6nouveau_.*
7panfrost_.*
8^v3d.*
9^vc4.*
10^vmwgfx*
11
12# Skip intel specific tests
13gem_.*
14i915_.*
15
16# Currently fails and causes coverage loss for other tests
17# since core_getversion also fails.
18core_hotunplug.*
19
20# Timeout occurs
21kms_flip@2x-wf_vblank-ts-check
drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-fails.txt+174−1
@@ -1,18 +1,191 @@
1device_reset@cold-reset-bound,Fail
2device_reset@reset-bound,Fail
3device_reset@unbind-cold-reset-rebind,Fail
4device_reset@unbind-reset-rebind,Fail
5dumb_buffer@invalid-bpp,Fail
6kms_atomic_transition@plane-primary-toggle-with-vblank-wait,Fail
1kms_color@ctm-0-25,Fail7kms_color@ctm-0-25,Fail
2kms_color@ctm-0-50,Fail8kms_color@ctm-0-50,Fail
3kms_color@ctm-0-75,Fail9kms_color@ctm-0-75,Fail
4kms_color@ctm-blue-to-red,Fail10kms_color@ctm-blue-to-red,Fail
5kms_color@ctm-green-to-red,Fail11kms_color@ctm-green-to-red,Fail
12kms_color@ctm-max,Fail
6kms_color@ctm-negative,Fail13kms_color@ctm-negative,Fail
7kms_color@ctm-red-to-blue,Fail14kms_color@ctm-red-to-blue,Fail
8kms_color@ctm-signed,Fail15kms_color@ctm-signed,Fail
16kms_content_protection@atomic,Crash
17kms_content_protection@atomic-dpms,Crash
18kms_content_protection@content-type-change,Crash
19kms_content_protection@lic-type-0,Crash
20kms_content_protection@lic-type-1,Crash
21kms_content_protection@srm,Crash
22kms_content_protection@type1,Crash
23kms_content_protection@uevent,Crash
24kms_cursor_crc@cursor-alpha-opaque,Fail
25kms_cursor_crc@cursor-alpha-transparent,Fail
26kms_cursor_crc@cursor-dpms,Fail
27kms_cursor_crc@cursor-offscreen-128x128,Fail
28kms_cursor_crc@cursor-offscreen-128x42,Fail
29kms_cursor_crc@cursor-offscreen-256x256,Fail
30kms_cursor_crc@cursor-offscreen-256x85,Fail
31kms_cursor_crc@cursor-offscreen-32x10,Fail
32kms_cursor_crc@cursor-offscreen-32x32,Fail
33kms_cursor_crc@cursor-offscreen-512x170,Fail
34kms_cursor_crc@cursor-offscreen-512x512,Fail
35kms_cursor_crc@cursor-offscreen-64x21,Fail
36kms_cursor_crc@cursor-offscreen-64x64,Fail
37kms_cursor_crc@cursor-onscreen-128x128,Fail
38kms_cursor_crc@cursor-onscreen-128x42,Fail
39kms_cursor_crc@cursor-onscreen-256x256,Fail
40kms_cursor_crc@cursor-onscreen-256x85,Fail
41kms_cursor_crc@cursor-onscreen-32x10,Fail
42kms_cursor_crc@cursor-onscreen-32x32,Fail
43kms_cursor_crc@cursor-onscreen-512x170,Fail
44kms_cursor_crc@cursor-onscreen-512x512,Fail
45kms_cursor_crc@cursor-onscreen-64x21,Fail
46kms_cursor_crc@cursor-onscreen-64x64,Fail
47kms_cursor_crc@cursor-random-128x128,Fail
48kms_cursor_crc@cursor-random-128x42,Fail
49kms_cursor_crc@cursor-random-256x256,Fail
50kms_cursor_crc@cursor-random-256x85,Fail
51kms_cursor_crc@cursor-random-32x10,Fail
52kms_cursor_crc@cursor-random-32x32,Fail
53kms_cursor_crc@cursor-random-512x170,Fail
54kms_cursor_crc@cursor-random-512x512,Fail
55kms_cursor_crc@cursor-random-64x21,Fail
56kms_cursor_crc@cursor-random-64x64,Fail
57kms_cursor_crc@cursor-rapid-movement-128x128,Fail
58kms_cursor_crc@cursor-rapid-movement-128x42,Fail
59kms_cursor_crc@cursor-rapid-movement-256x256,Fail
60kms_cursor_crc@cursor-rapid-movement-256x85,Fail
61kms_cursor_crc@cursor-rapid-movement-32x10,Fail
62kms_cursor_crc@cursor-rapid-movement-32x32,Fail
63kms_cursor_crc@cursor-rapid-movement-512x170,Fail
64kms_cursor_crc@cursor-rapid-movement-512x512,Fail
65kms_cursor_crc@cursor-rapid-movement-64x21,Fail
66kms_cursor_crc@cursor-rapid-movement-64x64,Fail
67kms_cursor_crc@cursor-size-change,Fail
68kms_cursor_crc@cursor-sliding-128x128,Fail
69kms_cursor_crc@cursor-sliding-128x42,Fail
70kms_cursor_crc@cursor-sliding-256x256,Fail
71kms_cursor_crc@cursor-sliding-256x85,Fail
72kms_cursor_crc@cursor-sliding-32x10,Fail
73kms_cursor_crc@cursor-sliding-32x32,Fail
74kms_cursor_crc@cursor-sliding-512x170,Fail
75kms_cursor_crc@cursor-sliding-512x512,Fail
76kms_cursor_crc@cursor-sliding-64x21,Fail
77kms_cursor_crc@cursor-sliding-64x64,Fail
78kms_cursor_edge_walk@128x128-left-edge,Fail
79kms_cursor_edge_walk@128x128-right-edge,Fail
80kms_cursor_edge_walk@128x128-top-bottom,Fail
81kms_cursor_edge_walk@128x128-top-edge,Fail
82kms_cursor_edge_walk@256x256-left-edge,Fail
83kms_cursor_edge_walk@256x256-right-edge,Fail
84kms_cursor_edge_walk@256x256-top-bottom,Fail
85kms_cursor_edge_walk@256x256-top-edge,Fail
86kms_cursor_edge_walk@64x64-left-edge,Fail
87kms_cursor_edge_walk@64x64-right-edge,Fail
88kms_cursor_edge_walk@64x64-top-bottom,Fail
89kms_cursor_edge_walk@64x64-top-edge,Fail
90kms_cursor_legacy@2x-cursor-vs-flip-atomic,Fail
91kms_cursor_legacy@2x-cursor-vs-flip-legacy,Fail
92kms_cursor_legacy@2x-flip-vs-cursor-atomic,Fail
93kms_cursor_legacy@2x-flip-vs-cursor-legacy,Fail
94kms_cursor_legacy@2x-long-cursor-vs-flip-atomic,Fail
95kms_cursor_legacy@2x-long-cursor-vs-flip-legacy,Fail
96kms_cursor_legacy@2x-long-flip-vs-cursor-atomic,Fail
97kms_cursor_legacy@2x-long-flip-vs-cursor-legacy,Fail
9kms_cursor_legacy@cursor-vs-flip-toggle,Fail98kms_cursor_legacy@cursor-vs-flip-toggle,Fail
10kms_cursor_legacy@cursor-vs-flip-varying-size,Fail99kms_cursor_legacy@cursor-vs-flip-varying-size,Fail
100kms_display_modes@extended-mode-basic,Fail
101kms_flip@2x-flip-vs-modeset-vs-hang,Fail
102kms_flip@2x-flip-vs-panning-vs-hang,Fail
103kms_flip@absolute-wf_vblank,Fail
104kms_flip@absolute-wf_vblank-interruptible,Fail
105kms_flip@basic-flip-vs-wf_vblank,Fail
106kms_flip@basic-plain-flip,Fail
107kms_flip@blocking-absolute-wf_vblank,Fail
108kms_flip@blocking-absolute-wf_vblank-interruptible,Fail
109kms_flip@blocking-wf_vblank,Fail
110kms_flip@busy-flip,Fail
111kms_flip@dpms-off-confusion,Fail
112kms_flip@dpms-off-confusion-interruptible,Fail
113kms_flip@dpms-vs-vblank-race,Fail
114kms_flip@dpms-vs-vblank-race-interruptible,Fail
115kms_flip@flip-vs-absolute-wf_vblank,Fail
116kms_flip@flip-vs-absolute-wf_vblank-interruptible,Fail
117kms_flip@flip-vs-blocking-wf-vblank,Fail
118kms_flip@flip-vs-expired-vblank,Fail
119kms_flip@flip-vs-expired-vblank-interruptible,Fail
11kms_flip@flip-vs-modeset-vs-hang,Fail120kms_flip@flip-vs-modeset-vs-hang,Fail
121kms_flip@flip-vs-panning,Fail
122kms_flip@flip-vs-panning-interruptible,Fail
12kms_flip@flip-vs-panning-vs-hang,Fail123kms_flip@flip-vs-panning-vs-hang,Fail
124kms_flip@flip-vs-rmfb,Fail
125kms_flip@flip-vs-rmfb-interruptible,Fail
126kms_flip@flip-vs-wf_vblank-interruptible,Fail
127kms_flip@modeset-vs-vblank-race,Fail
128kms_flip@modeset-vs-vblank-race-interruptible,Fail
129kms_flip@plain-flip-fb-recreate,Fail
130kms_flip@plain-flip-fb-recreate-interruptible,Fail
131kms_flip@plain-flip-interruptible,Fail
132kms_flip@plain-flip-ts-check,Fail
133kms_flip@plain-flip-ts-check-interruptible,Fail
134kms_flip@wf_vblank-ts-check,Fail
135kms_flip@wf_vblank-ts-check-interruptible,Fail
136kms_lease@cursor-implicit-plane,Fail
137kms_lease@lease-uevent,Fail
138kms_lease@page-flip-implicit-plane,Fail
139kms_lease@setcrtc-implicit-plane,Fail
140kms_lease@simple-lease,Fail
141kms_multipipe_modeset@basic-max-pipe-crc-check,Fail
13kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail142kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail
143kms_pipe_crc_basic@compare-crc-sanitycheck-xr24,Fail
144kms_pipe_crc_basic@disable-crc-after-crtc,Fail
145kms_pipe_crc_basic@nonblocking-crc,Fail
146kms_pipe_crc_basic@nonblocking-crc-frame-sequence,Fail
147kms_pipe_crc_basic@read-crc,Fail
148kms_pipe_crc_basic@read-crc-frame-sequence,Fail
149kms_plane@pixel-format,Fail
150kms_plane@pixel-format-source-clamping,Fail
151kms_plane@plane-panning-bottom-right,Fail
152kms_plane@plane-panning-top-left,Fail
153kms_plane@plane-position-covered,Fail
154kms_plane@plane-position-hole,Fail
155kms_plane@plane-position-hole-dpms,Fail
14kms_plane_alpha_blend@alpha-7efc,Fail156kms_plane_alpha_blend@alpha-7efc,Fail
157kms_plane_alpha_blend@alpha-basic,Fail
158kms_plane_alpha_blend@alpha-opaque-fb,Fail
159kms_plane_alpha_blend@alpha-transparent-fb,Fail
160kms_plane_alpha_blend@constant-alpha-max,Fail
161kms_plane_alpha_blend@constant-alpha-mid,Fail
162kms_plane_alpha_blend@constant-alpha-min,Fail
15kms_plane_alpha_blend@coverage-7efc,Fail163kms_plane_alpha_blend@coverage-7efc,Fail
16kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail164kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail
165kms_plane_cursor@primary,Fail
166kms_plane_lowres@tiling-none,Fail
167kms_plane_multiple@tiling-none,Fail
17kms_rmfb@close-fd,Fail168kms_rmfb@close-fd,Fail
18kms_universal_plane@universal-plane-sanity,Fail169kms_rotation_crc@cursor-rotation-180,Fail
170kms_rotation_crc@primary-rotation-180,Fail
171kms_sequence@get-busy,Fail
172kms_sequence@get-forked,Fail
173kms_sequence@get-forked-busy,Fail
174kms_sequence@get-idle,Fail
175kms_sequence@queue-busy,Fail
176kms_sequence@queue-idle,Fail
177kms_vblank@accuracy-idle,Fail
178kms_vblank@crtc-id,Fail
179kms_vblank@query-busy,Fail
180kms_vblank@query-forked,Fail
181kms_vblank@query-forked-busy,Fail
182kms_vblank@query-idle,Fail
183kms_vblank@ts-continuation-dpms-rpm,Fail
184kms_vblank@ts-continuation-idle,Fail
185kms_vblank@ts-continuation-modeset,Fail
186kms_vblank@ts-continuation-modeset-rpm,Fail
187kms_vblank@wait-busy,Fail
188kms_vblank@wait-forked,Fail
189kms_vblank@wait-forked-busy,Fail
190kms_vblank@wait-idle,Fail
191tools_test@tools_test,Fail
drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-flakes.txt+6−0
@@ -0,0 +1,6 @@
1# Board Name: sc7180-trogdor-lazor-limozeen-nots-r5
2# Bug Report: https://lore.kernel.org/linux-arm-msm/661483c8-ad82-400d-bcd8-e94986d20d7d@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
5# Failure Rate: 50
6msm_mapping@shadow
drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-skips.txt+16−0
@@ -1,2 +1,18 @@
1# Suspend to RAM seems to be broken on this machine1# Suspend to RAM seems to be broken on this machine
2.*suspend.*2.*suspend.*
3
4# Skip driver specific tests
5^amdgpu.*
6nouveau_.*
7panfrost_.*
8^v3d.*
9^vc4.*
10^vmwgfx*
11
12# Skip intel specific tests
13gem_.*
14i915_.*
15
16# Currently fails and causes coverage loss for other tests
17# since core_getversion also fails.
18core_hotunplug.*
drivers/gpu/drm/ci/xfails/msm-sdm845-fails.txt+7−31
@@ -1,3 +1,8 @@
1device_reset@cold-reset-bound,Fail
2device_reset@reset-bound,Fail
3device_reset@unbind-cold-reset-rebind,Fail
4device_reset@unbind-reset-rebind,Fail
5dumb_buffer@invalid-bpp,Fail
1kms_color@ctm-0-25,Fail6kms_color@ctm-0-25,Fail
2kms_color@ctm-0-50,Fail7kms_color@ctm-0-50,Fail
3kms_color@ctm-0-75,Fail8kms_color@ctm-0-75,Fail
@@ -6,17 +11,6 @@ kms_color@ctm-green-to-red,Fail · 2 unmodified lines
6kms_color@ctm-negative,Fail11kms_color@ctm-negative,Fail
7kms_color@ctm-red-to-blue,Fail12kms_color@ctm-red-to-blue,Fail
8kms_color@ctm-signed,Fail13kms_color@ctm-signed,Fail
9kms_color@pipe-A-ctm-0-25,Fail
10kms_color@pipe-A-ctm-0-5,Fail
11kms_color@pipe-A-ctm-0-75,Fail
12kms_color@pipe-A-ctm-blue-to-red,Fail
13kms_color@pipe-A-ctm-green-to-red,Fail
14kms_color@pipe-A-ctm-max,Fail
15kms_color@pipe-A-ctm-negative,Fail
16kms_color@pipe-A-ctm-red-to-blue,Fail
17kms_color@pipe-A-legacy-gamma,Fail
18kms_cursor_legacy@basic-flip-after-cursor-atomic,Fail
19kms_cursor_legacy@basic-flip-after-cursor-varying-size,Fail
20kms_cursor_legacy@basic-flip-before-cursor-atomic,Fail14kms_cursor_legacy@basic-flip-before-cursor-atomic,Fail
21kms_cursor_legacy@basic-flip-before-cursor-legacy,Fail15kms_cursor_legacy@basic-flip-before-cursor-legacy,Fail
22kms_cursor_legacy@cursor-vs-flip-atomic,Fail16kms_cursor_legacy@cursor-vs-flip-atomic,Fail
@@ -31,30 +25,12 @@ kms_cursor_legacy@flip-vs-cursor-crc-legacy,Fail · 8 unmodified lines
31kms_cursor_legacy@flip-vs-cursor-legacy,Fail25kms_cursor_legacy@flip-vs-cursor-legacy,Fail
32kms_flip@flip-vs-modeset-vs-hang,Fail26kms_flip@flip-vs-modeset-vs-hang,Fail
33kms_flip@flip-vs-panning-vs-hang,Fail27kms_flip@flip-vs-panning-vs-hang,Fail
28kms_lease@lease-uevent,Fail
34kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail29kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail
35kms_plane_alpha_blend@alpha-7efc,Fail30kms_plane_alpha_blend@alpha-7efc,Fail
36kms_plane_alpha_blend@coverage-7efc,Fail31kms_plane_alpha_blend@coverage-7efc,Fail
37kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail32kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail
38kms_plane_alpha_blend@pipe-A-alpha-7efc,Fail
39kms_plane_alpha_blend@pipe-A-coverage-7efc,Fail
40kms_plane_alpha_blend@pipe-A-coverage-vs-premult-vs-constant,Fail
41kms_plane_cursor@overlay,Fail33kms_plane_cursor@overlay,Fail
42kms_plane_cursor@pipe-A-overlay-size-128,Fail
43kms_plane_cursor@pipe-A-overlay-size-256,Fail
44kms_plane_cursor@pipe-A-overlay-size-64,Fail
45kms_plane_cursor@pipe-A-viewport-size-128,Fail
46kms_plane_cursor@pipe-A-viewport-size-256,Fail
47kms_plane_cursor@pipe-A-viewport-size-64,Fail
48kms_plane_cursor@viewport,Fail34kms_plane_cursor@viewport,Fail
49kms_plane_scaling@downscale-with-pixel-format-factor-0-25,Timeout
50kms_plane_scaling@downscale-with-pixel-format-factor-0-5,Timeout
51kms_plane_scaling@downscale-with-pixel-format-factor-0-75,Timeout
52kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25,Timeout
53kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5,Timeout
54kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75,Timeout
55kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats,Timeout
56kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling,Timeout
57kms_plane_scaling@planes-downscale-factor-0-25,Fail
58kms_plane_scaling@scaler-with-clipping-clamping,Timeout
59kms_plane_scaling@scaler-with-pixel-format-unity-scaling,Timeout
60kms_rmfb@close-fd,Fail35kms_rmfb@close-fd,Fail
36tools_test@tools_test,Fail
drivers/gpu/drm/ci/xfails/msm-sdm845-flakes.txt+11−14
@@ -1,22 +1,19 @@
1# Board Name: msm:sdm8451# Board Name: sdm845-cheza-r3
2# Bug Report: https://lore.kernel.org/dri-devel/46287831-edfa-78e8-6055-d7a08831c445@collabora.com/T/#u2# Bug Report: https://lore.kernel.org/linux-arm-msm/661483c8-ad82-400d-bcd8-e94986d20d7d@collabora.com/T/#u
3# IGT Version: 1.28-g0df7b9b97
4# Linux Version: 6.9.0-rc7
3# Failure Rate: 505# Failure Rate: 50
4# IGT Version: 1.28-gd2af13d9f6kms_cursor_legacy@basic-flip-after-cursor-atomic
5# Linux Version: 6.7.0-rc3
6
7# Reported by deqp-runner
8kms_cursor_legacy@basic-flip-after-cursor-legacy7kms_cursor_legacy@basic-flip-after-cursor-legacy
9kms_cursor_legacy@flip-vs-cursor-toggle8kms_cursor_legacy@basic-flip-after-cursor-varying-size
9kms_cursor_legacy@basic-flip-before-cursor-varying-size
10kms_cursor_legacy@flip-vs-cursor-atomic-transitions
11kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size
10kms_cursor_legacy@flip-vs-cursor-varying-size12kms_cursor_legacy@flip-vs-cursor-varying-size
13kms_cursor_legacy@short-flip-after-cursor-atomic-transitions
14kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size
11kms_cursor_legacy@short-flip-after-cursor-toggle15kms_cursor_legacy@short-flip-after-cursor-toggle
12kms_cursor_legacy@short-flip-before-cursor-atomic-transitions16kms_cursor_legacy@short-flip-before-cursor-atomic-transitions
13kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size17kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size
14msm_shrink@copy-gpu-3218msm_shrink@copy-gpu-32
15msm_shrink@copy-gpu-oom-3219msm_shrink@copy-gpu-oom-32
16
17# The below test shows inconsistency across multiple runs, giving
18# results of Pass and Fail alternately.
19kms_cursor_legacy@basic-flip-before-cursor-varying-size
20kms_cursor_legacy@flip-vs-cursor-atomic-transitions
21kms_cursor_legacy@short-flip-after-cursor-atomic-transitions
22kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size
drivers/gpu/drm/ci/xfails/msm-sdm845-skips.txt+19−0
@@ -5,3 +5,22 @@ kms_bw.* · 4 unmodified lines
5# https://gitlab.freedesktop.org/gfx-ci/linux/-/commit/4b49f902ec6f2bb382cbbf489870573f4b43371e5# https://gitlab.freedesktop.org/gfx-ci/linux/-/commit/4b49f902ec6f2bb382cbbf489870573f4b43371e
6# https://gitlab.freedesktop.org/gfx-ci/linux/-/commit/38cdf4c5559771e2474ae0fecef8469f65147bc16# https://gitlab.freedesktop.org/gfx-ci/linux/-/commit/38cdf4c5559771e2474ae0fecef8469f65147bc1
7msm_mapping@*7msm_mapping@*
8
9# Skip driver specific tests
10^amdgpu.*
11nouveau_.*
12panfrost_.*
13^v3d.*
14^vc4.*
15^vmwgfx*
16
17# Skip intel specific tests
18gem_.*
19i915_.*
20
21# Currently fails and causes coverage loss for other tests
22# since core_getversion also fails.
23core_hotunplug.*
24
25# Whole machine hangs
26kms_cursor_crc.*
drivers/gpu/drm/ci/xfails/rockchip-rk3288-fails.txt+8−54
@@ -1,54 +1,8 @@
1kms_3d,Crash1dumb_buffer@create-clear,Crash
2kms_bw@linear-tiling-2-displays-1920x1080p,Fail2dumb_buffer@create-valid-dumb,Crash
3kms_bw@linear-tiling-2-displays-2560x1440p,Fail3dumb_buffer@invalid-bpp,Crash
4kms_bw@linear-tiling-2-displays-3840x2160p,Fail4dumb_buffer@map-invalid-size,Crash
5kms_bw@linear-tiling-3-displays-1920x1080p,Fail5dumb_buffer@map-uaf,Crash
6kms_bw@linear-tiling-3-displays-2560x1440p,Fail6dumb_buffer@map-valid,Crash
7kms_bw@linear-tiling-3-displays-3840x2160p,Fail7panfrost_prime@gem-prime-import,Crash
8kms_flip@flip-vs-modeset-vs-hang,Crash8tools_test@tools_test,Crash
9kms_flip@flip-vs-panning-vs-hang,Crash
10kms_force_connector_basic@force-load-detect,Fail
11kms_invalid_mode@int-max-clock,Crash
12kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Crash
13kms_pipe_crc_basic@nonblocking-crc-frame-sequence,Crash
14kms_pipe_crc_basic@read-crc-frame-sequence,Crash
15kms_plane@pixel-format,Crash
16kms_plane@pixel-format-source-clamping,Crash
17kms_plane@plane-position-hole,Crash
18kms_plane@plane-position-hole-dpms,Crash
19kms_plane_cursor@overlay,Crash
20kms_plane_cursor@pipe-A-overlay-size-128,Fail
21kms_plane_cursor@pipe-A-overlay-size-256,Fail
22kms_plane_cursor@pipe-A-overlay-size-64,Fail
23kms_plane_cursor@pipe-A-primary-size-128,Fail
24kms_plane_cursor@pipe-A-primary-size-256,Fail
25kms_plane_cursor@pipe-A-primary-size-64,Fail
26kms_plane_cursor@pipe-A-viewport-size-128,Fail
27kms_plane_cursor@pipe-A-viewport-size-256,Fail
28kms_plane_cursor@pipe-A-viewport-size-64,Fail
29kms_plane_cursor@pipe-B-overlay-size-128,Fail
30kms_plane_cursor@pipe-B-overlay-size-256,Fail
31kms_plane_cursor@pipe-B-overlay-size-64,Fail
32kms_plane_cursor@pipe-B-primary-size-128,Fail
33kms_plane_cursor@pipe-B-primary-size-256,Fail
34kms_plane_cursor@pipe-B-primary-size-64,Fail
35kms_plane_cursor@pipe-B-viewport-size-128,Fail
36kms_plane_cursor@pipe-B-viewport-size-256,Fail
37kms_plane_cursor@pipe-B-viewport-size-64,Fail
38kms_plane_cursor@primary,Crash
39kms_plane_cursor@viewport,Crash
40kms_plane_lowres@tiling-none,Fail
41kms_plane_scaling@downscale-with-modifier-factor-0-25,Fail
42kms_plane_scaling@downscale-with-rotation-factor-0-25,Fail
43kms_plane_scaling@upscale-with-modifier-20x20,Fail
44kms_plane_scaling@upscale-with-modifier-factor-0-25,Fail
45kms_plane_scaling@upscale-with-pixel-format-20x20,Fail
46kms_plane_scaling@upscale-with-pixel-format-factor-0-25,Fail
47kms_plane_scaling@upscale-with-rotation-20x20,Fail
48kms_prime@basic-crc,Fail
49kms_properties@connector-properties-atomic,Crash
50kms_properties@connector-properties-legacy,Crash
51kms_properties@get_properties-sanity-atomic,Crash
52kms_properties@get_properties-sanity-non-atomic,Crash
53kms_rmfb@close-fd,Crash
54kms_setmode@invalid-clone-single-crtc,Crash
drivers/gpu/drm/ci/xfails/rockchip-rk3288-skips.txt+20−1
@@ -49,4 +49,23 @@ kms_plane_lowres@pipe-F-tiling-y · 48 unmodified lines
49kms_cursor_crc.*49kms_cursor_crc.*
50 50
51# Machine is hanging in this test, so skip it51# Machine is hanging in this test, so skip it
52kms_pipe_crc_basic@disable-crc-after-crtc52kms_pipe_crc_basic@disable-crc-after-crtc
53
54# Skip driver specific tests
55^amdgpu.*
56msm_.*
57nouveau_.*
58^v3d.*
59^vc4.*
60^vmwgfx*
61
62# Skip intel specific tests
63gem_.*
64i915_.*
65
66# Panfrost is not a KMS driver, so skip the KMS tests
67kms_.*
68
69# Currently fails and causes coverage loss for other tests
70# since core_getversion also fails.
71core_hotunplug.*
drivers/gpu/drm/ci/xfails/rockchip-rk3399-fails.txt+8−75
@@ -1,75 +1,8 @@
1kms_color@gamma,Fail1dumb_buffer@create-clear,Fail
2kms_color@legacy-gamma,Fail2dumb_buffer@create-valid-dumb,Fail
3kms_color@pipe-A-legacy-gamma,Fail3dumb_buffer@invalid-bpp,Fail
4kms_color@pipe-B-legacy-gamma,Fail4dumb_buffer@map-invalid-size,Fail
5kms_cursor_crc@cursor-alpha-opaque,Fail5dumb_buffer@map-uaf,Fail
6kms_cursor_crc@cursor-alpha-transparent,Fail6dumb_buffer@map-valid,Fail
7kms_cursor_crc@cursor-dpms,Fail7panfrost_prime@gem-prime-import,Fail
8kms_cursor_crc@cursor-offscreen-32x10,Fail8tools_test@tools_test,Fail
9kms_cursor_crc@cursor-offscreen-32x32,Fail
10kms_cursor_crc@cursor-offscreen-64x64,Fail
11kms_cursor_crc@cursor-onscreen-32x10,Fail
12kms_cursor_crc@cursor-onscreen-32x32,Fail
13kms_cursor_crc@cursor-onscreen-64x21,Fail
14kms_cursor_crc@cursor-onscreen-64x64,Fail
15kms_cursor_crc@cursor-random-32x10,Fail
16kms_cursor_crc@cursor-random-32x32,Fail
17kms_cursor_crc@cursor-random-64x21,Fail
18kms_cursor_crc@cursor-random-64x64,Fail
19kms_cursor_crc@cursor-rapid-movement-32x32,Fail
20kms_cursor_crc@cursor-rapid-movement-64x21,Fail
21kms_cursor_crc@cursor-rapid-movement-64x64,Fail
22kms_cursor_crc@cursor-size-change,Fail
23kms_cursor_crc@cursor-sliding-32x10,Fail
24kms_cursor_crc@cursor-sliding-32x32,Fail
25kms_cursor_crc@cursor-sliding-64x21,Fail
26kms_cursor_crc@cursor-sliding-64x64,Fail
27kms_flip@basic-flip-vs-wf_vblank,Fail
28kms_flip@blocking-wf_vblank,Fail
29kms_flip@dpms-vs-vblank-race,Fail
30kms_flip@flip-vs-absolute-wf_vblank,Fail
31kms_flip@flip-vs-absolute-wf_vblank-interruptible,Fail
32kms_flip@flip-vs-blocking-wf-vblank,Fail
33kms_flip@flip-vs-modeset-vs-hang,Fail
34kms_flip@flip-vs-panning,Fail
35kms_flip@flip-vs-panning-interruptible,Fail
36kms_flip@flip-vs-panning-vs-hang,Fail
37kms_flip@modeset-vs-vblank-race,Fail
38kms_flip@plain-flip-fb-recreate,Fail
39kms_flip@plain-flip-fb-recreate-interruptible,Fail
40kms_flip@plain-flip-ts-check,Fail
41kms_flip@plain-flip-ts-check-interruptible,Fail
42kms_flip@wf_vblank-ts-check,Fail
43kms_flip@wf_vblank-ts-check-interruptible,Fail
44kms_invalid_mode@int-max-clock,Fail
45kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail
46kms_pipe_crc_basic@compare-crc-sanitycheck-xr24,Fail
47kms_pipe_crc_basic@disable-crc-after-crtc,Fail
48kms_pipe_crc_basic@nonblocking-crc,Fail
49kms_pipe_crc_basic@nonblocking-crc-frame-sequence,Fail
50kms_pipe_crc_basic@read-crc,Fail
51kms_pipe_crc_basic@read-crc-frame-sequence,Fail
52kms_plane@pixel-format,Fail
53kms_plane@pixel-format-source-clamping,Fail
54kms_plane@plane-panning-bottom-right,Fail
55kms_plane@plane-panning-top-left,Fail
56kms_plane@plane-position-covered,Fail
57kms_plane@plane-position-hole,Fail
58kms_plane@plane-position-hole-dpms,Fail
59kms_plane_cursor@overlay,Fail
60kms_plane_cursor@pipe-B-overlay-size-128,Fail
61kms_plane_cursor@pipe-B-overlay-size-256,Fail
62kms_plane_cursor@pipe-B-overlay-size-64,Fail
63kms_plane_cursor@pipe-B-primary-size-128,Fail
64kms_plane_cursor@pipe-B-primary-size-256,Fail
65kms_plane_cursor@pipe-B-primary-size-64,Fail
66kms_plane_cursor@pipe-B-viewport-size-128,Fail
67kms_plane_cursor@pipe-B-viewport-size-256,Fail
68kms_plane_cursor@pipe-B-viewport-size-64,Fail
69kms_plane_cursor@primary,Fail
70kms_plane_cursor@viewport,Fail
71kms_plane_multiple@atomic-pipe-B-tiling-none,Fail
72kms_plane_multiple@tiling-none,Fail
73kms_prime@basic-crc,Fail
74kms_rmfb@close-fd,Fail
75kms_universal_plane@universal-plane-pipe-B-functional,Fail
drivers/gpu/drm/ci/xfails/rockchip-rk3399-flakes.txt+6−7
@@ -1,7 +1,6 @@
1kms_bw@linear-tiling-2-displays-1920x1080p1# Board Name: rk3399-gru-kevin
2kms_cursor_crc@cursor-offscreen-64x212# Bug Report: https://lore.kernel.org/dri-devel/5cc34a8b-c1fa-4744-9031-2d33ecf41011@collabora.com/T/#u
3kms_flip@dpms-vs-vblank-race-interruptible3# IGT Version: 1.28-g0df7b9b97
4kms_flip@flip-vs-wf_vblank-interruptible4# Linux Version: 6.9.0-rc7
5kms_plane_cursor@overlay5# Failure Rate: 50
6kms_plane_cursor@primary6panfrost_submit@pan-unhandled-pagefault
7kms_plane_cursor@viewport
drivers/gpu/drm/ci/xfails/rockchip-rk3399-skips.txt+19−0
@@ -3,3 +3,22 @@ · 2 unmodified lines
3 3
4# Too unstable, machine ends up hanging after lots of Oopses4# Too unstable, machine ends up hanging after lots of Oopses
5kms_cursor_legacy.*5kms_cursor_legacy.*
6
7# Skip driver specific tests
8^amdgpu.*
9msm_.*
10nouveau_.*
11^v3d.*
12^vc4.*
13^vmwgfx*
14
15# Skip intel specific tests
16gem_.*
17i915_.*
18
19# Panfrost is not a KMS driver, so skip the KMS tests
20kms_.*
21
22# Currently fails and causes coverage loss for other tests
23# since core_getversion also fails.
24core_hotunplug.*
drivers/gpu/drm/ci/xfails/update-xfails.py+2−2
@@ -93,10 +93,10 @@ def add_unit_test_or_update_result_to_fails_if_present(fails_txt, unit_test, fai · 92 unmodified lines
93def split_unit_test_from_collate(xfails):93def split_unit_test_from_collate(xfails):
94 for job_name in xfails.keys():94 for job_name in xfails.keys():
95 for job_id in xfails[job_name].copy().keys():95 for job_id in xfails[job_name].copy().keys():
96 if "not found" in xfails[job_name][job_id]:96 if "not found" in xfails[job_name][job_id].content_as_str:
97 del xfails[job_name][job_id]97 del xfails[job_name][job_id]
98 continue98 continue
99 xfails[job_name][job_id] = xfails[job_name][job_id].strip().split("\n")99 xfails[job_name][job_id] = xfails[job_name][job_id].content_as_str.splitlines()
100 100
101 101
102def get_xfails_from_pipeline_url(pipeline_url):102def get_xfails_from_pipeline_url(pipeline_url):
drivers/gpu/drm/ci/xfails/virtio_gpu-none-fails.txt+68−26
@@ -1,33 +1,72 @@
1kms_addfb_basic@addfb25-bad-modifier,Fail
2kms_addfb_basic@bad-pitch-65536,Fail1kms_addfb_basic@bad-pitch-65536,Fail
3kms_addfb_basic@bo-too-small,Fail2kms_addfb_basic@bo-too-small,Fail
4kms_addfb_basic@size-max,Fail3kms_addfb_basic@size-max,Fail
5kms_addfb_basic@too-high,Fail4kms_addfb_basic@too-high,Fail
6kms_atomic_transition@plane-primary-toggle-with-vblank-wait,Fail5kms_atomic_transition@plane-primary-toggle-with-vblank-wait,Fail
7kms_bw@linear-tiling-1-displays-1920x1080p,Fail6kms_bw@linear-tiling-1-displays-1920x1080p,Fail
7kms_bw@linear-tiling-1-displays-2160x1440p,Fail
8kms_bw@linear-tiling-1-displays-2560x1440p,Fail8kms_bw@linear-tiling-1-displays-2560x1440p,Fail
9kms_bw@linear-tiling-1-displays-3840x2160p,Fail9kms_bw@linear-tiling-1-displays-3840x2160p,Fail
10kms_bw@linear-tiling-10-displays-1920x1080p,Fail
11kms_bw@linear-tiling-10-displays-2160x1440p,Fail
12kms_bw@linear-tiling-10-displays-2560x1440p,Fail
13kms_bw@linear-tiling-10-displays-3840x2160p,Fail
14kms_bw@linear-tiling-11-displays-1920x1080p,Fail
15kms_bw@linear-tiling-11-displays-2160x1440p,Fail
16kms_bw@linear-tiling-11-displays-2560x1440p,Fail
17kms_bw@linear-tiling-11-displays-3840x2160p,Fail
18kms_bw@linear-tiling-12-displays-1920x1080p,Fail
19kms_bw@linear-tiling-12-displays-2160x1440p,Fail
20kms_bw@linear-tiling-12-displays-2560x1440p,Fail
21kms_bw@linear-tiling-12-displays-3840x2160p,Fail
22kms_bw@linear-tiling-13-displays-1920x1080p,Fail
23kms_bw@linear-tiling-13-displays-2160x1440p,Fail
24kms_bw@linear-tiling-13-displays-2560x1440p,Fail
25kms_bw@linear-tiling-13-displays-3840x2160p,Fail
26kms_bw@linear-tiling-14-displays-1920x1080p,Fail
27kms_bw@linear-tiling-14-displays-2160x1440p,Fail
28kms_bw@linear-tiling-14-displays-2560x1440p,Fail
29kms_bw@linear-tiling-14-displays-3840x2160p,Fail
30kms_bw@linear-tiling-15-displays-1920x1080p,Fail
31kms_bw@linear-tiling-15-displays-2160x1440p,Fail
32kms_bw@linear-tiling-15-displays-2560x1440p,Fail
33kms_bw@linear-tiling-15-displays-3840x2160p,Fail
34kms_bw@linear-tiling-16-displays-1920x1080p,Fail
35kms_bw@linear-tiling-16-displays-2160x1440p,Fail
36kms_bw@linear-tiling-16-displays-2560x1440p,Fail
37kms_bw@linear-tiling-16-displays-3840x2160p,Fail
10kms_bw@linear-tiling-2-displays-1920x1080p,Fail38kms_bw@linear-tiling-2-displays-1920x1080p,Fail
39kms_bw@linear-tiling-2-displays-2160x1440p,Fail
11kms_bw@linear-tiling-2-displays-2560x1440p,Fail40kms_bw@linear-tiling-2-displays-2560x1440p,Fail
12kms_bw@linear-tiling-2-displays-3840x2160p,Fail41kms_bw@linear-tiling-2-displays-3840x2160p,Fail
13kms_bw@linear-tiling-3-displays-1920x1080p,Fail42kms_bw@linear-tiling-3-displays-1920x1080p,Fail
43kms_bw@linear-tiling-3-displays-2160x1440p,Fail
14kms_bw@linear-tiling-3-displays-2560x1440p,Fail44kms_bw@linear-tiling-3-displays-2560x1440p,Fail
15kms_bw@linear-tiling-3-displays-3840x2160p,Fail45kms_bw@linear-tiling-3-displays-3840x2160p,Fail
16kms_bw@linear-tiling-4-displays-1920x1080p,Fail46kms_bw@linear-tiling-4-displays-1920x1080p,Fail
47kms_bw@linear-tiling-4-displays-2160x1440p,Fail
17kms_bw@linear-tiling-4-displays-2560x1440p,Fail48kms_bw@linear-tiling-4-displays-2560x1440p,Fail
18kms_bw@linear-tiling-4-displays-3840x2160p,Fail49kms_bw@linear-tiling-4-displays-3840x2160p,Fail
19kms_bw@linear-tiling-5-displays-1920x1080p,Fail50kms_bw@linear-tiling-5-displays-1920x1080p,Fail
51kms_bw@linear-tiling-5-displays-2160x1440p,Fail
20kms_bw@linear-tiling-5-displays-2560x1440p,Fail52kms_bw@linear-tiling-5-displays-2560x1440p,Fail
21kms_bw@linear-tiling-5-displays-3840x2160p,Fail53kms_bw@linear-tiling-5-displays-3840x2160p,Fail
22kms_bw@linear-tiling-6-displays-1920x1080p,Fail54kms_bw@linear-tiling-6-displays-1920x1080p,Fail
55kms_bw@linear-tiling-6-displays-2160x1440p,Fail
23kms_bw@linear-tiling-6-displays-2560x1440p,Fail56kms_bw@linear-tiling-6-displays-2560x1440p,Fail
24kms_bw@linear-tiling-6-displays-3840x2160p,Fail57kms_bw@linear-tiling-6-displays-3840x2160p,Fail
25kms_bw@linear-tiling-7-displays-1920x1080p,Fail58kms_bw@linear-tiling-7-displays-1920x1080p,Fail
59kms_bw@linear-tiling-7-displays-2160x1440p,Fail
26kms_bw@linear-tiling-7-displays-2560x1440p,Fail60kms_bw@linear-tiling-7-displays-2560x1440p,Fail
27kms_bw@linear-tiling-7-displays-3840x2160p,Fail61kms_bw@linear-tiling-7-displays-3840x2160p,Fail
28kms_bw@linear-tiling-8-displays-1920x1080p,Fail62kms_bw@linear-tiling-8-displays-1920x1080p,Fail
63kms_bw@linear-tiling-8-displays-2160x1440p,Fail
29kms_bw@linear-tiling-8-displays-2560x1440p,Fail64kms_bw@linear-tiling-8-displays-2560x1440p,Fail
30kms_bw@linear-tiling-8-displays-3840x2160p,Fail65kms_bw@linear-tiling-8-displays-3840x2160p,Fail
66kms_bw@linear-tiling-9-displays-1920x1080p,Fail
67kms_bw@linear-tiling-9-displays-2160x1440p,Fail
68kms_bw@linear-tiling-9-displays-2560x1440p,Fail
69kms_bw@linear-tiling-9-displays-3840x2160p,Fail
31kms_flip@absolute-wf_vblank,Fail70kms_flip@absolute-wf_vblank,Fail
32kms_flip@absolute-wf_vblank-interruptible,Fail71kms_flip@absolute-wf_vblank-interruptible,Fail
33kms_flip@basic-flip-vs-wf_vblank,Fail72kms_flip@basic-flip-vs-wf_vblank,Fail
@@ -54,31 +93,34 @@ kms_flip@plain-flip-ts-check-interruptible,Fail · 20 unmodified lines
54kms_flip@wf_vblank-ts-check,Fail93kms_flip@wf_vblank-ts-check,Fail
55kms_flip@wf_vblank-ts-check-interruptible,Fail94kms_flip@wf_vblank-ts-check-interruptible,Fail
56kms_invalid_mode@int-max-clock,Fail95kms_invalid_mode@int-max-clock,Fail
57kms_plane_scaling@downscale-with-modifier-factor-0-25,Fail96kms_lease@cursor-implicit-plane,Fail
58kms_plane_scaling@downscale-with-rotation-factor-0-25,Fail97kms_lease@lease-uevent,Fail
59kms_plane_scaling@planes-upscale-20x20,Fail98kms_lease@page-flip-implicit-plane,Fail
60kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25,Fail99kms_lease@setcrtc-implicit-plane,Fail
61kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5,Fail100kms_lease@simple-lease,Fail
62kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75,Fail101kms_sequence@get-busy,Fail
63kms_plane_scaling@upscale-with-modifier-20x20,Fail102kms_sequence@get-forked,Fail
64kms_plane_scaling@upscale-with-modifier-factor-0-25,Fail103kms_sequence@get-forked-busy,Fail
65kms_plane_scaling@upscale-with-pixel-format-20x20,Fail104kms_sequence@get-idle,Fail
66kms_plane_scaling@upscale-with-pixel-format-factor-0-25,Fail105kms_sequence@queue-busy,Fail
67kms_plane_scaling@upscale-with-rotation-20x20,Fail106kms_sequence@queue-idle,Fail
68kms_selftest@drm_format,Timeout
69kms_selftest@drm_format_helper,Timeout
70kms_setmode@basic,Fail107kms_setmode@basic,Fail
108kms_vblank@accuracy-idle,Fail
71kms_vblank@crtc-id,Fail109kms_vblank@crtc-id,Fail
72kms_vblank@invalid,Fail110kms_vblank@invalid,Fail
73kms_vblank@pipe-A-accuracy-idle,Fail111kms_vblank@query-busy,Fail
74kms_vblank@pipe-A-query-busy,Fail112kms_vblank@query-forked,Fail
75kms_vblank@pipe-A-query-forked,Fail113kms_vblank@query-forked-busy,Fail
76kms_vblank@pipe-A-query-forked-busy,Fail114kms_vblank@query-idle,Fail
77kms_vblank@pipe-A-query-idle,Fail115kms_vblank@ts-continuation-dpms-rpm,Fail
78kms_vblank@pipe-A-ts-continuation-idle,Fail116kms_vblank@ts-continuation-dpms-suspend,Fail
79kms_vblank@pipe-A-ts-continuation-modeset,Fail117kms_vblank@ts-continuation-idle,Fail
80kms_vblank@pipe-A-ts-continuation-suspend,Fail118kms_vblank@ts-continuation-modeset,Fail
81kms_vblank@pipe-A-wait-busy,Fail119kms_vblank@ts-continuation-modeset-rpm,Fail
82kms_vblank@pipe-A-wait-forked,Fail120kms_vblank@ts-continuation-suspend,Fail
83kms_vblank@pipe-A-wait-forked-busy,Fail121kms_vblank@wait-busy,Fail
84kms_vblank@pipe-A-wait-idle,Fail122kms_vblank@wait-forked,Fail
123kms_vblank@wait-forked-busy,Fail
124kms_vblank@wait-idle,Fail
125perf@i915-ref-count,Fail
126tools_test@tools_test,Fail
drivers/gpu/drm/ci/xfails/virtio_gpu-none-skips.txt+19−1
@@ -3,4 +3,22 @@ · 2 unmodified lines
3kms_cursor_legacy.*3kms_cursor_legacy.*
4 4
5# Job just hangs without any output5# Job just hangs without any output
6kms_flip@flip-vs-suspend.*6kms_flip@flip-vs-suspend.*
7
8# Skip driver specific tests
9^amdgpu.*
10msm_.*
11nouveau_.*
12panfrost_.*
13^v3d.*
14^vc4.*
15^vmwgfx*
16
17# Skip intel specific tests
18gem_.*
19i915_.*
20xe_.*
21
22# Currently fails and causes coverage loss for other tests
23# since core_getversion also fails.
24core_hotunplug.*
drivers/gpu/drm/ci/xfails/vkms-none-fails.txt+57−0
@@ -0,0 +1,57 @@
1core_hotunplug@hotrebind,Fail
2core_hotunplug@hotrebind-lateclose,Fail
3core_hotunplug@hotreplug,Fail
4core_hotunplug@hotreplug-lateclose,Fail
5core_hotunplug@hotunbind-rebind,Fail
6core_hotunplug@hotunplug-rescan,Fail
7core_hotunplug@unbind-rebind,Fail
8core_hotunplug@unplug-rescan,Fail
9device_reset@cold-reset-bound,Fail
10device_reset@reset-bound,Fail
11device_reset@unbind-cold-reset-rebind,Fail
12device_reset@unbind-reset-rebind,Fail
13dumb_buffer@invalid-bpp,Fail
14kms_content_protection@atomic,Crash
15kms_content_protection@atomic-dpms,Crash
16kms_content_protection@content-type-change,Crash
17kms_content_protection@lic-type-0,Crash
18kms_content_protection@lic-type-1,Crash
19kms_content_protection@srm,Crash
20kms_content_protection@type1,Crash
21kms_content_protection@uevent,Crash
22kms_cursor_crc@cursor-rapid-movement-128x128,Fail
23kms_cursor_crc@cursor-rapid-movement-128x42,Fail
24kms_cursor_crc@cursor-rapid-movement-256x256,Fail
25kms_cursor_crc@cursor-rapid-movement-256x85,Fail
26kms_cursor_crc@cursor-rapid-movement-32x10,Fail
27kms_cursor_crc@cursor-rapid-movement-32x32,Fail
28kms_cursor_crc@cursor-rapid-movement-512x170,Fail
29kms_cursor_crc@cursor-rapid-movement-512x512,Fail
30kms_cursor_crc@cursor-rapid-movement-64x21,Fail
31kms_cursor_crc@cursor-rapid-movement-64x64,Fail
32kms_cursor_legacy@basic-flip-before-cursor-atomic,Fail
33kms_cursor_legacy@basic-flip-before-cursor-legacy,Fail
34kms_cursor_legacy@cursor-vs-flip-atomic,Fail
35kms_cursor_legacy@cursor-vs-flip-legacy,Fail
36kms_cursor_legacy@cursor-vs-flip-toggle,Fail
37kms_cursor_legacy@cursor-vs-flip-varying-size,Fail
38kms_cursor_legacy@flip-vs-cursor-atomic,Fail
39kms_cursor_legacy@flip-vs-cursor-crc-atomic,Fail
40kms_cursor_legacy@flip-vs-cursor-crc-legacy,Fail
41kms_cursor_legacy@flip-vs-cursor-legacy,Fail
42kms_flip@flip-vs-modeset-vs-hang,Fail
43kms_flip@flip-vs-panning-vs-hang,Fail
44kms_flip@flip-vs-suspend,Timeout
45kms_flip@flip-vs-suspend-interruptible,Timeout
46kms_flip@plain-flip-fb-recreate,Fail
47kms_lease@lease-uevent,Fail
48kms_pipe_crc_basic@nonblocking-crc,Fail
49kms_pipe_crc_basic@nonblocking-crc-frame-sequence,Fail
50kms_writeback@writeback-check-output,Fail
51kms_writeback@writeback-check-output-XRGB2101010,Fail
52kms_writeback@writeback-fb-id,Fail
53kms_writeback@writeback-fb-id-XRGB2101010,Fail
54kms_writeback@writeback-invalid-parameters,Fail
55kms_writeback@writeback-pixel-formats,Fail
56perf@i915-ref-count,Fail
57tools_test@tools_test,Fail
drivers/gpu/drm/ci/xfails/vkms-none-flakes.txt+69−0
@@ -0,0 +1,69 @@
1# Board Name: vkms
2# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u
3# Failure Rate: 50
4# IGT Version: 1.28-g0df7b9b97
5# Linux Version: 6.9.0-rc7
6kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic
7
8# Board Name: vkms
9# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u
10# Failure Rate: 50
11# IGT Version: 1.28-g0df7b9b97
12# Linux Version: 6.9.0-rc7
13kms_flip@basic-flip-vs-wf_vblank
14
15# Board Name: vkms
16# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u
17# Failure Rate: 50
18# IGT Version: 1.28-g0df7b9b97
19# Linux Version: 6.9.0-rc7
20kms_flip@flip-vs-expired-vblank-interruptible
21
22# Board Name: vkms
23# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u
24# Failure Rate: 50
25# IGT Version: 1.28-g0df7b9b97
26# Linux Version: 6.9.0-rc7
27kms_flip@flip-vs-wf_vblank-interruptible
28
29# Board Name: vkms
30# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u
31# Failure Rate: 50
32# IGT Version: 1.28-g0df7b9b97
33# Linux Version: 6.9.0-rc7
34kms_flip@plain-flip-fb-recreate-interruptible
35
36# Board Name: vkms
37# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u
38# Failure Rate: 50
39# IGT Version: 1.28-g0df7b9b97
40# Linux Version: 6.9.0-rc7
41kms_flip@plain-flip-ts-check
42
43# Board Name: vkms
44# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u
45# Failure Rate: 50
46# IGT Version: 1.28-g0df7b9b97
47# Linux Version: 6.9.0-rc7
48kms_flip@plain-flip-ts-check-interruptible
49
50# Board Name: vkms
51# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u
52# Failure Rate: 50
53# IGT Version: 1.28-g0df7b9b97
54# Linux Version: 6.9.0-rc7
55kms_flip@flip-vs-absolute-wf_vblank
56
57# Board Name: vkms
58# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u
59# Failure Rate: 50
60# IGT Version: 1.28-g0df7b9b97
61# Linux Version: 6.9.0-rc7
62kms_flip@flip-vs-absolute-wf_vblank-interruptible
63
64# Board Name: vkms
65# Bug Report: https://lore.kernel.org/dri-devel/61ed26af-062c-443c-9df2-d1ee319f3fb0@collabora.com/T/#u
66# Failure Rate: 50
67# IGT Version: 1.28-g0df7b9b97
68# Linux Version: 6.9.0-rc7
69kms_flip@flip-vs-blocking-wf-vblank
drivers/gpu/drm/ci/xfails/vkms-none-skips.txt+119−0
@@ -0,0 +1,119 @@
1# keeps printing vkms_vblank_simulate: vblank timer overrun and never ends
2kms_invalid_mode@int-max-clock
3
4# Kernel panic
5kms_cursor_crc@cursor-rapid-movement-32x10
6# Oops: 0000 [#1] PREEMPT SMP NOPTI
7# CPU: 0 PID: 2635 Comm: kworker/u8:13 Not tainted 6.9.0-rc7-g40935263a1fd #1
8# Hardware name: ChromiumOS crosvm, BIOS 0
9# Workqueue: vkms_composer vkms_composer_worker [vkms]
10# RIP: 0010:compose_active_planes+0x1c7/0x4e0 [vkms]
11# Code: c9 0f 84 6a 01 00 00 8b 42 30 2b 42 28 41 39 c5 0f 8c 6f 01 00 00 49 83 c7 01 49 39 df 74 3b 4b 8b 34 fc 48 8b 96 48 01 00 00 <8b> 42 78 89 c1 83 e1 0a a8 20 74 b1 45 89 f5 41 f7 d5 44 03 6a 34
12# RSP: 0018:ffffbb4700c17d58 EFLAGS: 00010246
13# RAX: 0000000000000400 RBX: 0000000000000002 RCX: 0000000000000002
14# RDX: 0000000000000000 RSI: ffffa2ad0788c000 RDI: 00000000fff479a8
15# RBP: 0000000000000004 R08: 0000000000000000 R09: 0000000000000000
16# R10: ffffa2ad0bb14000 R11: 0000000000000000 R12: ffffa2ad03e21700
17# R13: 0000000000000003 R14: 0000000000000004 R15: 0000000000000000
18# FS: 0000000000000000(0000) GS:ffffa2ad2bc00000(0000) knlGS:0000000000000000
19# CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
20# CR2: 0000000000000078 CR3: 000000010bd30000 CR4: 0000000000350ef0
21# Call Trace:
22# <TASK>
23# ? __die+0x1e/0x60
24# ? page_fault_oops+0x17b/0x490
25# ? exc_page_fault+0x6d/0x230
26# ? asm_exc_page_fault+0x26/0x30
27# ? compose_active_planes+0x1c7/0x4e0 [vkms]
28# ? compose_active_planes+0x2a3/0x4e0 [vkms]
29# ? srso_return_thunk+0x5/0x5f
30# vkms_composer_worker+0x205/0x240 [vkms]
31# process_one_work+0x1f4/0x6b0
32# ? lock_is_held_type+0x9e/0x110
33# worker_thread+0x17e/0x350
34# ? __pfx_worker_thread+0x10/0x10
35# kthread+0xce/0x100
36# ? __pfx_kthread+0x10/0x10
37# ret_from_fork+0x2f/0x50
38# ? __pfx_kthread+0x10/0x10
39# ret_from_fork_asm+0x1a/0x30
40# </TASK>
41# Modules linked in: vkms
42# CR2: 0000000000000078
43# ---[ end trace 0000000000000000 ]---
44# RIP: 0010:compose_active_planes+0x1c7/0x4e0 [vkms]
45# Code: c9 0f 84 6a 01 00 00 8b 42 30 2b 42 28 41 39 c5 0f 8c 6f 01 00 00 49 83 c7 01 49 39 df 74 3b 4b 8b 34 fc 48 8b 96 48 01 00 00 <8b> 42 78 89 c1 83 e1 0a a8 20 74 b1 45 89 f5 41 f7 d5 44 03 6a 34
46# RSP: 0018:ffffbb4700c17d58 EFLAGS: 00010246
47# RAX: 0000000000000400 RBX: 0000000000000002 RCX: 0000000000000002
48# RDX: 0000000000000000 RSI: ffffa2ad0788c000 RDI: 00000000fff479a8
49# RBP: 0000000000000004 R08: 0000000000000000 R09: 0000000000000000
50# R10: ffffa2ad0bb14000 R11: 0000000000000000 R12: ffffa2ad03e21700
51# R13: 0000000000000003 R14: 0000000000000004 R15: 0000000000000000
52# FS: 0000000000000000(0000) GS:ffffa2ad2bc00000(0000) knlGS:0000000000000000
53# CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
54
55kms_cursor_crc@cursor-rapid-movement-256x85
56# [drm:drm_crtc_add_crc_entry] *ERROR* Overflow of CRC buffer, userspace reads too slow.
57# Oops: 0000 [#1] PREEMPT SMP NOPTI
58# CPU: 1 PID: 10 Comm: kworker/u8:0 Not tainted 6.9.0-rc7-g646381cde463 #1
59# Hardware name: ChromiumOS crosvm, BIOS 0
60# Workqueue: vkms_composer vkms_composer_worker [vkms]
61# RIP: 0010:compose_active_planes+0x1c7/0x4e0 [vkms]
62# Code: c9 0f 84 6a 01 00 00 8b 42 30 2b 42 28 41 39 c5 0f 8c 6f 01 00 00 49 83 c7 01 49 39 df 74 3b 4b 8b 34 fc 48 8b 96 48 01 00 00 <8b> 42 78 89 c1 83 e1 0a a8 20 74 b1 45 89 f5 41 f7 d5 44 03 6a 34
63# RSP: 0018:ffffa7e980057d58 EFLAGS: 00010246
64# RAX: 0000000000000400 RBX: 0000000000000002 RCX: 0000000000000002
65# RDX: 0000000000000000 RSI: ffff977987aa5c00 RDI: 000000001b43a85f
66# RBP: 0000000000000001 R08: 0000000000000000 R09: 0000000000000000
67# R10: ffff977981bf0000 R11: 0000000000000000 R12: ffff977989622590
68# R13: 0000000000000000 R14: 0000000000000001 R15: 0000000000000000
69# FS: 0000000000000000(0000) GS:ffff9779abd00000(0000) knlGS:0000000000000000
70# CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
71# CR2: 0000000000000078 CR3: 0000000109b38000 CR4: 0000000000350ef0
72# Call Trace:
73# <TASK>
74# ? __die+0x1e/0x60
75# ? page_fault_oops+0x17b/0x490
76# ? exc_page_fault+0x6d/0x230
77# ? asm_exc_page_fault+0x26/0x30
78# ? compose_active_planes+0x1c7/0x4e0 [vkms]
79# ? compose_active_planes+0x2a3/0x4e0 [vkms]
80# ? srso_return_thunk+0x5/0x5f
81# vkms_composer_worker+0x205/0x240 [vkms]
82# process_one_work+0x1f4/0x6b0
83# ? lock_is_held_type+0x9e/0x110
84# worker_thread+0x17e/0x350
85# ? __pfx_worker_thread+0x10/0x10
86# kthread+0xce/0x100
87# ? __pfx_kthread+0x10/0x10
88# ret_from_fork+0x2f/0x50
89# ? __pfx_kthread+0x10/0x10
90# ret_from_fork_asm+0x1a/0x30
91# </TASK>
92# Modules linked in: vkms
93# CR2: 0000000000000078
94# ---[ end trace 0000000000000000 ]---
95# RIP: 0010:compose_active_planes+0x1c7/0x4e0 [vkms]
96# Code: c9 0f 84 6a 01 00 00 8b 42 30 2b 42 28 41 39 c5 0f 8c 6f 01 00 00 49 83 c7 01 49 39 df 74 3b 4b 8b 34 fc 48 8b 96 48 01 00 00 <8b> 42 78 89 c1 83 e1 0a a8 20 74 b1 45 89 f5 41 f7 d5 44 03 6a 34
97# RSP: 0018:ffffa7e980057d58 EFLAGS: 00010246
98# RAX: 0000000000000400 RBX: 0000000000000002 RCX: 0000000000000002
99# RDX: 0000000000000000 RSI: ffff977987aa5c00 RDI: 000000001b43a85f
100# RBP: 0000000000000001 R08: 0000000000000000 R09: 0000000000000000
101# R10: ffff977981bf0000 R11: 0000000000000000 R12: ffff977989622590
102# R13: 0000000000000000 R14: 0000000000000001 R15: 0000000000000000
103# FS: 0000000000000000(0000) GS:ffff9779abd00000(0000) knlGS:0000000000000000
104# CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
105# CR2: 0000000000000078 CR3: 0000000109b38000 CR4: 0000000000350ef0
106
107# Skip driver specific tests
108^amdgpu.*
109msm_.*
110nouveau_.*
111panfrost_.*
112^v3d.*
113^vc4.*
114^vmwgfx*
115
116# Skip intel specific tests
117gem_.*
118i915_.*
119xe_.*
drivers/gpu/drm/display/Kconfig+7−0
@@ -70,3 +70,10 @@ config DRM_DISPLAY_HDMI_HELPER · 69 unmodified lines
70 depends on DRM_DISPLAY_HELPER70 depends on DRM_DISPLAY_HELPER
71 help71 help
72 DRM display helpers for HDMI.72 DRM display helpers for HDMI.
73
74config DRM_DISPLAY_HDMI_STATE_HELPER
75 bool
76 depends on DRM_DISPLAY_HELPER
77 select DRM_DISPLAY_HDMI_HELPER
78 help
79 DRM KMS state helpers for HDMI.
drivers/gpu/drm/display/Makefile+2−0
@@ -14,6 +14,8 @@ drm_display_helper-$(CONFIG_DRM_DISPLAY_HDCP_HELPER) += drm_hdcp_helper.o · 13 unmodified lines
14drm_display_helper-$(CONFIG_DRM_DISPLAY_HDMI_HELPER) += \14drm_display_helper-$(CONFIG_DRM_DISPLAY_HDMI_HELPER) += \
15 drm_hdmi_helper.o \15 drm_hdmi_helper.o \
16 drm_scdc_helper.o16 drm_scdc_helper.o
17drm_display_helper-$(CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER) += \
18 drm_hdmi_state_helper.o
17drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV) += drm_dp_aux_dev.o19drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV) += drm_dp_aux_dev.o
18drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_AUX_CEC) += drm_dp_cec.o20drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_AUX_CEC) += drm_dp_cec.o
19 21
drivers/gpu/drm/display/drm_hdmi_helper.c+61−0
@@ -195,3 +195,64 @@ void drm_hdmi_avi_infoframe_content_type(struct hdmi_avi_infoframe *frame, · 194 unmodified lines
195 frame->itc = conn_state->content_type != DRM_MODE_CONTENT_TYPE_NO_DATA;195 frame->itc = conn_state->content_type != DRM_MODE_CONTENT_TYPE_NO_DATA;
196}196}
197EXPORT_SYMBOL(drm_hdmi_avi_infoframe_content_type);197EXPORT_SYMBOL(drm_hdmi_avi_infoframe_content_type);
198
199/**
200 * drm_hdmi_compute_mode_clock() - Computes the TMDS Character Rate
201 * @mode: Display mode to compute the clock for
202 * @bpc: Bits per character
203 * @fmt: Output Pixel Format used
204 *
205 * Returns the TMDS Character Rate for a given mode, bpc count and output format.
206 *
207 * RETURNS:
208 * The TMDS Character Rate, in Hertz, or 0 on error.
209 */
210unsigned long long
211drm_hdmi_compute_mode_clock(const struct drm_display_mode *mode,
212 unsigned int bpc, enum hdmi_colorspace fmt)
213{
214 unsigned long long clock = mode->clock * 1000ULL;
215 unsigned int vic = drm_match_cea_mode(mode);
216
217 /*
218 * CTA-861-G Spec, section 5.4 - Color Coding and Quantization
219 * mandates that VIC 1 always uses 8 bpc.
220 */
221 if (vic == 1 && bpc != 8)
222 return 0;
223
224 if (fmt == HDMI_COLORSPACE_YUV422) {
225 /*
226 * HDMI 1.0 Spec, section 6.5 - Pixel Encoding states that
227 * YUV422 sends 24 bits over three channels, with Cb and Cr
228 * components being sent on odd and even pixels, respectively.
229 *
230 * If fewer than 12 bpc are sent, data are left justified.
231 */
232 if (bpc > 12)
233 return 0;
234
235 /*
236 * HDMI 1.0 Spec, section 6.5 - Pixel Encoding
237 * specifies that YUV422 sends two 12-bits components over
238 * three TMDS channels per pixel clock, which is equivalent to
239 * three 8-bits components over three channels used by RGB as
240 * far as the clock rate goes.
241 */
242 bpc = 8;
243 }
244
245 /*
246 * HDMI 2.0 Spec, Section 7.1 - YCbCr 4:2:0 Pixel Encoding
247 * specifies that YUV420 encoding is carried at a TMDS Character Rate
248 * equal to half the pixel clock rate.
249 */
250 if (fmt == HDMI_COLORSPACE_YUV420)
251 clock = clock / 2;
252
253 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
254 clock = clock * 2;
255
256 return DIV_ROUND_CLOSEST_ULL(clock * bpc, 8);
257}
258EXPORT_SYMBOL(drm_hdmi_compute_mode_clock);
drivers/gpu/drm/display/drm_hdmi_state_helper.c+752−0
@@ -0,0 +1,752 @@
1// SPDX-License-Identifier: MIT
2
3#include <drm/drm_atomic.h>
4#include <drm/drm_connector.h>
5#include <drm/drm_edid.h>
6#include <drm/drm_print.h>
7
8#include <drm/display/drm_hdmi_helper.h>
9#include <drm/display/drm_hdmi_state_helper.h>
10
11/**
12 * __drm_atomic_helper_connector_hdmi_reset() - Initializes all HDMI @drm_connector_state resources
13 * @connector: DRM connector
14 * @new_conn_state: connector state to reset
15 *
16 * Initializes all HDMI resources from a @drm_connector_state without
17 * actually allocating it. This is useful for HDMI drivers, in
18 * combination with __drm_atomic_helper_connector_reset() or
19 * drm_atomic_helper_connector_reset().
20 */
21void __drm_atomic_helper_connector_hdmi_reset(struct drm_connector *connector,
22 struct drm_connector_state *new_conn_state)
23{
24 unsigned int max_bpc = connector->max_bpc;
25
26 new_conn_state->max_bpc = max_bpc;
27 new_conn_state->max_requested_bpc = max_bpc;
28 new_conn_state->hdmi.broadcast_rgb = DRM_HDMI_BROADCAST_RGB_AUTO;
29}
30EXPORT_SYMBOL(__drm_atomic_helper_connector_hdmi_reset);
31
32static const struct drm_display_mode *
33connector_state_get_mode(const struct drm_connector_state *conn_state)
34{
35 struct drm_atomic_state *state;
36 struct drm_crtc_state *crtc_state;
37 struct drm_crtc *crtc;
38
39 state = conn_state->state;
40 if (!state)
41 return NULL;
42
43 crtc = conn_state->crtc;
44 if (!crtc)
45 return NULL;
46
47 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
48 if (!crtc_state)
49 return NULL;
50
51 return &crtc_state->mode;
52}
53
54static bool hdmi_is_limited_range(const struct drm_connector *connector,
55 const struct drm_connector_state *conn_state)
56{
57 const struct drm_display_info *info = &connector->display_info;
58 const struct drm_display_mode *mode =
59 connector_state_get_mode(conn_state);
60
61 /*
62 * The Broadcast RGB property only applies to RGB format, and
63 * i915 just assumes limited range for YCbCr output, so let's
64 * just do the same.
65 */
66 if (conn_state->hdmi.output_format != HDMI_COLORSPACE_RGB)
67 return true;
68
69 if (conn_state->hdmi.broadcast_rgb == DRM_HDMI_BROADCAST_RGB_FULL)
70 return false;
71
72 if (conn_state->hdmi.broadcast_rgb == DRM_HDMI_BROADCAST_RGB_LIMITED)
73 return true;
74
75 if (!info->is_hdmi)
76 return false;
77
78 return drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED;
79}
80
81static bool
82sink_supports_format_bpc(const struct drm_connector *connector,
83 const struct drm_display_info *info,
84 const struct drm_display_mode *mode,
85 unsigned int format, unsigned int bpc)
86{
87 struct drm_device *dev = connector->dev;
88 u8 vic = drm_match_cea_mode(mode);
89
90 /*
91 * CTA-861-F, section 5.4 - Color Coding & Quantization states
92 * that the bpc must be 8, 10, 12 or 16 except for the default
93 * 640x480 VIC1 where the value must be 8.
94 *
95 * The definition of default here is ambiguous but the spec
96 * refers to VIC1 being the default timing in several occasions
97 * so our understanding is that for the default timing (ie,
98 * VIC1), the bpc must be 8.
99 */
100 if (vic == 1 && bpc != 8) {
101 drm_dbg_kms(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
102 return false;
103 }
104
105 if (!info->is_hdmi &&
106 (format != HDMI_COLORSPACE_RGB || bpc != 8)) {
107 drm_dbg_kms(dev, "DVI Monitors require an RGB output at 8 bpc\n");
108 return false;
109 }
110
111 if (!(connector->hdmi.supported_formats & BIT(format))) {
112 drm_dbg_kms(dev, "%s format unsupported by the connector.\n",
113 drm_hdmi_connector_get_output_format_name(format));
114 return false;
115 }
116
117 switch (format) {
118 case HDMI_COLORSPACE_RGB:
119 drm_dbg_kms(dev, "RGB Format, checking the constraints.\n");
120
121 /*
122 * In some cases, like when the EDID readout fails, or
123 * is not an HDMI compliant EDID for some reason, the
124 * color_formats field will be blank and not report any
125 * format supported. In such a case, assume that RGB is
126 * supported so we can keep things going and light up
127 * the display.
128 */
129 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
130 drm_warn(dev, "HDMI Sink doesn't support RGB, something's wrong.\n");
131
132 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
133 drm_dbg_kms(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
134 return false;
135 }
136
137 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
138 drm_dbg_kms(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
139 return false;
140 }
141
142 drm_dbg_kms(dev, "RGB format supported in that configuration.\n");
143
144 return true;
145
146 case HDMI_COLORSPACE_YUV420:
147 /* TODO: YUV420 is unsupported at the moment. */
148 drm_dbg_kms(dev, "YUV420 format isn't supported yet.\n");
149 return false;
150
151 case HDMI_COLORSPACE_YUV422:
152 drm_dbg_kms(dev, "YUV422 format, checking the constraints.\n");
153
154 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
155 drm_dbg_kms(dev, "Sink doesn't support YUV422.\n");
156 return false;
157 }
158
159 if (bpc > 12) {
160 drm_dbg_kms(dev, "YUV422 only supports 12 bpc or lower.\n");
161 return false;
162 }
163
164 /*
165 * HDMI Spec 1.3 - Section 6.5 Pixel Encodings and Color Depth
166 * states that Deep Color is not relevant for YUV422 so we
167 * don't need to check the Deep Color bits in the EDIDs here.
168 */
169
170 drm_dbg_kms(dev, "YUV422 format supported in that configuration.\n");
171
172 return true;
173
174 case HDMI_COLORSPACE_YUV444:
175 drm_dbg_kms(dev, "YUV444 format, checking the constraints.\n");
176
177 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
178 drm_dbg_kms(dev, "Sink doesn't support YUV444.\n");
179 return false;
180 }
181
182 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
183 drm_dbg_kms(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
184 return false;
185 }
186
187 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
188 drm_dbg_kms(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
189 return false;
190 }
191
192 drm_dbg_kms(dev, "YUV444 format supported in that configuration.\n");
193
194 return true;
195 }
196
197 drm_dbg_kms(dev, "Unsupported pixel format.\n");
198 return false;
199}
200
201static enum drm_mode_status
202hdmi_clock_valid(const struct drm_connector *connector,
203 const struct drm_display_mode *mode,
204 unsigned long long clock)
205{
206 const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs;
207 const struct drm_display_info *info = &connector->display_info;
208
209 if (info->max_tmds_clock && clock > info->max_tmds_clock * 1000)
210 return MODE_CLOCK_HIGH;
211
212 if (funcs && funcs->tmds_char_rate_valid) {
213 enum drm_mode_status status;
214
215 status = funcs->tmds_char_rate_valid(connector, mode, clock);
216 if (status != MODE_OK)
217 return status;
218 }
219
220 return MODE_OK;
221}
222
223static int
224hdmi_compute_clock(const struct drm_connector *connector,
225 struct drm_connector_state *conn_state,
226 const struct drm_display_mode *mode,
227 unsigned int bpc, enum hdmi_colorspace fmt)
228{
229 enum drm_mode_status status;
230 unsigned long long clock;
231
232 clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt);
233 if (!clock)
234 return -EINVAL;
235
236 status = hdmi_clock_valid(connector, mode, clock);
237 if (status != MODE_OK)
238 return -EINVAL;
239
240 conn_state->hdmi.tmds_char_rate = clock;
241
242 return 0;
243}
244
245static bool
246hdmi_try_format_bpc(const struct drm_connector *connector,
247 struct drm_connector_state *conn_state,
248 const struct drm_display_mode *mode,
249 unsigned int bpc, enum hdmi_colorspace fmt)
250{
251 const struct drm_display_info *info = &connector->display_info;
252 struct drm_device *dev = connector->dev;
253 int ret;
254
255 drm_dbg_kms(dev, "Trying %s output format\n",
256 drm_hdmi_connector_get_output_format_name(fmt));
257
258 if (!sink_supports_format_bpc(connector, info, mode, fmt, bpc)) {
259 drm_dbg_kms(dev, "%s output format not supported with %u bpc\n",
260 drm_hdmi_connector_get_output_format_name(fmt),
261 bpc);
262 return false;
263 }
264
265 ret = hdmi_compute_clock(connector, conn_state, mode, bpc, fmt);
266 if (ret) {
267 drm_dbg_kms(dev, "Couldn't compute clock for %s output format and %u bpc\n",
268 drm_hdmi_connector_get_output_format_name(fmt),
269 bpc);
270 return false;
271 }
272
273 drm_dbg_kms(dev, "%s output format supported with %u (TMDS char rate: %llu Hz)\n",
274 drm_hdmi_connector_get_output_format_name(fmt),
275 bpc, conn_state->hdmi.tmds_char_rate);
276
277 return true;
278}
279
280static int
281hdmi_compute_format(const struct drm_connector *connector,
282 struct drm_connector_state *conn_state,
283 const struct drm_display_mode *mode,
284 unsigned int bpc)
285{
286 struct drm_device *dev = connector->dev;
287
288 /*
289 * TODO: Add support for YCbCr420 output for HDMI 2.0 capable
290 * devices, for modes that only support YCbCr420.
291 */
292 if (hdmi_try_format_bpc(connector, conn_state, mode, bpc, HDMI_COLORSPACE_RGB)) {
293 conn_state->hdmi.output_format = HDMI_COLORSPACE_RGB;
294 return 0;
295 }
296
297 drm_dbg_kms(dev, "Failed. No Format Supported for that bpc count.\n");
298
299 return -EINVAL;
300}
301
302static int
303hdmi_compute_config(const struct drm_connector *connector,
304 struct drm_connector_state *conn_state,
305 const struct drm_display_mode *mode)
306{
307 struct drm_device *dev = connector->dev;
308 unsigned int max_bpc = clamp_t(unsigned int,
309 conn_state->max_bpc,
310 8, connector->max_bpc);
311 unsigned int bpc;
312 int ret;
313
314 for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
315 drm_dbg_kms(dev, "Trying with a %d bpc output\n", bpc);
316
317 ret = hdmi_compute_format(connector, conn_state, mode, bpc);
318 if (ret)
319 continue;
320
321 conn_state->hdmi.output_bpc = bpc;
322
323 drm_dbg_kms(dev,
324 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
325 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
326 conn_state->hdmi.output_bpc,
327 drm_hdmi_connector_get_output_format_name(conn_state->hdmi.output_format),
328 conn_state->hdmi.tmds_char_rate);
329
330 return 0;
331 }
332
333 return -EINVAL;
334}
335
336static int hdmi_generate_avi_infoframe(const struct drm_connector *connector,
337 struct drm_connector_state *conn_state)
338{
339 const struct drm_display_mode *mode =
340 connector_state_get_mode(conn_state);
341 struct drm_connector_hdmi_infoframe *infoframe =
342 &conn_state->hdmi.infoframes.avi;
343 struct hdmi_avi_infoframe *frame =
344 &infoframe->data.avi;
345 bool is_limited_range = conn_state->hdmi.is_limited_range;
346 enum hdmi_quantization_range rgb_quant_range =
347 is_limited_range ? HDMI_QUANTIZATION_RANGE_LIMITED : HDMI_QUANTIZATION_RANGE_FULL;
348 int ret;
349
350 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, mode);
351 if (ret)
352 return ret;
353
354 frame->colorspace = conn_state->hdmi.output_format;
355
356 /*
357 * FIXME: drm_hdmi_avi_infoframe_quant_range() doesn't handle
358 * YUV formats at all at the moment, so if we ever support YUV
359 * formats this needs to be revised.
360 */
361 drm_hdmi_avi_infoframe_quant_range(frame, connector, mode, rgb_quant_range);
362 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
363 drm_hdmi_avi_infoframe_bars(frame, conn_state);
364
365 infoframe->set = true;
366
367 return 0;
368}
369
370static int hdmi_generate_spd_infoframe(const struct drm_connector *connector,
371 struct drm_connector_state *conn_state)
372{
373 struct drm_connector_hdmi_infoframe *infoframe =
374 &conn_state->hdmi.infoframes.spd;
375 struct hdmi_spd_infoframe *frame =
376 &infoframe->data.spd;
377 int ret;
378
379 ret = hdmi_spd_infoframe_init(frame,
380 connector->hdmi.vendor,
381 connector->hdmi.product);
382 if (ret)
383 return ret;
384
385 frame->sdi = HDMI_SPD_SDI_PC;
386
387 infoframe->set = true;
388
389 return 0;
390}
391
392static int hdmi_generate_hdr_infoframe(const struct drm_connector *connector,
393 struct drm_connector_state *conn_state)
394{
395 struct drm_connector_hdmi_infoframe *infoframe =
396 &conn_state->hdmi.infoframes.hdr_drm;
397 struct hdmi_drm_infoframe *frame =
398 &infoframe->data.drm;
399 int ret;
400
401 if (connector->max_bpc < 10)
402 return 0;
403
404 if (!conn_state->hdr_output_metadata)
405 return 0;
406
407 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
408 if (ret)
409 return ret;
410
411 infoframe->set = true;
412
413 return 0;
414}
415
416static int hdmi_generate_hdmi_vendor_infoframe(const struct drm_connector *connector,
417 struct drm_connector_state *conn_state)
418{
419 const struct drm_display_info *info = &connector->display_info;
420 const struct drm_display_mode *mode =
421 connector_state_get_mode(conn_state);
422 struct drm_connector_hdmi_infoframe *infoframe =
423 &conn_state->hdmi.infoframes.hdmi;
424 struct hdmi_vendor_infoframe *frame =
425 &infoframe->data.vendor.hdmi;
426 int ret;
427
428 if (!info->has_hdmi_infoframe)
429 return 0;
430
431 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, connector, mode);
432 if (ret)
433 return ret;
434
435 infoframe->set = true;
436
437 return 0;
438}
439
440static int
441hdmi_generate_infoframes(const struct drm_connector *connector,
442 struct drm_connector_state *conn_state)
443{
444 const struct drm_display_info *info = &connector->display_info;
445 int ret;
446
447 if (!info->is_hdmi)
448 return 0;
449
450 ret = hdmi_generate_avi_infoframe(connector, conn_state);
451 if (ret)
452 return ret;
453
454 ret = hdmi_generate_spd_infoframe(connector, conn_state);
455 if (ret)
456 return ret;
457
458 /*
459 * Audio Infoframes will be generated by ALSA, and updated by
460 * drm_atomic_helper_connector_hdmi_update_audio_infoframe().
461 */
462
463 ret = hdmi_generate_hdr_infoframe(connector, conn_state);
464 if (ret)
465 return ret;
466
467 ret = hdmi_generate_hdmi_vendor_infoframe(connector, conn_state);
468 if (ret)
469 return ret;
470
471 return 0;
472}
473
474/**
475 * drm_atomic_helper_connector_hdmi_check() - Helper to check HDMI connector atomic state
476 * @connector: DRM Connector
477 * @state: the DRM State object
478 *
479 * Provides a default connector state check handler for HDMI connectors.
480 * Checks that a desired connector update is valid, and updates various
481 * fields of derived state.
482 *
483 * RETURNS:
484 * Zero on success, or an errno code otherwise.
485 */
486int drm_atomic_helper_connector_hdmi_check(struct drm_connector *connector,
487 struct drm_atomic_state *state)
488{
489 struct drm_connector_state *old_conn_state =
490 drm_atomic_get_old_connector_state(state, connector);
491 struct drm_connector_state *new_conn_state =
492 drm_atomic_get_new_connector_state(state, connector);
493 const struct drm_display_mode *mode =
494 connector_state_get_mode(new_conn_state);
495 int ret;
496
497 new_conn_state->hdmi.is_limited_range = hdmi_is_limited_range(connector, new_conn_state);
498
499 ret = hdmi_compute_config(connector, new_conn_state, mode);
500 if (ret)
501 return ret;
502
503 ret = hdmi_generate_infoframes(connector, new_conn_state);
504 if (ret)
505 return ret;
506
507 if (old_conn_state->hdmi.broadcast_rgb != new_conn_state->hdmi.broadcast_rgb ||
508 old_conn_state->hdmi.output_bpc != new_conn_state->hdmi.output_bpc ||
509 old_conn_state->hdmi.output_format != new_conn_state->hdmi.output_format) {
510 struct drm_crtc *crtc = new_conn_state->crtc;
511 struct drm_crtc_state *crtc_state;
512
513 crtc_state = drm_atomic_get_crtc_state(state, crtc);
514 if (IS_ERR(crtc_state))
515 return PTR_ERR(crtc_state);
516
517 crtc_state->mode_changed = true;
518 }
519
520 return 0;
521}
522EXPORT_SYMBOL(drm_atomic_helper_connector_hdmi_check);
523
524#define HDMI_MAX_INFOFRAME_SIZE 29
525
526static int clear_device_infoframe(struct drm_connector *connector,
527 enum hdmi_infoframe_type type)
528{
529 const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs;
530 struct drm_device *dev = connector->dev;
531 int ret;
532
533 drm_dbg_kms(dev, "Clearing infoframe type 0x%x\n", type);
534
535 if (!funcs || !funcs->clear_infoframe) {
536 drm_dbg_kms(dev, "Function not implemented, bailing.\n");
537 return 0;
538 }
539
540 ret = funcs->clear_infoframe(connector, type);
541 if (ret) {
542 drm_dbg_kms(dev, "Call failed: %d\n", ret);
543 return ret;
544 }
545
546 return 0;
547}
548
549static int clear_infoframe(struct drm_connector *connector,
550 struct drm_connector_hdmi_infoframe *old_frame)
551{
552 int ret;
553
554 ret = clear_device_infoframe(connector, old_frame->data.any.type);
555 if (ret)
556 return ret;
557
558 return 0;
559}
560
561static int write_device_infoframe(struct drm_connector *connector,
562 union hdmi_infoframe *frame)
563{
564 const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs;
565 struct drm_device *dev = connector->dev;
566 u8 buffer[HDMI_MAX_INFOFRAME_SIZE];
567 int ret;
568 int len;
569
570 drm_dbg_kms(dev, "Writing infoframe type %x\n", frame->any.type);
571
572 if (!funcs || !funcs->write_infoframe) {
573 drm_dbg_kms(dev, "Function not implemented, bailing.\n");
574 return -EINVAL;
575 }
576
577 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
578 if (len < 0)
579 return len;
580
581 ret = funcs->write_infoframe(connector, frame->any.type, buffer, len);
582 if (ret) {
583 drm_dbg_kms(dev, "Call failed: %d\n", ret);
584 return ret;
585 }
586
587 return 0;
588}
589
590static int write_infoframe(struct drm_connector *connector,
591 struct drm_connector_hdmi_infoframe *new_frame)
592{
593 int ret;
594
595 ret = write_device_infoframe(connector, &new_frame->data);
596 if (ret)
597 return ret;
598
599 return 0;
600}
601
602static int write_or_clear_infoframe(struct drm_connector *connector,
603 struct drm_connector_hdmi_infoframe *old_frame,
604 struct drm_connector_hdmi_infoframe *new_frame)
605{
606 if (new_frame->set)
607 return write_infoframe(connector, new_frame);
608
609 if (old_frame->set && !new_frame->set)
610 return clear_infoframe(connector, old_frame);
611
612 return 0;
613}
614
615/**
616 * drm_atomic_helper_connector_hdmi_update_infoframes - Update the Infoframes
617 * @connector: A pointer to the HDMI connector
618 * @state: The HDMI connector state to generate the infoframe from
619 *
620 * This function is meant for HDMI connector drivers to write their
621 * infoframes. It will typically be used in a
622 * @drm_connector_helper_funcs.atomic_enable implementation.
623 *
624 * Returns:
625 * Zero on success, error code on failure.
626 */
627int drm_atomic_helper_connector_hdmi_update_infoframes(struct drm_connector *connector,
628 struct drm_atomic_state *state)
629{
630 struct drm_connector_state *old_conn_state =
631 drm_atomic_get_old_connector_state(state, connector);
632 struct drm_connector_state *new_conn_state =
633 drm_atomic_get_new_connector_state(state, connector);
634 struct drm_display_info *info = &connector->display_info;
635 int ret;
636
637 if (!info->is_hdmi)
638 return 0;
639
640 mutex_lock(&connector->hdmi.infoframes.lock);
641
642 ret = write_or_clear_infoframe(connector,
643 &old_conn_state->hdmi.infoframes.avi,
644 &new_conn_state->hdmi.infoframes.avi);
645 if (ret)
646 goto out;
647
648 if (connector->hdmi.infoframes.audio.set) {
649 ret = write_infoframe(connector,
650 &connector->hdmi.infoframes.audio);
651 if (ret)
652 goto out;
653 }
654
655 ret = write_or_clear_infoframe(connector,
656 &old_conn_state->hdmi.infoframes.hdr_drm,
657 &new_conn_state->hdmi.infoframes.hdr_drm);
658 if (ret)
659 goto out;
660
661 ret = write_or_clear_infoframe(connector,
662 &old_conn_state->hdmi.infoframes.spd,
663 &new_conn_state->hdmi.infoframes.spd);
664 if (ret)
665 goto out;
666
667 if (info->has_hdmi_infoframe) {
668 ret = write_or_clear_infoframe(connector,
669 &old_conn_state->hdmi.infoframes.hdmi,
670 &new_conn_state->hdmi.infoframes.hdmi);
671 if (ret)
672 goto out;
673 }
674
675out:
676 mutex_unlock(&connector->hdmi.infoframes.lock);
677 return ret;
678}
679EXPORT_SYMBOL(drm_atomic_helper_connector_hdmi_update_infoframes);
680
681/**
682 * drm_atomic_helper_connector_hdmi_update_audio_infoframe - Update the Audio Infoframe
683 * @connector: A pointer to the HDMI connector
684 * @frame: A pointer to the audio infoframe to write
685 *
686 * This function is meant for HDMI connector drivers to update their
687 * audio infoframe. It will typically be used in one of the ALSA hooks
688 * (most likely prepare).
689 *
690 * Returns:
691 * Zero on success, error code on failure.
692 */
693int
694drm_atomic_helper_connector_hdmi_update_audio_infoframe(struct drm_connector *connector,
695 struct hdmi_audio_infoframe *frame)
696{
697 struct drm_connector_hdmi_infoframe *infoframe =
698 &connector->hdmi.infoframes.audio;
699 struct drm_display_info *info = &connector->display_info;
700 int ret;
701
702 if (!info->is_hdmi)
703 return 0;
704
705 mutex_lock(&connector->hdmi.infoframes.lock);
706
707 memcpy(&infoframe->data, frame, sizeof(infoframe->data));
708 infoframe->set = true;
709
710 ret = write_infoframe(connector, infoframe);
711
712 mutex_unlock(&connector->hdmi.infoframes.lock);
713
714 return ret;
715}
716EXPORT_SYMBOL(drm_atomic_helper_connector_hdmi_update_audio_infoframe);
717
718/**
719 * drm_atomic_helper_connector_hdmi_disable_audio_infoframe - Stop sending the Audio Infoframe
720 * @connector: A pointer to the HDMI connector
721 *
722 * This function is meant for HDMI connector drivers to stop sending their
723 * audio infoframe. It will typically be used in one of the ALSA hooks
724 * (most likely shutdown).
725 *
726 * Returns:
727 * Zero on success, error code on failure.
728 */
729int
730drm_atomic_helper_connector_hdmi_disable_audio_infoframe(struct drm_connector *connector)
731{
732 struct drm_connector_hdmi_infoframe *infoframe =
733 &connector->hdmi.infoframes.audio;
734 struct drm_display_info *info = &connector->display_info;
735 int ret;
736
737 if (!info->is_hdmi)
738 return 0;
739
740 mutex_lock(&connector->hdmi.infoframes.lock);
741
742 infoframe->set = false;
743
744 ret = clear_infoframe(connector, infoframe);
745
746 memset(&infoframe->data, 0, sizeof(infoframe->data));
747
748 mutex_unlock(&connector->hdmi.infoframes.lock);
749
750 return ret;
751}
752EXPORT_SYMBOL(drm_atomic_helper_connector_hdmi_disable_audio_infoframe);
drivers/gpu/drm/drm_atomic.c+11−0
@@ -1143,6 +1143,17 @@ static void drm_atomic_connector_print_state(struct drm_printer *p, · 1142 unmodified lines
1143 drm_printf(p, "\tmax_requested_bpc=%d\n", state->max_requested_bpc);1143 drm_printf(p, "\tmax_requested_bpc=%d\n", state->max_requested_bpc);
1144 drm_printf(p, "\tcolorspace=%s\n", drm_get_colorspace_name(state->colorspace));1144 drm_printf(p, "\tcolorspace=%s\n", drm_get_colorspace_name(state->colorspace));
1145 1145
1146 if (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
1147 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
1148 drm_printf(p, "\tbroadcast_rgb=%s\n",
1149 drm_hdmi_connector_get_broadcast_rgb_name(state->hdmi.broadcast_rgb));
1150 drm_printf(p, "\tis_limited_range=%c\n", state->hdmi.is_limited_range ? 'y' : 'n');
1151 drm_printf(p, "\toutput_bpc=%u\n", state->hdmi.output_bpc);
1152 drm_printf(p, "\toutput_format=%s\n",
1153 drm_hdmi_connector_get_output_format_name(state->hdmi.output_format));
1154 drm_printf(p, "\ttmds_char_rate=%llu\n", state->hdmi.tmds_char_rate);
1155 }
1156
1146 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)1157 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
1147 if (state->writeback_job && state->writeback_job->fb)1158 if (state->writeback_job && state->writeback_job->fb)
1148 drm_printf(p, "\tfb=%d\n", state->writeback_job->fb->base.id);1159 drm_printf(p, "\tfb=%d\n", state->writeback_job->fb->base.id);
drivers/gpu/drm/drm_atomic_uapi.c+4−0
@@ -776,6 +776,8 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector, · 775 unmodified lines
776 state->max_requested_bpc = val;776 state->max_requested_bpc = val;
777 } else if (property == connector->privacy_screen_sw_state_property) {777 } else if (property == connector->privacy_screen_sw_state_property) {
778 state->privacy_screen_sw_state = val;778 state->privacy_screen_sw_state = val;
779 } else if (property == connector->broadcast_rgb_property) {
780 state->hdmi.broadcast_rgb = val;
779 } else if (connector->funcs->atomic_set_property) {781 } else if (connector->funcs->atomic_set_property) {
780 return connector->funcs->atomic_set_property(connector,782 return connector->funcs->atomic_set_property(connector,
781 state, property, val);783 state, property, val);
@@ -859,6 +861,8 @@ drm_atomic_connector_get_property(struct drm_connector *connector, · 77 unmodified lines
859 *val = state->max_requested_bpc;861 *val = state->max_requested_bpc;
860 } else if (property == connector->privacy_screen_sw_state_property) {862 } else if (property == connector->privacy_screen_sw_state_property) {
861 *val = state->privacy_screen_sw_state;863 *val = state->privacy_screen_sw_state;
864 } else if (property == connector->broadcast_rgb_property) {
865 *val = state->hdmi.broadcast_rgb;
862 } else if (connector->funcs->atomic_get_property) {866 } else if (connector->funcs->atomic_get_property) {
863 return connector->funcs->atomic_get_property(connector,867 return connector->funcs->atomic_get_property(connector,
864 state, property, val);868 state, property, val);
drivers/gpu/drm/drm_bridge.c+0−42
@@ -353,13 +353,8 @@ err_reset_bridge: · 352 unmodified lines
353 bridge->encoder = NULL;353 bridge->encoder = NULL;
354 list_del(&bridge->chain_node);354 list_del(&bridge->chain_node);
355 355
356#ifdef CONFIG_OF
357 DRM_ERROR("failed to attach bridge %pOF to encoder %s: %d\n",356 DRM_ERROR("failed to attach bridge %pOF to encoder %s: %d\n",
358 bridge->of_node, encoder->name, ret);357 bridge->of_node, encoder->name, ret);
359#else
360 DRM_ERROR("failed to attach bridge to encoder %s: %d\n",
361 encoder->name, ret);
362#endif
363 358
364 return ret;359 return ret;
365}360}
@@ -472,43 +467,6 @@ void drm_bridge_detach(struct drm_bridge *bridge) · 106 unmodified lines
472 * needed, in order to gradually transition to the new model.467 * needed, in order to gradually transition to the new model.
473 */468 */
474 469
475/**
476 * drm_bridge_chain_mode_fixup - fixup proposed mode for all bridges in the
477 * encoder chain
478 * @bridge: bridge control structure
479 * @mode: desired mode to be set for the bridge
480 * @adjusted_mode: updated mode that works for this bridge
481 *
482 * Calls &drm_bridge_funcs.mode_fixup for all the bridges in the
483 * encoder chain, starting from the first bridge to the last.
484 *
485 * Note: the bridge passed should be the one closest to the encoder
486 *
487 * RETURNS:
488 * true on success, false on failure
489 */
490bool drm_bridge_chain_mode_fixup(struct drm_bridge *bridge,
491 const struct drm_display_mode *mode,
492 struct drm_display_mode *adjusted_mode)
493{
494 struct drm_encoder *encoder;
495
496 if (!bridge)
497 return true;
498
499 encoder = bridge->encoder;
500 list_for_each_entry_from(bridge, &encoder->bridge_chain, chain_node) {
501 if (!bridge->funcs->mode_fixup)
502 continue;
503
504 if (!bridge->funcs->mode_fixup(bridge, mode, adjusted_mode))
505 return false;
506 }
507
508 return true;
509}
510EXPORT_SYMBOL(drm_bridge_chain_mode_fixup);
511
512/**470/**
513 * drm_bridge_chain_mode_valid - validate the mode against all bridges in the471 * drm_bridge_chain_mode_valid - validate the mode against all bridges in the
514 * encoder chain.472 * encoder chain.
drivers/gpu/drm/drm_bridge_connector.c+91−16
@@ -15,8 +15,10 @@ · 14 unmodified lines
15#include <drm/drm_connector.h>15#include <drm/drm_connector.h>
16#include <drm/drm_device.h>16#include <drm/drm_device.h>
17#include <drm/drm_edid.h>17#include <drm/drm_edid.h>
18#include <drm/drm_managed.h>
18#include <drm/drm_modeset_helper_vtables.h>19#include <drm/drm_modeset_helper_vtables.h>
19#include <drm/drm_probe_helper.h>20#include <drm/drm_probe_helper.h>
21#include <drm/display/drm_hdmi_state_helper.h>
20 22
21/**23/**
22 * DOC: overview24 * DOC: overview
@@ -86,6 +88,13 @@ struct drm_bridge_connector { · 63 unmodified lines
86 * connector modes detection, if any (see &DRM_BRIDGE_OP_MODES).88 * connector modes detection, if any (see &DRM_BRIDGE_OP_MODES).
87 */89 */
88 struct drm_bridge *bridge_modes;90 struct drm_bridge *bridge_modes;
91 /**
92 * @bridge_hdmi:
93 *
94 * The bridge in the chain that implements necessary support for the
95 * HDMI connector infrastructure, if any (see &DRM_BRIDGE_OP_HDMI).
96 */
97 struct drm_bridge *bridge_hdmi;
89};98};
90 99
91#define to_drm_bridge_connector(x) \100#define to_drm_bridge_connector(x) \
@@ -193,19 +202,6 @@ drm_bridge_connector_detect(struct drm_connector *connector, bool force) · 101 unmodified lines
193 return status;202 return status;
194}203}
195 204
196static void drm_bridge_connector_destroy(struct drm_connector *connector)
197{
198 struct drm_bridge_connector *bridge_connector =
199 to_drm_bridge_connector(connector);
200
201 drm_connector_unregister(connector);
202 drm_connector_cleanup(connector);
203
204 fwnode_handle_put(connector->fwnode);
205
206 kfree(bridge_connector);
207}
208
209static void drm_bridge_connector_debugfs_init(struct drm_connector *connector,205static void drm_bridge_connector_debugfs_init(struct drm_connector *connector,
210 struct dentry *root)206 struct dentry *root)
211{207{
@@ -224,7 +220,6 @@ static const struct drm_connector_funcs drm_bridge_connector_funcs = { · 12 unmodified lines
224 .reset = drm_atomic_helper_connector_reset,220 .reset = drm_atomic_helper_connector_reset,
225 .detect = drm_bridge_connector_detect,221 .detect = drm_bridge_connector_detect,
226 .fill_modes = drm_helper_probe_single_connector_modes,222 .fill_modes = drm_helper_probe_single_connector_modes,
227 .destroy = drm_bridge_connector_destroy,
228 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,223 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
229 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,224 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
230 .debugfs_init = drm_bridge_connector_debugfs_init,225 .debugfs_init = drm_bridge_connector_debugfs_init,
@@ -300,6 +295,60 @@ static const struct drm_connector_helper_funcs drm_bridge_connector_helper_funcs · 69 unmodified lines
300 .disable_hpd = drm_bridge_connector_disable_hpd,295 .disable_hpd = drm_bridge_connector_disable_hpd,
301};296};
302 297
298static enum drm_mode_status
299drm_bridge_connector_tmds_char_rate_valid(const struct drm_connector *connector,
300 const struct drm_display_mode *mode,
301 unsigned long long tmds_rate)
302{
303 struct drm_bridge_connector *bridge_connector =
304 to_drm_bridge_connector(connector);
305 struct drm_bridge *bridge;
306
307 bridge = bridge_connector->bridge_hdmi;
308 if (!bridge)
309 return MODE_ERROR;
310
311 if (bridge->funcs->hdmi_tmds_char_rate_valid)
312 return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, tmds_rate);
313 else
314 return MODE_OK;
315}
316
317static int drm_bridge_connector_clear_infoframe(struct drm_connector *connector,
318 enum hdmi_infoframe_type type)
319{
320 struct drm_bridge_connector *bridge_connector =
321 to_drm_bridge_connector(connector);
322 struct drm_bridge *bridge;
323
324 bridge = bridge_connector->bridge_hdmi;
325 if (!bridge)
326 return -EINVAL;
327
328 return bridge->funcs->hdmi_clear_infoframe(bridge, type);
329}
330
331static int drm_bridge_connector_write_infoframe(struct drm_connector *connector,
332 enum hdmi_infoframe_type type,
333 const u8 *buffer, size_t len)
334{
335 struct drm_bridge_connector *bridge_connector =
336 to_drm_bridge_connector(connector);
337 struct drm_bridge *bridge;
338
339 bridge = bridge_connector->bridge_hdmi;
340 if (!bridge)
341 return -EINVAL;
342
343 return bridge->funcs->hdmi_write_infoframe(bridge, type, buffer, len);
344}
345
346static const struct drm_connector_hdmi_funcs drm_bridge_connector_hdmi_funcs = {
347 .tmds_char_rate_valid = drm_bridge_connector_tmds_char_rate_valid,
348 .clear_infoframe = drm_bridge_connector_clear_infoframe,
349 .write_infoframe = drm_bridge_connector_write_infoframe,
350};
351
303/* -----------------------------------------------------------------------------352/* -----------------------------------------------------------------------------
304 * Bridge Connector Initialisation353 * Bridge Connector Initialisation
305 */354 */
@@ -325,10 +374,12 @@ struct drm_connector *drm_bridge_connector_init(struct drm_device *drm, · 19 unmodified lines
325 struct drm_connector *connector;374 struct drm_connector *connector;
326 struct i2c_adapter *ddc = NULL;375 struct i2c_adapter *ddc = NULL;
327 struct drm_bridge *bridge, *panel_bridge = NULL;376 struct drm_bridge *bridge, *panel_bridge = NULL;
377 unsigned int supported_formats = BIT(HDMI_COLORSPACE_RGB);
378 unsigned int max_bpc = 8;
328 int connector_type;379 int connector_type;
329 int ret;380 int ret;
330 381
331 bridge_connector = kzalloc(sizeof(*bridge_connector), GFP_KERNEL);382 bridge_connector = drmm_kzalloc(drm, sizeof(*bridge_connector), GFP_KERNEL);
332 if (!bridge_connector)383 if (!bridge_connector)
333 return ERR_PTR(-ENOMEM);384 return ERR_PTR(-ENOMEM);
334 385
@@ -361,6 +412,20 @@ struct drm_connector *drm_bridge_connector_init(struct drm_device *drm, · 26 unmodified lines
361 bridge_connector->bridge_detect = bridge;412 bridge_connector->bridge_detect = bridge;
362 if (bridge->ops & DRM_BRIDGE_OP_MODES)413 if (bridge->ops & DRM_BRIDGE_OP_MODES)
363 bridge_connector->bridge_modes = bridge;414 bridge_connector->bridge_modes = bridge;
415 if (bridge->ops & DRM_BRIDGE_OP_HDMI) {
416 if (bridge_connector->bridge_hdmi)
417 return ERR_PTR(-EBUSY);
418 if (!bridge->funcs->hdmi_write_infoframe ||
419 !bridge->funcs->hdmi_clear_infoframe)
420 return ERR_PTR(-EINVAL);
421
422 bridge_connector->bridge_hdmi = bridge;
423
424 if (bridge->supported_formats)
425 supported_formats = bridge->supported_formats;
426 if (bridge->max_bpc)
427 max_bpc = bridge->max_bpc;
428 }
364 429
365 if (!drm_bridge_get_next_bridge(bridge))430 if (!drm_bridge_get_next_bridge(bridge))
366 connector_type = bridge->type;431 connector_type = bridge->type;
@@ -383,7 +448,17 @@ struct drm_connector *drm_bridge_connector_init(struct drm_device *drm, · 16 unmodified lines
383 return ERR_PTR(-EINVAL);448 return ERR_PTR(-EINVAL);
384 }449 }
385 450
386 ret = drm_connector_init_with_ddc(drm, connector,451 if (bridge_connector->bridge_hdmi)
452 ret = drmm_connector_hdmi_init(drm, connector,
453 bridge_connector->bridge_hdmi->vendor,
454 bridge_connector->bridge_hdmi->product,
455 &drm_bridge_connector_funcs,
456 &drm_bridge_connector_hdmi_funcs,
457 connector_type, ddc,
458 supported_formats,
459 max_bpc);
460 else
461 ret = drmm_connector_init(drm, connector,
387 &drm_bridge_connector_funcs,462 &drm_bridge_connector_funcs,
388 connector_type, ddc);463 connector_type, ddc);
389 if (ret) {464 if (ret) {
drivers/gpu/drm/drm_connector.c+201−0
@@ -278,6 +278,7 @@ static int __drm_connector_init(struct drm_device *dev, · 277 unmodified lines
278 INIT_LIST_HEAD(&connector->modes);278 INIT_LIST_HEAD(&connector->modes);
279 mutex_init(&connector->mutex);279 mutex_init(&connector->mutex);
280 mutex_init(&connector->edid_override_mutex);280 mutex_init(&connector->edid_override_mutex);
281 mutex_init(&connector->hdmi.infoframes.lock);
281 connector->edid_blob_ptr = NULL;282 connector->edid_blob_ptr = NULL;
282 connector->epoch_counter = 0;283 connector->epoch_counter = 0;
283 connector->tile_blob_ptr = NULL;284 connector->tile_blob_ptr = NULL;
@@ -452,6 +453,86 @@ int drmm_connector_init(struct drm_device *dev, · 168 unmodified lines
452}453}
453EXPORT_SYMBOL(drmm_connector_init);454EXPORT_SYMBOL(drmm_connector_init);
454 455
456/**
457 * drmm_connector_hdmi_init - Init a preallocated HDMI connector
458 * @dev: DRM device
459 * @connector: A pointer to the HDMI connector to init
460 * @vendor: HDMI Controller Vendor name
461 * @product: HDMI Controller Product name
462 * @funcs: callbacks for this connector
463 * @hdmi_funcs: HDMI-related callbacks for this connector
464 * @connector_type: user visible type of the connector
465 * @ddc: optional pointer to the associated ddc adapter
466 * @supported_formats: Bitmask of @hdmi_colorspace listing supported output formats
467 * @max_bpc: Maximum bits per char the HDMI connector supports
468 *
469 * Initialises a preallocated HDMI connector. Connectors can be
470 * subclassed as part of driver connector objects.
471 *
472 * Cleanup is automatically handled with a call to
473 * drm_connector_cleanup() in a DRM-managed action.
474 *
475 * The connector structure should be allocated with drmm_kzalloc().
476 *
477 * Returns:
478 * Zero on success, error code on failure.
479 */
480int drmm_connector_hdmi_init(struct drm_device *dev,
481 struct drm_connector *connector,
482 const char *vendor, const char *product,
483 const struct drm_connector_funcs *funcs,
484 const struct drm_connector_hdmi_funcs *hdmi_funcs,
485 int connector_type,
486 struct i2c_adapter *ddc,
487 unsigned long supported_formats,
488 unsigned int max_bpc)
489{
490 int ret;
491
492 if (!vendor || !product)
493 return -EINVAL;
494
495 if ((strlen(vendor) > DRM_CONNECTOR_HDMI_VENDOR_LEN) ||
496 (strlen(product) > DRM_CONNECTOR_HDMI_PRODUCT_LEN))
497 return -EINVAL;
498
499 if (!(connector_type == DRM_MODE_CONNECTOR_HDMIA ||
500 connector_type == DRM_MODE_CONNECTOR_HDMIB))
501 return -EINVAL;
502
503 if (!supported_formats || !(supported_formats & BIT(HDMI_COLORSPACE_RGB)))
504 return -EINVAL;
505
506 if (!(max_bpc == 8 || max_bpc == 10 || max_bpc == 12))
507 return -EINVAL;
508
509 ret = drmm_connector_init(dev, connector, funcs, connector_type, ddc);
510 if (ret)
511 return ret;
512
513 connector->hdmi.supported_formats = supported_formats;
514 strtomem_pad(connector->hdmi.vendor, vendor, 0);
515 strtomem_pad(connector->hdmi.product, product, 0);
516
517 /*
518 * drm_connector_attach_max_bpc_property() requires the
519 * connector to have a state.
520 */
521 if (connector->funcs->reset)
522 connector->funcs->reset(connector);
523
524 drm_connector_attach_max_bpc_property(connector, 8, max_bpc);
525 connector->max_bpc = max_bpc;
526
527 if (max_bpc > 8)
528 drm_connector_attach_hdr_output_metadata_property(connector);
529
530 connector->hdmi.funcs = hdmi_funcs;
531
532 return 0;
533}
534EXPORT_SYMBOL(drmm_connector_hdmi_init);
535
455/**536/**
456 * drm_connector_attach_edid_property - attach edid property.537 * drm_connector_attach_edid_property - attach edid property.
457 * @connector: the connector538 * @connector: the connector
@@ -584,6 +665,7 @@ void drm_connector_cleanup(struct drm_connector *connector) · 126 unmodified lines
584 connector->funcs->atomic_destroy_state(connector,665 connector->funcs->atomic_destroy_state(connector,
585 connector->state);666 connector->state);
586 667
668 mutex_destroy(&connector->hdmi.infoframes.lock);
587 mutex_destroy(&connector->mutex);669 mutex_destroy(&connector->mutex);
588 670
589 memset(connector, 0, sizeof(*connector));671 memset(connector, 0, sizeof(*connector));
@@ -1005,6 +1087,7 @@ static const struct drm_prop_enum_list drm_tv_mode_enum_list[] = { · 415 unmodified lines
1005 { DRM_MODE_TV_MODE_PAL_M, "PAL-M" },1087 { DRM_MODE_TV_MODE_PAL_M, "PAL-M" },
1006 { DRM_MODE_TV_MODE_PAL_N, "PAL-N" },1088 { DRM_MODE_TV_MODE_PAL_N, "PAL-N" },
1007 { DRM_MODE_TV_MODE_SECAM, "SECAM" },1089 { DRM_MODE_TV_MODE_SECAM, "SECAM" },
1090 { DRM_MODE_TV_MODE_MONOCHROME, "Mono" },
1008};1091};
1009DRM_ENUM_NAME_FN(drm_get_tv_mode_name, drm_tv_mode_enum_list)1092DRM_ENUM_NAME_FN(drm_get_tv_mode_name, drm_tv_mode_enum_list)
1010 1093
@@ -1144,6 +1227,53 @@ static const u32 dp_colorspaces = · 133 unmodified lines
1144 BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) |1227 BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) |
1145 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);1228 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
1146 1229
1230static const struct drm_prop_enum_list broadcast_rgb_names[] = {
1231 { DRM_HDMI_BROADCAST_RGB_AUTO, "Automatic" },
1232 { DRM_HDMI_BROADCAST_RGB_FULL, "Full" },
1233 { DRM_HDMI_BROADCAST_RGB_LIMITED, "Limited 16:235" },
1234};
1235
1236/*
1237 * drm_hdmi_connector_get_broadcast_rgb_name - Return a string for HDMI connector RGB broadcast selection
1238 * @broadcast_rgb: Broadcast RGB selection to compute name of
1239 *
1240 * Returns: the name of the Broadcast RGB selection, or NULL if the type
1241 * is not valid.
1242 */
1243const char *
1244drm_hdmi_connector_get_broadcast_rgb_name(enum drm_hdmi_broadcast_rgb broadcast_rgb)
1245{
1246 if (broadcast_rgb >= ARRAY_SIZE(broadcast_rgb_names))
1247 return NULL;
1248
1249 return broadcast_rgb_names[broadcast_rgb].name;
1250}
1251EXPORT_SYMBOL(drm_hdmi_connector_get_broadcast_rgb_name);
1252
1253static const char * const output_format_str[] = {
1254 [HDMI_COLORSPACE_RGB] = "RGB",
1255 [HDMI_COLORSPACE_YUV420] = "YUV 4:2:0",
1256 [HDMI_COLORSPACE_YUV422] = "YUV 4:2:2",
1257 [HDMI_COLORSPACE_YUV444] = "YUV 4:4:4",
1258};
1259
1260/*
1261 * drm_hdmi_connector_get_output_format_name() - Return a string for HDMI connector output format
1262 * @fmt: Output format to compute name of
1263 *
1264 * Returns: the name of the output format, or NULL if the type is not
1265 * valid.
1266 */
1267const char *
1268drm_hdmi_connector_get_output_format_name(enum hdmi_colorspace fmt)
1269{
1270 if (fmt >= ARRAY_SIZE(output_format_str))
1271 return NULL;
1272
1273 return output_format_str[fmt];
1274}
1275EXPORT_SYMBOL(drm_hdmi_connector_get_output_format_name);
1276
1147/**1277/**
1148 * DOC: standard connector properties1278 * DOC: standard connector properties
1149 *1279 *
@@ -1616,6 +1746,38 @@ EXPORT_SYMBOL(drm_connector_attach_dp_subconnector_property); · 466 unmodified lines
1616/**1746/**
1617 * DOC: HDMI connector properties1747 * DOC: HDMI connector properties
1618 *1748 *
1749 * Broadcast RGB (HDMI specific)
1750 * Indicates the Quantization Range (Full vs Limited) used. The color
1751 * processing pipeline will be adjusted to match the value of the
1752 * property, and the Infoframes will be generated and sent accordingly.
1753 *
1754 * This property is only relevant if the HDMI output format is RGB. If
1755 * it's one of the YCbCr variant, it will be ignored.
1756 *
1757 * The CRTC attached to the connector must be configured by user-space to
1758 * always produce full-range pixels.
1759 *
1760 * The value of this property can be one of the following:
1761 *
1762 * Automatic:
1763 * The quantization range is selected automatically based on the
1764 * mode according to the HDMI specifications (HDMI 1.4b - Section
1765 * 6.6 - Video Quantization Ranges).
1766 *
1767 * Full:
1768 * Full quantization range is forced.
1769 *
1770 * Limited 16:235:
1771 * Limited quantization range is forced. Unlike the name suggests,
1772 * this works for any number of bits-per-component.
1773 *
1774 * Property values other than Automatic can result in colors being off (if
1775 * limited is selected but the display expects full), or a black screen
1776 * (if full is selected but the display expects limited).
1777 *
1778 * Drivers can set up this property by calling
1779 * drm_connector_attach_broadcast_rgb_property().
1780 *
1619 * content type (HDMI specific):1781 * content type (HDMI specific):
1620 * Indicates content type setting to be used in HDMI infoframes to indicate1782 * Indicates content type setting to be used in HDMI infoframes to indicate
1621 * content type for the external device, so that it adjusts its display1783 * content type for the external device, so that it adjusts its display
@@ -1697,6 +1859,12 @@ EXPORT_SYMBOL(drm_connector_attach_dp_subconnector_property); · 75 unmodified lines
1697 * TV Mode is CCIR System B (aka 625-lines) together with1859 * TV Mode is CCIR System B (aka 625-lines) together with
1698 * the SECAM Color Encoding.1860 * the SECAM Color Encoding.
1699 *1861 *
1862 * Mono:
1863 *
1864 * Use timings appropriate to the DRM mode, including
1865 * equalizing pulses for a 525-line or 625-line mode,
1866 * with no pedestal or color encoding.
1867 *
1700 * Drivers can set up this property by calling1868 * Drivers can set up this property by calling
1701 * drm_mode_create_tv_properties().1869 * drm_mode_create_tv_properties().
1702 */1870 */
@@ -2478,6 +2646,39 @@ int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *conn · 775 unmodified lines
2478}2646}
2479EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property);2647EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property);
2480 2648
2649/**
2650 * drm_connector_attach_broadcast_rgb_property - attach "Broadcast RGB" property
2651 * @connector: connector to attach the property on.
2652 *
2653 * This is used to add support for forcing the RGB range on a connector
2654 *
2655 * Returns:
2656 * Zero on success, negative errno on failure.
2657 */
2658int drm_connector_attach_broadcast_rgb_property(struct drm_connector *connector)
2659{
2660 struct drm_device *dev = connector->dev;
2661 struct drm_property *prop;
2662
2663 prop = connector->broadcast_rgb_property;
2664 if (!prop) {
2665 prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
2666 "Broadcast RGB",
2667 broadcast_rgb_names,
2668 ARRAY_SIZE(broadcast_rgb_names));
2669 if (!prop)
2670 return -EINVAL;
2671
2672 connector->broadcast_rgb_property = prop;
2673 }
2674
2675 drm_object_attach_property(&connector->base, prop,
2676 DRM_HDMI_BROADCAST_RGB_AUTO);
2677
2678 return 0;
2679}
2680EXPORT_SYMBOL(drm_connector_attach_broadcast_rgb_property);
2681
2481/**2682/**
2482 * drm_connector_attach_colorspace_property - attach "Colorspace" property2683 * drm_connector_attach_colorspace_property - attach "Colorspace" property
2483 * @connector: connector to attach the property on.2684 * @connector: connector to attach the property on.
drivers/gpu/drm/drm_crtc_internal.h+2−0
@@ -303,6 +303,8 @@ const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid, · 302 unmodified lines
303 int ext_id, int *ext_index);303 int ext_id, int *ext_index);
304void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad);304void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad);
305void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad);305void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad);
306ssize_t drm_edid_connector_property_show(struct drm_connector *connector,
307 char *buf, loff_t off, size_t count);
306 308
307/* drm_edid_load.c */309/* drm_edid_load.c */
308#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE310#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
drivers/gpu/drm/drm_debugfs.c+156−2
@@ -520,6 +520,156 @@ static const struct file_operations drm_connector_fops = { · 519 unmodified lines
520 .write = connector_write520 .write = connector_write
521};521};
522 522
523#define HDMI_MAX_INFOFRAME_SIZE 29
524
525static ssize_t
526audio_infoframe_read(struct file *filp, char __user *ubuf, size_t count, loff_t *ppos)
527{
528 struct drm_connector_hdmi_infoframe *infoframe;
529 struct drm_connector *connector;
530 union hdmi_infoframe *frame;
531 u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)];
532 ssize_t len = 0;
533
534 connector = filp->private_data;
535 mutex_lock(&connector->hdmi.infoframes.lock);
536
537 infoframe = &connector->hdmi.infoframes.audio;
538 if (!infoframe->set)
539 goto out;
540
541 frame = &infoframe->data;
542 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
543 if (len < 0)
544 goto out;
545
546 len = simple_read_from_buffer(ubuf, count, ppos, buf, len);
547
548out:
549 mutex_unlock(&connector->hdmi.infoframes.lock);
550 return len;
551}
552
553static const struct file_operations audio_infoframe_fops = {
554 .owner = THIS_MODULE,
555 .open = simple_open,
556 .read = audio_infoframe_read,
557};
558
559static int create_hdmi_audio_infoframe_file(struct drm_connector *connector,
560 struct dentry *parent)
561{
562 struct dentry *file;
563
564 file = debugfs_create_file("audio", 0400, parent, connector, &audio_infoframe_fops);
565 if (IS_ERR(file))
566 return PTR_ERR(file);
567
568 return 0;
569}
570
571#define DEFINE_INFOFRAME_FILE(_f) \
572static ssize_t _f##_read_infoframe(struct file *filp, \
573 char __user *ubuf, \
574 size_t count, \
575 loff_t *ppos) \
576{ \
577 struct drm_connector_hdmi_infoframe *infoframe; \
578 struct drm_connector_state *conn_state; \
579 struct drm_connector *connector; \
580 union hdmi_infoframe *frame; \
581 struct drm_device *dev; \
582 u8 buf[HDMI_MAX_INFOFRAME_SIZE]; \
583 ssize_t len = 0; \
584 \
585 connector = filp->private_data; \
586 dev = connector->dev; \
587 \
588 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); \
589 \
590 conn_state = connector->state; \
591 infoframe = &conn_state->hdmi.infoframes._f; \
592 if (!infoframe->set) \
593 goto out; \
594 \
595 frame = &infoframe->data; \
596 len = hdmi_infoframe_pack(frame, buf, sizeof(buf)); \
597 if (len < 0) \
598 goto out; \
599 \
600 len = simple_read_from_buffer(ubuf, count, ppos, buf, len); \
601 \
602out: \
603 drm_modeset_unlock(&dev->mode_config.connection_mutex); \
604 return len; \
605} \
606\
607static const struct file_operations _f##_infoframe_fops = { \
608 .owner = THIS_MODULE, \
609 .open = simple_open, \
610 .read = _f##_read_infoframe, \
611}; \
612\
613static int create_hdmi_## _f ## _infoframe_file(struct drm_connector *connector, \
614 struct dentry *parent) \
615{ \
616 struct dentry *file; \
617 \
618 file = debugfs_create_file(#_f, 0400, parent, connector, &_f ## _infoframe_fops); \
619 if (IS_ERR(file)) \
620 return PTR_ERR(file); \
621 \
622 return 0; \
623}
624
625DEFINE_INFOFRAME_FILE(avi);
626DEFINE_INFOFRAME_FILE(hdmi);
627DEFINE_INFOFRAME_FILE(hdr_drm);
628DEFINE_INFOFRAME_FILE(spd);
629
630static int create_hdmi_infoframe_files(struct drm_connector *connector,
631 struct dentry *parent)
632{
633 int ret;
634
635 ret = create_hdmi_audio_infoframe_file(connector, parent);
636 if (ret)
637 return ret;
638
639 ret = create_hdmi_avi_infoframe_file(connector, parent);
640 if (ret)
641 return ret;
642
643 ret = create_hdmi_hdmi_infoframe_file(connector, parent);
644 if (ret)
645 return ret;
646
647 ret = create_hdmi_hdr_drm_infoframe_file(connector, parent);
648 if (ret)
649 return ret;
650
651 ret = create_hdmi_spd_infoframe_file(connector, parent);
652 if (ret)
653 return ret;
654
655 return 0;
656}
657
658static void hdmi_debugfs_add(struct drm_connector *connector)
659{
660 struct dentry *dir;
661
662 if (!(connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
663 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB))
664 return;
665
666 dir = debugfs_create_dir("infoframes", connector->debugfs_entry);
667 if (IS_ERR(dir))
668 return;
669
670 create_hdmi_infoframe_files(connector, dir);
671}
672
523void drm_debugfs_connector_add(struct drm_connector *connector)673void drm_debugfs_connector_add(struct drm_connector *connector)
524{674{
525 struct drm_device *dev = connector->dev;675 struct drm_device *dev = connector->dev;
@@ -547,6 +697,8 @@ void drm_debugfs_connector_add(struct drm_connector *connector) · 21 unmodified lines
547 debugfs_create_file("output_bpc", 0444, root, connector,697 debugfs_create_file("output_bpc", 0444, root, connector,
548 &output_bpc_fops);698 &output_bpc_fops);
549 699
700 hdmi_debugfs_add(connector);
701
550 if (connector->funcs->debugfs_init)702 if (connector->funcs->debugfs_init)
551 connector->funcs->debugfs_init(connector, root);703 connector->funcs->debugfs_init(connector, root);
552}704}
@@ -597,10 +749,10 @@ static int bridges_show(struct seq_file *m, void *data) · 44 unmodified lines
597 drm_printf(&p, "\ttype: [%d] %s\n",749 drm_printf(&p, "\ttype: [%d] %s\n",
598 bridge->type,750 bridge->type,
599 drm_get_connector_type_name(bridge->type));751 drm_get_connector_type_name(bridge->type));
600#ifdef CONFIG_OF752
601 if (bridge->of_node)753 if (bridge->of_node)
602 drm_printf(&p, "\tOF: %pOFfc\n", bridge->of_node);754 drm_printf(&p, "\tOF: %pOFfc\n", bridge->of_node);
603#endif755
604 drm_printf(&p, "\tops: [0x%x]", bridge->ops);756 drm_printf(&p, "\tops: [0x%x]", bridge->ops);
605 if (bridge->ops & DRM_BRIDGE_OP_DETECT)757 if (bridge->ops & DRM_BRIDGE_OP_DETECT)
606 drm_puts(&p, " detect");758 drm_puts(&p, " detect");
@@ -610,6 +762,8 @@ static int bridges_show(struct seq_file *m, void *data) · 3 unmodified lines
610 drm_puts(&p, " hpd");762 drm_puts(&p, " hpd");
611 if (bridge->ops & DRM_BRIDGE_OP_MODES)763 if (bridge->ops & DRM_BRIDGE_OP_MODES)
612 drm_puts(&p, " modes");764 drm_puts(&p, " modes");
765 if (bridge->ops & DRM_BRIDGE_OP_HDMI)
766 drm_puts(&p, " hdmi");
613 drm_puts(&p, "\n");767 drm_puts(&p, "\n");
614 }768 }
615 769
drivers/gpu/drm/drm_drv.c+3−3
@@ -346,7 +346,7 @@ void drm_minor_release(struct drm_minor *minor) · 345 unmodified lines
346 * if (ret)346 * if (ret)
347 * return ret;347 * return ret;
348 *348 *
349 * drm_fbdev_generic_setup(drm, 32);349 * drm_fbdev_{...}_setup(drm, 32);
350 *350 *
351 * return 0;351 * return 0;
352 * }352 * }
@@ -947,9 +947,9 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags) · 594 unmodified lines
947 }947 }
948 drm_panic_register(dev);948 drm_panic_register(dev);
949 949
950 DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",950 DRM_INFO("Initialized %s %d.%d.%d for %s on minor %d\n",
951 driver->name, driver->major, driver->minor,951 driver->name, driver->major, driver->minor,
952 driver->patchlevel, driver->date,952 driver->patchlevel,
953 dev->dev ? dev_name(dev->dev) : "virtual device",953 dev->dev ? dev_name(dev->dev) : "virtual device",
954 dev->primary ? dev->primary->index : dev->accel->index);954 dev->primary ? dev->primary->index : dev->accel->index);
955 955
drivers/gpu/drm/drm_edid.c+33−28
@@ -2464,34 +2464,6 @@ fail: · 2463 unmodified lines
2464 return NULL;2464 return NULL;
2465}2465}
2466 2466
2467/**
2468 * drm_do_get_edid - get EDID data using a custom EDID block read function
2469 * @connector: connector we're probing
2470 * @read_block: EDID block read function
2471 * @context: private data passed to the block read function
2472 *
2473 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2474 * exposes a different interface to read EDID blocks this function can be used
2475 * to get EDID data using a custom block read function.
2476 *
2477 * As in the general case the DDC bus is accessible by the kernel at the I2C
2478 * level, drivers must make all reasonable efforts to expose it as an I2C
2479 * adapter and use drm_get_edid() instead of abusing this function.
2480 *
2481 * The EDID may be overridden using debugfs override_edid or firmware EDID
2482 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2483 * order. Having either of them bypasses actual EDID reads.
2484 *
2485 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2486 */
2487struct edid *drm_do_get_edid(struct drm_connector *connector,
2488 read_block_fn read_block,
2489 void *context)
2490{
2491 return _drm_do_get_edid(connector, read_block, context, NULL);
2492}
2493EXPORT_SYMBOL_GPL(drm_do_get_edid);
2494
2495/**2467/**
2496 * drm_edid_raw - Get a pointer to the raw EDID data.2468 * drm_edid_raw - Get a pointer to the raw EDID data.
2497 * @drm_edid: drm_edid container2469 * @drm_edid: drm_edid container
@@ -6969,6 +6941,39 @@ out: · 4471 unmodified lines
6969 return ret;6941 return ret;
6970}6942}
6971 6943
6944/* For sysfs edid show implementation */
6945ssize_t drm_edid_connector_property_show(struct drm_connector *connector,
6946 char *buf, loff_t off, size_t count)
6947{
6948 const void *edid;
6949 size_t size;
6950 ssize_t ret = 0;
6951
6952 mutex_lock(&connector->dev->mode_config.mutex);
6953
6954 if (!connector->edid_blob_ptr)
6955 goto unlock;
6956
6957 edid = connector->edid_blob_ptr->data;
6958 size = connector->edid_blob_ptr->length;
6959 if (!edid)
6960 goto unlock;
6961
6962 if (off >= size)
6963 goto unlock;
6964
6965 if (off + count > size)
6966 count = size - off;
6967
6968 memcpy(buf, edid + off, count);
6969
6970 ret = count;
6971unlock:
6972 mutex_unlock(&connector->dev->mode_config.mutex);
6973
6974 return ret;
6975}
6976
6972/**6977/**
6973 * drm_edid_connector_update - Update connector information from EDID6978 * drm_edid_connector_update - Update connector information from EDID
6974 * @connector: Connector6979 * @connector: Connector
drivers/gpu/drm/drm_fb_helper.c+2−9
@@ -85,12 +85,8 @@ static DEFINE_MUTEX(kernel_fb_helper_lock); · 84 unmodified lines
85 * The fb helper functions are useful to provide an fbdev on top of a drm kernel85 * The fb helper functions are useful to provide an fbdev on top of a drm kernel
86 * mode setting driver. They can be used mostly independently from the crtc86 * mode setting driver. They can be used mostly independently from the crtc
87 * helper functions used by many drivers to implement the kernel mode setting87 * helper functions used by many drivers to implement the kernel mode setting
88 * interfaces.88 * interfaces. Drivers that use one of the shared memory managers, TTM, SHMEM,
89 *89 * DMA, should instead use the corresponding fbdev emulation.
90 * Drivers that support a dumb buffer with a virtual address and mmap support,
91 * should try out the generic fbdev emulation using drm_fbdev_generic_setup().
92 * It will automatically set up deferred I/O if the driver requires a shadow
93 * buffer.
94 *90 *
95 * Existing fbdev implementations should restore the fbdev console by using91 * Existing fbdev implementations should restore the fbdev console by using
96 * drm_fb_helper_lastclose() as their &drm_driver.lastclose callback.92 * drm_fb_helper_lastclose() as their &drm_driver.lastclose callback.
@@ -126,9 +122,6 @@ static DEFINE_MUTEX(kernel_fb_helper_lock); · 29 unmodified lines
126 * atomic context. If drm_fb_helper_deferred_io() is used as the deferred_io122 * atomic context. If drm_fb_helper_deferred_io() is used as the deferred_io
127 * callback it will also schedule dirty_work with the damage collected from the123 * callback it will also schedule dirty_work with the damage collected from the
128 * mmap page writes.124 * mmap page writes.
129 *
130 * Deferred I/O is not compatible with SHMEM. Such drivers should request an
131 * fbdev shadow buffer and call drm_fbdev_generic_setup() instead.
132 */125 */
133 126
134static void drm_fb_helper_restore_lut_atomic(struct drm_crtc *crtc)127static void drm_fb_helper_restore_lut_atomic(struct drm_crtc *crtc)
drivers/gpu/drm/drm_fbdev_dma.c+52−14
@@ -4,6 +4,7 @@ · 3 unmodified lines
4 4
5#include <drm/drm_crtc_helper.h>5#include <drm/drm_crtc_helper.h>
6#include <drm/drm_drv.h>6#include <drm/drm_drv.h>
7#include <drm/drm_fb_dma_helper.h>
7#include <drm/drm_fb_helper.h>8#include <drm/drm_fb_helper.h>
8#include <drm/drm_framebuffer.h>9#include <drm/drm_framebuffer.h>
9#include <drm/drm_gem_dma_helper.h>10#include <drm/drm_gem_dma_helper.h>
@@ -35,6 +36,22 @@ static int drm_fbdev_dma_fb_release(struct fb_info *info, int user) · 25 unmodified lines
35 return 0;36 return 0;
36}37}
37 38
39FB_GEN_DEFAULT_DEFERRED_DMAMEM_OPS(drm_fbdev_dma,
40 drm_fb_helper_damage_range,
41 drm_fb_helper_damage_area);
42
43static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
44{
45 struct drm_fb_helper *fb_helper = info->par;
46 struct drm_framebuffer *fb = fb_helper->fb;
47 struct drm_gem_dma_object *dma = drm_fb_dma_get_gem_obj(fb, 0);
48
49 if (!dma->map_noncoherent)
50 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
51
52 return fb_deferred_io_mmap(info, vma);
53}
54
38static void drm_fbdev_dma_fb_destroy(struct fb_info *info)55static void drm_fbdev_dma_fb_destroy(struct fb_info *info)
39{56{
40 struct drm_fb_helper *fb_helper = info->par;57 struct drm_fb_helper *fb_helper = info->par;
@@ -42,6 +59,7 @@ static void drm_fbdev_dma_fb_destroy(struct fb_info *info) · 1 unmodified line
42 if (!fb_helper->dev)59 if (!fb_helper->dev)
43 return;60 return;
44 61
62 fb_deferred_io_cleanup(info);
45 drm_fb_helper_fini(fb_helper);63 drm_fb_helper_fini(fb_helper);
46 64
47 drm_client_buffer_vunmap(fb_helper->buffer);65 drm_client_buffer_vunmap(fb_helper->buffer);
@@ -51,20 +69,13 @@ static void drm_fbdev_dma_fb_destroy(struct fb_info *info) · 3 unmodified lines
51 kfree(fb_helper);69 kfree(fb_helper);
52}70}
53 71
54static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
55{
56 struct drm_fb_helper *fb_helper = info->par;
57
58 return drm_gem_prime_mmap(fb_helper->buffer->gem, vma);
59}
60
61static const struct fb_ops drm_fbdev_dma_fb_ops = {72static const struct fb_ops drm_fbdev_dma_fb_ops = {
62 .owner = THIS_MODULE,73 .owner = THIS_MODULE,
63 .fb_open = drm_fbdev_dma_fb_open,74 .fb_open = drm_fbdev_dma_fb_open,
64 .fb_release = drm_fbdev_dma_fb_release,75 .fb_release = drm_fbdev_dma_fb_release,
65 __FB_DEFAULT_DMAMEM_OPS_RDWR,76 __FB_DEFAULT_DEFERRED_OPS_RDWR(drm_fbdev_dma),
66 DRM_FB_HELPER_DEFAULT_OPS,77 DRM_FB_HELPER_DEFAULT_OPS,
67 __FB_DEFAULT_DMAMEM_OPS_DRAW,78 __FB_DEFAULT_DEFERRED_OPS_DRAW(drm_fbdev_dma),
68 .fb_mmap = drm_fbdev_dma_fb_mmap,79 .fb_mmap = drm_fbdev_dma_fb_mmap,
69 .fb_destroy = drm_fbdev_dma_fb_destroy,80 .fb_destroy = drm_fbdev_dma_fb_destroy,
70};81};
@@ -98,10 +109,6 @@ static int drm_fbdev_dma_helper_fb_probe(struct drm_fb_helper *fb_helper, · 27 unmodified lines
98 dma_obj = to_drm_gem_dma_obj(buffer->gem);109 dma_obj = to_drm_gem_dma_obj(buffer->gem);
99 110
100 fb = buffer->fb;111 fb = buffer->fb;
101 if (drm_WARN_ON(dev, fb->funcs->dirty)) {
102 ret = -ENODEV; /* damage handling not supported; use generic emulation */
103 goto err_drm_client_buffer_delete;
104 }
105 112
106 ret = drm_client_buffer_vmap(buffer, &map);113 ret = drm_client_buffer_vmap(buffer, &map);
107 if (ret) {114 if (ret) {
@@ -112,7 +119,7 @@ static int drm_fbdev_dma_helper_fb_probe(struct drm_fb_helper *fb_helper, · 4 unmodified lines
112 }119 }
113 120
114 fb_helper->buffer = buffer;121 fb_helper->buffer = buffer;
115 fb_helper->fb = buffer->fb;122 fb_helper->fb = fb;
116 123
117 info = drm_fb_helper_alloc_info(fb_helper);124 info = drm_fb_helper_alloc_info(fb_helper);
118 if (IS_ERR(info)) {125 if (IS_ERR(info)) {
@@ -133,8 +140,19 @@ static int drm_fbdev_dma_helper_fb_probe(struct drm_fb_helper *fb_helper, · 14 unmodified lines
133 info->fix.smem_start = page_to_phys(virt_to_page(info->screen_buffer));140 info->fix.smem_start = page_to_phys(virt_to_page(info->screen_buffer));
134 info->fix.smem_len = info->screen_size;141 info->fix.smem_len = info->screen_size;
135 142
143 /* deferred I/O */
144 fb_helper->fbdefio.delay = HZ / 20;
145 fb_helper->fbdefio.deferred_io = drm_fb_helper_deferred_io;
146
147 info->fbdefio = &fb_helper->fbdefio;
148 ret = fb_deferred_io_init(info);
149 if (ret)
150 goto err_drm_fb_helper_release_info;
151
136 return 0;152 return 0;
137 153
154err_drm_fb_helper_release_info:
155 drm_fb_helper_release_info(fb_helper);
138err_drm_client_buffer_vunmap:156err_drm_client_buffer_vunmap:
139 fb_helper->fb = NULL;157 fb_helper->fb = NULL;
140 fb_helper->buffer = NULL;158 fb_helper->buffer = NULL;
@@ -144,8 +162,28 @@ err_drm_client_buffer_delete: · 3 unmodified lines
144 return ret;162 return ret;
145}163}
146 164
165static int drm_fbdev_dma_helper_fb_dirty(struct drm_fb_helper *helper,
166 struct drm_clip_rect *clip)
167{
168 struct drm_device *dev = helper->dev;
169 int ret;
170
171 /* Call damage handlers only if necessary */
172 if (!(clip->x1 < clip->x2 && clip->y1 < clip->y2))
173 return 0;
174
175 if (helper->fb->funcs->dirty) {
176 ret = helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1);
177 if (drm_WARN_ONCE(dev, ret, "Dirty helper failed: ret=%d\n", ret))
178 return ret;
179 }
180
181 return 0;
182}
183
147static const struct drm_fb_helper_funcs drm_fbdev_dma_helper_funcs = {184static const struct drm_fb_helper_funcs drm_fbdev_dma_helper_funcs = {
148 .fb_probe = drm_fbdev_dma_helper_fb_probe,185 .fb_probe = drm_fbdev_dma_helper_fb_probe,
186 .fb_dirty = drm_fbdev_dma_helper_fb_dirty,
149};187};
150 188
151/*189/*
drivers/gpu/drm/drm_fbdev_shmem.c+317−0
@@ -0,0 +1,317 @@
1// SPDX-License-Identifier: MIT
2
3#include <linux/fb.h>
4
5#include <drm/drm_crtc_helper.h>
6#include <drm/drm_drv.h>
7#include <drm/drm_fb_helper.h>
8#include <drm/drm_framebuffer.h>
9#include <drm/drm_gem_framebuffer_helper.h>
10#include <drm/drm_gem_shmem_helper.h>
11
12#include <drm/drm_fbdev_shmem.h>
13
14/*
15 * struct fb_ops
16 */
17
18static int drm_fbdev_shmem_fb_open(struct fb_info *info, int user)
19{
20 struct drm_fb_helper *fb_helper = info->par;
21
22 /* No need to take a ref for fbcon because it unbinds on unregister */
23 if (user && !try_module_get(fb_helper->dev->driver->fops->owner))
24 return -ENODEV;
25
26 return 0;
27}
28
29static int drm_fbdev_shmem_fb_release(struct fb_info *info, int user)
30{
31 struct drm_fb_helper *fb_helper = info->par;
32
33 if (user)
34 module_put(fb_helper->dev->driver->fops->owner);
35
36 return 0;
37}
38
39FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(drm_fbdev_shmem,
40 drm_fb_helper_damage_range,
41 drm_fb_helper_damage_area);
42
43static int drm_fbdev_shmem_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
44{
45 struct drm_fb_helper *fb_helper = info->par;
46 struct drm_framebuffer *fb = fb_helper->fb;
47 struct drm_gem_object *obj = drm_gem_fb_get_obj(fb, 0);
48 struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
49
50 if (shmem->map_wc)
51 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
52
53 return fb_deferred_io_mmap(info, vma);
54}
55
56static void drm_fbdev_shmem_fb_destroy(struct fb_info *info)
57{
58 struct drm_fb_helper *fb_helper = info->par;
59
60 if (!fb_helper->dev)
61 return;
62
63 fb_deferred_io_cleanup(info);
64 drm_fb_helper_fini(fb_helper);
65
66 drm_client_buffer_vunmap(fb_helper->buffer);
67 drm_client_framebuffer_delete(fb_helper->buffer);
68 drm_client_release(&fb_helper->client);
69 drm_fb_helper_unprepare(fb_helper);
70 kfree(fb_helper);
71}
72
73static const struct fb_ops drm_fbdev_shmem_fb_ops = {
74 .owner = THIS_MODULE,
75 .fb_open = drm_fbdev_shmem_fb_open,
76 .fb_release = drm_fbdev_shmem_fb_release,
77 __FB_DEFAULT_DEFERRED_OPS_RDWR(drm_fbdev_shmem),
78 DRM_FB_HELPER_DEFAULT_OPS,
79 __FB_DEFAULT_DEFERRED_OPS_DRAW(drm_fbdev_shmem),
80 .fb_mmap = drm_fbdev_shmem_fb_mmap,
81 .fb_destroy = drm_fbdev_shmem_fb_destroy,
82};
83
84static struct page *drm_fbdev_shmem_get_page(struct fb_info *info, unsigned long offset)
85{
86 struct drm_fb_helper *fb_helper = info->par;
87 struct drm_framebuffer *fb = fb_helper->fb;
88 struct drm_gem_object *obj = drm_gem_fb_get_obj(fb, 0);
89 struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
90 unsigned int i = offset >> PAGE_SHIFT;
91 struct page *page;
92
93 if (fb_WARN_ON_ONCE(info, offset > obj->size))
94 return NULL;
95
96 page = shmem->pages[i]; // protected by active vmap
97 if (page)
98 get_page(page);
99 fb_WARN_ON_ONCE(info, !page);
100
101 return page;
102}
103
104/*
105 * struct drm_fb_helper
106 */
107
108static int drm_fbdev_shmem_helper_fb_probe(struct drm_fb_helper *fb_helper,
109 struct drm_fb_helper_surface_size *sizes)
110{
111 struct drm_client_dev *client = &fb_helper->client;
112 struct drm_device *dev = fb_helper->dev;
113 struct drm_client_buffer *buffer;
114 struct drm_gem_shmem_object *shmem;
115 struct drm_framebuffer *fb;
116 struct fb_info *info;
117 u32 format;
118 struct iosys_map map;
119 int ret;
120
121 drm_dbg_kms(dev, "surface width(%d), height(%d) and bpp(%d)\n",
122 sizes->surface_width, sizes->surface_height,
123 sizes->surface_bpp);
124
125 format = drm_driver_legacy_fb_format(dev, sizes->surface_bpp, sizes->surface_depth);
126 buffer = drm_client_framebuffer_create(client, sizes->surface_width,
127 sizes->surface_height, format);
128 if (IS_ERR(buffer))
129 return PTR_ERR(buffer);
130 shmem = to_drm_gem_shmem_obj(buffer->gem);
131
132 fb = buffer->fb;
133
134 ret = drm_client_buffer_vmap(buffer, &map);
135 if (ret) {
136 goto err_drm_client_buffer_delete;
137 } else if (drm_WARN_ON(dev, map.is_iomem)) {
138 ret = -ENODEV; /* I/O memory not supported; use generic emulation */
139 goto err_drm_client_buffer_delete;
140 }
141
142 fb_helper->buffer = buffer;
143 fb_helper->fb = fb;
144
145 info = drm_fb_helper_alloc_info(fb_helper);
146 if (IS_ERR(info)) {
147 ret = PTR_ERR(info);
148 goto err_drm_client_buffer_vunmap;
149 }
150
151 drm_fb_helper_fill_info(info, fb_helper, sizes);
152
153 info->fbops = &drm_fbdev_shmem_fb_ops;
154
155 /* screen */
156 info->flags |= FBINFO_VIRTFB; /* system memory */
157 if (!shmem->map_wc)
158 info->flags |= FBINFO_READS_FAST; /* signal caching */
159 info->screen_size = sizes->surface_height * fb->pitches[0];
160 info->screen_buffer = map.vaddr;
161 info->fix.smem_len = info->screen_size;
162
163 /* deferred I/O */
164 fb_helper->fbdefio.delay = HZ / 20;
165 fb_helper->fbdefio.get_page = drm_fbdev_shmem_get_page;
166 fb_helper->fbdefio.deferred_io = drm_fb_helper_deferred_io;
167
168 info->fbdefio = &fb_helper->fbdefio;
169 ret = fb_deferred_io_init(info);
170 if (ret)
171 goto err_drm_fb_helper_release_info;
172
173 return 0;
174
175err_drm_fb_helper_release_info:
176 drm_fb_helper_release_info(fb_helper);
177err_drm_client_buffer_vunmap:
178 fb_helper->fb = NULL;
179 fb_helper->buffer = NULL;
180 drm_client_buffer_vunmap(buffer);
181err_drm_client_buffer_delete:
182 drm_client_framebuffer_delete(buffer);
183 return ret;
184}
185
186static int drm_fbdev_shmem_helper_fb_dirty(struct drm_fb_helper *helper,
187 struct drm_clip_rect *clip)
188{
189 struct drm_device *dev = helper->dev;
190 int ret;
191
192 /* Call damage handlers only if necessary */
193 if (!(clip->x1 < clip->x2 && clip->y1 < clip->y2))
194 return 0;
195
196 if (helper->fb->funcs->dirty) {
197 ret = helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1);
198 if (drm_WARN_ONCE(dev, ret, "Dirty helper failed: ret=%d\n", ret))
199 return ret;
200 }
201
202 return 0;
203}
204
205static const struct drm_fb_helper_funcs drm_fbdev_shmem_helper_funcs = {
206 .fb_probe = drm_fbdev_shmem_helper_fb_probe,
207 .fb_dirty = drm_fbdev_shmem_helper_fb_dirty,
208};
209
210/*
211 * struct drm_client_funcs
212 */
213
214static void drm_fbdev_shmem_client_unregister(struct drm_client_dev *client)
215{
216 struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);
217
218 if (fb_helper->info) {
219 drm_fb_helper_unregister_info(fb_helper);
220 } else {
221 drm_client_release(&fb_helper->client);
222 drm_fb_helper_unprepare(fb_helper);
223 kfree(fb_helper);
224 }
225}
226
227static int drm_fbdev_shmem_client_restore(struct drm_client_dev *client)
228{
229 drm_fb_helper_lastclose(client->dev);
230
231 return 0;
232}
233
234static int drm_fbdev_shmem_client_hotplug(struct drm_client_dev *client)
235{
236 struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);
237 struct drm_device *dev = client->dev;
238 int ret;
239
240 if (dev->fb_helper)
241 return drm_fb_helper_hotplug_event(dev->fb_helper);
242
243 ret = drm_fb_helper_init(dev, fb_helper);
244 if (ret)
245 goto err_drm_err;
246
247 if (!drm_drv_uses_atomic_modeset(dev))
248 drm_helper_disable_unused_functions(dev);
249
250 ret = drm_fb_helper_initial_config(fb_helper);
251 if (ret)
252 goto err_drm_fb_helper_fini;
253
254 return 0;
255
256err_drm_fb_helper_fini:
257 drm_fb_helper_fini(fb_helper);
258err_drm_err:
259 drm_err(dev, "fbdev-shmem: Failed to setup emulation (ret=%d)\n", ret);
260 return ret;
261}
262
263static const struct drm_client_funcs drm_fbdev_shmem_client_funcs = {
264 .owner = THIS_MODULE,
265 .unregister = drm_fbdev_shmem_client_unregister,
266 .restore = drm_fbdev_shmem_client_restore,
267 .hotplug = drm_fbdev_shmem_client_hotplug,
268};
269
270/**
271 * drm_fbdev_shmem_setup() - Setup fbdev emulation for GEM SHMEM helpers
272 * @dev: DRM device
273 * @preferred_bpp: Preferred bits per pixel for the device.
274 * 32 is used if this is zero.
275 *
276 * This function sets up fbdev emulation for GEM DMA drivers that support
277 * dumb buffers with a virtual address and that can be mmap'ed.
278 * drm_fbdev_shmem_setup() shall be called after the DRM driver registered
279 * the new DRM device with drm_dev_register().
280 *
281 * Restore, hotplug events and teardown are all taken care of. Drivers that do
282 * suspend/resume need to call drm_fb_helper_set_suspend_unlocked() themselves.
283 * Simple drivers might use drm_mode_config_helper_suspend().
284 *
285 * This function is safe to call even when there are no connectors present.
286 * Setup will be retried on the next hotplug event.
287 *
288 * The fbdev is destroyed by drm_dev_unregister().
289 */
290void drm_fbdev_shmem_setup(struct drm_device *dev, unsigned int preferred_bpp)
291{
292 struct drm_fb_helper *fb_helper;
293 int ret;
294
295 drm_WARN(dev, !dev->registered, "Device has not been registered.\n");
296 drm_WARN(dev, dev->fb_helper, "fb_helper is already set!\n");
297
298 fb_helper = kzalloc(sizeof(*fb_helper), GFP_KERNEL);
299 if (!fb_helper)
300 return;
301 drm_fb_helper_prepare(dev, fb_helper, preferred_bpp, &drm_fbdev_shmem_helper_funcs);
302
303 ret = drm_client_init(dev, &fb_helper->client, "fbdev", &drm_fbdev_shmem_client_funcs);
304 if (ret) {
305 drm_err(dev, "Failed to register client: %d\n", ret);
306 goto err_drm_client_init;
307 }
308
309 drm_client_register(&fb_helper->client);
310
311 return;
312
313err_drm_client_init:
314 drm_fb_helper_unprepare(fb_helper);
315 kfree(fb_helper);
316}
317EXPORT_SYMBOL(drm_fbdev_shmem_setup);
drivers/gpu/drm/drm_fbdev_ttm.crenamed from drivers/gpu/drm/drm_fbdev_generic.c+40−40
@@ -10,10 +10,10 @@ · 9 unmodified lines
10#include <drm/drm_gem.h>10#include <drm/drm_gem.h>
11#include <drm/drm_print.h>11#include <drm/drm_print.h>
12 12
13#include <drm/drm_fbdev_generic.h>13#include <drm/drm_fbdev_ttm.h>
14 14
15/* @user: 1=userspace, 0=fbcon */15/* @user: 1=userspace, 0=fbcon */
16static int drm_fbdev_generic_fb_open(struct fb_info *info, int user)16static int drm_fbdev_ttm_fb_open(struct fb_info *info, int user)
17{17{
18 struct drm_fb_helper *fb_helper = info->par;18 struct drm_fb_helper *fb_helper = info->par;
19 19
@@ -24,7 +24,7 @@ static int drm_fbdev_generic_fb_open(struct fb_info *info, int user) · 4 unmodified lines
24 return 0;24 return 0;
25}25}
26 26
27static int drm_fbdev_generic_fb_release(struct fb_info *info, int user)27static int drm_fbdev_ttm_fb_release(struct fb_info *info, int user)
28{28{
29 struct drm_fb_helper *fb_helper = info->par;29 struct drm_fb_helper *fb_helper = info->par;
30 30
@@ -34,11 +34,11 @@ static int drm_fbdev_generic_fb_release(struct fb_info *info, int user) · 3 unmodified lines
34 return 0;34 return 0;
35}35}
36 36
37FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(drm_fbdev_generic,37FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(drm_fbdev_ttm,
38 drm_fb_helper_damage_range,38 drm_fb_helper_damage_range,
39 drm_fb_helper_damage_area);39 drm_fb_helper_damage_area);
40 40
41static void drm_fbdev_generic_fb_destroy(struct fb_info *info)41static void drm_fbdev_ttm_fb_destroy(struct fb_info *info)
42{42{
43 struct drm_fb_helper *fb_helper = info->par;43 struct drm_fb_helper *fb_helper = info->par;
44 void *shadow = info->screen_buffer;44 void *shadow = info->screen_buffer;
@@ -56,19 +56,19 @@ static void drm_fbdev_generic_fb_destroy(struct fb_info *info) · 11 unmodified lines
56 kfree(fb_helper);56 kfree(fb_helper);
57}57}
58 58
59static const struct fb_ops drm_fbdev_generic_fb_ops = {59static const struct fb_ops drm_fbdev_ttm_fb_ops = {
60 .owner = THIS_MODULE,60 .owner = THIS_MODULE,
61 .fb_open = drm_fbdev_generic_fb_open,61 .fb_open = drm_fbdev_ttm_fb_open,
62 .fb_release = drm_fbdev_generic_fb_release,62 .fb_release = drm_fbdev_ttm_fb_release,
63 FB_DEFAULT_DEFERRED_OPS(drm_fbdev_generic),63 FB_DEFAULT_DEFERRED_OPS(drm_fbdev_ttm),
64 DRM_FB_HELPER_DEFAULT_OPS,64 DRM_FB_HELPER_DEFAULT_OPS,
65 .fb_destroy = drm_fbdev_generic_fb_destroy,65 .fb_destroy = drm_fbdev_ttm_fb_destroy,
66};66};
67 67
68/*68/*
69 * This function uses the client API to create a framebuffer backed by a dumb buffer.69 * This function uses the client API to create a framebuffer backed by a dumb buffer.
70 */70 */
71static int drm_fbdev_generic_helper_fb_probe(struct drm_fb_helper *fb_helper,71static int drm_fbdev_ttm_helper_fb_probe(struct drm_fb_helper *fb_helper,
72 struct drm_fb_helper_surface_size *sizes)72 struct drm_fb_helper_surface_size *sizes)
73{73{
74 struct drm_client_dev *client = &fb_helper->client;74 struct drm_client_dev *client = &fb_helper->client;
@@ -108,7 +108,7 @@ static int drm_fbdev_generic_helper_fb_probe(struct drm_fb_helper *fb_helper, · 33 unmodified lines
108 108
109 drm_fb_helper_fill_info(info, fb_helper, sizes);109 drm_fb_helper_fill_info(info, fb_helper, sizes);
110 110
111 info->fbops = &drm_fbdev_generic_fb_ops;111 info->fbops = &drm_fbdev_ttm_fb_ops;
112 112
113 /* screen */113 /* screen */
114 info->flags |= FBINFO_VIRTFB | FBINFO_READS_FAST;114 info->flags |= FBINFO_VIRTFB | FBINFO_READS_FAST;
@@ -137,9 +137,9 @@ err_drm_client_framebuffer_delete: · 22 unmodified lines
137 return ret;137 return ret;
138}138}
139 139
140static void drm_fbdev_generic_damage_blit_real(struct drm_fb_helper *fb_helper,140static void drm_fbdev_ttm_damage_blit_real(struct drm_fb_helper *fb_helper,
141 struct drm_clip_rect *clip,141 struct drm_clip_rect *clip,
142 struct iosys_map *dst)142 struct iosys_map *dst)
143{143{
144 struct drm_framebuffer *fb = fb_helper->fb;144 struct drm_framebuffer *fb = fb_helper->fb;
145 size_t offset = clip->y1 * fb->pitches[0];145 size_t offset = clip->y1 * fb->pitches[0];
@@ -176,8 +176,8 @@ static void drm_fbdev_generic_damage_blit_real(struct drm_fb_helper *fb_helper, · 30 unmodified lines
176 }176 }
177}177}
178 178
179static int drm_fbdev_generic_damage_blit(struct drm_fb_helper *fb_helper,179static int drm_fbdev_ttm_damage_blit(struct drm_fb_helper *fb_helper,
180 struct drm_clip_rect *clip)180 struct drm_clip_rect *clip)
181{181{
182 struct drm_client_buffer *buffer = fb_helper->buffer;182 struct drm_client_buffer *buffer = fb_helper->buffer;
183 struct iosys_map map, dst;183 struct iosys_map map, dst;
@@ -201,7 +201,7 @@ static int drm_fbdev_generic_damage_blit(struct drm_fb_helper *fb_helper, · 17 unmodified lines
201 goto out;201 goto out;
202 202
203 dst = map;203 dst = map;
204 drm_fbdev_generic_damage_blit_real(fb_helper, clip, &dst);204 drm_fbdev_ttm_damage_blit_real(fb_helper, clip, &dst);
205 205
206 drm_client_buffer_vunmap_local(buffer);206 drm_client_buffer_vunmap_local(buffer);
207 207
@@ -211,8 +211,8 @@ out: · 3 unmodified lines
211 return ret;211 return ret;
212}212}
213 213
214static int drm_fbdev_generic_helper_fb_dirty(struct drm_fb_helper *helper,214static int drm_fbdev_ttm_helper_fb_dirty(struct drm_fb_helper *helper,
215 struct drm_clip_rect *clip)215 struct drm_clip_rect *clip)
216{216{
217 struct drm_device *dev = helper->dev;217 struct drm_device *dev = helper->dev;
218 int ret;218 int ret;
@@ -221,7 +221,7 @@ static int drm_fbdev_generic_helper_fb_dirty(struct drm_fb_helper *helper, · 2 unmodified lines
221 if (!(clip->x1 < clip->x2 && clip->y1 < clip->y2))221 if (!(clip->x1 < clip->x2 && clip->y1 < clip->y2))
222 return 0;222 return 0;
223 223
224 ret = drm_fbdev_generic_damage_blit(helper, clip);224 ret = drm_fbdev_ttm_damage_blit(helper, clip);
225 if (drm_WARN_ONCE(dev, ret, "Damage blitter failed: ret=%d\n", ret))225 if (drm_WARN_ONCE(dev, ret, "Damage blitter failed: ret=%d\n", ret))
226 return ret;226 return ret;
227 227
@@ -234,12 +234,12 @@ static int drm_fbdev_generic_helper_fb_dirty(struct drm_fb_helper *helper, · 6 unmodified lines
234 return 0;234 return 0;
235}235}
236 236
237static const struct drm_fb_helper_funcs drm_fbdev_generic_helper_funcs = {237static const struct drm_fb_helper_funcs drm_fbdev_ttm_helper_funcs = {
238 .fb_probe = drm_fbdev_generic_helper_fb_probe,238 .fb_probe = drm_fbdev_ttm_helper_fb_probe,
239 .fb_dirty = drm_fbdev_generic_helper_fb_dirty,239 .fb_dirty = drm_fbdev_ttm_helper_fb_dirty,
240};240};
241 241
242static void drm_fbdev_generic_client_unregister(struct drm_client_dev *client)242static void drm_fbdev_ttm_client_unregister(struct drm_client_dev *client)
243{243{
244 struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);244 struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);
245 245
@@ -252,14 +252,14 @@ static void drm_fbdev_generic_client_unregister(struct drm_client_dev *client) · 6 unmodified lines
252 }252 }
253}253}
254 254
255static int drm_fbdev_generic_client_restore(struct drm_client_dev *client)255static int drm_fbdev_ttm_client_restore(struct drm_client_dev *client)
256{256{
257 drm_fb_helper_lastclose(client->dev);257 drm_fb_helper_lastclose(client->dev);
258 258
259 return 0;259 return 0;
260}260}
261 261
262static int drm_fbdev_generic_client_hotplug(struct drm_client_dev *client)262static int drm_fbdev_ttm_client_hotplug(struct drm_client_dev *client)
263{263{
264 struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);264 struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);
265 struct drm_device *dev = client->dev;265 struct drm_device *dev = client->dev;
@@ -284,32 +284,32 @@ static int drm_fbdev_generic_client_hotplug(struct drm_client_dev *client) · 18 unmodified lines
284err_drm_fb_helper_fini:284err_drm_fb_helper_fini:
285 drm_fb_helper_fini(fb_helper);285 drm_fb_helper_fini(fb_helper);
286err_drm_err:286err_drm_err:
287 drm_err(dev, "fbdev: Failed to setup generic emulation (ret=%d)\n", ret);287 drm_err(dev, "fbdev: Failed to setup emulation (ret=%d)\n", ret);
288 return ret;288 return ret;
289}289}
290 290
291static const struct drm_client_funcs drm_fbdev_generic_client_funcs = {291static const struct drm_client_funcs drm_fbdev_ttm_client_funcs = {
292 .owner = THIS_MODULE,292 .owner = THIS_MODULE,
293 .unregister = drm_fbdev_generic_client_unregister,293 .unregister = drm_fbdev_ttm_client_unregister,
294 .restore = drm_fbdev_generic_client_restore,294 .restore = drm_fbdev_ttm_client_restore,
295 .hotplug = drm_fbdev_generic_client_hotplug,295 .hotplug = drm_fbdev_ttm_client_hotplug,
296};296};
297 297
298/**298/**
299 * drm_fbdev_generic_setup() - Setup generic fbdev emulation299 * drm_fbdev_ttm_setup() - Setup fbdev emulation for TTM-based drivers
300 * @dev: DRM device300 * @dev: DRM device
301 * @preferred_bpp: Preferred bits per pixel for the device.301 * @preferred_bpp: Preferred bits per pixel for the device.
302 *302 *
303 * This function sets up generic fbdev emulation for drivers that supports303 * This function sets up fbdev emulation for TTM-based drivers that support
304 * dumb buffers with a virtual address and that can be mmap'ed.304 * dumb buffers with a virtual address and that can be mmap'ed.
305 * drm_fbdev_generic_setup() shall be called after the DRM driver registered305 * drm_fbdev_ttm_setup() shall be called after the DRM driver registered
306 * the new DRM device with drm_dev_register().306 * the new DRM device with drm_dev_register().
307 *307 *
308 * Restore, hotplug events and teardown are all taken care of. Drivers that do308 * Restore, hotplug events and teardown are all taken care of. Drivers that do
309 * suspend/resume need to call drm_fb_helper_set_suspend_unlocked() themselves.309 * suspend/resume need to call drm_fb_helper_set_suspend_unlocked() themselves.
310 * Simple drivers might use drm_mode_config_helper_suspend().310 * Simple drivers might use drm_mode_config_helper_suspend().
311 *311 *
312 * In order to provide fixed mmap-able memory ranges, generic fbdev emulation312 * In order to provide fixed mmap-able memory ranges, fbdev emulation
313 * uses a shadow buffer in system memory. The implementation blits the shadow313 * uses a shadow buffer in system memory. The implementation blits the shadow
314 * fbdev buffer onto the real buffer in regular intervals.314 * fbdev buffer onto the real buffer in regular intervals.
315 *315 *
@@ -318,7 +318,7 @@ static const struct drm_client_funcs drm_fbdev_generic_client_funcs = { · 2 unmodified lines
318 *318 *
319 * The fbdev is destroyed by drm_dev_unregister().319 * The fbdev is destroyed by drm_dev_unregister().
320 */320 */
321void drm_fbdev_generic_setup(struct drm_device *dev, unsigned int preferred_bpp)321void drm_fbdev_ttm_setup(struct drm_device *dev, unsigned int preferred_bpp)
322{322{
323 struct drm_fb_helper *fb_helper;323 struct drm_fb_helper *fb_helper;
324 int ret;324 int ret;
@@ -329,9 +329,9 @@ void drm_fbdev_generic_setup(struct drm_device *dev, unsigned int preferred_bpp) · 4 unmodified lines
329 fb_helper = kzalloc(sizeof(*fb_helper), GFP_KERNEL);329 fb_helper = kzalloc(sizeof(*fb_helper), GFP_KERNEL);
330 if (!fb_helper)330 if (!fb_helper)
331 return;331 return;
332 drm_fb_helper_prepare(dev, fb_helper, preferred_bpp, &drm_fbdev_generic_helper_funcs);332 drm_fb_helper_prepare(dev, fb_helper, preferred_bpp, &drm_fbdev_ttm_helper_funcs);
333 333
334 ret = drm_client_init(dev, &fb_helper->client, "fbdev", &drm_fbdev_generic_client_funcs);334 ret = drm_client_init(dev, &fb_helper->client, "fbdev", &drm_fbdev_ttm_client_funcs);
335 if (ret) {335 if (ret) {
336 drm_err(dev, "Failed to register client: %d\n", ret);336 drm_err(dev, "Failed to register client: %d\n", ret);
337 goto err_drm_client_init;337 goto err_drm_client_init;
@@ -346,4 +346,4 @@ err_drm_client_init: · 8 unmodified lines
346 kfree(fb_helper);346 kfree(fb_helper);
347 return;347 return;
348}348}
349EXPORT_SYMBOL(drm_fbdev_generic_setup);349EXPORT_SYMBOL(drm_fbdev_ttm_setup);
drivers/gpu/drm/drm_ioctl.c+3−2
@@ -529,9 +529,10 @@ int drm_version(struct drm_device *dev, void *data, · 528 unmodified lines
529 version->version_patchlevel = dev->driver->patchlevel;529 version->version_patchlevel = dev->driver->patchlevel;
530 err = drm_copy_field(version->name, &version->name_len,530 err = drm_copy_field(version->name, &version->name_len,
531 dev->driver->name);531 dev->driver->name);
532
533 /* Driver date is deprecated. Userspace expects a non-empty string. */
532 if (!err)534 if (!err)
533 err = drm_copy_field(version->date, &version->date_len,535 err = drm_copy_field(version->date, &version->date_len, "0");
534 dev->driver->date);
535 if (!err)536 if (!err)
536 err = drm_copy_field(version->desc, &version->desc_len,537 err = drm_copy_field(version->desc, &version->desc_len,
537 dev->driver->desc);538 dev->driver->desc);
drivers/gpu/drm/drm_mipi_dbi.c+54−23
@@ -206,6 +206,7 @@ int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer * · 205 unmodified lines
206 struct drm_rect *clip, bool swap,206 struct drm_rect *clip, bool swap,
207 struct drm_format_conv_state *fmtcnv_state)207 struct drm_format_conv_state *fmtcnv_state)
208{208{
209 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
209 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);210 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
210 struct iosys_map dst_map = IOSYS_MAP_INIT_VADDR(dst);211 struct iosys_map dst_map = IOSYS_MAP_INIT_VADDR(dst);
211 int ret;212 int ret;
@@ -222,8 +223,18 @@ int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer * · 10 unmodified lines
222 else223 else
223 drm_fb_memcpy(&dst_map, NULL, src, fb, clip);224 drm_fb_memcpy(&dst_map, NULL, src, fb, clip);
224 break;225 break;
226 case DRM_FORMAT_RGB888:
227 drm_fb_memcpy(&dst_map, NULL, src, fb, clip);
228 break;
225 case DRM_FORMAT_XRGB8888:229 case DRM_FORMAT_XRGB8888:
226 drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, src, fb, clip, fmtcnv_state, swap);230 switch (dbidev->pixel_format) {
231 case DRM_FORMAT_RGB565:
232 drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, src, fb, clip, fmtcnv_state, swap);
233 break;
234 case DRM_FORMAT_RGB888:
235 drm_fb_xrgb8888_to_rgb888(&dst_map, NULL, src, fb, clip, fmtcnv_state);
236 break;
237 }
227 break;238 break;
228 default:239 default:
229 drm_err_once(fb->dev, "Format is not supported: %p4cc\n",240 drm_err_once(fb->dev, "Format is not supported: %p4cc\n",
@@ -260,9 +271,11 @@ static void mipi_dbi_fb_dirty(struct iosys_map *src, struct drm_framebuffer *fb, · 30 unmodified lines
260 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);271 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
261 unsigned int height = rect->y2 - rect->y1;272 unsigned int height = rect->y2 - rect->y1;
262 unsigned int width = rect->x2 - rect->x1;273 unsigned int width = rect->x2 - rect->x1;
274 const struct drm_format_info *dst_format;
263 struct mipi_dbi *dbi = &dbidev->dbi;275 struct mipi_dbi *dbi = &dbidev->dbi;
264 bool swap = dbi->swap_bytes;276 bool swap = dbi->swap_bytes;
265 int ret = 0;277 int ret = 0;
278 size_t len;
266 bool full;279 bool full;
267 void *tr;280 void *tr;
268 281
@@ -283,8 +296,13 @@ static void mipi_dbi_fb_dirty(struct iosys_map *src, struct drm_framebuffer *fb, · 14 unmodified lines
283 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,296 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
284 rect->y2 - 1);297 rect->y2 - 1);
285 298
286 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,299 if (fb->format->format == DRM_FORMAT_XRGB8888)
287 width * height * 2);300 dst_format = drm_format_info(dbidev->pixel_format);
301 else
302 dst_format = fb->format;
303 len = drm_format_info_min_pitch(dst_format, 0, width) * height;
304
305 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, len);
288err_msg:306err_msg:
289 if (ret)307 if (ret)
290 drm_err_once(fb->dev, "Failed to update display %d\n", ret);308 drm_err_once(fb->dev, "Failed to update display %d\n", ret);
@@ -572,7 +590,7 @@ static const uint32_t mipi_dbi_formats[] = { · 281 unmodified lines
572 * has one fixed &drm_display_mode which is rotated according to @rotation.590 * has one fixed &drm_display_mode which is rotated according to @rotation.
573 * This mode is used to set the mode config min/max width/height properties.591 * This mode is used to set the mode config min/max width/height properties.
574 *592 *
575 * Use mipi_dbi_dev_init() if you don't need custom formats.593 * Use mipi_dbi_dev_init() if you want native RGB565 and emulated XRGB8888 format.
576 *594 *
577 * Note:595 * Note:
578 * Some of the helper functions expects RGB565 to be the default format and the596 * Some of the helper functions expects RGB565 to be the default format and the
@@ -631,6 +649,9 @@ int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev, · 52 unmodified lines
631 drm->mode_config.min_height = dbidev->mode.vdisplay;649 drm->mode_config.min_height = dbidev->mode.vdisplay;
632 drm->mode_config.max_height = dbidev->mode.vdisplay;650 drm->mode_config.max_height = dbidev->mode.vdisplay;
633 dbidev->rotation = rotation;651 dbidev->rotation = rotation;
652 dbidev->pixel_format = formats[0];
653 if (formats[0] == DRM_FORMAT_RGB888)
654 dbidev->dbi.write_memory_bpw = 8;
634 655
635 DRM_DEBUG_KMS("rotation = %u\n", rotation);656 DRM_DEBUG_KMS("rotation = %u\n", rotation);
636 657
@@ -824,15 +845,6 @@ u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len) · 187 unmodified lines
824}845}
825EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);846EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
826 847
827static bool mipi_dbi_machine_little_endian(void)
828{
829#if defined(__LITTLE_ENDIAN)
830 return true;
831#else
832 return false;
833#endif
834}
835
836/*848/*
837 * MIPI DBI Type C Option 1849 * MIPI DBI Type C Option 1
838 *850 *
@@ -855,7 +867,7 @@ static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc, · 16 unmodified lines
855 const void *buf, size_t len,867 const void *buf, size_t len,
856 unsigned int bpw)868 unsigned int bpw)
857{869{
858 bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian());870 bool swap_bytes = (bpw == 16);
859 size_t chunk, max_chunk = dbi->tx_buf9_len;871 size_t chunk, max_chunk = dbi->tx_buf9_len;
860 struct spi_device *spi = dbi->spi;872 struct spi_device *spi = dbi->spi;
861 struct spi_transfer tr = {873 struct spi_transfer tr = {
@@ -1004,7 +1016,7 @@ static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc, · 142 unmodified lines
1004 size_t chunk = min(len, max_chunk);1016 size_t chunk = min(len, max_chunk);
1005 unsigned int i;1017 unsigned int i;
1006 1018
1007 if (bpw == 16 && mipi_dbi_machine_little_endian()) {1019 if (bpw == 16) {
1008 for (i = 0; i < (chunk * 2); i += 2) {1020 for (i = 0; i < (chunk * 2); i += 2) {
1009 dst16[i] = *src16 >> 8;1021 dst16[i] = *src16 >> 8;
1010 dst16[i + 1] = *src16++ & 0xFF;1022 dst16[i + 1] = *src16++ & 0xFF;
@@ -1088,7 +1100,7 @@ static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd, · 77 unmodified lines
1088static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,1100static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
1089 u8 *parameters, size_t num)1101 u8 *parameters, size_t num)
1090{1102{
1091 unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;1103 unsigned int bpw = 8;
1092 int ret;1104 int ret;
1093 1105
1094 if (mipi_dbi_command_is_read(dbi, *cmd))1106 if (mipi_dbi_command_is_read(dbi, *cmd))
@@ -1100,6 +1112,9 @@ static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, · 5 unmodified lines
1100 if (ret || !num)1112 if (ret || !num)
1101 return ret;1113 return ret;
1102 1114
1115 if (*cmd == MIPI_DCS_WRITE_MEMORY_START)
1116 bpw = dbi->write_memory_bpw;
1117
1103 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);1118 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
1104}1119}
1105 1120
@@ -1193,8 +1208,8 @@ static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, · 87 unmodified lines
1193 if (ret || !num)1208 if (ret || !num)
1194 return ret;1209 return ret;
1195 1210
1196 if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)1211 if (*cmd == MIPI_DCS_WRITE_MEMORY_START)
1197 bpw = 16;1212 bpw = dbi->write_memory_bpw;
1198 1213
1199 spi_bus_lock(spi->controller);1214 spi_bus_lock(spi->controller);
1200 gpiod_set_value_cansleep(dbi->dc, 1);1215 gpiod_set_value_cansleep(dbi->dc, 1);
@@ -1218,11 +1233,23 @@ static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, · 17 unmodified lines
1218 * If @dc is set, a Type C Option 3 interface is assumed, if not1233 * If @dc is set, a Type C Option 3 interface is assumed, if not
1219 * Type C Option 1.1234 * Type C Option 1.
1220 *1235 *
1221 * If the SPI master driver doesn't support the necessary bits per word,1236 * If the command is %MIPI_DCS_WRITE_MEMORY_START and the pixel format is RGB565, endianness has
1222 * the following transformation is used:1237 * to be taken into account. The MIPI DBI serial interface is big endian and framebuffers are
1238 * assumed stored in memory as little endian (%DRM_FORMAT_BIG_ENDIAN is not supported).
1223 *1239 *
1224 * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command.1240 * This is how endianness is handled:
1225 * - 16-bit: if big endian send as 8-bit, if little endian swap bytes1241 *
1242 * Option 1 (D/C as a bit): The buffer is sent on the wire byte by byte so the 16-bit buffer is
1243 * byteswapped before transfer.
1244 *
1245 * Option 3 (D/C as a gpio): If the SPI controller supports 16 bits per word the buffer can be
1246 * sent as-is. If not the caller is responsible for swapping the bytes
1247 * before calling mipi_dbi_command_buf() and the buffer is sent 8 bpw.
1248 *
1249 * This handling is optimised for %DRM_FORMAT_RGB565 framebuffers.
1250 *
1251 * If the interface is Option 1 and the SPI controller doesn't support 9 bits per word,
1252 * the buffer is sent as 9x 8-bit words, padded with MIPI DCS no-op commands if necessary.
1226 *1253 *
1227 * Returns:1254 * Returns:

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drivers/gpu/drm/i915/display/icl_dsi.c+29−17

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drivers/gpu/drm/i915/display/intel_vblank.c+82−87

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drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c+2−2

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drivers/gpu/drm/i915/gvt/dmabuf.c+2−1

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include/drm/intel/i915_component.hrenamed from include/drm/i915_component.h+0−0

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include/drm/intel/i915_gsc_proxy_mei_interface.hrenamed from include/drm/i915_gsc_proxy_mei_interface.h+0−0

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include/drm/intel/i915_hdcp_interface.hrenamed from include/drm/i915_hdcp_interface.h+0−0

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include/drm/intel/i915_pxp_tee_interface.hrenamed from include/drm/i915_pxp_tee_interface.h+0−0

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include/drm/intel/intel_lpe_audio.hrenamed from include/drm/intel_lpe_audio.h+0−0

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include/drm/intel/xe_pciids.hrenamed from include/drm/xe_pciids.h+0−0

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