Gen12 display can decompress surfaces compressed by render engine with Clear Color, add a new modifier as the driver needs to know the surface was compressed by render engine. V2: Description changes as suggested by Rafael. V3: Mention the Clear Color size of 64 bits in the comments(DK) v4: Fix trailing whitespaces v5: Explain Clear Color in the documentation. v6: Documentation Nitpicks(Nanley)
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| @@ -527,6 +527,25 @@ extern "C" { · 526 unmodified lines | ||
| 527 | 527 | */ |
| 528 | 528 | #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) |
| 529 | 529 | |
| 530 | +/* | |
| 531 | + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render | |
| 532 | + * compression. | |
| 533 | + * | |
| 534 | + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear | |
| 535 | + * and at index 1. The clear color is stored at index 2, and the pitch should | |
| 536 | + * be ignored. The clear color structure is 256 bits. The first 128 bits | |
| 537 | + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented | |
| 538 | + * by 32 bits. The raw clear color is consumed by the 3d engine and generates | |
| 539 | + * the converted clear color of size 64 bits. The first 32 bits store the Lower | |
| 540 | + * Converted Clear Color value and the next 32 bits store the Higher Converted | |
| 541 | + * Clear Color value when applicable. The Converted Clear Color values are | |
| 542 | + * consumed by the DE. The last 64 bits are used to store Color Discard Enable | |
| 543 | + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line | |
| 544 | + * corresponds to an area of 4x1 tiles in the main surface. The main surface | |
| 545 | + * pitch is required to be a multiple of 4 tile widths. | |
| 546 | + */ | |
| 547 | +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) | |
| 548 | + | |
| 530 | 549 | /* |
| 531 | 550 | * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks |
| 532 | 551 | * |