+ preemption support for a5xx[1][2] + display fixes for 8x96 (snapdragon 820) including fixes for 4k scanout (hwpipe assignment re-work to handle multiple hwpipe assigned to plane for wide scanout) + async cursor plane updates and fixes + refactor adreno_bind/hwinit.. still defer fw loading until device open, but move clk/irq/etc to probe/bind time to fix issues when fw isn't present in filesys + clk/dt bindings cleanups w/ backward compat via msm_clk_get() (dt docs part ack'ed by Rob Herring) + fw loading re-work with helper to handle either /lib/firmware/qcom/$fw or /lib/firmware/$fw.. background, we've started landing fw for some of generations in linux-firmware, but there is a preference to put fw files under 'qcom' subdirectory, which is not what was done on android or for people who copied fw from android. So now we first look in qcom subdir and then fallback to the original location. + bunch of GPU debugging enhancements, to dump full cmdline of processes that trigger faults, and to add a new debugfs to capture cmdstream of just submits that triggered faults.. both quite useful for piglit ;-) * tag 'drm-msm-next-2017-11-01' of git://people.freedesktop.org/~robclark/linux: (38 commits) drm/msm: use %z format modifier for printing size_t drm/msm/mdp5: Don't use async plane update path if plane visibility changes drm/msm/mdp5: mdp5_crtc: Restore cursor state only if LM cursors are enabled drm/msm/mdp5: Update mdp5_pipe_assign to spit out both planes drm/msm/mdp5: Prepare mdp5_pipe_assign for some rework drm/msm: remove mdp5_cursor_plane_funcs drm/msm: update cursors asynchronously through atomic drm/msm/atomic: switch to drm_atomic_helper_check drm/msm/mdp5: restore cursor state when enabling crtc drm/msm/mdp5: don't use autosuspend drm/msm/mdp5: ignore planes that are not visible drm/msm: dump submits which triggered gpu hang drm/msm: preserve IOVAs in submit's bo table drm/msm/rd: allow adding addition msg to top of dump drm/msm: split rd debugfs file drm/msm: add special _get_vaddr_active() for cmdstream dumps drm/msm: show task cmdline in gpu recovery messages drm/msm: dump a rd GPUADDR header for all buffers in the command drm/msm: Removed unused struct_mutex_task drm/msm: Implement preemption for A5XX targets ...
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| @@ -73,6 +73,7 @@ struct drm_msm_timespec { · 72 unmodified lines | |||
| 73 | #define MSM_PARAM_MAX_FREQ 0x04 | 73 | #define MSM_PARAM_MAX_FREQ 0x04 |
| 74 | #define MSM_PARAM_TIMESTAMP 0x05 | 74 | #define MSM_PARAM_TIMESTAMP 0x05 |
| 75 | #define MSM_PARAM_GMEM_BASE 0x06 | 75 | #define MSM_PARAM_GMEM_BASE 0x06 |
| 76 | #define MSM_PARAM_NR_RINGS 0x07 | ||
| 76 | 77 | ||
| 77 | struct drm_msm_param { | 78 | struct drm_msm_param { |
| 78 | __u32 pipe; /* in, MSM_PIPE_x */ | 79 | __u32 pipe; /* in, MSM_PIPE_x */ |
| @@ -218,6 +219,7 @@ struct drm_msm_gem_submit { · 139 unmodified lines | |||
| 218 | __u64 bos; /* in, ptr to array of submit_bo's */ | 219 | __u64 bos; /* in, ptr to array of submit_bo's */ |
| 219 | __u64 cmds; /* in, ptr to array of submit_cmd's */ | 220 | __u64 cmds; /* in, ptr to array of submit_cmd's */ |
| 220 | __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ | 221 | __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ |
| 222 | __u32 queueid; /* in, submitqueue id */ | ||
| 221 | }; | 223 | }; |
| 222 | 224 | ||
| 223 | /* The normal way to synchronize with the GPU is just to CPU_PREP on | 225 | /* The normal way to synchronize with the GPU is just to CPU_PREP on |
| @@ -231,6 +233,7 @@ struct drm_msm_wait_fence { · 7 unmodified lines | |||
| 231 | __u32 fence; /* in */ | 233 | __u32 fence; /* in */ |
| 232 | __u32 pad; | 234 | __u32 pad; |
| 233 | struct drm_msm_timespec timeout; /* in */ | 235 | struct drm_msm_timespec timeout; /* in */ |
| 236 | __u32 queueid; /* in, submitqueue id */ | ||
| 234 | }; | 237 | }; |
| 235 | 238 | ||
| 236 | /* madvise provides a way to tell the kernel in case a buffers contents | 239 | /* madvise provides a way to tell the kernel in case a buffers contents |
| @@ -254,6 +257,20 @@ struct drm_msm_gem_madvise { · 17 unmodified lines | |||
| 254 | __u32 retained; /* out, whether backing store still exists */ | 257 | __u32 retained; /* out, whether backing store still exists */ |
| 255 | }; | 258 | }; |
| 256 | 259 | ||
| 260 | /* | ||
| 261 | * Draw queues allow the user to set specific submission parameter. Command | ||
| 262 | * submissions specify a specific submitqueue to use. ID 0 is reserved for | ||
| 263 | * backwards compatibility as a "default" submitqueue | ||
| 264 | */ | ||
| 265 | |||
| 266 | #define MSM_SUBMITQUEUE_FLAGS (0) | ||
| 267 | |||
| 268 | struct drm_msm_submitqueue { | ||
| 269 | __u32 flags; /* in, MSM_SUBMITQUEUE_x */ | ||
| 270 | __u32 prio; /* in, Priority level */ | ||
| 271 | __u32 id; /* out, identifier */ | ||
| 272 | }; | ||
| 273 | |||
| 257 | #define DRM_MSM_GET_PARAM 0x00 | 274 | #define DRM_MSM_GET_PARAM 0x00 |
| 258 | /* placeholder: | 275 | /* placeholder: |
| 259 | #define DRM_MSM_SET_PARAM 0x01 | 276 | #define DRM_MSM_SET_PARAM 0x01 |
| @@ -265,6 +282,11 @@ struct drm_msm_gem_madvise { · 5 unmodified lines | |||
| 265 | #define DRM_MSM_GEM_SUBMIT 0x06 | 282 | #define DRM_MSM_GEM_SUBMIT 0x06 |
| 266 | #define DRM_MSM_WAIT_FENCE 0x07 | 283 | #define DRM_MSM_WAIT_FENCE 0x07 |
| 267 | #define DRM_MSM_GEM_MADVISE 0x08 | 284 | #define DRM_MSM_GEM_MADVISE 0x08 |
| 285 | /* placeholder: | ||
| 286 | #define DRM_MSM_GEM_SVM_NEW 0x09 | ||
| 287 | */ | ||
| 288 | #define DRM_MSM_SUBMITQUEUE_NEW 0x0A | ||
| 289 | #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B | ||
| 268 | 290 | ||
| 269 | #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) | 291 | #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) |
| 270 | #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) | 292 | #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) |
| @@ -274,6 +296,8 @@ struct drm_msm_gem_madvise { · 3 unmodified lines | |||
| 274 | #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) | 296 | #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) |
| 275 | #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) | 297 | #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) |
| 276 | #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) | 298 | #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) |
| 299 | #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) | ||
| 300 | #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) | ||
| 277 | 301 | ||
| 278 | #if defined(__cplusplus) | 302 | #if defined(__cplusplus) |
| 279 | } | 303 | } |