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clk: ti: Drop legacy compatibility clocks for am3

We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using.

Tony Lindgren committed 4 years ago

Commit 8850c3e1 parent 99105cc5 files · +4 −323Browse files

Unified · Split

5 files
  1. drivers/clk/ti/Makefile +1 −2
  2. drivers/clk/ti/clk-33xx-compat.c +0 −218
  3. drivers/clk/ti/clk-33xx.c +1 −4
  4. drivers/clk/ti/clkctrl.c +2 −6
  5. include/dt-bindings/clock/am3.h +0 −93
drivers/clk/ti/Makefile+1−2
@@ -6,8 +6,7 @@ clk-common = dpll.o composite.o divider.o gate.o \ · 5 unmodified lines
6 fixed-factor.o mux.o apll.o \6 fixed-factor.o mux.o apll.o \
7 clkt_dpll.o clkt_iclk.o clkt_dflt.o \7 clkt_dpll.o clkt_iclk.o clkt_dflt.o \
8 clkctrl.o8 clkctrl.o
9obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o \9obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o
10 clk-33xx-compat.o
11obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o10obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
12obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o11obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
13obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \12obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
drivers/clk/ti/clk-33xx-compat.c+0−218
@@ -1,218 +0,0 @@
1/*
2 * AM33XX Clock init
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk.h>
20#include <linux/clk-provider.h>
21#include <linux/clk/ti.h>
22#include <dt-bindings/clock/am3.h>
23
24#include "clock.h"
25
26static const char * const am3_gpio1_dbclk_parents[] __initconst = {
27 "l4_per_cm:clk:0138:0",
28 NULL,
29};
30
31static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
32 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
33 { 0 },
34};
35
36static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
37 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
38 { 0 },
39};
40
41static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
42 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
43 { 0 },
44};
45
46static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
47 { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
48 { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
49 { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
50 { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
51 { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
52 { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
53 { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
54 { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
55 { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
56 { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
57 { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
58 { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
59 { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
60 { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
61 { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
62 { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
63 { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
64 { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
65 { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
66 { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
67 { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
68 { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
69 { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
70 { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
71 { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
72 { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
73 { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
74 { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
75 { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
76 { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
77 { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
78 { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
79 { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
80 { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
81 { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
82 { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
83 { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
84 { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
85 { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
86 { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
87 { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
88 { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
89 { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
90 { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
91 { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
92 { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
93 { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
94 { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
95 { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
96 { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
97 { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
98 { 0 },
99};
100
101static const char * const am3_gpio0_dbclk_parents[] __initconst = {
102 "gpio0_dbclk_mux_ck",
103 NULL,
104};
105
106static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
107 { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
108 { 0 },
109};
110
111static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
112 "sys_clkin_ck",
113 NULL,
114};
115
116static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
117 "l4_wkup_cm:clk:0010:19",
118 "l4_wkup_cm:clk:0010:30",
119 NULL,
120};
121
122static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
123 "l4_wkup_cm:clk:0010:20",
124 NULL,
125};
126
127static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
128 .max_div = 64,
129 .flags = CLK_DIVIDER_POWER_OF_TWO,
130};
131
132static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
133 "l4_wkup_cm:clk:0010:22",
134 NULL,
135};
136
137static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
138 .max_div = 64,
139 .flags = CLK_DIVIDER_POWER_OF_TWO,
140};
141
142static const char * const am3_dbg_clka_ck_parents[] __initconst = {
143 "dpll_core_m4_ck",
144 NULL,
145};
146
147static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
148 { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
149 { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
150 { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
151 { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
152 { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
153 { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
154 { 0 },
155};
156
157static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
158 { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
159 { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
160 { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
161 { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
162 { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
163 { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
164 { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
165 { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
166 { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
167 { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
168 { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
169 { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
170 { 0 },
171};
172
173static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
174 { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
175 { 0 },
176};
177
178static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
179 { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
180 { 0 },
181};
182
183static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
184 { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
185 { 0 },
186};
187
188static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
189 { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
190 { 0 },
191};
192
193const struct omap_clkctrl_data am3_clkctrl_compat_data[] __initconst = {
194 { 0x44e00014, am3_l4_per_clkctrl_regs },
195 { 0x44e00404, am3_l4_wkup_clkctrl_regs },
196 { 0x44e00604, am3_mpu_clkctrl_regs },
197 { 0x44e00800, am3_l4_rtc_clkctrl_regs },
198 { 0x44e00904, am3_gfx_l3_clkctrl_regs },
199 { 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
200 { 0 },
201};
202
203struct ti_dt_clk am33xx_compat_clks[] = {
204 DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
205 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
206 DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
207 DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
208 DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
209 DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
210 DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
211 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
212 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
213 DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
214 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
215 DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
216 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
217 { .node_name = NULL },
218};
drivers/clk/ti/clk-33xx.c+1−4
@@ -279,10 +279,7 @@ int __init am33xx_dt_clk_init(void) · 278 unmodified lines
279{279{
280 struct clk *clk1, *clk2;280 struct clk *clk1, *clk2;
281 281
282 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)282 ti_dt_clocks_register(am33xx_clks);
283 ti_dt_clocks_register(am33xx_compat_clks);
284 else
285 ti_dt_clocks_register(am33xx_clks);
286 283
287 omap2_clk_disable_autoidle_all();284 omap2_clk_disable_autoidle_all();
288 285
drivers/clk/ti/clkctrl.c+2−6
@@ -560,12 +560,8 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) · 559 unmodified lines
560 soc_mask = CLKF_SOC_DRA76;560 soc_mask = CLKF_SOC_DRA76;
561#endif561#endif
562#ifdef CONFIG_SOC_AM33XX562#ifdef CONFIG_SOC_AM33XX
563 if (of_machine_is_compatible("ti,am33xx")) {563 if (of_machine_is_compatible("ti,am33xx"))
564 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)564 data = am3_clkctrl_data;
565 data = am3_clkctrl_compat_data;
566 else
567 data = am3_clkctrl_data;
568 }
569#endif565#endif
570#ifdef CONFIG_SOC_AM43XX566#ifdef CONFIG_SOC_AM43XX
571 if (of_machine_is_compatible("ti,am4372")) {567 if (of_machine_is_compatible("ti,am4372")) {
include/dt-bindings/clock/am3.h+0−93
@@ -8,99 +8,6 @@ · 7 unmodified lines
8#define AM3_CLKCTRL_OFFSET 0x08#define AM3_CLKCTRL_OFFSET 0x0
9#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)9#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
10 10
11/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
12
13/* l4_per clocks */
14#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
15#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
16#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
17#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
18#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
19#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
20#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
21#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
22#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
23#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
24#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38)
25#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c)
26#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40)
27#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44)
28#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48)
29#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c)
30#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50)
31#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60)
32#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68)
33#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c)
34#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70)
35#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74)
36#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78)
37#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c)
38#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80)
39#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84)
40#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88)
41#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90)
42#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94)
43#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0)
44#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac)
45#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0)
46#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4)
47#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc)
48#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0)
49#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4)
50#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc)
51#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4)
52#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8)
53#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc)
54#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0)
55#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8)
56#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec)
57#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0)
58#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4)
59#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8)
60#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc)
61#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100)
62#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c)
63#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110)
64#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120)
65#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130)
66#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c)
67
68/* l4_wkup clocks */
69#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4
70#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
71#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
72#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
73#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
74#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
75#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
76#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
77#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
78#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
79#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
80#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
81#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
82#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
83
84/* mpu clocks */
85#define AM3_MPU_CLKCTRL_OFFSET 0x4
86#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET)
87#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4)
88
89/* l4_rtc clocks */
90#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
91
92/* gfx_l3 clocks */
93#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4
94#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
95#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4)
96
97/* l4_cefuse clocks */
98#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20
99#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
100#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
101
102/* XXX: Compatibility part end */
103
104/* l4ls clocks */11/* l4ls clocks */
105#define AM3_L4LS_CLKCTRL_OFFSET 0x3812#define AM3_L4LS_CLKCTRL_OFFSET 0x38
106#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)13#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)

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