We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using.
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| @@ -8,99 +8,6 @@ · 7 unmodified lines | ||
| 8 | 8 | #define AM3_CLKCTRL_OFFSET 0x0 |
| 9 | 9 | #define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) |
| 10 | 10 | |
| 11 | −/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ | |
| 12 | − | |
| 13 | −/* l4_per clocks */ | |
| 14 | −#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 | |
| 15 | −#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) | |
| 16 | −#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) | |
| 17 | −#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) | |
| 18 | −#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) | |
| 19 | −#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) | |
| 20 | −#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) | |
| 21 | −#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) | |
| 22 | −#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) | |
| 23 | −#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) | |
| 24 | −#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) | |
| 25 | −#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) | |
| 26 | −#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) | |
| 27 | −#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) | |
| 28 | −#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) | |
| 29 | −#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) | |
| 30 | −#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) | |
| 31 | −#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) | |
| 32 | −#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) | |
| 33 | −#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) | |
| 34 | −#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) | |
| 35 | −#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) | |
| 36 | −#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) | |
| 37 | −#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) | |
| 38 | −#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) | |
| 39 | −#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) | |
| 40 | −#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) | |
| 41 | −#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) | |
| 42 | −#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) | |
| 43 | −#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) | |
| 44 | −#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) | |
| 45 | −#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) | |
| 46 | −#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) | |
| 47 | −#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) | |
| 48 | −#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) | |
| 49 | −#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) | |
| 50 | −#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) | |
| 51 | −#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) | |
| 52 | −#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) | |
| 53 | −#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) | |
| 54 | −#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) | |
| 55 | −#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) | |
| 56 | −#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) | |
| 57 | −#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) | |
| 58 | −#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) | |
| 59 | −#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) | |
| 60 | −#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) | |
| 61 | −#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) | |
| 62 | −#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) | |
| 63 | −#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) | |
| 64 | −#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) | |
| 65 | −#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) | |
| 66 | −#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) | |
| 67 | − | |
| 68 | −/* l4_wkup clocks */ | |
| 69 | −#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 | |
| 70 | −#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) | |
| 71 | −#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) | |
| 72 | −#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) | |
| 73 | −#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) | |
| 74 | −#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) | |
| 75 | −#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) | |
| 76 | −#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) | |
| 77 | −#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) | |
| 78 | −#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) | |
| 79 | −#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) | |
| 80 | −#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) | |
| 81 | −#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) | |
| 82 | −#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) | |
| 83 | − | |
| 84 | −/* mpu clocks */ | |
| 85 | −#define AM3_MPU_CLKCTRL_OFFSET 0x4 | |
| 86 | −#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) | |
| 87 | −#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) | |
| 88 | − | |
| 89 | −/* l4_rtc clocks */ | |
| 90 | −#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) | |
| 91 | − | |
| 92 | −/* gfx_l3 clocks */ | |
| 93 | −#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 | |
| 94 | −#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) | |
| 95 | −#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) | |
| 96 | − | |
| 97 | −/* l4_cefuse clocks */ | |
| 98 | −#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 | |
| 99 | −#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) | |
| 100 | −#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) | |
| 101 | − | |
| 102 | −/* XXX: Compatibility part end */ | |
| 103 | − | |
| 104 | 11 | /* l4ls clocks */ |
| 105 | 12 | #define AM3_L4LS_CLKCTRL_OFFSET 0x38 |
| 106 | 13 | #define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) |