Merge tag 'mips_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips

Pull MIPS updates from James Hogan: "These are the main MIPS changes for 4.15. Fixes: - ralink: Fix MT7620 PCI build issues (4.5) - Disable cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN for 32-bit SMP (4.1) - Fix MIPS64 FP save/restore on 32-bit kernels (4.0) - ptrace: Pick up ptrace/seccomp changed syscall numbers (3.19) - ralink: Fix MT7628 pinmux (3.19) - BCM47XX: Fix LED inversion on WRT54GSv1 (3.17) - Fix n32 core dumping as o32 since regset support (3.13) - ralink: Drop obsolete USB_ARCH_HAS_HCD select Build system: - Default to "generic" (multiplatform) system type instead of IP22 - Use generic little endian MIPS32 r2 configuration as default defconfig instead of ip22_defconfig FPU emulation: - Fix exception generation for certain R6 FPU instructions SMP: - Allow __cpu_number_map to be larger than NR_CPUS for sparse CPU id spaces Miscellaneous: - Add iomem resource for kernel bss section for kexec/kdump - Atomics: Nudge writes on bit unlock - DT files: Standardise "ok" -> "okay" Minor cleanups: - Define virt_to_pfn() - Make thread_saved_pc static - Simplify 32-bit sign extension in __read_64bit_c0_split() - DMA: Use vma_pages() helper - FPU emulation: Replace unsigned with unsigned int - MM: Removed unused lastpfn - Alchemy: Make clk_ops const - Lasat: Use setup_timer() helper - ralink: Use BIT() in MT7620 PCI driver Platform support: BMIPS: - Enable HARDIRQS_SW_RESEND Broadcom BCM63XX: - Add clkdev lookup support - Update clk driver, UART driver, DTs to handle named refclk from DTs - Split apart various clocks to more closely match hardware - Add ethernet clocks Cavium Octeon: - Remove usage of cvmx_wait() in favour of __delay() ImgTec Pistachio: - DT: Drop deprecated dwmmc num-slots property Ingenic JZ4780: - Add NFS root to Ci20 defconfig - Add watchdog to Ci20 DT & defconfig, and allow building of watchdog driver with this SoC Generic (multiplatform): - Migrate xilfpga (MIPSfpga) platform to the generic platform Lantiq xway: - Fix ASC0/ASC1 clocks" * tag 'mips_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (46 commits) MIPS: Add iomem resource for kernel bss section. MIPS: cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN don't work for 32-bit SMP MIPS: BMIPS: Enable HARDIRQS_SW_RESEND MIPS: pci: Make use of the BIT() macro inside the mt7620 driver MIPS: pci: Remove KERN_WARN instance inside the mt7620 driver MIPS: pci: Remove duplicate define in mt7620 driver MIPS: ralink: Fix typo in mt7628 pinmux function MIPS: ralink: Fix MT7628 pinmux MIPS: Fix odd fp register warnings with MIPS64r2 watchdog: jz4780: Allow selection of jz4740-wdt driver MIPS/ptrace: Update syscall nr on register changes MIPS/ptrace: Pick up ptrace/seccomp changed syscalls MIPS: Fix an n32 core file generation regset support regression MIPS: Fix MIPS64 FP save/restore on 32-bit kernels MIPS: page.h: Define virt_to_pfn() MIPS: Xilfpga: Switch to using generic defconfigs MIPS: generic: Add support for MIPSfpga MIPS: Set defconfig target to a generic system for 32r2el MIPS: Kconfig: Set default MIPS system type as generic MIPS: DTS: Remove num-slots from Pistachio SoC ...

Linus Torvalds committed 8 years ago

Commit 892204e2 parents c9b012e e0c5f3672 files · +514 −436Browse files

Unified · Split

72 files

Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt +6 −0
arch/mips/Kbuild.platforms +0 −1
arch/mips/Kconfig +15 −27
arch/mips/Makefile +5 −1
arch/mips/alchemy/common/clock.c +5 −5
arch/mips/bcm47xx/leds.c +1 −1
arch/mips/bcm63xx/clk.c +195 −47
arch/mips/boot/dts/brcm/bcm3368.dtsi +2 −0
arch/mips/boot/dts/brcm/bcm63268-comtrend-vr-3032u.dts +1 −1
arch/mips/boot/dts/brcm/bcm63268.dtsi +2 −0
arch/mips/boot/dts/brcm/bcm6328.dtsi +2 −0
arch/mips/boot/dts/brcm/bcm6358-neufbox4-sercomm.dts +1 −1
arch/mips/boot/dts/brcm/bcm6358.dtsi +2 −0
arch/mips/boot/dts/brcm/bcm6362.dtsi +2 −0
arch/mips/boot/dts/brcm/bcm6368.dtsi +2 −0
arch/mips/boot/dts/img/pistachio.dtsi +0 −1
arch/mips/boot/dts/ingenic/jz4780.dtsi +5 −0
arch/mips/boot/dts/ralink/rt3052_eval.dts +1 −1
arch/mips/boot/dts/xilfpga/Makefile +1 −1
arch/mips/boot/dts/xilfpga/nexys4ddr.dts +8 −0
arch/mips/cavium-octeon/executive/cvmx-helper.c +1 −1
arch/mips/cavium-octeon/executive/cvmx-spi.c +5 −5
arch/mips/configs/ci20_defconfig +6 −1
arch/mips/configs/generic/board-xilfpga.config +22 −0
arch/mips/configs/ip22_defconfig +1 −0
arch/mips/configs/xilfpga_defconfig +0 −75
arch/mips/generic/Kconfig +6 −0
arch/mips/generic/board-xilfpga.its.S +22 −0
arch/mips/include/asm/asmmacro.h +9 −7
arch/mips/include/asm/bitops.h +1 −0
arch/mips/include/asm/cmpxchg.h +2 −0
arch/mips/include/asm/mipsregs.h +6 −8
arch/mips/include/asm/octeon/cvmx-fpa.h +3 −1
arch/mips/include/asm/octeon/cvmx.h +2 −13
arch/mips/include/asm/page.h +2 −2
arch/mips/include/asm/processor.h +0 −2
arch/mips/include/asm/smp.h +1 −1
arch/mips/include/asm/syscall.h +25 −4
arch/mips/kernel/process.c +1 −1
arch/mips/kernel/ptrace.c +38 −3
arch/mips/kernel/ptrace32.c +7 −0
arch/mips/kernel/r4k_fpu.S +10 −10
arch/mips/kernel/setup.c +4 −0
arch/mips/kernel/smp.c +1 −1
arch/mips/lantiq/xway/sysctrl.c +2 −4
arch/mips/lasat/picvue_proc.c +1 −2
arch/mips/math-emu/cp1emu.c +24 −22
arch/mips/math-emu/dp_maddf.c +4 −4
arch/mips/math-emu/dp_mul.c +4 −4
arch/mips/math-emu/dp_sqrt.c +2 −2
arch/mips/math-emu/ieee754.h +8 −7
arch/mips/math-emu/ieee754int.h +3 −3
arch/mips/math-emu/ieee754sp.c +2 −2
arch/mips/math-emu/ieee754sp.h +1 −1
arch/mips/math-emu/sp_div.c +2 −2
arch/mips/math-emu/sp_fint.c +1 −1
arch/mips/math-emu/sp_maddf.c +3 −3
arch/mips/math-emu/sp_mul.c +5 −5
arch/mips/mm/dma-default.c +1 −1
arch/mips/mm/init.c +0 −4
arch/mips/pci/pci-mt7620.c +7 −8
arch/mips/pci/pcie-octeon.c +6 −6
arch/mips/ralink/Kconfig +0 −1
arch/mips/ralink/mt7620.c +2 −2
arch/mips/xilfpga/Kconfig +0 −10
arch/mips/xilfpga/Makefile +0 −7
arch/mips/xilfpga/Platform +0 −3
arch/mips/xilfpga/init.c +0 −44
arch/mips/xilfpga/intc.c +0 −22
arch/mips/xilfpga/time.c +0 −41
drivers/tty/serial/bcm63xx_uart.c +4 −2
drivers/watchdog/Kconfig +1 −1

Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt+6−0

@@ -11,6 +11,11 @@ Required properties: · 10 unmodified lines
11	11	- clocks: Clock driving the hardware; used to figure out the baud rate
12	12	divisor.
13	13
	14	+
	15	+Optional properties:
	16	+
	17	+- clock-names: Should be "refclk".
	18	+
14	19	Example:
15	20
16	21	uart0: serial@14e00520 {
@@ -19,6 +24,7 @@ Example: · 2 unmodified lines
19	24	interrupt-parent = <&periph_intc>;
20	25	interrupts = <2>;
21	26	clocks = <&periph_clk>;
	27	+ clock-names = "refclk";
22	28	};
23	29
24	30	clocks {

arch/mips/Kbuild.platforms+0−1

@@ -34,7 +34,6 @@ platforms += sibyte · 33 unmodified lines
34	34	platforms += sni
35	35	platforms += txx9
36	36	platforms += vr41xx
37		−platforms += xilfpga
38	37
39	38	# include the platform specific files
40	39	include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))

arch/mips/Kconfig+15−27

@@ -65,7 +65,7 @@ config MIPS · 64 unmodified lines
65	65	select HAVE_PERF_EVENTS
66	66	select HAVE_REGS_AND_STACK_ACCESS_API
67	67	select HAVE_SYSCALL_TRACEPOINTS
68		− select HAVE_VIRT_CPU_ACCOUNTING_GEN
	68	+ select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT \|\| !SMP
69	69	select IRQ_FORCED_THREADING
70	70	select MODULES_USE_ELF_RELA if MODULES && 64BIT
71	71	select MODULES_USE_ELF_REL if MODULES
@@ -78,7 +78,7 @@ menu "Machine selection" · 6 unmodified lines
78	78
79	79	choice
80	80	prompt "System type"
81		− default SGI_IP22
	81	+ default MIPS_GENERIC
82	82
83	83	config MIPS_GENERIC
84	84	bool "Generic board-agnostic MIPS kernel"
@@ -233,6 +233,7 @@ config BMIPS_GENERIC · 148 unmodified lines
233	233	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
234	234	select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
235	235	select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
	236	+ select HARDIRQS_SW_RESEND
236	237	help
237	238	Build a generic DT-based kernel image that boots on select
238	239	BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
@@ -276,6 +277,7 @@ config BCM63XX · 37 unmodified lines
276	277	select GPIOLIB
277	278	select HAVE_CLK
278	279	select MIPS_L1_CACHE_SHIFT_4
	280	+ select CLKDEV_LOOKUP
279	281	help
280	282	Support for BCM63XX based boards
281	283
@@ -468,29 +470,6 @@ config MACH_PISTACHIO · 186 unmodified lines
468	470	help
469	471	This enables support for the IMG Pistachio SoC platform.
470	472
471		−config MACH_XILFPGA
472		− bool "MIPSfpga Xilinx based boards"
473		− select BOOT_ELF32
474		− select BOOT_RAW
475		− select BUILTIN_DTB
476		− select CEVT_R4K
477		− select COMMON_CLK
478		− select CSRC_R4K
479		− select GPIOLIB
480		− select IRQ_MIPS_CPU
481		− select LIBFDT
482		− select MIPS_CPU_SCACHE
483		− select SYS_HAS_EARLY_PRINTK
484		− select SYS_HAS_CPU_MIPS32_R2
485		− select SYS_SUPPORTS_32BIT_KERNEL
486		− select SYS_SUPPORTS_LITTLE_ENDIAN
487		− select SYS_SUPPORTS_ZBOOT_UART16550
488		− select USE_OF
489		− select USE_GENERIC_EARLY_PRINTK_8250
490		− select XILINX_INTC
491		− help
492		− This enables support for the IMG University Program MIPSfpga platform.
493		−
494	473	config MIPS_MALTA
495	474	bool "MIPS Malta board"
496	475	select ARCH_MAY_HAVE_PC_FDC
@@ -916,7 +895,8 @@ config CAVIUM_OCTEON_SOC · 419 unmodified lines
916	895	select USE_OF
917	896	select ARCH_SPARSEMEM_ENABLE
918	897	select SYS_SUPPORTS_SMP
919		− select NR_CPUS_DEFAULT_16
	898	+ select NR_CPUS_DEFAULT_64
	899	+ select MIPS_NR_CPU_NR_MAP_1024
920	900	select BUILTIN_DTB
921	901	select MTD_COMPLEX_MAPPINGS
922	902	select SYS_SUPPORTS_RELOCATABLE
@@ -1034,7 +1014,6 @@ source "arch/mips/loongson32/Kconfig" · 111 unmodified lines
1034	1014	source "arch/mips/loongson64/Kconfig"
1035	1015	source "arch/mips/netlogic/Kconfig"
1036	1016	source "arch/mips/paravirt/Kconfig"
1037		−source "arch/mips/xilfpga/Kconfig"
1038	1017
1039	1018	endmenu
1040	1019
@@ -2726,6 +2705,15 @@ config NR_CPUS · 1685 unmodified lines
2726	2705	config MIPS_PERF_SHARED_TC_COUNTERS
2727	2706	bool
2728	2707
	2708	+config MIPS_NR_CPU_NR_MAP_1024
	2709	+ bool
	2710	+
	2711	+config MIPS_NR_CPU_NR_MAP
	2712	+ int
	2713	+ depends on SMP
	2714	+ default 1024 if MIPS_NR_CPU_NR_MAP_1024
	2715	+ default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
	2716	+
2729	2717	#
2730	2718	# Timer Interrupt Frequency Configuration
2731	2719	#

arch/mips/Makefile+5−1

@@ -15,7 +15,7 @@ · 14 unmodified lines
15	15	archscripts: scripts_basic
16	16	$(Q)$(MAKE) $(build)=arch/mips/boot/tools relocs
17	17
18		−KBUILD_DEFCONFIG := ip22_defconfig
	18	+KBUILD_DEFCONFIG := 32r2el_defconfig
19	19
20	20	#
21	21	# Select the object file format to substitute into the linker script.
@@ -544,3 +544,7 @@ sead3_defconfig: · 522 unmodified lines
544	544	.PHONY: sead3micro_defconfig
545	545	sead3micro_defconfig:
546	546	$(Q)$(MAKE) -f $(srctree)/Makefile micro32r2el_defconfig BOARDS=sead-3
	547	+
	548	+.PHONY: xilfpga_defconfig
	549	+xilfpga_defconfig:
	550	+ $(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=xilfpga

arch/mips/alchemy/common/clock.c+5−5

@@ -143,7 +143,7 @@ void __init alchemy_set_lpj(void) · 142 unmodified lines
143	143	preset_lpj /= 2 * HZ;
144	144	}
145	145
146		−static struct clk_ops alchemy_clkops_cpu = {
	146	+static const struct clk_ops alchemy_clkops_cpu = {
147	147	.recalc_rate = alchemy_clk_cpu_recalc,
148	148	};
149	149
@@ -224,7 +224,7 @@ static long alchemy_clk_aux_roundr(struct clk_hw *hw, · 74 unmodified lines
224	224	return (parent_rate) mult;
225	225	}
226	226
227		−static struct clk_ops alchemy_clkops_aux = {
	227	+static const struct clk_ops alchemy_clkops_aux = {
228	228	.recalc_rate = alchemy_clk_aux_recalc,
229	229	.set_rate = alchemy_clk_aux_setr,
230	230	.round_rate = alchemy_clk_aux_roundr,
@@ -576,7 +576,7 @@ static int alchemy_clk_fgv1_detr(struct clk_hw *hw, · 345 unmodified lines
576	576	}
577	577
578	578	/* Au1000, Au1100, Au15x0, Au12x0 */
579		−static struct clk_ops alchemy_clkops_fgenv1 = {
	579	+static const struct clk_ops alchemy_clkops_fgenv1 = {
580	580	.recalc_rate = alchemy_clk_fgv1_recalc,
581	581	.determine_rate = alchemy_clk_fgv1_detr,
582	582	.set_rate = alchemy_clk_fgv1_setr,
@@ -717,7 +717,7 @@ static int alchemy_clk_fgv2_detr(struct clk_hw *hw, · 134 unmodified lines
717	717	}
718	718
719	719	/* Au1300 larger input mux, no separate disable bit, flexible divider */
720		−static struct clk_ops alchemy_clkops_fgenv2 = {
	720	+static const struct clk_ops alchemy_clkops_fgenv2 = {
721	721	.recalc_rate = alchemy_clk_fgv2_recalc,
722	722	.determine_rate = alchemy_clk_fgv2_detr,
723	723	.set_rate = alchemy_clk_fgv2_setr,
@@ -925,7 +925,7 @@ static int alchemy_clk_csrc_detr(struct clk_hw *hw, · 201 unmodified lines
925	925	return alchemy_clk_fgcs_detr(hw, req, scale, 4);
926	926	}
927	927
928		−static struct clk_ops alchemy_clkops_csrc = {
	928	+static const struct clk_ops alchemy_clkops_csrc = {
929	929	.recalc_rate = alchemy_clk_csrc_recalc,
930	930	.determine_rate = alchemy_clk_csrc_detr,
931	931	.set_rate = alchemy_clk_csrc_setr,

arch/mips/bcm47xx/leds.c+1−1

@@ -331,7 +331,7 @@ bcm47xx_leds_linksys_wrt54g3gv2[] __initconst = { · 330 unmodified lines
331	331	/* Verified on: WRT54GS V1.0 */
332	332	static const struct gpio_led
333	333	bcm47xx_leds_linksys_wrt54g_type_0101[] __initconst = {
334		− BCM47XX_GPIO_LED(0, "green", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
	334	+ BCM47XX_GPIO_LED(0, "green", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
335	335	BCM47XX_GPIO_LED(1, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
336	336	BCM47XX_GPIO_LED(7, "green", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
337	337	};

arch/mips/bcm63xx/clk.c+195−47

@@ -11,6 +11,7 @@ · 10 unmodified lines
11	11	#include <linux/mutex.h>
12	12	#include <linux/err.h>
13	13	#include <linux/clk.h>
	14	+#include <linux/clkdev.h>
14	15	#include <linux/delay.h>
15	16	#include <bcm63xx_cpu.h>
16	17	#include <bcm63xx_io.h>
@@ -120,22 +121,57 @@ static struct clk clk_ephy = { · 103 unmodified lines
120	121	.set = ephy_set,
121	122	};
122	123
	124	+/*
	125	+ * Ethernet switch SAR clock
	126	+ */
	127	+static void swpkt_sar_set(struct clk *clk, int enable)
	128	+{
	129	+ if (BCMCPU_IS_6368())
	130	+ bcm_hwclock_set(CKCTL_6368_SWPKT_SAR_EN, enable);
	131	+ else
	132	+ return;
	133	+}
	134	+
	135	+static struct clk clk_swpkt_sar = {
	136	+ .set = swpkt_sar_set,
	137	+};
	138	+
	139	+/*
	140	+ * Ethernet switch USB clock
	141	+ */
	142	+static void swpkt_usb_set(struct clk *clk, int enable)
	143	+{
	144	+ if (BCMCPU_IS_6368())
	145	+ bcm_hwclock_set(CKCTL_6368_SWPKT_USB_EN, enable);
	146	+ else
	147	+ return;
	148	+}
	149	+
	150	+static struct clk clk_swpkt_usb = {
	151	+ .set = swpkt_usb_set,
	152	+};
	153	+
123	154	/*
124	155	* Ethernet switch clock
125	156	*/
126	157	static void enetsw_set(struct clk *clk, int enable)
127	158	{
128		− if (BCMCPU_IS_6328())
	159	+ if (BCMCPU_IS_6328()) {
129	160	bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);
130		− else if (BCMCPU_IS_6362())
	161	+ } else if (BCMCPU_IS_6362()) {
131	162	bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);
132		− else if (BCMCPU_IS_6368())
133		− bcm_hwclock_set(CKCTL_6368_ROBOSW_EN \|
134		− CKCTL_6368_SWPKT_USB_EN \|
135		− CKCTL_6368_SWPKT_SAR_EN,
136		− enable);
137		− else
	163	+ } else if (BCMCPU_IS_6368()) {
	164	+ if (enable) {
	165	+ clk_enable_unlocked(&clk_swpkt_sar);
	166	+ clk_enable_unlocked(&clk_swpkt_usb);
	167	+ } else {
	168	+ clk_disable_unlocked(&clk_swpkt_usb);
	169	+ clk_disable_unlocked(&clk_swpkt_sar);
	170	+ }
	171	+ bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable);
	172	+ } else {
138	173	return;
	174	+ }
139	175
140	176	if (enable) {
141	177	/* reset switch core afer clock change */
@@ -247,6 +283,10 @@ static struct clk clk_hsspi = { · 105 unmodified lines
247	283	.set = hsspi_set,
248	284	};
249	285
	286	+/*
	287	+ * HSSPI PLL
	288	+ */
	289	+static struct clk clk_hsspi_pll;
250	290
251	291	/*
252	292	* XTM clock
@@ -256,8 +296,12 @@ static void xtm_set(struct clk *clk, int enable) · 3 unmodified lines
256	296	if (!BCMCPU_IS_6368())
257	297	return;
258	298
259		− bcm_hwclock_set(CKCTL_6368_SAR_EN \|
260		− CKCTL_6368_SWPKT_SAR_EN, enable);
	299	+ if (enable)
	300	+ clk_enable_unlocked(&clk_swpkt_sar);
	301	+ else
	302	+ clk_disable_unlocked(&clk_swpkt_sar);
	303	+
	304	+ bcm_hwclock_set(CKCTL_6368_SAR_EN, enable);
261	305
262	306	if (enable) {
263	307	/* reset sar core afer clock change */
@@ -359,44 +403,128 @@ long clk_round_rate(struct clk *clk, unsigned long rate) · 95 unmodified lines
359	403	}
360	404	EXPORT_SYMBOL_GPL(clk_round_rate);
361	405
362		−struct clk clk_get(struct device dev, const char *id)
363		−{
364		− if (!strcmp(id, "enet0"))
365		− return &clk_enet0;
366		− if (!strcmp(id, "enet1"))
367		− return &clk_enet1;
368		− if (!strcmp(id, "enetsw"))
369		− return &clk_enetsw;
370		− if (!strcmp(id, "ephy"))
371		− return &clk_ephy;
372		− if (!strcmp(id, "usbh"))
373		− return &clk_usbh;
374		− if (!strcmp(id, "usbd"))
375		− return &clk_usbd;
376		− if (!strcmp(id, "spi"))
377		− return &clk_spi;
378		− if (!strcmp(id, "hsspi"))
379		− return &clk_hsspi;
380		− if (!strcmp(id, "xtm"))
381		− return &clk_xtm;
382		− if (!strcmp(id, "periph"))
383		− return &clk_periph;
384		− if ((BCMCPU_IS_3368() \|\| BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
385		− return &clk_pcm;
386		− if ((BCMCPU_IS_6362() \|\| BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
387		− return &clk_ipsec;
388		− if ((BCMCPU_IS_6328() \|\| BCMCPU_IS_6362()) && !strcmp(id, "pcie"))
389		− return &clk_pcie;
390		− return ERR_PTR(-ENOENT);
391		−}
	406	+static struct clk_lookup bcm3368_clks[] = {
	407	+ /* fixed rate clocks */
	408	+ CLKDEV_INIT(NULL, "periph", &clk_periph),
	409	+ CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
	410	+ CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
	411	+ /* gated clocks */
	412	+ CLKDEV_INIT(NULL, "enet0", &clk_enet0),
	413	+ CLKDEV_INIT(NULL, "enet1", &clk_enet1),
	414	+ CLKDEV_INIT(NULL, "ephy", &clk_ephy),
	415	+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
	416	+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
	417	+ CLKDEV_INIT(NULL, "spi", &clk_spi),
	418	+ CLKDEV_INIT(NULL, "pcm", &clk_pcm),
	419	+ CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
	420	+ CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
	421	+};
392	422
393		−EXPORT_SYMBOL(clk_get);
	423	+static struct clk_lookup bcm6328_clks[] = {
	424	+ /* fixed rate clocks */
	425	+ CLKDEV_INIT(NULL, "periph", &clk_periph),
	426	+ CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
	427	+ CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
	428	+ CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
	429	+ /* gated clocks */
	430	+ CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
	431	+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
	432	+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
	433	+ CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
	434	+ CLKDEV_INIT(NULL, "pcie", &clk_pcie),
	435	+};
394	436
395		−void clk_put(struct clk *clk)
396		−{
397		−}
	437	+static struct clk_lookup bcm6338_clks[] = {
	438	+ /* fixed rate clocks */
	439	+ CLKDEV_INIT(NULL, "periph", &clk_periph),
	440	+ CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
	441	+ /* gated clocks */
	442	+ CLKDEV_INIT(NULL, "enet0", &clk_enet0),
	443	+ CLKDEV_INIT(NULL, "enet1", &clk_enet1),
	444	+ CLKDEV_INIT(NULL, "ephy", &clk_ephy),
	445	+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
	446	+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
	447	+ CLKDEV_INIT(NULL, "spi", &clk_spi),
	448	+ CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
	449	+};
398	450
399		−EXPORT_SYMBOL(clk_put);
	451	+static struct clk_lookup bcm6345_clks[] = {
	452	+ /* fixed rate clocks */
	453	+ CLKDEV_INIT(NULL, "periph", &clk_periph),
	454	+ CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
	455	+ /* gated clocks */
	456	+ CLKDEV_INIT(NULL, "enet0", &clk_enet0),
	457	+ CLKDEV_INIT(NULL, "enet1", &clk_enet1),
	458	+ CLKDEV_INIT(NULL, "ephy", &clk_ephy),
	459	+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
	460	+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
	461	+ CLKDEV_INIT(NULL, "spi", &clk_spi),
	462	+ CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
	463	+};
	464	+
	465	+static struct clk_lookup bcm6348_clks[] = {
	466	+ /* fixed rate clocks */
	467	+ CLKDEV_INIT(NULL, "periph", &clk_periph),
	468	+ CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
	469	+ /* gated clocks */
	470	+ CLKDEV_INIT(NULL, "enet0", &clk_enet0),
	471	+ CLKDEV_INIT(NULL, "enet1", &clk_enet1),
	472	+ CLKDEV_INIT(NULL, "ephy", &clk_ephy),
	473	+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
	474	+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
	475	+ CLKDEV_INIT(NULL, "spi", &clk_spi),
	476	+ CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
	477	+ CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet_misc),
	478	+};
	479	+
	480	+static struct clk_lookup bcm6358_clks[] = {
	481	+ /* fixed rate clocks */
	482	+ CLKDEV_INIT(NULL, "periph", &clk_periph),
	483	+ CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
	484	+ CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
	485	+ /* gated clocks */
	486	+ CLKDEV_INIT(NULL, "enet0", &clk_enet0),
	487	+ CLKDEV_INIT(NULL, "enet1", &clk_enet1),
	488	+ CLKDEV_INIT(NULL, "ephy", &clk_ephy),
	489	+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
	490	+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
	491	+ CLKDEV_INIT(NULL, "spi", &clk_spi),
	492	+ CLKDEV_INIT(NULL, "pcm", &clk_pcm),
	493	+ CLKDEV_INIT(NULL, "swpkt_sar", &clk_swpkt_sar),
	494	+ CLKDEV_INIT(NULL, "swpkt_usb", &clk_swpkt_usb),
	495	+ CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
	496	+ CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
	497	+};
	498	+
	499	+static struct clk_lookup bcm6362_clks[] = {
	500	+ /* fixed rate clocks */
	501	+ CLKDEV_INIT(NULL, "periph", &clk_periph),
	502	+ CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
	503	+ CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
	504	+ CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
	505	+ /* gated clocks */
	506	+ CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
	507	+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
	508	+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
	509	+ CLKDEV_INIT(NULL, "spi", &clk_spi),
	510	+ CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
	511	+ CLKDEV_INIT(NULL, "pcie", &clk_pcie),
	512	+ CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
	513	+};
	514	+
	515	+static struct clk_lookup bcm6368_clks[] = {
	516	+ /* fixed rate clocks */
	517	+ CLKDEV_INIT(NULL, "periph", &clk_periph),
	518	+ CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
	519	+ CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
	520	+ /* gated clocks */
	521	+ CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
	522	+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
	523	+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
	524	+ CLKDEV_INIT(NULL, "spi", &clk_spi),
	525	+ CLKDEV_INIT(NULL, "xtm", &clk_xtm),
	526	+ CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
	527	+};
400	528
401	529	#define HSSPI_PLL_HZ_6328 133333333
402	530	#define HSSPI_PLL_HZ_6362 400000000
@@ -404,11 +532,31 @@ EXPORT_SYMBOL(clk_put); · 1 unmodified line
404	532	static int __init bcm63xx_clk_init(void)
405	533	{
406	534	switch (bcm63xx_get_cpu_id()) {
	535	+ case BCM3368_CPU_ID:
	536	+ clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
	537	+ break;
407	538	case BCM6328_CPU_ID:
408		− clk_hsspi.rate = HSSPI_PLL_HZ_6328;
	539	+ clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
	540	+ clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
	541	+ break;
	542	+ case BCM6338_CPU_ID:
	543	+ clkdev_add_table(bcm6338_clks, ARRAY_SIZE(bcm6338_clks));
	544	+ break;
	545	+ case BCM6345_CPU_ID:
	546	+ clkdev_add_table(bcm6345_clks, ARRAY_SIZE(bcm6345_clks));
	547	+ break;
	548	+ case BCM6348_CPU_ID:
	549	+ clkdev_add_table(bcm6348_clks, ARRAY_SIZE(bcm6348_clks));
	550	+ break;
	551	+ case BCM6358_CPU_ID:
	552	+ clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
409	553	break;
410	554	case BCM6362_CPU_ID:
411		− clk_hsspi.rate = HSSPI_PLL_HZ_6362;
	555	+ clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
	556	+ clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
	557	+ break;
	558	+ case BCM6368_CPU_ID:
	559	+ clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
412	560	break;
413	561	}
414	562

arch/mips/boot/dts/brcm/bcm3368.dtsi+2−0

@@ -83,6 +83,7 @@ · 82 unmodified lines
83	83	interrupts = <2>;
84	84
85	85	clocks = <&periph_clk>;
	86	+ clock-names = "refclk";
86	87
87	88	status = "disabled";
88	89	};
@@ -95,6 +96,7 @@ · 6 unmodified lines
95	96	interrupts = <3>;
96	97
97	98	clocks = <&periph_clk>;
	99	+ clock-names = "refclk";
98	100
99	101	status = "disabled";
100	102	};

arch/mips/boot/dts/brcm/bcm63268-comtrend-vr-3032u.dts+1−1

@@ -19,7 +19,7 @@ · 18 unmodified lines
19	19	};
20	20
21	21	&leds0 {
22		− status = "ok";
	22	+ status = "okay";
23	23	brcm,serial-leds;
24	24	brcm,serial-dat-low;
25	25	brcm,serial-shift-inv;

arch/mips/boot/dts/brcm/bcm63268.dtsi+2−0

@@ -84,6 +84,7 @@ · 83 unmodified lines
84	84	interrupts = <5>;
85	85
86	86	clocks = <&periph_clk>;
	87	+ clock-names = "refclk";
87	88
88	89	status = "disabled";
89	90	};
@@ -96,6 +97,7 @@ · 6 unmodified lines
96	97	interrupts = <34>;
97	98
98	99	clocks = <&periph_clk>;
	100	+ clock-names = "refclk";
99	101
100	102	status = "disabled";
101	103	};

arch/mips/boot/dts/brcm/bcm6328.dtsi+2−0

@@ -69,6 +69,7 @@ · 68 unmodified lines
69	69	interrupt-parent = <&periph_intc>;
70	70	interrupts = <28>;
71	71	clocks = <&periph_clk>;
	72	+ clock-names = "refclk";
72	73	status = "disabled";
73	74	};
74	75
@@ -78,6 +79,7 @@ · 3 unmodified lines
78	79	interrupt-parent = <&periph_intc>;
79	80	interrupts = <39>;
80	81	clocks = <&periph_clk>;
	82	+ clock-names = "refclk";
81	83	status = "disabled";
82	84	};
83	85

arch/mips/boot/dts/brcm/bcm6358-neufbox4-sercomm.dts+1−1

@@ -19,7 +19,7 @@ · 18 unmodified lines
19	19	};
20	20
21	21	&leds0 {
22		− status = "ok";
	22	+ status = "okay";
23	23
24	24	led@0 {
25	25	reg = <0>;

arch/mips/boot/dts/brcm/bcm6358.dtsi+2−0

@@ -93,6 +93,7 @@ · 92 unmodified lines
93	93	interrupts = <2>;
94	94
95	95	clocks = <&periph_clk>;
	96	+ clock-names = "refclk";
96	97
97	98	status = "disabled";
98	99	};
@@ -105,6 +106,7 @@ · 6 unmodified lines
105	106	interrupts = <3>;
106	107
107	108	clocks = <&periph_clk>;
	109	+ clock-names = "refclk";
108	110
109	111	status = "disabled";
110	112	};

arch/mips/boot/dts/brcm/bcm6362.dtsi+2−0

@@ -84,6 +84,7 @@ · 83 unmodified lines
84	84	interrupts = <3>;
85	85
86	86	clocks = <&periph_clk>;
	87	+ clock-names = "refclk";
87	88
88	89	status = "disabled";
89	90	};
@@ -96,6 +97,7 @@ · 6 unmodified lines
96	97	interrupts = <4>;
97	98
98	99	clocks = <&periph_clk>;
	100	+ clock-names = "refclk";
99	101
100	102	status = "disabled";
101	103	};

arch/mips/boot/dts/brcm/bcm6368.dtsi+2−0

@@ -90,6 +90,7 @@ · 89 unmodified lines
90	90	interrupt-parent = <&periph_intc>;
91	91	interrupts = <2>;
92	92	clocks = <&periph_clk>;
	93	+ clock-names = "refclk";
93	94	status = "disabled";
94	95	};
95	96
@@ -99,6 +100,7 @@ · 3 unmodified lines
99	100	interrupt-parent = <&periph_intc>;
100	101	interrupts = <3>;
101	102	clocks = <&periph_clk>;
	103	+ clock-names = "refclk";
102	104	status = "disabled";
103	105	};
104	106

arch/mips/boot/dts/img/pistachio.dtsi+0−1

@@ -805,7 +805,6 @@ · 804 unmodified lines
805	805	pinctrl-0 = <&sdhost_pins>;
806	806	pinctrl-names = "default";
807	807	fifo-depth = <0x20>;
808		− num-slots = <1>;
809	808	clock-frequency = <50000000>;
810	809	bus-width = <8>;
811	810	cap-mmc-highspeed;

arch/mips/boot/dts/ingenic/jz4780.dtsi+5−0

@@ -219,6 +219,11 @@ · 218 unmodified lines
219	219	status = "disabled";
220	220	};
221	221
	222	+ watchdog: watchdog@10002000 {
	223	+ compatible = "ingenic,jz4780-watchdog";
	224	+ reg = <0x10002000 0x100>;
	225	+ };
	226	+
222	227	nemc: nemc@13410000 {
223	228	compatible = "ingenic,jz4780-nemc";
224	229	reg = <0x13410000 0x10000>;

arch/mips/boot/dts/ralink/rt3052_eval.dts+1−1

@@ -47,6 +47,6 @@ · 46 unmodified lines
47	47	};
48	48
49	49	usb@101c0000 {
50		− status = "ok";
	50	+ status = "okay";
51	51	};
52	52	};

arch/mips/boot/dts/xilfpga/Makefile+1−1

@@ -1,5 +1,5 @@
1	1	# SPDX-License-Identifier: GPL-2.0
2		−dtb-$(CONFIG_XILFPGA_NEXYS4DDR) += nexys4ddr.dtb
	2	+dtb-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += nexys4ddr.dtb
3	3
4	4	obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
5	5

arch/mips/boot/dts/xilfpga/nexys4ddr.dts+8−0

@@ -6,6 +6,14 @@ · 5 unmodified lines
6	6	/ {
7	7	compatible = "digilent,nexys4ddr";
8	8
	9	+ aliases {
	10	+ serial0 = &axi_uart16550;
	11	+ };
	12	+ chosen {
	13	+ bootargs = "console=ttyS0,115200";
	14	+ stdout-path = "serial0:115200n8";
	15	+ };
	16	+
9	17	memory {
10	18	device_type = "memory";
11	19	reg = <0x0 0x08000000>;

arch/mips/cavium-octeon/executive/cvmx-helper.c+1−1

@@ -862,7 +862,7 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) · 861 unmodified lines
862	862	*/
863	863	cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
864	864
865		− cvmx_wait(100000000ull);
	865	+ __delay(100000000ull);
866	866
867	867	for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) {
868	868	retry_cnt = 100000;

arch/mips/cavium-octeon/executive/cvmx-spi.c+5−5

@@ -215,7 +215,7 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode) · 214 unmodified lines
215	215	spxx_clk_ctl.u64 = 0;
216	216	spxx_clk_ctl.s.runbist = 1;
217	217	cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
218		− cvmx_wait(10 * MS);
	218	+ __delay(10 * MS);
219	219	spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));
220	220	if (spxx_bist_stat.s.stat0)
221	221	cvmx_dprintf
@@ -265,14 +265,14 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode) · 43 unmodified lines
265	265	spxx_clk_ctl.s.rcvtrn = 0;
266	266	spxx_clk_ctl.s.srxdlck = 0;
267	267	cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
268		− cvmx_wait(100 * MS);
	268	+ __delay(100 * MS);
269	269
270	270	/* Reset SRX0 DLL */
271	271	spxx_clk_ctl.s.srxdlck = 1;
272	272	cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
273	273
274	274	/* Waiting for Inf0 Spi4 RX DLL to lock */
275		− cvmx_wait(100 * MS);
	275	+ __delay(100 * MS);
276	276
277	277	/* Enable dynamic alignment */
278	278	spxx_trn4_ctl.s.trntest = 0;
@@ -527,7 +527,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout) · 248 unmodified lines
527	527	spxx_clk_ctl.s.rcvtrn = 1;
528	528	spxx_clk_ctl.s.srxdlck = 1;
529	529	cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
530		− cvmx_wait(1000 * MS);
	530	+ __delay(1000 * MS);
531	531
532	532	/* SRX0 clear the boot bit */
533	533	spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));
@@ -536,7 +536,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout) · 2 unmodified lines
536	536
537	537	/* Wait for the training sequence to complete */
538	538	cvmx_dprintf("SPI%d: Waiting for training\n", interface);
539		− cvmx_wait(1000 * MS);
	539	+ __delay(1000 * MS);
540	540	/* Wait a really long time here */
541	541	timeout_time = cvmx_get_cycle() + 1000ull * MS * 600;
542	542	/*

arch/mips/configs/ci20_defconfig+6−1

@@ -38,6 +38,8 @@ CONFIG_NET=y · 37 unmodified lines
38	38	CONFIG_PACKET=y
39	39	CONFIG_UNIX=y
40	40	CONFIG_INET=y
	41	+CONFIG_IP_PNP=y
	42	+CONFIG_IP_PNP_DHCP=y
41	43	# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
42	44	# CONFIG_INET_XFRM_MODE_TUNNEL is not set
43	45	# CONFIG_INET_XFRM_MODE_BEET is not set
@@ -93,6 +95,8 @@ CONFIG_I2C_JZ4780=y · 49 unmodified lines
93	95	CONFIG_GPIO_SYSFS=y
94	96	CONFIG_GPIO_INGENIC=y
95	97	# CONFIG_HWMON is not set
	98	+CONFIG_WATCHDOG=y
	99	+CONFIG_JZ4740_WDT=y
96	100	CONFIG_REGULATOR=y
97	101	CONFIG_REGULATOR_DEBUG=y
98	102	CONFIG_REGULATOR_FIXED_VOLTAGE=y
@@ -110,7 +114,8 @@ CONFIG_PROC_KCORE=y · 11 unmodified lines
110	114	CONFIG_TMPFS=y
111	115	CONFIG_CONFIGFS_FS=y
112	116	CONFIG_UBIFS_FS=y
113		−# CONFIG_NETWORK_FILESYSTEMS is not set
	117	+CONFIG_NFS_FS=y
	118	+CONFIG_ROOT_NFS=y
114	119	CONFIG_NLS=y
115	120	CONFIG_NLS_CODEPAGE_437=y
116	121	CONFIG_NLS_CODEPAGE_737=y

arch/mips/configs/generic/board-xilfpga.config+22−0

@@ -0,0 +1,22 @@
	1	+# require CONFIG_CPU_MIPS32_R2=y
	2	+# require CONFIG_CPU_LITTLE_ENDIAN=y
	3	+
	4	+CONFIG_SERIAL_8250=y
	5	+CONFIG_SERIAL_8250_CONSOLE=y
	6	+CONFIG_SERIAL_OF_PLATFORM=y
	7	+CONFIG_GPIO_SYSFS=y
	8	+CONFIG_GPIO_XILINX=y
	9	+CONFIG_PANIC_ON_OOPS=y
	10	+CONFIG_FIT_IMAGE_FDT_XILFPGA=y
	11	+CONFIG_I2C=y
	12	+CONFIG_I2C_CHARDEV=y
	13	+CONFIG_I2C_XILINX=y
	14	+CONFIG_SENSORS_ADT7410=y
	15	+CONFIG_TMPFS=y
	16	+CONFIG_NET=y
	17	+CONFIG_PACKET=y
	18	+CONFIG_UNIX=y
	19	+CONFIG_INET=y
	20	+CONFIG_NETDEVICES=y
	21	+CONFIG_XILINX_EMACLITE=y
	22	+CONFIG_SMSC_PHY=y

arch/mips/configs/ip22_defconfig+1−0

@@ -1,3 +1,4 @@
	1	+CONFIG_SGI_IP22=y
1	2	CONFIG_ARC_CONSOLE=y
2	3	CONFIG_CPU_R5000=y
3	4	CONFIG_NO_HZ=y

arch/mips/configs/xilfpga_defconfig+0−75

@@ -1,75 +0,0 @@
1		−CONFIG_MACH_XILFPGA=y
2		−# CONFIG_COMPACTION is not set
3		−# CONFIG_LOCALVERSION_AUTO is not set
4		−CONFIG_EMBEDDED=y
5		−# CONFIG_VM_EVENT_COUNTERS is not set
6		−# CONFIG_COMPAT_BRK is not set
7		−CONFIG_SLAB=y
8		−# CONFIG_BLOCK is not set
9		−# CONFIG_SUSPEND is not set
10		−CONFIG_NET=y
11		−CONFIG_PACKET=y
12		−CONFIG_UNIX=y
13		−CONFIG_INET=y
14		−# CONFIG_IPV6 is not set
15		−# CONFIG_WIRELESS is not set
16		−# CONFIG_UEVENT_HELPER is not set
17		−CONFIG_DEVTMPFS=y
18		−CONFIG_DEVTMPFS_MOUNT=y
19		−# CONFIG_STANDALONE is not set
20		−# CONFIG_PREVENT_FIRMWARE_BUILD is not set
21		−# CONFIG_FW_LOADER is not set
22		−# CONFIG_ALLOW_DEV_COREDUMP is not set
23		−CONFIG_NETDEVICES=y
24		−# CONFIG_NET_CORE is not set
25		−# CONFIG_NET_VENDOR_ARC is not set
26		−# CONFIG_NET_CADENCE is not set
27		−# CONFIG_NET_VENDOR_BROADCOM is not set
28		−# CONFIG_NET_VENDOR_EZCHIP is not set
29		−# CONFIG_NET_VENDOR_INTEL is not set
30		−# CONFIG_NET_VENDOR_MARVELL is not set
31		−# CONFIG_NET_VENDOR_MICREL is not set
32		−# CONFIG_NET_VENDOR_NATSEMI is not set
33		−# CONFIG_NET_VENDOR_NETRONOME is not set
34		−# CONFIG_NET_VENDOR_QUALCOMM is not set
35		−# CONFIG_NET_VENDOR_RENESAS is not set
36		−# CONFIG_NET_VENDOR_ROCKER is not set
37		−# CONFIG_NET_VENDOR_SAMSUNG is not set
38		−# CONFIG_NET_VENDOR_SEEQ is not set
39		−# CONFIG_NET_VENDOR_SMSC is not set
40		−# CONFIG_NET_VENDOR_STMICRO is not set
41		−# CONFIG_NET_VENDOR_SYNOPSYS is not set
42		−# CONFIG_NET_VENDOR_VIA is not set
43		−# CONFIG_NET_VENDOR_WIZNET is not set
44		−CONFIG_XILINX_EMACLITE=y
45		−CONFIG_SMSC_PHY=y
46		−# CONFIG_WLAN is not set
47		−# CONFIG_INPUT_MOUSEDEV is not set
48		−# CONFIG_INPUT_KEYBOARD is not set
49		−# CONFIG_INPUT_MOUSE is not set
50		−# CONFIG_SERIO is not set
51		−CONFIG_VT_HW_CONSOLE_BINDING=y
52		−# CONFIG_UNIX98_PTYS is not set
53		−# CONFIG_LEGACY_PTYS is not set
54		−CONFIG_SERIAL_8250=y
55		−CONFIG_SERIAL_8250_CONSOLE=y
56		−CONFIG_SERIAL_OF_PLATFORM=y
57		−# CONFIG_HW_RANDOM is not set
58		−CONFIG_I2C=y
59		−CONFIG_I2C_CHARDEV=y
60		−# CONFIG_I2C_HELPER_AUTO is not set
61		−CONFIG_I2C_XILINX=y
62		−CONFIG_GPIO_SYSFS=y
63		−CONFIG_GPIO_XILINX=y
64		−CONFIG_SENSORS_ADT7410=y
65		−# CONFIG_USB_SUPPORT is not set
66		−# CONFIG_MIPS_PLATFORM_DEVICES is not set
67		−# CONFIG_IOMMU_SUPPORT is not set
68		−# CONFIG_PROC_PAGE_MONITOR is not set
69		−CONFIG_TMPFS=y
70		−# CONFIG_MISC_FILESYSTEMS is not set
71		−CONFIG_PANIC_ON_OOPS=y
72		−# CONFIG_SCHED_DEBUG is not set
73		−# CONFIG_FTRACE is not set
74		−CONFIG_CMDLINE_BOOL=y
75		−CONFIG_CMDLINE="console=ttyS0,115200"

arch/mips/generic/Kconfig+6−0

@@ -43,4 +43,10 @@ config FIT_IMAGE_FDT_NI169445 · 42 unmodified lines
43	43	Enable this to include the FDT for the 169445 platform from
44	44	National Instruments in the FIT kernel image.
45	45
	46	+config FIT_IMAGE_FDT_XILFPGA
	47	+ bool "Include FDT for Xilfpga"
	48	+ help
	49	+ Enable this to include the FDT for the MIPSfpga platform
	50	+ from Imagination Technologies in the FIT kernel image.
	51	+
46	52	endif

arch/mips/generic/board-xilfpga.its.S+22−0

@@ -0,0 +1,22 @@
	1	+/ {
	2	+ images {
	3	+ fdt@xilfpga {
	4	+ description = "MIPSfpga (xilfpga) Device Tree";
	5	+ data = /incbin/("boot/dts/xilfpga/nexys4ddr.dtb");
	6	+ type = "flat_dt";
	7	+ arch = "mips";
	8	+ compression = "none";
	9	+ hash@0 {
	10	+ algo = "sha1";
	11	+ };
	12	+ };
	13	+ };
	14	+
	15	+ configurations {
	16	+ conf@xilfpga {
	17	+ description = "MIPSfpga Linux kernel";
	18	+ kernel = "kernel@0";
	19	+ fdt = "fdt@xilfpga";
	20	+ };
	21	+ };
	22	+};

arch/mips/include/asm/asmmacro.h+9−7

@@ -19,6 +19,9 @@ · 18 unmodified lines
19	19	#include <asm/asmmacro-64.h>
20	20	#endif
21	21
	22	+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
	23	+#undef fp
	24	+
22	25	/*
23	26	* Helper macros for generating raw instruction encodings.
24	27	*/
@@ -105,6 +108,7 @@ · 80 unmodified lines
105	108	.macro fpu_save_16odd thread
106	109	.set push
107	110	.set mips64r2
	111	+ .set fp=64
108	112	SET_HARDFLOAT
109	113	sdc1 $f1, THREAD_FPR1(\thread)
110	114	sdc1 $f3, THREAD_FPR3(\thread)
@@ -126,8 +130,8 @@ · 15 unmodified lines
126	130	.endm
127	131
128	132	.macro fpu_save_double thread status tmp
129		−#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
130		− defined(CONFIG_CPU_MIPS32_R6)
	133	+#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPSR2) \|\| \
	134	+ defined(CONFIG_CPU_MIPSR6)
131	135	sll \tmp, \status, 5
132	136	bgez \tmp, 10f
133	137	fpu_save_16odd \thread
@@ -163,6 +167,7 @@ · 29 unmodified lines
163	167	.macro fpu_restore_16odd thread
164	168	.set push
165	169	.set mips64r2
	170	+ .set fp=64
166	171	SET_HARDFLOAT
167	172	ldc1 $f1, THREAD_FPR1(\thread)
168	173	ldc1 $f3, THREAD_FPR3(\thread)
@@ -184,8 +189,8 @@ · 15 unmodified lines
184	189	.endm
185	190
186	191	.macro fpu_restore_double thread status tmp
187		−#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
188		− defined(CONFIG_CPU_MIPS32_R6)
	192	+#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPSR2) \|\| \
	193	+ defined(CONFIG_CPU_MIPSR6)
189	194	sll \tmp, \status, 5
190	195	bgez \tmp, 10f # 16 register mode?
191	196
@@ -234,9 +239,6 @@ · 42 unmodified lines
234	239	.endm
235	240
236	241	#ifdef TOOLCHAIN_SUPPORTS_MSA
237		−/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
238		−#undef fp
239		−
240	242	.macro _cfcmsa rd, cs
241	243	.set push
242	244	.set mips32r2

arch/mips/include/asm/bitops.h+1−0

@@ -456,6 +456,7 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long * · 455 unmodified lines
456	456	{
457	457	smp_mb__before_llsc();
458	458	__clear_bit(nr, addr);
	459	+ nudge_writes();
459	460	}
460	461
461	462	/*

arch/mips/include/asm/cmpxchg.h+2−0

@@ -204,8 +204,10 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, · 203 unmodified lines
204	204	#else
205	205	#include <asm-generic/cmpxchg-local.h>
206	206	#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
	207	+#ifndef CONFIG_SMP
207	208	#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
208	209	#endif
	210	+#endif
209	211
210	212	#undef __scbeqz
211	213

arch/mips/include/asm/mipsregs.h+6−8

@@ -1355,19 +1355,17 @@ do { \ · 1354 unmodified lines
1355	1355	if (sel == 0) \
1356	1356	__asm__ __volatile__( \
1357	1357	".set\tmips64\n\t" \
1358		− "dmfc0\t%M0, " #source "\n\t" \
1359		− "dsll\t%L0, %M0, 32\n\t" \
1360		− "dsra\t%M0, %M0, 32\n\t" \
1361		− "dsra\t%L0, %L0, 32\n\t" \
	1358	+ "dmfc0\t%L0, " #source "\n\t" \
	1359	+ "dsra\t%M0, %L0, 32\n\t" \
	1360	+ "sll\t%L0, %L0, 0\n\t" \
1362	1361	".set\tmips0" \
1363	1362	: "=r" (__val)); \
1364	1363	else \
1365	1364	__asm__ __volatile__( \
1366	1365	".set\tmips64\n\t" \
1367		− "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1368		− "dsll\t%L0, %M0, 32\n\t" \
1369		− "dsra\t%M0, %M0, 32\n\t" \
1370		− "dsra\t%L0, %L0, 32\n\t" \
	1366	+ "dmfc0\t%L0, " #source ", " #sel "\n\t" \
	1367	+ "dsra\t%M0, %L0, 32\n\t" \
	1368	+ "sll\t%L0, %L0, 0\n\t" \
1371	1369	".set\tmips0" \
1372	1370	: "=r" (__val)); \
1373	1371	local_irq_restore(__flags); \

arch/mips/include/asm/octeon/cvmx-fpa.h+3−1

@@ -36,6 +36,8 @@ · 35 unmodified lines
36	36	#ifndef __CVMX_FPA_H__
37	37	#define __CVMX_FPA_H__
38	38
	39	+#include <linux/delay.h>
	40	+
39	41	#include <asm/octeon/cvmx-address.h>
40	42	#include <asm/octeon/cvmx-fpa-defs.h>
41	43
@@ -165,7 +167,7 @@ static inline void cvmx_fpa_enable(void) · 123 unmodified lines
165	167	}
166	168
167	169	/* Enforce a 10 cycle delay between config and enable */
168		− cvmx_wait(10);
	170	+ __delay(10);
169	171	}
170	172
171	173	/* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */

arch/mips/include/asm/octeon/cvmx.h+2−13

@@ -30,6 +30,7 @@ · 29 unmodified lines
30	30
31	31	#include <linux/kernel.h>
32	32	#include <linux/string.h>
	33	+#include <linux/delay.h>
33	34
34	35	enum cvmx_mips_space {
35	36	CVMX_MIPS_SPACE_XKSEG = 3LL,
@@ -428,18 +429,6 @@ static inline uint64_t cvmx_get_cycle(void) · 392 unmodified lines
428	429	return cycle;
429	430	}
430	431
431		−/**
432		− * Wait for the specified number of cycle
433		− *
434		− */
435		−static inline void cvmx_wait(uint64_t cycles)
436		−{
437		− uint64_t done = cvmx_get_cycle() + cycles;
438		−
439		− while (cvmx_get_cycle() < done)
440		− ; /* Spin */
441		−}
442		−
443	432	/**
444	433	* Reads a chip global cycle counter. This counts CPU cycles since
445	434	* chip reset. The counter is 64 bit.
@@ -481,7 +470,7 @@ static inline uint64_t cvmx_get_cycle_global(void) · 35 unmodified lines
481	470	result = -1; \
482	471	break; \
483	472	} else \
484		− cvmx_wait(100); \
	473	+ __delay(100); \
485	474	} \
486	475	} while (0); \
487	476	result; \

arch/mips/include/asm/page.h+2−2

@@ -240,8 +240,8 @@ static inline int pfn_valid(unsigned long pfn) · 239 unmodified lines
240	240
241	241	#endif
242	242
243		−#define virt_to_page(kaddr) pfn_to_page(PFN_DOWN(virt_to_phys((void *) \
244		− (kaddr))))
	243	+#define virt_to_pfn(kaddr) PFN_DOWN(virt_to_phys((void *)(kaddr)))
	244	+#define virt_to_page(kaddr) pfn_to_page(virt_to_pfn(kaddr))
245	245
246	246	extern int __virt_addr_valid(const volatile void *kaddr);
247	247	#define virt_addr_valid(kaddr) \

arch/mips/include/asm/processor.h+0−2

@@ -368,8 +368,6 @@ struct task_struct; · 367 unmodified lines
368	368	/* Free all resources held by a thread. */
369	369	#define release_thread(thread) do { } while(0)
370	370
371		−extern unsigned long thread_saved_pc(struct task_struct *tsk);
372		−
373	371	/*
374	372	* Do necessary setup to start up a newly executed thread.
375	373	*/

arch/mips/include/asm/smp.h+1−1

@@ -29,7 +29,7 @@ extern cpumask_t cpu_foreign_map[]; · 28 unmodified lines
29	29
30	30	/* Map from cpu id to sequential logical cpu number. This will only
31	31	not be idempotent when cpus failed to come on-line. */
32		−extern int __cpu_number_map[NR_CPUS];
	32	+extern int __cpu_number_map[CONFIG_MIPS_NR_CPU_NR_MAP];
33	33	#define cpu_number_map(cpu) __cpu_number_map[cpu]
34	34
35	35	/* The reverse map from sequential logical cpu number to cpu id. */

arch/mips/include/asm/syscall.h+25−4

@@ -26,12 +26,34 @@ · 25 unmodified lines
26	26	#define __NR_syscall 4000
27	27	#endif
28	28
	29	+static inline bool mips_syscall_is_indirect(struct task_struct *task,
	30	+ struct pt_regs *regs)
	31	+{
	32	+ /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
	33	+ return (IS_ENABLED(CONFIG_32BIT) \|\|
	34	+ test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
	35	+ (regs->regs[2] == __NR_syscall);
	36	+}
	37	+
29	38	static inline long syscall_get_nr(struct task_struct *task,
30	39	struct pt_regs *regs)
31	40	{
32	41	return current_thread_info()->syscall;
33	42	}
34	43
	44	+static inline void mips_syscall_update_nr(struct task_struct *task,
	45	+ struct pt_regs *regs)
	46	+{
	47	+ /*
	48	+ * v0 is the system call number, except for O32 ABI syscall(), where it
	49	+ * ends up in a0.
	50	+ */
	51	+ if (mips_syscall_is_indirect(task, regs))
	52	+ task_thread_info(task)->syscall = regs->regs[4];
	53	+ else
	54	+ task_thread_info(task)->syscall = regs->regs[2];
	55	+}
	56	+
35	57	static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
36	58	struct task_struct task, struct pt_regs regs, unsigned int n)
37	59	{
@@ -98,10 +120,9 @@ static inline void syscall_get_arguments(struct task_struct *task, · 60 unmodified lines
98	120	unsigned long *args)
99	121	{
100	122	int ret;
101		− /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
102		− if ((IS_ENABLED(CONFIG_32BIT) \|\|
103		− test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
104		− (regs->regs[2] == __NR_syscall))
	123	+
	124	+ /* O32 ABI syscall() */
	125	+ if (mips_syscall_is_indirect(task, regs))
105	126	i++;
106	127
107	128	while (n--)

arch/mips/kernel/process.c+1−1

@@ -487,7 +487,7 @@ arch_initcall(frame_info_init); · 486 unmodified lines
487	487	/*
488	488	* Return saved PC of a blocked thread.
489	489	*/
490		−unsigned long thread_saved_pc(struct task_struct *tsk)
	490	+static unsigned long thread_saved_pc(struct task_struct *tsk)
491	491	{
492	492	struct thread_struct *t = &tsk->thread;
493	493

arch/mips/kernel/ptrace.c+38−3

@@ -144,6 +144,9 @@ int ptrace_setregs(struct task_struct child, struct user_pt_regs __user data) · 143 unmodified lines
144	144
145	145	/* badvaddr, status, and cause may not be written. */
146	146
	147	+ /* System call number may have been changed */
	148	+ mips_syscall_update_nr(child, regs);
	149	+
147	150	return 0;
148	151	}
149	152
@@ -345,6 +348,9 @@ static int gpr32_set(struct task_struct *target, · 195 unmodified lines
345	348	}
346	349	}
347	350
	351	+ /* System call number may have been changed */
	352	+ mips_syscall_update_nr(target, regs);
	353	+
348	354	return 0;
349	355	}
350	356
@@ -405,6 +411,9 @@ static int gpr64_set(struct task_struct *target, · 54 unmodified lines
405	411	}
406	412	}
407	413
	414	+ /* System call number may have been changed */
	415	+ mips_syscall_update_nr(target, regs);
	416	+
408	417	return 0;
409	418	}
410	419
@@ -618,6 +627,19 @@ static const struct user_regset_view user_mips64_view = { · 207 unmodified lines
618	627	.n = ARRAY_SIZE(mips64_regsets),
619	628	};
620	629
	630	+#ifdef CONFIG_MIPS32_N32
	631	+
	632	+static const struct user_regset_view user_mipsn32_view = {
	633	+ .name = "mipsn32",
	634	+ .e_flags = EF_MIPS_ABI2,
	635	+ .e_machine = ELF_ARCH,
	636	+ .ei_osabi = ELF_OSABI,
	637	+ .regsets = mips64_regsets,
	638	+ .n = ARRAY_SIZE(mips64_regsets),
	639	+};
	640	+
	641	+#endif /* CONFIG_MIPS32_N32 */
	642	+
621	643	#endif /* CONFIG_64BIT */
622	644
623	645	const struct user_regset_view task_user_regset_view(struct task_struct task)
@@ -628,6 +650,10 @@ const struct user_regset_view task_user_regset_view(struct task_struct task) · 4 unmodified lines
628	650	#ifdef CONFIG_MIPS32_O32
629	651	if (test_tsk_thread_flag(task, TIF_32BIT_REGS))
630	652	return &user_mips_view;
	653	+#endif
	654	+#ifdef CONFIG_MIPS32_N32
	655	+ if (test_tsk_thread_flag(task, TIF_32BIT_ADDR))
	656	+ return &user_mipsn32_view;
631	657	#endif
632	658	return &user_mips64_view;
633	659	#endif
@@ -753,6 +779,12 @@ long arch_ptrace(struct task_struct *child, long request, · 119 unmodified lines
753	779	switch (addr) {
754	780	case 0 ... 31:
755	781	regs->regs[addr] = data;
	782	+ /* System call number may have been changed */
	783	+ if (addr == 2)
	784	+ mips_syscall_update_nr(child, regs);
	785	+ else if (addr == 4 &&
	786	+ mips_syscall_is_indirect(child, regs))
	787	+ mips_syscall_update_nr(child, regs);
756	788	break;
757	789	case FPR_BASE ... FPR_BASE + 31: {
758	790	union fpureg *fregs = get_fpu_regs(child);
@@ -864,9 +896,11 @@ asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall) · 105 unmodified lines
864	896
865	897	current_thread_info()->syscall = syscall;
866	898
867		− if (test_thread_flag(TIF_SYSCALL_TRACE) &&
868		− tracehook_report_syscall_entry(regs))
869		− return -1;
	899	+ if (test_thread_flag(TIF_SYSCALL_TRACE)) {
	900	+ if (tracehook_report_syscall_entry(regs))
	901	+ return -1;
	902	+ syscall = current_thread_info()->syscall;
	903	+ }
870	904
871	905	#ifdef CONFIG_SECCOMP
872	906	if (unlikely(test_thread_flag(TIF_SECCOMP))) {
@@ -884,6 +918,7 @@ asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall) · 11 unmodified lines
884	918	ret = __secure_computing(&sd);
885	919	if (ret == -1)
886	920	return ret;
	921	+ syscall = current_thread_info()->syscall;
887	922	}
888	923	#endif
889	924

arch/mips/kernel/ptrace32.c+7−0

@@ -33,6 +33,7 @@ · 32 unmodified lines
33	33	#include <asm/pgtable.h>
34	34	#include <asm/page.h>
35	35	#include <asm/reg.h>
	36	+#include <asm/syscall.h>
36	37	#include <linux/uaccess.h>
37	38	#include <asm/bootinfo.h>
38	39
@@ -195,6 +196,12 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, · 156 unmodified lines
195	196	switch (addr) {
196	197	case 0 ... 31:
197	198	regs->regs[addr] = data;
	199	+ /* System call number may have been changed */
	200	+ if (addr == 2)
	201	+ mips_syscall_update_nr(child, regs);
	202	+ else if (addr == 4 &&
	203	+ mips_syscall_is_indirect(child, regs))
	204	+ mips_syscall_update_nr(child, regs);
198	205	break;
199	206	case FPR_BASE ... FPR_BASE + 31: {
200	207	union fpureg *fregs = get_fpu_regs(child);

arch/mips/kernel/r4k_fpu.S+10−10

@@ -40,8 +40,8 @@ · 39 unmodified lines
40	40	*/
41	41	LEAF(_save_fp)
42	42	EXPORT_SYMBOL(_save_fp)
43		−#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
44		− defined(CONFIG_CPU_MIPS32_R6)
	43	+#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPSR2) \|\| \
	44	+ defined(CONFIG_CPU_MIPSR6)
45	45	mfc0 t0, CP0_STATUS
46	46	#endif
47	47	fpu_save_double a0 t0 t1 # clobbers t1
@@ -52,8 +52,8 @@ EXPORT_SYMBOL(_save_fp) · 4 unmodified lines
52	52	* Restore a thread's fp context.
53	53	*/
54	54	LEAF(_restore_fp)
55		−#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
56		− defined(CONFIG_CPU_MIPS32_R6)
	55	+#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPSR2) \|\| \
	56	+ defined(CONFIG_CPU_MIPSR6)
57	57	mfc0 t0, CP0_STATUS
58	58	#endif
59	59	fpu_restore_double a0 t0 t1 # clobbers t1
@@ -246,11 +246,11 @@ LEAF(_save_fp_context) · 186 unmodified lines
246	246	cfc1 t1, fcr31
247	247	.set pop
248	248
249		−#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
250		− defined(CONFIG_CPU_MIPS32_R6)
	249	+#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPSR2) \|\| \
	250	+ defined(CONFIG_CPU_MIPSR6)
251	251	.set push
252	252	SET_HARDFLOAT
253		−#ifdef CONFIG_CPU_MIPS32_R2
	253	+#ifdef CONFIG_CPU_MIPSR2
254	254	.set mips32r2
255	255	.set fp=64
256	256	mfc0 t0, CP0_STATUS
@@ -314,11 +314,11 @@ LEAF(_save_fp_context) · 57 unmodified lines
314	314	LEAF(_restore_fp_context)
315	315	EX lw t1, 0(a1)
316	316
317		−#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
318		− defined(CONFIG_CPU_MIPS32_R6)
	317	+#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPSR2) \|\| \
	318	+ defined(CONFIG_CPU_MIPSR6)
319	319	.set push
320	320	SET_HARDFLOAT
321		−#ifdef CONFIG_CPU_MIPS32_R2
	321	+#ifdef CONFIG_CPU_MIPSR2
322	322	.set mips32r2
323	323	.set fp=64
324	324	mfc0 t0, CP0_STATUS

arch/mips/kernel/setup.c+4−0

@@ -80,6 +80,7 @@ EXPORT_SYMBOL(mips_io_port_base); · 79 unmodified lines
80	80
81	81	static struct resource code_resource = { .name = "Kernel code", };
82	82	static struct resource data_resource = { .name = "Kernel data", };
	83	+static struct resource bss_resource = { .name = "Kernel bss", };
83	84
84	85	static void *detect_magic __initdata = detect_memory_region;
85	86
@@ -927,6 +928,8 @@ static void __init resource_init(void) · 841 unmodified lines
927	928	code_resource.end = __pa_symbol(&_etext) - 1;
928	929	data_resource.start = __pa_symbol(&_etext);
929	930	data_resource.end = __pa_symbol(&_edata) - 1;
	931	+ bss_resource.start = __pa_symbol(&__bss_start);
	932	+ bss_resource.end = __pa_symbol(&__bss_stop) - 1;
930	933
931	934	for (i = 0; i < boot_mem_map.nr_map; i++) {
932	935	struct resource *res;
@@ -966,6 +969,7 @@ static void __init resource_init(void) · 33 unmodified lines
966	969	*/
967	970	request_resource(res, &code_resource);
968	971	request_resource(res, &data_resource);
	972	+ request_resource(res, &bss_resource);
969	973	request_crashkernel(res);
970	974	}
971	975	}

arch/mips/kernel/smp.c+1−1

@@ -48,7 +48,7 @@ · 47 unmodified lines
48	48	#include <asm/setup.h>
49	49	#include <asm/maar.h>
50	50
51		−int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
	51	+int __cpu_number_map[CONFIG_MIPS_NR_CPU_NR_MAP]; /* Map physical to logical */
52	52	EXPORT_SYMBOL(__cpu_number_map);
53	53
54	54	int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */

arch/mips/lantiq/xway/sysctrl.c+2−4

@@ -446,9 +446,9 @@ void __init ltq_soc_init(void) · 445 unmodified lines
446	446
447	447	/* add our generic xway clocks */
448	448	clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
449		− clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
450	449	clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
451	450	clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
	451	+ clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
452	452	clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
453	453	clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
454	454	clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
@@ -462,10 +462,8 @@ void __init ltq_soc_init(void) · 7 unmodified lines
462	462	clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
463	463	}
464	464
465		− if (!of_machine_is_compatible("lantiq,ase")) {
466		− clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
	465	+ if (!of_machine_is_compatible("lantiq,ase"))
467	466	clkdev_add_pci();
468		− }
469	467
470	468	if (of_machine_is_compatible("lantiq,grx390") \|\|
471	469	of_machine_is_compatible("lantiq,ar10")) {

arch/mips/lasat/picvue_proc.c+1−2

@@ -197,8 +197,7 @@ static int __init pvc_proc_init(void) · 196 unmodified lines
197	197	if (proc_entry == NULL)
198	198	goto error;
199	199
200		− init_timer(&timer);
201		− timer.function = pvc_proc_timerfunc;
	200	+ setup_timer(&timer, pvc_proc_timerfunc, 0UL);
202	201
203	202	return 0;
204	203	error:

arch/mips/math-emu/cp1emu.c+24−22

@@ -810,7 +810,7 @@ do { \ · 809 unmodified lines
810	810	#define SITOREG(si, x) \
811	811	do { \
812	812	if (cop1_64bit(xcp) && !hybrid_fprs()) { \
813		− unsigned i; \
	813	+ unsigned int i; \
814	814	set_fpr32(&ctx->fpr[x], 0, si); \
815	815	for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
816	816	set_fpr32(&ctx->fpr[x], i, 0); \
@@ -823,7 +823,7 @@ do { \ · 6 unmodified lines
823	823
824	824	#define SITOHREG(si, x) \
825	825	do { \
826		− unsigned i; \
	826	+ unsigned int i; \
827	827	set_fpr32(&ctx->fpr[x], 1, si); \
828	828	for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
829	829	set_fpr32(&ctx->fpr[x], i, 0); \
@@ -834,7 +834,7 @@ do { \ · 4 unmodified lines
834	834
835	835	#define DITOREG(di, x) \
836	836	do { \
837		− unsigned fpr, i; \
	837	+ unsigned int fpr, i; \
838	838	fpr = (x) & ~(cop1_64bit(xcp) ^ 1); \
839	839	set_fpr64(&ctx->fpr[fpr], 0, di); \
840	840	for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
@@ -1465,7 +1465,7 @@ DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); · 624 unmodified lines
1465	1465	static int fpux_emu(struct pt_regs xcp, struct mips_fpu_struct ctx,
1466	1466	mips_instruction ir, void __user **fault_addr)
1467	1467	{
1468		− unsigned rcsr = 0; /* resulting csr */
	1468	+ unsigned int rcsr = 0; /* resulting csr */
1469	1469
1470	1470	MIPS_FPU_EMU_INC_STATS(cp1xops);
1471	1471
@@ -1661,10 +1661,10 @@ static int fpu_emu(struct pt_regs xcp, struct mips_fpu_struct ctx, · 189 unmodified lines
1661	1661	mips_instruction ir)
1662	1662	{
1663	1663	int rfmt; /* resulting format */
1664		− unsigned rcsr = 0; /* resulting csr */
	1664	+ unsigned int rcsr = 0; /* resulting csr */
1665	1665	unsigned int oldrm;
1666	1666	unsigned int cbit;
1667		− unsigned cond;
	1667	+ unsigned int cond;
1668	1668	union {
1669	1669	union ieee754dp d;
1670	1670	union ieee754sp s;
@@ -1795,7 +1795,7 @@ static int fpu_emu(struct pt_regs xcp, struct mips_fpu_struct ctx, · 124 unmodified lines
1795	1795	SPFROMREG(fs, MIPSInst_FS(ir));
1796	1796	SPFROMREG(fd, MIPSInst_FD(ir));
1797	1797	rv.s = ieee754sp_maddf(fd, fs, ft);
1798		− break;
	1798	+ goto copcsr;
1799	1799	}
1800	1800
1801	1801	case fmsubf_op: {
@@ -1809,7 +1809,7 @@ static int fpu_emu(struct pt_regs xcp, struct mips_fpu_struct ctx, · 7 unmodified lines
1809	1809	SPFROMREG(fs, MIPSInst_FS(ir));
1810	1810	SPFROMREG(fd, MIPSInst_FD(ir));
1811	1811	rv.s = ieee754sp_msubf(fd, fs, ft);
1812		− break;
	1812	+ goto copcsr;
1813	1813	}
1814	1814
1815	1815	case frint_op: {
@@ -1834,7 +1834,7 @@ static int fpu_emu(struct pt_regs xcp, struct mips_fpu_struct ctx, · 18 unmodified lines
1834	1834	SPFROMREG(fs, MIPSInst_FS(ir));
1835	1835	rv.w = ieee754sp_2008class(fs);
1836	1836	rfmt = w_fmt;
1837		− break;
	1837	+ goto copcsr;
1838	1838	}
1839	1839
1840	1840	case fmin_op: {
@@ -1847,7 +1847,7 @@ static int fpu_emu(struct pt_regs xcp, struct mips_fpu_struct ctx, · 6 unmodified lines
1847	1847	SPFROMREG(ft, MIPSInst_FT(ir));
1848	1848	SPFROMREG(fs, MIPSInst_FS(ir));
1849	1849	rv.s = ieee754sp_fmin(fs, ft);
1850		− break;
	1850	+ goto copcsr;
1851	1851	}
1852	1852
1853	1853	case fmina_op: {
@@ -1860,7 +1860,7 @@ static int fpu_emu(struct pt_regs xcp, struct mips_fpu_struct ctx, · 6 unmodified lines
1860	1860	SPFROMREG(ft, MIPSInst_FT(ir));
1861	1861	SPFROMREG(fs, MIPSInst_FS(ir));
1862	1862	rv.s = ieee754sp_fmina(fs, ft);
1863		− break;
	1863	+ goto copcsr;
1864	1864	}
1865	1865
1866	1866	case fmax_op: {
@@ -1873,7 +1873,7 @@ static int fpu_emu(struct pt_regs xcp, struct mips_fpu_struct ctx, · 6 unmodified lines
1873	1873	SPFROMREG(ft, MIPSInst_FT(ir));
1874	1874	SPFROMREG(fs, MIPSInst_FS(ir));
1875	1875	rv.s = ieee754sp_fmax(fs, ft);
1876		− break;
	1876	+ goto copcsr;
1877	1877	}
1878	1878
1879	1879	case fmaxa_op: {
@@ -1886,7 +1886,7 @@ static int fpu_emu(struct pt_regs xcp, struct mips_fpu_struct ctx, · 6 unmodified lines
1886	1886	SPFROMREG(ft, MIPSInst_FT(ir));
1887	1887	SPFROMREG(fs, MIPSInst_FS(ir));
1888	1888	rv.s = ieee754sp_fmaxa(fs, ft);
1889		− break;
	1889	+ goto copcsr;
1890	1890	}
1891	1891
1892	1892	case fabs_op:
@@ -2029,9 +2029,10 @@ copcsr: · 136 unmodified lines
2029	2029
2030	2030	default:
2031	2031	if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2032		− unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
	2032	+ unsigned int cmpop;
2033	2033	union ieee754sp fs, ft;
2034	2034
	2035	+ cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2035	2036	SPFROMREG(fs, MIPSInst_FS(ir));
2036	2037	SPFROMREG(ft, MIPSInst_FT(ir));
2037	2038	rv.w = ieee754sp_cmp(fs, ft,
@@ -2165,7 +2166,7 @@ copcsr: · 127 unmodified lines
2165	2166	DPFROMREG(fs, MIPSInst_FS(ir));
2166	2167	DPFROMREG(fd, MIPSInst_FD(ir));
2167	2168	rv.d = ieee754dp_maddf(fd, fs, ft);
2168		− break;
	2169	+ goto copcsr;
2169	2170	}
2170	2171
2171	2172	case fmsubf_op: {
@@ -2179,7 +2180,7 @@ copcsr: · 7 unmodified lines
2179	2180	DPFROMREG(fs, MIPSInst_FS(ir));
2180	2181	DPFROMREG(fd, MIPSInst_FD(ir));
2181	2182	rv.d = ieee754dp_msubf(fd, fs, ft);
2182		− break;
	2183	+ goto copcsr;
2183	2184	}
2184	2185
2185	2186	case frint_op: {
@@ -2204,7 +2205,7 @@ copcsr: · 18 unmodified lines
2204	2205	DPFROMREG(fs, MIPSInst_FS(ir));
2205	2206	rv.l = ieee754dp_2008class(fs);
2206	2207	rfmt = l_fmt;
2207		− break;
	2208	+ goto copcsr;
2208	2209	}
2209	2210
2210	2211	case fmin_op: {
@@ -2217,7 +2218,7 @@ copcsr: · 6 unmodified lines
2217	2218	DPFROMREG(ft, MIPSInst_FT(ir));
2218	2219	DPFROMREG(fs, MIPSInst_FS(ir));
2219	2220	rv.d = ieee754dp_fmin(fs, ft);
2220		− break;
	2221	+ goto copcsr;
2221	2222	}
2222	2223
2223	2224	case fmina_op: {
@@ -2230,7 +2231,7 @@ copcsr: · 6 unmodified lines
2230	2231	DPFROMREG(ft, MIPSInst_FT(ir));
2231	2232	DPFROMREG(fs, MIPSInst_FS(ir));
2232	2233	rv.d = ieee754dp_fmina(fs, ft);
2233		− break;
	2234	+ goto copcsr;
2234	2235	}
2235	2236
2236	2237	case fmax_op: {
@@ -2243,7 +2244,7 @@ copcsr: · 6 unmodified lines
2243	2244	DPFROMREG(ft, MIPSInst_FT(ir));
2244	2245	DPFROMREG(fs, MIPSInst_FS(ir));
2245	2246	rv.d = ieee754dp_fmax(fs, ft);
2246		− break;
	2247	+ goto copcsr;
2247	2248	}
2248	2249
2249	2250	case fmaxa_op: {
@@ -2256,7 +2257,7 @@ copcsr: · 6 unmodified lines
2256	2257	DPFROMREG(ft, MIPSInst_FT(ir));
2257	2258	DPFROMREG(fs, MIPSInst_FS(ir));
2258	2259	rv.d = ieee754dp_fmaxa(fs, ft);
2259		− break;
	2260	+ goto copcsr;
2260	2261	}
2261	2262
2262	2263	case fabs_op:
@@ -2379,9 +2380,10 @@ dcopuop: · 116 unmodified lines
2379	2380
2380	2381	default:
2381	2382	if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2382		− unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
	2383	+ unsigned int cmpop;
2383	2384	union ieee754dp fs, ft;
2384	2385
	2386	+ cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2385	2387	DPFROMREG(fs, MIPSInst_FS(ir));
2386	2388	DPFROMREG(ft, MIPSInst_FT(ir));
2387	2389	rv.w = ieee754dp_cmp(fs, ft,

arch/mips/math-emu/dp_maddf.c+4−4

@@ -45,10 +45,10 @@ static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x, · 44 unmodified lines
45	45	{
46	46	int re;
47	47	int rs;
48		− unsigned lxm;
49		− unsigned hxm;
50		− unsigned lym;
51		− unsigned hym;
	48	+ unsigned int lxm;
	49	+ unsigned int hxm;
	50	+ unsigned int lym;
	51	+ unsigned int hym;
52	52	u64 lrm;
53	53	u64 hrm;
54	54	u64 lzm;

arch/mips/math-emu/dp_mul.c+4−4

@@ -26,10 +26,10 @@ union ieee754dp ieee754dp_mul(union ieee754dp x, union ieee754dp y) · 25 unmodified lines
26	26	int re;
27	27	int rs;
28	28	u64 rm;
29		− unsigned lxm;
30		− unsigned hxm;
31		− unsigned lym;
32		− unsigned hym;
	29	+ unsigned int lxm;
	30	+ unsigned int hxm;
	31	+ unsigned int lym;
	32	+ unsigned int hym;
33	33	u64 lrm;
34	34	u64 hrm;
35	35	u64 t;

arch/mips/math-emu/dp_sqrt.c+2−2

@@ -21,7 +21,7 @@ · 20 unmodified lines
21	21
22	22	#include "ieee754dp.h"
23	23
24		−static const unsigned table[] = {
	24	+static const unsigned int table[] = {
25	25	0, 1204, 3062, 5746, 9193, 13348, 18162, 23592,
26	26	29598, 36145, 43202, 50740, 58733, 67158, 75992,
27	27	85215, 83599, 71378, 60428, 50647, 41945, 34246,
@@ -33,7 +33,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x) · 5 unmodified lines
33	33	{
34	34	struct _ieee754_csr oldcsr;
35	35	union ieee754dp y, z, t;
36		− unsigned scalx, yh;
	36	+ unsigned int scalx, yh;
37	37	COMPXDP;
38	38
39	39	EXPLODEXDP;

arch/mips/math-emu/ieee754.h+8−7

@@ -165,11 +165,12 @@ struct _ieee754_csr { · 164 unmodified lines
165	165	};
166	166	#define ieee754_csr ((struct _ieee754_csr )(&current->thread.fpu.fcr31))
167	167
168		−static inline unsigned ieee754_getrm(void)
	168	+static inline unsigned int ieee754_getrm(void)
169	169	{
170	170	return (ieee754_csr.rm);
171	171	}
172		−static inline unsigned ieee754_setrm(unsigned rm)
	172	+
	173	+static inline unsigned int ieee754_setrm(unsigned int rm)
173	174	{
174	175	return (ieee754_csr.rm = rm);
175	176	}
@@ -177,14 +178,14 @@ static inline unsigned ieee754_setrm(unsigned rm) · 1 unmodified line
177	178	/*
178	179	* get current exceptions
179	180	*/
180		−static inline unsigned ieee754_getcx(void)
	181	+static inline unsigned int ieee754_getcx(void)
181	182	{
182	183	return (ieee754_csr.cx);
183	184	}
184	185
185	186	/* test for current exception condition
186	187	*/
187		−static inline int ieee754_cxtest(unsigned n)
	188	+static inline int ieee754_cxtest(unsigned int n)
188	189	{
189	190	return (ieee754_csr.cx & n);
190	191	}
@@ -192,21 +193,21 @@ static inline int ieee754_cxtest(unsigned n) · 1 unmodified line
192	193	/*
193	194	* get sticky exceptions
194	195	*/
195		−static inline unsigned ieee754_getsx(void)
	196	+static inline unsigned int ieee754_getsx(void)
196	197	{
197	198	return (ieee754_csr.sx);
198	199	}
199	200
200	201	/* clear sticky conditions
201	202	*/
202		−static inline unsigned ieee754_clrsx(void)
	203	+static inline unsigned int ieee754_clrsx(void)
203	204	{
204	205	return (ieee754_csr.sx = 0);
205	206	}
206	207
207	208	/* test for sticky exception condition
208	209	*/
209		−static inline int ieee754_sxtest(unsigned n)
	210	+static inline int ieee754_sxtest(unsigned int n)
210	211	{
211	212	return (ieee754_csr.sx & n);
212	213	}

arch/mips/math-emu/ieee754int.h+3−3

@@ -54,13 +54,13 @@ static inline int ieee754_class_nan(int xc) · 53 unmodified lines
54	54	}
55	55
56	56	#define COMPXSP \
57		− unsigned xm; int xe; int xs __maybe_unused; int xc
	57	+ unsigned int xm; int xe; int xs __maybe_unused; int xc
58	58
59	59	#define COMPYSP \
60		− unsigned ym; int ye; int ys; int yc
	60	+ unsigned int ym; int ye; int ys; int yc
61	61
62	62	#define COMPZSP \
63		− unsigned zm; int ze; int zs; int zc
	63	+ unsigned int zm; int ze; int zs; int zc
64	64
65	65	#define EXPLODESP(v, vc, vs, ve, vm) \
66	66	{ \

arch/mips/math-emu/ieee754sp.c+2−2

@@ -65,7 +65,7 @@ union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r) · 64 unmodified lines
65	65	return r;
66	66	}
67	67
68		−static unsigned ieee754sp_get_rounding(int sn, unsigned xm)
	68	+static unsigned int ieee754sp_get_rounding(int sn, unsigned int xm)
69	69	{
70	70	/* inexact must round of 3 bits
71	71	*/
@@ -96,7 +96,7 @@ static unsigned ieee754sp_get_rounding(int sn, unsigned xm) · 24 unmodified lines
96	96	* xe is an unbiased exponent
97	97	* xm is 3bit extended precision value.
98	98	*/
99		−union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
	99	+union ieee754sp ieee754sp_format(int sn, int xe, unsigned int xm)
100	100	{
101	101	assert(xm); /* we don't gen exact zeros (probably should) */
102	102

arch/mips/math-emu/ieee754sp.h+1−1

@@ -69,7 +69,7 @@ static inline int ieee754sp_finite(union ieee754sp x) · 68 unmodified lines
69	69	#define SPDNORMY SPDNORMx(ym, ye)
70	70	#define SPDNORMZ SPDNORMx(zm, ze)
71	71
72		−static inline union ieee754sp buildsp(int s, int bx, unsigned m)
	72	+static inline union ieee754sp buildsp(int s, int bx, unsigned int m)
73	73	{
74	74	union ieee754sp r;
75	75

arch/mips/math-emu/sp_div.c+2−2

@@ -23,9 +23,9 @@ · 22 unmodified lines
23	23
24	24	union ieee754sp ieee754sp_div(union ieee754sp x, union ieee754sp y)
25	25	{
26		− unsigned rm;
	26	+ unsigned int rm;
27	27	int re;
28		− unsigned bm;
	28	+ unsigned int bm;
29	29
30	30	COMPXSP;
31	31	COMPYSP;

arch/mips/math-emu/sp_fint.c+1−1

@@ -23,7 +23,7 @@ · 22 unmodified lines
23	23
24	24	union ieee754sp ieee754sp_fint(int x)
25	25	{
26		− unsigned xm;
	26	+ unsigned int xm;
27	27	int xe;
28	28	int xs;
29	29

arch/mips/math-emu/sp_maddf.c+3−3

@@ -20,9 +20,9 @@ static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x, · 19 unmodified lines
20	20	{
21	21	int re;
22	22	int rs;
23		− unsigned rm;
24		− uint64_t rm64;
25		− uint64_t zm64;
	23	+ unsigned int rm;
	24	+ u64 rm64;
	25	+ u64 zm64;
26	26	int s;
27	27
28	28	COMPXSP;

arch/mips/math-emu/sp_mul.c+5−5

@@ -25,15 +25,15 @@ union ieee754sp ieee754sp_mul(union ieee754sp x, union ieee754sp y) · 24 unmodified lines
25	25	{
26	26	int re;
27	27	int rs;
28		− unsigned rm;
	28	+ unsigned int rm;
29	29	unsigned short lxm;
30	30	unsigned short hxm;
31	31	unsigned short lym;
32	32	unsigned short hym;
33		− unsigned lrm;
34		− unsigned hrm;
35		− unsigned t;
36		− unsigned at;
	33	+ unsigned int lrm;
	34	+ unsigned int hrm;
	35	+ unsigned int t;
	36	+ unsigned int at;
37	37
38	38	COMPXSP;
39	39	COMPYSP;

arch/mips/mm/dma-default.c+1−1

@@ -179,7 +179,7 @@ static int mips_dma_mmap(struct device dev, struct vm_area_struct vma, · 178 unmodified lines
179	179	void *cpu_addr, dma_addr_t dma_addr, size_t size,
180	180	unsigned long attrs)
181	181	{
182		− unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
	182	+ unsigned long user_count = vma_pages(vma);
183	183	unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
184	184	unsigned long addr = (unsigned long)cpu_addr;
185	185	unsigned long off = vma->vm_pgoff;

arch/mips/mm/init.c+0−4

@@ -402,7 +402,6 @@ int page_is_ram(unsigned long pagenr) · 401 unmodified lines
402	402	void __init paging_init(void)
403	403	{
404	404	unsigned long max_zone_pfns[MAX_NR_ZONES];
405		− unsigned long lastpfn __maybe_unused;
406	405
407	406	pagetable_init();
408	407
@@ -416,17 +415,14 @@ void __init paging_init(void) · 7 unmodified lines
416	415	max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
417	416	#endif
418	417	max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
419		− lastpfn = max_low_pfn;
420	418	#ifdef CONFIG_HIGHMEM
421	419	max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
422		− lastpfn = highend_pfn;
423	420
424	421	if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
425	422	printk(KERN_WARNING "This processor doesn't support highmem."
426	423	" %ldk highmem ignored\n",
427	424	(highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
428	425	max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
429		− lastpfn = max_low_pfn;
430	426	}
431	427	#endif
432	428

arch/mips/pci/pci-mt7620.c+7−8

@@ -33,14 +33,13 @@ · 32 unmodified lines
33	33	#define RALINK_GPIOMODE 0x60
34	34
35	35	#define PPLL_CFG1 0x9c
36		−#define PDRV_SW_SET BIT(23)
37	36
38	37	#define PPLL_DRV 0xa0
39		−#define PDRV_SW_SET (1<<31)
40		−#define LC_CKDRVPD (1<<19)
41		−#define LC_CKDRVOHZ (1<<18)
42		−#define LC_CKDRVHZ (1<<17)
43		−#define LC_CKTEST (1<<16)
	38	+#define PDRV_SW_SET BIT(31)
	39	+#define LC_CKDRVPD BIT(19)
	40	+#define LC_CKDRVOHZ BIT(18)
	41	+#define LC_CKDRVHZ BIT(17)
	42	+#define LC_CKTEST BIT(16)
44	43
45	44	/* PCI Bridge registers */
46	45	#define RALINK_PCI_PCICFG_ADDR 0x00
@@ -66,7 +65,7 @@ · 19 unmodified lines
66	65	#define PCIEPHY0_CFG 0x90
67	66
68	67	#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
69		−#define RALINK_PCIE0_CLK_EN (1 << 26)
	68	+#define RALINK_PCIE0_CLK_EN BIT(26)
70	69
71	70	#define BUSY 0x80000000
72	71	#define WAITRETRY_MAX 10
@@ -121,7 +120,7 @@ static int wait_pciephy_busy(void) · 48 unmodified lines
121	120	else
122	121	break;
123	122	if (retry++ > WAITRETRY_MAX) {
124		− printk(KERN_WARN "PCIE-PHY retry failed.\n");
	123	+ pr_warn("PCIE-PHY retry failed.\n");
125	124	return -1;
126	125	}
127	126	}

arch/mips/pci/pcie-octeon.c+6−6

@@ -639,7 +639,7 @@ static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port) · 638 unmodified lines
639	639	cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
640	640	return -1;
641	641	}
642		− cvmx_wait(10000);
	642	+ __delay(10000);
643	643	pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
644	644	} while (pciercx_cfg032.s.dlla == 0);
645	645
@@ -821,7 +821,7 @@ retry: · 175 unmodified lines
821	821	* don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
822	822	* fixed number of cycles.
823	823	*/
824		− cvmx_wait(400000);
	824	+ __delay(400000);
825	825
826	826	/*
827	827	* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
@@ -1018,7 +1018,7 @@ retry: · 190 unmodified lines
1018	1018	i = in_p_offset;
1019	1019	while (i--) {
1020	1020	cvmx_write64_uint32(write_address, 0);
1021		− cvmx_wait(10000);
	1021	+ __delay(10000);
1022	1022	}
1023	1023
1024	1024	/*
@@ -1034,7 +1034,7 @@ retry: · 9 unmodified lines
1034	1034	dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1035	1035	old_in_fif_p_count = dbg_data.s.data & 0xff;
1036	1036	cvmx_write64_uint32(write_address, 0);
1037		− cvmx_wait(10000);
	1037	+ __delay(10000);
1038	1038	dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1039	1039	in_fif_p_count = dbg_data.s.data & 0xff;
1040	1040	} while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
@@ -1053,7 +1053,7 @@ retry: · 12 unmodified lines
1053	1053	cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
1054	1054	while (in_fif_p_count != 0) {
1055	1055	cvmx_write64_uint32(write_address, 0);
1056		− cvmx_wait(10000);
	1056	+ __delay(10000);
1057	1057	in_fif_p_count = (in_fif_p_count + 1) & 0xff;
1058	1058	}
1059	1059	/*
@@ -1105,7 +1105,7 @@ static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port) · 45 unmodified lines
1105	1105	do {
1106	1106	if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
1107	1107	return -1;
1108		− cvmx_wait(10000);
	1108	+ __delay(10000);
1109	1109	pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1110	1110	} while ((pciercx_cfg032.s.dlla == 0) \|\| (pciercx_cfg032.s.lt == 1));
1111	1111

arch/mips/ralink/Kconfig+0−1

@@ -31,7 +31,6 @@ choice · 30 unmodified lines
31	31
32	32	config SOC_RT305X
33	33	bool "RT305x"
34		− select USB_ARCH_HAS_HCD
35	34
36	35	config SOC_RT3883
37	36	bool "RT3883"

arch/mips/ralink/mt7620.c+2−2

@@ -145,8 +145,8 @@ static struct rt2880_pmx_func i2c_grp_mt7628[] = { · 144 unmodified lines
145	145	FUNC("i2c", 0, 4, 2),
146	146	};
147	147
148		−static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
149		−static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
	148	+static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("refclk", 0, 37, 1) };
	149	+static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 36, 1) };
150	150	static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) };
151	151	static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
152	152

arch/mips/xilfpga/Kconfig+0−10

@@ -1,10 +0,0 @@
1		−# SPDX-License-Identifier: GPL-2.0
2		−choice
3		− prompt "Machine type"
4		− depends on MACH_XILFPGA
5		− default XILFPGA_NEXYS4DDR
6		−
7		−config XILFPGA_NEXYS4DDR
8		− bool "Nexys4DDR by Digilent"
9		−
10		−endchoice

arch/mips/xilfpga/Makefile+0−7

@@ -1,7 +0,0 @@
1		−#
2		−# Makefile for the Xilfpga
3		−#
4		−
5		−obj-y += init.o
6		−obj-y += intc.o
7		−obj-y += time.o

arch/mips/xilfpga/Platform+0−3

@@ -1,3 +0,0 @@
1		−platform-$(CONFIG_MACH_XILFPGA) += xilfpga/
2		−cflags-$(CONFIG_MACH_XILFPGA) += -I$(srctree)/arch/mips/include/asm/mach-xilfpga
3		−load-$(CONFIG_MACH_XILFPGA) += 0xffffffff80100000

arch/mips/xilfpga/init.c+0−44

@@ -1,44 +0,0 @@
1		−/*
2		− * Xilfpga platform setup
3		− *
4		− * Copyright (C) 2015 Imagination Technologies
5		− * Author: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
6		− *
7		− * This program is free software; you can redistribute it and/or modify it
8		− * under the terms and conditions of the GNU General Public License,
9		− * version 2, as published by the Free Software Foundation.
10		− */
11		−
12		−#include <linux/of_fdt.h>
13		−
14		−#include <asm/prom.h>
15		−
16		−#define XILFPGA_UART_BASE 0xb0401000
17		−
18		−const char *get_system_type(void)
19		−{
20		− return "MIPSfpga";
21		−}
22		−
23		−void __init plat_mem_setup(void)
24		−{
25		− __dt_setup_arch(__dtb_start);
26		− strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
27		−}
28		−
29		−void __init prom_init(void)
30		−{
31		− setup_8250_early_printk_port(XILFPGA_UART_BASE, 2, 50000);
32		−}
33		−
34		−void __init prom_free_prom_memory(void)
35		−{
36		−}
37		−
38		−void __init device_tree_init(void)
39		−{
40		− if (!initial_boot_params)
41		− return;
42		−
43		− unflatten_and_copy_device_tree();
44		−}

arch/mips/xilfpga/intc.c+0−22

@@ -1,22 +0,0 @@
1		−/*
2		− * Xilfpga interrupt controller setup
3		− *
4		− * Copyright (C) 2015 Imagination Technologies
5		− * Author: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
6		− *
7		− * This program is free software; you can redistribute it and/or modify it
8		− * under the terms and conditions of the GNU General Public License,
9		− * version 2, as published by the Free Software Foundation.
10		− */
11		−
12		−#include <linux/of.h>
13		−#include <linux/of_irq.h>
14		−#include <linux/irqchip.h>
15		−
16		−#include <asm/irq_cpu.h>
17		−
18		−
19		−void __init arch_init_irq(void)
20		−{
21		− irqchip_init();
22		−}

arch/mips/xilfpga/time.c+0−41

@@ -1,41 +0,0 @@
1		−/*
2		− * Xilfpga clocksource/timer setup
3		− *
4		− * Copyright (C) 2015 Imagination Technologies
5		− * Author: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
6		− *
7		− * This program is free software; you can redistribute it and/or modify it
8		− * under the terms and conditions of the GNU General Public License,
9		− * version 2, as published by the Free Software Foundation.
10		− */
11		−
12		−#include <linux/clk.h>
13		−#include <linux/clk-provider.h>
14		−#include <linux/clocksource.h>
15		−#include <linux/of.h>
16		−
17		−#include <asm/time.h>
18		−
19		−void __init plat_time_init(void)
20		−{
21		− struct device_node *np;
22		− struct clk *clk;
23		−
24		− of_clk_init(NULL);
25		− timer_probe();
26		−
27		− np = of_get_cpu_node(0, NULL);
28		− if (!np) {
29		− pr_err("Failed to get CPU node\n");
30		− return;
31		− }
32		−
33		− clk = of_clk_get(np, 0);
34		− if (IS_ERR(clk)) {
35		− pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
36		− return;
37		− }
38		−
39		− mips_hpt_frequency = clk_get_rate(clk) / 2;
40		− clk_put(clk);
41		−}

drivers/tty/serial/bcm63xx_uart.c+4−2

@@ -843,8 +843,10 @@ static int bcm_uart_probe(struct platform_device *pdev) · 842 unmodified lines
843	843	if (!res_irq)
844	844	return -ENODEV;
845	845
846		− clk = pdev->dev.of_node ? of_clk_get(pdev->dev.of_node, 0) :
847		− clk_get(&pdev->dev, "periph");
	846	+ clk = clk_get(&pdev->dev, "refclk");
	847	+ if (IS_ERR(clk) && pdev->dev.of_node)
	848	+ clk = of_clk_get(pdev->dev.of_node, 0);
	849	+
848	850	if (IS_ERR(clk))
849	851	return -ENODEV;
850	852

drivers/watchdog/Kconfig+1−1

@@ -1460,7 +1460,7 @@ config INDYDOG · 1459 unmodified lines
1460	1460
1461	1461	config JZ4740_WDT
1462	1462	tristate "Ingenic jz4740 SoC hardware watchdog"
1463		− depends on MACH_JZ4740
	1463	+ depends on MACH_JZ4740 \|\| MACH_JZ4780
1464	1464	select WATCHDOG_CORE
1465	1465	help
1466	1466	Hardware driver for the built-in watchdog timer on Ingenic jz4740 SoCs.