We only set a few bits in the ADPA register, which we then read back in the enable/disable hooks. So we can just move that bit of state computation code to the place where we need it since setting these bits without enabling the CRT encoder has no effects. The only exceptions are the hotplug bits since they affect the hotplug detection logic, but we already set those in the ->reset function and then never touch them.
Unified · Split
| @@ -144,28 +144,49 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) · 143 unmodified lines | |||
| 144 | struct drm_device *dev = encoder->base.dev; | 144 | struct drm_device *dev = encoder->base.dev; |
| 145 | struct drm_i915_private *dev_priv = dev->dev_private; | 145 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 146 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | 146 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
| 147 | u32 temp; | 147 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 148 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | ||
| 149 | u32 adpa; | ||
| 150 | |||
| 151 | if (INTEL_INFO(dev)->gen >= 5) | ||
| 152 | adpa = ADPA_HOTPLUG_BITS; | ||
| 153 | else | ||
| 154 | adpa = 0; | ||
| 148 | 155 | ||
| 149 | temp = I915_READ(crt->adpa_reg); | 156 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 150 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); | 157 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
| 151 | temp &= ~ADPA_DAC_ENABLE; | 158 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 159 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | ||
| 160 | |||
| 161 | /* For CPT allow 3 pipe config, for others just use A or B */ | ||
| 162 | if (HAS_PCH_LPT(dev)) | ||
| 163 | ; /* Those bits don't exist here */ | ||
| 164 | else if (HAS_PCH_CPT(dev)) | ||
| 165 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); | ||
| 166 | else if (crtc->pipe == 0) | ||
| 167 | adpa |= ADPA_PIPE_A_SELECT; | ||
| 168 | else | ||
| 169 | adpa |= ADPA_PIPE_B_SELECT; | ||
| 170 | |||
| 171 | if (!HAS_PCH_SPLIT(dev)) | ||
| 172 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | ||
| 152 | 173 | ||
| 153 | switch (mode) { | 174 | switch (mode) { |
| 154 | case DRM_MODE_DPMS_ON: | 175 | case DRM_MODE_DPMS_ON: |
| 155 | temp |= ADPA_DAC_ENABLE; | 176 | adpa |= ADPA_DAC_ENABLE; |
| 156 | break; | 177 | break; |
| 157 | case DRM_MODE_DPMS_STANDBY: | 178 | case DRM_MODE_DPMS_STANDBY: |
| 158 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; | 179 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
| 159 | break; | 180 | break; |
| 160 | case DRM_MODE_DPMS_SUSPEND: | 181 | case DRM_MODE_DPMS_SUSPEND: |
| 161 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; | 182 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
| 162 | break; | 183 | break; |
| 163 | case DRM_MODE_DPMS_OFF: | 184 | case DRM_MODE_DPMS_OFF: |
| 164 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; | 185 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
| 165 | break; | 186 | break; |
| 166 | } | 187 | } |
| 167 | 188 | ||
| 168 | I915_WRITE(crt->adpa_reg, temp); | 189 | I915_WRITE(crt->adpa_reg, adpa); |
| 169 | } | 190 | } |
| 170 | 191 | ||
| 171 | static void intel_disable_crt(struct intel_encoder *encoder) | 192 | static void intel_disable_crt(struct intel_encoder *encoder) |
| @@ -274,42 +295,6 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder, · 102 unmodified lines | |||
| 274 | return true; | 295 | return true; |
| 275 | } | 296 | } |
| 276 | 297 | ||
| 277 | static void intel_crt_mode_set(struct intel_encoder *encoder) | ||
| 278 | { | ||
| 279 | |||
| 280 | struct drm_device *dev = encoder->base.dev; | ||
| 281 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | ||
| 282 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | ||
| 283 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
| 284 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | ||
| 285 | u32 adpa; | ||
| 286 | |||
| 287 | if (INTEL_INFO(dev)->gen >= 5) | ||
| 288 | adpa = ADPA_HOTPLUG_BITS; | ||
| 289 | else | ||
| 290 | adpa = 0; | ||
| 291 | |||
| 292 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | ||
| 293 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | ||
| 294 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | ||
| 295 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | ||
| 296 | |||
| 297 | /* For CPT allow 3 pipe config, for others just use A or B */ | ||
| 298 | if (HAS_PCH_LPT(dev)) | ||
| 299 | ; /* Those bits don't exist here */ | ||
| 300 | else if (HAS_PCH_CPT(dev)) | ||
| 301 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); | ||
| 302 | else if (crtc->pipe == 0) | ||
| 303 | adpa |= ADPA_PIPE_A_SELECT; | ||
| 304 | else | ||
| 305 | adpa |= ADPA_PIPE_B_SELECT; | ||
| 306 | |||
| 307 | if (!HAS_PCH_SPLIT(dev)) | ||
| 308 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | ||
| 309 | |||
| 310 | I915_WRITE(crt->adpa_reg, adpa); | ||
| 311 | } | ||
| 312 | |||
| 313 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) | 298 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
| 314 | { | 299 | { |
| 315 | struct drm_device *dev = connector->dev; | 300 | struct drm_device *dev = connector->dev; |
| @@ -867,7 +852,6 @@ void intel_crt_init(struct drm_device *dev) · 551 unmodified lines | |||
| 867 | crt->adpa_reg = ADPA; | 852 | crt->adpa_reg = ADPA; |
| 868 | 853 | ||
| 869 | crt->base.compute_config = intel_crt_compute_config; | 854 | crt->base.compute_config = intel_crt_compute_config; |
| 870 | crt->base.mode_set = intel_crt_mode_set; | ||
| 871 | crt->base.disable = intel_disable_crt; | 855 | crt->base.disable = intel_disable_crt; |
| 872 | crt->base.enable = intel_enable_crt; | 856 | crt->base.enable = intel_enable_crt; |
| 873 | if (I915_HAS_HOTPLUG(dev)) | 857 | if (I915_HAS_HOTPLUG(dev)) |