History

Merge branch 'drm-fixes-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

- OD fixes for powerplay - Vega20 fixes - KFD fix for Kaveri - add missing firmware declaration for hainan (SI chip) - Fix DC user experience regressions related to panels that support >8 bpc

Dave Airlie committed 7 years ago

Commit 8cf6f362 parents 1d74f13 a5d0f4511 files · +115 −56Browse files

Unified · Split

11 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +5 −2
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +7 −0
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +2 −0
  4. drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +1 −0
  5. drivers/gpu/drm/amd/amdgpu/soc15.c +32 −7
  6. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +16 −0
  7. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +1 −0
  8. drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +10 −10
  9. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +10 −15
  10. drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +10 −13
  11. drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +21 −9
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c+5−2
@@ -501,8 +501,11 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) · 500 unmodified lines
501501 {
502502 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
503503
504− amdgpu_dpm_switch_power_profile(adev,
505− PP_SMC_POWER_PROFILE_COMPUTE, !idle);
504+ if (adev->powerplay.pp_funcs &&
505+ adev->powerplay.pp_funcs->switch_power_profile)
506+ amdgpu_dpm_switch_power_profile(adev,
507+ PP_SMC_POWER_PROFILE_COMPUTE,
508+ !idle);
506509 }
507510
508511 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c+7−0
@@ -626,6 +626,13 @@ int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) · 625 unmodified lines
626626 "dither",
627627 amdgpu_dither_enum_list, sz);
628628
629+ if (amdgpu_device_has_dc_support(adev)) {
630+ adev->mode_info.max_bpc_property =
631+ drm_property_create_range(adev->ddev, 0, "max bpc", 8, 16);
632+ if (!adev->mode_info.max_bpc_property)
633+ return -ENOMEM;
634+ }
635+
629636 return 0;
630637 }
631638
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h+2−0
@@ -339,6 +339,8 @@ struct amdgpu_mode_info { · 338 unmodified lines
339339 struct drm_property *audio_property;
340340 /* FMT dithering */
341341 struct drm_property *dither_property;
342+ /* maximum number of bits per channel for monitor color */
343+ struct drm_property *max_bpc_property;
342344 /* hardcoded DFP edid from BIOS */
343345 struct edid *bios_hardcoded_edid;
344346 int bios_hardcoded_edid_size;
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c+1−0
@@ -46,6 +46,7 @@ MODULE_FIRMWARE("amdgpu/tahiti_mc.bin"); · 45 unmodified lines
4646 MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
4747 MODULE_FIRMWARE("amdgpu/verde_mc.bin");
4848 MODULE_FIRMWARE("amdgpu/oland_mc.bin");
49+MODULE_FIRMWARE("amdgpu/hainan_mc.bin");
4950 MODULE_FIRMWARE("amdgpu/si58_mc.bin");
5051
5152 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
drivers/gpu/drm/amd/amdgpu/soc15.c+32−7
@@ -65,6 +65,13 @@ · 64 unmodified lines
6565 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
6666 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
6767
68+/* for Vega20 register name change */
69+#define mmHDP_MEM_POWER_CTRL 0x00d4
70+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
71+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
72+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
73+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
74+#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
6875 /*
6976 * Indirect registers accessor
7077 */
@@ -870,15 +877,33 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable · 799 unmodified lines
870877 {
871878 uint32_t def, data;
872879
873− def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
880+ if (adev->asic_type == CHIP_VEGA20) {
881+ def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
874882
875− if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
876− data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
877− else
878− data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
883+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
884+ data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
885+ HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
886+ HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
887+ HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
888+ else
889+ data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
890+ HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
891+ HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
892+ HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
879893
880− if (def != data)
881− WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
894+ if (def != data)
895+ WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
896+ } else {
897+ def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
898+
899+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
900+ data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
901+ else
902+ data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
903+
904+ if (def != data)
905+ WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
906+ }
882907 }
883908
884909 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+16−0
@@ -2358,8 +2358,15 @@ static void update_stream_scaling_settings(const struct drm_display_mode *mode, · 2357 unmodified lines
23582358 static enum dc_color_depth
23592359 convert_color_depth_from_display_info(const struct drm_connector *connector)
23602360 {
2361+ struct dm_connector_state *dm_conn_state =
2362+ to_dm_connector_state(connector->state);
23612363 uint32_t bpc = connector->display_info.bpc;
23622364
2365+ /* TODO: Remove this when there's support for max_bpc in drm */
2366+ if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2367+ /* Round down to nearest even number. */
2368+ bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2369+
23632370 switch (bpc) {
23642371 case 0:
23652372 /*
@@ -2943,6 +2950,9 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, · 577 unmodified lines
29432950 } else if (property == adev->mode_info.underscan_property) {
29442951 dm_new_state->underscan_enable = val;
29452952 ret = 0;
2953+ } else if (property == adev->mode_info.max_bpc_property) {
2954+ dm_new_state->max_bpc = val;
2955+ ret = 0;
29462956 }
29472957
29482958 return ret;
@@ -2985,6 +2995,9 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, · 36 unmodified lines
29852995 } else if (property == adev->mode_info.underscan_property) {
29862996 *val = dm_state->underscan_enable;
29872997 ret = 0;
2998+ } else if (property == adev->mode_info.max_bpc_property) {
2999+ *val = dm_state->max_bpc;
3000+ ret = 0;
29883001 }
29893002 return ret;
29903003 }
@@ -3795,6 +3808,9 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, · 804 unmodified lines
37953808 drm_object_attach_property(&aconnector->base.base,
37963809 adev->mode_info.underscan_vborder_property,
37973810 0);
3811+ drm_object_attach_property(&aconnector->base.base,
3812+ adev->mode_info.max_bpc_property,
3813+ 0);
37983814
37993815 }
38003816
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h+1−0
@@ -204,6 +204,7 @@ struct dm_connector_state { · 203 unmodified lines
204204 enum amdgpu_rmx_type scaling;
205205 uint8_t underscan_vborder;
206206 uint8_t underscan_hborder;
207+ uint8_t max_bpc;
207208 bool underscan_enable;
208209 bool freesync_enable;
209210 bool freesync_capable;
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c+10−10
@@ -4525,12 +4525,12 @@ static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr) · 4524 unmodified lines
45254525 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
45264526 struct smu7_single_dpm_table *golden_sclk_table =
45274527 &(data->golden_dpm_table.sclk_table);
4528− int value;
4528+ int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
4529+ int golden_value = golden_sclk_table->dpm_levels
4530+ [golden_sclk_table->count - 1].value;
45294531
4530− value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4531− golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
4532− 100 /
4533− golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4532+ value -= golden_value;
4533+ value = DIV_ROUND_UP(value * 100, golden_value);
45344534
45354535 return value;
45364536 }
@@ -4567,12 +4567,12 @@ static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr) · 30 unmodified lines
45674567 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
45684568 struct smu7_single_dpm_table *golden_mclk_table =
45694569 &(data->golden_dpm_table.mclk_table);
4570− int value;
4570+ int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
4571+ int golden_value = golden_mclk_table->dpm_levels
4572+ [golden_mclk_table->count - 1].value;
45714573
4572− value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
4573− golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
4574− 100 /
4575− golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4574+ value -= golden_value;
4575+ value = DIV_ROUND_UP(value * 100, golden_value);
45764576
45774577 return value;
45784578 }
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c+10−15
@@ -4522,15 +4522,13 @@ static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) · 4521 unmodified lines
45224522 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
45234523 struct vega10_single_dpm_table *golden_sclk_table =
45244524 &(data->golden_dpm_table.gfx_table);
4525− int value;
4526−
4527− value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4528− golden_sclk_table->dpm_levels
4529− [golden_sclk_table->count - 1].value) *
4530− 100 /
4531− golden_sclk_table->dpm_levels
4525+ int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
4526+ int golden_value = golden_sclk_table->dpm_levels
45324527 [golden_sclk_table->count - 1].value;
45334528
4529+ value -= golden_value;
4530+ value = DIV_ROUND_UP(value * 100, golden_value);
4531+
45344532 return value;
45354533 }
45364534
@@ -4575,16 +4573,13 @@ static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr) · 38 unmodified lines
45754573 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
45764574 struct vega10_single_dpm_table *golden_mclk_table =
45774575 &(data->golden_dpm_table.mem_table);
4578− int value;
4579−
4580− value = (mclk_table->dpm_levels
4581− [mclk_table->count - 1].value -
4582− golden_mclk_table->dpm_levels
4583− [golden_mclk_table->count - 1].value) *
4584− 100 /
4585− golden_mclk_table->dpm_levels
4576+ int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
4577+ int golden_value = golden_mclk_table->dpm_levels
45864578 [golden_mclk_table->count - 1].value;
45874579
4580+ value -= golden_value;
4581+ value = DIV_ROUND_UP(value * 100, golden_value);
4582+
45884583 return value;
45894584 }
45904585
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c+10−13
@@ -2243,12 +2243,12 @@ static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr) · 2242 unmodified lines
22432243 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
22442244 struct vega12_single_dpm_table *golden_sclk_table =
22452245 &(data->golden_dpm_table.gfx_table);
2246− int value;
2246+ int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
2247+ int golden_value = golden_sclk_table->dpm_levels
2248+ [golden_sclk_table->count - 1].value;
22472249
2248− value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
2249− golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
2250− 100 /
2251− golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
2250+ value -= golden_value;
2251+ value = DIV_ROUND_UP(value * 100, golden_value);
22522252
22532253 return value;
22542254 }
@@ -2264,16 +2264,13 @@ static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr) · 9 unmodified lines
22642264 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
22652265 struct vega12_single_dpm_table *golden_mclk_table =
22662266 &(data->golden_dpm_table.mem_table);
2267− int value;
2268−
2269− value = (mclk_table->dpm_levels
2270− [mclk_table->count - 1].value -
2271− golden_mclk_table->dpm_levels
2272− [golden_mclk_table->count - 1].value) *
2273− 100 /
2274− golden_mclk_table->dpm_levels
2267+ int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
2268+ int golden_value = golden_mclk_table->dpm_levels
22752269 [golden_mclk_table->count - 1].value;
22762270
2271+ value -= golden_value;
2272+ value = DIV_ROUND_UP(value * 100, golden_value);
2273+
22772274 return value;
22782275 }
22792276
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c+21−9
@@ -75,7 +75,17 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr) · 74 unmodified lines
7575 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
7676 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
7777
78− data->registry_data.disallowed_features = 0x0;
78+ /*
79+ * Disable the following features for now:
80+ * GFXCLK DS
81+ * SOCLK DS
82+ * LCLK DS
83+ * DCEFCLK DS
84+ * FCLK DS
85+ * MP1CLK DS
86+ * MP0CLK DS
87+ */
88+ data->registry_data.disallowed_features = 0xE0041C00;
7989 data->registry_data.od_state_in_dc_support = 0;
8090 data->registry_data.thermal_support = 1;
8191 data->registry_data.skip_baco_hardware = 0;
@@ -1313,12 +1323,13 @@ static int vega20_get_sclk_od( · 1231 unmodified lines
13131323 &(data->dpm_table.gfx_table);
13141324 struct vega20_single_dpm_table *golden_sclk_table =
13151325 &(data->golden_dpm_table.gfx_table);
1316− int value;
1326+ int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1327+ int golden_value = golden_sclk_table->dpm_levels
1328+ [golden_sclk_table->count - 1].value;
13171329
13181330 /* od percentage */
1319− value = DIV_ROUND_UP((sclk_table->dpm_levels[sclk_table->count - 1].value -
1320− golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * 100,
1321− golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value);
1331+ value -= golden_value;
1332+ value = DIV_ROUND_UP(value * 100, golden_value);
13221333
13231334 return value;
13241335 }
@@ -1358,12 +1369,13 @@ static int vega20_get_mclk_od( · 33 unmodified lines
13581369 &(data->dpm_table.mem_table);
13591370 struct vega20_single_dpm_table *golden_mclk_table =
13601371 &(data->golden_dpm_table.mem_table);
1361− int value;
1372+ int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1373+ int golden_value = golden_mclk_table->dpm_levels
1374+ [golden_mclk_table->count - 1].value;
13621375
13631376 /* od percentage */
1364− value = DIV_ROUND_UP((mclk_table->dpm_levels[mclk_table->count - 1].value -
1365− golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * 100,
1366− golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value);
1377+ value -= golden_value;
1378+ value = DIV_ROUND_UP(value * 100, golden_value);
13671379
13681380 return value;
13691381 }

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