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| @@ -1540,9 +1540,6 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 1539 unmodified lines | ||
| 1540 | 1540 | #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 |
| 1541 | 1541 | #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 |
| 1542 | 1542 | |
| 1543 | −#define AMD_FMT_MOD_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 | |
| 1544 | −#define AMD_FMT_MOD_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ | |
| 1545 | − | |
| 1546 | 1543 | /* |
| 1547 | 1544 | * DCC supports embedding some clear colors directly in the DCC surface. |
| 1548 | 1545 | * However, on older GPUs the rendering HW ignores the embedded clear color |