Exynos DRM IPP subsystem is in fact non-functional and frankly speaking dead-code. This patch clearly marks that Exynos DRM IPP subsystem is broken and never really functional. It will be replaced by a completely rewritten API. Exynos DRM IPP user-space API can be obsoleted for the following reasons: 1. Exynos DRM IPP user-space API can be optional in Exynos DRM, so userspace should not rely that it is always available and should have a software fallback in case it is not there. 2. The only mode which was initially semi-working was memory-to-memory image processing. The remaining modes (LCD-"writeback" and "output") were never operational due to missing code (both in mainline and even vendor kernels). 3. Exynos DRM IPP mainline user-space API compatibility for memory-to-memory got broken very early by commit 083500baefd5 ("drm: remove DRM_FORMAT_NV12MT", which removed the support for tiled formats, the main feature which made this API somehow useful on Exynos platforms (video codec that time produced only tiled frames, to implement xvideo or any other video overlay, one has to de-tile them for proper display). 4. Broken drivers. Especially once support for IOMMU has been added, it revealed that drivers don't configure DMA operations properly and in many cases operate outside the provided buffers trashing memory around. 5. Need for external patches. Although IPP user-space API has been used in some vendor kernels, but in such cases there were additional patches applied (like reverting mentioned 083500baefd5 patch) what means that those userspace apps which might use it, still won't work with the mainline kernel version. We don't have time machines, so we cannot change it, but Exynos DRM IPP extension should never have been merged to mainline in that form. Exynos IPP subsystem and user-space API will be rewritten, so remove current IPP core code and mark existing drivers as BROKEN.
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| @@ -135,172 +135,6 @@ struct drm_exynos_g2d_exec { · 134 unmodified lines | |||
| 135 | __u64 async; | 135 | __u64 async; |
| 136 | }; | 136 | }; |
| 137 | 137 | ||
| 138 | enum drm_exynos_ops_id { | ||
| 139 | EXYNOS_DRM_OPS_SRC, | ||
| 140 | EXYNOS_DRM_OPS_DST, | ||
| 141 | EXYNOS_DRM_OPS_MAX, | ||
| 142 | }; | ||
| 143 | |||
| 144 | struct drm_exynos_sz { | ||
| 145 | __u32 hsize; | ||
| 146 | __u32 vsize; | ||
| 147 | }; | ||
| 148 | |||
| 149 | struct drm_exynos_pos { | ||
| 150 | __u32 x; | ||
| 151 | __u32 y; | ||
| 152 | __u32 w; | ||
| 153 | __u32 h; | ||
| 154 | }; | ||
| 155 | |||
| 156 | enum drm_exynos_flip { | ||
| 157 | EXYNOS_DRM_FLIP_NONE = (0 << 0), | ||
| 158 | EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), | ||
| 159 | EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), | ||
| 160 | EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | | ||
| 161 | EXYNOS_DRM_FLIP_HORIZONTAL, | ||
| 162 | }; | ||
| 163 | |||
| 164 | enum drm_exynos_degree { | ||
| 165 | EXYNOS_DRM_DEGREE_0, | ||
| 166 | EXYNOS_DRM_DEGREE_90, | ||
| 167 | EXYNOS_DRM_DEGREE_180, | ||
| 168 | EXYNOS_DRM_DEGREE_270, | ||
| 169 | }; | ||
| 170 | |||
| 171 | enum drm_exynos_planer { | ||
| 172 | EXYNOS_DRM_PLANAR_Y, | ||
| 173 | EXYNOS_DRM_PLANAR_CB, | ||
| 174 | EXYNOS_DRM_PLANAR_CR, | ||
| 175 | EXYNOS_DRM_PLANAR_MAX, | ||
| 176 | }; | ||
| 177 | |||
| 178 | /** | ||
| 179 | * A structure for ipp supported property list. | ||
| 180 | * | ||
| 181 | * @version: version of this structure. | ||
| 182 | * @ipp_id: id of ipp driver. | ||
| 183 | * @count: count of ipp driver. | ||
| 184 | * @writeback: flag of writeback supporting. | ||
| 185 | * @flip: flag of flip supporting. | ||
| 186 | * @degree: flag of degree information. | ||
| 187 | * @csc: flag of csc supporting. | ||
| 188 | * @crop: flag of crop supporting. | ||
| 189 | * @scale: flag of scale supporting. | ||
| 190 | * @refresh_min: min hz of refresh. | ||
| 191 | * @refresh_max: max hz of refresh. | ||
| 192 | * @crop_min: crop min resolution. | ||
| 193 | * @crop_max: crop max resolution. | ||
| 194 | * @scale_min: scale min resolution. | ||
| 195 | * @scale_max: scale max resolution. | ||
| 196 | */ | ||
| 197 | struct drm_exynos_ipp_prop_list { | ||
| 198 | __u32 version; | ||
| 199 | __u32 ipp_id; | ||
| 200 | __u32 count; | ||
| 201 | __u32 writeback; | ||
| 202 | __u32 flip; | ||
| 203 | __u32 degree; | ||
| 204 | __u32 csc; | ||
| 205 | __u32 crop; | ||
| 206 | __u32 scale; | ||
| 207 | __u32 refresh_min; | ||
| 208 | __u32 refresh_max; | ||
| 209 | __u32 reserved; | ||
| 210 | struct drm_exynos_sz crop_min; | ||
| 211 | struct drm_exynos_sz crop_max; | ||
| 212 | struct drm_exynos_sz scale_min; | ||
| 213 | struct drm_exynos_sz scale_max; | ||
| 214 | }; | ||
| 215 | |||
| 216 | /** | ||
| 217 | * A structure for ipp config. | ||
| 218 | * | ||
| 219 | * @ops_id: property of operation directions. | ||
| 220 | * @flip: property of mirror, flip. | ||
| 221 | * @degree: property of rotation degree. | ||
| 222 | * @fmt: property of image format. | ||
| 223 | * @sz: property of image size. | ||
| 224 | * @pos: property of image position(src-cropped,dst-scaler). | ||
| 225 | */ | ||
| 226 | struct drm_exynos_ipp_config { | ||
| 227 | __u32 ops_id; | ||
| 228 | __u32 flip; | ||
| 229 | __u32 degree; | ||
| 230 | __u32 fmt; | ||
| 231 | struct drm_exynos_sz sz; | ||
| 232 | struct drm_exynos_pos pos; | ||
| 233 | }; | ||
| 234 | |||
| 235 | enum drm_exynos_ipp_cmd { | ||
| 236 | IPP_CMD_NONE, | ||
| 237 | IPP_CMD_M2M, | ||
| 238 | IPP_CMD_WB, | ||
| 239 | IPP_CMD_OUTPUT, | ||
| 240 | IPP_CMD_MAX, | ||
| 241 | }; | ||
| 242 | |||
| 243 | /** | ||
| 244 | * A structure for ipp property. | ||
| 245 | * | ||
| 246 | * @config: source, destination config. | ||
| 247 | * @cmd: definition of command. | ||
| 248 | * @ipp_id: id of ipp driver. | ||
| 249 | * @prop_id: id of property. | ||
| 250 | * @refresh_rate: refresh rate. | ||
| 251 | */ | ||
| 252 | struct drm_exynos_ipp_property { | ||
| 253 | struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; | ||
| 254 | __u32 cmd; | ||
| 255 | __u32 ipp_id; | ||
| 256 | __u32 prop_id; | ||
| 257 | __u32 refresh_rate; | ||
| 258 | }; | ||
| 259 | |||
| 260 | enum drm_exynos_ipp_buf_type { | ||
| 261 | IPP_BUF_ENQUEUE, | ||
| 262 | IPP_BUF_DEQUEUE, | ||
| 263 | }; | ||
| 264 | |||
| 265 | /** | ||
| 266 | * A structure for ipp buffer operations. | ||
| 267 | * | ||
| 268 | * @ops_id: operation directions. | ||
| 269 | * @buf_type: definition of buffer. | ||
| 270 | * @prop_id: id of property. | ||
| 271 | * @buf_id: id of buffer. | ||
| 272 | * @handle: Y, Cb, Cr each planar handle. | ||
| 273 | * @user_data: user data. | ||
| 274 | */ | ||
| 275 | struct drm_exynos_ipp_queue_buf { | ||
| 276 | __u32 ops_id; | ||
| 277 | __u32 buf_type; | ||
| 278 | __u32 prop_id; | ||
| 279 | __u32 buf_id; | ||
| 280 | __u32 handle[EXYNOS_DRM_PLANAR_MAX]; | ||
| 281 | __u32 reserved; | ||
| 282 | __u64 user_data; | ||
| 283 | }; | ||
| 284 | |||
| 285 | enum drm_exynos_ipp_ctrl { | ||
| 286 | IPP_CTRL_PLAY, | ||
| 287 | IPP_CTRL_STOP, | ||
| 288 | IPP_CTRL_PAUSE, | ||
| 289 | IPP_CTRL_RESUME, | ||
| 290 | IPP_CTRL_MAX, | ||
| 291 | }; | ||
| 292 | |||
| 293 | /** | ||
| 294 | * A structure for ipp start/stop operations. | ||
| 295 | * | ||
| 296 | * @prop_id: id of property. | ||
| 297 | * @ctrl: definition of control. | ||
| 298 | */ | ||
| 299 | struct drm_exynos_ipp_cmd_ctrl { | ||
| 300 | __u32 prop_id; | ||
| 301 | __u32 ctrl; | ||
| 302 | }; | ||
| 303 | |||
| 304 | #define DRM_EXYNOS_GEM_CREATE 0x00 | 138 | #define DRM_EXYNOS_GEM_CREATE 0x00 |
| 305 | #define DRM_EXYNOS_GEM_MAP 0x01 | 139 | #define DRM_EXYNOS_GEM_MAP 0x01 |
| 306 | /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ | 140 | /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ |
| @@ -312,11 +146,7 @@ struct drm_exynos_ipp_cmd_ctrl { · 5 unmodified lines | |||
| 312 | #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 | 146 | #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 |
| 313 | #define DRM_EXYNOS_G2D_EXEC 0x22 | 147 | #define DRM_EXYNOS_G2D_EXEC 0x22 |
| 314 | 148 | ||
| 315 | /* IPP - Image Post Processing */ | 149 | /* Reserved 0x30 ~ 0x33 for obsolete Exynos IPP ioctls */ |
| 316 | #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 | ||
| 317 | #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 | ||
| 318 | #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 | ||
| 319 | #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 | ||
| 320 | 150 | ||
| 321 | #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ | 151 | #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ |
| 322 | DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) | 152 | DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) |
| @@ -335,18 +165,8 @@ struct drm_exynos_ipp_cmd_ctrl { · 12 unmodified lines | |||
| 335 | #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ | 165 | #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ |
| 336 | DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) | 166 | DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) |
| 337 | 167 | ||
| 338 | #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ | ||
| 339 | DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) | ||
| 340 | #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ | ||
| 341 | DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) | ||
| 342 | #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \ | ||
| 343 | DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) | ||
| 344 | #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \ | ||
| 345 | DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) | ||
| 346 | |||
| 347 | /* EXYNOS specific events */ | 168 | /* EXYNOS specific events */ |
| 348 | #define DRM_EXYNOS_G2D_EVENT 0x80000000 | 169 | #define DRM_EXYNOS_G2D_EVENT 0x80000000 |
| 349 | #define DRM_EXYNOS_IPP_EVENT 0x80000001 | ||
| 350 | 170 | ||
| 351 | struct drm_exynos_g2d_event { | 171 | struct drm_exynos_g2d_event { |
| 352 | struct drm_event base; | 172 | struct drm_event base; |
| @@ -357,16 +177,6 @@ struct drm_exynos_g2d_event { · 4 unmodified lines | |||
| 357 | __u32 reserved; | 177 | __u32 reserved; |
| 358 | }; | 178 | }; |
| 359 | 179 | ||
| 360 | struct drm_exynos_ipp_event { | ||
| 361 | struct drm_event base; | ||
| 362 | __u64 user_data; | ||
| 363 | __u32 tv_sec; | ||
| 364 | __u32 tv_usec; | ||
| 365 | __u32 prop_id; | ||
| 366 | __u32 reserved; | ||
| 367 | __u32 buf_id[EXYNOS_DRM_OPS_MAX]; | ||
| 368 | }; | ||
| 369 | |||
| 370 | #if defined(__cplusplus) | 180 | #if defined(__cplusplus) |
| 371 | } | 181 | } |
| 372 | #endif | 182 | #endif |