History

Merge tag 'drm-intel-next-2018-04-13' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

First drm/i915 feature batch heading for v4.18: - drm-next backmerge to fix build (Rodrigo) - GPU documentation improvements (Kevin) - GuC and HuC refactoring, host/GuC communication, logging, fixes, and more (mostly Michal and Michał, also Jackie, Michel and Piotr) - PSR and PSR2 enabling and fixes (DK, José, Rodrigo and Chris) - Selftest updates (Chris, Daniele) - DPLL management refactoring (Lucas) - DP MST fixes (Lyude and DK) - Watermark refactoring and changes to support NV12 (Mahesh) - NV12 prep work (Chandra) - Icelake Combo PHY enablers (Manasi) - Perf OA refactoring and ICL enabling (Lionel) - ICL enabling (Oscar, Paulo, Nabendu, Mika, Kelvin, Michel) - Workarounds refactoring (Oscar) - HDCP fixes and improvements (Ramalingam, Radhakrishna) - Power management fixes (Imre) - Various display fixes (Maarten, Ville, Vidya, Jani, Gaurav) - debugfs for FIFO underrun clearing (Maarten) - Execlist improvements (Chris) - Reset improvements (Chris) - Plenty of things here and there I overlooked and/or didn't understand... (Everyone)

Dave Airlie committed 8 years ago

Commit 8eb008c2 parents 0ab3902 fadec6e87 files · +7246 −3711Browse files

Unified · Split

87 files
  1. Documentation/gpu/i915.rst +121 −20
  2. drivers/gpu/drm/i915/Kconfig.debug +13 −0
  3. drivers/gpu/drm/i915/Makefile +7 −4
  4. drivers/gpu/drm/i915/gvt/debugfs.c +1 −12
  5. drivers/gpu/drm/i915/i915_debugfs.c +193 −125
  6. drivers/gpu/drm/i915/i915_drv.c +33 −33
  7. drivers/gpu/drm/i915/i915_drv.h +39 −350
  8. drivers/gpu/drm/i915/i915_gem.c +161 −76
  9. drivers/gpu/drm/i915/i915_gem.h +7 −0
  10. drivers/gpu/drm/i915/i915_gem_batch_pool.c +6 −24
  11. drivers/gpu/drm/i915/i915_gem_batch_pool.h +5 −24
  12. drivers/gpu/drm/i915/i915_gem_context.c +9 −2
  13. drivers/gpu/drm/i915/i915_gem_execbuffer.c +29 −0
  14. drivers/gpu/drm/i915/i915_gem_stolen.c +94 −69
  15. drivers/gpu/drm/i915/i915_gpu_error.c +1 −0
  16. drivers/gpu/drm/i915/i915_gpu_error.h +362 −0
  17. drivers/gpu/drm/i915/i915_irq.c +219 −147
  18. drivers/gpu/drm/i915/i915_oa_icl.c +118 −0
  19. drivers/gpu/drm/i915/i915_oa_icl.h +34 −0
  20. drivers/gpu/drm/i915/i915_params.h +1 −1
  21. drivers/gpu/drm/i915/i915_pci.c +1 −0
  22. drivers/gpu/drm/i915/i915_perf.c +40 −29
  23. drivers/gpu/drm/i915/i915_pmu.c +3 −24
  24. drivers/gpu/drm/i915/i915_pmu.h +10 −20
  25. drivers/gpu/drm/i915/i915_reg.h +267 −377
  26. drivers/gpu/drm/i915/i915_request.c +53 −72
  27. drivers/gpu/drm/i915/i915_utils.h +2 −2
  28. drivers/gpu/drm/i915/intel_atomic.c +15 −4
  29. drivers/gpu/drm/i915/intel_bios.c +4 −13
  30. drivers/gpu/drm/i915/intel_breadcrumbs.c +13 −8
  31. drivers/gpu/drm/i915/intel_ddi.c +141 −13
  32. drivers/gpu/drm/i915/intel_device_info.c +148 −21
  33. drivers/gpu/drm/i915/intel_device_info.h +3 −1
  34. drivers/gpu/drm/i915/intel_display.c +171 −80
  35. drivers/gpu/drm/i915/intel_dp.c +4 −17
  36. drivers/gpu/drm/i915/intel_dp_mst.c +7 −1
  37. drivers/gpu/drm/i915/intel_dpio_phy.c +6 −5
  38. drivers/gpu/drm/i915/intel_dpll_mgr.c +132 −121
  39. drivers/gpu/drm/i915/intel_dpll_mgr.h +33 −23
  40. drivers/gpu/drm/i915/intel_drv.h +29 −29
  41. drivers/gpu/drm/i915/intel_engine_cs.c +105 −691
  42. drivers/gpu/drm/i915/intel_fbc.c +28 −0
  43. drivers/gpu/drm/i915/intel_fbdev.c +3 −2
  44. drivers/gpu/drm/i915/intel_frontbuffer.c +1 −1
  45. drivers/gpu/drm/i915/intel_gpu_commands.h +274 −0
  46. drivers/gpu/drm/i915/intel_guc.c +159 −52
  47. drivers/gpu/drm/i915/intel_guc.h +70 −12
  48. drivers/gpu/drm/i915/intel_guc_ads.c +4 −4
  49. drivers/gpu/drm/i915/intel_guc_ct.c +494 −51
  50. drivers/gpu/drm/i915/intel_guc_ct.h +14 −4
  51. drivers/gpu/drm/i915/intel_guc_fw.c +3 −4
  52. drivers/gpu/drm/i915/intel_guc_fwif.h +129 −28
  53. drivers/gpu/drm/i915/intel_guc_log.c +209 −335
  54. drivers/gpu/drm/i915/intel_guc_log.h +40 −19
  55. drivers/gpu/drm/i915/intel_guc_reg.h +6 −8
  56. drivers/gpu/drm/i915/intel_guc_submission.c +30 −17
  57. drivers/gpu/drm/i915/intel_hangcheck.c +6 −7
  58. drivers/gpu/drm/i915/intel_hdcp.c +132 −53
  59. drivers/gpu/drm/i915/intel_hdmi.c +16 −24
  60. drivers/gpu/drm/i915/intel_hotplug.c +3 −0
  61. drivers/gpu/drm/i915/intel_huc.c +28 −2
  62. drivers/gpu/drm/i915/intel_huc.h +7 −0
  63. drivers/gpu/drm/i915/intel_huc_fw.c +4 −4
  64. drivers/gpu/drm/i915/intel_lrc.c +178 −76
  65. drivers/gpu/drm/i915/intel_overlay.c +1 −0
  66. drivers/gpu/drm/i915/intel_pipe_crc.c +46 −7
  67. drivers/gpu/drm/i915/intel_pm.c +292 −182
  68. drivers/gpu/drm/i915/intel_psr.c +169 −158
  69. drivers/gpu/drm/i915/intel_ringbuffer.c +14 −8
  70. drivers/gpu/drm/i915/intel_ringbuffer.h +34 −9
  71. drivers/gpu/drm/i915/intel_sprite.c +6 −1
  72. drivers/gpu/drm/i915/intel_uc.c +66 −66
  73. drivers/gpu/drm/i915/intel_uc.h +2 −3
  74. drivers/gpu/drm/i915/intel_uc_fw.c +3 −10
  75. drivers/gpu/drm/i915/intel_uc_fw.h +22 −0
  76. drivers/gpu/drm/i915/intel_uncore.c +146 −22
  77. drivers/gpu/drm/i915/intel_uncore.h +1 −0
  78. drivers/gpu/drm/i915/intel_wopcm.c +275 −0
  79. drivers/gpu/drm/i915/intel_wopcm.h +31 −0
  80. drivers/gpu/drm/i915/intel_workarounds.c +856 −0
  81. drivers/gpu/drm/i915/intel_workarounds.h +17 −0
  82. drivers/gpu/drm/i915/selftests/i915_live_selftests.h +1 −0
  83. drivers/gpu/drm/i915/selftests/i915_mock_selftests.h +1 −0
  84. drivers/gpu/drm/i915/selftests/intel_engine_cs.c +58 −0
  85. drivers/gpu/drm/i915/selftests/intel_hangcheck.c +210 −104
  86. drivers/gpu/drm/i915/selftests/intel_lrc.c +507 −0
  87. include/drm/drm_dp_helper.h +10 −0
Documentation/gpu/i915.rst+121−20
@@ -58,6 +58,12 @@ Intel GVT-g Host Support(vGPU device model) · 57 unmodified lines
5858 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
5959 :internal:
6060
61+Workarounds
62+-----------
63+
64+.. kernel-doc:: drivers/gpu/drm/i915/intel_workarounds.c
65+ :doc: Hardware workarounds
66+
6167 Display Hardware Handling
6268 =========================
6369
@@ -249,6 +255,103 @@ Memory Management and Command Submission · 185 unmodified lines
249255 This sections covers all things related to the GEM implementation in the
250256 i915 driver.
251257
258+Intel GPU Basics
259+----------------
260+
261+An Intel GPU has multiple engines. There are several engine types.
262+
263+- RCS engine is for rendering 3D and performing compute, this is named
264+ `I915_EXEC_RENDER` in user space.
265+- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user
266+ space.
267+- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD`
268+ in user space
269+- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user
270+ space.
271+- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine;
272+ instead it is to be used by user space to specify a default rendering
273+ engine (for 3D) that may or may not be the same as RCS.
274+
275+The Intel GPU family is a family of integrated GPU's using Unified
276+Memory Access. For having the GPU "do work", user space will feed the
277+GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
278+or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
279+instruct the GPU to perform work (for example rendering) and that work
280+needs memory from which to read and memory to which to write. All memory
281+is encapsulated within GEM buffer objects (usually created with the ioctl
282+`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
283+to create will also list all GEM buffer objects that the batchbuffer reads
284+and/or writes. For implementation details of memory management see
285+`GEM BO Management Implementation Details`_.
286+
287+The i915 driver allows user space to create a context via the ioctl
288+`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
289+integer. Such a context should be viewed by user-space as -loosely-
290+analogous to the idea of a CPU process of an operating system. The i915
291+driver guarantees that commands issued to a fixed context are to be
292+executed so that writes of a previously issued command are seen by
293+reads of following commands. Actions issued between different contexts
294+(even if from the same file descriptor) are NOT given that guarantee
295+and the only way to synchronize across contexts (even from the same
296+file descriptor) is through the use of fences. At least as far back as
297+Gen4, also have that a context carries with it a GPU HW context;
298+the HW context is essentially (most of atleast) the state of a GPU.
299+In addition to the ordering guarantees, the kernel will restore GPU
300+state via HW context when commands are issued to a context, this saves
301+user space the need to restore (most of atleast) the GPU state at the
302+start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
303+work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
304+to identify what context to use with the command.
305+
306+The GPU has its own memory management and address space. The kernel
307+driver maintains the memory translation table for the GPU. For older
308+GPUs (i.e. those before Gen8), there is a single global such translation
309+table, a global Graphics Translation Table (GTT). For newer generation
310+GPUs each context has its own translation table, called Per-Process
311+Graphics Translation Table (PPGTT). Of important note, is that although
312+PPGTT is named per-process it is actually per context. When user space
313+submits a batchbuffer, the kernel walks the list of GEM buffer objects
314+used by the batchbuffer and guarantees that not only is the memory of
315+each such GEM buffer object resident but it is also present in the
316+(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
317+then it is given an address. Two consequences of this are: the kernel
318+needs to edit the batchbuffer submitted to write the correct value of
319+the GPU address when a GEM BO is assigned a GPU address and the kernel
320+might evict a different GEM BO from the (PP)GTT to make address room
321+for another GEM BO. Consequently, the ioctls submitting a batchbuffer
322+for execution also include a list of all locations within buffers that
323+refer to GPU-addresses so that the kernel can edit the buffer correctly.
324+This process is dubbed relocation.
325+
326+GEM BO Management Implementation Details
327+----------------------------------------
328+
329+.. kernel-doc:: drivers/gpu/drm/i915/i915_vma.h
330+ :doc: Virtual Memory Address
331+
332+Buffer Object Eviction
333+----------------------
334+
335+This section documents the interface functions for evicting buffer
336+objects to make space available in the virtual gpu address spaces. Note
337+that this is mostly orthogonal to shrinking buffer objects caches, which
338+has the goal to make main memory (shared with the gpu through the
339+unified memory architecture) available.
340+
341+.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
342+ :internal:
343+
344+Buffer Object Memory Shrinking
345+------------------------------
346+
347+This section documents the interface function for shrinking memory usage
348+of buffer object caches. Shrinking is used to make main memory
349+available. Note that this is mostly orthogonal to evicting buffer
350+objects, which has the goal to make space in gpu virtual address spaces.
351+
352+.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c
353+ :internal:
354+
252355 Batchbuffer Parsing
253356 -------------------
254357
@@ -267,6 +370,12 @@ Batchbuffer Pools · 12 unmodified lines
267370 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c
268371 :internal:
269372
373+User Batchbuffer Execution
374+--------------------------
375+
376+.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_execbuffer.c
377+ :doc: User command execution
378+
270379 Logical Rings, Logical Ring Contexts and Execlists
271380 --------------------------------------------------
272381
@@ -312,28 +421,14 @@ Object Tiling IOCTLs · 39 unmodified lines
312421 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c
313422 :doc: buffer object tiling
314423
315−Buffer Object Eviction
316−----------------------
317−
318−This section documents the interface functions for evicting buffer
319−objects to make space available in the virtual gpu address spaces. Note
320−that this is mostly orthogonal to shrinking buffer objects caches, which
321−has the goal to make main memory (shared with the gpu through the
322−unified memory architecture) available.
323−
324−.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
325− :internal:
326−
327−Buffer Object Memory Shrinking
328−------------------------------
424+WOPCM
425+=====
329426
330−This section documents the interface function for shrinking memory usage
331−of buffer object caches. Shrinking is used to make main memory
332−available. Note that this is mostly orthogonal to evicting buffer
333−objects, which has the goal to make space in gpu virtual address spaces.
427+WOPCM Layout
428+------------
334429
335−.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c
336− :internal:
430+.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c
431+ :doc: WOPCM Layout
337432
338433 GuC
339434 ===
@@ -359,6 +454,12 @@ GuC Firmware Layout · 19 unmodified lines
359454 .. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h
360455 :doc: GuC Firmware Layout
361456
457+GuC Address Space
458+-----------------
459+
460+.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c
461+ :doc: GuC Address Space
462+
362463 Tracing
363464 =======
364465
drivers/gpu/drm/i915/Kconfig.debug+13−0
@@ -25,6 +25,7 @@ config DRM_I915_DEBUG · 24 unmodified lines
2525 select X86_MSR # used by igt/pm_rpm
2626 select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)
2727 select DRM_DEBUG_MM if DRM=y
28+ select STACKDEPOT if DRM=y # for DRM_DEBUG_MM
2829 select DRM_DEBUG_MM_SELFTEST
2930 select SW_SYNC # signaling validation framework (igt/syncobj*)
3031 select DRM_I915_SW_FENCE_DEBUG_OBJECTS
@@ -89,6 +90,18 @@ config DRM_I915_SW_FENCE_CHECK_DAG · 58 unmodified lines
8990
9091 If in doubt, say "N".
9192
93+config DRM_I915_DEBUG_GUC
94+ bool "Enable additional driver debugging for GuC"
95+ depends on DRM_I915
96+ default n
97+ help
98+ Choose this option to turn on extra driver debugging that may affect
99+ performance but will help resolve GuC related issues.
100+
101+ Recommended for driver developers only.
102+
103+ If in doubt, say "N".
104+
92105 config DRM_I915_SELFTEST
93106 bool "Enable selftests upon driver load"
94107 depends on DRM_I915
drivers/gpu/drm/i915/Makefile+7−4
@@ -12,7 +12,7 @@ · 11 unmodified lines
1212 # Note the danger in using -Wall -Wextra is that when CI updates gcc we
1313 # will most likely get a sudden build breakage... Hopefully we will fix
1414 # new warnings before CI updates!
15−subdir-ccflags-y := -Wall -Wextra
15+subdir-ccflags-y := -Wall -Wextra -Wvla
1616 subdir-ccflags-y += $(call cc-disable-warning, unused-parameter)
1717 subdir-ccflags-y += $(call cc-disable-warning, type-limits)
1818 subdir-ccflags-y += $(call cc-disable-warning, missing-field-initializers)
@@ -43,7 +43,8 @@ i915-y := i915_drv.o \ · 24 unmodified lines
4343 intel_csr.o \
4444 intel_device_info.o \
4545 intel_pm.o \
46− intel_runtime_pm.o
46+ intel_runtime_pm.o \
47+ intel_workarounds.o
4748
4849 i915-$(CONFIG_COMPAT) += i915_ioc32.o
4950 i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
@@ -79,7 +80,8 @@ i915-y += i915_cmd_parser.o \ · 29 unmodified lines
7980 intel_lrc.o \
8081 intel_mocs.o \
8182 intel_ringbuffer.o \
82− intel_uncore.o
83+ intel_uncore.o \
84+ intel_wopcm.o
8385
8486 # general-purpose microcontroller (GuC) support
8587 i915-y += intel_uc.o \
@@ -171,7 +173,8 @@ i915-y += i915_perf.o \ · 85 unmodified lines
171173 i915_oa_glk.o \
172174 i915_oa_cflgt2.o \
173175 i915_oa_cflgt3.o \
174− i915_oa_cnl.o
176+ i915_oa_cnl.o \
177+ i915_oa_icl.o
175178
176179 ifeq ($(CONFIG_DRM_I915_GVT),y)
177180 i915-y += intel_gvt.o
drivers/gpu/drm/i915/gvt/debugfs.c+1−12
@@ -122,18 +122,7 @@ static int vgpu_mmio_diff_show(struct seq_file *s, void *unused) · 121 unmodified lines
122122 seq_printf(s, "Total: %d, Diff: %d\n", param.total, param.diff);
123123 return 0;
124124 }
125−
126−static int vgpu_mmio_diff_open(struct inode *inode, struct file *file)
127−{
128− return single_open(file, vgpu_mmio_diff_show, inode->i_private);
129−}
130−
131−static const struct file_operations vgpu_mmio_diff_fops = {
132− .open = vgpu_mmio_diff_open,
133− .read = seq_read,
134− .llseek = seq_lseek,
135− .release = single_release,
136−};
125+DEFINE_SHOW_ATTRIBUTE(vgpu_mmio_diff);
137126
138127 /**
139128 * intel_gvt_debugfs_add_vgpu - register debugfs entries for a vGPU
drivers/gpu/drm/i915/i915_debugfs.c+193−125
@@ -1215,20 +1215,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused) · 1214 unmodified lines
12151215 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
12161216 rp_state_cap >> 16) & 0xff;
12171217 max_freq *= (IS_GEN9_BC(dev_priv) ||
1218− IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1218+ INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
12191219 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
12201220 intel_gpu_freq(dev_priv, max_freq));
12211221
12221222 max_freq = (rp_state_cap & 0xff00) >> 8;
12231223 max_freq *= (IS_GEN9_BC(dev_priv) ||
1224− IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1224+ INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
12251225 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
12261226 intel_gpu_freq(dev_priv, max_freq));
12271227
12281228 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
12291229 rp_state_cap >> 0) & 0xff;
12301230 max_freq *= (IS_GEN9_BC(dev_priv) ||
1231− IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1231+ INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
12321232 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
12331233 intel_gpu_freq(dev_priv, max_freq));
12341234 seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -1796,9 +1796,9 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) · 561 unmodified lines
17961796 {
17971797 struct drm_i915_private *dev_priv = node_to_i915(m->private);
17981798 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1799− int ret = 0;
1800− int gpu_freq, ia_freq;
18011799 unsigned int max_gpu_freq, min_gpu_freq;
1800+ int gpu_freq, ia_freq;
1801+ int ret;
18021802
18031803 if (!HAS_LLC(dev_priv))
18041804 return -ENODEV;
@@ -1809,13 +1809,12 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) · 4 unmodified lines
18091809 if (ret)
18101810 goto out;
18111811
1812− if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
1812+ min_gpu_freq = rps->min_freq;
1813+ max_gpu_freq = rps->max_freq;
1814+ if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
18131815 /* Convert GT frequency to 50 HZ units */
1814− min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER;
1815− max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER;
1816− } else {
1817− min_gpu_freq = rps->min_freq_softlimit;
1818− max_gpu_freq = rps->max_freq_softlimit;
1816+ min_gpu_freq /= GEN9_FREQ_SCALER;
1817+ max_gpu_freq /= GEN9_FREQ_SCALER;
18191818 }
18201819
18211820 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
@@ -1828,7 +1827,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) · 6 unmodified lines
18281827 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
18291828 intel_gpu_freq(dev_priv, (gpu_freq *
18301829 (IS_GEN9_BC(dev_priv) ||
1831− IS_CANNONLAKE(dev_priv) ?
1830+ INTEL_GEN(dev_priv) >= 10 ?
18321831 GEN9_FREQ_SCALER : 1))),
18331832 ((ia_freq >> 0) & 0xff) * 100,
18341833 ((ia_freq >> 8) & 0xff) * 100);
@@ -1923,8 +1922,8 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data) · 88 unmodified lines
19231922
19241923 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
19251924 {
1926− seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)",
1927− ring->space, ring->head, ring->tail);
1925+ seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, emit: %u)",
1926+ ring->space, ring->head, ring->tail, ring->emit);
19281927 }
19291928
19301929 static int i915_context_status(struct seq_file *m, void *unused)
@@ -2326,30 +2325,45 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data) · 395 unmodified lines
23262325 return 0;
23272326 }
23282327
2329−static void i915_guc_log_info(struct seq_file *m,
2330− struct drm_i915_private *dev_priv)
2328+static const char *
2329+stringify_guc_log_type(enum guc_log_buffer_type type)
23312330 {
2332− struct intel_guc *guc = &dev_priv->guc;
2331+ switch (type) {
2332+ case GUC_ISR_LOG_BUFFER:
2333+ return "ISR";
2334+ case GUC_DPC_LOG_BUFFER:
2335+ return "DPC";
2336+ case GUC_CRASH_DUMP_LOG_BUFFER:
2337+ return "CRASH";
2338+ default:
2339+ MISSING_CASE(type);
2340+ }
23332341
2334− seq_puts(m, "\nGuC logging stats:\n");
2342+ return "";
2343+}
23352344
2336− seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n",
2337− guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2338− guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2345+static void i915_guc_log_info(struct seq_file *m,
2346+ struct drm_i915_private *dev_priv)
2347+{
2348+ struct intel_guc_log *log = &dev_priv->guc.log;
2349+ enum guc_log_buffer_type type;
23392350
2340− seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n",
2341− guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2342− guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2351+ if (!intel_guc_log_relay_enabled(log)) {
2352+ seq_puts(m, "GuC log relay disabled\n");
2353+ return;
2354+ }
23432355
2344− seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2345− guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2346− guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2356+ seq_puts(m, "GuC logging stats:\n");
23472357
2348− seq_printf(m, "\tTotal flush interrupt count: %u\n",
2349− guc->log.flush_interrupt_count);
2358+ seq_printf(m, "\tRelay full count: %u\n",
2359+ log->relay.full_count);
23502360
2351− seq_printf(m, "\tCapture miss count: %u\n",
2352− guc->log.capture_miss_count);
2361+ for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
2362+ seq_printf(m, "\t%s:\tflush count %10u, overflow count %10u\n",
2363+ stringify_guc_log_type(type),
2364+ log->stats[type].flush,
2365+ log->stats[type].sampled_overflow);
2366+ }
23532367 }
23542368
23552369 static void i915_guc_client_info(struct seq_file *m,
@@ -2379,14 +2393,19 @@ static int i915_guc_info(struct seq_file *m, void *data) · 23 unmodified lines
23792393 struct drm_i915_private *dev_priv = node_to_i915(m->private);
23802394 const struct intel_guc *guc = &dev_priv->guc;
23812395
2382− if (!USES_GUC_SUBMISSION(dev_priv))
2396+ if (!USES_GUC(dev_priv))
23832397 return -ENODEV;
23842398
2399+ i915_guc_log_info(m, dev_priv);
2400+
2401+ if (!USES_GUC_SUBMISSION(dev_priv))
2402+ return 0;
2403+
23852404 GEM_BUG_ON(!guc->execbuf_client);
23862405
2387− seq_printf(m, "Doorbell map:\n");
2406+ seq_printf(m, "\nDoorbell map:\n");
23882407 seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2389− seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2408+ seq_printf(m, "Doorbell next cacheline: 0x%x\n", guc->db_cacheline);
23902409
23912410 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
23922411 i915_guc_client_info(m, dev_priv, guc->execbuf_client);
@@ -2396,8 +2415,6 @@ static int i915_guc_info(struct seq_file *m, void *data) · 3 unmodified lines
23962415 i915_guc_client_info(m, dev_priv, guc->preempt_client);
23972416 }
23982417
2399− i915_guc_log_info(m, dev_priv);
2400−
24012418 /* Add more as required ... */
24022419
24032420 return 0;
@@ -2496,35 +2513,73 @@ static int i915_guc_log_dump(struct seq_file *m, void *data) · 92 unmodified lines
24962513 return 0;
24972514 }
24982515
2499−static int i915_guc_log_control_get(void *data, u64 *val)
2516+static int i915_guc_log_level_get(void *data, u64 *val)
25002517 {
25012518 struct drm_i915_private *dev_priv = data;
25022519
2503− if (!HAS_GUC(dev_priv))
2520+ if (!USES_GUC(dev_priv))
25042521 return -ENODEV;
25052522
2506− if (!dev_priv->guc.log.vma)
2507− return -EINVAL;
2508−
2509− *val = i915_modparams.guc_log_level;
2523+ *val = intel_guc_log_level_get(&dev_priv->guc.log);
25102524
25112525 return 0;
25122526 }
25132527
2514−static int i915_guc_log_control_set(void *data, u64 val)
2528+static int i915_guc_log_level_set(void *data, u64 val)
25152529 {
25162530 struct drm_i915_private *dev_priv = data;
25172531
2518− if (!HAS_GUC(dev_priv))
2532+ if (!USES_GUC(dev_priv))
25192533 return -ENODEV;
25202534
2521− return intel_guc_log_control(&dev_priv->guc, val);
2535+ return intel_guc_log_level_set(&dev_priv->guc.log, val);
25222536 }
25232537
2524−DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2525− i915_guc_log_control_get, i915_guc_log_control_set,
2538+DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
2539+ i915_guc_log_level_get, i915_guc_log_level_set,
25262540 "%lld\n");
25272541
2542+static int i915_guc_log_relay_open(struct inode *inode, struct file *file)
2543+{
2544+ struct drm_i915_private *dev_priv = inode->i_private;
2545+
2546+ if (!USES_GUC(dev_priv))
2547+ return -ENODEV;
2548+
2549+ file->private_data = &dev_priv->guc.log;
2550+
2551+ return intel_guc_log_relay_open(&dev_priv->guc.log);
2552+}
2553+
2554+static ssize_t
2555+i915_guc_log_relay_write(struct file *filp,
2556+ const char __user *ubuf,
2557+ size_t cnt,
2558+ loff_t *ppos)
2559+{
2560+ struct intel_guc_log *log = filp->private_data;
2561+
2562+ intel_guc_log_relay_flush(log);
2563+
2564+ return cnt;
2565+}
2566+
2567+static int i915_guc_log_relay_release(struct inode *inode, struct file *file)
2568+{
2569+ struct drm_i915_private *dev_priv = inode->i_private;
2570+
2571+ intel_guc_log_relay_close(&dev_priv->guc.log);
2572+
2573+ return 0;
2574+}
2575+
2576+static const struct file_operations i915_guc_log_relay_fops = {
2577+ .owner = THIS_MODULE,
2578+ .open = i915_guc_log_relay_open,
2579+ .write = i915_guc_log_relay_write,
2580+ .release = i915_guc_log_relay_release,
2581+};
2582+
25282583 static const char *psr2_live_status(u32 val)
25292584 {
25302585 static const char * const live_status[] = {
@@ -2569,14 +2624,13 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) · 38 unmodified lines
25692624
25702625 mutex_lock(&dev_priv->psr.lock);
25712626 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2572− seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
25732627 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
25742628 dev_priv->psr.busy_frontbuffer_bits);
25752629 seq_printf(m, "Re-enable work scheduled: %s\n",
25762630 yesno(work_busy(&dev_priv->psr.work.work)));
25772631
25782632 if (HAS_DDI(dev_priv)) {
2579− if (dev_priv->psr.psr2_support)
2633+ if (dev_priv->psr.psr2_enabled)
25802634 enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
25812635 else
25822636 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
@@ -2624,7 +2678,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) · 41 unmodified lines
26242678
26252679 seq_printf(m, "Performance_Counter: %u\n", psrperf);
26262680 }
2627− if (dev_priv->psr.psr2_support) {
2681+ if (dev_priv->psr.psr2_enabled) {
26282682 u32 psr2 = I915_READ(EDP_PSR2_STATUS);
26292683
26302684 seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
@@ -3231,7 +3285,8 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) · 600 unmodified lines
32313285 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
32323286 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
32333287
3234− seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3288+ seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
3289+ pll->info->id);
32353290 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
32363291 pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
32373292 seq_printf(m, " tracked hardware state:\n");
@@ -3567,7 +3622,8 @@ static ssize_t i915_displayport_test_active_write(struct file *file, · 329 unmodified lines
35673622
35683623 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
35693624 {
3570− struct drm_device *dev = m->private;
3625+ struct drm_i915_private *dev_priv = m->private;
3626+ struct drm_device *dev = &dev_priv->drm;
35713627 struct drm_connector *connector;
35723628 struct drm_connector_list_iter conn_iter;
35733629 struct intel_dp *intel_dp;
@@ -3601,10 +3657,8 @@ static int i915_displayport_test_active_show(struct seq_file *m, void *data) · 27 unmodified lines
36013657 static int i915_displayport_test_active_open(struct inode *inode,
36023658 struct file *file)
36033659 {
3604− struct drm_i915_private *dev_priv = inode->i_private;
3605−
36063660 return single_open(file, i915_displayport_test_active_show,
3607− &dev_priv->drm);
3661+ inode->i_private);
36083662 }
36093663
36103664 static const struct file_operations i915_displayport_test_active_fops = {
@@ -3618,7 +3672,8 @@ static const struct file_operations i915_displayport_test_active_fops = { · 7 unmodified lines
36183672
36193673 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
36203674 {
3621− struct drm_device *dev = m->private;
3675+ struct drm_i915_private *dev_priv = m->private;
3676+ struct drm_device *dev = &dev_priv->drm;
36223677 struct drm_connector *connector;
36233678 struct drm_connector_list_iter conn_iter;
36243679 struct intel_dp *intel_dp;
@@ -3657,26 +3712,12 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data) · 32 unmodified lines
36573712
36583713 return 0;
36593714 }
3660−static int i915_displayport_test_data_open(struct inode *inode,
3661− struct file *file)
3662−{
3663− struct drm_i915_private *dev_priv = inode->i_private;
3664−
3665− return single_open(file, i915_displayport_test_data_show,
3666− &dev_priv->drm);
3667−}
3668−
3669−static const struct file_operations i915_displayport_test_data_fops = {
3670− .owner = THIS_MODULE,
3671− .open = i915_displayport_test_data_open,
3672− .read = seq_read,
3673− .llseek = seq_lseek,
3674− .release = single_release
3675−};
3715+DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data);
36763716
36773717 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
36783718 {
3679− struct drm_device *dev = m->private;
3719+ struct drm_i915_private *dev_priv = m->private;
3720+ struct drm_device *dev = &dev_priv->drm;
36803721 struct drm_connector *connector;
36813722 struct drm_connector_list_iter conn_iter;
36823723 struct intel_dp *intel_dp;
@@ -3703,23 +3744,7 @@ static int i915_displayport_test_type_show(struct seq_file *m, void *data) · 20 unmodified lines
37033744
37043745 return 0;
37053746 }
3706−
3707−static int i915_displayport_test_type_open(struct inode *inode,
3708− struct file *file)
3709−{
3710− struct drm_i915_private *dev_priv = inode->i_private;
3711−
3712− return single_open(file, i915_displayport_test_type_show,
3713− &dev_priv->drm);
3714−}
3715−
3716−static const struct file_operations i915_displayport_test_type_fops = {
3717− .owner = THIS_MODULE,
3718− .open = i915_displayport_test_type_open,
3719− .read = seq_read,
3720− .llseek = seq_lseek,
3721− .release = single_release
3722−};
3747+DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type);
37233748
37243749 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
37253750 {
@@ -3987,8 +4012,8 @@ i915_wedged_set(void *data, u64 val) · 261 unmodified lines
39874012 engine->hangcheck.stalled = true;
39884013 }
39894014
3990− i915_handle_error(i915, val, "Manually set wedged engine mask = %llx",
3991− val);
4015+ i915_handle_error(i915, val, I915_ERROR_CAPTURE,
4016+ "Manually set wedged engine mask = %llx", val);
39924017
39934018 wait_on_bit(&i915->gpu_error.flags,
39944019 I915_RESET_HANDOFF,
@@ -4316,9 +4341,10 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, · 321 unmodified lines
43164341 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
43174342 struct sseu_dev_info *sseu)
43184343 {
4319− int ss_max = 2;
4344+#define SS_MAX 2
4345+ const int ss_max = SS_MAX;
4346+ u32 sig1[SS_MAX], sig2[SS_MAX];
43204347 int ss;
4321− u32 sig1[ss_max], sig2[ss_max];
43224348
43234349 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
43244350 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
@@ -4342,15 +4368,16 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, · 17 unmodified lines
43424368 sseu->eu_per_subslice = max_t(unsigned int,
43434369 sseu->eu_per_subslice, eu_cnt);
43444370 }
4371+#undef SS_MAX
43454372 }
43464373
43474374 static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
43484375 struct sseu_dev_info *sseu)
43494376 {
4377+#define SS_MAX 6
43504378 const struct intel_device_info *info = INTEL_INFO(dev_priv);
4379+ u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
43514380 int s, ss;
4352− u32 s_reg[info->sseu.max_slices];
4353− u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
43544381
43554382 for (s = 0; s < info->sseu.max_slices; s++) {
43564383 /*
@@ -4397,15 +4424,16 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, · 40 unmodified lines
43974424 eu_cnt);
43984425 }
43994426 }
4427+#undef SS_MAX
44004428 }
44014429
44024430 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
44034431 struct sseu_dev_info *sseu)
44044432 {
4433+#define SS_MAX 3
44054434 const struct intel_device_info *info = INTEL_INFO(dev_priv);
4435+ u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
44064436 int s, ss;
4407− u32 s_reg[info->sseu.max_slices];
4408− u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
44094437
44104438 for (s = 0; s < info->sseu.max_slices; s++) {
44114439 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
@@ -4452,6 +4480,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, · 40 unmodified lines
44524480 eu_cnt);
44534481 }
44544482 }
4483+#undef SS_MAX
44554484 }
44564485
44574486 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
@@ -4703,6 +4732,67 @@ static int i915_drrs_ctl_set(void *data, u64 val) · 245 unmodified lines
47034732
47044733 DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n");
47054734
4735+static ssize_t
4736+i915_fifo_underrun_reset_write(struct file *filp,
4737+ const char __user *ubuf,
4738+ size_t cnt, loff_t *ppos)
4739+{
4740+ struct drm_i915_private *dev_priv = filp->private_data;
4741+ struct intel_crtc *intel_crtc;
4742+ struct drm_device *dev = &dev_priv->drm;
4743+ int ret;
4744+ bool reset;
4745+
4746+ ret = kstrtobool_from_user(ubuf, cnt, &reset);
4747+ if (ret)
4748+ return ret;
4749+
4750+ if (!reset)
4751+ return cnt;
4752+
4753+ for_each_intel_crtc(dev, intel_crtc) {
4754+ struct drm_crtc_commit *commit;
4755+ struct intel_crtc_state *crtc_state;
4756+
4757+ ret = drm_modeset_lock_single_interruptible(&intel_crtc->base.mutex);
4758+ if (ret)
4759+ return ret;
4760+
4761+ crtc_state = to_intel_crtc_state(intel_crtc->base.state);
4762+ commit = crtc_state->base.commit;
4763+ if (commit) {
4764+ ret = wait_for_completion_interruptible(&commit->hw_done);
4765+ if (!ret)
4766+ ret = wait_for_completion_interruptible(&commit->flip_done);
4767+ }
4768+
4769+ if (!ret && crtc_state->base.active) {
4770+ DRM_DEBUG_KMS("Re-arming FIFO underruns on pipe %c\n",
4771+ pipe_name(intel_crtc->pipe));
4772+
4773+ intel_crtc_arm_fifo_underrun(intel_crtc, crtc_state);
4774+ }
4775+
4776+ drm_modeset_unlock(&intel_crtc->base.mutex);
4777+
4778+ if (ret)
4779+ return ret;
4780+ }
4781+
4782+ ret = intel_fbc_reset_underrun(dev_priv);
4783+ if (ret)
4784+ return ret;
4785+
4786+ return cnt;
4787+}
4788+
4789+static const struct file_operations i915_fifo_underrun_reset_ops = {
4790+ .owner = THIS_MODULE,
4791+ .open = simple_open,
4792+ .write = i915_fifo_underrun_reset_write,
4793+ .llseek = default_llseek,
4794+};
4795+
47064796 static const struct drm_info_list i915_debugfs_list[] = {
47074797 {"i915_capabilities", i915_capabilities, 0},
47084798 {"i915_gem_objects", i915_gem_object_info, 0},
@@ -4770,6 +4860,7 @@ static const struct i915_debugfs_files { · 61 unmodified lines
47704860 {"i915_error_state", &i915_error_state_fops},
47714861 {"i915_gpu_info", &i915_gpu_info_fops},
47724862 #endif
4863+ {"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops},
47734864 {"i915_next_seqno", &i915_next_seqno_fops},
47744865 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
47754866 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
@@ -4779,7 +4870,8 @@ static const struct i915_debugfs_files { · 3 unmodified lines
47794870 {"i915_dp_test_data", &i915_displayport_test_data_fops},
47804871 {"i915_dp_test_type", &i915_displayport_test_type_fops},
47814872 {"i915_dp_test_active", &i915_displayport_test_active_fops},
4782− {"i915_guc_log_control", &i915_guc_log_control_fops},
4873+ {"i915_guc_log_level", &i915_guc_log_level_fops},
4874+ {"i915_guc_log_relay", &i915_guc_log_relay_fops},
47834875 {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
47844876 {"i915_ipc_status", &i915_ipc_status_fops},
47854877 {"i915_drrs_ctl", &i915_drrs_ctl_fops}
@@ -4876,19 +4968,7 @@ static int i915_dpcd_show(struct seq_file *m, void *data) · 90 unmodified lines
48764968
48774969 return 0;
48784970 }
4879−
4880−static int i915_dpcd_open(struct inode *inode, struct file *file)
4881−{
4882− return single_open(file, i915_dpcd_show, inode->i_private);
4883−}
4884−
4885−static const struct file_operations i915_dpcd_fops = {
4886− .owner = THIS_MODULE,
4887− .open = i915_dpcd_open,
4888− .read = seq_read,
4889− .llseek = seq_lseek,
4890− .release = single_release,
4891−};
4971+DEFINE_SHOW_ATTRIBUTE(i915_dpcd);
48924972
48934973 static int i915_panel_show(struct seq_file *m, void *data)
48944974 {
@@ -4910,19 +4990,7 @@ static int i915_panel_show(struct seq_file *m, void *data) · 15 unmodified lines
49104990
49114991 return 0;
49124992 }
4913−
4914−static int i915_panel_open(struct inode *inode, struct file *file)
4915−{
4916− return single_open(file, i915_panel_show, inode->i_private);
4917−}
4918−
4919−static const struct file_operations i915_panel_fops = {
4920− .owner = THIS_MODULE,
4921− .open = i915_panel_open,
4922− .read = seq_read,
4923− .llseek = seq_lseek,
4924− .release = single_release,
4925−};
4993+DEFINE_SHOW_ATTRIBUTE(i915_panel);
49264994
49274995 /**
49284996 * i915_debugfs_connector_add - add i915 specific connector debugfs files
drivers/gpu/drm/i915/i915_drv.c+33−33
@@ -377,9 +377,9 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, · 376 unmodified lines
377377 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
378378 break;
379379 case I915_PARAM_HUC_STATUS:
380− intel_runtime_pm_get(dev_priv);
381− value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
382− intel_runtime_pm_put(dev_priv);
380+ value = intel_huc_check_status(&dev_priv->huc);
381+ if (value < 0)
382+ return value;
383383 break;
384384 case I915_PARAM_MMAP_GTT_VERSION:
385385 /* Though we've started our numbering from 1, and so class all
@@ -695,11 +695,9 @@ static int i915_load_modeset_init(struct drm_device *dev) · 309 unmodified lines
695695 if (ret)
696696 goto cleanup_irq;
697697
698− intel_uc_init_fw(dev_priv);
699−
700698 ret = i915_gem_init(dev_priv);
701699 if (ret)
702− goto cleanup_uc;
700+ goto cleanup_irq;
703701
704702 intel_setup_overlay(dev_priv);
705703
@@ -719,8 +717,6 @@ cleanup_gem: · 13 unmodified lines
719717 if (i915_gem_suspend(dev_priv))
720718 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
721719 i915_gem_fini(dev_priv);
722−cleanup_uc:
723− intel_uc_fini_fw(dev_priv);
724720 cleanup_irq:
725721 drm_irq_uninstall(dev);
726722 intel_teardown_gmbus(dev_priv);
@@ -922,16 +918,21 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, · 195 unmodified lines
922918 mutex_init(&dev_priv->wm.wm_mutex);
923919 mutex_init(&dev_priv->pps_mutex);
924920
925− intel_uc_init_early(dev_priv);
926921 i915_memcpy_init_early(dev_priv);
927922
928923 ret = i915_workqueues_init(dev_priv);
929924 if (ret < 0)
930925 goto err_engines;
931926
927+ ret = i915_gem_init_early(dev_priv);
928+ if (ret < 0)
929+ goto err_workqueues;
930+
932931 /* This must be called before any calls to HAS_PCH_* */
933932 intel_detect_pch(dev_priv);
934933
934+ intel_wopcm_init_early(&dev_priv->wopcm);
935+ intel_uc_init_early(dev_priv);
935936 intel_pm_setup(dev_priv);
936937 intel_init_dpio(dev_priv);
937938 intel_power_domains_init(dev_priv);
@@ -940,18 +941,13 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, · 2 unmodified lines
940941 intel_init_display_hooks(dev_priv);
941942 intel_init_clock_gating_hooks(dev_priv);
942943 intel_init_audio_hooks(dev_priv);
943− ret = i915_gem_load_init(dev_priv);
944− if (ret < 0)
945− goto err_irq;
946−
947944 intel_display_crc_init(dev_priv);
948945
949946 intel_detect_preproduction_hw(dev_priv);
950947
951948 return 0;
952949
953−err_irq:
954− intel_irq_fini(dev_priv);
950+err_workqueues:
955951 i915_workqueues_cleanup(dev_priv);
956952 err_engines:
957953 i915_engines_cleanup(dev_priv);
@@ -964,8 +960,9 @@ err_engines: · 6 unmodified lines
964960 */
965961 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
966962 {
967− i915_gem_load_cleanup(dev_priv);
968963 intel_irq_fini(dev_priv);
964+ intel_uc_cleanup_early(dev_priv);
965+ i915_gem_cleanup_early(dev_priv);
969966 i915_workqueues_cleanup(dev_priv);
970967 i915_engines_cleanup(dev_priv);
971968 }
@@ -1035,6 +1032,10 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) · 63 unmodified lines
10351032
10361033 intel_uncore_init(dev_priv);
10371034
1035+ intel_device_info_init_mmio(dev_priv);
1036+
1037+ intel_uncore_prune(dev_priv);
1038+
10381039 intel_uc_init_mmio(dev_priv);
10391040
10401041 ret = intel_engines_init_mmio(dev_priv);
@@ -1077,8 +1078,6 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv) · 36 unmodified lines
10771078 i915_modparams.enable_ppgtt);
10781079 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
10791080
1080− intel_uc_sanitize_options(dev_priv);
1081−
10821081 intel_gvt_sanitize_options(dev_priv);
10831082 }
10841083
@@ -1244,7 +1243,6 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) · 159 unmodified lines
12441243 /* Reveal our presence to userspace */
12451244 if (drm_dev_register(dev, 0) == 0) {
12461245 i915_debugfs_register(dev_priv);
1247− i915_guc_log_register(dev_priv);
12481246 i915_setup_sysfs(dev_priv);
12491247
12501248 /* Depends on sysfs having been initialized */
@@ -1304,7 +1302,6 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) · 53 unmodified lines
13041302 i915_pmu_unregister(dev_priv);
13051303
13061304 i915_teardown_sysfs(dev_priv);
1307− i915_guc_log_unregister(dev_priv);
13081305 drm_dev_unregister(&dev_priv->drm);
13091306
13101307 i915_gem_shrinker_unregister(dev_priv);
@@ -1463,7 +1460,6 @@ void i915_driver_unload(struct drm_device *dev) · 152 unmodified lines
14631460 i915_reset_error_state(dev_priv);
14641461
14651462 i915_gem_fini(dev_priv);
1466− intel_uc_fini_fw(dev_priv);
14671463 intel_fbc_cleanup_cfb(dev_priv);
14681464
14691465 intel_power_domains_fini(dev_priv);
@@ -1876,7 +1872,8 @@ static int i915_resume_switcheroo(struct drm_device *dev) · 406 unmodified lines
18761872 /**
18771873 * i915_reset - reset chip after a hang
18781874 * @i915: #drm_i915_private to reset
1879− * @flags: Instructions
1875+ * @stalled_mask: mask of the stalled engines with the guilty requests
1876+ * @reason: user error message for why we are resetting
18801877 *
18811878 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
18821879 * on failure.
@@ -1891,12 +1888,16 @@ static int i915_resume_switcheroo(struct drm_device *dev) · 8 unmodified lines
18911888 * - re-init interrupt state
18921889 * - re-init display
18931890 */
1894−void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1891+void i915_reset(struct drm_i915_private *i915,
1892+ unsigned int stalled_mask,
1893+ const char *reason)
18951894 {
18961895 struct i915_gpu_error *error = &i915->gpu_error;
18971896 int ret;
18981897 int i;
18991898
1899+ GEM_TRACE("flags=%lx\n", error->flags);
1900+
19001901 might_sleep();
19011902 lockdep_assert_held(&i915->drm.struct_mutex);
19021903 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
@@ -1908,8 +1909,8 @@ void i915_reset(struct drm_i915_private *i915, unsigned int flags) · 5 unmodified lines
19081909 if (!i915_gem_unset_wedged(i915))
19091910 goto wakeup;
19101911
1911− if (!(flags & I915_RESET_QUIET))
1912− dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1912+ if (reason)
1913+ dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
19131914 error->reset_count++;
19141915
19151916 disable_irq(i915->drm.irq);
@@ -1952,7 +1953,7 @@ void i915_reset(struct drm_i915_private *i915, unsigned int flags) · 36 unmodified lines
19521953 goto error;
19531954 }
19541955
1955− i915_gem_reset(i915);
1956+ i915_gem_reset(i915, stalled_mask);
19561957 intel_overlay_reset(i915);
19571958
19581959 /*
@@ -1998,7 +1999,6 @@ taint: · 39 unmodified lines
19981999 error:
19992000 i915_gem_set_wedged(i915);
20002001 i915_retire_requests(i915);
2001− intel_gpu_reset(i915, ALL_ENGINES);
20022002 goto finish;
20032003 }
20042004
@@ -2011,7 +2011,7 @@ static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv, · 6 unmodified lines
20112011 /**
20122012 * i915_reset_engine - reset GPU engine to recover from a hang
20132013 * @engine: engine to reset
2014− * @flags: options
2014+ * @msg: reason for GPU reset; or NULL for no dev_notice()
20152015 *
20162016 * Reset a specific GPU engine. Useful if a hang is detected.
20172017 * Returns zero on successful reset or otherwise an error code.
@@ -2021,12 +2021,13 @@ static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv, · 3 unmodified lines
20212021 * - reset engine (which will force the engine to idle)
20222022 * - re-init/configure engine
20232023 */
2024−int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
2024+int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
20252025 {
20262026 struct i915_gpu_error *error = &engine->i915->gpu_error;
20272027 struct i915_request *active_request;
20282028 int ret;
20292029
2030+ GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
20302031 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
20312032
20322033 active_request = i915_gem_reset_prepare_engine(engine);
@@ -2036,10 +2037,9 @@ int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags) · 3 unmodified lines
20362037 goto out;
20372038 }
20382039
2039− if (!(flags & I915_RESET_QUIET)) {
2040+ if (msg)
20402041 dev_notice(engine->i915->drm.dev,
2041− "Resetting %s after gpu hang\n", engine->name);
2042− }
2042+ "Resetting %s for %s\n", engine->name, msg);
20432043 error->reset_engine_count[engine->id]++;
20442044
20452045 if (!engine->i915->guc.execbuf_client)
@@ -2059,7 +2059,7 @@ int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags) · 13 unmodified lines
20592059 * active request and can drop it, adjust head to skip the offending
20602060 * request to resume executing remaining requests in the queue.
20612061 */
2062− i915_gem_reset_engine(engine, active_request);
2062+ i915_gem_reset_engine(engine, active_request, true);
20632063
20642064 /*
20652065 * The engine and its registers (and workarounds in case of render)
drivers/gpu/drm/i915/i915_drv.h+39−350
@@ -64,6 +64,7 @@ · 63 unmodified lines
6464 #include "intel_opregion.h"
6565 #include "intel_ringbuffer.h"
6666 #include "intel_uncore.h"
67+#include "intel_wopcm.h"
6768 #include "intel_uc.h"
6869
6970 #include "i915_gem.h"
@@ -72,7 +73,7 @@ · 2 unmodified lines
7273 #include "i915_gem_object.h"
7374 #include "i915_gem_gtt.h"
7475 #include "i915_gem_timeline.h"
75−
76+#include "i915_gpu_error.h"
7677 #include "i915_request.h"
7778 #include "i915_vma.h"
7879
@@ -83,8 +84,8 @@ · 4 unmodified lines
8384
8485 #define DRIVER_NAME "i915"
8586 #define DRIVER_DESC "Intel Graphics"
86−#define DRIVER_DATE "20180308"
87−#define DRIVER_TIMESTAMP 1520513379
87+#define DRIVER_DATE "20180413"
88+#define DRIVER_TIMESTAMP 1523611258
8889
8990 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
9091 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
@@ -261,6 +262,7 @@ enum hpd_pin { · 170 unmodified lines
261262 HPD_PORT_C,
262263 HPD_PORT_D,
263264 HPD_PORT_E,
265+ HPD_PORT_F,
264266 HPD_NUM_PINS
265267 };
266268
@@ -453,172 +455,6 @@ struct intel_csr { · 186 unmodified lines
453455 uint32_t allowed_dc_mask;
454456 };
455457
456−struct intel_display_error_state;
457−
458−struct i915_gpu_state {
459− struct kref ref;
460− ktime_t time;
461− ktime_t boottime;
462− ktime_t uptime;
463−
464− struct drm_i915_private *i915;
465−
466− char error_msg[128];
467− bool simulated;
468− bool awake;
469− bool wakelock;
470− bool suspended;
471− int iommu;
472− u32 reset_count;
473− u32 suspend_count;
474− struct intel_device_info device_info;
475− struct intel_driver_caps driver_caps;
476− struct i915_params params;
477−
478− struct i915_error_uc {
479− struct intel_uc_fw guc_fw;
480− struct intel_uc_fw huc_fw;
481− struct drm_i915_error_object *guc_log;
482− } uc;
483−
484− /* Generic register state */
485− u32 eir;
486− u32 pgtbl_er;
487− u32 ier;
488− u32 gtier[4], ngtier;
489− u32 ccid;
490− u32 derrmr;
491− u32 forcewake;
492− u32 error; /* gen6+ */
493− u32 err_int; /* gen7 */
494− u32 fault_data0; /* gen8, gen9 */
495− u32 fault_data1; /* gen8, gen9 */
496− u32 done_reg;
497− u32 gac_eco;
498− u32 gam_ecochk;
499− u32 gab_ctl;
500− u32 gfx_mode;
501−
502− u32 nfence;
503− u64 fence[I915_MAX_NUM_FENCES];
504− struct intel_overlay_error_state *overlay;
505− struct intel_display_error_state *display;
506−
507− struct drm_i915_error_engine {
508− int engine_id;
509− /* Software tracked state */
510− bool idle;
511− bool waiting;
512− int num_waiters;
513− unsigned long hangcheck_timestamp;
514− bool hangcheck_stalled;
515− enum intel_engine_hangcheck_action hangcheck_action;
516− struct i915_address_space *vm;
517− int num_requests;
518− u32 reset_count;
519−
520− /* position of active request inside the ring */
521− u32 rq_head, rq_post, rq_tail;
522−
523− /* our own tracking of ring head and tail */
524− u32 cpu_ring_head;
525− u32 cpu_ring_tail;
526−
527− u32 last_seqno;
528−
529− /* Register state */
530− u32 start;
531− u32 tail;
532− u32 head;
533− u32 ctl;
534− u32 mode;
535− u32 hws;
536− u32 ipeir;
537− u32 ipehr;
538− u32 bbstate;
539− u32 instpm;
540− u32 instps;
541− u32 seqno;
542− u64 bbaddr;
543− u64 acthd;
544− u32 fault_reg;
545− u64 faddr;
546− u32 rc_psmi; /* sleep state */
547− u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
548− struct intel_instdone instdone;
549−
550− struct drm_i915_error_context {
551− char comm[TASK_COMM_LEN];
552− pid_t pid;
553− u32 handle;
554− u32 hw_id;
555− int priority;
556− int ban_score;
557− int active;
558− int guilty;
559− bool bannable;
560− } context;
561−
562− struct drm_i915_error_object {
563− u64 gtt_offset;
564− u64 gtt_size;
565− int page_count;
566− int unused;
567− u32 *pages[0];
568− } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
569−
570− struct drm_i915_error_object **user_bo;
571− long user_bo_count;
572−
573− struct drm_i915_error_object *wa_ctx;
574− struct drm_i915_error_object *default_state;
575−
576− struct drm_i915_error_request {
577− long jiffies;
578− pid_t pid;
579− u32 context;
580− int priority;
581− int ban_score;
582− u32 seqno;
583− u32 head;
584− u32 tail;
585− } *requests, execlist[EXECLIST_MAX_PORTS];
586− unsigned int num_ports;
587−
588− struct drm_i915_error_waiter {
589− char comm[TASK_COMM_LEN];
590− pid_t pid;
591− u32 seqno;
592− } *waiters;
593−
594− struct {
595− u32 gfx_mode;
596− union {
597− u64 pdp[4];
598− u32 pp_dir_base;
599− };
600− } vm_info;
601− } engine[I915_NUM_ENGINES];
602−
603− struct drm_i915_error_buffer {
604− u32 size;
605− u32 name;
606− u32 rseqno[I915_NUM_ENGINES], wseqno;
607− u64 gtt_offset;
608− u32 read_domains;
609− u32 write_domain;
610− s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
611− u32 tiling:2;
612− u32 dirty:1;
613− u32 purgeable:1;
614− u32 userptr:1;
615− s32 engine:4;
616− u32 cache_level:3;
617− } *active_bo[I915_NUM_ENGINES], *pinned_bo;
618− u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
619− struct i915_address_space *active_vm[I915_NUM_ENGINES];
620−};
621−
622458 enum i915_cache_level {
623459 I915_CACHE_NONE = 0,
624460 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
@@ -766,12 +602,13 @@ struct i915_psr { · 141 unmodified lines
766602 bool active;
767603 struct delayed_work work;
768604 unsigned busy_frontbuffer_bits;
769− bool psr2_support;
770− bool aux_frame_sync;
605+ bool sink_psr2_support;
771606 bool link_standby;
772− bool y_cord_support;
773607 bool colorimetry_support;
774608 bool alpm;
609+ bool has_hw_tracking;
610+ bool psr2_enabled;
611+ u8 sink_sync_latency;
775612
776613 void (*enable_source)(struct intel_dp *,
777614 const struct intel_crtc_state *);
@@ -1146,16 +983,6 @@ struct i915_gem_mm { · 368 unmodified lines
1146983 u32 object_count;
1147984 };
1148985
1149−struct drm_i915_error_state_buf {
1150− struct drm_i915_private *i915;
1151− unsigned bytes;
1152− unsigned size;
1153− int err;
1154− u8 *buf;
1155− loff_t start;
1156− loff_t pos;
1157−};
1158−
1159986 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
1160987
1161988 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
@@ -1164,102 +991,6 @@ struct drm_i915_error_state_buf { · 2 unmodified lines
1164991 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1165992 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1166993
1167−struct i915_gpu_error {
1168− /* For hangcheck timer */
1169−#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1170−#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1171−
1172− struct delayed_work hangcheck_work;
1173−
1174− /* For reset and error_state handling. */
1175− spinlock_t lock;
1176− /* Protected by the above dev->gpu_error.lock. */
1177− struct i915_gpu_state *first_error;
1178−
1179− atomic_t pending_fb_pin;
1180−
1181− unsigned long missed_irq_rings;
1182−
1183− /**
1184− * State variable controlling the reset flow and count
1185− *
1186− * This is a counter which gets incremented when reset is triggered,
1187− *
1188− * Before the reset commences, the I915_RESET_BACKOFF bit is set
1189− * meaning that any waiters holding onto the struct_mutex should
1190− * relinquish the lock immediately in order for the reset to start.
1191− *
1192− * If reset is not completed succesfully, the I915_WEDGE bit is
1193− * set meaning that hardware is terminally sour and there is no
1194− * recovery. All waiters on the reset_queue will be woken when
1195− * that happens.
1196− *
1197− * This counter is used by the wait_seqno code to notice that reset
1198− * event happened and it needs to restart the entire ioctl (since most
1199− * likely the seqno it waited for won't ever signal anytime soon).
1200− *
1201− * This is important for lock-free wait paths, where no contended lock
1202− * naturally enforces the correct ordering between the bail-out of the
1203− * waiter and the gpu reset work code.
1204− */
1205− unsigned long reset_count;
1206−
1207− /**
1208− * flags: Control various stages of the GPU reset
1209− *
1210− * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1211− * other users acquiring the struct_mutex. To do this we set the
1212− * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1213− * and then check for that bit before acquiring the struct_mutex (in
1214− * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1215− * secondary role in preventing two concurrent global reset attempts.
1216− *
1217− * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1218− * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1219− * but it may be held by some long running waiter (that we cannot
1220− * interrupt without causing trouble). Once we are ready to do the GPU
1221− * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1222− * they already hold the struct_mutex and want to participate they can
1223− * inspect the bit and do the reset directly, otherwise the worker
1224− * waits for the struct_mutex.
1225− *
1226− * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
1227− * acquire the struct_mutex to reset an engine, we need an explicit
1228− * flag to prevent two concurrent reset attempts in the same engine.
1229− * As the number of engines continues to grow, allocate the flags from
1230− * the most significant bits.
1231− *
1232− * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1233− * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1234− * i915_request_alloc(), this bit is checked and the sequence
1235− * aborted (with -EIO reported to userspace) if set.
1236− */
1237− unsigned long flags;
1238−#define I915_RESET_BACKOFF 0
1239−#define I915_RESET_HANDOFF 1
1240−#define I915_RESET_MODESET 2
1241−#define I915_WEDGED (BITS_PER_LONG - 1)
1242−#define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
1243−
1244− /** Number of times an engine has been reset */
1245− u32 reset_engine_count[I915_NUM_ENGINES];
1246−
1247− /**
1248− * Waitqueue to signal when a hang is detected. Used to for waiters
1249− * to release the struct_mutex for the reset to procede.
1250− */
1251− wait_queue_head_t wait_queue;
1252−
1253− /**
1254− * Waitqueue to signal when the reset has completed. Used by clients
1255− * that wait for dev_priv->mm.wedged to settle.
1256− */
1257− wait_queue_head_t reset_queue;
1258−
1259− /* For missed irq/seqno simulation. */
1260− unsigned long test_irq_rings;
1261−};
1262−
1263994 enum modeset_restore {
1264995 MODESET_ON_LID_OPEN,
1265996 MODESET_DONE,
@@ -1451,11 +1182,12 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, · 185 unmodified lines
14511182 }
14521183
14531184 struct skl_ddb_allocation {
1454− struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1455− struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1185+ /* packed/y */
1186+ struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1187+ struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
14561188 };
14571189
1458−struct skl_wm_values {
1190+struct skl_ddb_values {
14591191 unsigned dirty_pipes;
14601192 struct skl_ddb_allocation ddb;
14611193 };
@@ -1470,6 +1202,7 @@ struct skl_wm_level { · 8 unmodified lines
14701202 struct skl_wm_params {
14711203 bool x_tiled, y_tiled;
14721204 bool rc_surface;
1205+ bool is_planar;
14731206 uint32_t width;
14741207 uint8_t cpp;
14751208 uint32_t plane_pixel_rate;
@@ -1860,6 +1593,8 @@ struct drm_i915_private { · 384 unmodified lines
18601593
18611594 struct intel_gvt *gvt;
18621595
1596+ struct intel_wopcm wopcm;
1597+
18631598 struct intel_huc huc;
18641599 struct intel_guc guc;
18651600
@@ -2152,7 +1887,7 @@ struct drm_i915_private { · 286 unmodified lines
21521887 /* current hardware state */
21531888 union {
21541889 struct ilk_wm_values hw;
2155− struct skl_wm_values skl_hw;
1890+ struct skl_ddb_values skl_hw;
21561891 struct vlv_wm_values vlv;
21571892 struct g4x_wm_values g4x;
21581893 };
@@ -2392,6 +2127,11 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) · 233 unmodified lines
23922127 return to_i915(dev_get_drvdata(kdev));
23932128 }
23942129
2130+static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2131+{
2132+ return container_of(wopcm, struct drm_i915_private, wopcm);
2133+}
2134+
23952135 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
23962136 {
23972137 return container_of(guc, struct drm_i915_private, guc);
@@ -2411,8 +2151,10 @@ static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc) · 13 unmodified lines
24112151
24122152 /* Iterator over subset of engines selected by mask */
24132153 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2414− for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2415− tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2154+ for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
2155+ (tmp__) ? \
2156+ ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2157+ 0;)
24162158
24172159 enum hdmi_force_audio {
24182160 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
@@ -2963,10 +2705,11 @@ extern void i915_driver_unload(struct drm_device *dev); · 544 unmodified lines
29632705 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
29642706 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
29652707
2966−#define I915_RESET_QUIET BIT(0)
2967−extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
2708+extern void i915_reset(struct drm_i915_private *i915,
2709+ unsigned int stalled_mask,
2710+ const char *reason);
29682711 extern int i915_reset_engine(struct intel_engine_cs *engine,
2969− unsigned int flags);
2712+ const char *reason);
29702713
29712714 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
29722715 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
@@ -3014,10 +2757,12 @@ static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) · 41 unmodified lines
30142757 &dev_priv->gpu_error.hangcheck_work, delay);
30152758 }
30162759
3017−__printf(3, 4)
2760+__printf(4, 5)
30182761 void i915_handle_error(struct drm_i915_private *dev_priv,
30192762 u32 engine_mask,
2763+ unsigned long flags,
30202764 const char *fmt, ...);
2765+#define I915_ERROR_CAPTURE BIT(0)
30212766
30222767 extern void intel_irq_init(struct drm_i915_private *dev_priv);
30232768 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
@@ -3132,8 +2877,8 @@ int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, · 108 unmodified lines
31322877 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
31332878 struct drm_file *file_priv);
31342879 void i915_gem_sanitize(struct drm_i915_private *i915);
3135−int i915_gem_load_init(struct drm_i915_private *dev_priv);
3136−void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
2880+int i915_gem_init_early(struct drm_i915_private *dev_priv);
2881+void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
31372882 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
31382883 int i915_gem_freeze(struct drm_i915_private *dev_priv);
31392884 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
@@ -3388,13 +3133,15 @@ static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, · 248 unmodified lines
33883133 struct i915_request *
33893134 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
33903135 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3391−void i915_gem_reset(struct drm_i915_private *dev_priv);
3136+void i915_gem_reset(struct drm_i915_private *dev_priv,
3137+ unsigned int stalled_mask);
33923138 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
33933139 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
33943140 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
33953141 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
33963142 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3397− struct i915_request *request);
3143+ struct i915_request *request,
3144+ bool stalled);
33983145
33993146 void i915_gem_init_mmio(struct drm_i915_private *i915);
34003147 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
@@ -3589,64 +3336,6 @@ static inline int i915_debugfs_connector_add(struct drm_connector *connector) · 188 unmodified lines
35893336 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
35903337 #endif
35913338
3592−/* i915_gpu_error.c */
3593−#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3594−
3595−__printf(2, 3)
3596−void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3597−int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3598− const struct i915_gpu_state *gpu);
3599−int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3600− struct drm_i915_private *i915,
3601− size_t count, loff_t pos);
3602−static inline void i915_error_state_buf_release(
3603− struct drm_i915_error_state_buf *eb)
3604−{
3605− kfree(eb->buf);
3606−}
3607−
3608−struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3609−void i915_capture_error_state(struct drm_i915_private *dev_priv,
3610− u32 engine_mask,
3611− const char *error_msg);
3612−
3613−static inline struct i915_gpu_state *
3614−i915_gpu_state_get(struct i915_gpu_state *gpu)
3615−{
3616− kref_get(&gpu->ref);
3617− return gpu;
3618−}
3619−
3620−void __i915_gpu_state_free(struct kref *kref);
3621−static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3622−{
3623− if (gpu)
3624− kref_put(&gpu->ref, __i915_gpu_state_free);
3625−}
3626−
3627−struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3628−void i915_reset_error_state(struct drm_i915_private *i915);
3629−
3630−#else
3631−
3632−static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3633− u32 engine_mask,
3634− const char *error_msg)
3635−{
3636−}
3637−
3638−static inline struct i915_gpu_state *
3639−i915_first_error_state(struct drm_i915_private *i915)
3640−{
3641− return NULL;
3642−}
3643−
3644−static inline void i915_reset_error_state(struct drm_i915_private *i915)
3645−{
3646−}
3647−
3648−#endif
3649−
36503339 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
36513340
36523341 /* i915_cmd_parser.c */
drivers/gpu/drm/i915/i915_gem.c+161−76
@@ -35,6 +35,7 @@ · 34 unmodified lines
3535 #include "intel_drv.h"
3636 #include "intel_frontbuffer.h"
3737 #include "intel_mocs.h"
38+#include "intel_workarounds.h"
3839 #include "i915_gemfs.h"
3940 #include <linux/dma-fence-array.h>
4041 #include <linux/kthread.h>
@@ -136,6 +137,100 @@ int i915_mutex_lock_interruptible(struct drm_device *dev) · 95 unmodified lines
136137 return 0;
137138 }
138139
140+static u32 __i915_gem_park(struct drm_i915_private *i915)
141+{
142+ lockdep_assert_held(&i915->drm.struct_mutex);
143+ GEM_BUG_ON(i915->gt.active_requests);
144+
145+ if (!i915->gt.awake)
146+ return I915_EPOCH_INVALID;
147+
148+ GEM_BUG_ON(i915->gt.epoch == I915_EPOCH_INVALID);
149+
150+ /*
151+ * Be paranoid and flush a concurrent interrupt to make sure
152+ * we don't reactivate any irq tasklets after parking.
153+ *
154+ * FIXME: Note that even though we have waited for execlists to be idle,
155+ * there may still be an in-flight interrupt even though the CSB
156+ * is now empty. synchronize_irq() makes sure that a residual interrupt
157+ * is completed before we continue, but it doesn't prevent the HW from
158+ * raising a spurious interrupt later. To complete the shield we should
159+ * coordinate disabling the CS irq with flushing the interrupts.
160+ */
161+ synchronize_irq(i915->drm.irq);
162+
163+ intel_engines_park(i915);
164+ i915_gem_timelines_park(i915);
165+
166+ i915_pmu_gt_parked(i915);
167+
168+ i915->gt.awake = false;
169+
170+ if (INTEL_GEN(i915) >= 6)
171+ gen6_rps_idle(i915);
172+
173+ intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ);
174+
175+ intel_runtime_pm_put(i915);
176+
177+ return i915->gt.epoch;
178+}
179+
180+void i915_gem_park(struct drm_i915_private *i915)
181+{
182+ lockdep_assert_held(&i915->drm.struct_mutex);
183+ GEM_BUG_ON(i915->gt.active_requests);
184+
185+ if (!i915->gt.awake)
186+ return;
187+
188+ /* Defer the actual call to __i915_gem_park() to prevent ping-pongs */
189+ mod_delayed_work(i915->wq, &i915->gt.idle_work, msecs_to_jiffies(100));
190+}
191+
192+void i915_gem_unpark(struct drm_i915_private *i915)
193+{
194+ lockdep_assert_held(&i915->drm.struct_mutex);
195+ GEM_BUG_ON(!i915->gt.active_requests);
196+
197+ if (i915->gt.awake)
198+ return;
199+
200+ intel_runtime_pm_get_noresume(i915);
201+
202+ /*
203+ * It seems that the DMC likes to transition between the DC states a lot
204+ * when there are no connected displays (no active power domains) during
205+ * command submission.
206+ *
207+ * This activity has negative impact on the performance of the chip with
208+ * huge latencies observed in the interrupt handler and elsewhere.
209+ *
210+ * Work around it by grabbing a GT IRQ power domain whilst there is any
211+ * GT activity, preventing any DC state transitions.
212+ */
213+ intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
214+
215+ i915->gt.awake = true;
216+ if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */
217+ i915->gt.epoch = 1;
218+
219+ intel_enable_gt_powersave(i915);
220+ i915_update_gfx_val(i915);
221+ if (INTEL_GEN(i915) >= 6)
222+ gen6_rps_busy(i915);
223+ i915_pmu_gt_unparked(i915);
224+
225+ intel_engines_unpark(i915);
226+
227+ i915_queue_hangcheck(i915);
228+
229+ queue_delayed_work(i915->wq,
230+ &i915->gt.retire_work,
231+ round_jiffies_up_relative(HZ));
232+}
233+
139234 int
140235 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
141236 struct drm_file *file)
@@ -2896,20 +2991,6 @@ i915_gem_find_active_request(struct intel_engine_cs *engine) · 2754 unmodified lines
28962991 return active;
28972992 }
28982993
2899−static bool engine_stalled(struct intel_engine_cs *engine)
2900−{
2901− if (!engine->hangcheck.stalled)
2902− return false;
2903−
2904− /* Check for possible seqno movement after hang declaration */
2905− if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) {
2906− DRM_DEBUG_DRIVER("%s pardoned\n", engine->name);
2907− return false;
2908− }
2909−
2910− return true;
2911−}
2912−
29132994 /*
29142995 * Ensure irq handler finishes, and not run again.
29152996 * Also return the active request so that we only search for it once.
@@ -2998,6 +3079,7 @@ int i915_gem_reset_prepare(struct drm_i915_private *dev_priv) · 82 unmodified lines
29983079 }
29993080
30003081 i915_gem_revoke_fences(dev_priv);
3082+ intel_uc_sanitize(dev_priv);
30013083
30023084 return err;
30033085 }
@@ -3047,7 +3129,8 @@ static void engine_skip_context(struct i915_request *request) · 43 unmodified lines
30473129 /* Returns the request if it was guilty of the hang */
30483130 static struct i915_request *
30493131 i915_gem_reset_request(struct intel_engine_cs *engine,
3050− struct i915_request *request)
3132+ struct i915_request *request,
3133+ bool stalled)
30513134 {
30523135 /* The guilty request will get skipped on a hung engine.
30533136 *
@@ -3070,7 +3153,15 @@ i915_gem_reset_request(struct intel_engine_cs *engine, · 16 unmodified lines
30703153 * subsequent hangs.
30713154 */
30723155
3073− if (engine_stalled(engine)) {
3156+ if (i915_request_completed(request)) {
3157+ GEM_TRACE("%s pardoned global=%d (fence %llx:%d), current %d\n",
3158+ engine->name, request->global_seqno,
3159+ request->fence.context, request->fence.seqno,
3160+ intel_engine_get_seqno(engine));
3161+ stalled = false;
3162+ }
3163+
3164+ if (stalled) {
30743165 i915_gem_context_mark_guilty(request->ctx);
30753166 skip_request(request);
30763167
@@ -3101,7 +3192,8 @@ i915_gem_reset_request(struct intel_engine_cs *engine, · 24 unmodified lines
31013192 }
31023193
31033194 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3104− struct i915_request *request)
3195+ struct i915_request *request,
3196+ bool stalled)
31053197 {
31063198 /*
31073199 * Make sure this write is visible before we re-enable the interrupt
@@ -3111,7 +3203,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine, · 3 unmodified lines
31113203 smp_store_mb(engine->irq_posted, 0);
31123204
31133205 if (request)
3114− request = i915_gem_reset_request(engine, request);
3206+ request = i915_gem_reset_request(engine, request, stalled);
31153207
31163208 if (request) {
31173209 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
@@ -3122,7 +3214,8 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine, · 4 unmodified lines
31223214 engine->reset_hw(engine, request);
31233215 }
31243216
3125−void i915_gem_reset(struct drm_i915_private *dev_priv)
3217+void i915_gem_reset(struct drm_i915_private *dev_priv,
3218+ unsigned int stalled_mask)
31263219 {
31273220 struct intel_engine_cs *engine;
31283221 enum intel_engine_id id;
@@ -3134,7 +3227,9 @@ void i915_gem_reset(struct drm_i915_private *dev_priv) · 5 unmodified lines
31343227 for_each_engine(engine, dev_priv, id) {
31353228 struct i915_gem_context *ctx;
31363229
3137− i915_gem_reset_engine(engine, engine->hangcheck.active_request);
3230+ i915_gem_reset_engine(engine,
3231+ engine->hangcheck.active_request,
3232+ stalled_mask & ENGINE_MASK(id));
31383233 ctx = fetch_and_zero(&engine->last_retired_context);
31393234 if (ctx)
31403235 engine->context_unpin(engine, ctx);
@@ -3160,13 +3255,6 @@ void i915_gem_reset(struct drm_i915_private *dev_priv) · 19 unmodified lines
31603255 }
31613256
31623257 i915_gem_restore_fences(dev_priv);
3163−
3164− if (dev_priv->gt.awake) {
3165− intel_sanitize_gt_powersave(dev_priv);
3166− intel_enable_gt_powersave(dev_priv);
3167− if (INTEL_GEN(dev_priv) >= 6)
3168− gen6_rps_busy(dev_priv);
3169− }
31703258 }
31713259
31723260 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
@@ -3192,6 +3280,9 @@ void i915_gem_reset_finish(struct drm_i915_private *dev_priv) · 19 unmodified lines
31923280
31933281 static void nop_submit_request(struct i915_request *request)
31943282 {
3283+ GEM_TRACE("%s fence %llx:%d -> -EIO\n",
3284+ request->engine->name,
3285+ request->fence.context, request->fence.seqno);
31953286 dma_fence_set_error(&request->fence, -EIO);
31963287
31973288 i915_request_submit(request);
@@ -3201,6 +3292,9 @@ static void nop_complete_submit_request(struct i915_request *request) · 3 unmodified lines
32013292 {
32023293 unsigned long flags;
32033294
3295+ GEM_TRACE("%s fence %llx:%d -> -EIO\n",
3296+ request->engine->name,
3297+ request->fence.context, request->fence.seqno);
32043298 dma_fence_set_error(&request->fence, -EIO);
32053299
32063300 spin_lock_irqsave(&request->engine->timeline->lock, flags);
@@ -3214,6 +3308,8 @@ void i915_gem_set_wedged(struct drm_i915_private *i915) · 7 unmodified lines
32143308 struct intel_engine_cs *engine;
32153309 enum intel_engine_id id;
32163310
3311+ GEM_TRACE("start\n");
3312+
32173313 if (drm_debug & DRM_UT_DRIVER) {
32183314 struct drm_printer p = drm_debug_printer(__func__);
32193315
@@ -3237,6 +3333,9 @@ void i915_gem_set_wedged(struct drm_i915_private *i915) · 17 unmodified lines
32373333 }
32383334 i915->caps.scheduler = 0;
32393335
3336+ /* Even if the GPU reset fails, it should still stop the engines */
3337+ intel_gpu_reset(i915, ALL_ENGINES);
3338+
32403339 /*
32413340 * Make sure no one is running the old callback before we proceed with
32423341 * cancelling requests and resetting the completion tracking. Otherwise
@@ -3278,6 +3377,8 @@ void i915_gem_set_wedged(struct drm_i915_private *i915) · 35 unmodified lines
32783377 i915_gem_reset_finish_engine(engine);
32793378 }
32803379
3380+ GEM_TRACE("end\n");
3381+
32813382 wake_up_all(&i915->gpu_error.reset_queue);
32823383 }
32833384
@@ -3290,7 +3391,10 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915) · 6 unmodified lines
32903391 if (!test_bit(I915_WEDGED, &i915->gpu_error.flags))
32913392 return true;
32923393
3293− /* Before unwedging, make sure that all pending operations
3394+ GEM_TRACE("start\n");
3395+
3396+ /*
3397+ * Before unwedging, make sure that all pending operations
32943398 * are flushed and errored out - we may have requests waiting upon
32953399 * third party fences. We marked all inflight requests as EIO, and
32963400 * every execbuf since returned EIO, for consistency we want all
@@ -3308,7 +3412,8 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915) · 11 unmodified lines
33083412 if (!rq)
33093413 continue;
33103414
3311− /* We can't use our normal waiter as we want to
3415+ /*
3416+ * We can't use our normal waiter as we want to
33123417 * avoid recursively trying to handle the current
33133418 * reset. The basic dma_fence_default_wait() installs
33143419 * a callback for dma_fence_signal(), which is
@@ -3323,8 +3428,11 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915) · 8 unmodified lines
33233428 return false;
33243429 }
33253430 }
3431+ i915_retire_requests(i915);
3432+ GEM_BUG_ON(i915->gt.active_requests);
33263433
3327− /* Undo nop_submit_request. We prevent all new i915 requests from
3434+ /*
3435+ * Undo nop_submit_request. We prevent all new i915 requests from
33283436 * being queued (by disallowing execbuf whilst wedged) so having
33293437 * waited for all active requests above, we know the system is idle
33303438 * and do not have to worry about a thread being inside
@@ -3335,6 +3443,8 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915) · 4 unmodified lines
33353443 intel_engines_reset_default_submission(i915);
33363444 i915_gem_contexts_lost(i915);
33373445
3446+ GEM_TRACE("end\n");
3447+
33383448 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
33393449 clear_bit(I915_WEDGED, &i915->gpu_error.flags);
33403450
@@ -3473,36 +3583,9 @@ i915_gem_idle_work_handler(struct work_struct *work) · 132 unmodified lines
34733583 if (new_requests_since_last_retire(dev_priv))
34743584 goto out_unlock;
34753585
3476− /*
3477− * Be paranoid and flush a concurrent interrupt to make sure
3478− * we don't reactivate any irq tasklets after parking.
3479− *
3480− * FIXME: Note that even though we have waited for execlists to be idle,
3481− * there may still be an in-flight interrupt even though the CSB
3482− * is now empty. synchronize_irq() makes sure that a residual interrupt
3483− * is completed before we continue, but it doesn't prevent the HW from
3484− * raising a spurious interrupt later. To complete the shield we should
3485− * coordinate disabling the CS irq with flushing the interrupts.
3486− */
3487− synchronize_irq(dev_priv->drm.irq);
3488−
3489− intel_engines_park(dev_priv);
3490− i915_gem_timelines_park(dev_priv);
3491−
3492− i915_pmu_gt_parked(dev_priv);
3586+ epoch = __i915_gem_park(dev_priv);
34933587
3494− GEM_BUG_ON(!dev_priv->gt.awake);
3495− dev_priv->gt.awake = false;
3496− epoch = dev_priv->gt.epoch;
3497− GEM_BUG_ON(epoch == I915_EPOCH_INVALID);
34983588 rearm_hangcheck = false;
3499−
3500− if (INTEL_GEN(dev_priv) >= 6)
3501− gen6_rps_idle(dev_priv);
3502−
3503− intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ);
3504−
3505− intel_runtime_pm_put(dev_priv);
35063589 out_unlock:
35073590 mutex_unlock(&dev_priv->drm.struct_mutex);
35083591
@@ -3666,16 +3749,7 @@ static int wait_for_engines(struct drm_i915_private *i915) · 157 unmodified lines
36663749 if (wait_for(intel_engines_are_idle(i915), I915_IDLE_ENGINES_TIMEOUT)) {
36673750 dev_err(i915->drm.dev,
36683751 "Failed to idle engines, declaring wedged!\n");
3669− if (drm_debug & DRM_UT_DRIVER) {
3670− struct drm_printer p = drm_debug_printer(__func__);
3671− struct intel_engine_cs *engine;
3672− enum intel_engine_id id;
3673−
3674− for_each_engine(engine, i915, id)
3675− intel_engine_dump(engine, &p,
3676− "%s\n", engine->name);
3677− }
3678−
3752+ GEM_TRACE_DUMP();
36793753 i915_gem_set_wedged(i915);
36803754 return -EIO;
36813755 }
@@ -4088,9 +4162,10 @@ out: · 406 unmodified lines
40884162 }
40894163
40904164 /*
4091− * Prepare buffer for display plane (scanout, cursors, etc).
4092− * Can be called from an uninterruptible phase (modesetting) and allows
4093− * any flushes to be pipelined (for pageflips).
4165+ * Prepare buffer for display plane (scanout, cursors, etc). Can be called from
4166+ * an uninterruptible phase (modesetting) and allows any flushes to be pipelined
4167+ * (for pageflips). We only flush the caches while preparing the buffer for
4168+ * display, the callers are responsible for frontbuffer flush.
40944169 */
40954170 struct i915_vma *
40964171 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
@@ -4146,9 +4221,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, · 49 unmodified lines
41464221
41474222 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
41484223
4149− /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
41504224 __i915_gem_object_flush_for_display(obj);
4151− intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
41524225
41534226 /* It should now be out of any other write domains, and we can update
41544227 * the domain values for our changes.
@@ -4973,6 +5046,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv) · 818 unmodified lines
49735046 * machines is a good idea, we don't - just in case it leaves the
49745047 * machine in an unusable condition.
49755048 */
5049+ intel_uc_sanitize(dev_priv);
49765050 i915_gem_sanitize(dev_priv);
49775051
49785052 intel_runtime_pm_put(dev_priv);
@@ -5118,6 +5192,8 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) · 139 unmodified lines
51185192 }
51195193 }
51205194
5195+ intel_gt_workarounds_apply(dev_priv);
5196+
51215197 i915_gem_init_swizzling(dev_priv);
51225198
51235199 /*
@@ -5140,6 +5216,12 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) · 16 unmodified lines
51405216 goto out;
51415217 }
51425218
5219+ ret = intel_wopcm_init_hw(&dev_priv->wopcm);
5220+ if (ret) {
5221+ DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
5222+ goto out;
5223+ }
5224+
51435225 /* We can't enable contexts until all firmware is loaded */
51445226 ret = intel_uc_init_hw(dev_priv);
51455227 if (ret) {
@@ -5297,6 +5379,10 @@ int i915_gem_init(struct drm_i915_private *dev_priv) · 151 unmodified lines
52975379 if (ret)
52985380 return ret;
52995381
5382+ ret = intel_wopcm_init(&dev_priv->wopcm);
5383+ if (ret)
5384+ return ret;
5385+
53005386 ret = intel_uc_init_misc(dev_priv);
53015387 if (ret)
53025388 return ret;
@@ -5478,8 +5564,7 @@ static void i915_gem_init__mm(struct drm_i915_private *i915) · 175 unmodified lines
54785564 INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);
54795565 }
54805566
5481−int
5482−i915_gem_load_init(struct drm_i915_private *dev_priv)
5567+int i915_gem_init_early(struct drm_i915_private *dev_priv)
54835568 {
54845569 int err = -ENOMEM;
54855570
@@ -5554,7 +5639,7 @@ err_out: · 68 unmodified lines
55545639 return err;
55555640 }
55565641
5557−void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
5642+void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
55585643 {
55595644 i915_gem_drain_freed_objects(dev_priv);
55605645 GEM_BUG_ON(!llist_empty(&dev_priv->mm.free_list));
drivers/gpu/drm/i915/i915_gem.h+7−0
@@ -27,6 +27,8 @@ · 26 unmodified lines
2727
2828 #include <linux/bug.h>
2929
30+struct drm_i915_private;
31+
3032 #ifdef CONFIG_DRM_I915_DEBUG_GEM
3133 #define GEM_BUG_ON(condition) do { if (unlikely((condition))) { \
3234 pr_err("%s:%d GEM_BUG_ON(%s)\n", \
@@ -53,10 +55,15 @@ · 20 unmodified lines
5355
5456 #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GEM)
5557 #define GEM_TRACE(...) trace_printk(__VA_ARGS__)
58+#define GEM_TRACE_DUMP() ftrace_dump(DUMP_ALL)
5659 #else
5760 #define GEM_TRACE(...) do { } while (0)
61+#define GEM_TRACE_DUMP() do { } while (0)
5862 #endif
5963
6064 #define I915_NUM_ENGINES 8
6165
66+void i915_gem_park(struct drm_i915_private *i915);
67+void i915_gem_unpark(struct drm_i915_private *i915);
68+
6269 #endif /* __I915_GEM_H__ */
drivers/gpu/drm/i915/i915_gem_batch_pool.c+6−24
@@ -1,29 +1,11 @@
11 /*
2− * Copyright © 2014 Intel Corporation
3− *
4− * Permission is hereby granted, free of charge, to any person obtaining a
5− * copy of this software and associated documentation files (the "Software"),
6− * to deal in the Software without restriction, including without limitation
7− * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8− * and/or sell copies of the Software, and to permit persons to whom the
9− * Software is furnished to do so, subject to the following conditions:
10− *
11− * The above copyright notice and this permission notice (including the next
12− * paragraph) shall be included in all copies or substantial portions of the
13− * Software.
14− *
15− * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16− * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17− * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18− * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19− * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20− * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21− * IN THE SOFTWARE.
2+ * SPDX-License-Identifier: MIT
223 *
4+ * Copyright © 2014-2018 Intel Corporation
235 */
246
25−#include "i915_drv.h"
267 #include "i915_gem_batch_pool.h"
8+#include "i915_drv.h"
279
2810 /**
2911 * DOC: batch pool
@@ -41,11 +23,11 @@ · 11 unmodified lines
4123
4224 /**
4325 * i915_gem_batch_pool_init() - initialize a batch buffer pool
44− * @engine: the associated request submission engine
4526 * @pool: the batch buffer pool
27+ * @engine: the associated request submission engine
4628 */
47−void i915_gem_batch_pool_init(struct intel_engine_cs *engine,
48− struct i915_gem_batch_pool *pool)
29+void i915_gem_batch_pool_init(struct i915_gem_batch_pool *pool,
30+ struct intel_engine_cs *engine)
4931 {
5032 int n;
5133
drivers/gpu/drm/i915/i915_gem_batch_pool.h+5−24
@@ -1,31 +1,13 @@
11 /*
2− * Copyright © 2014 Intel Corporation
3− *
4− * Permission is hereby granted, free of charge, to any person obtaining a
5− * copy of this software and associated documentation files (the "Software"),
6− * to deal in the Software without restriction, including without limitation
7− * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8− * and/or sell copies of the Software, and to permit persons to whom the
9− * Software is furnished to do so, subject to the following conditions:
10− *
11− * The above copyright notice and this permission notice (including the next
12− * paragraph) shall be included in all copies or substantial portions of the
13− * Software.
14− *
15− * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16− * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17− * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18− * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19− * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20− * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21− * IN THE SOFTWARE.
2+ * SPDX-License-Identifier: MIT
223 *
4+ * Copyright © 2014-2018 Intel Corporation
235 */
246
257 #ifndef I915_GEM_BATCH_POOL_H
268 #define I915_GEM_BATCH_POOL_H
279
28−#include "i915_drv.h"
10+#include <linux/types.h>
2911
3012 struct intel_engine_cs;
3113
@@ -34,9 +16,8 @@ struct i915_gem_batch_pool { · 2 unmodified lines
3416 struct list_head cache_list[4];
3517 };
3618
37−/* i915_gem_batch_pool.c */
38−void i915_gem_batch_pool_init(struct intel_engine_cs *engine,
39− struct i915_gem_batch_pool *pool);
19+void i915_gem_batch_pool_init(struct i915_gem_batch_pool *pool,
20+ struct intel_engine_cs *engine);
4021 void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool);
4122 struct drm_i915_gem_object*
4223 i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size);
drivers/gpu/drm/i915/i915_gem_context.c+9−2
@@ -90,6 +90,7 @@ · 89 unmodified lines
9090 #include <drm/i915_drm.h>
9191 #include "i915_drv.h"
9292 #include "i915_trace.h"
93+#include "intel_workarounds.h"
9394
9495 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
9596
@@ -318,12 +319,13 @@ __create_hw_context(struct drm_i915_private *dev_priv, · 222 unmodified lines
318319 ctx->desc_template =
319320 default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
320321
321− /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
322+ /*
323+ * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
322324 * present or not in use we still need a small bias as ring wraparound
323325 * at offset 0 sometimes hangs. No idea why.
324326 */
325327 if (USES_GUC(dev_priv))
326− ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
328+ ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias;
327329 else
328330 ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
329331
@@ -458,11 +460,16 @@ static bool needs_preempt_context(struct drm_i915_private *i915) · 128 unmodified lines
458460 int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
459461 {
460462 struct i915_gem_context *ctx;
463+ int ret;
461464
462465 /* Reassure ourselves we are only called once */
463466 GEM_BUG_ON(dev_priv->kernel_context);
464467 GEM_BUG_ON(dev_priv->preempt_context);
465468
469+ ret = intel_ctx_workarounds_init(dev_priv);
470+ if (ret)
471+ return ret;
472+
466473 INIT_LIST_HEAD(&dev_priv->contexts.list);
467474 INIT_WORK(&dev_priv->contexts.free_work, contexts_free_worker);
468475 init_llist_head(&dev_priv->contexts.free_list);
drivers/gpu/drm/i915/i915_gem_execbuffer.c+29−0
@@ -81,6 +81,35 @@ enum { · 80 unmodified lines
8181 * but this remains just a hint as the kernel may choose a new location for
8282 * any object in the future.
8383 *
84+ * At the level of talking to the hardware, submitting a batchbuffer for the
85+ * GPU to execute is to add content to a buffer from which the HW
86+ * command streamer is reading.
87+ *
88+ * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e.
89+ * Execlists, this command is not placed on the same buffer as the
90+ * remaining items.
91+ *
92+ * 2. Add a command to invalidate caches to the buffer.
93+ *
94+ * 3. Add a batchbuffer start command to the buffer; the start command is
95+ * essentially a token together with the GPU address of the batchbuffer
96+ * to be executed.
97+ *
98+ * 4. Add a pipeline flush to the buffer.
99+ *
100+ * 5. Add a memory write command to the buffer to record when the GPU
101+ * is done executing the batchbuffer. The memory write writes the
102+ * global sequence number of the request, ``i915_request::global_seqno``;
103+ * the i915 driver uses the current value in the register to determine
104+ * if the GPU has completed the batchbuffer.
105+ *
106+ * 6. Add a user interrupt command to the buffer. This command instructs
107+ * the GPU to issue an interrupt when the command, pipeline flush and
108+ * memory write are completed.
109+ *
110+ * 7. Inform the hardware of the additional commands added to the buffer
111+ * (by updating the tail pointer).
112+ *
84113 * Processing an execbuf ioctl is conceptually split up into a few phases.
85114 *
86115 * 1. Validation - Ensure all the pointers, handles and flags are valid.
drivers/gpu/drm/i915/i915_gem_stolen.c+94−69
@@ -121,8 +121,8 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv, · 120 unmodified lines
121121
122122 if (stolen[0].start != stolen[1].start ||
123123 stolen[0].end != stolen[1].end) {
124− DRM_DEBUG_KMS("GTT within stolen memory at %pR\n", &ggtt_res);
125− DRM_DEBUG_KMS("Stolen memory adjusted to %pR\n", dsm);
124+ DRM_DEBUG_DRIVER("GTT within stolen memory at %pR\n", &ggtt_res);
125+ DRM_DEBUG_DRIVER("Stolen memory adjusted to %pR\n", dsm);
126126 }
127127 }
128128
@@ -174,18 +174,19 @@ void i915_gem_cleanup_stolen(struct drm_device *dev) · 45 unmodified lines
174174 }
175175
176176 static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv,
177− resource_size_t *base, resource_size_t *size)
177+ resource_size_t *base,
178+ resource_size_t *size)
178179 {
179− uint32_t reg_val = I915_READ(IS_GM45(dev_priv) ?
180− CTG_STOLEN_RESERVED :
181− ELK_STOLEN_RESERVED);
180+ u32 reg_val = I915_READ(IS_GM45(dev_priv) ?
181+ CTG_STOLEN_RESERVED :
182+ ELK_STOLEN_RESERVED);
182183 resource_size_t stolen_top = dev_priv->dsm.end + 1;
183184
184− if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0) {
185− *base = 0;
186− *size = 0;
185+ DRM_DEBUG_DRIVER("%s_STOLEN_RESERVED = %08x\n",
186+ IS_GM45(dev_priv) ? "CTG" : "ELK", reg_val);
187+
188+ if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0)
187189 return;
188− }
189190
190191 /*
191192 * Whether ILK really reuses the ELK register for this is unclear.
@@ -193,30 +194,25 @@ static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv, · 1 unmodified line
193194 */
194195 WARN(IS_GEN5(dev_priv), "ILK stolen reserved found? 0x%08x\n", reg_val);
195196
196− *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;
197+ if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK))
198+ return;
197199
200+ *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;
198201 WARN_ON((reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base);
199202
200− /* On these platforms, the register doesn't have a size field, so the
201− * size is the distance between the base and the top of the stolen
202− * memory. We also have the genuine case where base is zero and there's
203− * nothing reserved. */
204− if (*base == 0)
205− *size = 0;
206− else
207− *size = stolen_top - *base;
203+ *size = stolen_top - *base;
208204 }
209205
210206 static void gen6_get_stolen_reserved(struct drm_i915_private *dev_priv,
211− resource_size_t *base, resource_size_t *size)
207+ resource_size_t *base,
208+ resource_size_t *size)
212209 {
213− uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
210+ u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);
211+
212+ DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = %08x\n", reg_val);
214213
215− if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
216− *base = 0;
217− *size = 0;
214+ if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))
218215 return;
219− }
220216
221217 *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
222218
@@ -239,17 +235,44 @@ static void gen6_get_stolen_reserved(struct drm_i915_private *dev_priv, · 16 unmodified lines
239235 }
240236 }
241237
242−static void gen7_get_stolen_reserved(struct drm_i915_private *dev_priv,
243− resource_size_t *base, resource_size_t *size)
238+static void vlv_get_stolen_reserved(struct drm_i915_private *dev_priv,
239+ resource_size_t *base,
240+ resource_size_t *size)
244241 {
245− uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
242+ u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);
243+ resource_size_t stolen_top = dev_priv->dsm.end + 1;
246244
247− if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
248− *base = 0;
249− *size = 0;
245+ DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = %08x\n", reg_val);
246+
247+ if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))
250248 return;
249+
250+ switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {
251+ default:
252+ MISSING_CASE(reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK);
253+ case GEN7_STOLEN_RESERVED_1M:
254+ *size = 1024 * 1024;
255+ break;
251256 }
252257
258+ /*
259+ * On vlv, the ADDR_MASK portion is left as 0 and HW deduces the
260+ * reserved location as (top - size).
261+ */
262+ *base = stolen_top - *size;
263+}
264+
265+static void gen7_get_stolen_reserved(struct drm_i915_private *dev_priv,
266+ resource_size_t *base,
267+ resource_size_t *size)
268+{
269+ u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);
270+
271+ DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = %08x\n", reg_val);
272+
273+ if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))
274+ return;
275+
253276 *base = reg_val & GEN7_STOLEN_RESERVED_ADDR_MASK;
254277
255278 switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {
@@ -266,15 +289,15 @@ static void gen7_get_stolen_reserved(struct drm_i915_private *dev_priv, · 10 unmodified lines
266289 }
267290
268291 static void chv_get_stolen_reserved(struct drm_i915_private *dev_priv,
269− resource_size_t *base, resource_size_t *size)
292+ resource_size_t *base,
293+ resource_size_t *size)
270294 {
271− uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
295+ u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);
272296
273− if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
274− *base = 0;
275− *size = 0;
297+ DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = %08x\n", reg_val);
298+
299+ if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))
276300 return;
277− }
278301
279302 *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
280303
@@ -298,29 +321,22 @@ static void chv_get_stolen_reserved(struct drm_i915_private *dev_priv, · 17 unmodified lines
298321 }
299322
300323 static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv,
301− resource_size_t *base, resource_size_t *size)
324+ resource_size_t *base,
325+ resource_size_t *size)
302326 {
303− uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
304− resource_size_t stolen_top;
327+ u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);
328+ resource_size_t stolen_top = dev_priv->dsm.end + 1;
305329
306− if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
307− *base = 0;
308− *size = 0;
330+ DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = %08x\n", reg_val);
331+
332+ if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))
309333 return;
310− }
311334
312− stolen_top = dev_priv->dsm.end + 1;
335+ if (!(reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK))
336+ return;
313337
314338 *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
315−
316− /* On these platforms, the register doesn't have a size field, so the
317− * size is the distance between the base and the top of the stolen
318− * memory. We also have the genuine case where base is zero and there's
319− * nothing reserved. */
320− if (*base == 0)
321− *size = 0;
322− else
323− *size = stolen_top - *base;
339+ *size = stolen_top - *base;
324340 }
325341
326342 int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
@@ -353,7 +369,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) · 26 unmodified lines
353369 GEM_BUG_ON(dev_priv->dsm.end <= dev_priv->dsm.start);
354370
355371 stolen_top = dev_priv->dsm.end + 1;
356− reserved_base = 0;
372+ reserved_base = stolen_top;
357373 reserved_size = 0;
358374
359375 switch (INTEL_GEN(dev_priv)) {
@@ -373,8 +389,12 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) · 13 unmodified lines
373389 &reserved_base, &reserved_size);
374390 break;
375391 case 7:
376− gen7_get_stolen_reserved(dev_priv,
377− &reserved_base, &reserved_size);
392+ if (IS_VALLEYVIEW(dev_priv))
393+ vlv_get_stolen_reserved(dev_priv,
394+ &reserved_base, &reserved_size);
395+ else
396+ gen7_get_stolen_reserved(dev_priv,
397+ &reserved_base, &reserved_size);
378398 break;
379399 default:
380400 if (IS_LP(dev_priv))
@@ -386,11 +406,16 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) · 5 unmodified lines
386406 break;
387407 }
388408
389− /* It is possible for the reserved base to be zero, but the register
390− * field for size doesn't have a zero option. */
391− if (reserved_base == 0) {
392− reserved_size = 0;
409+ /*
410+ * Our expectation is that the reserved space is at the top of the
411+ * stolen region and *never* at the bottom. If we see !reserved_base,
412+ * it likely means we failed to read the registers correctly.
413+ */
414+ if (!reserved_base) {
415+ DRM_ERROR("inconsistent reservation %pa + %pa; ignoring\n",
416+ &reserved_base, &reserved_size);
393417 reserved_base = stolen_top;
418+ reserved_size = 0;
394419 }
395420
396421 dev_priv->dsm_reserved =
@@ -406,9 +431,9 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) · 9 unmodified lines
406431 * memory, so just consider the start. */
407432 reserved_total = stolen_top - reserved_base;
408433
409− DRM_DEBUG_KMS("Memory reserved for graphics device: %lluK, usable: %lluK\n",
410− (u64)resource_size(&dev_priv->dsm) >> 10,
411− ((u64)resource_size(&dev_priv->dsm) - reserved_total) >> 10);
434+ DRM_DEBUG_DRIVER("Memory reserved for graphics device: %lluK, usable: %lluK\n",
435+ (u64)resource_size(&dev_priv->dsm) >> 10,
436+ ((u64)resource_size(&dev_priv->dsm) - reserved_total) >> 10);
412437
413438 stolen_usable_start = 0;
414439 /* WaSkipStolenMemoryFirstPage:bdw+ */
@@ -580,8 +605,8 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv · 165 unmodified lines
580605
581606 lockdep_assert_held(&dev_priv->drm.struct_mutex);
582607
583− DRM_DEBUG_KMS("creating preallocated stolen object: stolen_offset=%pa, gtt_offset=%pa, size=%pa\n",
584− &stolen_offset, &gtt_offset, &size);
608+ DRM_DEBUG_DRIVER("creating preallocated stolen object: stolen_offset=%pa, gtt_offset=%pa, size=%pa\n",
609+ &stolen_offset, &gtt_offset, &size);
585610
586611 /* KISS and expect everything to be page-aligned */
587612 if (WARN_ON(size == 0) ||
@@ -599,14 +624,14 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv · 11 unmodified lines
599624 ret = drm_mm_reserve_node(&dev_priv->mm.stolen, stolen);
600625 mutex_unlock(&dev_priv->mm.stolen_lock);
601626 if (ret) {
602− DRM_DEBUG_KMS("failed to allocate stolen space\n");
627+ DRM_DEBUG_DRIVER("failed to allocate stolen space\n");
603628 kfree(stolen);
604629 return NULL;
605630 }
606631
607632 obj = _i915_gem_object_create_stolen(dev_priv, stolen);
608633 if (obj == NULL) {
609− DRM_DEBUG_KMS("failed to allocate stolen object\n");
634+ DRM_DEBUG_DRIVER("failed to allocate stolen object\n");
610635 i915_gem_stolen_remove_node(dev_priv, stolen);
611636 kfree(stolen);
612637 return NULL;
@@ -635,7 +660,7 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv · 22 unmodified lines
635660 size, gtt_offset, obj->cache_level,
636661 0);
637662 if (ret) {
638− DRM_DEBUG_KMS("failed to allocate stolen GTT space\n");
663+ DRM_DEBUG_DRIVER("failed to allocate stolen GTT space\n");
639664 goto err_pages;
640665 }
641666
drivers/gpu/drm/i915/i915_gpu_error.c+1−0
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 #include <linux/zlib.h>
3333 #include <drm/drm_print.h>
3434
35+#include "i915_gpu_error.h"
3536 #include "i915_drv.h"
3637
3738 static inline const struct intel_engine_cs *
drivers/gpu/drm/i915/i915_gpu_error.h+362−0
@@ -0,0 +1,362 @@
1+/*
2+ * SPDX-License-Identifier: MIT
3+ *
4+ * Copyright � 2008-2018 Intel Corporation
5+ */
6+
7+#ifndef _I915_GPU_ERROR_H_
8+#define _I915_GPU_ERROR_H_
9+
10+#include <linux/kref.h>
11+#include <linux/ktime.h>
12+#include <linux/sched.h>
13+
14+#include <drm/drm_mm.h>
15+
16+#include "intel_device_info.h"
17+#include "intel_ringbuffer.h"
18+#include "intel_uc_fw.h"
19+
20+#include "i915_gem.h"
21+#include "i915_gem_gtt.h"
22+#include "i915_params.h"
23+
24+struct drm_i915_private;
25+struct intel_overlay_error_state;
26+struct intel_display_error_state;
27+
28+struct i915_gpu_state {
29+ struct kref ref;
30+ ktime_t time;
31+ ktime_t boottime;
32+ ktime_t uptime;
33+
34+ struct drm_i915_private *i915;
35+
36+ char error_msg[128];
37+ bool simulated;
38+ bool awake;
39+ bool wakelock;
40+ bool suspended;
41+ int iommu;
42+ u32 reset_count;
43+ u32 suspend_count;
44+ struct intel_device_info device_info;
45+ struct intel_driver_caps driver_caps;
46+ struct i915_params params;
47+
48+ struct i915_error_uc {
49+ struct intel_uc_fw guc_fw;
50+ struct intel_uc_fw huc_fw;
51+ struct drm_i915_error_object *guc_log;
52+ } uc;
53+
54+ /* Generic register state */
55+ u32 eir;
56+ u32 pgtbl_er;
57+ u32 ier;
58+ u32 gtier[4], ngtier;
59+ u32 ccid;
60+ u32 derrmr;
61+ u32 forcewake;
62+ u32 error; /* gen6+ */
63+ u32 err_int; /* gen7 */
64+ u32 fault_data0; /* gen8, gen9 */
65+ u32 fault_data1; /* gen8, gen9 */
66+ u32 done_reg;
67+ u32 gac_eco;
68+ u32 gam_ecochk;
69+ u32 gab_ctl;
70+ u32 gfx_mode;
71+
72+ u32 nfence;
73+ u64 fence[I915_MAX_NUM_FENCES];
74+ struct intel_overlay_error_state *overlay;
75+ struct intel_display_error_state *display;
76+
77+ struct drm_i915_error_engine {
78+ int engine_id;
79+ /* Software tracked state */
80+ bool idle;
81+ bool waiting;
82+ int num_waiters;
83+ unsigned long hangcheck_timestamp;
84+ bool hangcheck_stalled;
85+ enum intel_engine_hangcheck_action hangcheck_action;
86+ struct i915_address_space *vm;
87+ int num_requests;
88+ u32 reset_count;
89+
90+ /* position of active request inside the ring */
91+ u32 rq_head, rq_post, rq_tail;
92+
93+ /* our own tracking of ring head and tail */
94+ u32 cpu_ring_head;
95+ u32 cpu_ring_tail;
96+
97+ u32 last_seqno;
98+
99+ /* Register state */
100+ u32 start;
101+ u32 tail;
102+ u32 head;
103+ u32 ctl;
104+ u32 mode;
105+ u32 hws;
106+ u32 ipeir;
107+ u32 ipehr;
108+ u32 bbstate;
109+ u32 instpm;
110+ u32 instps;
111+ u32 seqno;
112+ u64 bbaddr;
113+ u64 acthd;
114+ u32 fault_reg;
115+ u64 faddr;
116+ u32 rc_psmi; /* sleep state */
117+ u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
118+ struct intel_instdone instdone;
119+
120+ struct drm_i915_error_context {
121+ char comm[TASK_COMM_LEN];
122+ pid_t pid;
123+ u32 handle;
124+ u32 hw_id;
125+ int priority;
126+ int ban_score;
127+ int active;
128+ int guilty;
129+ bool bannable;
130+ } context;
131+
132+ struct drm_i915_error_object {
133+ u64 gtt_offset;
134+ u64 gtt_size;
135+ int page_count;
136+ int unused;
137+ u32 *pages[0];
138+ } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
139+
140+ struct drm_i915_error_object **user_bo;
141+ long user_bo_count;
142+
143+ struct drm_i915_error_object *wa_ctx;
144+ struct drm_i915_error_object *default_state;
145+
146+ struct drm_i915_error_request {
147+ long jiffies;
148+ pid_t pid;
149+ u32 context;
150+ int priority;
151+ int ban_score;
152+ u32 seqno;
153+ u32 head;
154+ u32 tail;
155+ } *requests, execlist[EXECLIST_MAX_PORTS];
156+ unsigned int num_ports;
157+
158+ struct drm_i915_error_waiter {
159+ char comm[TASK_COMM_LEN];
160+ pid_t pid;
161+ u32 seqno;
162+ } *waiters;
163+
164+ struct {
165+ u32 gfx_mode;
166+ union {
167+ u64 pdp[4];
168+ u32 pp_dir_base;
169+ };
170+ } vm_info;
171+ } engine[I915_NUM_ENGINES];
172+
173+ struct drm_i915_error_buffer {
174+ u32 size;
175+ u32 name;
176+ u32 rseqno[I915_NUM_ENGINES], wseqno;
177+ u64 gtt_offset;
178+ u32 read_domains;
179+ u32 write_domain;
180+ s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
181+ u32 tiling:2;
182+ u32 dirty:1;
183+ u32 purgeable:1;
184+ u32 userptr:1;
185+ s32 engine:4;
186+ u32 cache_level:3;
187+ } *active_bo[I915_NUM_ENGINES], *pinned_bo;
188+ u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
189+ struct i915_address_space *active_vm[I915_NUM_ENGINES];
190+};
191+
192+struct i915_gpu_error {
193+ /* For hangcheck timer */
194+#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
195+#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
196+
197+ struct delayed_work hangcheck_work;
198+
199+ /* For reset and error_state handling. */
200+ spinlock_t lock;
201+ /* Protected by the above dev->gpu_error.lock. */
202+ struct i915_gpu_state *first_error;
203+
204+ atomic_t pending_fb_pin;
205+
206+ unsigned long missed_irq_rings;
207+
208+ /**
209+ * State variable controlling the reset flow and count
210+ *
211+ * This is a counter which gets incremented when reset is triggered,
212+ *
213+ * Before the reset commences, the I915_RESET_BACKOFF bit is set
214+ * meaning that any waiters holding onto the struct_mutex should
215+ * relinquish the lock immediately in order for the reset to start.
216+ *
217+ * If reset is not completed successfully, the I915_WEDGE bit is
218+ * set meaning that hardware is terminally sour and there is no
219+ * recovery. All waiters on the reset_queue will be woken when
220+ * that happens.
221+ *
222+ * This counter is used by the wait_seqno code to notice that reset
223+ * event happened and it needs to restart the entire ioctl (since most
224+ * likely the seqno it waited for won't ever signal anytime soon).
225+ *
226+ * This is important for lock-free wait paths, where no contended lock
227+ * naturally enforces the correct ordering between the bail-out of the
228+ * waiter and the gpu reset work code.
229+ */
230+ unsigned long reset_count;
231+
232+ /**
233+ * flags: Control various stages of the GPU reset
234+ *
235+ * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
236+ * other users acquiring the struct_mutex. To do this we set the
237+ * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
238+ * and then check for that bit before acquiring the struct_mutex (in
239+ * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
240+ * secondary role in preventing two concurrent global reset attempts.
241+ *
242+ * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
243+ * struct_mutex. We try to acquire the struct_mutex in the reset worker,
244+ * but it may be held by some long running waiter (that we cannot
245+ * interrupt without causing trouble). Once we are ready to do the GPU
246+ * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
247+ * they already hold the struct_mutex and want to participate they can
248+ * inspect the bit and do the reset directly, otherwise the worker
249+ * waits for the struct_mutex.
250+ *
251+ * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
252+ * acquire the struct_mutex to reset an engine, we need an explicit
253+ * flag to prevent two concurrent reset attempts in the same engine.
254+ * As the number of engines continues to grow, allocate the flags from
255+ * the most significant bits.
256+ *
257+ * #I915_WEDGED - If reset fails and we can no longer use the GPU,
258+ * we set the #I915_WEDGED bit. Prior to command submission, e.g.
259+ * i915_request_alloc(), this bit is checked and the sequence
260+ * aborted (with -EIO reported to userspace) if set.
261+ */
262+ unsigned long flags;
263+#define I915_RESET_BACKOFF 0
264+#define I915_RESET_HANDOFF 1
265+#define I915_RESET_MODESET 2
266+#define I915_WEDGED (BITS_PER_LONG - 1)
267+#define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
268+
269+ /** Number of times an engine has been reset */
270+ u32 reset_engine_count[I915_NUM_ENGINES];
271+
272+ /** Set of stalled engines with guilty requests, in the current reset */
273+ u32 stalled_mask;
274+
275+ /** Reason for the current *global* reset */
276+ const char *reason;
277+
278+ /**
279+ * Waitqueue to signal when a hang is detected. Used to for waiters
280+ * to release the struct_mutex for the reset to procede.
281+ */
282+ wait_queue_head_t wait_queue;
283+
284+ /**
285+ * Waitqueue to signal when the reset has completed. Used by clients
286+ * that wait for dev_priv->mm.wedged to settle.
287+ */
288+ wait_queue_head_t reset_queue;
289+
290+ /* For missed irq/seqno simulation. */
291+ unsigned long test_irq_rings;
292+};
293+
294+struct drm_i915_error_state_buf {
295+ struct drm_i915_private *i915;
296+ unsigned int bytes;
297+ unsigned int size;
298+ int err;
299+ u8 *buf;
300+ loff_t start;
301+ loff_t pos;
302+};
303+
304+#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
305+
306+__printf(2, 3)
307+void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
308+int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
309+ const struct i915_gpu_state *gpu);
310+int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
311+ struct drm_i915_private *i915,
312+ size_t count, loff_t pos);
313+
314+static inline void
315+i915_error_state_buf_release(struct drm_i915_error_state_buf *eb)
316+{
317+ kfree(eb->buf);
318+}
319+
320+struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
321+void i915_capture_error_state(struct drm_i915_private *dev_priv,
322+ u32 engine_mask,
323+ const char *error_msg);
324+
325+static inline struct i915_gpu_state *
326+i915_gpu_state_get(struct i915_gpu_state *gpu)
327+{
328+ kref_get(&gpu->ref);
329+ return gpu;
330+}
331+
332+void __i915_gpu_state_free(struct kref *kref);
333+static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
334+{
335+ if (gpu)
336+ kref_put(&gpu->ref, __i915_gpu_state_free);
337+}
338+
339+struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
340+void i915_reset_error_state(struct drm_i915_private *i915);
341+
342+#else
343+
344+static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
345+ u32 engine_mask,
346+ const char *error_msg)
347+{
348+}
349+
350+static inline struct i915_gpu_state *
351+i915_first_error_state(struct drm_i915_private *i915)
352+{
353+ return NULL;
354+}
355+
356+static inline void i915_reset_error_state(struct drm_i915_private *i915)
357+{
358+}
359+
360+#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
361+
362+#endif /* _I915_GPU_ERROR_H_ */
drivers/gpu/drm/i915/i915_irq.c+219−147
@@ -243,6 +243,41 @@ void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, · 242 unmodified lines
243243 spin_unlock_irq(&dev_priv->irq_lock);
244244 }
245245
246+static u32
247+gen11_gt_engine_identity(struct drm_i915_private * const i915,
248+ const unsigned int bank, const unsigned int bit);
249+
250+static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
251+ const unsigned int bank,
252+ const unsigned int bit)
253+{
254+ void __iomem * const regs = i915->regs;
255+ u32 dw;
256+
257+ lockdep_assert_held(&i915->irq_lock);
258+
259+ dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
260+ if (dw & BIT(bit)) {
261+ /*
262+ * According to the BSpec, DW_IIR bits cannot be cleared without
263+ * first servicing the Selector & Shared IIR registers.
264+ */
265+ gen11_gt_engine_identity(i915, bank, bit);
266+
267+ /*
268+ * We locked GT INT DW by reading it. If we want to (try
269+ * to) recover from this succesfully, we need to clear
270+ * our bit, otherwise we are locking the register for
271+ * everybody.
272+ */
273+ raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
274+
275+ return true;
276+ }
277+
278+ return false;
279+}
280+
246281 /**
247282 * ilk_update_display_irq - update DEIMR
248283 * @dev_priv: driver private
@@ -308,17 +343,29 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) · 59 unmodified lines
308343
309344 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
310345 {
346+ WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
347+
311348 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
312349 }
313350
314351 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
315352 {
316− return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
353+ if (INTEL_GEN(dev_priv) >= 11)
354+ return GEN11_GPM_WGBOXPERF_INTR_MASK;
355+ else if (INTEL_GEN(dev_priv) >= 8)
356+ return GEN8_GT_IMR(2);
357+ else
358+ return GEN6_PMIMR;
317359 }
318360
319361 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
320362 {
321− return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
363+ if (INTEL_GEN(dev_priv) >= 11)
364+ return GEN11_GPM_WGBOXPERF_INTR_ENABLE;
365+ else if (INTEL_GEN(dev_priv) >= 8)
366+ return GEN8_GT_IER(2);
367+ else
368+ return GEN6_PMIER;
322369 }
323370
324371 /**
@@ -400,6 +447,18 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m · 75 unmodified lines
400447 /* though a barrier is missing here, but don't really need a one */
401448 }
402449
450+void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
451+{
452+ spin_lock_irq(&dev_priv->irq_lock);
453+
454+ while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
455+ ;
456+
457+ dev_priv->gt_pm.rps.pm_iir = 0;
458+
459+ spin_unlock_irq(&dev_priv->irq_lock);
460+}
461+
403462 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
404463 {
405464 spin_lock_irq(&dev_priv->irq_lock);
@@ -415,12 +474,14 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) · 9 unmodified lines
415474 if (READ_ONCE(rps->interrupts_enabled))
416475 return;
417476
418− if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
419− return;
420−
421477 spin_lock_irq(&dev_priv->irq_lock);
422478 WARN_ON_ONCE(rps->pm_iir);
423− WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
479+
480+ if (INTEL_GEN(dev_priv) >= 11)
481+ WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM));
482+ else
483+ WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
484+
424485 rps->interrupts_enabled = true;
425486 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
426487
@@ -434,9 +495,6 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) · 7 unmodified lines
434495 if (!READ_ONCE(rps->interrupts_enabled))
435496 return;
436497
437− if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
438− return;
439−
440498 spin_lock_irq(&dev_priv->irq_lock);
441499 rps->interrupts_enabled = false;
442500
@@ -453,7 +511,10 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) · 10 unmodified lines
453511 * state of the worker can be discarded.
454512 */
455513 cancel_work_sync(&rps->work);
456− gen6_reset_rps_interrupts(dev_priv);
514+ if (INTEL_GEN(dev_priv) >= 11)
515+ gen11_reset_rps_interrupts(dev_priv);
516+ else
517+ gen6_reset_rps_interrupts(dev_priv);
457518 }
458519
459520 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
@@ -1399,19 +1460,18 @@ static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, · 939 unmodified lines
13991460 }
14001461
14011462 static void
1402−gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1463+gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
14031464 {
14041465 struct intel_engine_execlists * const execlists = &engine->execlists;
14051466 bool tasklet = false;
14061467
1407− if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
1408− if (READ_ONCE(engine->execlists.active)) {
1409− __set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1410− tasklet = true;
1411− }
1468+ if (iir & GT_CONTEXT_SWITCH_INTERRUPT) {
1469+ if (READ_ONCE(engine->execlists.active))
1470+ tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST,
1471+ &engine->irq_posted);
14121472 }
14131473
1414− if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {
1474+ if (iir & GT_RENDER_USER_INTERRUPT) {
14151475 notify_ring(engine);
14161476 tasklet |= USES_GUC_SUBMISSION(engine->i915);
14171477 }
@@ -1466,21 +1526,21 @@ static void gen8_gt_irq_handler(struct drm_i915_private *i915, · 48 unmodified lines
14661526 {
14671527 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
14681528 gen8_cs_irq_handler(i915->engine[RCS],
1469− gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1529+ gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
14701530 gen8_cs_irq_handler(i915->engine[BCS],
1471− gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1531+ gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
14721532 }
14731533
14741534 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
14751535 gen8_cs_irq_handler(i915->engine[VCS],
1476− gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1536+ gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
14771537 gen8_cs_irq_handler(i915->engine[VCS2],
1478− gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1538+ gt_iir[1] >> GEN8_VCS2_IRQ_SHIFT);
14791539 }
14801540
14811541 if (master_ctl & GEN8_GT_VECS_IRQ) {
14821542 gen8_cs_irq_handler(i915->engine[VECS],
1483− gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1543+ gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
14841544 }
14851545
14861546 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
@@ -1627,7 +1687,7 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, · 140 unmodified lines
16271687 int head, tail;
16281688
16291689 spin_lock(&pipe_crc->lock);
1630− if (pipe_crc->source) {
1690+ if (pipe_crc->source && !crtc->base.crc.opened) {
16311691 if (!pipe_crc->entries) {
16321692 spin_unlock(&pipe_crc->lock);
16331693 DRM_DEBUG_KMS("spurious interrupt\n");
@@ -1667,7 +1727,7 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, · 33 unmodified lines
16671727 * On GEN8+ sometimes the second CRC is bonkers as well, so
16681728 * don't trust that one either.
16691729 */
1670− if (pipe_crc->skipped == 0 ||
1730+ if (pipe_crc->skipped <= 0 ||
16711731 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
16721732 pipe_crc->skipped++;
16731733 spin_unlock(&pipe_crc->lock);
@@ -1766,37 +1826,8 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) · 92 unmodified lines
17661826
17671827 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
17681828 {
1769− if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
1770− /* Sample the log buffer flush related bits & clear them out now
1771− * itself from the message identity register to minimize the
1772− * probability of losing a flush interrupt, when there are back
1773− * to back flush interrupts.
1774− * There can be a new flush interrupt, for different log buffer
1775− * type (like for ISR), whilst Host is handling one (for DPC).
1776− * Since same bit is used in message register for ISR & DPC, it
1777− * could happen that GuC sets the bit for 2nd interrupt but Host
1778− * clears out the bit on handling the 1st interrupt.
1779− */
1780− u32 msg, flush;
1781−
1782− msg = I915_READ(SOFT_SCRATCH(15));
1783− flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
1784− INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
1785− if (flush) {
1786− /* Clear the message bits that are handled */
1787− I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
1788−
1789− /* Handle flush interrupt in bottom half */
1790− queue_work(dev_priv->guc.log.runtime.flush_wq,
1791− &dev_priv->guc.log.runtime.flush_work);
1792−
1793− dev_priv->guc.log.flush_interrupt_count++;
1794− } else {
1795− /* Not clearing of unhandled event bits won't result in
1796− * re-triggering of the interrupt.
1797− */
1798− }
1799− }
1829+ if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
1830+ intel_guc_to_host_event_handler(&dev_priv->guc);
18001831 }
18011832
18021833 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
@@ -2762,58 +2793,16 @@ static void __fini_wedge(struct wedge_me *w) · 959 unmodified lines
27622793 (W)->i915; \
27632794 __fini_wedge((W)))
27642795
2765−static __always_inline void
2766−gen11_cs_irq_handler(struct intel_engine_cs * const engine, const u32 iir)
2767−{
2768− gen8_cs_irq_handler(engine, iir, 0);
2769−}
2770−
2771−static void
2772−gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
2773− const unsigned int bank,
2774− const unsigned int engine_n,
2775− const u16 iir)
2776−{
2777− struct intel_engine_cs ** const engine = i915->engine;
2778−
2779− switch (bank) {
2780− case 0:
2781− switch (engine_n) {
2782−
2783− case GEN11_RCS0:
2784− return gen11_cs_irq_handler(engine[RCS], iir);
2785−
2786− case GEN11_BCS:
2787− return gen11_cs_irq_handler(engine[BCS], iir);
2788− }
2789− case 1:
2790− switch (engine_n) {
2791−
2792− case GEN11_VCS(0):
2793− return gen11_cs_irq_handler(engine[_VCS(0)], iir);
2794− case GEN11_VCS(1):
2795− return gen11_cs_irq_handler(engine[_VCS(1)], iir);
2796− case GEN11_VCS(2):
2797− return gen11_cs_irq_handler(engine[_VCS(2)], iir);
2798− case GEN11_VCS(3):
2799− return gen11_cs_irq_handler(engine[_VCS(3)], iir);
2800−
2801− case GEN11_VECS(0):
2802− return gen11_cs_irq_handler(engine[_VECS(0)], iir);
2803− case GEN11_VECS(1):
2804− return gen11_cs_irq_handler(engine[_VECS(1)], iir);
2805− }
2806− }
2807−}
2808−
28092796 static u32
2810−gen11_gt_engine_intr(struct drm_i915_private * const i915,
2811− const unsigned int bank, const unsigned int bit)
2797+gen11_gt_engine_identity(struct drm_i915_private * const i915,
2798+ const unsigned int bank, const unsigned int bit)
28122799 {
28132800 void __iomem * const regs = i915->regs;
28142801 u32 timeout_ts;
28152802 u32 ident;
28162803
2804+ lockdep_assert_held(&i915->irq_lock);
2805+
28172806 raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
28182807
28192808 /*
@@ -2835,42 +2824,101 @@ gen11_gt_engine_intr(struct drm_i915_private * const i915, · 15 unmodified lines
28352824 raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
28362825 GEN11_INTR_DATA_VALID);
28372826
2838− return ident & GEN11_INTR_ENGINE_MASK;
2827+ return ident;
28392828 }
28402829
28412830 static void
2842−gen11_gt_irq_handler(struct drm_i915_private * const i915,
2843− const u32 master_ctl)
2831+gen11_other_irq_handler(struct drm_i915_private * const i915,
2832+ const u8 instance, const u16 iir)
2833+{
2834+ if (instance == OTHER_GTPM_INSTANCE)
2835+ return gen6_rps_irq_handler(i915, iir);
2836+
2837+ WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
2838+ instance, iir);
2839+}
2840+
2841+static void
2842+gen11_engine_irq_handler(struct drm_i915_private * const i915,
2843+ const u8 class, const u8 instance, const u16 iir)
2844+{
2845+ struct intel_engine_cs *engine;
2846+
2847+ if (instance <= MAX_ENGINE_INSTANCE)
2848+ engine = i915->engine_class[class][instance];
2849+ else
2850+ engine = NULL;
2851+
2852+ if (likely(engine))
2853+ return gen8_cs_irq_handler(engine, iir);
2854+
2855+ WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
2856+ class, instance);
2857+}
2858+
2859+static void
2860+gen11_gt_identity_handler(struct drm_i915_private * const i915,
2861+ const u32 identity)
2862+{
2863+ const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
2864+ const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
2865+ const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
2866+
2867+ if (unlikely(!intr))
2868+ return;
2869+
2870+ if (class <= COPY_ENGINE_CLASS)
2871+ return gen11_engine_irq_handler(i915, class, instance, intr);
2872+
2873+ if (class == OTHER_CLASS)
2874+ return gen11_other_irq_handler(i915, instance, intr);
2875+
2876+ WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
2877+ class, instance, intr);
2878+}
2879+
2880+static void
2881+gen11_gt_bank_handler(struct drm_i915_private * const i915,
2882+ const unsigned int bank)
28442883 {
28452884 void __iomem * const regs = i915->regs;
2846− unsigned int bank;
2885+ unsigned long intr_dw;
2886+ unsigned int bit;
28472887
2848− for (bank = 0; bank < 2; bank++) {
2849− unsigned long intr_dw;
2850− unsigned int bit;
2888+ lockdep_assert_held(&i915->irq_lock);
28512889
2852− if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
2853− continue;
2890+ intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
28542891
2855− intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
2892+ if (unlikely(!intr_dw)) {
2893+ DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
2894+ return;
2895+ }
28562896
2857− if (unlikely(!intr_dw)) {
2858− DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
2859− continue;
2860− }
2897+ for_each_set_bit(bit, &intr_dw, 32) {
2898+ const u32 ident = gen11_gt_engine_identity(i915,
2899+ bank, bit);
28612900
2862− for_each_set_bit(bit, &intr_dw, 32) {
2863− const u16 iir = gen11_gt_engine_intr(i915, bank, bit);
2901+ gen11_gt_identity_handler(i915, ident);
2902+ }
28642903
2865− if (unlikely(!iir))
2866− continue;
2904+ /* Clear must be after shared has been served for engine */
2905+ raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
2906+}
28672907
2868− gen11_gt_engine_irq_handler(i915, bank, bit, iir);
2869− }
2908+static void
2909+gen11_gt_irq_handler(struct drm_i915_private * const i915,
2910+ const u32 master_ctl)
2911+{
2912+ unsigned int bank;
28702913
2871− /* Clear must be after shared has been served for engine */
2872− raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
2914+ spin_lock(&i915->irq_lock);
2915+
2916+ for (bank = 0; bank < 2; bank++) {
2917+ if (master_ctl & GEN11_GT_DW_IRQ(bank))
2918+ gen11_gt_bank_handler(i915, bank);
28732919 }
2920+
2921+ spin_unlock(&i915->irq_lock);
28742922 }
28752923
28762924 static irqreturn_t gen11_irq_handler(int irq, void *arg)
@@ -2912,15 +2960,11 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg) · 35 unmodified lines
29122960 return IRQ_HANDLED;
29132961 }
29142962
2915−/**
2916− * i915_reset_device - do process context error handling work
2917− * @dev_priv: i915 device private
2918− *
2919− * Fire an error uevent so userspace can see that a hang or error
2920− * was detected.
2921− */
2922−static void i915_reset_device(struct drm_i915_private *dev_priv)
2963+static void i915_reset_device(struct drm_i915_private *dev_priv,
2964+ u32 engine_mask,
2965+ const char *reason)
29232966 {
2967+ struct i915_gpu_error *error = &dev_priv->gpu_error;
29242968 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
29252969 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
29262970 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
@@ -2936,29 +2980,35 @@ static void i915_reset_device(struct drm_i915_private *dev_priv) · 9 unmodified lines
29362980 i915_wedge_on_timeout(&w, dev_priv, 5*HZ) {
29372981 intel_prepare_reset(dev_priv);
29382982
2983+ error->reason = reason;
2984+ error->stalled_mask = engine_mask;
2985+
29392986 /* Signal that locked waiters should reset the GPU */
2940− set_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags);
2941− wake_up_all(&dev_priv->gpu_error.wait_queue);
2987+ smp_mb__before_atomic();
2988+ set_bit(I915_RESET_HANDOFF, &error->flags);
2989+ wake_up_all(&error->wait_queue);
29422990
29432991 /* Wait for anyone holding the lock to wakeup, without
29442992 * blocking indefinitely on struct_mutex.
29452993 */
29462994 do {
29472995 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2948− i915_reset(dev_priv, 0);
2996+ i915_reset(dev_priv, engine_mask, reason);
29492997 mutex_unlock(&dev_priv->drm.struct_mutex);
29502998 }
2951− } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2999+ } while (wait_on_bit_timeout(&error->flags,
29523000 I915_RESET_HANDOFF,
29533001 TASK_UNINTERRUPTIBLE,
29543002 1));
29553003
3004+ error->stalled_mask = 0;
3005+ error->reason = NULL;
3006+
29563007 intel_finish_reset(dev_priv);
29573008 }
29583009
2959− if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2960− kobject_uevent_env(kobj,
2961− KOBJ_CHANGE, reset_done_event);
3010+ if (!test_bit(I915_WEDGED, &error->flags))
3011+ kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
29623012 }
29633013
29643014 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
@@ -2990,6 +3040,7 @@ static void i915_clear_error_registers(struct drm_i915_private *dev_priv) · 25 unmodified lines
29903040 * i915_handle_error - handle a gpu error
29913041 * @dev_priv: i915 device private
29923042 * @engine_mask: mask representing engines that are hung
3043+ * @flags: control flags
29933044 * @fmt: Error message format string
29943045 *
29953046 * Do some basic checking of register state at error time and
@@ -3000,16 +3051,23 @@ static void i915_clear_error_registers(struct drm_i915_private *dev_priv) · 4 unmodified lines
30003051 */
30013052 void i915_handle_error(struct drm_i915_private *dev_priv,
30023053 u32 engine_mask,
3054+ unsigned long flags,
30033055 const char *fmt, ...)
30043056 {
30053057 struct intel_engine_cs *engine;
30063058 unsigned int tmp;
3007− va_list args;
30083059 char error_msg[80];
3060+ char *msg = NULL;
30093061
3010− va_start(args, fmt);
3011− vscnprintf(error_msg, sizeof(error_msg), fmt, args);
3012− va_end(args);
3062+ if (fmt) {
3063+ va_list args;
3064+
3065+ va_start(args, fmt);
3066+ vscnprintf(error_msg, sizeof(error_msg), fmt, args);
3067+ va_end(args);
3068+
3069+ msg = error_msg;
3070+ }
30133071
30143072 /*
30153073 * In most cases it's guaranteed that we get here with an RPM
@@ -3020,8 +3078,12 @@ void i915_handle_error(struct drm_i915_private *dev_priv, · 4 unmodified lines
30203078 */
30213079 intel_runtime_pm_get(dev_priv);
30223080
3023− i915_capture_error_state(dev_priv, engine_mask, error_msg);
3024− i915_clear_error_registers(dev_priv);
3081+ engine_mask &= INTEL_INFO(dev_priv)->ring_mask;
3082+
3083+ if (flags & I915_ERROR_CAPTURE) {
3084+ i915_capture_error_state(dev_priv, engine_mask, msg);
3085+ i915_clear_error_registers(dev_priv);
3086+ }
30253087
30263088 /*
30273089 * Try engine reset when available. We fall back to full reset if
@@ -3034,7 +3096,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv, · 6 unmodified lines
30343096 &dev_priv->gpu_error.flags))
30353097 continue;
30363098
3037− if (i915_reset_engine(engine, 0) == 0)
3099+ if (i915_reset_engine(engine, msg) == 0)
30383100 engine_mask &= ~intel_engine_flag(engine);
30393101
30403102 clear_bit(I915_RESET_ENGINE + engine->id,
@@ -3064,7 +3126,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv, · 23 unmodified lines
30643126 TASK_UNINTERRUPTIBLE);
30653127 }
30663128
3067− i915_reset_device(dev_priv);
3129+ i915_reset_device(dev_priv, engine_mask, msg);
30683130
30693131 for_each_engine(engine, dev_priv, tmp) {
30703132 clear_bit(I915_RESET_ENGINE + engine->id,
@@ -3349,6 +3411,9 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv) · 278 unmodified lines
33493411 I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0);
33503412 I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0);
33513413 I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0);
3414+
3415+ I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
3416+ I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
33523417 }
33533418
33543419 static void gen11_irq_reset(struct drm_device *dev)
@@ -3887,7 +3952,14 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv) · 532 unmodified lines
38873952 I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16));
38883953 I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16));
38893954
3890− dev_priv->pm_imr = 0xffffffff; /* TODO */
3955+ /*
3956+ * RPS interrupts will get enabled/disabled on demand when RPS itself
3957+ * is enabled/disabled.
3958+ */
3959+ dev_priv->pm_ier = 0x0;
3960+ dev_priv->pm_imr = ~dev_priv->pm_ier;
3961+ I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
3962+ I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
38913963 }
38923964
38933965 static int gen11_irq_postinstall(struct drm_device *dev)
drivers/gpu/drm/i915/i915_oa_icl.c+118−0
@@ -0,0 +1,118 @@
1+/*
2+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
3+ * DO NOT EDIT manually!
4+ *
5+ *
6+ * Copyright (c) 2015 Intel Corporation
7+ *
8+ * Permission is hereby granted, free of charge, to any person obtaining a
9+ * copy of this software and associated documentation files (the "Software"),
10+ * to deal in the Software without restriction, including without limitation
11+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12+ * and/or sell copies of the Software, and to permit persons to whom the
13+ * Software is furnished to do so, subject to the following conditions:
14+ *
15+ * The above copyright notice and this permission notice (including the next
16+ * paragraph) shall be included in all copies or substantial portions of the
17+ * Software.
18+ *
19+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25+ * IN THE SOFTWARE.
26+ *
27+ */
28+
29+#include <linux/sysfs.h>
30+
31+#include "i915_drv.h"
32+#include "i915_oa_icl.h"
33+
34+static const struct i915_oa_reg b_counter_config_test_oa[] = {
35+ { _MMIO(0x2740), 0x00000000 },
36+ { _MMIO(0x2710), 0x00000000 },
37+ { _MMIO(0x2714), 0xf0800000 },
38+ { _MMIO(0x2720), 0x00000000 },
39+ { _MMIO(0x2724), 0xf0800000 },
40+ { _MMIO(0x2770), 0x00000004 },
41+ { _MMIO(0x2774), 0x0000ffff },
42+ { _MMIO(0x2778), 0x00000003 },
43+ { _MMIO(0x277c), 0x0000ffff },
44+ { _MMIO(0x2780), 0x00000007 },
45+ { _MMIO(0x2784), 0x0000ffff },
46+ { _MMIO(0x2788), 0x00100002 },
47+ { _MMIO(0x278c), 0x0000fff7 },
48+ { _MMIO(0x2790), 0x00100002 },
49+ { _MMIO(0x2794), 0x0000ffcf },
50+ { _MMIO(0x2798), 0x00100082 },
51+ { _MMIO(0x279c), 0x0000ffef },
52+ { _MMIO(0x27a0), 0x001000c2 },
53+ { _MMIO(0x27a4), 0x0000ffe7 },
54+ { _MMIO(0x27a8), 0x00100001 },
55+ { _MMIO(0x27ac), 0x0000ffe7 },
56+};
57+
58+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
59+};
60+
61+static const struct i915_oa_reg mux_config_test_oa[] = {
62+ { _MMIO(0xd04), 0x00000200 },
63+ { _MMIO(0x9840), 0x00000000 },
64+ { _MMIO(0x9884), 0x00000000 },
65+ { _MMIO(0x9888), 0x10060000 },
66+ { _MMIO(0x9888), 0x22060000 },
67+ { _MMIO(0x9888), 0x16060000 },
68+ { _MMIO(0x9888), 0x24060000 },
69+ { _MMIO(0x9888), 0x18060000 },
70+ { _MMIO(0x9888), 0x1a060000 },
71+ { _MMIO(0x9888), 0x12060000 },
72+ { _MMIO(0x9888), 0x14060000 },
73+ { _MMIO(0x9888), 0x10060000 },
74+ { _MMIO(0x9888), 0x22060000 },
75+ { _MMIO(0x9884), 0x00000003 },
76+ { _MMIO(0x9888), 0x16130000 },
77+ { _MMIO(0x9888), 0x24000001 },
78+ { _MMIO(0x9888), 0x0e130056 },
79+ { _MMIO(0x9888), 0x10130000 },
80+ { _MMIO(0x9888), 0x1a130000 },
81+ { _MMIO(0x9888), 0x541f0001 },
82+ { _MMIO(0x9888), 0x181f0000 },
83+ { _MMIO(0x9888), 0x4c1f0000 },
84+ { _MMIO(0x9888), 0x301f0000 },
85+};
86+
87+static ssize_t
88+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
89+{
90+ return sprintf(buf, "1\n");
91+}
92+
93+void
94+i915_perf_load_test_config_icl(struct drm_i915_private *dev_priv)
95+{
96+ strlcpy(dev_priv->perf.oa.test_config.uuid,
97+ "a291665e-244b-4b76-9b9a-01de9d3c8068",
98+ sizeof(dev_priv->perf.oa.test_config.uuid));
99+ dev_priv->perf.oa.test_config.id = 1;
100+
101+ dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
102+ dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
103+
104+ dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
105+ dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
106+
107+ dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
108+ dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
109+
110+ dev_priv->perf.oa.test_config.sysfs_metric.name = "a291665e-244b-4b76-9b9a-01de9d3c8068";
111+ dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
112+
113+ dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
114+
115+ dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
116+ dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
117+ dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
118+}
drivers/gpu/drm/i915/i915_oa_icl.h+34−0
@@ -0,0 +1,34 @@
1+/*
2+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
3+ * DO NOT EDIT manually!
4+ *
5+ *
6+ * Copyright (c) 2015 Intel Corporation
7+ *
8+ * Permission is hereby granted, free of charge, to any person obtaining a
9+ * copy of this software and associated documentation files (the "Software"),
10+ * to deal in the Software without restriction, including without limitation
11+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12+ * and/or sell copies of the Software, and to permit persons to whom the
13+ * Software is furnished to do so, subject to the following conditions:
14+ *
15+ * The above copyright notice and this permission notice (including the next
16+ * paragraph) shall be included in all copies or substantial portions of the
17+ * Software.
18+ *
19+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25+ * IN THE SOFTWARE.
26+ *
27+ */
28+
29+#ifndef __I915_OA_ICL_H__
30+#define __I915_OA_ICL_H__
31+
32+extern void i915_perf_load_test_config_icl(struct drm_i915_private *dev_priv);
33+
34+#endif
drivers/gpu/drm/i915/i915_params.h+1−1
@@ -48,7 +48,7 @@ struct drm_printer; · 47 unmodified lines
4848 param(int, enable_ips, 1) \
4949 param(int, invert_brightness, 0) \
5050 param(int, enable_guc, 0) \
51− param(int, guc_log_level, 0) \
51+ param(int, guc_log_level, -1) \
5252 param(char *, guc_firmware_path, NULL) \
5353 param(char *, huc_firmware_path, NULL) \
5454 param(int, mmio_debug, 0) \
drivers/gpu/drm/i915/i915_pci.c+1−0
@@ -602,6 +602,7 @@ static const struct intel_device_info intel_icelake_11_info = { · 601 unmodified lines
602602 PLATFORM(INTEL_ICELAKE),
603603 .is_alpha_support = 1,
604604 .has_resource_streamer = 0,
605+ .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
605606 };
606607
607608 #undef GEN
drivers/gpu/drm/i915/i915_perf.c+40−29
@@ -209,6 +209,7 @@ · 208 unmodified lines
209209 #include "i915_oa_cflgt2.h"
210210 #include "i915_oa_cflgt3.h"
211211 #include "i915_oa_cnl.h"
212+#include "i915_oa_icl.h"
212213
213214 /* HW requires this to be a power of two, between 128k and 16M, though driver
214215 * is currently generally designed assuming the largest 16M size is used such
@@ -1042,7 +1043,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream, · 827 unmodified lines
10421043
10431044 I915_WRITE(GEN7_OASTATUS2,
10441045 ((head & GEN7_OASTATUS2_HEAD_MASK) |
1045− OA_MEM_SELECT_GGTT));
1046+ GEN7_OASTATUS2_MEM_SELECT_GGTT));
10461047 dev_priv->perf.oa.oa_buffer.head = head;
10471048
10481049 spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
@@ -1332,7 +1333,8 @@ static void gen7_init_oa_buffer(struct drm_i915_private *dev_priv) · 283 unmodified lines
13321333 /* Pre-DevBDW: OABUFFER must be set with counters off,
13331334 * before OASTATUS1, but after OASTATUS2
13341335 */
1335− I915_WRITE(GEN7_OASTATUS2, gtt_offset | OA_MEM_SELECT_GGTT); /* head */
1336+ I915_WRITE(GEN7_OASTATUS2,
1337+ gtt_offset | GEN7_OASTATUS2_MEM_SELECT_GGTT); /* head */
13361338 dev_priv->perf.oa.oa_buffer.head = gtt_offset;
13371339
13381340 I915_WRITE(GEN7_OABUFFER, gtt_offset);
@@ -1392,7 +1394,7 @@ static void gen8_init_oa_buffer(struct drm_i915_private *dev_priv) · 53 unmodified lines
13921394 * bit."
13931395 */
13941396 I915_WRITE(GEN8_OABUFFER, gtt_offset |
1395− OABUFFER_SIZE_16M | OA_MEM_SELECT_GGTT);
1397+ OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
13961398 I915_WRITE(GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
13971399
13981400 /* Mark that we need updated tail pointers to read from... */
@@ -1840,7 +1842,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv, · 441 unmodified lines
18401842 * be read back from automatically triggered reports, as part of the
18411843 * RPT_ID field.
18421844 */
1843− if (IS_GEN9(dev_priv) || IS_GEN10(dev_priv)) {
1845+ if (IS_GEN(dev_priv, 9, 11)) {
18441846 I915_WRITE(GEN8_OA_DEBUG,
18451847 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
18461848 GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
@@ -1870,7 +1872,6 @@ static void gen8_disable_metric_set(struct drm_i915_private *dev_priv) · 23 unmodified lines
18701872
18711873 I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) &
18721874 ~GT_NOA_ENABLE));
1873−
18741875 }
18751876
18761877 static void gen10_disable_metric_set(struct drm_i915_private *dev_priv)
@@ -1885,6 +1886,13 @@ static void gen10_disable_metric_set(struct drm_i915_private *dev_priv) · 8 unmodified lines
18851886
18861887 static void gen7_oa_enable(struct drm_i915_private *dev_priv)
18871888 {
1889+ struct i915_gem_context *ctx =
1890+ dev_priv->perf.oa.exclusive_stream->ctx;
1891+ u32 ctx_id = dev_priv->perf.oa.specific_ctx_id;
1892+ bool periodic = dev_priv->perf.oa.periodic;
1893+ u32 period_exponent = dev_priv->perf.oa.period_exponent;
1894+ u32 report_format = dev_priv->perf.oa.oa_buffer.format;
1895+
18881896 /*
18891897 * Reset buf pointers so we don't forward reports from before now.
18901898 *
@@ -1896,25 +1904,14 @@ static void gen7_oa_enable(struct drm_i915_private *dev_priv) · 5 unmodified lines
18961904 */
18971905 gen7_init_oa_buffer(dev_priv);
18981906
1899− if (dev_priv->perf.oa.exclusive_stream->enabled) {
1900− struct i915_gem_context *ctx =
1901− dev_priv->perf.oa.exclusive_stream->ctx;
1902− u32 ctx_id = dev_priv->perf.oa.specific_ctx_id;
1903−
1904− bool periodic = dev_priv->perf.oa.periodic;
1905− u32 period_exponent = dev_priv->perf.oa.period_exponent;
1906− u32 report_format = dev_priv->perf.oa.oa_buffer.format;
1907−
1908− I915_WRITE(GEN7_OACONTROL,
1909− (ctx_id & GEN7_OACONTROL_CTX_MASK) |
1910− (period_exponent <<
1911− GEN7_OACONTROL_TIMER_PERIOD_SHIFT) |
1912− (periodic ? GEN7_OACONTROL_TIMER_ENABLE : 0) |
1913− (report_format << GEN7_OACONTROL_FORMAT_SHIFT) |
1914− (ctx ? GEN7_OACONTROL_PER_CTX_ENABLE : 0) |
1915− GEN7_OACONTROL_ENABLE);
1916− } else
1917− I915_WRITE(GEN7_OACONTROL, 0);
1907+ I915_WRITE(GEN7_OACONTROL,
1908+ (ctx_id & GEN7_OACONTROL_CTX_MASK) |
1909+ (period_exponent <<
1910+ GEN7_OACONTROL_TIMER_PERIOD_SHIFT) |
1911+ (periodic ? GEN7_OACONTROL_TIMER_ENABLE : 0) |
1912+ (report_format << GEN7_OACONTROL_FORMAT_SHIFT) |
1913+ (ctx ? GEN7_OACONTROL_PER_CTX_ENABLE : 0) |
1914+ GEN7_OACONTROL_ENABLE);
19181915 }
19191916
19201917 static void gen8_oa_enable(struct drm_i915_private *dev_priv)
@@ -2099,13 +2096,17 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, · 178 unmodified lines
20992096
21002097 if (stream->ctx) {
21012098 ret = oa_get_render_ctx_id(stream);
2102− if (ret)
2099+ if (ret) {
2100+ DRM_DEBUG("Invalid context id to filter with\n");
21032101 return ret;
2102+ }
21042103 }
21052104
21062105 ret = get_oa_config(dev_priv, props->metrics_set, &stream->oa_config);
2107− if (ret)
2106+ if (ret) {
2107+ DRM_DEBUG("Invalid OA config id=%i\n", props->metrics_set);
21082108 goto err_config;
2109+ }
21092110
21102111 /* PRM - observability performance counters:
21112112 *
@@ -2132,8 +2133,10 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, · 20 unmodified lines
21322133
21332134 ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv,
21342135 stream->oa_config);
2135− if (ret)
2136+ if (ret) {
2137+ DRM_DEBUG("Unable to enable metric set\n");
21362138 goto err_enable;
2139+ }
21372140
21382141 stream->ops = &i915_oa_stream_ops;
21392142
@@ -2745,7 +2748,8 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv, · 605 unmodified lines
27452748 props->ctx_handle = value;
27462749 break;
27472750 case DRM_I915_PERF_PROP_SAMPLE_OA:
2748− props->sample_flags |= SAMPLE_OA_REPORT;
2751+ if (value)
2752+ props->sample_flags |= SAMPLE_OA_REPORT;
27492753 break;
27502754 case DRM_I915_PERF_PROP_OA_METRICS_SET:
27512755 if (value == 0) {
@@ -2935,6 +2939,8 @@ void i915_perf_register(struct drm_i915_private *dev_priv) · 183 unmodified lines
29352939 i915_perf_load_test_config_cflgt3(dev_priv);
29362940 } else if (IS_CANNONLAKE(dev_priv)) {
29372941 i915_perf_load_test_config_cnl(dev_priv);
2942+ } else if (IS_ICELAKE(dev_priv)) {
2943+ i915_perf_load_test_config_icl(dev_priv);
29382944 }
29392945
29402946 if (dev_priv->perf.oa.test_config.id == 0)
@@ -3292,6 +3298,8 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, · 351 unmodified lines
32923298
32933299 mutex_unlock(&dev_priv->perf.metrics_lock);
32943300
3301+ DRM_DEBUG("Added config %s id=%i\n", oa_config->uuid, oa_config->id);
3302+
32953303 return oa_config->id;
32963304
32973305 sysfs_err:
@@ -3348,6 +3356,9 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, · 50 unmodified lines
33483356 &oa_config->sysfs_metric);
33493357
33503358 idr_remove(&dev_priv->perf.metrics_idr, *arg);
3359+
3360+ DRM_DEBUG("Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
3361+
33513362 put_oa_config(dev_priv, oa_config);
33523363
33533364 config_err:
@@ -3467,7 +3478,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) · 113 unmodified lines
34673478
34683479 dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
34693480 }
3470− } else if (IS_GEN10(dev_priv)) {
3481+ } else if (IS_GEN(dev_priv, 10, 11)) {
34713482 dev_priv->perf.oa.ops.is_valid_b_counter_reg =
34723483 gen7_is_valid_b_counter_addr;
34733484 dev_priv->perf.oa.ops.is_valid_mux_reg =
drivers/gpu/drm/i915/i915_pmu.c+3−24
@@ -1,33 +1,12 @@
11 /*
2− * Copyright © 2017 Intel Corporation
3− *
4− * Permission is hereby granted, free of charge, to any person obtaining a
5− * copy of this software and associated documentation files (the "Software"),
6− * to deal in the Software without restriction, including without limitation
7− * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8− * and/or sell copies of the Software, and to permit persons to whom the
9− * Software is furnished to do so, subject to the following conditions:
10− *
11− * The above copyright notice and this permission notice (including the next
12− * paragraph) shall be included in all copies or substantial portions of the
13− * Software.
14− *
15− * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16− * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17− * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18− * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19− * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20− * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21− * IN THE SOFTWARE.
2+ * SPDX-License-Identifier: MIT
223 *
4+ * Copyright © 2017-2018 Intel Corporation
235 */
246
25−#include <linux/perf_event.h>
26−#include <linux/pm_runtime.h>
27−
28−#include "i915_drv.h"
297 #include "i915_pmu.h"
308 #include "intel_ringbuffer.h"
9+#include "i915_drv.h"
3110
3211 /* Frequency for the sampling timer for events which need it. */
3312 #define FREQUENCY 200
drivers/gpu/drm/i915/i915_pmu.h+10−20
@@ -1,29 +1,19 @@
11 /*
2− * Copyright © 2017 Intel Corporation
3− *
4− * Permission is hereby granted, free of charge, to any person obtaining a
5− * copy of this software and associated documentation files (the "Software"),
6− * to deal in the Software without restriction, including without limitation
7− * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8− * and/or sell copies of the Software, and to permit persons to whom the
9− * Software is furnished to do so, subject to the following conditions:
10− *
11− * The above copyright notice and this permission notice (including the next
12− * paragraph) shall be included in all copies or substantial portions of the
13− * Software.
14− *
15− * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16− * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17− * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18− * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19− * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20− * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21− * IN THE SOFTWARE.
2+ * SPDX-License-Identifier: MIT
223 *
4+ * Copyright © 2017-2018 Intel Corporation
235 */
6+
247 #ifndef __I915_PMU_H__
258 #define __I915_PMU_H__
269
10+#include <linux/hrtimer.h>
11+#include <linux/perf_event.h>
12+#include <linux/spinlock_types.h>
13+#include <drm/i915_drm.h>
14+
15+struct drm_i915_private;
16+
2717 enum {
2818 __I915_SAMPLE_FREQ_ACT = 0,
2919 __I915_SAMPLE_FREQ_REQ,
drivers/gpu/drm/i915/i915_reg.h+267−377
@@ -153,9 +153,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 152 unmodified lines
153153 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
154154 #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
155155 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
156−#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
157−#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \
158− _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
159156 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
160157 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
161158
@@ -191,6 +188,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 29 unmodified lines
191188 #define OTHER_CLASS 4
192189 #define MAX_ENGINE_CLASS 4
193190
191+#define OTHER_GTPM_INSTANCE 1
194192 #define MAX_ENGINE_INSTANCE 3
195193
196194 /* PCI config space */
@@ -304,6 +302,17 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 107 unmodified lines
304302 #define GEN6_GRDOM_VECS (1 << 4)
305303 #define GEN9_GRDOM_GUC (1 << 5)
306304 #define GEN8_GRDOM_MEDIA2 (1 << 7)
305+/* GEN11 changed all bit defs except for FULL & RENDER */
306+#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
307+#define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
308+#define GEN11_GRDOM_BLT (1 << 2)
309+#define GEN11_GRDOM_GUC (1 << 3)
310+#define GEN11_GRDOM_MEDIA (1 << 5)
311+#define GEN11_GRDOM_MEDIA2 (1 << 6)
312+#define GEN11_GRDOM_MEDIA3 (1 << 7)
313+#define GEN11_GRDOM_MEDIA4 (1 << 8)
314+#define GEN11_GRDOM_VECS (1 << 13)
315+#define GEN11_GRDOM_VECS2 (1 << 14)
307316
308317 #define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base+0x228)
309318 #define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base+0x518)
@@ -430,145 +439,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 120 unmodified lines
430439 #define VGA_CR_INDEX_CGA 0x3d4
431440 #define VGA_CR_DATA_CGA 0x3d5
432441
433−/*
434− * Instruction field definitions used by the command parser
435− */
436−#define INSTR_CLIENT_SHIFT 29
437−#define INSTR_MI_CLIENT 0x0
438−#define INSTR_BC_CLIENT 0x2
439−#define INSTR_RC_CLIENT 0x3
440−#define INSTR_SUBCLIENT_SHIFT 27
441−#define INSTR_SUBCLIENT_MASK 0x18000000
442−#define INSTR_MEDIA_SUBCLIENT 0x2
443−#define INSTR_26_TO_24_MASK 0x7000000
444−#define INSTR_26_TO_24_SHIFT 24
445−
446−/*
447− * Memory interface instructions used by the kernel
448− */
449−#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
450−/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
451−#define MI_GLOBAL_GTT (1<<22)
452−
453−#define MI_NOOP MI_INSTR(0, 0)
454−#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
455−#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
456−#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
457−#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
458−#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
459−#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
460−#define MI_FLUSH MI_INSTR(0x04, 0)
461−#define MI_READ_FLUSH (1 << 0)
462−#define MI_EXE_FLUSH (1 << 1)
463−#define MI_NO_WRITE_FLUSH (1 << 2)
464−#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
465−#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
466−#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
467−#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
468−#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
469−#define MI_ARB_ENABLE (1<<0)
470−#define MI_ARB_DISABLE (0<<0)
471−#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
472−#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
473−#define MI_SUSPEND_FLUSH_EN (1<<0)
474−#define MI_SET_APPID MI_INSTR(0x0e, 0)
475−#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
476−#define MI_OVERLAY_CONTINUE (0x0<<21)
477−#define MI_OVERLAY_ON (0x1<<21)
478−#define MI_OVERLAY_OFF (0x2<<21)
479−#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
480−#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
481−#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
482−#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
483−/* IVB has funny definitions for which plane to flip. */
484−#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
485−#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
486−#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
487−#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
488−#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
489−#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
490−/* SKL ones */
491−#define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
492−#define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
493−#define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
494−#define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
495−#define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
496−#define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
497−#define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
498−#define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
499−#define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
500−#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
501−#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
502−#define MI_SEMAPHORE_UPDATE (1<<21)
503−#define MI_SEMAPHORE_COMPARE (1<<20)
504−#define MI_SEMAPHORE_REGISTER (1<<18)
505−#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
506−#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
507−#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
508−#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
509−#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
510−#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
511−#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
512−#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
513−#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
514−#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
515−#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
516−#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
517−#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
518−#define MI_SEMAPHORE_SYNC_MASK (3<<16)
519−#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
520−#define MI_MM_SPACE_GTT (1<<8)
521−#define MI_MM_SPACE_PHYSICAL (0<<8)
522−#define MI_SAVE_EXT_STATE_EN (1<<3)
523−#define MI_RESTORE_EXT_STATE_EN (1<<2)
524−#define MI_FORCE_RESTORE (1<<1)
525−#define MI_RESTORE_INHIBIT (1<<0)
526−#define HSW_MI_RS_SAVE_STATE_EN (1<<3)
527−#define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
528−#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
529−#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
530−#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
531−#define MI_SEMAPHORE_POLL (1<<15)
532−#define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
533−#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
534−#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
535−#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
536−#define MI_USE_GGTT (1 << 22) /* g4x+ */
537−#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
538−#define MI_STORE_DWORD_INDEX_SHIFT 2
539−/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
540− * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
541− * simply ignores the register load under certain conditions.
542− * - One can actually load arbitrary many arbitrary registers: Simply issue x
543− * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
544− */
545−#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
546−#define MI_LRI_FORCE_POSTED (1<<12)
547−#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
548−#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
549−#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
550−#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
551−#define MI_FLUSH_DW_STORE_INDEX (1<<21)
552−#define MI_INVALIDATE_TLB (1<<18)
553−#define MI_FLUSH_DW_OP_STOREDW (1<<14)
554−#define MI_FLUSH_DW_OP_MASK (3<<14)
555−#define MI_FLUSH_DW_NOTIFY (1<<8)
556−#define MI_INVALIDATE_BSD (1<<7)
557−#define MI_FLUSH_DW_USE_GTT (1<<2)
558−#define MI_FLUSH_DW_USE_PPGTT (0<<2)
559−#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
560−#define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
561−#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
562−#define MI_BATCH_NON_SECURE (1)
563−/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
564−#define MI_BATCH_NON_SECURE_I965 (1<<8)
565−#define MI_BATCH_PPGTT_HSW (1<<8)
566−#define MI_BATCH_NON_SECURE_HSW (1<<13)
567−#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
568−#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
569−#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
570−#define MI_BATCH_RESOURCE_STREAMER (1<<10)
571−
572442 #define MI_PREDICATE_SRC0 _MMIO(0x2400)
573443 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
574444 #define MI_PREDICATE_SRC1 _MMIO(0x2408)
@@ -578,130 +448,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 3 unmodified lines
578448 #define LOWER_SLICE_ENABLED (1<<0)
579449 #define LOWER_SLICE_DISABLED (0<<0)
580450
581−/*
582− * 3D instructions used by the kernel
583− */
584−#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
585−
586−#define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
587−#define GEN9_MEDIA_POOL_ENABLE (1 << 31)
588−#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
589−#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
590−#define SC_UPDATE_SCISSOR (0x1<<1)
591−#define SC_ENABLE_MASK (0x1<<0)
592−#define SC_ENABLE (0x1<<0)
593−#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
594−#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
595−#define SCI_YMIN_MASK (0xffff<<16)
596−#define SCI_XMIN_MASK (0xffff<<0)
597−#define SCI_YMAX_MASK (0xffff<<16)
598−#define SCI_XMAX_MASK (0xffff<<0)
599−#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
600−#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
601−#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
602−#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
603−#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
604−#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
605−#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
606−#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
607−#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
608−
609−#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
610−#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
611−#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
612−#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
613−#define BLT_WRITE_A (2<<20)
614−#define BLT_WRITE_RGB (1<<20)
615−#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
616−#define BLT_DEPTH_8 (0<<24)
617−#define BLT_DEPTH_16_565 (1<<24)
618−#define BLT_DEPTH_16_1555 (2<<24)
619−#define BLT_DEPTH_32 (3<<24)
620−#define BLT_ROP_SRC_COPY (0xcc<<16)
621−#define BLT_ROP_COLOR_COPY (0xf0<<16)
622−#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
623−#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
624−#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
625−#define ASYNC_FLIP (1<<22)
626−#define DISPLAY_PLANE_A (0<<20)
627−#define DISPLAY_PLANE_B (1<<20)
628−#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
629−#define PIPE_CONTROL_FLUSH_L3 (1<<27)
630−#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
631−#define PIPE_CONTROL_MMIO_WRITE (1<<23)
632−#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
633−#define PIPE_CONTROL_CS_STALL (1<<20)
634−#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
635−#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
636−#define PIPE_CONTROL_QW_WRITE (1<<14)
637−#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
638−#define PIPE_CONTROL_DEPTH_STALL (1<<13)
639−#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
640−#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
641−#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
642−#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
643−#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
644−#define PIPE_CONTROL_NOTIFY (1<<8)
645−#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
646−#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
647−#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
648−#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
649−#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
650−#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
651−#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
652−#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
653−
654−/*
655− * Commands used only by the command parser
656− */
657−#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
658−#define MI_ARB_CHECK MI_INSTR(0x05, 0)
659−#define MI_RS_CONTROL MI_INSTR(0x06, 0)
660−#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
661−#define MI_PREDICATE MI_INSTR(0x0C, 0)
662−#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
663−#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
664−#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
665−#define MI_URB_CLEAR MI_INSTR(0x19, 0)
666−#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
667−#define MI_CLFLUSH MI_INSTR(0x27, 0)
668−#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
669−#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
670−#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
671−#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
672−#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
673−#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
674−#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
675−
676−#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
677−#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
678−#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
679−#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
680−#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
681−#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
682−#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
683− ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
684−#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
685− ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
686−#define GFX_OP_3DSTATE_SO_DECL_LIST \
687− ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
688−
689−#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
690− ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
691−#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
692− ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
693−#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
694− ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
695−#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
696− ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
697−#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
698− ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
699−
700−#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
701−
702−#define COLOR_BLT ((0x2<<29)|(0x40<<22))
703−#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
704−
705451 /*
706452 * Registers used only by the command parser
707453 */
@@ -802,6 +548,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 94 unmodified lines
802548
803549 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
804550 #define GEN8_OABUFFER _MMIO(0x2b14)
551+#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
805552
806553 #define GEN7_OASTATUS1 _MMIO(0x2364)
807554 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
@@ -810,7 +557,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 2 unmodified lines
810557 #define GEN7_OASTATUS1_REPORT_LOST (1<<0)
811558
812559 #define GEN7_OASTATUS2 _MMIO(0x2368)
813−#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
560+#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
561+#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
814562
815563 #define GEN8_OASTATUS _MMIO(0x2b08)
816564 #define GEN8_OASTATUS_OVERRUN_STATUS (1<<3)
@@ -832,8 +580,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 15 unmodified lines
832580 #define OABUFFER_SIZE_8M (6<<3)
833581 #define OABUFFER_SIZE_16M (7<<3)
834582
835−#define OA_MEM_SELECT_GGTT (1<<0)
836−
837583 /*
838584 * Flexible, Aggregate EU Counter Registers.
839585 * Note: these aren't contiguous
@@ -1127,6 +873,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 287 unmodified lines
1127873 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1128874 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
1129875 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
876+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
877+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
878+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
879+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
880+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
881+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
1130882 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
1131883 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1132884
@@ -1948,79 +1700,100 @@ enum i915_power_well_id { · 815 unmodified lines
19481700 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
19491701 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
19501702 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1951−#define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT6(port, \
1703+#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \
19521704 _CNL_PORT_PCS_DW1_GRP_AE, \
19531705 _CNL_PORT_PCS_DW1_GRP_B, \
19541706 _CNL_PORT_PCS_DW1_GRP_C, \
19551707 _CNL_PORT_PCS_DW1_GRP_D, \
19561708 _CNL_PORT_PCS_DW1_GRP_AE, \
1957− _CNL_PORT_PCS_DW1_GRP_F)
1958−#define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT6(port, \
1709+ _CNL_PORT_PCS_DW1_GRP_F))
1710+
1711+#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \
19591712 _CNL_PORT_PCS_DW1_LN0_AE, \
19601713 _CNL_PORT_PCS_DW1_LN0_B, \
19611714 _CNL_PORT_PCS_DW1_LN0_C, \
19621715 _CNL_PORT_PCS_DW1_LN0_D, \
19631716 _CNL_PORT_PCS_DW1_LN0_AE, \
1964− _CNL_PORT_PCS_DW1_LN0_F)
1717+ _CNL_PORT_PCS_DW1_LN0_F))
1718+#define _ICL_PORT_PCS_DW1_GRP_A 0x162604
1719+#define _ICL_PORT_PCS_DW1_GRP_B 0x6C604
1720+#define _ICL_PORT_PCS_DW1_LN0_A 0x162804
1721+#define _ICL_PORT_PCS_DW1_LN0_B 0x6C804
1722+#define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\
1723+ _ICL_PORT_PCS_DW1_GRP_A, \
1724+ _ICL_PORT_PCS_DW1_GRP_B)
1725+#define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \
1726+ _ICL_PORT_PCS_DW1_LN0_A, \
1727+ _ICL_PORT_PCS_DW1_LN0_B)
19651728 #define COMMON_KEEPER_EN (1 << 26)
19661729
1967−#define _CNL_PORT_TX_DW2_GRP_AE 0x162348
1968−#define _CNL_PORT_TX_DW2_GRP_B 0x1623C8
1969−#define _CNL_PORT_TX_DW2_GRP_C 0x162B48
1970−#define _CNL_PORT_TX_DW2_GRP_D 0x162BC8
1971−#define _CNL_PORT_TX_DW2_GRP_F 0x162A48
1972−#define _CNL_PORT_TX_DW2_LN0_AE 0x162448
1973−#define _CNL_PORT_TX_DW2_LN0_B 0x162648
1974−#define _CNL_PORT_TX_DW2_LN0_C 0x162C48
1975−#define _CNL_PORT_TX_DW2_LN0_D 0x162E48
1976−#define _CNL_PORT_TX_DW2_LN0_F 0x162848
1977−#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \
1978− _CNL_PORT_TX_DW2_GRP_AE, \
1979− _CNL_PORT_TX_DW2_GRP_B, \
1980− _CNL_PORT_TX_DW2_GRP_C, \
1981− _CNL_PORT_TX_DW2_GRP_D, \
1982− _CNL_PORT_TX_DW2_GRP_AE, \
1983− _CNL_PORT_TX_DW2_GRP_F)
1984−#define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \
1985− _CNL_PORT_TX_DW2_LN0_AE, \
1986− _CNL_PORT_TX_DW2_LN0_B, \
1987− _CNL_PORT_TX_DW2_LN0_C, \
1988− _CNL_PORT_TX_DW2_LN0_D, \
1989− _CNL_PORT_TX_DW2_LN0_AE, \
1990− _CNL_PORT_TX_DW2_LN0_F)
1991−#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
1730+/* CNL Port TX registers */
1731+#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
1732+#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
1733+#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
1734+#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
1735+#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
1736+#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
1737+#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
1738+#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
1739+#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
1740+#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
1741+#define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \
1742+ _CNL_PORT_TX_AE_GRP_OFFSET, \
1743+ _CNL_PORT_TX_B_GRP_OFFSET, \
1744+ _CNL_PORT_TX_B_GRP_OFFSET, \
1745+ _CNL_PORT_TX_D_GRP_OFFSET, \
1746+ _CNL_PORT_TX_AE_GRP_OFFSET, \
1747+ _CNL_PORT_TX_F_GRP_OFFSET) + \
1748+ 4*(dw))
1749+#define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \
1750+ _CNL_PORT_TX_AE_LN0_OFFSET, \
1751+ _CNL_PORT_TX_B_LN0_OFFSET, \
1752+ _CNL_PORT_TX_B_LN0_OFFSET, \
1753+ _CNL_PORT_TX_D_LN0_OFFSET, \
1754+ _CNL_PORT_TX_AE_LN0_OFFSET, \
1755+ _CNL_PORT_TX_F_LN0_OFFSET) + \
1756+ 4*(dw))
1757+
1758+#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
1759+#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
1760+#define _ICL_PORT_TX_DW2_GRP_A 0x162688
1761+#define _ICL_PORT_TX_DW2_GRP_B 0x6C688
1762+#define _ICL_PORT_TX_DW2_LN0_A 0x162888
1763+#define _ICL_PORT_TX_DW2_LN0_B 0x6C888
1764+#define ICL_PORT_TX_DW2_GRP(port) _MMIO_PORT(port, \
1765+ _ICL_PORT_TX_DW2_GRP_A, \
1766+ _ICL_PORT_TX_DW2_GRP_B)
1767+#define ICL_PORT_TX_DW2_LN0(port) _MMIO_PORT(port, \
1768+ _ICL_PORT_TX_DW2_LN0_A, \
1769+ _ICL_PORT_TX_DW2_LN0_B)
1770+#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
19921771 #define SWING_SEL_UPPER_MASK (1 << 15)
1993−#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
1772+#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
19941773 #define SWING_SEL_LOWER_MASK (0x7 << 11)
19951774 #define RCOMP_SCALAR(x) ((x) << 0)
19961775 #define RCOMP_SCALAR_MASK (0xFF << 0)
19971776
1998−#define _CNL_PORT_TX_DW4_GRP_AE 0x162350
1999−#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
2000−#define _CNL_PORT_TX_DW4_GRP_C 0x162B50
2001−#define _CNL_PORT_TX_DW4_GRP_D 0x162BD0
2002−#define _CNL_PORT_TX_DW4_GRP_F 0x162A50
20031777 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450
20041778 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
2005−#define _CNL_PORT_TX_DW4_LN0_B 0x162650
2006−#define _CNL_PORT_TX_DW4_LN0_C 0x162C50
2007−#define _CNL_PORT_TX_DW4_LN0_D 0x162E50
2008−#define _CNL_PORT_TX_DW4_LN0_F 0x162850
2009−#define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \
2010− _CNL_PORT_TX_DW4_GRP_AE, \
2011− _CNL_PORT_TX_DW4_GRP_B, \
2012− _CNL_PORT_TX_DW4_GRP_C, \
2013− _CNL_PORT_TX_DW4_GRP_D, \
2014− _CNL_PORT_TX_DW4_GRP_AE, \
2015− _CNL_PORT_TX_DW4_GRP_F)
2016−#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \
2017− _CNL_PORT_TX_DW4_LN0_AE, \
2018− _CNL_PORT_TX_DW4_LN1_AE, \
2019− _CNL_PORT_TX_DW4_LN0_B, \
2020− _CNL_PORT_TX_DW4_LN0_C, \
2021− _CNL_PORT_TX_DW4_LN0_D, \
2022− _CNL_PORT_TX_DW4_LN0_AE, \
2023− _CNL_PORT_TX_DW4_LN0_F)
1779+#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))
1780+#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))
1781+#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
1782+ (ln * (_CNL_PORT_TX_DW4_LN1_AE - \
1783+ _CNL_PORT_TX_DW4_LN0_AE)))
1784+#define _ICL_PORT_TX_DW4_GRP_A 0x162690
1785+#define _ICL_PORT_TX_DW4_GRP_B 0x6C690
1786+#define _ICL_PORT_TX_DW4_LN0_A 0x162890
1787+#define _ICL_PORT_TX_DW4_LN1_A 0x162990
1788+#define _ICL_PORT_TX_DW4_LN0_B 0x6C890
1789+#define ICL_PORT_TX_DW4_GRP(port) _MMIO_PORT(port, \
1790+ _ICL_PORT_TX_DW4_GRP_A, \
1791+ _ICL_PORT_TX_DW4_GRP_B)
1792+#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \
1793+ _ICL_PORT_TX_DW4_LN0_A, \
1794+ _ICL_PORT_TX_DW4_LN0_B) + \
1795+ (ln * (_ICL_PORT_TX_DW4_LN1_A - \
1796+ _ICL_PORT_TX_DW4_LN0_A)))
20241797 #define LOADGEN_SELECT (1 << 31)
20251798 #define POST_CURSOR_1(x) ((x) << 12)
20261799 #define POST_CURSOR_1_MASK (0x3F << 12)
@@ -2029,64 +1802,147 @@ enum i915_power_well_id { · 2 unmodified lines
20291802 #define CURSOR_COEFF(x) ((x) << 0)
20301803 #define CURSOR_COEFF_MASK (0x3F << 0)
20311804
2032−#define _CNL_PORT_TX_DW5_GRP_AE 0x162354
2033−#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
2034−#define _CNL_PORT_TX_DW5_GRP_C 0x162B54
2035−#define _CNL_PORT_TX_DW5_GRP_D 0x162BD4
2036−#define _CNL_PORT_TX_DW5_GRP_F 0x162A54
2037−#define _CNL_PORT_TX_DW5_LN0_AE 0x162454
2038−#define _CNL_PORT_TX_DW5_LN0_B 0x162654
2039−#define _CNL_PORT_TX_DW5_LN0_C 0x162C54
2040−#define _CNL_PORT_TX_DW5_LN0_D 0x162E54
2041−#define _CNL_PORT_TX_DW5_LN0_F 0x162854
2042−#define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \
2043− _CNL_PORT_TX_DW5_GRP_AE, \
2044− _CNL_PORT_TX_DW5_GRP_B, \
2045− _CNL_PORT_TX_DW5_GRP_C, \
2046− _CNL_PORT_TX_DW5_GRP_D, \
2047− _CNL_PORT_TX_DW5_GRP_AE, \
2048− _CNL_PORT_TX_DW5_GRP_F)
2049−#define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \
2050− _CNL_PORT_TX_DW5_LN0_AE, \
2051− _CNL_PORT_TX_DW5_LN0_B, \
2052− _CNL_PORT_TX_DW5_LN0_C, \
2053− _CNL_PORT_TX_DW5_LN0_D, \
2054− _CNL_PORT_TX_DW5_LN0_AE, \
2055− _CNL_PORT_TX_DW5_LN0_F)
1805+#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
1806+#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
1807+#define _ICL_PORT_TX_DW5_GRP_A 0x162694
1808+#define _ICL_PORT_TX_DW5_GRP_B 0x6C694
1809+#define _ICL_PORT_TX_DW5_LN0_A 0x162894
1810+#define _ICL_PORT_TX_DW5_LN0_B 0x6C894
1811+#define ICL_PORT_TX_DW5_GRP(port) _MMIO_PORT(port, \
1812+ _ICL_PORT_TX_DW5_GRP_A, \
1813+ _ICL_PORT_TX_DW5_GRP_B)
1814+#define ICL_PORT_TX_DW5_LN0(port) _MMIO_PORT(port, \
1815+ _ICL_PORT_TX_DW5_LN0_A, \
1816+ _ICL_PORT_TX_DW5_LN0_B)
20561817 #define TX_TRAINING_EN (1 << 31)
1818+#define TAP2_DISABLE (1 << 30)
20571819 #define TAP3_DISABLE (1 << 29)
20581820 #define SCALING_MODE_SEL(x) ((x) << 18)
20591821 #define SCALING_MODE_SEL_MASK (0x7 << 18)
20601822 #define RTERM_SELECT(x) ((x) << 3)
20611823 #define RTERM_SELECT_MASK (0x7 << 3)
20621824
2063−#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
2064−#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
2065−#define _CNL_PORT_TX_DW7_GRP_C 0x162B5C
2066−#define _CNL_PORT_TX_DW7_GRP_D 0x162BDC
2067−#define _CNL_PORT_TX_DW7_GRP_F 0x162A5C
2068−#define _CNL_PORT_TX_DW7_LN0_AE 0x16245C
2069−#define _CNL_PORT_TX_DW7_LN0_B 0x16265C
2070−#define _CNL_PORT_TX_DW7_LN0_C 0x162C5C
2071−#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C
2072−#define _CNL_PORT_TX_DW7_LN0_F 0x16285C
2073−#define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \
2074− _CNL_PORT_TX_DW7_GRP_AE, \
2075− _CNL_PORT_TX_DW7_GRP_B, \
2076− _CNL_PORT_TX_DW7_GRP_C, \
2077− _CNL_PORT_TX_DW7_GRP_D, \
2078− _CNL_PORT_TX_DW7_GRP_AE, \
2079− _CNL_PORT_TX_DW7_GRP_F)
2080−#define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \
2081− _CNL_PORT_TX_DW7_LN0_AE, \
2082− _CNL_PORT_TX_DW7_LN0_B, \
2083− _CNL_PORT_TX_DW7_LN0_C, \
2084− _CNL_PORT_TX_DW7_LN0_D, \
2085− _CNL_PORT_TX_DW7_LN0_AE, \
2086− _CNL_PORT_TX_DW7_LN0_F)
1825+#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
1826+#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
20871827 #define N_SCALAR(x) ((x) << 24)
20881828 #define N_SCALAR_MASK (0x7F << 24)
20891829
1830+#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
1831+ _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
1832+
1833+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
1834+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
1835+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
1836+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
1837+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
1838+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
1839+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
1840+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
1841+#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
1842+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
1843+ _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
1844+ _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
1845+
1846+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
1847+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
1848+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
1849+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
1850+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
1851+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
1852+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
1853+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
1854+#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
1855+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
1856+ _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
1857+ _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
1858+#define CRI_USE_FS32 (1 << 5)
1859+
1860+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
1861+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
1862+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
1863+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
1864+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
1865+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
1866+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
1867+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
1868+#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
1869+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
1870+ _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
1871+ _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1)
1872+
1873+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
1874+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
1875+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
1876+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
1877+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
1878+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
1879+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
1880+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
1881+#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
1882+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
1883+ _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
1884+ _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1)
1885+#define CRI_CALCINIT (1 << 1)
1886+
1887+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
1888+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
1889+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
1890+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
1891+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
1892+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
1893+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
1894+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
1895+#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
1896+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
1897+ _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2, \
1898+ _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1)
1899+
1900+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
1901+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
1902+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
1903+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
1904+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
1905+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
1906+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
1907+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
1908+#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
1909+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
1910+ _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2, \
1911+ _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1)
1912+#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
1913+#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
1914+
1915+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1 0x168144
1916+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1 0x168544
1917+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2 0x169144
1918+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2 0x169544
1919+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3 0x16A144
1920+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3 0x16A544
1921+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4 0x16B144
1922+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4 0x16B544
1923+#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
1924+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
1925+ _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2, \
1926+ _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1)
1927+
1928+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
1929+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
1930+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
1931+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
1932+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
1933+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
1934+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
1935+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
1936+#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
1937+ _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
1938+ _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2, \
1939+ _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1)
1940+#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
1941+#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
1942+#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
1943+#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
1944+#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
1945+
20901946 /* The spec defines this only for BXT PHY0, but lets assume that this
20911947 * would exist for PHY1 too if it had a second channel.
20921948 */
@@ -2473,6 +2329,10 @@ enum i915_power_well_id { · 380 unmodified lines
24732329 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
24742330 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
24752331 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2332+#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
2333+#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
2334+#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
2335+#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
24762336 #define RING_IPEIR(base) _MMIO((base)+0x64)
24772337 #define RING_IPEHR(base) _MMIO((base)+0x68)
24782338 /*
@@ -2867,6 +2727,19 @@ enum i915_power_well_id { · 388 unmodified lines
28672727 #define GEN10_EU_DISABLE3 _MMIO(0x9140)
28682728 #define GEN10_EU_DIS_SS_MASK 0xff
28692729
2730+#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
2731+#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
2732+#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
2733+#define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
2734+
2735+#define GEN11_EU_DISABLE _MMIO(0x9134)
2736+#define GEN11_EU_DIS_MASK 0xFF
2737+
2738+#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
2739+#define GEN11_GT_S_ENA_MASK 0xFF
2740+
2741+#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
2742+
28702743 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
28712744 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
28722745 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
@@ -3951,6 +3824,9 @@ enum { · 1078 unmodified lines
39513824 #define _CLKGATE_DIS_PSL_A 0x46520
39523825 #define _CLKGATE_DIS_PSL_B 0x46524
39533826 #define _CLKGATE_DIS_PSL_C 0x46528
3827+#define DUPS1_GATING_DIS (1 << 15)
3828+#define DUPS2_GATING_DIS (1 << 19)
3829+#define DUPS3_GATING_DIS (1 << 23)
39543830 #define DPF_GATING_DIS (1 << 10)
39553831 #define DPF_RAM_GATING_DIS (1 << 9)
39563832 #define DPFR_GATING_DIS (1 << 8)
@@ -4151,6 +4027,12 @@ enum { · 194 unmodified lines
41514027 #define EDP_PSR_IDLE_FRAME_SHIFT 0
41524028
41534029 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
4030+#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
4031+#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4032+#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
4033+#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
4034+#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4035+
41544036 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
41554037
41564038 #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
@@ -4180,17 +4062,19 @@ enum { · 23 unmodified lines
41804062 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
41814063 #define EDP_PSR_PERF_CNT_MASK 0xffffff
41824064
4183−#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60)
4065+#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
41844066 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1<<28)
41854067 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
41864068 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
41874069 #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
41884070 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1<<16)
4189−#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
4071+#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15) /* SKL+ */
41904072
41914073 #define EDP_PSR2_CTL _MMIO(0x6f900)
41924074 #define EDP_PSR2_ENABLE (1<<31)
41934075 #define EDP_SU_TRACK_ENABLE (1<<30)
4076+#define EDP_Y_COORDINATE_VALID (1<<26) /* GLK and CNL+ */
4077+#define EDP_Y_COORDINATE_ENABLE (1<<25) /* GLK and CNL+ */
41944078 #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
41954079 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
41964080 #define EDP_PSR2_TP2_TIME_500 (0<<8)
@@ -4200,8 +4084,9 @@ enum { · 3 unmodified lines
42004084 #define EDP_PSR2_TP2_TIME_MASK (3<<8)
42014085 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
42024086 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
4203−#define EDP_PSR2_IDLE_MASK 0xf
42044087 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
4088+#define EDP_PSR2_IDLE_FRAME_MASK 0xf
4089+#define EDP_PSR2_IDLE_FRAME_SHIFT 0
42054090
42064091 #define EDP_PSR2_STATUS _MMIO(0x6f940)
42074092 #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
@@ -5265,8 +5150,6 @@ enum { · 1057 unmodified lines
52655150 #define DP_LINK_TRAIN_OFF (3 << 28)
52665151 #define DP_LINK_TRAIN_MASK (3 << 28)
52675152 #define DP_LINK_TRAIN_SHIFT 28
5268−#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
5269−#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
52705153
52715154 /* CPT Link training mode */
52725155 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
@@ -6009,6 +5892,7 @@ enum { · 736 unmodified lines
60095892 #define CURSIZE _MMIO(0x700a0) /* 845/865 */
60105893 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
60115894 #define CUR_FBC_CTL_EN (1 << 31)
5895+#define _CURASURFLIVE 0x700ac /* g4x+ */
60125896 #define _CURBCNTR 0x700c0
60135897 #define _CURBBASE 0x700c4
60145898 #define _CURBPOS 0x700c8
@@ -6025,6 +5909,7 @@ enum { · 10 unmodified lines
60255909 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
60265910 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
60275911 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
5912+#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
60285913
60295914 #define CURSOR_A_OFFSET 0x70080
60305915 #define CURSOR_B_OFFSET 0x700c0
@@ -6779,6 +6664,8 @@ enum { · 748 unmodified lines
67796664 #define PS_SCALER_MODE_MASK (3 << 28)
67806665 #define PS_SCALER_MODE_DYN (0 << 28)
67816666 #define PS_SCALER_MODE_HQ (1 << 28)
6667+#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
6668+#define PS_SCALER_MODE_PLANAR (1 << 29)
67826669 #define PS_PLANE_SEL_MASK (7 << 25)
67836670 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
67846671 #define PS_FILTER_MASK (3 << 23)
@@ -7117,7 +7004,9 @@ enum { · 332 unmodified lines
71177004 #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
71187005 #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
71197006 #define GEN11_INTR_DATA_VALID (1 << 31)
7120−#define GEN11_INTR_ENGINE_MASK (0xffff)
7007+#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
7008+#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
7009+#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
71217010
71227011 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + (x * 4))
71237012
@@ -7197,6 +7086,7 @@ enum { · 73 unmodified lines
71977086 #define CHICKEN_TRANS_A 0x420c0
71987087 #define CHICKEN_TRANS_B 0x420c4
71997088 #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
7089+#define VSC_DATA_SEL_SOFTWARE_CONTROL (1<<25) /* GLK and CNL+ */
72007090 #define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
72017091 #define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
72027092 #define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
drivers/gpu/drm/i915/i915_request.c+53−72
@@ -59,11 +59,7 @@ static bool i915_fence_signaled(struct dma_fence *fence) · 58 unmodified lines
5959
6060 static bool i915_fence_enable_signaling(struct dma_fence *fence)
6161 {
62− if (i915_fence_signaled(fence))
63− return false;
64−
65− intel_engine_enable_signaling(to_request(fence), true);
66− return !i915_fence_signaled(fence);
62+ return intel_engine_enable_signaling(to_request(fence), true);
6763 }
6864
6965 static signed long i915_fence_wait(struct dma_fence *fence,
@@ -211,11 +207,19 @@ static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno) · 141 unmodified lines
211207 if (ret)
212208 return ret;
213209
210+ GEM_BUG_ON(i915->gt.active_requests);
211+
214212 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
215213 for_each_engine(engine, i915, id) {
216214 struct i915_gem_timeline *timeline;
217215 struct intel_timeline *tl = engine->timeline;
218216
217+ GEM_TRACE("%s seqno %d (current %d) -> %d\n",
218+ engine->name,
219+ tl->seqno,
220+ intel_engine_get_seqno(engine),
221+ seqno);
222+
219223 if (!i915_seqno_passed(seqno, tl->seqno)) {
220224 /* Flush any waiters before we reuse the seqno */
221225 intel_engine_disarm_breadcrumbs(engine);
@@ -251,47 +255,6 @@ int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno) · 29 unmodified lines
251255 return reset_all_global_seqno(i915, seqno - 1);
252256 }
253257
254−static void mark_busy(struct drm_i915_private *i915)
255−{
256− if (i915->gt.awake)
257− return;
258−
259− GEM_BUG_ON(!i915->gt.active_requests);
260−
261− intel_runtime_pm_get_noresume(i915);
262−
263− /*
264− * It seems that the DMC likes to transition between the DC states a lot
265− * when there are no connected displays (no active power domains) during
266− * command submission.
267− *
268− * This activity has negative impact on the performance of the chip with
269− * huge latencies observed in the interrupt handler and elsewhere.
270− *
271− * Work around it by grabbing a GT IRQ power domain whilst there is any
272− * GT activity, preventing any DC state transitions.
273− */
274− intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
275−
276− i915->gt.awake = true;
277− if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */
278− i915->gt.epoch = 1;
279−
280− intel_enable_gt_powersave(i915);
281− i915_update_gfx_val(i915);
282− if (INTEL_GEN(i915) >= 6)
283− gen6_rps_busy(i915);
284− i915_pmu_gt_unparked(i915);
285−
286− intel_engines_unpark(i915);
287−
288− i915_queue_hangcheck(i915);
289−
290− queue_delayed_work(i915->wq,
291− &i915->gt.retire_work,
292− round_jiffies_up_relative(HZ));
293−}
294−
295258 static int reserve_engine(struct intel_engine_cs *engine)
296259 {
297260 struct drm_i915_private *i915 = engine->i915;
@@ -309,7 +272,7 @@ static int reserve_engine(struct intel_engine_cs *engine) · 11 unmodified lines
309272 }
310273
311274 if (!i915->gt.active_requests++)
312− mark_busy(i915);
275+ i915_gem_unpark(i915);
313276
314277 return 0;
315278 }
@@ -318,13 +281,8 @@ static void unreserve_engine(struct intel_engine_cs *engine) · 2 unmodified lines
318281 {
319282 struct drm_i915_private *i915 = engine->i915;
320283
321− if (!--i915->gt.active_requests) {
322− /* Cancel the mark_busy() from our reserve_engine() */
323− GEM_BUG_ON(!i915->gt.awake);
324− mod_delayed_work(i915->wq,
325− &i915->gt.idle_work,
326− msecs_to_jiffies(100));
327− }
284+ if (!--i915->gt.active_requests)
285+ i915_gem_park(i915);
328286
329287 GEM_BUG_ON(!engine->timeline->inflight_seqnos);
330288 engine->timeline->inflight_seqnos--;
@@ -358,7 +316,7 @@ static void advance_ring(struct i915_request *request) · 27 unmodified lines
358316 * is just about to be. Either works, if we miss the last two
359317 * noops - they are safe to be replayed on a reset.
360318 */
361− tail = READ_ONCE(request->ring->tail);
319+ tail = READ_ONCE(request->tail);
362320 } else {
363321 tail = request->postfix;
364322 }
@@ -385,6 +343,12 @@ static void i915_request_retire(struct i915_request *request) · 20 unmodified lines
385343 struct intel_engine_cs *engine = request->engine;
386344 struct i915_gem_active *active, *next;
387345
346+ GEM_TRACE("%s fence %llx:%d, global=%d, current %d\n",
347+ engine->name,
348+ request->fence.context, request->fence.seqno,
349+ request->global_seqno,
350+ intel_engine_get_seqno(engine));
351+
388352 lockdep_assert_held(&request->i915->drm.struct_mutex);
389353 GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit));
390354 GEM_BUG_ON(!i915_request_completed(request));
@@ -486,21 +450,34 @@ static u32 timeline_get_seqno(struct intel_timeline *tl) · 95 unmodified lines
486450 return ++tl->seqno;
487451 }
488452
453+static void move_to_timeline(struct i915_request *request,
454+ struct intel_timeline *timeline)
455+{
456+ GEM_BUG_ON(request->timeline == request->engine->timeline);
457+ lockdep_assert_held(&request->engine->timeline->lock);
458+
459+ spin_lock(&request->timeline->lock);
460+ list_move_tail(&request->link, &timeline->requests);
461+ spin_unlock(&request->timeline->lock);
462+}
463+
489464 void __i915_request_submit(struct i915_request *request)
490465 {
491466 struct intel_engine_cs *engine = request->engine;
492− struct intel_timeline *timeline;
493467 u32 seqno;
494468
469+ GEM_TRACE("%s fence %llx:%d -> global=%d, current %d\n",
470+ engine->name,
471+ request->fence.context, request->fence.seqno,
472+ engine->timeline->seqno + 1,
473+ intel_engine_get_seqno(engine));
474+
495475 GEM_BUG_ON(!irqs_disabled());
496476 lockdep_assert_held(&engine->timeline->lock);
497477
498− /* Transfer from per-context onto the global per-engine timeline */
499− timeline = engine->timeline;
500− GEM_BUG_ON(timeline == request->timeline);
501478 GEM_BUG_ON(request->global_seqno);
502479
503− seqno = timeline_get_seqno(timeline);
480+ seqno = timeline_get_seqno(engine->timeline);
504481 GEM_BUG_ON(!seqno);
505482 GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno));
506483
@@ -514,9 +491,8 @@ void __i915_request_submit(struct i915_request *request) · 7 unmodified lines
514491 engine->emit_breadcrumb(request,
515492 request->ring->vaddr + request->postfix);
516493
517− spin_lock(&request->timeline->lock);
518− list_move_tail(&request->link, &timeline->requests);
519− spin_unlock(&request->timeline->lock);
494+ /* Transfer from per-context onto the global per-engine timeline */
495+ move_to_timeline(request, engine->timeline);
520496
521497 trace_i915_request_execute(request);
522498
@@ -539,7 +515,12 @@ void i915_request_submit(struct i915_request *request) · 16 unmodified lines
539515 void __i915_request_unsubmit(struct i915_request *request)
540516 {
541517 struct intel_engine_cs *engine = request->engine;
542− struct intel_timeline *timeline;
518+
519+ GEM_TRACE("%s fence %llx:%d <- global=%d, current %d\n",
520+ engine->name,
521+ request->fence.context, request->fence.seqno,
522+ request->global_seqno,
523+ intel_engine_get_seqno(engine));
543524
544525 GEM_BUG_ON(!irqs_disabled());
545526 lockdep_assert_held(&engine->timeline->lock);
@@ -562,12 +543,7 @@ void __i915_request_unsubmit(struct i915_request *request) · 16 unmodified lines
562543 spin_unlock(&request->lock);
563544
564545 /* Transfer back from the global per-engine timeline to per-context */
565− timeline = request->timeline;
566− GEM_BUG_ON(timeline == engine->timeline);
567−
568− spin_lock(&timeline->lock);
569− list_move(&request->link, &timeline->requests);
570− spin_unlock(&timeline->lock);
546+ move_to_timeline(request, request->timeline);
571547
572548 /*
573549 * We don't need to wake_up any waiters on request->execute, they
@@ -1000,6 +976,9 @@ void __i915_request_add(struct i915_request *request, bool flush_caches) · 426 unmodified lines
1000976 u32 *cs;
1001977 int err;
1002978
979+ GEM_TRACE("%s fence %llx:%d\n",
980+ engine->name, request->fence.context, request->fence.seqno);
981+
1003982 lockdep_assert_held(&request->i915->drm.struct_mutex);
1004983 trace_i915_request_add(request);
1005984
@@ -1206,11 +1185,13 @@ static bool __i915_spin_request(const struct i915_request *rq, · 200 unmodified lines
12061185
12071186 static bool __i915_wait_request_check_and_reset(struct i915_request *request)
12081187 {
1209− if (likely(!i915_reset_handoff(&request->i915->gpu_error)))
1188+ struct i915_gpu_error *error = &request->i915->gpu_error;
1189+
1190+ if (likely(!i915_reset_handoff(error)))
12101191 return false;
12111192
12121193 __set_current_state(TASK_RUNNING);
1213− i915_reset(request->i915, 0);
1194+ i915_reset(request->i915, error->stalled_mask, error->reason);
12141195 return true;
12151196 }
12161197
drivers/gpu/drm/i915/i915_utils.h+2−2
@@ -40,8 +40,8 @@ · 39 unmodified lines
4040 #undef WARN_ON_ONCE
4141 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
4242
43−#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
44− (long)(x), __func__)
43+#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
44+ __stringify(x), (long)(x))
4545
4646 #if GCC_VERSION >= 70000
4747 #define add_overflows(A, B) \
drivers/gpu/drm/i915/intel_atomic.c+15−4
@@ -227,6 +227,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, · 226 unmodified lines
227227 struct intel_crtc_scaler_state *scaler_state =
228228 &crtc_state->scaler_state;
229229 struct drm_atomic_state *drm_state = crtc_state->base.state;
230+ struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
230231 int num_scalers_need;
231232 int i, j;
232233
@@ -304,8 +305,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, · 71 unmodified lines
304305 continue;
305306 }
306307
307− plane_state = intel_atomic_get_existing_plane_state(drm_state,
308− intel_plane);
308+ plane_state = intel_atomic_get_new_plane_state(intel_state,
309+ intel_plane);
309310 scaler_id = &plane_state->scaler_id;
310311 }
311312
@@ -328,8 +329,18 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, · 16 unmodified lines
328329 }
329330
330331 /* set scaler mode */
331− if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
332− scaler_state->scalers[*scaler_id].mode = 0;
332+ if ((INTEL_GEN(dev_priv) >= 9) &&
333+ plane_state && plane_state->base.fb &&
334+ plane_state->base.fb->format->format ==
335+ DRM_FORMAT_NV12) {
336+ if (INTEL_GEN(dev_priv) == 9 &&
337+ !IS_GEMINILAKE(dev_priv) &&
338+ !IS_SKYLAKE(dev_priv))
339+ scaler_state->scalers[*scaler_id].mode =
340+ SKL_PS_SCALER_MODE_NV12;
341+ else
342+ scaler_state->scalers[*scaler_id].mode =
343+ PS_SCALER_MODE_PLANAR;
333344 } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
334345 /*
335346 * when only 1 scaler is in use on either pipe A or B,
drivers/gpu/drm/i915/intel_bios.c+4−13
@@ -1215,10 +1215,8 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, · 1214 unmodified lines
12151215 {
12161216 struct child_device_config *it, *child = NULL;
12171217 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
1218− uint8_t hdmi_level_shift;
12191218 int i, j;
12201219 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
1221− uint8_t aux_channel, ddc_pin;
12221220 /* Each DDI port can have more than one value on the "DVO Port" field,
12231221 * so look for all the possible values for each port.
12241222 */
@@ -1255,8 +1253,6 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, · 30 unmodified lines
12551253 if (!child)
12561254 return;
12571255
1258− aux_channel = child->aux_channel;
1259−
12601256 is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
12611257 is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
12621258 is_crt = child->device_type & DEVICE_TYPE_ANALOG_OUTPUT;
@@ -1270,13 +1266,6 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, · 7 unmodified lines
12701266 is_hdmi = false;
12711267 }
12721268
1273− if (port == PORT_A && is_dvi) {
1274− DRM_DEBUG_KMS("VBT claims port A supports DVI%s, ignoring\n",
1275− is_hdmi ? "/HDMI" : "");
1276− is_dvi = false;
1277− is_hdmi = false;
1278− }
1279−
12801269 info->supports_dvi = is_dvi;
12811270 info->supports_hdmi = is_hdmi;
12821271 info->supports_dp = is_dp;
@@ -1302,6 +1291,8 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, · 19 unmodified lines
13021291 DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
13031292
13041293 if (is_dvi) {
1294+ u8 ddc_pin;
1295+
13051296 ddc_pin = map_ddc_pin(dev_priv, child->ddc_pin);
13061297 if (intel_gmbus_is_valid_pin(dev_priv, ddc_pin)) {
13071298 info->alternate_ddc_pin = ddc_pin;
@@ -1314,14 +1305,14 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, · 6 unmodified lines
13141305 }
13151306
13161307 if (is_dp) {
1317− info->alternate_aux_channel = aux_channel;
1308+ info->alternate_aux_channel = child->aux_channel;
13181309
13191310 sanitize_aux_ch(dev_priv, port);
13201311 }
13211312
13221313 if (bdb_version >= 158) {
13231314 /* The VBT HDMI level shift values match the table we have. */
1324− hdmi_level_shift = child->hdmi_level_shifter_value;
1315+ u8 hdmi_level_shift = child->hdmi_level_shifter_value;
13251316 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
13261317 port_name(port),
13271318 hdmi_level_shift);
drivers/gpu/drm/i915/intel_breadcrumbs.c+13−8
@@ -730,10 +730,11 @@ static void insert_signal(struct intel_breadcrumbs *b, · 729 unmodified lines
730730 list_add(&request->signaling.link, &iter->signaling.link);
731731 }
732732
733−void intel_engine_enable_signaling(struct i915_request *request, bool wakeup)
733+bool intel_engine_enable_signaling(struct i915_request *request, bool wakeup)
734734 {
735735 struct intel_engine_cs *engine = request->engine;
736736 struct intel_breadcrumbs *b = &engine->breadcrumbs;
737+ struct intel_wait *wait = &request->signaling.wait;
737738 u32 seqno;
738739
739740 /*
@@ -750,12 +751,12 @@ void intel_engine_enable_signaling(struct i915_request *request, bool wakeup) · 10 unmodified lines
750751
751752 seqno = i915_request_global_seqno(request);
752753 if (!seqno) /* will be enabled later upon execution */
753− return;
754+ return true;
754755
755− GEM_BUG_ON(request->signaling.wait.seqno);
756− request->signaling.wait.tsk = b->signaler;
757− request->signaling.wait.request = request;
758− request->signaling.wait.seqno = seqno;
756+ GEM_BUG_ON(wait->seqno);
757+ wait->tsk = b->signaler;
758+ wait->request = request;
759+ wait->seqno = seqno;
759760
760761 /*
761762 * Add ourselves into the list of waiters, but registering our
@@ -768,11 +769,15 @@ void intel_engine_enable_signaling(struct i915_request *request, bool wakeup) · 6 unmodified lines
768769 */
769770 spin_lock(&b->rb_lock);
770771 insert_signal(b, request, seqno);
771− wakeup &= __intel_engine_add_wait(engine, &request->signaling.wait);
772+ wakeup &= __intel_engine_add_wait(engine, wait);
772773 spin_unlock(&b->rb_lock);
773774
774− if (wakeup)
775+ if (wakeup) {
775776 wake_up_process(b->signaler);
777+ return !intel_wait_complete(wait);
778+ }
779+
780+ return true;
776781 }
777782
778783 void intel_engine_cancel_signaling(struct i915_request *request)
drivers/gpu/drm/i915/intel_ddi.c+141−13
@@ -493,6 +493,125 @@ static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { · 492 unmodified lines
493493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494494 };
495495
496+struct icl_combo_phy_ddi_buf_trans {
497+ u32 dw2_swing_select;
498+ u32 dw2_swing_scalar;
499+ u32 dw4_scaling;
500+};
501+
502+/* Voltage Swing Programming for VccIO 0.85V for DP */
503+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
504+ /* Voltage mV db */
505+ { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
506+ { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
507+ { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
508+ { 0x2, 0x98, 0x900F }, /* 400 9.5 */
509+ { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
510+ { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
511+ { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
512+ { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
513+ { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
514+ { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
515+};
516+
517+/* FIXME - After table is updated in Bspec */
518+/* Voltage Swing Programming for VccIO 0.85V for eDP */
519+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
520+ /* Voltage mV db */
521+ { 0x0, 0x00, 0x00 }, /* 200 0.0 */
522+ { 0x0, 0x00, 0x00 }, /* 200 1.5 */
523+ { 0x0, 0x00, 0x00 }, /* 200 4.0 */
524+ { 0x0, 0x00, 0x00 }, /* 200 6.0 */
525+ { 0x0, 0x00, 0x00 }, /* 250 0.0 */
526+ { 0x0, 0x00, 0x00 }, /* 250 1.5 */
527+ { 0x0, 0x00, 0x00 }, /* 250 4.0 */
528+ { 0x0, 0x00, 0x00 }, /* 300 0.0 */
529+ { 0x0, 0x00, 0x00 }, /* 300 1.5 */
530+ { 0x0, 0x00, 0x00 }, /* 350 0.0 */
531+};
532+
533+/* Voltage Swing Programming for VccIO 0.95V for DP */
534+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
535+ /* Voltage mV db */
536+ { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
537+ { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
538+ { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
539+ { 0x2, 0x98, 0x900F }, /* 400 9.5 */
540+ { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
541+ { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
542+ { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
543+ { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
544+ { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
545+ { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
546+};
547+
548+/* FIXME - After table is updated in Bspec */
549+/* Voltage Swing Programming for VccIO 0.95V for eDP */
550+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
551+ /* Voltage mV db */
552+ { 0x0, 0x00, 0x00 }, /* 200 0.0 */
553+ { 0x0, 0x00, 0x00 }, /* 200 1.5 */
554+ { 0x0, 0x00, 0x00 }, /* 200 4.0 */
555+ { 0x0, 0x00, 0x00 }, /* 200 6.0 */
556+ { 0x0, 0x00, 0x00 }, /* 250 0.0 */
557+ { 0x0, 0x00, 0x00 }, /* 250 1.5 */
558+ { 0x0, 0x00, 0x00 }, /* 250 4.0 */
559+ { 0x0, 0x00, 0x00 }, /* 300 0.0 */
560+ { 0x0, 0x00, 0x00 }, /* 300 1.5 */
561+ { 0x0, 0x00, 0x00 }, /* 350 0.0 */
562+};
563+
564+/* Voltage Swing Programming for VccIO 1.05V for DP */
565+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
566+ /* Voltage mV db */
567+ { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
568+ { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
569+ { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
570+ { 0x2, 0x98, 0x900F }, /* 400 9.5 */
571+ { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
572+ { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
573+ { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
574+ { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
575+ { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
576+ { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
577+};
578+
579+/* FIXME - After table is updated in Bspec */
580+/* Voltage Swing Programming for VccIO 1.05V for eDP */
581+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
582+ /* Voltage mV db */
583+ { 0x0, 0x00, 0x00 }, /* 200 0.0 */
584+ { 0x0, 0x00, 0x00 }, /* 200 1.5 */
585+ { 0x0, 0x00, 0x00 }, /* 200 4.0 */
586+ { 0x0, 0x00, 0x00 }, /* 200 6.0 */
587+ { 0x0, 0x00, 0x00 }, /* 250 0.0 */
588+ { 0x0, 0x00, 0x00 }, /* 250 1.5 */
589+ { 0x0, 0x00, 0x00 }, /* 250 4.0 */
590+ { 0x0, 0x00, 0x00 }, /* 300 0.0 */
591+ { 0x0, 0x00, 0x00 }, /* 300 1.5 */
592+ { 0x0, 0x00, 0x00 }, /* 350 0.0 */
593+};
594+
595+struct icl_mg_phy_ddi_buf_trans {
596+ u32 cri_txdeemph_override_5_0;
597+ u32 cri_txdeemph_override_11_6;
598+ u32 cri_txdeemph_override_17_12;
599+};
600+
601+static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
602+ /* Voltage swing pre-emphasis */
603+ { 0x0, 0x1B, 0x00 }, /* 0 0 */
604+ { 0x0, 0x23, 0x08 }, /* 0 1 */
605+ { 0x0, 0x2D, 0x12 }, /* 0 2 */
606+ { 0x0, 0x00, 0x00 }, /* 0 3 */
607+ { 0x0, 0x23, 0x00 }, /* 1 0 */
608+ { 0x0, 0x2B, 0x09 }, /* 1 1 */
609+ { 0x0, 0x2E, 0x11 }, /* 1 2 */
610+ { 0x0, 0x2F, 0x00 }, /* 2 0 */
611+ { 0x0, 0x33, 0x0C }, /* 2 1 */
612+ { 0x0, 0x00, 0x00 }, /* 3 0 */
613+};
614+
496615 static const struct ddi_buf_trans *
497616 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
498617 {
@@ -875,7 +994,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, · 376 unmodified lines
875994
876995 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
877996 {
878− switch (pll->id) {
997+ switch (pll->info->id) {
879998 case DPLL_ID_WRPLL1:
880999 return PORT_CLK_SEL_WRPLL1;
8811000 case DPLL_ID_WRPLL2:
@@ -889,7 +1008,7 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) · 7 unmodified lines
8891008 case DPLL_ID_LCPLL_2700:
8901009 return PORT_CLK_SEL_LCPLL_2700;
8911010 default:
892− MISSING_CASE(pll->id);
1011+ MISSING_CASE(pll->info->id);
8931012 return PORT_CLK_SEL_NONE;
8941013 }
8951014 }
@@ -2131,7 +2250,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, · 1235 unmodified lines
21312250 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
21322251 val = I915_READ(DPCLKA_CFGCR0);
21332252 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2134− val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2253+ val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
21352254 I915_WRITE(DPCLKA_CFGCR0, val);
21362255
21372256 /*
@@ -2148,7 +2267,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, · 10 unmodified lines
21482267
21492268 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
21502269 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2151− val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
2270+ val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
21522271 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
21532272
21542273 I915_WRITE(DPLL_CTRL2, val);
@@ -2205,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, · 50 unmodified lines
22052324 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
22062325
22072326 intel_ddi_init_dp_buf_reg(encoder);
2208− intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2327+ if (!is_mst)
2328+ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
22092329 intel_dp_start_link_train(intel_dp);
22102330 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
22112331 intel_dp_stop_link_train(intel_dp);
@@ -2303,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, · 91 unmodified lines
23032423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
23042424 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
23052425 struct intel_dp *intel_dp = &dig_port->dp;
2426+ bool is_mst = intel_crtc_has_type(old_crtc_state,
2427+ INTEL_OUTPUT_DP_MST);
23062428
23072429 /*
23082430 * Power down sink before disabling the port, otherwise we end
23092431 * up getting interrupts from the sink on detecting link loss.
23102432 */
2311− intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2433+ if (!is_mst)
2434+ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
23122435
23132436 intel_disable_ddi_buf(encoder);
23142437
@@ -2424,12 +2547,14 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, · 109 unmodified lines
24242547 {
24252548 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
24262549 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2550+ struct drm_connector *connector = conn_state->connector;
24272551 enum port port = encoder->port;
24282552
2429− intel_hdmi_handle_sink_scrambling(encoder,
2430− conn_state->connector,
2431− crtc_state->hdmi_high_tmds_clock_ratio,
2432− crtc_state->hdmi_scrambling);
2553+ if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2554+ crtc_state->hdmi_high_tmds_clock_ratio,
2555+ crtc_state->hdmi_scrambling))
2556+ DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
2557+ connector->base.id, connector->name);
24332558
24342559 /* Display WA #1143: skl,kbl,cfl */
24352560 if (IS_GEN9_BC(dev_priv)) {
@@ -2520,13 +2645,16 @@ static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, · 84 unmodified lines
25202645 const struct intel_crtc_state *old_crtc_state,
25212646 const struct drm_connector_state *old_conn_state)
25222647 {
2648+ struct drm_connector *connector = old_conn_state->connector;
2649+
25232650 if (old_crtc_state->has_audio)
25242651 intel_audio_codec_disable(encoder,
25252652 old_crtc_state, old_conn_state);
25262653
2527− intel_hdmi_handle_sink_scrambling(encoder,
2528− old_conn_state->connector,
2529− false, false);
2654+ if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2655+ false, false))
2656+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
2657+ connector->base.id, connector->name);
25302658 }
25312659
25322660 static void intel_disable_ddi(struct intel_encoder *encoder,
drivers/gpu/drm/i915/intel_device_info.c+148−21
@@ -83,11 +83,11 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) · 82 unmodified lines
8383 {
8484 int s;
8585
86− drm_printf(p, "slice mask: %04x\n", sseu->slice_mask);
87− drm_printf(p, "slice total: %u\n", hweight8(sseu->slice_mask));
86+ drm_printf(p, "slice total: %u, mask=%04x\n",
87+ hweight8(sseu->slice_mask), sseu->slice_mask);
8888 drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
89− for (s = 0; s < ARRAY_SIZE(sseu->subslice_mask); s++) {
90− drm_printf(p, "slice%d %u subslices mask=%04x\n",
89+ for (s = 0; s < sseu->max_slices; s++) {
90+ drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
9191 s, hweight8(sseu->subslice_mask[s]),
9292 sseu->subslice_mask[s]);
9393 }
@@ -158,6 +158,45 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu) · 64 unmodified lines
158158 return total;
159159 }
160160
161+static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
162+{
163+ struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
164+ u8 s_en;
165+ u32 ss_en, ss_en_mask;
166+ u8 eu_en;
167+ int s;
168+
169+ sseu->max_slices = 1;
170+ sseu->max_subslices = 8;
171+ sseu->max_eus_per_subslice = 8;
172+
173+ s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
174+ ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
175+ ss_en_mask = BIT(sseu->max_subslices) - 1;
176+ eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
177+
178+ for (s = 0; s < sseu->max_slices; s++) {
179+ if (s_en & BIT(s)) {
180+ int ss_idx = sseu->max_subslices * s;
181+ int ss;
182+
183+ sseu->slice_mask |= BIT(s);
184+ sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
185+ for (ss = 0; ss < sseu->max_subslices; ss++) {
186+ if (sseu->subslice_mask[s] & BIT(ss))
187+ sseu_set_eus(sseu, s, ss, eu_en);
188+ }
189+ }
190+ }
191+ sseu->eu_per_subslice = hweight8(eu_en);
192+ sseu->eu_total = compute_eu_total(sseu);
193+
194+ /* ICL has no power gating restrictions. */
195+ sseu->has_slice_pg = 1;
196+ sseu->has_subslice_pg = 1;
197+ sseu->has_eu_pg = 1;
198+}
199+
161200 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
162201 {
163202 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -557,6 +596,52 @@ static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) · 393 unmodified lines
557596 return base_freq + frac_freq;
558597 }
559598
599+static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
600+ u32 rpm_config_reg)
601+{
602+ u32 f19_2_mhz = 19200;
603+ u32 f24_mhz = 24000;
604+ u32 crystal_clock = (rpm_config_reg &
605+ GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
606+ GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
607+
608+ switch (crystal_clock) {
609+ case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
610+ return f19_2_mhz;
611+ case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
612+ return f24_mhz;
613+ default:
614+ MISSING_CASE(crystal_clock);
615+ return 0;
616+ }
617+}
618+
619+static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
620+ u32 rpm_config_reg)
621+{
622+ u32 f19_2_mhz = 19200;
623+ u32 f24_mhz = 24000;
624+ u32 f25_mhz = 25000;
625+ u32 f38_4_mhz = 38400;
626+ u32 crystal_clock = (rpm_config_reg &
627+ GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
628+ GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
629+
630+ switch (crystal_clock) {
631+ case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
632+ return f24_mhz;
633+ case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
634+ return f19_2_mhz;
635+ case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
636+ return f38_4_mhz;
637+ case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
638+ return f25_mhz;
639+ default:
640+ MISSING_CASE(crystal_clock);
641+ return 0;
642+ }
643+}
644+
560645 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
561646 {
562647 u32 f12_5_mhz = 12500;
@@ -597,10 +682,9 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) · 34 unmodified lines
597682 }
598683
599684 return freq;
600− } else if (INTEL_GEN(dev_priv) <= 10) {
685+ } else if (INTEL_GEN(dev_priv) <= 11) {
601686 u32 ctc_reg = I915_READ(CTC_MODE);
602687 u32 freq = 0;
603− u32 rpm_config_reg = 0;
604688
605689 /* First figure out the reference frequency. There are 2 ways
606690 * we can compute the frequency, either through the
@@ -610,20 +694,14 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) · 3 unmodified lines
610694 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
611695 freq = read_reference_ts_freq(dev_priv);
612696 } else {
613− u32 crystal_clock;
614−
615− rpm_config_reg = I915_READ(RPM_CONFIG0);
616− crystal_clock = (rpm_config_reg &
617− GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
618− GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
619− switch (crystal_clock) {
620− case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
621− freq = f19_2_mhz;
622− break;
623− case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
624− freq = f24_mhz;
625− break;
626− }
697+ u32 rpm_config_reg = I915_READ(RPM_CONFIG0);
698+
699+ if (INTEL_GEN(dev_priv) <= 10)
700+ freq = gen10_get_crystal_clock_freq(dev_priv,
701+ rpm_config_reg);
702+ else
703+ freq = gen11_get_crystal_clock_freq(dev_priv,
704+ rpm_config_reg);
627705
628706 /* Now figure out how the command stream's timestamp
629707 * register increments from this frequency (it might
@@ -768,8 +846,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info) · 138 unmodified lines
768846 broadwell_sseu_info_init(dev_priv);
769847 else if (INTEL_GEN(dev_priv) == 9)
770848 gen9_sseu_info_init(dev_priv);
771− else if (INTEL_GEN(dev_priv) >= 10)
849+ else if (INTEL_GEN(dev_priv) == 10)
772850 gen10_sseu_info_init(dev_priv);
851+ else if (INTEL_INFO(dev_priv)->gen >= 11)
852+ gen11_sseu_info_init(dev_priv);
773853
774854 /* Initialize command stream timestamp frequency */
775855 info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
@@ -780,3 +860,50 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps, · 4 unmodified lines
780860 {
781861 drm_printf(p, "scheduler: %x\n", caps->scheduler);
782862 }
863+
864+/*
865+ * Determine which engines are fused off in our particular hardware. Since the
866+ * fuse register is in the blitter powerwell, we need forcewake to be ready at
867+ * this point (but later we need to prune the forcewake domains for engines that
868+ * are indeed fused off).
869+ */
870+void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
871+{
872+ struct intel_device_info *info = mkwrite_device_info(dev_priv);
873+ u8 vdbox_disable, vebox_disable;
874+ u32 media_fuse;
875+ int i;
876+
877+ if (INTEL_GEN(dev_priv) < 11)
878+ return;
879+
880+ media_fuse = I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
881+
882+ vdbox_disable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
883+ vebox_disable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
884+ GEN11_GT_VEBOX_DISABLE_SHIFT;
885+
886+ DRM_DEBUG_DRIVER("vdbox disable: %04x\n", vdbox_disable);
887+ for (i = 0; i < I915_MAX_VCS; i++) {
888+ if (!HAS_ENGINE(dev_priv, _VCS(i)))
889+ continue;
890+
891+ if (!(BIT(i) & vdbox_disable))
892+ continue;
893+
894+ info->ring_mask &= ~ENGINE_MASK(_VCS(i));
895+ DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
896+ }
897+
898+ DRM_DEBUG_DRIVER("vebox disable: %04x\n", vebox_disable);
899+ for (i = 0; i < I915_MAX_VECS; i++) {
900+ if (!HAS_ENGINE(dev_priv, _VECS(i)))
901+ continue;
902+
903+ if (!(BIT(i) & vebox_disable))
904+ continue;
905+
906+ info->ring_mask &= ~ENGINE_MASK(_VECS(i));
907+ DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
908+ }
909+}
drivers/gpu/drm/i915/intel_device_info.h+3−1
@@ -114,7 +114,7 @@ enum intel_platform { · 113 unmodified lines
114114 func(has_ipc);
115115
116116 #define GEN_MAX_SLICES (6) /* CNL upper bound */
117−#define GEN_MAX_SUBSLICES (7)
117+#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
118118
119119 struct sseu_dev_info {
120120 u8 slice_mask;
@@ -247,6 +247,8 @@ void intel_device_info_dump_runtime(const struct intel_device_info *info, · 126 unmodified lines
247247 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
248248 struct drm_printer *p);
249249
250+void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
251+
250252 void intel_driver_caps_print(const struct intel_driver_caps *caps,
251253 struct drm_printer *p);
252254
drivers/gpu/drm/i915/intel_display.c+171−80
@@ -488,6 +488,21 @@ static const struct intel_limit intel_limits_bxt = { · 487 unmodified lines
488488 .p2 = { .p2_slow = 1, .p2_fast = 20 },
489489 };
490490
491+static void
492+skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
493+{
494+ if (IS_SKYLAKE(dev_priv))
495+ return;
496+
497+ if (enable)
498+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
499+ DUPS1_GATING_DIS | DUPS2_GATING_DIS);
500+ else
501+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
502+ I915_READ(CLKGATE_DIS_PSL(pipe)) &
503+ ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
504+}
505+
491506 static bool
492507 needs_modeset(const struct drm_crtc_state *state)
493508 {
@@ -2657,11 +2672,13 @@ static int i9xx_format_to_fourcc(int format) · 2163 unmodified lines
26572672 }
26582673 }
26592674
2660−static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2675+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
26612676 {
26622677 switch (format) {
26632678 case PLANE_CTL_FORMAT_RGB_565:
26642679 return DRM_FORMAT_RGB565;
2680+ case PLANE_CTL_FORMAT_NV12:
2681+ return DRM_FORMAT_NV12;
26652682 default:
26662683 case PLANE_CTL_FORMAT_XRGB_8888:
26672684 if (rgb_order) {
@@ -2858,6 +2875,9 @@ valid_fb: · 190 unmodified lines
28582875 return;
28592876 }
28602877
2878+ obj = intel_fb_obj(fb);
2879+ intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2880+
28612881 plane_state->src_x = 0;
28622882 plane_state->src_y = 0;
28632883 plane_state->src_w = fb->width << 16;
@@ -2871,7 +2891,6 @@ valid_fb: · 7 unmodified lines
28712891 intel_state->base.src = drm_plane_state_src(plane_state);
28722892 intel_state->base.dst = drm_plane_state_dest(plane_state);
28732893
2874− obj = intel_fb_obj(fb);
28752894 if (i915_gem_object_is_tiled(obj))
28762895 dev_priv->preserve_bios_swizzle = true;
28772896
@@ -3464,6 +3483,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) · 586 unmodified lines
34643483 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
34653484 case DRM_FORMAT_VYUY:
34663485 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3486+ case DRM_FORMAT_NV12:
3487+ return PLANE_CTL_FORMAT_NV12;
34673488 default:
34683489 MISSING_CASE(pixel_format);
34693490 }
@@ -3611,6 +3632,11 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, · 141 unmodified lines
36113632 plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
36123633
36133634 if (intel_format_is_yuv(fb->format->format)) {
3635+ if (fb->format->format == DRM_FORMAT_NV12) {
3636+ plane_color_ctl |=
3637+ PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3638+ goto out;
3639+ }
36143640 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
36153641 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
36163642 else
@@ -3619,7 +3645,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, · 2 unmodified lines
36193645 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
36203646 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
36213647 }
3622−
3648+out:
36233649 return plane_color_ctl;
36243650 }
36253651
@@ -3675,7 +3701,6 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) · 49 unmodified lines
36753701 struct drm_atomic_state *state;
36763702 int ret;
36773703
3678−
36793704 /* reset doesn't touch the display */
36803705 if (!i915_modparams.force_reset_modeset_test &&
36813706 !gpu_reset_clobbers_display(dev_priv))
@@ -3729,19 +3754,17 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) · 47 unmodified lines
37293754 {
37303755 struct drm_device *dev = &dev_priv->drm;
37313756 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3732− struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3757+ struct drm_atomic_state *state;
37333758 int ret;
37343759
37353760 /* reset doesn't touch the display */
3736− if (!i915_modparams.force_reset_modeset_test &&
3737− !gpu_reset_clobbers_display(dev_priv))
3761+ if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
37383762 return;
37393763
3764+ state = fetch_and_zero(&dev_priv->modeset_restore_state);
37403765 if (!state)
37413766 goto unlock;
37423767
3743− dev_priv->modeset_restore_state = NULL;
3744−
37453768 /* reset doesn't touch the display */
37463769 if (!gpu_reset_clobbers_display(dev_priv)) {
37473770 /* for testing only restore the display */
@@ -4703,7 +4726,9 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe) · 955 unmodified lines
47034726 static int
47044727 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
47054728 unsigned int scaler_user, int *scaler_id,
4706− int src_w, int src_h, int dst_w, int dst_h)
4729+ int src_w, int src_h, int dst_w, int dst_h,
4730+ bool plane_scaler_check,
4731+ uint32_t pixel_format)
47074732 {
47084733 struct intel_crtc_scaler_state *scaler_state =
47094734 &crtc_state->scaler_state;
@@ -4721,6 +4746,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, · 11 unmodified lines
47214746 */
47224747 need_scaling = src_w != dst_w || src_h != dst_h;
47234748
4749+ if (plane_scaler_check)
4750+ if (pixel_format == DRM_FORMAT_NV12)
4751+ need_scaling = true;
4752+
47244753 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
47254754 need_scaling = true;
47264755
@@ -4760,12 +4789,22 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, · 33 unmodified lines
47604789 return 0;
47614790 }
47624791
4792+ if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
4793+ (src_h < SKL_MIN_YUV_420_SRC_H || (src_w % 4) != 0 ||
4794+ (src_h % 4) != 0)) {
4795+ DRM_DEBUG_KMS("NV12: src dimensions not met\n");
4796+ return -EINVAL;
4797+ }
4798+
47634799 /* range checks */
47644800 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4765− dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4766−
4767− src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4768− dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4801+ dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4802+ (IS_GEN11(dev_priv) &&
4803+ (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
4804+ dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
4805+ (!IS_GEN11(dev_priv) &&
4806+ (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4807+ dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
47694808 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
47704809 "size is out of scaler range\n",
47714810 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
@@ -4796,9 +4835,10 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state) · 24 unmodified lines
47964835 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
47974836
47984837 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4799− &state->scaler_state.scaler_id,
4800− state->pipe_src_w, state->pipe_src_h,
4801− adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4838+ &state->scaler_state.scaler_id,
4839+ state->pipe_src_w, state->pipe_src_h,
4840+ adjusted_mode->crtc_hdisplay,
4841+ adjusted_mode->crtc_vdisplay, false, 0);
48024842 }
48034843
48044844 /**
@@ -4827,7 +4867,8 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, · 22 unmodified lines
48274867 drm_rect_width(&plane_state->base.src) >> 16,
48284868 drm_rect_height(&plane_state->base.src) >> 16,
48294869 drm_rect_width(&plane_state->base.dst),
4830− drm_rect_height(&plane_state->base.dst));
4870+ drm_rect_height(&plane_state->base.dst),
4871+ fb ? true : false, fb ? fb->format->format : 0);
48314872
48324873 if (ret || plane_state->scaler_id < 0)
48334874 return ret;
@@ -4853,6 +4894,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, · 19 unmodified lines
48534894 case DRM_FORMAT_YVYU:
48544895 case DRM_FORMAT_UYVY:
48554896 case DRM_FORMAT_VYUY:
4897+ case DRM_FORMAT_NV12:
48564898 break;
48574899 default:
48584900 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -5099,13 +5141,15 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s · 240 unmodified lines
50995141 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
51005142 {
51015143 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5144+ struct drm_device *dev = crtc->base.dev;
5145+ struct drm_i915_private *dev_priv = to_i915(dev);
51025146 struct drm_atomic_state *old_state = old_crtc_state->base.state;
51035147 struct intel_crtc_state *pipe_config =
51045148 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
51055149 crtc);
51065150 struct drm_plane *primary = crtc->base.primary;
5107− struct drm_plane_state *old_pri_state =
5108− drm_atomic_get_existing_plane_state(old_state, primary);
5151+ struct drm_plane_state *old_primary_state =
5152+ drm_atomic_get_old_plane_state(old_state, primary);
51095153
51105154 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
51115155
@@ -5115,19 +5159,25 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) · 3 unmodified lines
51155159 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
51165160 hsw_enable_ips(pipe_config);
51175161
5118− if (old_pri_state) {
5119− struct intel_plane_state *primary_state =
5120− intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5121− to_intel_plane(primary));
5122− struct intel_plane_state *old_primary_state =
5123− to_intel_plane_state(old_pri_state);
5162+ if (old_primary_state) {
5163+ struct drm_plane_state *new_primary_state =
5164+ drm_atomic_get_new_plane_state(old_state, primary);
5165+ struct drm_framebuffer *fb = new_primary_state->fb;
51245166
51255167 intel_fbc_post_update(crtc);
51265168
5127− if (primary_state->base.visible &&
5169+ if (new_primary_state->visible &&
51285170 (needs_modeset(&pipe_config->base) ||
5129− !old_primary_state->base.visible))
5171+ !old_primary_state->visible))
51305172 intel_post_enable_primary(&crtc->base, pipe_config);
5173+
5174+ /* Display WA 827 */
5175+ if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
5176+ IS_CANNONLAKE(dev_priv)) {
5177+ if (fb && fb->format->format == DRM_FORMAT_NV12)
5178+ skl_wa_clkgate(dev_priv, crtc->pipe, false);
5179+ }
5180+
51315181 }
51325182 }
51335183
@@ -5139,8 +5189,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, · 5 unmodified lines
51395189 struct drm_i915_private *dev_priv = to_i915(dev);
51405190 struct drm_atomic_state *old_state = old_crtc_state->base.state;
51415191 struct drm_plane *primary = crtc->base.primary;
5142− struct drm_plane_state *old_pri_state =
5143− drm_atomic_get_existing_plane_state(old_state, primary);
5192+ struct drm_plane_state *old_primary_state =
5193+ drm_atomic_get_old_plane_state(old_state, primary);
51445194 bool modeset = needs_modeset(&pipe_config->base);
51455195 struct intel_atomic_state *old_intel_state =
51465196 to_intel_atomic_state(old_state);
@@ -5148,20 +5198,26 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, · 1 unmodified line
51485198 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
51495199 hsw_disable_ips(old_crtc_state);
51505200
5151− if (old_pri_state) {
5152− struct intel_plane_state *primary_state =
5201+ if (old_primary_state) {
5202+ struct intel_plane_state *new_primary_state =
51535203 intel_atomic_get_new_plane_state(old_intel_state,
51545204 to_intel_plane(primary));
5155− struct intel_plane_state *old_primary_state =
5156− to_intel_plane_state(old_pri_state);
5205+ struct drm_framebuffer *fb = new_primary_state->base.fb;
5206+
5207+ /* Display WA 827 */
5208+ if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
5209+ IS_CANNONLAKE(dev_priv)) {
5210+ if (fb && fb->format->format == DRM_FORMAT_NV12)
5211+ skl_wa_clkgate(dev_priv, crtc->pipe, true);
5212+ }
51575213
5158− intel_fbc_pre_update(crtc, pipe_config, primary_state);
5214+ intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
51595215 /*
51605216 * Gen2 reports pipe underruns whenever all planes are disabled.
51615217 * So disable underrun reporting before all the planes get disabled.
51625218 */
5163− if (IS_GEN2(dev_priv) && old_primary_state->base.visible &&
5164− (modeset || !primary_state->base.visible))
5219+ if (IS_GEN2(dev_priv) && old_primary_state->visible &&
5220+ (modeset || !new_primary_state->base.visible))
51655221 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
51665222 }
51675223
@@ -8766,8 +8822,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, · 3598 unmodified lines
87668822 intel_get_shared_dpll_by_id(dev_priv, pll_id);
87678823 pll = pipe_config->shared_dpll;
87688824
8769− WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8770− &pipe_config->dpll_hw_state));
8825+ WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
8826+ &pipe_config->dpll_hw_state));
87718827
87728828 tmp = pipe_config->dpll_hw_state.dpll;
87738829 pipe_config->pixel_multiplier =
@@ -9243,8 +9299,8 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, · 469 unmodified lines
92439299
92449300 pll = pipe_config->shared_dpll;
92459301 if (pll) {
9246− WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9247− &pipe_config->dpll_hw_state));
9302+ WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9303+ &pipe_config->dpll_hw_state));
92489304 }
92499305
92509306 /*
@@ -10775,7 +10831,7 @@ static bool check_digital_port_conflicts(struct drm_atomic_state *state) · 1524 unmodified lines
1077510831 struct drm_connector_state *connector_state;
1077610832 struct intel_encoder *encoder;
1077710833
10778− connector_state = drm_atomic_get_existing_connector_state(state, connector);
10834+ connector_state = drm_atomic_get_new_connector_state(state, connector);
1077910835 if (!connector_state)
1078010836 connector_state = connector->state;
1078110837
@@ -11645,11 +11701,11 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv, · 863 unmodified lines
1164511701
1164611702 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
1164711703
11648− DRM_DEBUG_KMS("%s\n", pll->name);
11704+ DRM_DEBUG_KMS("%s\n", pll->info->name);
1164911705
11650− active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11706+ active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
1165111707
11652− if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11708+ if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
1165311709 I915_STATE_WARN(!pll->on && pll->active_mask,
1165411710 "pll in active use but not on in sw tracking\n");
1165511711 I915_STATE_WARN(pll->on && !pll->active_mask,
@@ -12138,20 +12194,23 @@ static void intel_update_crtc(struct drm_crtc *crtc, · 482 unmodified lines
1213812194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1213912195 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
1214012196 bool modeset = needs_modeset(new_crtc_state);
12197+ struct intel_plane_state *new_plane_state =
12198+ intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
12199+ to_intel_plane(crtc->primary));
1214112200
1214212201 if (modeset) {
1214312202 update_scanline_offset(intel_crtc);
1214412203 dev_priv->display.crtc_enable(pipe_config, state);
12204+
12205+ /* vblanks work again, re-enable pipe CRC. */
12206+ intel_crtc_enable_pipe_crc(intel_crtc);
1214512207 } else {
1214612208 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
1214712209 pipe_config);
1214812210 }
1214912211
12150− if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12151− intel_fbc_enable(
12152− intel_crtc, pipe_config,
12153− to_intel_plane_state(crtc->primary->state));
12154− }
12212+ if (new_plane_state)
12213+ intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
1215512214
1215612215 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
1215712216 }
@@ -12322,6 +12381,13 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) · 164 unmodified lines
1232212381
1232312382 if (old_crtc_state->active) {
1232412383 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12384+
12385+ /*
12386+ * We need to disable pipe CRC before disabling the pipe,
12387+ * or we race against vblank off.
12388+ */
12389+ intel_crtc_disable_pipe_crc(intel_crtc);
12390+
1232512391 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
1232612392 intel_crtc->active = false;
1232712393 intel_fbc_disable(intel_crtc);
@@ -12725,8 +12791,8 @@ intel_prepare_plane_fb(struct drm_plane *plane, · 397 unmodified lines
1272512791
1272612792 if (old_obj) {
1272712793 struct drm_crtc_state *crtc_state =
12728− drm_atomic_get_existing_crtc_state(new_state->state,
12729− plane->state->crtc);
12794+ drm_atomic_get_new_crtc_state(new_state->state,
12795+ plane->state->crtc);
1273012796
1273112797 /* Big Hammer, we also need to ensure that any pending
1273212798 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
@@ -12780,6 +12846,8 @@ intel_prepare_plane_fb(struct drm_plane *plane, · 47 unmodified lines
1278012846 if (ret)
1278112847 return ret;
1278212848
12849+ intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
12850+
1278312851 if (!new_state->fence) { /* implicit fencing */
1278412852 struct dma_fence *fence;
1278512853
@@ -12824,11 +12892,13 @@ intel_cleanup_plane_fb(struct drm_plane *plane, · 38 unmodified lines
1282412892 }
1282512893
1282612894 int
12827−skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12895+skl_max_scale(struct intel_crtc *intel_crtc,
12896+ struct intel_crtc_state *crtc_state,
12897+ uint32_t pixel_format)
1282812898 {
1282912899 struct drm_i915_private *dev_priv;
12830− int max_scale;
12831− int crtc_clock, max_dotclk;
12900+ int max_scale, mult;
12901+ int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
1283212902
1283312903 if (!intel_crtc || !crtc_state->base.enable)
1283412904 return DRM_PLANE_HELPER_NO_SCALING;
@@ -12850,8 +12920,10 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state · 15 unmodified lines
1285012920 * or
1285112921 * cdclk/crtc_clock
1285212922 */
12853− max_scale = min((1 << 16) * 3 - 1,
12854− (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12923+ mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
12924+ tmpclk1 = (1 << 16) * mult - 1;
12925+ tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
12926+ max_scale = min(tmpclk1, tmpclk2);
1285512927
1285612928 return max_scale;
1285712929 }
@@ -12867,12 +12939,16 @@ intel_check_primary_plane(struct intel_plane *plane, · 9 unmodified lines
1286712939 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
1286812940 bool can_position = false;
1286912941 int ret;
12942+ uint32_t pixel_format = 0;
1287012943
1287112944 if (INTEL_GEN(dev_priv) >= 9) {
1287212945 /* use scaler when colorkey is not required */
1287312946 if (!state->ckey.flags) {
1287412947 min_scale = 1;
12875− max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12948+ if (state->base.fb)
12949+ pixel_format = state->base.fb->format->format;
12950+ max_scale = skl_max_scale(to_intel_crtc(crtc),
12951+ crtc_state, pixel_format);
1287612952 }
1287712953 can_position = true;
1287812954 }
@@ -12945,10 +13021,25 @@ out: · 66 unmodified lines
1294513021 intel_cstate);
1294613022 }
1294713023
13024+void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
13025+ struct intel_crtc_state *crtc_state)
13026+{
13027+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13028+
13029+ if (!IS_GEN2(dev_priv))
13030+ intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
13031+
13032+ if (crtc_state->has_pch_encoder) {
13033+ enum pipe pch_transcoder =
13034+ intel_crtc_pch_transcoder(crtc);
13035+
13036+ intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
13037+ }
13038+}
13039+
1294813040 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
1294913041 struct drm_crtc_state *old_crtc_state)
1295013042 {
12951− struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1295213043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1295313044 struct intel_atomic_state *old_intel_state =
1295413045 to_intel_atomic_state(old_crtc_state->state);
@@ -12959,17 +13050,8 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc, · 4 unmodified lines
1295913050
1296013051 if (new_crtc_state->update_pipe &&
1296113052 !needs_modeset(&new_crtc_state->base) &&
12962− old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED) {
12963− if (!IS_GEN2(dev_priv))
12964− intel_set_cpu_fifo_underrun_reporting(dev_priv, intel_crtc->pipe, true);
12965−
12966− if (new_crtc_state->has_pch_encoder) {
12967− enum pipe pch_transcoder =
12968− intel_crtc_pch_transcoder(intel_crtc);
12969−
12970− intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
12971− }
12972− }
13053+ old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED)
13054+ intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);
1297313055 }
1297413056
1297513057 /**
@@ -13167,8 +13249,9 @@ intel_legacy_cursor_update(struct drm_plane *plane, · 191 unmodified lines
1316713249 if (ret)
1316813250 goto out_unlock;
1316913251
13170− old_fb = old_plane_state->fb;
13252+ intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
1317113253
13254+ old_fb = old_plane_state->fb;
1317213255 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
1317313256 intel_plane->frontbuffer_bit);
1317413257
@@ -13555,10 +13638,17 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) · 380 unmodified lines
1355513638 /* initialize shared scalers */
1355613639 intel_crtc_init_scalers(intel_crtc, crtc_state);
1355713640
13558− BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13559− dev_priv->plane_to_crtc_mapping[primary->i9xx_plane] != NULL);
13560− dev_priv->plane_to_crtc_mapping[primary->i9xx_plane] = intel_crtc;
13561− dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13641+ BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
13642+ dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
13643+ dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
13644+
13645+ if (INTEL_GEN(dev_priv) < 9) {
13646+ enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
13647+
13648+ BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13649+ dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
13650+ dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
13651+ }
1356213652
1356313653 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
1356413654
@@ -15103,8 +15193,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) · 1538 unmodified lines
1510315193 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1510415194 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
1510515195
15106− pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15107− &pll->state.hw_state);
15196+ pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
15197+ &pll->state.hw_state);
1510815198 pll->state.crtc_mask = 0;
1510915199 for_each_intel_crtc(dev, crtc) {
1511015200 struct intel_crtc_state *crtc_state =
@@ -15117,7 +15207,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) · 6 unmodified lines
1511715207 pll->active_mask = pll->state.crtc_mask;
1511815208
1511915209 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15120− pll->name, pll->state.crtc_mask, pll->on);
15210+ pll->info->name, pll->state.crtc_mask, pll->on);
1512115211 }
1512215212
1512315213 for_each_intel_encoder(dev, encoder) {
@@ -15291,9 +15381,10 @@ intel_modeset_setup_hw_state(struct drm_device *dev, · 167 unmodified lines
1529115381 if (!pll->on || pll->active_mask)
1529215382 continue;
1529315383
15294− DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15384+ DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
15385+ pll->info->name);
1529515386
15296− pll->funcs.disable(dev_priv, pll);
15387+ pll->info->funcs->disable(dev_priv, pll);
1529715388 pll->on = false;
1529815389 }
1529915390
drivers/gpu/drm/i915/intel_dp.c+4−17
@@ -43,7 +43,6 @@ · 42 unmodified lines
4343 #include <drm/i915_drm.h>
4444 #include "i915_drv.h"
4545
46−#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
4746 #define DP_DPRX_ESI_LEN 14
4847
4948 /* Compliance test status bits */
@@ -92,8 +91,6 @@ static const struct dp_link_dpll chv_dpll[] = { · 42 unmodified lines
9291 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
9392 { 270000, /* m2_int = 27, m2_fraction = 0 */
9493 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
95− { 540000, /* m2_int = 27, m2_fraction = 0 */
96− { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
9794 };
9895
9996 /**
@@ -2901,10 +2898,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, · 2801 unmodified lines
29012898 }
29022899
29032900 } else {
2904− if (IS_CHERRYVIEW(dev_priv))
2905− *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2906− else
2907− *DP &= ~DP_LINK_TRAIN_MASK;
2901+ *DP &= ~DP_LINK_TRAIN_MASK;
29082902
29092903 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
29102904 case DP_TRAINING_PATTERN_DISABLE:
@@ -2917,12 +2911,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, · 6 unmodified lines
29172911 *DP |= DP_LINK_TRAIN_PAT_2;
29182912 break;
29192913 case DP_TRAINING_PATTERN_3:
2920− if (IS_CHERRYVIEW(dev_priv)) {
2921− *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2922− } else {
2923− DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2924− *DP |= DP_LINK_TRAIN_PAT_2;
2925− }
2914+ DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2915+ *DP |= DP_LINK_TRAIN_PAT_2;
29262916 break;
29272917 }
29282918 }
@@ -3661,10 +3651,7 @@ intel_dp_link_down(struct intel_encoder *encoder, · 732 unmodified lines
36613651 DP &= ~DP_LINK_TRAIN_MASK_CPT;
36623652 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
36633653 } else {
3664− if (IS_CHERRYVIEW(dev_priv))
3665− DP &= ~DP_LINK_TRAIN_MASK_CHV;
3666− else
3667− DP &= ~DP_LINK_TRAIN_MASK;
3654+ DP &= ~DP_LINK_TRAIN_MASK;
36683655 DP |= DP_LINK_TRAIN_PAT_IDLE;
36693656 }
36703657 I915_WRITE(intel_dp->output_reg, DP);
drivers/gpu/drm/i915/intel_dp_mst.c+7−1
@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, · 179 unmodified lines
180180 intel_dp->active_mst_links--;
181181
182182 intel_mst->connector = NULL;
183− if (intel_dp->active_mst_links == 0)
183+ if (intel_dp->active_mst_links == 0) {
184+ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
184185 intel_dig_port->base.post_disable(&intel_dig_port->base,
185186 old_crtc_state, NULL);
187+ }
186188
187189 DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
188190 }
@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, · 34 unmodified lines
223225
224226 DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
225227
228+ if (intel_dp->active_mst_links == 0)
229+ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
230+
226231 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
232+
227233 if (intel_dp->active_mst_links == 0)
228234 intel_dig_port->base.pre_enable(&intel_dig_port->base,
229235 pipe_config, NULL);
drivers/gpu/drm/i915/intel_dpio_phy.c+6−5
@@ -380,13 +380,14 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, · 379 unmodified lines
380380 * all 1s. Eventually they become accessible as they power up, then
381381 * the reserved bit will give the default 0. Poll on the reserved bit
382382 * becoming 0 to find when the PHY is accessible.
383− * HW team confirmed that the time to reach phypowergood status is
384− * anywhere between 50 us and 100us.
383+ * The flag should get set in 100us according to the HW team, but
384+ * use 1ms due to occasional timeouts observed with that.
385385 */
386− if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
387− (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
386+ if (intel_wait_for_register_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
387+ PHY_RESERVED | PHY_POWER_GOOD,
388+ PHY_POWER_GOOD,
389+ 1))
388390 DRM_ERROR("timeout during PHY%d power on\n", phy);
389− }
390391
391392 /* Program PLL Rcomp code offset */
392393 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
drivers/gpu/drm/i915/intel_dpll_mgr.c+132−121
@@ -118,10 +118,10 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv, · 117 unmodified lines
118118 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
119119 return;
120120
121− cur_state = pll->funcs.get_hw_state(dev_priv, pll, &hw_state);
121+ cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
122122 I915_STATE_WARN(cur_state != state,
123123 "%s assertion failure (expected %s, current %s)\n",
124− pll->name, onoff(state), onoff(cur_state));
124+ pll->info->name, onoff(state), onoff(cur_state));
125125 }
126126
127127 /**
@@ -143,11 +143,11 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc) · 15 unmodified lines
143143 mutex_lock(&dev_priv->dpll_lock);
144144 WARN_ON(!pll->state.crtc_mask);
145145 if (!pll->active_mask) {
146− DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
146+ DRM_DEBUG_DRIVER("setting up %s\n", pll->info->name);
147147 WARN_ON(pll->on);
148148 assert_shared_dpll_disabled(dev_priv, pll);
149149
150− pll->funcs.prepare(dev_priv, pll);
150+ pll->info->funcs->prepare(dev_priv, pll);
151151 }
152152 mutex_unlock(&dev_priv->dpll_lock);
153153 }
@@ -179,7 +179,7 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc) · 25 unmodified lines
179179 pll->active_mask |= crtc_mask;
180180
181181 DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
182− pll->name, pll->active_mask, pll->on,
182+ pll->info->name, pll->active_mask, pll->on,
183183 crtc->base.base.id);
184184
185185 if (old_mask) {
@@ -189,8 +189,8 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc) · 3 unmodified lines
189189 }
190190 WARN_ON(pll->on);
191191
192− DRM_DEBUG_KMS("enabling %s\n", pll->name);
193− pll->funcs.enable(dev_priv, pll);
192+ DRM_DEBUG_KMS("enabling %s\n", pll->info->name);
193+ pll->info->funcs->enable(dev_priv, pll);
194194 pll->on = true;
195195
196196 out:
@@ -221,7 +221,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc) · 24 unmodified lines
221221 goto out;
222222
223223 DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
224− pll->name, pll->active_mask, pll->on,
224+ pll->info->name, pll->active_mask, pll->on,
225225 crtc->base.base.id);
226226
227227 assert_shared_dpll_enabled(dev_priv, pll);
@@ -231,8 +231,8 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc) · 3 unmodified lines
231231 if (pll->active_mask)
232232 goto out;
233233
234− DRM_DEBUG_KMS("disabling %s\n", pll->name);
235− pll->funcs.disable(dev_priv, pll);
234+ DRM_DEBUG_KMS("disabling %s\n", pll->info->name);
235+ pll->info->funcs->disable(dev_priv, pll);
236236 pll->on = false;
237237
238238 out:
@@ -263,7 +263,8 @@ intel_find_shared_dpll(struct intel_crtc *crtc, · 24 unmodified lines
263263 &shared_dpll[i].hw_state,
264264 sizeof(crtc_state->dpll_hw_state)) == 0) {
265265 DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
266− crtc->base.base.id, crtc->base.name, pll->name,
266+ crtc->base.base.id, crtc->base.name,
267+ pll->info->name,
267268 shared_dpll[i].crtc_mask,
268269 pll->active_mask);
269270 return pll;
@@ -275,7 +276,8 @@ intel_find_shared_dpll(struct intel_crtc *crtc, · 5 unmodified lines
275276 pll = &dev_priv->shared_dplls[i];
276277 if (shared_dpll[i].crtc_mask == 0) {
277278 DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
278− crtc->base.base.id, crtc->base.name, pll->name);
279+ crtc->base.base.id, crtc->base.name,
280+ pll->info->name);
279281 return pll;
280282 }
281283 }
@@ -289,19 +291,19 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll, · 7 unmodified lines
289291 {
290292 struct intel_shared_dpll_state *shared_dpll;
291293 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
292− enum intel_dpll_id i = pll->id;
294+ const enum intel_dpll_id id = pll->info->id;
293295
294296 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
295297
296− if (shared_dpll[i].crtc_mask == 0)
297− shared_dpll[i].hw_state =
298+ if (shared_dpll[id].crtc_mask == 0)
299+ shared_dpll[id].hw_state =
298300 crtc_state->dpll_hw_state;
299301
300302 crtc_state->shared_dpll = pll;
301− DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
303+ DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
302304 pipe_name(crtc->pipe));
303305
304− shared_dpll[pll->id].crtc_mask |= 1 << crtc->pipe;
306+ shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
305307 }
306308
307309 /**
@@ -341,15 +343,16 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, · 33 unmodified lines
341343 struct intel_shared_dpll *pll,
342344 struct intel_dpll_hw_state *hw_state)
343345 {
346+ const enum intel_dpll_id id = pll->info->id;
344347 uint32_t val;
345348
346349 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
347350 return false;
348351
349− val = I915_READ(PCH_DPLL(pll->id));
352+ val = I915_READ(PCH_DPLL(id));
350353 hw_state->dpll = val;
351− hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
352− hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
354+ hw_state->fp0 = I915_READ(PCH_FP0(id));
355+ hw_state->fp1 = I915_READ(PCH_FP1(id));
353356
354357 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
355358
@@ -359,8 +362,10 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, · 3 unmodified lines
359362 static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,
360363 struct intel_shared_dpll *pll)
361364 {
362− I915_WRITE(PCH_FP0(pll->id), pll->state.hw_state.fp0);
363− I915_WRITE(PCH_FP1(pll->id), pll->state.hw_state.fp1);
365+ const enum intel_dpll_id id = pll->info->id;
366+
367+ I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0);
368+ I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1);
364369 }
365370
366371 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
@@ -379,13 +384,15 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) · 12 unmodified lines
379384 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
380385 struct intel_shared_dpll *pll)
381386 {
387+ const enum intel_dpll_id id = pll->info->id;
388+
382389 /* PCH refclock must be enabled first */
383390 ibx_assert_pch_refclk_enabled(dev_priv);
384391
385− I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
392+ I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
386393
387394 /* Wait for the clocks to stabilize. */
388− POSTING_READ(PCH_DPLL(pll->id));
395+ POSTING_READ(PCH_DPLL(id));
389396 udelay(150);
390397
391398 /* The pixel multiplier can only be updated once the
@@ -393,14 +400,15 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, · 1 unmodified line
393400 *
394401 * So write it again.
395402 */
396− I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
397− POSTING_READ(PCH_DPLL(pll->id));
403+ I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
404+ POSTING_READ(PCH_DPLL(id));
398405 udelay(200);
399406 }
400407
401408 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
402409 struct intel_shared_dpll *pll)
403410 {
411+ const enum intel_dpll_id id = pll->info->id;
404412 struct drm_device *dev = &dev_priv->drm;
405413 struct intel_crtc *crtc;
406414
@@ -410,8 +418,8 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, · 3 unmodified lines
410418 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
411419 }
412420
413− I915_WRITE(PCH_DPLL(pll->id), 0);
414− POSTING_READ(PCH_DPLL(pll->id));
421+ I915_WRITE(PCH_DPLL(id), 0);
422+ POSTING_READ(PCH_DPLL(id));
415423 udelay(200);
416424 }
417425
@@ -429,7 +437,8 @@ ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, · 11 unmodified lines
429437 pll = &dev_priv->shared_dplls[i];
430438
431439 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
432− crtc->base.base.id, crtc->base.name, pll->name);
440+ crtc->base.base.id, crtc->base.name,
441+ pll->info->name);
433442 } else {
434443 pll = intel_find_shared_dpll(crtc, crtc_state,
435444 DPLL_ID_PCH_PLL_A,
@@ -466,8 +475,10 @@ static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { · 30 unmodified lines
466475 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
467476 struct intel_shared_dpll *pll)
468477 {
469− I915_WRITE(WRPLL_CTL(pll->id), pll->state.hw_state.wrpll);
470− POSTING_READ(WRPLL_CTL(pll->id));
478+ const enum intel_dpll_id id = pll->info->id;
479+
480+ I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll);
481+ POSTING_READ(WRPLL_CTL(id));
471482 udelay(20);
472483 }
473484
@@ -482,11 +493,12 @@ static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, · 8 unmodified lines
482493 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
483494 struct intel_shared_dpll *pll)
484495 {
496+ const enum intel_dpll_id id = pll->info->id;
485497 uint32_t val;
486498
487− val = I915_READ(WRPLL_CTL(pll->id));
488− I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
489− POSTING_READ(WRPLL_CTL(pll->id));
499+ val = I915_READ(WRPLL_CTL(id));
500+ I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
501+ POSTING_READ(WRPLL_CTL(id));
490502 }
491503
492504 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
@@ -503,12 +515,13 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, · 10 unmodified lines
503515 struct intel_shared_dpll *pll,
504516 struct intel_dpll_hw_state *hw_state)
505517 {
518+ const enum intel_dpll_id id = pll->info->id;
506519 uint32_t val;
507520
508521 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
509522 return false;
510523
511− val = I915_READ(WRPLL_CTL(pll->id));
524+ val = I915_READ(WRPLL_CTL(id));
512525 hw_state->wrpll = val;
513526
514527 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
@@ -914,13 +927,15 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = { · 399 unmodified lines
914927 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
915928 struct intel_shared_dpll *pll)
916929 {
930+ const enum intel_dpll_id id = pll->info->id;
917931 uint32_t val;
918932
919933 val = I915_READ(DPLL_CTRL1);
920934
921− val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) |
922− DPLL_CTRL1_LINK_RATE_MASK(pll->id));
923− val |= pll->state.hw_state.ctrl1 << (pll->id * 6);
935+ val &= ~(DPLL_CTRL1_HDMI_MODE(id) |
936+ DPLL_CTRL1_SSC(id) |
937+ DPLL_CTRL1_LINK_RATE_MASK(id));
938+ val |= pll->state.hw_state.ctrl1 << (id * 6);
924939
925940 I915_WRITE(DPLL_CTRL1, val);
926941 POSTING_READ(DPLL_CTRL1);
@@ -930,24 +945,25 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, · 3 unmodified lines
930945 struct intel_shared_dpll *pll)
931946 {
932947 const struct skl_dpll_regs *regs = skl_dpll_regs;
948+ const enum intel_dpll_id id = pll->info->id;
933949
934950 skl_ddi_pll_write_ctrl1(dev_priv, pll);
935951
936− I915_WRITE(regs[pll->id].cfgcr1, pll->state.hw_state.cfgcr1);
937− I915_WRITE(regs[pll->id].cfgcr2, pll->state.hw_state.cfgcr2);
938− POSTING_READ(regs[pll->id].cfgcr1);
939− POSTING_READ(regs[pll->id].cfgcr2);
952+ I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
953+ I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
954+ POSTING_READ(regs[id].cfgcr1);
955+ POSTING_READ(regs[id].cfgcr2);
940956
941957 /* the enable bit is always bit 31 */
942− I915_WRITE(regs[pll->id].ctl,
943− I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
958+ I915_WRITE(regs[id].ctl,
959+ I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
944960
945961 if (intel_wait_for_register(dev_priv,
946962 DPLL_STATUS,
947− DPLL_LOCK(pll->id),
948− DPLL_LOCK(pll->id),
963+ DPLL_LOCK(id),
964+ DPLL_LOCK(id),
949965 5))
950− DRM_ERROR("DPLL %d not locked\n", pll->id);
966+ DRM_ERROR("DPLL %d not locked\n", id);
951967 }
952968
953969 static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
@@ -960,11 +976,12 @@ static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, · 6 unmodified lines
960976 struct intel_shared_dpll *pll)
961977 {
962978 const struct skl_dpll_regs *regs = skl_dpll_regs;
979+ const enum intel_dpll_id id = pll->info->id;
963980
964981 /* the enable bit is always bit 31 */
965− I915_WRITE(regs[pll->id].ctl,
966− I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
967− POSTING_READ(regs[pll->id].ctl);
982+ I915_WRITE(regs[id].ctl,
983+ I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE);
984+ POSTING_READ(regs[id].ctl);
968985 }
969986
970987 static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
@@ -978,6 +995,7 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, · 7 unmodified lines
978995 {
979996 uint32_t val;
980997 const struct skl_dpll_regs *regs = skl_dpll_regs;
998+ const enum intel_dpll_id id = pll->info->id;
981999 bool ret;
9821000
9831001 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
@@ -985,17 +1003,17 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, · 1 unmodified line
9851003
9861004 ret = false;
9871005
988− val = I915_READ(regs[pll->id].ctl);
1006+ val = I915_READ(regs[id].ctl);
9891007 if (!(val & LCPLL_PLL_ENABLE))
9901008 goto out;
9911009
9921010 val = I915_READ(DPLL_CTRL1);
993− hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
1011+ hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
9941012
9951013 /* avoid reading back stale values if HDMI mode is not enabled */
996− if (val & DPLL_CTRL1_HDMI_MODE(pll->id)) {
997− hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
998− hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
1014+ if (val & DPLL_CTRL1_HDMI_MODE(id)) {
1015+ hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);
1016+ hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);
9991017 }
10001018 ret = true;
10011019
@@ -1011,6 +1029,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, · 9 unmodified lines
10111029 {
10121030 uint32_t val;
10131031 const struct skl_dpll_regs *regs = skl_dpll_regs;
1032+ const enum intel_dpll_id id = pll->info->id;
10141033 bool ret;
10151034
10161035 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
@@ -1019,12 +1038,12 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, · 2 unmodified lines
10191038 ret = false;
10201039
10211040 /* DPLL0 is always enabled since it drives CDCLK */
1022− val = I915_READ(regs[pll->id].ctl);
1041+ val = I915_READ(regs[id].ctl);
10231042 if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
10241043 goto out;
10251044
10261045 val = I915_READ(DPLL_CTRL1);
1027− hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
1046+ hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
10281047
10291048 ret = true;
10301049
@@ -1424,7 +1443,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, · 393 unmodified lines
14241443 struct intel_shared_dpll *pll)
14251444 {
14261445 uint32_t temp;
1427− enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1446+ enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
14281447 enum dpio_phy phy;
14291448 enum dpio_channel ch;
14301449
@@ -1543,7 +1562,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, · 112 unmodified lines
15431562 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
15441563 struct intel_shared_dpll *pll)
15451564 {
1546− enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1565+ enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
15471566 uint32_t temp;
15481567
15491568 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
@@ -1566,7 +1585,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, · 16 unmodified lines
15661585 struct intel_shared_dpll *pll,
15671586 struct intel_dpll_hw_state *hw_state)
15681587 {
1569− enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1588+ enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
15701589 uint32_t val;
15711590 bool ret;
15721591 enum dpio_phy phy;
@@ -1824,7 +1843,7 @@ bxt_get_dpll(struct intel_crtc *crtc, · 251 unmodified lines
18241843 pll = intel_get_shared_dpll_by_id(dev_priv, i);
18251844
18261845 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
1827− crtc->base.base.id, crtc->base.name, pll->name);
1846+ crtc->base.base.id, crtc->base.name, pll->info->name);
18281847
18291848 intel_reference_shared_dpll(pll, crtc_state);
18301849
@@ -1877,13 +1896,6 @@ static void intel_ddi_pll_init(struct drm_device *dev) · 46 unmodified lines
18771896 }
18781897 }
18791898
1880−struct dpll_info {
1881− const char *name;
1882− const int id;
1883− const struct intel_shared_dpll_funcs *funcs;
1884− uint32_t flags;
1885−};
1886−
18871899 struct intel_dpll_mgr {
18881900 const struct dpll_info *dpll_info;
18891901
@@ -1896,9 +1908,9 @@ struct intel_dpll_mgr { · 6 unmodified lines
18961908 };
18971909
18981910 static const struct dpll_info pch_plls[] = {
1899− { "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 },
1900− { "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 },
1901− { NULL, -1, NULL, 0 },
1911+ { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
1912+ { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
1913+ { },
19021914 };
19031915
19041916 static const struct intel_dpll_mgr pch_pll_mgr = {
@@ -1908,13 +1920,13 @@ static const struct intel_dpll_mgr pch_pll_mgr = { · 3 unmodified lines
19081920 };
19091921
19101922 static const struct dpll_info hsw_plls[] = {
1911− { "WRPLL 1", DPLL_ID_WRPLL1, &hsw_ddi_wrpll_funcs, 0 },
1912− { "WRPLL 2", DPLL_ID_WRPLL2, &hsw_ddi_wrpll_funcs, 0 },
1913− { "SPLL", DPLL_ID_SPLL, &hsw_ddi_spll_funcs, 0 },
1914− { "LCPLL 810", DPLL_ID_LCPLL_810, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1915− { "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1916− { "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1917− { NULL, -1, NULL, },
1923+ { "WRPLL 1", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 },
1924+ { "WRPLL 2", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 },
1925+ { "SPLL", &hsw_ddi_spll_funcs, DPLL_ID_SPLL, 0 },
1926+ { "LCPLL 810", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810, INTEL_DPLL_ALWAYS_ON },
1927+ { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
1928+ { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
1929+ { },
19181930 };
19191931
19201932 static const struct intel_dpll_mgr hsw_pll_mgr = {
@@ -1924,11 +1936,11 @@ static const struct intel_dpll_mgr hsw_pll_mgr = { · 3 unmodified lines
19241936 };
19251937
19261938 static const struct dpll_info skl_plls[] = {
1927− { "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON },
1928− { "DPLL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs, 0 },
1929− { "DPLL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs, 0 },
1930− { "DPLL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs, 0 },
1931− { NULL, -1, NULL, },
1939+ { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
1940+ { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1941+ { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1942+ { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 },
1943+ { },
19321944 };
19331945
19341946 static const struct intel_dpll_mgr skl_pll_mgr = {
@@ -1938,10 +1950,10 @@ static const struct intel_dpll_mgr skl_pll_mgr = { · 3 unmodified lines
19381950 };
19391951
19401952 static const struct dpll_info bxt_plls[] = {
1941− { "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 },
1942− { "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 },
1943− { "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 },
1944− { NULL, -1, NULL, },
1953+ { "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
1954+ { "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1955+ { "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1956+ { },
19451957 };
19461958
19471959 static const struct intel_dpll_mgr bxt_pll_mgr = {
@@ -1953,38 +1965,39 @@ static const struct intel_dpll_mgr bxt_pll_mgr = { · 5 unmodified lines
19531965 static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
19541966 struct intel_shared_dpll *pll)
19551967 {
1968+ const enum intel_dpll_id id = pll->info->id;
19561969 uint32_t val;
19571970
19581971 /* 1. Enable DPLL power in DPLL_ENABLE. */
1959− val = I915_READ(CNL_DPLL_ENABLE(pll->id));
1972+ val = I915_READ(CNL_DPLL_ENABLE(id));
19601973 val |= PLL_POWER_ENABLE;
1961− I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
1974+ I915_WRITE(CNL_DPLL_ENABLE(id), val);
19621975
19631976 /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
19641977 if (intel_wait_for_register(dev_priv,
1965− CNL_DPLL_ENABLE(pll->id),
1978+ CNL_DPLL_ENABLE(id),
19661979 PLL_POWER_STATE,
19671980 PLL_POWER_STATE,
19681981 5))
1969− DRM_ERROR("PLL %d Power not enabled\n", pll->id);
1982+ DRM_ERROR("PLL %d Power not enabled\n", id);
19701983
19711984 /*
19721985 * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
19731986 * select DP mode, and set DP link rate.
19741987 */
19751988 val = pll->state.hw_state.cfgcr0;
1976− I915_WRITE(CNL_DPLL_CFGCR0(pll->id), val);
1989+ I915_WRITE(CNL_DPLL_CFGCR0(id), val);
19771990
19781991 /* 4. Reab back to ensure writes completed */
1979− POSTING_READ(CNL_DPLL_CFGCR0(pll->id));
1992+ POSTING_READ(CNL_DPLL_CFGCR0(id));
19801993
19811994 /* 3. Configure DPLL_CFGCR0 */
19821995 /* Avoid touch CFGCR1 if HDMI mode is not enabled */
19831996 if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
19841997 val = pll->state.hw_state.cfgcr1;
1985− I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
1998+ I915_WRITE(CNL_DPLL_CFGCR1(id), val);
19861999 /* 4. Reab back to ensure writes completed */
1987− POSTING_READ(CNL_DPLL_CFGCR1(pll->id));
2000+ POSTING_READ(CNL_DPLL_CFGCR1(id));
19882001 }
19892002
19902003 /*
@@ -1997,17 +2010,17 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv, · 6 unmodified lines
19972010 */
19982011
19992012 /* 6. Enable DPLL in DPLL_ENABLE. */
2000− val = I915_READ(CNL_DPLL_ENABLE(pll->id));
2013+ val = I915_READ(CNL_DPLL_ENABLE(id));
20012014 val |= PLL_ENABLE;
2002− I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
2015+ I915_WRITE(CNL_DPLL_ENABLE(id), val);
20032016
20042017 /* 7. Wait for PLL lock status in DPLL_ENABLE. */
20052018 if (intel_wait_for_register(dev_priv,
2006− CNL_DPLL_ENABLE(pll->id),
2019+ CNL_DPLL_ENABLE(id),
20072020 PLL_LOCK,
20082021 PLL_LOCK,
20092022 5))
2010− DRM_ERROR("PLL %d not locked\n", pll->id);
2023+ DRM_ERROR("PLL %d not locked\n", id);
20112024
20122025 /*
20132026 * 8. If the frequency will result in a change to the voltage
@@ -2027,6 +2040,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv, · 13 unmodified lines
20272040 static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
20282041 struct intel_shared_dpll *pll)
20292042 {
2043+ const enum intel_dpll_id id = pll->info->id;
20302044 uint32_t val;
20312045
20322046 /*
@@ -2044,17 +2058,17 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv, · 11 unmodified lines
20442058 */
20452059
20462060 /* 3. Disable DPLL through DPLL_ENABLE. */
2047− val = I915_READ(CNL_DPLL_ENABLE(pll->id));
2061+ val = I915_READ(CNL_DPLL_ENABLE(id));
20482062 val &= ~PLL_ENABLE;
2049− I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
2063+ I915_WRITE(CNL_DPLL_ENABLE(id), val);
20502064
20512065 /* 4. Wait for PLL not locked status in DPLL_ENABLE. */
20522066 if (intel_wait_for_register(dev_priv,
2053− CNL_DPLL_ENABLE(pll->id),
2067+ CNL_DPLL_ENABLE(id),
20542068 PLL_LOCK,
20552069 0,
20562070 5))
2057− DRM_ERROR("PLL %d locked\n", pll->id);
2071+ DRM_ERROR("PLL %d locked\n", id);
20582072
20592073 /*
20602074 * 5. If the frequency will result in a change to the voltage
@@ -2066,23 +2080,24 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv, · 5 unmodified lines
20662080 */
20672081
20682082 /* 6. Disable DPLL power in DPLL_ENABLE. */
2069− val = I915_READ(CNL_DPLL_ENABLE(pll->id));
2083+ val = I915_READ(CNL_DPLL_ENABLE(id));
20702084 val &= ~PLL_POWER_ENABLE;
2071− I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
2085+ I915_WRITE(CNL_DPLL_ENABLE(id), val);
20722086
20732087 /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
20742088 if (intel_wait_for_register(dev_priv,
2075− CNL_DPLL_ENABLE(pll->id),
2089+ CNL_DPLL_ENABLE(id),
20762090 PLL_POWER_STATE,
20772091 0,
20782092 5))
2079− DRM_ERROR("PLL %d Power not disabled\n", pll->id);
2093+ DRM_ERROR("PLL %d Power not disabled\n", id);
20802094 }
20812095
20822096 static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
20832097 struct intel_shared_dpll *pll,
20842098 struct intel_dpll_hw_state *hw_state)
20852099 {
2100+ const enum intel_dpll_id id = pll->info->id;
20862101 uint32_t val;
20872102 bool ret;
20882103
@@ -2091,16 +2106,16 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, · 2 unmodified lines
20912106
20922107 ret = false;
20932108
2094− val = I915_READ(CNL_DPLL_ENABLE(pll->id));
2109+ val = I915_READ(CNL_DPLL_ENABLE(id));
20952110 if (!(val & PLL_ENABLE))
20962111 goto out;
20972112
2098− val = I915_READ(CNL_DPLL_CFGCR0(pll->id));
2113+ val = I915_READ(CNL_DPLL_CFGCR0(id));
20992114 hw_state->cfgcr0 = val;
21002115
21012116 /* avoid reading back stale values if HDMI mode is not enabled */
21022117 if (val & DPLL_CFGCR0_HDMI_MODE) {
2103− hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll->id));
2118+ hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));
21042119 }
21052120 ret = true;
21062121
@@ -2372,10 +2387,10 @@ static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = { · 265 unmodified lines
23722387 };
23732388
23742389 static const struct dpll_info cnl_plls[] = {
2375− { "DPLL 0", DPLL_ID_SKL_DPLL0, &cnl_ddi_pll_funcs, 0 },
2376− { "DPLL 1", DPLL_ID_SKL_DPLL1, &cnl_ddi_pll_funcs, 0 },
2377− { "DPLL 2", DPLL_ID_SKL_DPLL2, &cnl_ddi_pll_funcs, 0 },
2378− { NULL, -1, NULL, },
2390+ { "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
2391+ { "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
2392+ { "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
2393+ { },
23792394 };
23802395
23812396 static const struct intel_dpll_mgr cnl_pll_mgr = {
@@ -2415,13 +2430,9 @@ void intel_shared_dpll_init(struct drm_device *dev) · 33 unmodified lines
24152430
24162431 dpll_info = dpll_mgr->dpll_info;
24172432
2418− for (i = 0; dpll_info[i].id >= 0; i++) {
2433+ for (i = 0; dpll_info[i].name; i++) {
24192434 WARN_ON(i != dpll_info[i].id);
2420−
2421− dev_priv->shared_dplls[i].id = dpll_info[i].id;
2422− dev_priv->shared_dplls[i].name = dpll_info[i].name;
2423− dev_priv->shared_dplls[i].funcs = *dpll_info[i].funcs;
2424− dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
2435+ dev_priv->shared_dplls[i].info = &dpll_info[i];
24252436 }
24262437
24272438 dev_priv->dpll_mgr = dpll_mgr;
@@ -2481,7 +2492,7 @@ void intel_release_shared_dpll(struct intel_shared_dpll *dpll, · 53 unmodified lines
24812492 struct intel_shared_dpll_state *shared_dpll_state;
24822493
24832494 shared_dpll_state = intel_atomic_get_shared_dpll_state(state);
2484− shared_dpll_state[dpll->id].crtc_mask &= ~(1 << crtc->pipe);
2495+ shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);
24852496 }
24862497
24872498 /**
drivers/gpu/drm/i915/intel_dpll_mgr.h+33−23
@@ -205,6 +205,37 @@ struct intel_shared_dpll_funcs { · 204 unmodified lines
205205 struct intel_dpll_hw_state *hw_state);
206206 };
207207
208+/**
209+ * struct dpll_info - display PLL platform specific info
210+ */
211+struct dpll_info {
212+ /**
213+ * @name: DPLL name; used for logging
214+ */
215+ const char *name;
216+
217+ /**
218+ * @funcs: platform specific hooks
219+ */
220+ const struct intel_shared_dpll_funcs *funcs;
221+
222+ /**
223+ * @id: unique indentifier for this DPLL; should match the index in the
224+ * dev_priv->shared_dplls array
225+ */
226+ enum intel_dpll_id id;
227+
228+#define INTEL_DPLL_ALWAYS_ON (1 << 0)
229+ /**
230+ * @flags:
231+ *
232+ * INTEL_DPLL_ALWAYS_ON
233+ * Inform the state checker that the DPLL is kept enabled even if
234+ * not in use by any CRTC.
235+ */
236+ uint32_t flags;
237+};
238+
208239 /**
209240 * struct intel_shared_dpll - display PLL with tracked state and users
210241 */
@@ -228,30 +259,9 @@ struct intel_shared_dpll { · 17 unmodified lines
228259 bool on;
229260
230261 /**
231− * @name: DPLL name; used for logging
262+ * @info: platform specific info
232263 */
233− const char *name;
234−
235− /**
236− * @id: unique indentifier for this DPLL; should match the index in the
237− * dev_priv->shared_dplls array
238− */
239− enum intel_dpll_id id;
240−
241− /**
242− * @funcs: platform specific hooks
243− */
244− struct intel_shared_dpll_funcs funcs;
245−
246−#define INTEL_DPLL_ALWAYS_ON (1 << 0)
247− /**
248− * @flags:
249− *
250− * INTEL_DPLL_ALWAYS_ON
251− * Inform the state checker that the DPLL is kept enabled even if
252− * not in use by any CRTC.
253− */
254− uint32_t flags;
264+ const struct dpll_info *info;
255265 };
256266
257267 #define SKL_DPLL0 0
drivers/gpu/drm/i915/intel_drv.h+29−29
@@ -482,7 +482,7 @@ struct intel_atomic_state { · 481 unmodified lines
482482 bool skip_intermediate_wm;
483483
484484 /* Gen9+ only */
485− struct skl_wm_values wm_results;
485+ struct skl_ddb_values wm_results;
486486
487487 struct i915_sw_fence commit_ready;
488488
@@ -548,6 +548,12 @@ struct intel_initial_plane_config { · 59 unmodified lines
548548 #define SKL_MAX_DST_W 4096
549549 #define SKL_MIN_DST_H 8
550550 #define SKL_MAX_DST_H 4096
551+#define ICL_MAX_SRC_W 5120
552+#define ICL_MAX_SRC_H 4096
553+#define ICL_MAX_DST_W 5120
554+#define ICL_MAX_DST_H 4096
555+#define SKL_MIN_YUV_420_SRC_W 16
556+#define SKL_MIN_YUV_420_SRC_H 16
551557
552558 struct intel_scaler {
553559 int in_use;
@@ -598,7 +604,9 @@ struct intel_pipe_wm { · 44 unmodified lines
598604
599605 struct skl_plane_wm {
600606 struct skl_wm_level wm[8];
607+ struct skl_wm_level uv_wm[8];
601608 struct skl_wm_level trans_wm;
609+ bool is_planar;
602610 };
603611
604612 struct skl_pipe_wm {
@@ -1325,6 +1333,7 @@ void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); · 720 unmodified lines
13251333 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
13261334 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
13271335 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1336+void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
13281337 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
13291338 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
13301339 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
@@ -1588,9 +1597,12 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state); · 257 unmodified lines
15881597 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
15891598 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
15901599 struct intel_crtc_state *pipe_config);
1600+void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1601+ struct intel_crtc_state *crtc_state);
15911602
15921603 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1593−int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1604+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1605+ uint32_t pixel_format);
15941606
15951607 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
15961608 {
@@ -1607,6 +1619,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, · 10 unmodified lines
16071619 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
16081620 struct intel_plane_state *plane_state);
16091621 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1622+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
16101623
16111624 /* intel_csr.c */
16121625 void intel_csr_ucode_init(struct drm_i915_private *);
@@ -1773,6 +1786,7 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, · 160 unmodified lines
17731786 unsigned int frontbuffer_bits, enum fb_op_origin origin);
17741787 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
17751788 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1789+int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
17761790
17771791 /* intel_hdmi.c */
17781792 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
@@ -1783,7 +1797,7 @@ struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); · 4 unmodified lines
17831797 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
17841798 struct intel_crtc_state *pipe_config,
17851799 struct drm_connector_state *conn_state);
1786−void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1800+bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
17871801 struct drm_connector *connector,
17881802 bool high_tmds_clock_ratio,
17891803 bool scrambling);
@@ -1877,7 +1891,8 @@ void intel_psr_enable(struct intel_dp *intel_dp, · 87 unmodified lines
18771891 void intel_psr_disable(struct intel_dp *intel_dp,
18781892 const struct intel_crtc_state *old_crtc_state);
18791893 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1880− unsigned frontbuffer_bits);
1894+ unsigned frontbuffer_bits,
1895+ enum fb_op_origin origin);
18811896 void intel_psr_flush(struct drm_i915_private *dev_priv,
18821897 unsigned frontbuffer_bits,
18831898 enum fb_op_origin origin);
@@ -2046,6 +2061,7 @@ void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc); · 162 unmodified lines
20462061 bool skl_plane_get_hw_state(struct intel_plane *plane);
20472062 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
20482063 enum pipe pipe, enum plane_id plane_id);
2064+bool intel_format_is_yuv(uint32_t format);
20492065
20502066 /* intel_tv.c */
20512067 void intel_tv_init(struct drm_i915_private *dev_priv);
@@ -2082,31 +2098,6 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state, · 30 unmodified lines
20822098 return to_intel_crtc_state(crtc_state);
20832099 }
20842100
2085−static inline struct intel_crtc_state *
2086−intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
2087− struct intel_crtc *crtc)
2088−{
2089− struct drm_crtc_state *crtc_state;
2090−
2091− crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
2092−
2093− if (crtc_state)
2094− return to_intel_crtc_state(crtc_state);
2095− else
2096− return NULL;
2097−}
2098−
2099−static inline struct intel_plane_state *
2100−intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
2101− struct intel_plane *plane)
2102−{
2103− struct drm_plane_state *plane_state;
2104−
2105− plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
2106−
2107− return to_intel_plane_state(plane_state);
2108−}
2109−
21102101 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
21112102 struct intel_crtc *intel_crtc,
21122103 struct intel_crtc_state *crtc_state);
@@ -2138,8 +2129,17 @@ int intel_pipe_crc_create(struct drm_minor *minor); · 25 unmodified lines
21382129 #ifdef CONFIG_DEBUG_FS
21392130 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
21402131 size_t *values_cnt);
2132+void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2133+void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
21412134 #else
21422135 #define intel_crtc_set_crc_source NULL
2136+static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2137+{
2138+}
2139+
2140+static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2141+{
2142+}
21432143 #endif
21442144 extern const struct file_operations i915_display_crc_ctl_fops;
21452145 #endif /* __INTEL_DRV_H__ */
drivers/gpu/drm/i915/intel_engine_cs.c+105−691
@@ -81,13 +81,17 @@ static const struct engine_class_info intel_engine_classes[] = { · 80 unmodified lines
8181 },
8282 };
8383
84+#define MAX_MMIO_BASES 3
8485 struct engine_info {
8586 unsigned int hw_id;
8687 unsigned int uabi_id;
8788 u8 class;
8889 u8 instance;
89− u32 mmio_base;
90− unsigned irq_shift;
90+ /* mmio bases table *must* be sorted in reverse gen order */
91+ struct engine_mmio_base {
92+ u32 gen : 8;
93+ u32 base : 24;
94+ } mmio_bases[MAX_MMIO_BASES];
9195 };
9296
9397 static const struct engine_info intel_engines[] = {
@@ -96,64 +100,76 @@ static const struct engine_info intel_engines[] = { · 2 unmodified lines
96100 .uabi_id = I915_EXEC_RENDER,
97101 .class = RENDER_CLASS,
98102 .instance = 0,
99− .mmio_base = RENDER_RING_BASE,
100− .irq_shift = GEN8_RCS_IRQ_SHIFT,
103+ .mmio_bases = {
104+ { .gen = 1, .base = RENDER_RING_BASE }
105+ },
101106 },
102107 [BCS] = {
103108 .hw_id = BCS_HW,
104109 .uabi_id = I915_EXEC_BLT,
105110 .class = COPY_ENGINE_CLASS,
106111 .instance = 0,
107− .mmio_base = BLT_RING_BASE,
108− .irq_shift = GEN8_BCS_IRQ_SHIFT,
112+ .mmio_bases = {
113+ { .gen = 6, .base = BLT_RING_BASE }
114+ },
109115 },
110116 [VCS] = {
111117 .hw_id = VCS_HW,
112118 .uabi_id = I915_EXEC_BSD,
113119 .class = VIDEO_DECODE_CLASS,
114120 .instance = 0,
115− .mmio_base = GEN6_BSD_RING_BASE,
116− .irq_shift = GEN8_VCS1_IRQ_SHIFT,
121+ .mmio_bases = {
122+ { .gen = 11, .base = GEN11_BSD_RING_BASE },
123+ { .gen = 6, .base = GEN6_BSD_RING_BASE },
124+ { .gen = 4, .base = BSD_RING_BASE }
125+ },
117126 },
118127 [VCS2] = {
119128 .hw_id = VCS2_HW,
120129 .uabi_id = I915_EXEC_BSD,
121130 .class = VIDEO_DECODE_CLASS,
122131 .instance = 1,
123− .mmio_base = GEN8_BSD2_RING_BASE,
124− .irq_shift = GEN8_VCS2_IRQ_SHIFT,
132+ .mmio_bases = {
133+ { .gen = 11, .base = GEN11_BSD2_RING_BASE },
134+ { .gen = 8, .base = GEN8_BSD2_RING_BASE }
135+ },
125136 },
126137 [VCS3] = {
127138 .hw_id = VCS3_HW,
128139 .uabi_id = I915_EXEC_BSD,
129140 .class = VIDEO_DECODE_CLASS,
130141 .instance = 2,
131− .mmio_base = GEN11_BSD3_RING_BASE,
132− .irq_shift = 0, /* not used */
142+ .mmio_bases = {
143+ { .gen = 11, .base = GEN11_BSD3_RING_BASE }
144+ },
133145 },
134146 [VCS4] = {
135147 .hw_id = VCS4_HW,
136148 .uabi_id = I915_EXEC_BSD,
137149 .class = VIDEO_DECODE_CLASS,
138150 .instance = 3,
139− .mmio_base = GEN11_BSD4_RING_BASE,
140− .irq_shift = 0, /* not used */
151+ .mmio_bases = {
152+ { .gen = 11, .base = GEN11_BSD4_RING_BASE }
153+ },
141154 },
142155 [VECS] = {
143156 .hw_id = VECS_HW,
144157 .uabi_id = I915_EXEC_VEBOX,
145158 .class = VIDEO_ENHANCEMENT_CLASS,
146159 .instance = 0,
147− .mmio_base = VEBOX_RING_BASE,
148− .irq_shift = GEN8_VECS_IRQ_SHIFT,
160+ .mmio_bases = {
161+ { .gen = 11, .base = GEN11_VEBOX_RING_BASE },
162+ { .gen = 7, .base = VEBOX_RING_BASE }
163+ },
149164 },
150165 [VECS2] = {
151166 .hw_id = VECS2_HW,
152167 .uabi_id = I915_EXEC_VEBOX,
153168 .class = VIDEO_ENHANCEMENT_CLASS,
154169 .instance = 1,
155− .mmio_base = GEN11_VEBOX2_RING_BASE,
156− .irq_shift = 0, /* not used */
170+ .mmio_bases = {
171+ { .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
172+ },
157173 },
158174 };
159175
@@ -223,16 +239,36 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class) · 63 unmodified lines
223239 }
224240 }
225241
242+static u32 __engine_mmio_base(struct drm_i915_private *i915,
243+ const struct engine_mmio_base *bases)
244+{
245+ int i;
246+
247+ for (i = 0; i < MAX_MMIO_BASES; i++)
248+ if (INTEL_GEN(i915) >= bases[i].gen)
249+ break;
250+
251+ GEM_BUG_ON(i == MAX_MMIO_BASES);
252+ GEM_BUG_ON(!bases[i].base);
253+
254+ return bases[i].base;
255+}
256+
257+static void __sprint_engine_name(char *name, const struct engine_info *info)
258+{
259+ WARN_ON(snprintf(name, INTEL_ENGINE_CS_MAX_NAME, "%s%u",
260+ intel_engine_classes[info->class].name,
261+ info->instance) >= INTEL_ENGINE_CS_MAX_NAME);
262+}
263+
226264 static int
227265 intel_engine_setup(struct drm_i915_private *dev_priv,
228266 enum intel_engine_id id)
229267 {
230268 const struct engine_info *info = &intel_engines[id];
231− const struct engine_class_info *class_info;
232269 struct intel_engine_cs *engine;
233270
234271 GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes));
235− class_info = &intel_engine_classes[info->class];
236272
237273 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
238274 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
@@ -253,35 +289,14 @@ intel_engine_setup(struct drm_i915_private *dev_priv, · 14 unmodified lines
253289
254290 engine->id = id;
255291 engine->i915 = dev_priv;
256− WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s%u",
257− class_info->name, info->instance) >=
258− sizeof(engine->name));
292+ __sprint_engine_name(engine->name, info);
259293 engine->hw_id = engine->guc_id = info->hw_id;
260− if (INTEL_GEN(dev_priv) >= 11) {
261− switch (engine->id) {
262− case VCS:
263− engine->mmio_base = GEN11_BSD_RING_BASE;
264− break;
265− case VCS2:
266− engine->mmio_base = GEN11_BSD2_RING_BASE;
267− break;
268− case VECS:
269− engine->mmio_base = GEN11_VEBOX_RING_BASE;
270− break;
271− default:
272− /* take the original value for all other engines */
273− engine->mmio_base = info->mmio_base;
274− break;
275− }
276− } else {
277− engine->mmio_base = info->mmio_base;
278− }
279− engine->irq_shift = info->irq_shift;
294+ engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases);
280295 engine->class = info->class;
281296 engine->instance = info->instance;
282297
283298 engine->uabi_id = info->uabi_id;
284− engine->uabi_class = class_info->uabi_class;
299+ engine->uabi_class = intel_engine_classes[info->class].uabi_class;
285300
286301 engine->context_size = __intel_engine_context_size(dev_priv,
287302 engine->class);
@@ -441,6 +456,11 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine) · 153 unmodified lines
441456 engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
442457 }
443458
459+static void intel_engine_init_batch_pool(struct intel_engine_cs *engine)
460+{
461+ i915_gem_batch_pool_init(&engine->batch_pool, engine);
462+}
463+
444464 static bool csb_force_mmio(struct drm_i915_private *i915)
445465 {
446466 /*
@@ -455,6 +475,9 @@ static bool csb_force_mmio(struct drm_i915_private *i915) · 8 unmodified lines
455475 if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
456476 return true;
457477
478+ if (IS_CANNONLAKE(i915))
479+ return true;
480+
458481 return false;
459482 }
460483
@@ -485,11 +508,9 @@ static void intel_engine_init_execlist(struct intel_engine_cs *engine) · 24 unmodified lines
485508 void intel_engine_setup_common(struct intel_engine_cs *engine)
486509 {
487510 intel_engine_init_execlist(engine);
488−
489511 intel_engine_init_timeline(engine);
490512 intel_engine_init_hangcheck(engine);
491− i915_gem_batch_pool_init(engine, &engine->batch_pool);
492−
513+ intel_engine_init_batch_pool(engine);
493514 intel_engine_init_cmd_parser(engine);
494515 }
495516
@@ -782,10 +803,24 @@ static inline uint32_t · 286 unmodified lines
782803 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
783804 int subslice, i915_reg_t reg)
784805 {
806+ uint32_t mcr_slice_subslice_mask;
807+ uint32_t mcr_slice_subslice_select;
785808 uint32_t mcr;
786809 uint32_t ret;
787810 enum forcewake_domains fw_domains;
788811
812+ if (INTEL_GEN(dev_priv) >= 11) {
813+ mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
814+ GEN11_MCR_SUBSLICE_MASK;
815+ mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
816+ GEN11_MCR_SUBSLICE(subslice);
817+ } else {
818+ mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
819+ GEN8_MCR_SUBSLICE_MASK;
820+ mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
821+ GEN8_MCR_SUBSLICE(subslice);
822+ }
823+
789824 fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
790825 FW_REG_READ);
791826 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
@@ -800,14 +835,14 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice, · 8 unmodified lines
800835 * The HW expects the slice and sublice selectors to be reset to 0
801836 * after reading out the registers.
802837 */
803− WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
804− mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
805− mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
838+ WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
839+ mcr &= ~mcr_slice_subslice_mask;
840+ mcr |= mcr_slice_subslice_select;
806841 I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
807842
808843 ret = I915_READ_FW(reg);
809844
810− mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
845+ mcr &= ~mcr_slice_subslice_mask;
811846 I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
812847
813848 intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
@@ -871,640 +906,6 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine, · 57 unmodified lines
871906 }
872907 }
873908
874−static int wa_add(struct drm_i915_private *dev_priv,
875− i915_reg_t addr,
876− const u32 mask, const u32 val)
877−{
878− const u32 idx = dev_priv->workarounds.count;
879−
880− if (WARN_ON(idx >= I915_MAX_WA_REGS))
881− return -ENOSPC;
882−
883− dev_priv->workarounds.reg[idx].addr = addr;
884− dev_priv->workarounds.reg[idx].value = val;
885− dev_priv->workarounds.reg[idx].mask = mask;
886−
887− dev_priv->workarounds.count++;
888−
889− return 0;
890−}
891−
892−#define WA_REG(addr, mask, val) do { \
893− const int r = wa_add(dev_priv, (addr), (mask), (val)); \
894− if (r) \
895− return r; \
896− } while (0)
897−
898−#define WA_SET_BIT_MASKED(addr, mask) \
899− WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
900−
901−#define WA_CLR_BIT_MASKED(addr, mask) \
902− WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
903−
904−#define WA_SET_FIELD_MASKED(addr, mask, value) \
905− WA_REG(addr, mask, _MASKED_FIELD(mask, value))
906−
907−static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
908− i915_reg_t reg)
909−{
910− struct drm_i915_private *dev_priv = engine->i915;
911− struct i915_workarounds *wa = &dev_priv->workarounds;
912− const uint32_t index = wa->hw_whitelist_count[engine->id];
913−
914− if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
915− return -EINVAL;
916−
917− I915_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
918− i915_mmio_reg_offset(reg));
919− wa->hw_whitelist_count[engine->id]++;
920−
921− return 0;
922−}
923−
924−static int gen8_init_workarounds(struct intel_engine_cs *engine)
925−{
926− struct drm_i915_private *dev_priv = engine->i915;
927−
928− WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
929−
930− /* WaDisableAsyncFlipPerfMode:bdw,chv */
931− WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
932−
933− /* WaDisablePartialInstShootdown:bdw,chv */
934− WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
935− PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
936−
937− /* Use Force Non-Coherent whenever executing a 3D context. This is a
938− * workaround for for a possible hang in the unlikely event a TLB
939− * invalidation occurs during a PSD flush.
940− */
941− /* WaForceEnableNonCoherent:bdw,chv */
942− /* WaHdcDisableFetchWhenMasked:bdw,chv */
943− WA_SET_BIT_MASKED(HDC_CHICKEN0,
944− HDC_DONOT_FETCH_MEM_WHEN_MASKED |
945− HDC_FORCE_NON_COHERENT);
946−
947− /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
948− * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
949− * polygons in the same 8x4 pixel/sample area to be processed without
950− * stalling waiting for the earlier ones to write to Hierarchical Z
951− * buffer."
952− *
953− * This optimization is off by default for BDW and CHV; turn it on.
954− */
955− WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
956−
957− /* Wa4x4STCOptimizationDisable:bdw,chv */
958− WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
959−
960− /*
961− * BSpec recommends 8x4 when MSAA is used,
962− * however in practice 16x4 seems fastest.
963− *
964− * Note that PS/WM thread counts depend on the WIZ hashing
965− * disable bit, which we don't touch here, but it's good
966− * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
967− */
968− WA_SET_FIELD_MASKED(GEN7_GT_MODE,
969− GEN6_WIZ_HASHING_MASK,
970− GEN6_WIZ_HASHING_16x4);
971−
972− return 0;
973−}
974−
975−static int bdw_init_workarounds(struct intel_engine_cs *engine)
976−{
977− struct drm_i915_private *dev_priv = engine->i915;
978− int ret;
979−
980− ret = gen8_init_workarounds(engine);
981− if (ret)
982− return ret;
983−
984− /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
985− WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
986−
987− /* WaDisableDopClockGating:bdw
988− *
989− * Also see the related UCGTCL1 write in broadwell_init_clock_gating()
990− * to disable EUTC clock gating.
991− */
992− WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
993− DOP_CLOCK_GATING_DISABLE);
994−
995− WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
996− GEN8_SAMPLER_POWER_BYPASS_DIS);
997−
998− WA_SET_BIT_MASKED(HDC_CHICKEN0,
999− /* WaForceContextSaveRestoreNonCoherent:bdw */
1000− HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
1001− /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
1002− (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
1003−
1004− return 0;
1005−}
1006−
1007−static int chv_init_workarounds(struct intel_engine_cs *engine)
1008−{
1009− struct drm_i915_private *dev_priv = engine->i915;
1010− int ret;
1011−
1012− ret = gen8_init_workarounds(engine);
1013− if (ret)
1014− return ret;
1015−
1016− /* WaDisableThreadStallDopClockGating:chv */
1017− WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
1018−
1019− /* Improve HiZ throughput on CHV. */
1020− WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
1021−
1022− return 0;
1023−}
1024−
1025−static int gen9_init_workarounds(struct intel_engine_cs *engine)
1026−{
1027− struct drm_i915_private *dev_priv = engine->i915;
1028− int ret;
1029−
1030− /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
1031− I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
1032−
1033− /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
1034− I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
1035− GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
1036−
1037− /* WaDisableKillLogic:bxt,skl,kbl */
1038− if (!IS_COFFEELAKE(dev_priv))
1039− I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1040− ECOCHK_DIS_TLB);
1041−
1042− if (HAS_LLC(dev_priv)) {
1043− /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
1044− *
1045− * Must match Display Engine. See
1046− * WaCompressedResourceDisplayNewHashMode.
1047− */
1048− WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1049− GEN9_PBE_COMPRESSED_HASH_SELECTION);
1050− WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
1051− GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
1052−
1053− I915_WRITE(MMCD_MISC_CTRL,
1054− I915_READ(MMCD_MISC_CTRL) |
1055− MMCD_PCLA |
1056− MMCD_HOTSPOT_EN);
1057− }
1058−
1059− /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
1060− /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
1061− WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1062− FLOW_CONTROL_ENABLE |
1063− PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
1064−
1065− /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
1066− if (!IS_COFFEELAKE(dev_priv))
1067− WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1068− GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
1069−
1070− /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
1071− /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
1072− WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
1073− GEN9_ENABLE_YV12_BUGFIX |
1074− GEN9_ENABLE_GPGPU_PREEMPTION);
1075−
1076− /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
1077− /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
1078− WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
1079− GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
1080−
1081− /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
1082− WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
1083− GEN9_CCS_TLB_PREFETCH_ENABLE);
1084−
1085− /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
1086− WA_SET_BIT_MASKED(HDC_CHICKEN0,
1087− HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
1088− HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
1089−
1090− /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
1091− * both tied to WaForceContextSaveRestoreNonCoherent
1092− * in some hsds for skl. We keep the tie for all gen9. The
1093− * documentation is a bit hazy and so we want to get common behaviour,
1094− * even though there is no clear evidence we would need both on kbl/bxt.
1095− * This area has been source of system hangs so we play it safe
1096− * and mimic the skl regardless of what bspec says.
1097− *
1098− * Use Force Non-Coherent whenever executing a 3D context. This
1099− * is a workaround for a possible hang in the unlikely event
1100− * a TLB invalidation occurs during a PSD flush.
1101− */
1102−
1103− /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
1104− WA_SET_BIT_MASKED(HDC_CHICKEN0,
1105− HDC_FORCE_NON_COHERENT);
1106−
1107− /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
1108− I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1109− BDW_DISABLE_HDC_INVALIDATION);
1110−
1111− /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
1112− if (IS_SKYLAKE(dev_priv) ||
1113− IS_KABYLAKE(dev_priv) ||
1114− IS_COFFEELAKE(dev_priv))
1115− WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1116− GEN8_SAMPLER_POWER_BYPASS_DIS);
1117−
1118− /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
1119− WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1120−
1121− /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
1122− if (IS_GEN9_LP(dev_priv)) {
1123− u32 val = I915_READ(GEN8_L3SQCREG1);
1124−
1125− val &= ~L3_PRIO_CREDITS_MASK;
1126− val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
1127− I915_WRITE(GEN8_L3SQCREG1, val);
1128− }
1129−
1130− /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
1131− I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
1132− GEN8_LQSC_FLUSH_COHERENT_LINES));
1133−
1134− /*
1135− * Supporting preemption with fine-granularity requires changes in the
1136− * batch buffer programming. Since we can't break old userspace, we
1137− * need to set our default preemption level to safe value. Userspace is
1138− * still able to use more fine-grained preemption levels, since in
1139− * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
1140− * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
1141− * not real HW workarounds, but merely a way to start using preemption
1142− * while maintaining old contract with userspace.
1143− */
1144−
1145− /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
1146− WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
1147−
1148− /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
1149− WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
1150− GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
1151−
1152− /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
1153− ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
1154− if (ret)
1155− return ret;
1156−
1157− /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
1158− I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1159− _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1160− ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1161− if (ret)
1162− return ret;
1163−
1164− /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
1165− ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1166− if (ret)
1167− return ret;
1168−
1169− return 0;
1170−}
1171−
1172−static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1173−{
1174− struct drm_i915_private *dev_priv = engine->i915;
1175− u8 vals[3] = { 0, 0, 0 };
1176− unsigned int i;
1177−
1178− for (i = 0; i < 3; i++) {
1179− u8 ss;
1180−
1181− /*
1182− * Only consider slices where one, and only one, subslice has 7
1183− * EUs
1184− */
1185− if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
1186− continue;
1187−
1188− /*
1189− * subslice_7eu[i] != 0 (because of the check above) and
1190− * ss_max == 4 (maximum number of subslices possible per slice)
1191− *
1192− * -> 0 <= ss <= 3;
1193− */
1194− ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
1195− vals[i] = 3 - ss;
1196− }
1197−
1198− if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1199− return 0;
1200−
1201− /* Tune IZ hashing. See intel_device_info_runtime_init() */
1202− WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1203− GEN9_IZ_HASHING_MASK(2) |
1204− GEN9_IZ_HASHING_MASK(1) |
1205− GEN9_IZ_HASHING_MASK(0),
1206− GEN9_IZ_HASHING(2, vals[2]) |
1207− GEN9_IZ_HASHING(1, vals[1]) |
1208− GEN9_IZ_HASHING(0, vals[0]));
1209−
1210− return 0;
1211−}
1212−
1213−static int skl_init_workarounds(struct intel_engine_cs *engine)
1214−{
1215− struct drm_i915_private *dev_priv = engine->i915;
1216− int ret;
1217−
1218− ret = gen9_init_workarounds(engine);
1219− if (ret)
1220− return ret;
1221−
1222− /* WaEnableGapsTsvCreditFix:skl */
1223− I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1224− GEN9_GAPS_TSV_CREDIT_DISABLE));
1225−
1226− /* WaDisableGafsUnitClkGating:skl */
1227− I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
1228− GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
1229−
1230− /* WaInPlaceDecompressionHang:skl */
1231− if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
1232− I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
1233− (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
1234− GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
1235−
1236− /* WaDisableLSQCROPERFforOCL:skl */
1237− ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1238− if (ret)
1239− return ret;
1240−
1241− return skl_tune_iz_hashing(engine);
1242−}
1243−
1244−static int bxt_init_workarounds(struct intel_engine_cs *engine)
1245−{
1246− struct drm_i915_private *dev_priv = engine->i915;
1247− int ret;
1248−
1249− ret = gen9_init_workarounds(engine);
1250− if (ret)
1251− return ret;
1252−
1253− /* WaDisableThreadStallDopClockGating:bxt */
1254− WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1255− STALL_DOP_GATING_DISABLE);
1256−
1257− /* WaDisablePooledEuLoadBalancingFix:bxt */
1258− I915_WRITE(FF_SLICE_CS_CHICKEN2,
1259− _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
1260−
1261− /* WaToEnableHwFixForPushConstHWBug:bxt */
1262− WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1263− GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1264−
1265− /* WaInPlaceDecompressionHang:bxt */
1266− I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
1267− (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
1268− GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
1269−
1270− return 0;
1271−}
1272−
1273−static int cnl_init_workarounds(struct intel_engine_cs *engine)
1274−{
1275− struct drm_i915_private *dev_priv = engine->i915;
1276− int ret;
1277−
1278− /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
1279− if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
1280− I915_WRITE(GAMT_CHKN_BIT_REG,
1281− (I915_READ(GAMT_CHKN_BIT_REG) |
1282− GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT));
1283−
1284− /* WaForceContextSaveRestoreNonCoherent:cnl */
1285− WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
1286− HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
1287−
1288− /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
1289− if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
1290− WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);
1291−
1292− /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
1293− WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1294− GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1295−
1296− /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */
1297− if (IS_CNL_REVID(dev_priv, 0, CNL_REVID_B0))
1298− WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1299− GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
1300−
1301− /* WaInPlaceDecompressionHang:cnl */
1302− I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
1303− (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
1304− GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
1305−
1306− /* WaPushConstantDereferenceHoldDisable:cnl */
1307− WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
1308−
1309− /* FtrEnableFastAnisoL1BankingFix: cnl */
1310− WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
1311−
1312− /* WaDisable3DMidCmdPreemption:cnl */
1313− WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
1314−
1315− /* WaDisableGPGPUMidCmdPreemption:cnl */
1316− WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
1317− GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
1318−
1319− /* WaEnablePreemptionGranularityControlByUMD:cnl */
1320− I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1321− _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1322− ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1323− if (ret)
1324− return ret;
1325−
1326− /* WaDisableEarlyEOT:cnl */
1327− WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
1328−
1329− return 0;
1330−}
1331−
1332−static int kbl_init_workarounds(struct intel_engine_cs *engine)
1333−{
1334− struct drm_i915_private *dev_priv = engine->i915;
1335− int ret;
1336−
1337− ret = gen9_init_workarounds(engine);
1338− if (ret)
1339− return ret;
1340−
1341− /* WaEnableGapsTsvCreditFix:kbl */
1342− I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1343− GEN9_GAPS_TSV_CREDIT_DISABLE));
1344−
1345− /* WaDisableDynamicCreditSharing:kbl */
1346− if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1347− I915_WRITE(GAMT_CHKN_BIT_REG,
1348− (I915_READ(GAMT_CHKN_BIT_REG) |
1349− GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING));
1350−
1351− /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1352− if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1353− WA_SET_BIT_MASKED(HDC_CHICKEN0,
1354− HDC_FENCE_DEST_SLM_DISABLE);
1355−
1356− /* WaToEnableHwFixForPushConstHWBug:kbl */
1357− if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
1358− WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1359− GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1360−
1361− /* WaDisableGafsUnitClkGating:kbl */
1362− I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
1363− GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
1364−
1365− /* WaDisableSbeCacheDispatchPortSharing:kbl */
1366− WA_SET_BIT_MASKED(
1367− GEN7_HALF_SLICE_CHICKEN1,
1368− GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1369−
1370− /* WaInPlaceDecompressionHang:kbl */
1371− I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
1372− (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
1373− GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
1374−
1375− /* WaDisableLSQCROPERFforOCL:kbl */
1376− ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1377− if (ret)
1378− return ret;
1379−
1380− return 0;
1381−}
1382−
1383−static int glk_init_workarounds(struct intel_engine_cs *engine)
1384−{
1385− struct drm_i915_private *dev_priv = engine->i915;
1386− int ret;
1387−
1388− ret = gen9_init_workarounds(engine);
1389− if (ret)
1390− return ret;
1391−
1392− /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
1393− ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1394− if (ret)
1395− return ret;
1396−
1397− /* WaToEnableHwFixForPushConstHWBug:glk */
1398− WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1399− GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1400−
1401− return 0;
1402−}
1403−
1404−static int cfl_init_workarounds(struct intel_engine_cs *engine)
1405−{
1406− struct drm_i915_private *dev_priv = engine->i915;
1407− int ret;
1408−
1409− ret = gen9_init_workarounds(engine);
1410− if (ret)
1411− return ret;
1412−
1413− /* WaEnableGapsTsvCreditFix:cfl */
1414− I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1415− GEN9_GAPS_TSV_CREDIT_DISABLE));
1416−
1417− /* WaToEnableHwFixForPushConstHWBug:cfl */
1418− WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1419− GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1420−
1421− /* WaDisableGafsUnitClkGating:cfl */
1422− I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
1423− GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
1424−
1425− /* WaDisableSbeCacheDispatchPortSharing:cfl */
1426− WA_SET_BIT_MASKED(
1427− GEN7_HALF_SLICE_CHICKEN1,
1428− GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1429−
1430− /* WaInPlaceDecompressionHang:cfl */
1431− I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
1432− (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
1433− GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
1434−
1435− return 0;
1436−}
1437−
1438−int init_workarounds_ring(struct intel_engine_cs *engine)
1439−{
1440− struct drm_i915_private *dev_priv = engine->i915;
1441− int err;
1442−
1443− if (GEM_WARN_ON(engine->id != RCS))
1444− return -EINVAL;
1445−
1446− dev_priv->workarounds.count = 0;
1447− dev_priv->workarounds.hw_whitelist_count[engine->id] = 0;
1448−
1449− if (IS_BROADWELL(dev_priv))
1450− err = bdw_init_workarounds(engine);
1451− else if (IS_CHERRYVIEW(dev_priv))
1452− err = chv_init_workarounds(engine);
1453− else if (IS_SKYLAKE(dev_priv))
1454− err = skl_init_workarounds(engine);
1455− else if (IS_BROXTON(dev_priv))
1456− err = bxt_init_workarounds(engine);
1457− else if (IS_KABYLAKE(dev_priv))
1458− err = kbl_init_workarounds(engine);
1459− else if (IS_GEMINILAKE(dev_priv))
1460− err = glk_init_workarounds(engine);
1461− else if (IS_COFFEELAKE(dev_priv))
1462− err = cfl_init_workarounds(engine);
1463− else if (IS_CANNONLAKE(dev_priv))
1464− err = cnl_init_workarounds(engine);
1465− else
1466− err = 0;
1467− if (err)
1468− return err;
1469−
1470− DRM_DEBUG_DRIVER("%s: Number of context specific w/a: %d\n",
1471− engine->name, dev_priv->workarounds.count);
1472− return 0;
1473−}
1474−
1475−int intel_ring_workarounds_emit(struct i915_request *rq)
1476−{
1477− struct i915_workarounds *w = &rq->i915->workarounds;
1478− u32 *cs;
1479− int ret, i;
1480−
1481− if (w->count == 0)
1482− return 0;
1483−
1484− ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
1485− if (ret)
1486− return ret;
1487−
1488− cs = intel_ring_begin(rq, w->count * 2 + 2);
1489− if (IS_ERR(cs))
1490− return PTR_ERR(cs);
1491−
1492− *cs++ = MI_LOAD_REGISTER_IMM(w->count);
1493− for (i = 0; i < w->count; i++) {
1494− *cs++ = i915_mmio_reg_offset(w->reg[i].addr);
1495− *cs++ = w->reg[i].value;
1496− }
1497− *cs++ = MI_NOOP;
1498−
1499− intel_ring_advance(rq, cs);
1500−
1501− ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
1502− if (ret)
1503− return ret;
1504−
1505− return 0;
1506−}
1507−
1508909 static bool ring_is_idle(struct intel_engine_cs *engine)
1509910 {
1510911 struct drm_i915_private *dev_priv = engine->i915;
@@ -1655,6 +1056,9 @@ void intel_engines_park(struct drm_i915_private *i915) · 144 unmodified lines
16551056 intel_engine_dump(engine, &p, NULL);
16561057 }
16571058
1059+ /* Must be reset upon idling, or we may miss the busy wakeup. */
1060+ GEM_BUG_ON(engine->execlists.queue_priority != INT_MIN);
1061+
16581062 if (engine->park)
16591063 engine->park(engine);
16601064
@@ -1713,13 +1117,15 @@ static void print_request(struct drm_printer *m, · 52 unmodified lines
17131117 struct i915_request *rq,
17141118 const char *prefix)
17151119 {
1120+ const char *name = rq->fence.ops->get_timeline_name(&rq->fence);
1121+
17161122 drm_printf(m, "%s%x%s [%llx:%x] prio=%d @ %dms: %s\n", prefix,
17171123 rq->global_seqno,
17181124 i915_request_completed(rq) ? "!" : "",
17191125 rq->fence.context, rq->fence.seqno,
17201126 rq->priotree.priority,
17211127 jiffies_to_msecs(jiffies - rq->emitted_jiffies),
1722− rq->timeline->common->name);
1128+ name);
17231129 }
17241130
17251131 static void hexdump(struct drm_printer *m, const void *buf, size_t len)
@@ -1825,12 +1231,15 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, · 99 unmodified lines
18251231 ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
18261232 read = GEN8_CSB_READ_PTR(ptr);
18271233 write = GEN8_CSB_WRITE_PTR(ptr);
1828− drm_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], interrupt posted? %s\n",
1234+ drm_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], interrupt posted? %s, tasklet queued? %s (%s)\n",
18291235 read, execlists->csb_head,
18301236 write,
18311237 intel_read_status_page(engine, intel_hws_csb_write_index(engine->i915)),
18321238 yesno(test_bit(ENGINE_IRQ_EXECLIST,
1833− &engine->irq_posted)));
1239+ &engine->irq_posted)),
1240+ yesno(test_bit(TASKLET_STATE_SCHED,
1241+ &engine->execlists.tasklet.state)),
1242+ enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
18341243 if (read >= GEN8_CSB_ENTRIES)
18351244 read = 0;
18361245 if (write >= GEN8_CSB_ENTRIES)
@@ -1929,12 +1338,16 @@ void intel_engine_dump(struct intel_engine_cs *engine, · 92 unmodified lines
19291338 rq->head, rq->postfix, rq->tail,
19301339 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
19311340 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
1932− drm_printf(m, "\t\tring->start: 0x%08x\n",
1341+ drm_printf(m, "\t\tring->start: 0x%08x\n",
19331342 i915_ggtt_offset(rq->ring->vma));
1934− drm_printf(m, "\t\tring->head: 0x%08x\n",
1343+ drm_printf(m, "\t\tring->head: 0x%08x\n",
19351344 rq->ring->head);
1936− drm_printf(m, "\t\tring->tail: 0x%08x\n",
1345+ drm_printf(m, "\t\tring->tail: 0x%08x\n",
19371346 rq->ring->tail);
1347+ drm_printf(m, "\t\tring->emit: 0x%08x\n",
1348+ rq->ring->emit);
1349+ drm_printf(m, "\t\tring->space: 0x%08x\n",
1350+ rq->ring->space);
19381351 }
19391352
19401353 rcu_read_unlock();
@@ -2109,4 +1522,5 @@ void intel_disable_engine_stats(struct intel_engine_cs *engine) · 168 unmodified lines
21091522
21101523 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
21111524 #include "selftests/mock_engine.c"
1525+#include "selftests/intel_engine_cs.c"
21121526 #endif
drivers/gpu/drm/i915/intel_fbc.c+28−0
@@ -1272,6 +1272,34 @@ out: · 1271 unmodified lines
12721272 mutex_unlock(&fbc->lock);
12731273 }
12741274
1275+/*
1276+ * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1277+ * @dev_priv: i915 device instance
1278+ *
1279+ * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1280+ * want to re-enable FBC after an underrun to increase test coverage.
1281+ */
1282+int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1283+{
1284+ int ret;
1285+
1286+ cancel_work_sync(&dev_priv->fbc.underrun_work);
1287+
1288+ ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1289+ if (ret)
1290+ return ret;
1291+
1292+ if (dev_priv->fbc.underrun_detected) {
1293+ DRM_DEBUG_KMS("Re-allowing FBC after fifo underrun\n");
1294+ dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1295+ }
1296+
1297+ dev_priv->fbc.underrun_detected = false;
1298+ mutex_unlock(&dev_priv->fbc.lock);
1299+
1300+ return 0;
1301+}
1302+
12751303 /**
12761304 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
12771305 * @dev_priv: i915 device instance
drivers/gpu/drm/i915/intel_fbdev.c+3−2
@@ -221,6 +221,9 @@ static int intelfb_create(struct drm_fb_helper *helper, · 220 unmodified lines
221221 goto out_unlock;
222222 }
223223
224+ fb = &ifbdev->fb->base;
225+ intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_DIRTYFB);
226+
224227 info = drm_fb_helper_alloc_fbi(helper);
225228 if (IS_ERR(info)) {
226229 DRM_ERROR("Failed to allocate fb_info\n");
@@ -230,8 +233,6 @@ static int intelfb_create(struct drm_fb_helper *helper, · 3 unmodified lines
230233
231234 info->par = helper;
232235
233− fb = &ifbdev->fb->base;
234−
235236 ifbdev->helper.fb = fb;
236237
237238 strcpy(info->fix.id, "inteldrmfb");
drivers/gpu/drm/i915/intel_frontbuffer.c+1−1
@@ -80,7 +80,7 @@ void __intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, · 79 unmodified lines
8080 }
8181
8282 might_sleep();
83− intel_psr_invalidate(dev_priv, frontbuffer_bits);
83+ intel_psr_invalidate(dev_priv, frontbuffer_bits, origin);
8484 intel_edp_drrs_invalidate(dev_priv, frontbuffer_bits);
8585 intel_fbc_invalidate(dev_priv, frontbuffer_bits, origin);
8686 }
drivers/gpu/drm/i915/intel_gpu_commands.h+274−0
@@ -0,0 +1,274 @@
1+/*
2+ * SPDX-License-Identifier: MIT
3+ *
4+ * Copyright � 2003-2018 Intel Corporation
5+ */
6+
7+#ifndef _INTEL_GPU_COMMANDS_H_
8+#define _INTEL_GPU_COMMANDS_H_
9+
10+/*
11+ * Instruction field definitions used by the command parser
12+ */
13+#define INSTR_CLIENT_SHIFT 29
14+#define INSTR_MI_CLIENT 0x0
15+#define INSTR_BC_CLIENT 0x2
16+#define INSTR_RC_CLIENT 0x3
17+#define INSTR_SUBCLIENT_SHIFT 27
18+#define INSTR_SUBCLIENT_MASK 0x18000000
19+#define INSTR_MEDIA_SUBCLIENT 0x2
20+#define INSTR_26_TO_24_MASK 0x7000000
21+#define INSTR_26_TO_24_SHIFT 24
22+
23+/*
24+ * Memory interface instructions used by the kernel
25+ */
26+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
27+/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
28+#define MI_GLOBAL_GTT (1<<22)
29+
30+#define MI_NOOP MI_INSTR(0, 0)
31+#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
32+#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
33+#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
34+#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
35+#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
36+#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
37+#define MI_FLUSH MI_INSTR(0x04, 0)
38+#define MI_READ_FLUSH (1 << 0)
39+#define MI_EXE_FLUSH (1 << 1)
40+#define MI_NO_WRITE_FLUSH (1 << 2)
41+#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
42+#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
43+#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
44+#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
45+#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
46+#define MI_ARB_ENABLE (1<<0)
47+#define MI_ARB_DISABLE (0<<0)
48+#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
49+#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
50+#define MI_SUSPEND_FLUSH_EN (1<<0)
51+#define MI_SET_APPID MI_INSTR(0x0e, 0)
52+#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
53+#define MI_OVERLAY_CONTINUE (0x0<<21)
54+#define MI_OVERLAY_ON (0x1<<21)
55+#define MI_OVERLAY_OFF (0x2<<21)
56+#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
57+#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
58+#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
59+#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
60+/* IVB has funny definitions for which plane to flip. */
61+#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
62+#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
63+#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
64+#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
65+#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
66+#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
67+/* SKL ones */
68+#define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
69+#define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
70+#define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
71+#define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
72+#define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
73+#define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
74+#define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
75+#define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
76+#define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
77+#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
78+#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
79+#define MI_SEMAPHORE_UPDATE (1<<21)
80+#define MI_SEMAPHORE_COMPARE (1<<20)
81+#define MI_SEMAPHORE_REGISTER (1<<18)
82+#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
83+#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
84+#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
85+#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
86+#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
87+#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
88+#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
89+#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
90+#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
91+#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
92+#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
93+#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
94+#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
95+#define MI_SEMAPHORE_SYNC_MASK (3<<16)
96+#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
97+#define MI_MM_SPACE_GTT (1<<8)
98+#define MI_MM_SPACE_PHYSICAL (0<<8)
99+#define MI_SAVE_EXT_STATE_EN (1<<3)
100+#define MI_RESTORE_EXT_STATE_EN (1<<2)
101+#define MI_FORCE_RESTORE (1<<1)
102+#define MI_RESTORE_INHIBIT (1<<0)
103+#define HSW_MI_RS_SAVE_STATE_EN (1<<3)
104+#define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
105+#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
106+#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
107+#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
108+#define MI_SEMAPHORE_POLL (1<<15)
109+#define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
110+#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
111+#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
112+#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
113+#define MI_USE_GGTT (1 << 22) /* g4x+ */
114+#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
115+#define MI_STORE_DWORD_INDEX_SHIFT 2
116+/*
117+ * Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
118+ * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
119+ * simply ignores the register load under certain conditions.
120+ * - One can actually load arbitrary many arbitrary registers: Simply issue x
121+ * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
122+ */
123+#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
124+#define MI_LRI_FORCE_POSTED (1<<12)
125+#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
126+#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
127+#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
128+#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
129+#define MI_FLUSH_DW_STORE_INDEX (1<<21)
130+#define MI_INVALIDATE_TLB (1<<18)
131+#define MI_FLUSH_DW_OP_STOREDW (1<<14)
132+#define MI_FLUSH_DW_OP_MASK (3<<14)
133+#define MI_FLUSH_DW_NOTIFY (1<<8)
134+#define MI_INVALIDATE_BSD (1<<7)
135+#define MI_FLUSH_DW_USE_GTT (1<<2)
136+#define MI_FLUSH_DW_USE_PPGTT (0<<2)
137+#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
138+#define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
139+#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
140+#define MI_BATCH_NON_SECURE (1)
141+/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
142+#define MI_BATCH_NON_SECURE_I965 (1<<8)
143+#define MI_BATCH_PPGTT_HSW (1<<8)
144+#define MI_BATCH_NON_SECURE_HSW (1<<13)
145+#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
146+#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
147+#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
148+#define MI_BATCH_RESOURCE_STREAMER (1<<10)
149+
150+/*
151+ * 3D instructions used by the kernel
152+ */
153+#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
154+
155+#define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
156+#define GEN9_MEDIA_POOL_ENABLE (1 << 31)
157+#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
158+#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
159+#define SC_UPDATE_SCISSOR (0x1<<1)
160+#define SC_ENABLE_MASK (0x1<<0)
161+#define SC_ENABLE (0x1<<0)
162+#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
163+#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
164+#define SCI_YMIN_MASK (0xffff<<16)
165+#define SCI_XMIN_MASK (0xffff<<0)
166+#define SCI_YMAX_MASK (0xffff<<16)
167+#define SCI_XMAX_MASK (0xffff<<0)
168+#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
169+#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
170+#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
171+#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
172+#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
173+#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
174+#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
175+#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
176+#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
177+
178+#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
179+#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
180+#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
181+#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
182+#define BLT_WRITE_A (2<<20)
183+#define BLT_WRITE_RGB (1<<20)
184+#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
185+#define BLT_DEPTH_8 (0<<24)
186+#define BLT_DEPTH_16_565 (1<<24)
187+#define BLT_DEPTH_16_1555 (2<<24)
188+#define BLT_DEPTH_32 (3<<24)
189+#define BLT_ROP_SRC_COPY (0xcc<<16)
190+#define BLT_ROP_COLOR_COPY (0xf0<<16)
191+#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
192+#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
193+#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
194+#define ASYNC_FLIP (1<<22)
195+#define DISPLAY_PLANE_A (0<<20)
196+#define DISPLAY_PLANE_B (1<<20)
197+#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
198+#define PIPE_CONTROL_FLUSH_L3 (1<<27)
199+#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
200+#define PIPE_CONTROL_MMIO_WRITE (1<<23)
201+#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
202+#define PIPE_CONTROL_CS_STALL (1<<20)
203+#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
204+#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
205+#define PIPE_CONTROL_QW_WRITE (1<<14)
206+#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
207+#define PIPE_CONTROL_DEPTH_STALL (1<<13)
208+#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
209+#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
210+#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */
211+#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
212+#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
213+#define PIPE_CONTROL_NOTIFY (1<<8)
214+#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
215+#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
216+#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
217+#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
218+#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
219+#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
220+#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
221+#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
222+
223+/*
224+ * Commands used only by the command parser
225+ */
226+#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
227+#define MI_ARB_CHECK MI_INSTR(0x05, 0)
228+#define MI_RS_CONTROL MI_INSTR(0x06, 0)
229+#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
230+#define MI_PREDICATE MI_INSTR(0x0C, 0)
231+#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
232+#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
233+#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
234+#define MI_URB_CLEAR MI_INSTR(0x19, 0)
235+#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
236+#define MI_CLFLUSH MI_INSTR(0x27, 0)
237+#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
238+#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
239+#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
240+#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
241+#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
242+#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
243+#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
244+
245+#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
246+#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
247+#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
248+#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
249+#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
250+#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
251+#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
252+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
253+#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
254+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
255+#define GFX_OP_3DSTATE_SO_DECL_LIST \
256+ ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
257+
258+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
259+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
260+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
261+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
262+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
263+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
264+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
265+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
266+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
267+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
268+
269+#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
270+
271+#define COLOR_BLT ((0x2<<29)|(0x40<<22))
272+#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
273+
274+#endif /* _INTEL_GPU_COMMANDS_H_ */
drivers/gpu/drm/i915/intel_guc.c+159−52
@@ -64,10 +64,12 @@ void intel_guc_init_early(struct intel_guc *guc) · 63 unmodified lines
6464 {
6565 intel_guc_fw_init_early(guc);
6666 intel_guc_ct_init_early(&guc->ct);
67− intel_guc_log_init_early(guc);
67+ intel_guc_log_init_early(&guc->log);
6868
6969 mutex_init(&guc->send_mutex);
70+ spin_lock_init(&guc->irq_lock);
7071 guc->send = intel_guc_send_nop;
72+ guc->handler = intel_guc_to_host_event_handler_nop;
7173 guc->notify = gen8_guc_raise_irq;
7274 }
7375
@@ -86,9 +88,10 @@ int intel_guc_init_wq(struct intel_guc *guc) · 12 unmodified lines
8688 * or scheduled later on resume. This way the handling of work
8789 * item can be kept same between system suspend & rpm suspend.
8890 */
89− guc->log.runtime.flush_wq = alloc_ordered_workqueue("i915-guc_log",
90− WQ_HIGHPRI | WQ_FREEZABLE);
91− if (!guc->log.runtime.flush_wq) {
91+ guc->log.relay.flush_wq =
92+ alloc_ordered_workqueue("i915-guc_log",
93+ WQ_HIGHPRI | WQ_FREEZABLE);
94+ if (!guc->log.relay.flush_wq) {
9295 DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
9396 return -ENOMEM;
9497 }
@@ -111,7 +114,7 @@ int intel_guc_init_wq(struct intel_guc *guc) · 16 unmodified lines
111114 guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
112115 WQ_HIGHPRI);
113116 if (!guc->preempt_wq) {
114− destroy_workqueue(guc->log.runtime.flush_wq);
117+ destroy_workqueue(guc->log.relay.flush_wq);
115118 DRM_ERROR("Couldn't allocate workqueue for GuC "
116119 "preemption\n");
117120 return -ENOMEM;
@@ -129,7 +132,7 @@ void intel_guc_fini_wq(struct intel_guc *guc) · 11 unmodified lines
129132 USES_GUC_SUBMISSION(dev_priv))
130133 destroy_workqueue(guc->preempt_wq);
131134
132− destroy_workqueue(guc->log.runtime.flush_wq);
135+ destroy_workqueue(guc->log.relay.flush_wq);
133136 }
134137
135138 static int guc_shared_data_create(struct intel_guc *guc)
@@ -169,7 +172,7 @@ int intel_guc_init(struct intel_guc *guc) · 33 unmodified lines
169172 return ret;
170173 GEM_BUG_ON(!guc->shared_data);
171174
172− ret = intel_guc_log_create(guc);
175+ ret = intel_guc_log_create(&guc->log);
173176 if (ret)
174177 goto err_shared;
175178
@@ -184,7 +187,7 @@ int intel_guc_init(struct intel_guc *guc) · 8 unmodified lines
184187 return 0;
185188
186189 err_log:
187− intel_guc_log_destroy(guc);
190+ intel_guc_log_destroy(&guc->log);
188191 err_shared:
189192 guc_shared_data_destroy(guc);
190193 return ret;
@@ -196,7 +199,7 @@ void intel_guc_fini(struct intel_guc *guc) · 5 unmodified lines
196199
197200 i915_ggtt_disable_guc(dev_priv);
198201 intel_guc_ads_destroy(guc);
199− intel_guc_log_destroy(guc);
202+ intel_guc_log_destroy(&guc->log);
200203 guc_shared_data_destroy(guc);
201204 }
202205
@@ -220,17 +223,23 @@ static u32 get_core_family(struct drm_i915_private *dev_priv) · 17 unmodified lines
220223 }
221224 }
222225
223−static u32 get_log_verbosity_flags(void)
226+static u32 get_log_control_flags(void)
224227 {
225− if (i915_modparams.guc_log_level > 0) {
226− u32 verbosity = i915_modparams.guc_log_level - 1;
228+ u32 level = i915_modparams.guc_log_level;
229+ u32 flags = 0;
227230
228− GEM_BUG_ON(verbosity > GUC_LOG_VERBOSITY_MAX);
229− return verbosity << GUC_LOG_VERBOSITY_SHIFT;
230− }
231+ GEM_BUG_ON(level < 0);
232+
233+ if (!GUC_LOG_LEVEL_IS_ENABLED(level))
234+ flags |= GUC_LOG_DEFAULT_DISABLED;
235+
236+ if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
237+ flags |= GUC_LOG_DISABLED;
238+ else
239+ flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
240+ GUC_LOG_VERBOSITY_SHIFT;
231241
232− GEM_BUG_ON(i915_modparams.enable_guc < 0);
233− return GUC_LOG_DISABLED;
242+ return flags;
234243 }
235244
236245 /*
@@ -265,12 +274,13 @@ void intel_guc_init_params(struct intel_guc *guc) · 28 unmodified lines
265274
266275 params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
267276
268− params[GUC_CTL_DEBUG] = get_log_verbosity_flags();
277+ params[GUC_CTL_DEBUG] = get_log_control_flags();
269278
270279 /* If GuC submission is enabled, set up additional parameters here */
271280 if (USES_GUC_SUBMISSION(dev_priv)) {
272− u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
273− u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
281+ u32 ads = intel_guc_ggtt_offset(guc,
282+ guc->ads_vma) >> PAGE_SHIFT;
283+ u32 pgs = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
274284 u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
275285
276286 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
@@ -301,16 +311,23 @@ void intel_guc_init_params(struct intel_guc *guc) · 24 unmodified lines
301311 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
302312 }
303313
304−int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
314+int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
315+ u32 *response_buf, u32 response_buf_size)
305316 {
306317 WARN(1, "Unexpected send: action=%#x\n", *action);
307318 return -ENODEV;
308319 }
309320
321+void intel_guc_to_host_event_handler_nop(struct intel_guc *guc)
322+{
323+ WARN(1, "Unexpected event: no suitable handler\n");
324+}
325+
310326 /*
311327 * This function implements the MMIO based host to GuC interface.
312328 */
313−int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
329+int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
330+ u32 *response_buf, u32 response_buf_size)
314331 {
315332 struct drm_i915_private *dev_priv = guc_to_i915(guc);
316333 u32 status;
@@ -320,6 +337,9 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len) · 3 unmodified lines
320337 GEM_BUG_ON(!len);
321338 GEM_BUG_ON(len > guc->send_regs.count);
322339
340+ /* We expect only action code */
341+ GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK);
342+
323343 /* If CT is available, we expect to use MMIO only during init/fini */
324344 GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
325345 *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
@@ -341,29 +361,74 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len) · 15 unmodified lines
341361 */
342362 ret = __intel_wait_for_register_fw(dev_priv,
343363 guc_send_reg(guc, 0),
344− INTEL_GUC_RECV_MASK,
345− INTEL_GUC_RECV_MASK,
364+ INTEL_GUC_MSG_TYPE_MASK,
365+ INTEL_GUC_MSG_TYPE_RESPONSE <<
366+ INTEL_GUC_MSG_TYPE_SHIFT,
346367 10, 10, &status);
347− if (status != INTEL_GUC_STATUS_SUCCESS) {
348− /*
349− * Either the GuC explicitly returned an error (which
350− * we convert to -EIO here) or no response at all was
351− * received within the timeout limit (-ETIMEDOUT)
352− */
353− if (ret != -ETIMEDOUT)
354− ret = -EIO;
355−
356− DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
357− " ret=%d status=0x%08X response=0x%08X\n",
358− action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
368+ /* If GuC explicitly returned an error, convert it to -EIO */
369+ if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status))
370+ ret = -EIO;
371+
372+ if (ret) {
373+ DRM_DEBUG_DRIVER("INTEL_GUC_SEND: Action 0x%X failed;"
374+ " ret=%d status=0x%08X response=0x%08X\n",
375+ action[0], ret, status,
376+ I915_READ(SOFT_SCRATCH(15)));
377+ goto out;
359378 }
360379
380+ if (response_buf) {
381+ int count = min(response_buf_size, guc->send_regs.count - 1);
382+
383+ for (i = 0; i < count; i++)
384+ response_buf[i] = I915_READ(guc_send_reg(guc, i + 1));
385+ }
386+
387+ /* Use data from the GuC response as our return value */
388+ ret = INTEL_GUC_MSG_TO_DATA(status);
389+
390+out:
361391 intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
362392 mutex_unlock(&guc->send_mutex);
363393
364394 return ret;
365395 }
366396
397+void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc)
398+{
399+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
400+ u32 msg, val;
401+
402+ /*
403+ * Sample the log buffer flush related bits & clear them out now
404+ * itself from the message identity register to minimize the
405+ * probability of losing a flush interrupt, when there are back
406+ * to back flush interrupts.
407+ * There can be a new flush interrupt, for different log buffer
408+ * type (like for ISR), whilst Host is handling one (for DPC).
409+ * Since same bit is used in message register for ISR & DPC, it
410+ * could happen that GuC sets the bit for 2nd interrupt but Host
411+ * clears out the bit on handling the 1st interrupt.
412+ */
413+ spin_lock(&guc->irq_lock);
414+ val = I915_READ(SOFT_SCRATCH(15));
415+ msg = val & guc->msg_enabled_mask;
416+ I915_WRITE(SOFT_SCRATCH(15), val & ~msg);
417+ spin_unlock(&guc->irq_lock);
418+
419+ intel_guc_to_host_process_recv_msg(guc, msg);
420+}
421+
422+void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg)
423+{
424+ /* Make sure to handle only enabled messages */
425+ msg &= guc->msg_enabled_mask;
426+
427+ if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
428+ INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
429+ intel_guc_log_handle_flush_event(&guc->log);
430+}
431+
367432 int intel_guc_sample_forcewake(struct intel_guc *guc)
368433 {
369434 struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -410,7 +475,7 @@ int intel_guc_suspend(struct intel_guc *guc) · 40 unmodified lines
410475 u32 data[] = {
411476 INTEL_GUC_ACTION_ENTER_S_STATE,
412477 GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
413− guc_ggtt_offset(guc->shared_data)
478+ intel_guc_ggtt_offset(guc, guc->shared_data)
414479 };
415480
416481 return intel_guc_send(guc, data, ARRAY_SIZE(data));
@@ -434,7 +499,7 @@ int intel_guc_reset_engine(struct intel_guc *guc, · 17 unmodified lines
434499 data[3] = 0;
435500 data[4] = 0;
436501 data[5] = guc->execbuf_client->stage_id;
437− data[6] = guc_ggtt_offset(guc->shared_data);
502+ data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
438503
439504 return intel_guc_send(guc, data, ARRAY_SIZE(data));
440505 }
@@ -448,12 +513,65 @@ int intel_guc_resume(struct intel_guc *guc) · 7 unmodified lines
448513 u32 data[] = {
449514 INTEL_GUC_ACTION_EXIT_S_STATE,
450515 GUC_POWER_D0,
451− guc_ggtt_offset(guc->shared_data)
516+ intel_guc_ggtt_offset(guc, guc->shared_data)
452517 };
453518
454519 return intel_guc_send(guc, data, ARRAY_SIZE(data));
455520 }
456521
522+/**
523+ * DOC: GuC Address Space
524+ *
525+ * The layout of GuC address space is shown below:
526+ *
527+ * ::
528+ *
529+ * +==============> +====================+ <== GUC_GGTT_TOP
530+ * ^ | |
531+ * | | |
532+ * | | DRAM |
533+ * | | Memory |
534+ * | | |
535+ * GuC | |
536+ * Address +========> +====================+ <== WOPCM Top
537+ * Space ^ | HW contexts RSVD |
538+ * | | | WOPCM |
539+ * | | +==> +--------------------+ <== GuC WOPCM Top
540+ * | GuC ^ | |
541+ * | GGTT | | |
542+ * | Pin GuC | GuC |
543+ * | Bias WOPCM | WOPCM |
544+ * | | Size | |
545+ * | | | | |
546+ * v v v | |
547+ * +=====+=====+==> +====================+ <== GuC WOPCM Base
548+ * | Non-GuC WOPCM |
549+ * | (HuC/Reserved) |
550+ * +====================+ <== WOPCM Base
551+ *
552+ * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM
553+ * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
554+ * to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and
555+ * actual GuC WOPCM size.
556+ */
557+
558+/**
559+ * intel_guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
560+ * @guc: intel_guc structure.
561+ *
562+ * This function will calculate and initialize the ggtt_pin_bias value based on
563+ * overall WOPCM size and GuC WOPCM size.
564+ */
565+void intel_guc_init_ggtt_pin_bias(struct intel_guc *guc)
566+{
567+ struct drm_i915_private *i915 = guc_to_i915(guc);
568+
569+ GEM_BUG_ON(!i915->wopcm.size);
570+ GEM_BUG_ON(i915->wopcm.size < i915->wopcm.guc.base);
571+
572+ guc->ggtt_pin_bias = i915->wopcm.size - i915->wopcm.guc.base;
573+}
574+
457575 /**
458576 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
459577 * @guc: the guc
@@ -462,7 +580,7 @@ int intel_guc_resume(struct intel_guc *guc) · 2 unmodified lines
462580 * This is a wrapper to create an object for use with the GuC. In order to
463581 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
464582 * both some backing storage and a range inside the Global GTT. We must pin
465− * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
583+ * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
466584 * range is reserved inside GuC.
467585 *
468586 * Return: A i915_vma if successful, otherwise an ERR_PTR.
@@ -483,7 +601,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) · 14 unmodified lines
483601 goto err;
484602
485603 ret = i915_vma_pin(vma, 0, PAGE_SIZE,
486− PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
604+ PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
487605 if (ret) {
488606 vma = ERR_PTR(ret);
489607 goto err;
@@ -495,14 +613,3 @@ err: · 5 unmodified lines
495613 i915_gem_object_put(obj);
496614 return vma;
497615 }
498−
499−u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
500−{
501− u32 wopcm_size = GUC_WOPCM_TOP;
502−
503− /* On BXT, the top of WOPCM is reserved for RC6 context */
504− if (IS_GEN9_LP(dev_priv))
505− wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
506−
507− return wopcm_size;
508−}
drivers/gpu/drm/i915/intel_guc.h+70−12
@@ -49,11 +49,16 @@ struct intel_guc { · 48 unmodified lines
4949 struct intel_guc_log log;
5050 struct intel_guc_ct ct;
5151
52+ /* Offset where Non-WOPCM memory starts. */
53+ u32 ggtt_pin_bias;
54+
5255 /* Log snapshot if GuC errors during load */
5356 struct drm_i915_gem_object *load_err_log;
5457
5558 /* intel_guc_recv interrupt related state */
59+ spinlock_t irq_lock;
5660 bool interrupts_enabled;
61+ unsigned int msg_enabled_mask;
5762
5863 struct i915_vma *ads_vma;
5964 struct i915_vma *stage_desc_pool;
@@ -83,7 +88,11 @@ struct intel_guc { · 23 unmodified lines
8388 struct mutex send_mutex;
8489
8590 /* GuC's FW specific send function */
86− int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
91+ int (*send)(struct intel_guc *guc, const u32 *data, u32 len,
92+ u32 *response_buf, u32 response_buf_size);
93+
94+ /* GuC's FW specific event handler function */
95+ void (*handler)(struct intel_guc *guc);
8796
8897 /* GuC's FW specific notify function */
8998 void (*notify)(struct intel_guc *guc);
@@ -92,7 +101,14 @@ struct intel_guc { · 2 unmodified lines
92101 static
93102 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
94103 {
95− return guc->send(guc, action, len);
104+ return guc->send(guc, action, len, NULL, 0);
105+}
106+
107+static inline int
108+intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
109+ u32 *response_buf, u32 response_buf_size)
110+{
111+ return guc->send(guc, action, len, response_buf, response_buf_size);
96112 }
97113
98114 static inline void intel_guc_notify(struct intel_guc *guc)
@@ -100,17 +116,33 @@ static inline void intel_guc_notify(struct intel_guc *guc) · 1 unmodified line
100116 guc->notify(guc);
101117 }
102118
103−/*
104− * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
105− * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
106− * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
107− * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
119+static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
120+{
121+ guc->handler(guc);
122+}
123+
124+/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
125+#define GUC_GGTT_TOP 0xFEE00000
126+
127+/**
128+ * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
129+ * @guc: intel_guc structure.
130+ * @vma: i915 graphics virtual memory area.
131+ *
132+ * GuC does not allow any gfx GGTT address that falls into range
133+ * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
134+ * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from
135+ * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
136+ * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias.
137+ *
138+ * Return: GGTT offset of the @vma.
108139 */
109−static inline u32 guc_ggtt_offset(struct i915_vma *vma)
140+static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
141+ struct i915_vma *vma)
110142 {
111143 u32 offset = i915_ggtt_offset(vma);
112144
113− GEM_BUG_ON(offset < GUC_WOPCM_TOP);
145+ GEM_BUG_ON(offset < guc->ggtt_pin_bias);
114146 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
115147
116148 return offset;
@@ -119,17 +151,43 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma) · 2 unmodified lines
119151 void intel_guc_init_early(struct intel_guc *guc);
120152 void intel_guc_init_send_regs(struct intel_guc *guc);
121153 void intel_guc_init_params(struct intel_guc *guc);
154+void intel_guc_init_ggtt_pin_bias(struct intel_guc *guc);
122155 int intel_guc_init_wq(struct intel_guc *guc);
123156 void intel_guc_fini_wq(struct intel_guc *guc);
124157 int intel_guc_init(struct intel_guc *guc);
125158 void intel_guc_fini(struct intel_guc *guc);
126−int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
127−int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
159+int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
160+ u32 *response_buf, u32 response_buf_size);
161+int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
162+ u32 *response_buf, u32 response_buf_size);
163+void intel_guc_to_host_event_handler(struct intel_guc *guc);
164+void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
165+void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc);
166+void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg);
128167 int intel_guc_sample_forcewake(struct intel_guc *guc);
129168 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
130169 int intel_guc_suspend(struct intel_guc *guc);
131170 int intel_guc_resume(struct intel_guc *guc);
132171 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
133−u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
172+
173+static inline int intel_guc_sanitize(struct intel_guc *guc)
174+{
175+ intel_uc_fw_sanitize(&guc->fw);
176+ return 0;
177+}
178+
179+static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
180+{
181+ spin_lock_irq(&guc->irq_lock);
182+ guc->msg_enabled_mask |= mask;
183+ spin_unlock_irq(&guc->irq_lock);
184+}
185+
186+static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
187+{
188+ spin_lock_irq(&guc->irq_lock);
189+ guc->msg_enabled_mask &= ~mask;
190+ spin_unlock_irq(&guc->irq_lock);
191+}
134192
135193 #endif
drivers/gpu/drm/i915/intel_guc_ads.c+4−4
@@ -75,7 +75,7 @@ static void guc_policies_init(struct guc_policies *policies) · 74 unmodified lines
7575 int intel_guc_ads_create(struct intel_guc *guc)
7676 {
7777 struct drm_i915_private *dev_priv = guc_to_i915(guc);
78− struct i915_vma *vma;
78+ struct i915_vma *vma, *kernel_ctx_vma;
7979 struct page *page;
8080 /* The ads obj includes the struct itself and buffers passed to GuC */
8181 struct {
@@ -121,9 +121,9 @@ int intel_guc_ads_create(struct intel_guc *guc) · 39 unmodified lines
121121 * to find it. Note that we have to skip our header (1 page),
122122 * because our GuC shared data is there.
123123 */
124+ kernel_ctx_vma = dev_priv->kernel_context->engine[RCS].state;
124125 blob->ads.golden_context_lrca =
125− guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) +
126− skipped_offset;
126+ intel_guc_ggtt_offset(guc, kernel_ctx_vma) + skipped_offset;
127127
128128 /*
129129 * The GuC expects us to exclude the portion of the context image that
@@ -135,7 +135,7 @@ int intel_guc_ads_create(struct intel_guc *guc) · 5 unmodified lines
135135 blob->ads.eng_state_size[engine->guc_id] =
136136 engine->context_size - skipped_size;
137137
138− base = guc_ggtt_offset(vma);
138+ base = intel_guc_ggtt_offset(guc, vma);
139139 blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
140140 blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
141141 blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
drivers/gpu/drm/i915/intel_guc_ct.c+494−51
@@ -24,14 +24,49 @@ · 23 unmodified lines
2424 #include "i915_drv.h"
2525 #include "intel_guc_ct.h"
2626
27+#ifdef CONFIG_DRM_I915_DEBUG_GUC
28+#define CT_DEBUG_DRIVER(...) DRM_DEBUG_DRIVER(__VA_ARGS__)
29+#else
30+#define CT_DEBUG_DRIVER(...) do { } while (0)
31+#endif
32+
33+struct ct_request {
34+ struct list_head link;
35+ u32 fence;
36+ u32 status;
37+ u32 response_len;
38+ u32 *response_buf;
39+};
40+
41+struct ct_incoming_request {
42+ struct list_head link;
43+ u32 msg[];
44+};
45+
2746 enum { CTB_SEND = 0, CTB_RECV = 1 };
2847
2948 enum { CTB_OWNER_HOST = 0 };
3049
50+static void ct_incoming_request_worker_func(struct work_struct *w);
51+
52+/**
53+ * intel_guc_ct_init_early - Initialize CT state without requiring device access
54+ * @ct: pointer to CT struct
55+ */
3156 void intel_guc_ct_init_early(struct intel_guc_ct *ct)
3257 {
3358 /* we're using static channel owners */
3459 ct->host_channel.owner = CTB_OWNER_HOST;
60+
61+ spin_lock_init(&ct->lock);
62+ INIT_LIST_HEAD(&ct->pending_requests);
63+ INIT_LIST_HEAD(&ct->incoming_requests);
64+ INIT_WORK(&ct->worker, ct_incoming_request_worker_func);
65+}
66+
67+static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
68+{
69+ return container_of(ct, struct intel_guc, ct);
3570 }
3671
3772 static inline const char *guc_ct_buffer_type_to_str(u32 type)
@@ -49,8 +84,8 @@ static inline const char *guc_ct_buffer_type_to_str(u32 type) · 11 unmodified lines
4984 static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc,
5085 u32 cmds_addr, u32 size, u32 owner)
5186 {
52− DRM_DEBUG_DRIVER("CT: desc %p init addr=%#x size=%u owner=%u\n",
53− desc, cmds_addr, size, owner);
87+ CT_DEBUG_DRIVER("CT: desc %p init addr=%#x size=%u owner=%u\n",
88+ desc, cmds_addr, size, owner);
5489 memset(desc, 0, sizeof(*desc));
5590 desc->addr = cmds_addr;
5691 desc->size = size;
@@ -59,8 +94,8 @@ static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc, · 2 unmodified lines
5994
6095 static void guc_ct_buffer_desc_reset(struct guc_ct_buffer_desc *desc)
6196 {
62− DRM_DEBUG_DRIVER("CT: desc %p reset head=%u tail=%u\n",
63− desc, desc->head, desc->tail);
97+ CT_DEBUG_DRIVER("CT: desc %p reset head=%u tail=%u\n",
98+ desc, desc->head, desc->tail);
6499 desc->head = 0;
65100 desc->tail = 0;
66101 desc->is_in_error = 0;
@@ -79,7 +114,7 @@ static int guc_action_register_ct_buffer(struct intel_guc *guc, · 12 unmodified lines
79114 int err;
80115
81116 /* Can't use generic send(), CT registration must go over MMIO */
82− err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action));
117+ err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
83118 if (err)
84119 DRM_ERROR("CT: register %s buffer failed; err=%d\n",
85120 guc_ct_buffer_type_to_str(type), err);
@@ -98,7 +133,7 @@ static int guc_action_deregister_ct_buffer(struct intel_guc *guc, · 12 unmodified lines
98133 int err;
99134
100135 /* Can't use generic send(), CT deregistration must go over MMIO */
101− err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action));
136+ err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
102137 if (err)
103138 DRM_ERROR("CT: deregister %s buffer failed; owner=%d err=%d\n",
104139 guc_ct_buffer_type_to_str(type), owner, err);
@@ -156,7 +191,8 @@ static int ctch_init(struct intel_guc *guc, · 51 unmodified lines
156191 err = PTR_ERR(blob);
157192 goto err_vma;
158193 }
159− DRM_DEBUG_DRIVER("CT: vma base=%#x\n", guc_ggtt_offset(ctch->vma));
194+ CT_DEBUG_DRIVER("CT: vma base=%#x\n",
195+ intel_guc_ggtt_offset(guc, ctch->vma));
160196
161197 /* store pointers to desc and cmds */
162198 for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
@@ -170,8 +206,8 @@ static int ctch_init(struct intel_guc *guc, · 7 unmodified lines
170206 err_vma:
171207 i915_vma_unpin_and_release(&ctch->vma);
172208 err_out:
173− DRM_DEBUG_DRIVER("CT: channel %d initialization failed; err=%d\n",
174− ctch->owner, err);
209+ CT_DEBUG_DRIVER("CT: channel %d initialization failed; err=%d\n",
210+ ctch->owner, err);
175211 return err;
176212 }
177213
@@ -191,8 +227,8 @@ static int ctch_open(struct intel_guc *guc, · 13 unmodified lines
191227 int err;
192228 int i;
193229
194− DRM_DEBUG_DRIVER("CT: channel %d reopen=%s\n",
195− ctch->owner, yesno(ctch_is_open(ctch)));
230+ CT_DEBUG_DRIVER("CT: channel %d reopen=%s\n",
231+ ctch->owner, yesno(ctch_is_open(ctch)));
196232
197233 if (!ctch->vma) {
198234 err = ctch_init(guc, ctch);
@@ -202,7 +238,7 @@ static int ctch_open(struct intel_guc *guc, · 3 unmodified lines
202238 }
203239
204240 /* vma should be already allocated and map'ed */
205− base = guc_ggtt_offset(ctch->vma);
241+ base = intel_guc_ggtt_offset(guc, ctch->vma);
206242
207243 /* (re)initialize descriptors
208244 * cmds buffers are in the second half of the blob page
@@ -263,10 +299,29 @@ static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch) · 54 unmodified lines
263299 return ++ctch->next_fence;
264300 }
265301
302+/**
303+ * DOC: CTB Host to GuC request
304+ *
305+ * Format of the CTB Host to GuC request message is as follows::
306+ *
307+ * +------------+---------+---------+---------+---------+
308+ * | msg[0] | [1] | [2] | ... | [n-1] |
309+ * +------------+---------+---------+---------+---------+
310+ * | MESSAGE | MESSAGE PAYLOAD |
311+ * + HEADER +---------+---------+---------+---------+
312+ * | | 0 | 1 | ... | n |
313+ * +============+=========+=========+=========+=========+
314+ * | len >= 1 | FENCE | request specific data |
315+ * +------+-----+---------+---------+---------+---------+
316+ *
317+ * ^-----------------len-------------------^
318+ */
319+
266320 static int ctb_write(struct intel_guc_ct_buffer *ctb,
267321 const u32 *action,
268322 u32 len /* in dwords */,
269− u32 fence)
323+ u32 fence,
324+ bool want_response)
270325 {
271326 struct guc_ct_buffer_desc *desc = ctb->desc;
272327 u32 head = desc->head / 4; /* in dwords */
@@ -295,15 +350,21 @@ static int ctb_write(struct intel_guc_ct_buffer *ctb, · 22 unmodified lines
295350 if (unlikely(used + len + 1 >= size))
296351 return -ENOSPC;
297352
298− /* Write the message. The format is the following:
353+ /*
354+ * Write the message. The format is the following:
299355 * DW0: header (including action code)
300356 * DW1: fence
301357 * DW2+: action data
302358 */
303359 header = (len << GUC_CT_MSG_LEN_SHIFT) |
304360 (GUC_CT_MSG_WRITE_FENCE_TO_DESC) |
361+ (want_response ? GUC_CT_MSG_SEND_STATUS : 0) |
305362 (action[0] << GUC_CT_MSG_ACTION_SHIFT);
306363
364+ CT_DEBUG_DRIVER("CT: writing %*ph %*ph %*ph\n",
365+ 4, &header, 4, &fence,
366+ 4 * (len - 1), &action[1]);
367+
307368 cmds[tail] = header;
308369 tail = (tail + 1) % size;
309370
@@ -322,16 +383,25 @@ static int ctb_write(struct intel_guc_ct_buffer *ctb, · 12 unmodified lines
322383 return 0;
323384 }
324385
325−/* Wait for the response from the GuC.
386+/**
387+ * wait_for_ctb_desc_update - Wait for the CT buffer descriptor update.
388+ * @desc: buffer descriptor
326389 * @fence: response fence
327390 * @status: placeholder for status
328− * return: 0 response received (status is valid)
329− * -ETIMEDOUT no response within hardcoded timeout
330− * -EPROTO no response, ct buffer was in error
391+ *
392+ * Guc will update CT buffer descriptor with new fence and status
393+ * after processing the command identified by the fence. Wait for
394+ * specified fence and then read from the descriptor status of the
395+ * command.
396+ *
397+ * Return:
398+ * * 0 response received (status is valid)
399+ * * -ETIMEDOUT no response within hardcoded timeout
400+ * * -EPROTO no response, CT buffer is in error
331401 */
332−static int wait_for_response(struct guc_ct_buffer_desc *desc,
333− u32 fence,
334− u32 *status)
402+static int wait_for_ctb_desc_update(struct guc_ct_buffer_desc *desc,
403+ u32 fence,
404+ u32 *status)
335405 {
336406 int err;
337407
@@ -363,71 +433,440 @@ static int wait_for_response(struct guc_ct_buffer_desc *desc, · 25 unmodified lines
363433 return err;
364434 }
365435
366−static int ctch_send(struct intel_guc *guc,
436+/**
437+ * wait_for_ct_request_update - Wait for CT request state update.
438+ * @req: pointer to pending request
439+ * @status: placeholder for status
440+ *
441+ * For each sent request, Guc shall send bac CT response message.
442+ * Our message handler will update status of tracked request once
443+ * response message with given fence is received. Wait here and
444+ * check for valid response status value.
445+ *
446+ * Return:
447+ * * 0 response received (status is valid)
448+ * * -ETIMEDOUT no response within hardcoded timeout
449+ */
450+static int wait_for_ct_request_update(struct ct_request *req, u32 *status)
451+{
452+ int err;
453+
454+ /*
455+ * Fast commands should complete in less than 10us, so sample quickly
456+ * up to that length of time, then switch to a slower sleep-wait loop.
457+ * No GuC command should ever take longer than 10ms.
458+ */
459+#define done INTEL_GUC_MSG_IS_RESPONSE(READ_ONCE(req->status))
460+ err = wait_for_us(done, 10);
461+ if (err)
462+ err = wait_for(done, 10);
463+#undef done
464+
465+ if (unlikely(err))
466+ DRM_ERROR("CT: fence %u err %d\n", req->fence, err);
467+
468+ *status = req->status;
469+ return err;
470+}
471+
472+static int ctch_send(struct intel_guc_ct *ct,
367473 struct intel_guc_ct_channel *ctch,
368474 const u32 *action,
369475 u32 len,
476+ u32 *response_buf,
477+ u32 response_buf_size,
370478 u32 *status)
371479 {
372480 struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_SEND];
373481 struct guc_ct_buffer_desc *desc = ctb->desc;
482+ struct ct_request request;
483+ unsigned long flags;
374484 u32 fence;
375485 int err;
376486
377487 GEM_BUG_ON(!ctch_is_open(ctch));
378488 GEM_BUG_ON(!len);
379489 GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
490+ GEM_BUG_ON(!response_buf && response_buf_size);
380491
381492 fence = ctch_get_next_fence(ctch);
382− err = ctb_write(ctb, action, len, fence);
493+ request.fence = fence;
494+ request.status = 0;
495+ request.response_len = response_buf_size;
496+ request.response_buf = response_buf;
497+
498+ spin_lock_irqsave(&ct->lock, flags);
499+ list_add_tail(&request.link, &ct->pending_requests);
500+ spin_unlock_irqrestore(&ct->lock, flags);
501+
502+ err = ctb_write(ctb, action, len, fence, !!response_buf);
383503 if (unlikely(err))
384− return err;
504+ goto unlink;
385505
386− intel_guc_notify(guc);
506+ intel_guc_notify(ct_to_guc(ct));
387507
388− err = wait_for_response(desc, fence, status);
508+ if (response_buf)
509+ err = wait_for_ct_request_update(&request, status);
510+ else
511+ err = wait_for_ctb_desc_update(desc, fence, status);
389512 if (unlikely(err))
390− return err;
391− if (*status != INTEL_GUC_STATUS_SUCCESS)
392− return -EIO;
393− return 0;
513+ goto unlink;
514+
515+ if (!INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(*status)) {
516+ err = -EIO;
517+ goto unlink;
518+ }
519+
520+ if (response_buf) {
521+ /* There shall be no data in the status */
522+ WARN_ON(INTEL_GUC_MSG_TO_DATA(request.status));
523+ /* Return actual response len */
524+ err = request.response_len;
525+ } else {
526+ /* There shall be no response payload */
527+ WARN_ON(request.response_len);
528+ /* Return data decoded from the status dword */
529+ err = INTEL_GUC_MSG_TO_DATA(*status);
530+ }
531+
532+unlink:
533+ spin_lock_irqsave(&ct->lock, flags);
534+ list_del(&request.link);
535+ spin_unlock_irqrestore(&ct->lock, flags);
536+
537+ return err;
394538 }
395539
396540 /*
397541 * Command Transport (CT) buffer based GuC send function.
398542 */
399−static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len)
543+static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
544+ u32 *response_buf, u32 response_buf_size)
400545 {
401− struct intel_guc_ct_channel *ctch = &guc->ct.host_channel;
546+ struct intel_guc_ct *ct = &guc->ct;
547+ struct intel_guc_ct_channel *ctch = &ct->host_channel;
402548 u32 status = ~0; /* undefined */
403− int err;
549+ int ret;
404550
405551 mutex_lock(&guc->send_mutex);
406552
407− err = ctch_send(guc, ctch, action, len, &status);
408− if (unlikely(err)) {
553+ ret = ctch_send(ct, ctch, action, len, response_buf, response_buf_size,
554+ &status);
555+ if (unlikely(ret < 0)) {
409556 DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
410− action[0], err, status);
557+ action[0], ret, status);
558+ } else if (unlikely(ret)) {
559+ CT_DEBUG_DRIVER("CT: send action %#x returned %d (%#x)\n",
560+ action[0], ret, ret);
411561 }
412562
413563 mutex_unlock(&guc->send_mutex);
414− return err;
564+ return ret;
565+}
566+
567+static inline unsigned int ct_header_get_len(u32 header)
568+{
569+ return (header >> GUC_CT_MSG_LEN_SHIFT) & GUC_CT_MSG_LEN_MASK;
570+}
571+
572+static inline unsigned int ct_header_get_action(u32 header)
573+{
574+ return (header >> GUC_CT_MSG_ACTION_SHIFT) & GUC_CT_MSG_ACTION_MASK;
575+}
576+
577+static inline bool ct_header_is_response(u32 header)
578+{
579+ return ct_header_get_action(header) == INTEL_GUC_ACTION_DEFAULT;
580+}
581+
582+static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)
583+{
584+ struct guc_ct_buffer_desc *desc = ctb->desc;
585+ u32 head = desc->head / 4; /* in dwords */
586+ u32 tail = desc->tail / 4; /* in dwords */
587+ u32 size = desc->size / 4; /* in dwords */
588+ u32 *cmds = ctb->cmds;
589+ s32 available; /* in dwords */
590+ unsigned int len;
591+ unsigned int i;
592+
593+ GEM_BUG_ON(desc->size % 4);
594+ GEM_BUG_ON(desc->head % 4);
595+ GEM_BUG_ON(desc->tail % 4);
596+ GEM_BUG_ON(tail >= size);
597+ GEM_BUG_ON(head >= size);
598+
599+ /* tail == head condition indicates empty */
600+ available = tail - head;
601+ if (unlikely(available == 0))
602+ return -ENODATA;
603+
604+ /* beware of buffer wrap case */
605+ if (unlikely(available < 0))
606+ available += size;
607+ CT_DEBUG_DRIVER("CT: available %d (%u:%u)\n", available, head, tail);
608+ GEM_BUG_ON(available < 0);
609+
610+ data[0] = cmds[head];
611+ head = (head + 1) % size;
612+
613+ /* message len with header */
614+ len = ct_header_get_len(data[0]) + 1;
615+ if (unlikely(len > (u32)available)) {
616+ DRM_ERROR("CT: incomplete message %*ph %*ph %*ph\n",
617+ 4, data,
618+ 4 * (head + available - 1 > size ?
619+ size - head : available - 1), &cmds[head],
620+ 4 * (head + available - 1 > size ?
621+ available - 1 - size + head : 0), &cmds[0]);
622+ return -EPROTO;
623+ }
624+
625+ for (i = 1; i < len; i++) {
626+ data[i] = cmds[head];
627+ head = (head + 1) % size;
628+ }
629+ CT_DEBUG_DRIVER("CT: received %*ph\n", 4 * len, data);
630+
631+ desc->head = head * 4;
632+ return 0;
415633 }
416634
417635 /**
418− * Enable buffer based command transport
636+ * DOC: CTB GuC to Host response
637+ *
638+ * Format of the CTB GuC to Host response message is as follows::
639+ *
640+ * +------------+---------+---------+---------+---------+---------+
641+ * | msg[0] | [1] | [2] | [3] | ... | [n-1] |
642+ * +------------+---------+---------+---------+---------+---------+
643+ * | MESSAGE | MESSAGE PAYLOAD |
644+ * + HEADER +---------+---------+---------+---------+---------+
645+ * | | 0 | 1 | 2 | ... | n |
646+ * +============+=========+=========+=========+=========+=========+
647+ * | len >= 2 | FENCE | STATUS | response specific data |
648+ * +------+-----+---------+---------+---------+---------+---------+
649+ *
650+ * ^-----------------------len-----------------------^
651+ */
652+
653+static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
654+{
655+ u32 header = msg[0];
656+ u32 len = ct_header_get_len(header);
657+ u32 msglen = len + 1; /* total message length including header */
658+ u32 fence;
659+ u32 status;
660+ u32 datalen;
661+ struct ct_request *req;
662+ bool found = false;
663+
664+ GEM_BUG_ON(!ct_header_is_response(header));
665+ GEM_BUG_ON(!in_irq());
666+
667+ /* Response payload shall at least include fence and status */
668+ if (unlikely(len < 2)) {
669+ DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
670+ return -EPROTO;
671+ }
672+
673+ fence = msg[1];
674+ status = msg[2];
675+ datalen = len - 2;
676+
677+ /* Format of the status follows RESPONSE message */
678+ if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
679+ DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
680+ return -EPROTO;
681+ }
682+
683+ CT_DEBUG_DRIVER("CT: response fence %u status %#x\n", fence, status);
684+
685+ spin_lock(&ct->lock);
686+ list_for_each_entry(req, &ct->pending_requests, link) {
687+ if (unlikely(fence != req->fence)) {
688+ CT_DEBUG_DRIVER("CT: request %u awaits response\n",
689+ req->fence);
690+ continue;
691+ }
692+ if (unlikely(datalen > req->response_len)) {
693+ DRM_ERROR("CT: response %u too long %*ph\n",
694+ req->fence, 4 * msglen, msg);
695+ datalen = 0;
696+ }
697+ if (datalen)
698+ memcpy(req->response_buf, msg + 3, 4 * datalen);
699+ req->response_len = datalen;
700+ WRITE_ONCE(req->status, status);
701+ found = true;
702+ break;
703+ }
704+ spin_unlock(&ct->lock);
705+
706+ if (!found)
707+ DRM_ERROR("CT: unsolicited response %*ph\n", 4 * msglen, msg);
708+ return 0;
709+}
710+
711+static void ct_process_request(struct intel_guc_ct *ct,
712+ u32 action, u32 len, const u32 *payload)
713+{
714+ struct intel_guc *guc = ct_to_guc(ct);
715+
716+ CT_DEBUG_DRIVER("CT: request %x %*ph\n", action, 4 * len, payload);
717+
718+ switch (action) {
719+ case INTEL_GUC_ACTION_DEFAULT:
720+ if (unlikely(len < 1))
721+ goto fail_unexpected;
722+ intel_guc_to_host_process_recv_msg(guc, *payload);
723+ break;
724+
725+ default:
726+fail_unexpected:
727+ DRM_ERROR("CT: unexpected request %x %*ph\n",
728+ action, 4 * len, payload);
729+ break;
730+ }
731+}
732+
733+static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
734+{
735+ unsigned long flags;
736+ struct ct_incoming_request *request;
737+ u32 header;
738+ u32 *payload;
739+ bool done;
740+
741+ spin_lock_irqsave(&ct->lock, flags);
742+ request = list_first_entry_or_null(&ct->incoming_requests,
743+ struct ct_incoming_request, link);
744+ if (request)
745+ list_del(&request->link);
746+ done = !!list_empty(&ct->incoming_requests);
747+ spin_unlock_irqrestore(&ct->lock, flags);
748+
749+ if (!request)
750+ return true;
751+
752+ header = request->msg[0];
753+ payload = &request->msg[1];
754+ ct_process_request(ct,
755+ ct_header_get_action(header),
756+ ct_header_get_len(header),
757+ payload);
758+
759+ kfree(request);
760+ return done;
761+}
762+
763+static void ct_incoming_request_worker_func(struct work_struct *w)
764+{
765+ struct intel_guc_ct *ct = container_of(w, struct intel_guc_ct, worker);
766+ bool done;
767+
768+ done = ct_process_incoming_requests(ct);
769+ if (!done)
770+ queue_work(system_unbound_wq, &ct->worker);
771+}
772+
773+/**
774+ * DOC: CTB GuC to Host request
775+ *
776+ * Format of the CTB GuC to Host request message is as follows::
777+ *
778+ * +------------+---------+---------+---------+---------+---------+
779+ * | msg[0] | [1] | [2] | [3] | ... | [n-1] |
780+ * +------------+---------+---------+---------+---------+---------+
781+ * | MESSAGE | MESSAGE PAYLOAD |
782+ * + HEADER +---------+---------+---------+---------+---------+
783+ * | | 0 | 1 | 2 | ... | n |
784+ * +============+=========+=========+=========+=========+=========+
785+ * | len | request specific data |
786+ * +------+-----+---------+---------+---------+---------+---------+
787+ *
788+ * ^-----------------------len-----------------------^
789+ */
790+
791+static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
792+{
793+ u32 header = msg[0];
794+ u32 len = ct_header_get_len(header);
795+ u32 msglen = len + 1; /* total message length including header */
796+ struct ct_incoming_request *request;
797+ unsigned long flags;
798+
799+ GEM_BUG_ON(ct_header_is_response(header));
800+
801+ request = kmalloc(sizeof(*request) + 4 * msglen, GFP_ATOMIC);
802+ if (unlikely(!request)) {
803+ DRM_ERROR("CT: dropping request %*ph\n", 4 * msglen, msg);
804+ return 0; /* XXX: -ENOMEM ? */
805+ }
806+ memcpy(request->msg, msg, 4 * msglen);
807+
808+ spin_lock_irqsave(&ct->lock, flags);
809+ list_add_tail(&request->link, &ct->incoming_requests);
810+ spin_unlock_irqrestore(&ct->lock, flags);
811+
812+ queue_work(system_unbound_wq, &ct->worker);
813+ return 0;
814+}
815+
816+static void ct_process_host_channel(struct intel_guc_ct *ct)
817+{
818+ struct intel_guc_ct_channel *ctch = &ct->host_channel;
819+ struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_RECV];
820+ u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
821+ int err = 0;
822+
823+ if (!ctch_is_open(ctch))
824+ return;
825+
826+ do {
827+ err = ctb_read(ctb, msg);
828+ if (err)
829+ break;
830+
831+ if (ct_header_is_response(msg[0]))
832+ err = ct_handle_response(ct, msg);
833+ else
834+ err = ct_handle_request(ct, msg);
835+ } while (!err);
836+
837+ if (GEM_WARN_ON(err == -EPROTO)) {
838+ DRM_ERROR("CT: corrupted message detected!\n");
839+ ctb->desc->is_in_error = 1;
840+ }
841+}
842+
843+/*
844+ * When we're communicating with the GuC over CT, GuC uses events
845+ * to notify us about new messages being posted on the RECV buffer.
846+ */
847+static void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
848+{
849+ struct intel_guc_ct *ct = &guc->ct;
850+
851+ ct_process_host_channel(ct);
852+}
853+
854+/**
855+ * intel_guc_ct_enable - Enable buffer based command transport.
856+ * @ct: pointer to CT struct
857+ *
419858 * Shall only be called for platforms with HAS_GUC_CT.
420− * @guc: the guc
421− * return: 0 on success
422− * non-zero on failure
859+ *
860+ * Return: 0 on success, a negative errno code on failure.
423861 */
424−int intel_guc_enable_ct(struct intel_guc *guc)
862+int intel_guc_ct_enable(struct intel_guc_ct *ct)
425863 {
426− struct drm_i915_private *dev_priv = guc_to_i915(guc);
427− struct intel_guc_ct_channel *ctch = &guc->ct.host_channel;
864+ struct intel_guc *guc = ct_to_guc(ct);
865+ struct drm_i915_private *i915 = guc_to_i915(guc);
866+ struct intel_guc_ct_channel *ctch = &ct->host_channel;
428867 int err;
429868
430− GEM_BUG_ON(!HAS_GUC_CT(dev_priv));
869+ GEM_BUG_ON(!HAS_GUC_CT(i915));
431870
432871 err = ctch_open(guc, ctch);
433872 if (unlikely(err))
@@ -435,21 +874,24 @@ int intel_guc_enable_ct(struct intel_guc *guc) · 1 unmodified line
435874
436875 /* Switch into cmd transport buffer based send() */
437876 guc->send = intel_guc_send_ct;
877+ guc->handler = intel_guc_to_host_event_handler_ct;
438878 DRM_INFO("CT: %s\n", enableddisabled(true));
439879 return 0;
440880 }
441881
442882 /**
443− * Disable buffer based command transport.
883+ * intel_guc_ct_disable - Disable buffer based command transport.
884+ * @ct: pointer to CT struct
885+ *
444886 * Shall only be called for platforms with HAS_GUC_CT.
445− * @guc: the guc
446887 */
447−void intel_guc_disable_ct(struct intel_guc *guc)
888+void intel_guc_ct_disable(struct intel_guc_ct *ct)
448889 {
449− struct drm_i915_private *dev_priv = guc_to_i915(guc);
450− struct intel_guc_ct_channel *ctch = &guc->ct.host_channel;
890+ struct intel_guc *guc = ct_to_guc(ct);
891+ struct drm_i915_private *i915 = guc_to_i915(guc);
892+ struct intel_guc_ct_channel *ctch = &ct->host_channel;
451893
452− GEM_BUG_ON(!HAS_GUC_CT(dev_priv));
894+ GEM_BUG_ON(!HAS_GUC_CT(i915));
453895
454896 if (!ctch_is_open(ctch))
455897 return;
@@ -458,5 +900,6 @@ void intel_guc_disable_ct(struct intel_guc *guc) · 2 unmodified lines
458900
459901 /* Disable send */
460902 guc->send = intel_guc_send_nop;
903+ guc->handler = intel_guc_to_host_event_handler_nop;
461904 DRM_INFO("CT: %s\n", enableddisabled(false));
462905 }
drivers/gpu/drm/i915/intel_guc_ct.h+14−4
@@ -75,12 +75,22 @@ struct intel_guc_ct_channel { · 74 unmodified lines
7575 struct intel_guc_ct {
7676 struct intel_guc_ct_channel host_channel;
7777 /* other channels are tbd */
78+
79+ /** @lock: protects pending requests list */
80+ spinlock_t lock;
81+
82+ /** @pending_requests: list of requests waiting for response */
83+ struct list_head pending_requests;
84+
85+ /** @incoming_requests: list of incoming requests */
86+ struct list_head incoming_requests;
87+
88+ /** @worker: worker for handling incoming requests */
89+ struct work_struct worker;
7890 };
7991
8092 void intel_guc_ct_init_early(struct intel_guc_ct *ct);
81−
82−/* XXX: move to intel_uc.h ? don't fit there either */
83−int intel_guc_enable_ct(struct intel_guc *guc);
84−void intel_guc_disable_ct(struct intel_guc *guc);
93+int intel_guc_ct_enable(struct intel_guc_ct *ct);
94+void intel_guc_ct_disable(struct intel_guc_ct *ct);
8595
8696 #endif /* _INTEL_GUC_CT_H_ */
drivers/gpu/drm/i915/intel_guc_fw.c+3−4
@@ -165,7 +165,7 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma) · 164 unmodified lines
165165 I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
166166
167167 /* Set the source address for the new blob */
168− offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
168+ offset = intel_guc_ggtt_offset(guc, vma) + guc_fw->header_offset;
169169 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
170170 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
171171
@@ -275,9 +275,8 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma) · 103 unmodified lines
275275 * Called from intel_uc_init_hw() during driver load, resume from sleep and
276276 * after a GPU reset.
277277 *
278− * The firmware image should have already been fetched into memory by the
279− * earlier call to intel_uc_init_fw(), so here we need to only check that
280− * fetch succeeded, and then transfer the image to the h/w.
278+ * The firmware image should have already been fetched into memory, so only
279+ * check that fetch succeeded, and then transfer the image to the h/w.
281280 *
282281 * Return: non-zero code on error
283282 */
drivers/gpu/drm/i915/intel_guc_fwif.h+129−28
@@ -127,7 +127,7 @@ · 126 unmodified lines
127127 #define GUC_PROFILE_ENABLED (1 << 7)
128128 #define GUC_WQ_TRACK_ENABLED (1 << 8)
129129 #define GUC_ADS_ENABLED (1 << 9)
130−#define GUC_DEBUG_RESERVED (1 << 10)
130+#define GUC_LOG_DEFAULT_DISABLED (1 << 10)
131131 #define GUC_ADS_ADDR_SHIFT 11
132132 #define GUC_ADS_ADDR_MASK 0xfffff800
133133
@@ -327,6 +327,58 @@ struct guc_stage_desc { · 193 unmodified lines
327327 u64 desc_private;
328328 } __packed;
329329
330+/**
331+ * DOC: CTB based communication
332+ *
333+ * The CTB (command transport buffer) communication between Host and GuC
334+ * is based on u32 data stream written to the shared buffer. One buffer can
335+ * be used to transmit data only in one direction (one-directional channel).
336+ *
337+ * Current status of the each buffer is stored in the buffer descriptor.
338+ * Buffer descriptor holds tail and head fields that represents active data
339+ * stream. The tail field is updated by the data producer (sender), and head
340+ * field is updated by the data consumer (receiver)::
341+ *
342+ * +------------+
343+ * | DESCRIPTOR | +=================+============+========+
344+ * +============+ | | MESSAGE(s) | |
345+ * | address |--------->+=================+============+========+
346+ * +------------+
347+ * | head | ^-----head--------^
348+ * +------------+
349+ * | tail | ^---------tail-----------------^
350+ * +------------+
351+ * | size | ^---------------size--------------------^
352+ * +------------+
353+ *
354+ * Each message in data stream starts with the single u32 treated as a header,
355+ * followed by optional set of u32 data that makes message specific payload::
356+ *
357+ * +------------+---------+---------+---------+
358+ * | MESSAGE |
359+ * +------------+---------+---------+---------+
360+ * | msg[0] | [1] | ... | [n-1] |
361+ * +------------+---------+---------+---------+
362+ * | MESSAGE | MESSAGE PAYLOAD |
363+ * + HEADER +---------+---------+---------+
364+ * | | 0 | ... | n |
365+ * +======+=====+=========+=========+=========+
366+ * | 31:16| code| | | |
367+ * +------+-----+ | | |
368+ * | 15:5|flags| | | |
369+ * +------+-----+ | | |
370+ * | 4:0| len| | | |
371+ * +------+-----+---------+---------+---------+
372+ *
373+ * ^-------------len-------------^
374+ *
375+ * The message header consists of:
376+ *
377+ * - **len**, indicates length of the message payload (in u32)
378+ * - **code**, indicates message code
379+ * - **flags**, holds various bits to control message handling
380+ */
381+
330382 /*
331383 * Describes single command transport buffer.
332384 * Used by both guc-master and clients.
@@ -534,16 +586,6 @@ struct guc_log_buffer_state { · 201 unmodified lines
534586 u32 version;
535587 } __packed;
536588
537−union guc_log_control {
538− struct {
539− u32 logging_enabled:1;
540− u32 reserved1:3;
541− u32 verbosity:4;
542− u32 reserved2:24;
543− };
544− u32 value;
545−} __packed;
546−
547589 struct guc_ctx_report {
548590 u32 report_return_status;
549591 u32 reserved1[64];
@@ -570,7 +612,68 @@ struct guc_shared_ctx_data { · 20 unmodified lines
570612 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
571613 } __packed;
572614
573−/* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
615+/**
616+ * DOC: MMIO based communication
617+ *
618+ * The MMIO based communication between Host and GuC uses software scratch
619+ * registers, where first register holds data treated as message header,
620+ * and other registers are used to hold message payload.
621+ *
622+ * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8
623+ *
624+ * +-----------+---------+---------+---------+
625+ * | MMIO[0] | MMIO[1] | ... | MMIO[n] |
626+ * +-----------+---------+---------+---------+
627+ * | header | optional payload |
628+ * +======+====+=========+=========+=========+
629+ * | 31:28|type| | | |
630+ * +------+----+ | | |
631+ * | 27:16|data| | | |
632+ * +------+----+ | | |
633+ * | 15:0|code| | | |
634+ * +------+----+---------+---------+---------+
635+ *
636+ * The message header consists of:
637+ *
638+ * - **type**, indicates message type
639+ * - **code**, indicates message code, is specific for **type**
640+ * - **data**, indicates message data, optional, depends on **code**
641+ *
642+ * The following message **types** are supported:
643+ *
644+ * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code
645+ * must be priovided in **code** field. Optional action specific parameters
646+ * can be provided in remaining payload registers or **data** field.
647+ *
648+ * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request,
649+ * action response status will be provided in **code** field. Optional
650+ * response data can be returned in remaining payload registers or **data**
651+ * field.
652+ */
653+
654+#define INTEL_GUC_MSG_TYPE_SHIFT 28
655+#define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT)
656+#define INTEL_GUC_MSG_DATA_SHIFT 16
657+#define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT)
658+#define INTEL_GUC_MSG_CODE_SHIFT 0
659+#define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT)
660+
661+#define __INTEL_GUC_MSG_GET(T, m) \
662+ (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
663+#define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m)
664+#define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m)
665+#define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m)
666+
667+enum intel_guc_msg_type {
668+ INTEL_GUC_MSG_TYPE_REQUEST = 0x0,
669+ INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,
670+};
671+
672+#define __INTEL_GUC_MSG_TYPE_IS(T, m) \
673+ (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
674+#define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m)
675+#define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
676+
574677 enum intel_guc_action {
575678 INTEL_GUC_ACTION_DEFAULT = 0x0,
576679 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
@@ -602,24 +705,22 @@ enum intel_guc_report_status { · 25 unmodified lines
602705 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
603706 };
604707
605−/*
606− * The GuC sends its response to a command by overwriting the
607− * command in SS0. The response is distinguishable from a command
608− * by the fact that all the MASK bits are set. The remaining bits
609− * give more detail.
610− */
611−#define INTEL_GUC_RECV_MASK ((u32)0xF0000000)
612−#define INTEL_GUC_RECV_IS_RESPONSE(x) ((u32)(x) >= INTEL_GUC_RECV_MASK)
613−#define INTEL_GUC_RECV_STATUS(x) (INTEL_GUC_RECV_MASK | (x))
614−
615−/* GUC will return status back to SOFT_SCRATCH_O_REG */
616−enum intel_guc_status {
617− INTEL_GUC_STATUS_SUCCESS = INTEL_GUC_RECV_STATUS(0x0),
618− INTEL_GUC_STATUS_ALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x10),
619− INTEL_GUC_STATUS_DEALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x20),
620− INTEL_GUC_STATUS_GENERIC_FAIL = INTEL_GUC_RECV_STATUS(0x0000F000)
708+#define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)
709+#define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4
710+#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
711+#define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8)
712+
713+enum intel_guc_response_status {
714+ INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
715+ INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
621716 };
622717
718+#define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \
719+ (typecheck(u32, (m)) && \
720+ ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \
721+ ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \
722+ (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT)))
723+
623724 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
624725 enum intel_guc_recv_message {
625726 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
drivers/gpu/drm/i915/intel_guc_log.c+209−335
@@ -23,12 +23,11 @@ · 22 unmodified lines
2323 */
2424
2525 #include <linux/debugfs.h>
26−#include <linux/relay.h>
2726
2827 #include "intel_guc_log.h"
2928 #include "i915_drv.h"
3029
31−static void guc_log_capture_logs(struct intel_guc *guc);
30+static void guc_log_capture_logs(struct intel_guc_log *log);
3231
3332 /**
3433 * DOC: GuC firmware log
@@ -39,7 +38,7 @@ static void guc_log_capture_logs(struct intel_guc *guc); · 4 unmodified lines
3938 * registers value.
4039 */
4140
42−static int guc_log_flush_complete(struct intel_guc *guc)
41+static int guc_action_flush_log_complete(struct intel_guc *guc)
4342 {
4443 u32 action[] = {
4544 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE
@@ -48,7 +47,7 @@ static int guc_log_flush_complete(struct intel_guc *guc) · 2 unmodified lines
4847 return intel_guc_send(guc, action, ARRAY_SIZE(action));
4948 }
5049
51−static int guc_log_flush(struct intel_guc *guc)
50+static int guc_action_flush_log(struct intel_guc *guc)
5251 {
5352 u32 action[] = {
5453 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH,
@@ -58,22 +57,40 @@ static int guc_log_flush(struct intel_guc *guc) · 3 unmodified lines
5857 return intel_guc_send(guc, action, ARRAY_SIZE(action));
5958 }
6059
61−static int guc_log_control(struct intel_guc *guc, bool enable, u32 verbosity)
60+static int guc_action_control_log(struct intel_guc *guc, bool enable,
61+ bool default_logging, u32 verbosity)
6262 {
63− union guc_log_control control_val = {
64− {
65− .logging_enabled = enable,
66− .verbosity = verbosity,
67− },
68− };
6963 u32 action[] = {
7064 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING,
71− control_val.value
65+ (enable ? GUC_LOG_CONTROL_LOGGING_ENABLED : 0) |
66+ (verbosity << GUC_LOG_CONTROL_VERBOSITY_SHIFT) |
67+ (default_logging ? GUC_LOG_CONTROL_DEFAULT_LOGGING : 0)
7268 };
7369
70+ GEM_BUG_ON(verbosity > GUC_LOG_VERBOSITY_MAX);
71+
7472 return intel_guc_send(guc, action, ARRAY_SIZE(action));
7573 }
7674
75+static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
76+{
77+ return container_of(log, struct intel_guc, log);
78+}
79+
80+static void guc_log_enable_flush_events(struct intel_guc_log *log)
81+{
82+ intel_guc_enable_msg(log_to_guc(log),
83+ INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
84+ INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
85+}
86+
87+static void guc_log_disable_flush_events(struct intel_guc_log *log)
88+{
89+ intel_guc_disable_msg(log_to_guc(log),
90+ INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
91+ INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
92+}
93+
7794 /*
7895 * Sub buffer switch callback. Called whenever relay has to switch to a new
7996 * sub buffer, relay stays on the same sub buffer if 0 is returned.
@@ -121,14 +138,7 @@ static struct dentry *create_buf_file_callback(const char *filename, · 41 unmodified lines
121138 if (!parent)
122139 return NULL;
123140
124− /*
125− * Not using the channel filename passed as an argument, since for each
126− * channel relay appends the corresponding CPU number to the filename
127− * passed in relay_open(). This should be fine as relay just needs a
128− * dentry of the file associated with the channel buffer and that file's
129− * name need not be same as the filename passed as an argument.
130− */
131− buf_file = debugfs_create_file("guc_log", mode,
141+ buf_file = debugfs_create_file(filename, mode,
132142 parent, buf, &relay_file_operations);
133143 return buf_file;
134144 }
@@ -149,59 +159,7 @@ static struct rchan_callbacks relay_callbacks = { · 14 unmodified lines
149159 .remove_buf_file = remove_buf_file_callback,
150160 };
151161
152−static int guc_log_relay_file_create(struct intel_guc *guc)
153−{
154− struct drm_i915_private *dev_priv = guc_to_i915(guc);
155− struct dentry *log_dir;
156− int ret;
157−
158− if (!i915_modparams.guc_log_level)
159− return 0;
160−
161− mutex_lock(&guc->log.runtime.relay_lock);
162−
163− /* For now create the log file in /sys/kernel/debug/dri/0 dir */
164− log_dir = dev_priv->drm.primary->debugfs_root;
165−
166− /*
167− * If /sys/kernel/debug/dri/0 location do not exist, then debugfs is
168− * not mounted and so can't create the relay file.
169− * The relay API seems to fit well with debugfs only, for availing relay
170− * there are 3 requirements which can be met for debugfs file only in a
171− * straightforward/clean manner :-
172− * i) Need the associated dentry pointer of the file, while opening the
173− * relay channel.
174− * ii) Should be able to use 'relay_file_operations' fops for the file.
175− * iii) Set the 'i_private' field of file's inode to the pointer of
176− * relay channel buffer.
177− */
178− if (!log_dir) {
179− DRM_ERROR("Debugfs dir not available yet for GuC log file\n");
180− ret = -ENODEV;
181− goto out_unlock;
182− }
183−
184− ret = relay_late_setup_files(guc->log.runtime.relay_chan, "guc_log", log_dir);
185− if (ret < 0 && ret != -EEXIST) {
186− DRM_ERROR("Couldn't associate relay chan with file %d\n", ret);
187− goto out_unlock;
188− }
189−
190− ret = 0;
191−
192−out_unlock:
193− mutex_unlock(&guc->log.runtime.relay_lock);
194− return ret;
195−}
196−
197−static bool guc_log_has_relay(struct intel_guc *guc)
198−{
199− lockdep_assert_held(&guc->log.runtime.relay_lock);
200−
201− return guc->log.runtime.relay_chan != NULL;
202−}
203−
204−static void guc_move_to_next_buf(struct intel_guc *guc)
162+static void guc_move_to_next_buf(struct intel_guc_log *log)
205163 {
206164 /*
207165 * Make sure the updates made in the sub buffer are visible when
@@ -209,21 +167,15 @@ static void guc_move_to_next_buf(struct intel_guc *guc) · 1 unmodified line
209167 */
210168 smp_wmb();
211169
212− if (!guc_log_has_relay(guc))
213− return;
214−
215170 /* All data has been written, so now move the offset of sub buffer. */
216− relay_reserve(guc->log.runtime.relay_chan, guc->log.vma->obj->base.size);
171+ relay_reserve(log->relay.channel, log->vma->obj->base.size);
217172
218173 /* Switch to the next sub buffer */
219− relay_flush(guc->log.runtime.relay_chan);
174+ relay_flush(log->relay.channel);
220175 }
221176
222−static void *guc_get_write_buffer(struct intel_guc *guc)
177+static void *guc_get_write_buffer(struct intel_guc_log *log)
223178 {
224− if (!guc_log_has_relay(guc))
225− return NULL;
226−
227179 /*
228180 * Just get the base address of a new sub buffer and copy data into it
229181 * ourselves. NULL will be returned in no-overwrite mode, if all sub
@@ -233,25 +185,25 @@ static void *guc_get_write_buffer(struct intel_guc *guc) · 3 unmodified lines
233185 * done without using relay_reserve() along with relay_write(). So its
234186 * better to use relay_reserve() alone.
235187 */
236− return relay_reserve(guc->log.runtime.relay_chan, 0);
188+ return relay_reserve(log->relay.channel, 0);
237189 }
238190
239−static bool guc_check_log_buf_overflow(struct intel_guc *guc,
191+static bool guc_check_log_buf_overflow(struct intel_guc_log *log,
240192 enum guc_log_buffer_type type,
241193 unsigned int full_cnt)
242194 {
243− unsigned int prev_full_cnt = guc->log.prev_overflow_count[type];
195+ unsigned int prev_full_cnt = log->stats[type].sampled_overflow;
244196 bool overflow = false;
245197
246198 if (full_cnt != prev_full_cnt) {
247199 overflow = true;
248200
249− guc->log.prev_overflow_count[type] = full_cnt;
250− guc->log.total_overflow_count[type] += full_cnt - prev_full_cnt;
201+ log->stats[type].overflow = full_cnt;
202+ log->stats[type].sampled_overflow += full_cnt - prev_full_cnt;
251203
252204 if (full_cnt < prev_full_cnt) {
253205 /* buffer_full_cnt is a 4 bit counter */
254− guc->log.total_overflow_count[type] += 16;
206+ log->stats[type].sampled_overflow += 16;
255207 }
256208 DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
257209 }
@@ -275,7 +227,7 @@ static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type) · 17 unmodified lines
275227 return 0;
276228 }
277229
278−static void guc_read_update_log_buffer(struct intel_guc *guc)
230+static void guc_read_update_log_buffer(struct intel_guc_log *log)
279231 {
280232 unsigned int buffer_size, read_offset, write_offset, bytes_to_copy, full_cnt;
281233 struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
@@ -284,16 +236,16 @@ static void guc_read_update_log_buffer(struct intel_guc *guc) · 2 unmodified lines
284236 void *src_data, *dst_data;
285237 bool new_overflow;
286238
287− if (WARN_ON(!guc->log.runtime.buf_addr))
288− return;
239+ mutex_lock(&log->relay.lock);
289240
290− /* Get the pointer to shared GuC log buffer */
291− log_buf_state = src_data = guc->log.runtime.buf_addr;
241+ if (WARN_ON(!intel_guc_log_relay_enabled(log)))
242+ goto out_unlock;
292243
293− mutex_lock(&guc->log.runtime.relay_lock);
244+ /* Get the pointer to shared GuC log buffer */
245+ log_buf_state = src_data = log->relay.buf_addr;
294246
295247 /* Get the pointer to local buffer to store the logs */
296− log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc);
248+ log_buf_snapshot_state = dst_data = guc_get_write_buffer(log);
297249
298250 if (unlikely(!log_buf_snapshot_state)) {
299251 /*
@@ -301,10 +253,9 @@ static void guc_read_update_log_buffer(struct intel_guc *guc) · 1 unmodified line
301253 * getting consumed by User at a slow rate.
302254 */
303255 DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
304− guc->log.capture_miss_count++;
305− mutex_unlock(&guc->log.runtime.relay_lock);
256+ log->relay.full_count++;
306257
307− return;
258+ goto out_unlock;
308259 }
309260
310261 /* Actual logs are present from the 2nd page */
@@ -325,8 +276,8 @@ static void guc_read_update_log_buffer(struct intel_guc *guc) · 14 unmodified lines
325276 full_cnt = log_buf_state_local.buffer_full_cnt;
326277
327278 /* Bookkeeping stuff */
328− guc->log.flush_count[type] += log_buf_state_local.flush_to_file;
329− new_overflow = guc_check_log_buf_overflow(guc, type, full_cnt);
279+ log->stats[type].flush += log_buf_state_local.flush_to_file;
280+ new_overflow = guc_check_log_buf_overflow(log, type, full_cnt);
330281
331282 /* Update the state of shared log buffer */
332283 log_buf_state->read_ptr = write_offset;
@@ -373,38 +324,35 @@ static void guc_read_update_log_buffer(struct intel_guc *guc) · 40 unmodified lines
373324 dst_data += buffer_size;
374325 }
375326
376− guc_move_to_next_buf(guc);
327+ guc_move_to_next_buf(log);
377328
378− mutex_unlock(&guc->log.runtime.relay_lock);
329+out_unlock:
330+ mutex_unlock(&log->relay.lock);
379331 }
380332
381333 static void capture_logs_work(struct work_struct *work)
382334 {
383− struct intel_guc *guc =
384− container_of(work, struct intel_guc, log.runtime.flush_work);
385−
386− guc_log_capture_logs(guc);
387−}
335+ struct intel_guc_log *log =
336+ container_of(work, struct intel_guc_log, relay.flush_work);
388337
389−static bool guc_log_has_runtime(struct intel_guc *guc)
390−{
391− return guc->log.runtime.buf_addr != NULL;
338+ guc_log_capture_logs(log);
392339 }
393340
394−static int guc_log_runtime_create(struct intel_guc *guc)
341+static int guc_log_map(struct intel_guc_log *log)
395342 {
343+ struct intel_guc *guc = log_to_guc(log);
396344 struct drm_i915_private *dev_priv = guc_to_i915(guc);
397345 void *vaddr;
398346 int ret;
399347
400− lockdep_assert_held(&dev_priv->drm.struct_mutex);
348+ lockdep_assert_held(&log->relay.lock);
401349
402− if (!guc->log.vma)
350+ if (!log->vma)
403351 return -ENODEV;
404352
405− GEM_BUG_ON(guc_log_has_runtime(guc));
406−
407− ret = i915_gem_object_set_to_wc_domain(guc->log.vma->obj, true);
353+ mutex_lock(&dev_priv->drm.struct_mutex);
354+ ret = i915_gem_object_set_to_wc_domain(log->vma->obj, true);
355+ mutex_unlock(&dev_priv->drm.struct_mutex);
408356 if (ret)
409357 return ret;
410358
@@ -413,49 +361,40 @@ static int guc_log_runtime_create(struct intel_guc *guc) · 2 unmodified lines
413361 * buffer pages, so that we can directly get the data
414362 * (up-to-date) from memory.
415363 */
416− vaddr = i915_gem_object_pin_map(guc->log.vma->obj, I915_MAP_WC);
364+ vaddr = i915_gem_object_pin_map(log->vma->obj, I915_MAP_WC);
417365 if (IS_ERR(vaddr)) {
418366 DRM_ERROR("Couldn't map log buffer pages %d\n", ret);
419367 return PTR_ERR(vaddr);
420368 }
421369
422− guc->log.runtime.buf_addr = vaddr;
370+ log->relay.buf_addr = vaddr;
423371
424372 return 0;
425373 }
426374
427−static void guc_log_runtime_destroy(struct intel_guc *guc)
375+static void guc_log_unmap(struct intel_guc_log *log)
428376 {
429− /*
430− * It's possible that the runtime stuff was never allocated because
431− * GuC log was disabled at the boot time.
432− */
433− if (!guc_log_has_runtime(guc))
434− return;
377+ lockdep_assert_held(&log->relay.lock);
435378
436− i915_gem_object_unpin_map(guc->log.vma->obj);
437− guc->log.runtime.buf_addr = NULL;
379+ i915_gem_object_unpin_map(log->vma->obj);
380+ log->relay.buf_addr = NULL;
438381 }
439382
440−void intel_guc_log_init_early(struct intel_guc *guc)
383+void intel_guc_log_init_early(struct intel_guc_log *log)
441384 {
442− mutex_init(&guc->log.runtime.relay_lock);
443− INIT_WORK(&guc->log.runtime.flush_work, capture_logs_work);
385+ mutex_init(&log->relay.lock);
386+ INIT_WORK(&log->relay.flush_work, capture_logs_work);
444387 }
445388
446−int intel_guc_log_relay_create(struct intel_guc *guc)
389+static int guc_log_relay_create(struct intel_guc_log *log)
447390 {
391+ struct intel_guc *guc = log_to_guc(log);
448392 struct drm_i915_private *dev_priv = guc_to_i915(guc);
449393 struct rchan *guc_log_relay_chan;
450394 size_t n_subbufs, subbuf_size;
451395 int ret;
452396
453− if (!i915_modparams.guc_log_level)
454− return 0;
455−
456− mutex_lock(&guc->log.runtime.relay_lock);
457−
458− GEM_BUG_ON(guc_log_has_relay(guc));
397+ lockdep_assert_held(&log->relay.lock);
459398
460399 /* Keep the size of sub buffers same as shared log buffer */
461400 subbuf_size = GUC_LOG_SIZE;
@@ -468,157 +407,56 @@ int intel_guc_log_relay_create(struct intel_guc *guc) · 6 unmodified lines
468407 */
469408 n_subbufs = 8;
470409
471− /*
472− * Create a relay channel, so that we have buffers for storing
473− * the GuC firmware logs, the channel will be linked with a file
474− * later on when debugfs is registered.
475− */
476− guc_log_relay_chan = relay_open(NULL, NULL, subbuf_size,
477− n_subbufs, &relay_callbacks, dev_priv);
410+ guc_log_relay_chan = relay_open("guc_log",
411+ dev_priv->drm.primary->debugfs_root,
412+ subbuf_size, n_subbufs,
413+ &relay_callbacks, dev_priv);
478414 if (!guc_log_relay_chan) {
479415 DRM_ERROR("Couldn't create relay chan for GuC logging\n");
480416
481417 ret = -ENOMEM;
482− goto err;
418+ return ret;
483419 }
484420
485421 GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size);
486− guc->log.runtime.relay_chan = guc_log_relay_chan;
487−
488− mutex_unlock(&guc->log.runtime.relay_lock);
422+ log->relay.channel = guc_log_relay_chan;
489423
490424 return 0;
491−
492−err:
493− mutex_unlock(&guc->log.runtime.relay_lock);
494− /* logging will be off */
495− i915_modparams.guc_log_level = 0;
496− return ret;
497−}
498−
499−void intel_guc_log_relay_destroy(struct intel_guc *guc)
500−{
501− mutex_lock(&guc->log.runtime.relay_lock);
502−
503− /*
504− * It's possible that the relay was never allocated because
505− * GuC log was disabled at the boot time.
506− */
507− if (!guc_log_has_relay(guc))
508− goto out_unlock;
509−
510− relay_close(guc->log.runtime.relay_chan);
511− guc->log.runtime.relay_chan = NULL;
512−
513−out_unlock:
514− mutex_unlock(&guc->log.runtime.relay_lock);
515425 }
516426
517−static int guc_log_late_setup(struct intel_guc *guc)
427+static void guc_log_relay_destroy(struct intel_guc_log *log)
518428 {
519− struct drm_i915_private *dev_priv = guc_to_i915(guc);
520− int ret;
521−
522− if (!guc_log_has_runtime(guc)) {
523− /*
524− * If log was disabled at boot time, then setup needed to handle
525− * log buffer flush interrupts would not have been done yet, so
526− * do that now.
527− */
528− ret = intel_guc_log_relay_create(guc);
529− if (ret)
530− goto err;
531−
532− mutex_lock(&dev_priv->drm.struct_mutex);
533− intel_runtime_pm_get(dev_priv);
534− ret = guc_log_runtime_create(guc);
535− intel_runtime_pm_put(dev_priv);
536− mutex_unlock(&dev_priv->drm.struct_mutex);
537−
538− if (ret)
539− goto err_relay;
540− }
541−
542− ret = guc_log_relay_file_create(guc);
543− if (ret)
544− goto err_runtime;
545−
546− return 0;
429+ lockdep_assert_held(&log->relay.lock);
547430
548−err_runtime:
549− mutex_lock(&dev_priv->drm.struct_mutex);
550− guc_log_runtime_destroy(guc);
551− mutex_unlock(&dev_priv->drm.struct_mutex);
552−err_relay:
553− intel_guc_log_relay_destroy(guc);
554−err:
555− /* logging will remain off */
556− i915_modparams.guc_log_level = 0;
557− return ret;
431+ relay_close(log->relay.channel);
432+ log->relay.channel = NULL;
558433 }
559434
560−static void guc_log_capture_logs(struct intel_guc *guc)
435+static void guc_log_capture_logs(struct intel_guc_log *log)
561436 {
437+ struct intel_guc *guc = log_to_guc(log);
562438 struct drm_i915_private *dev_priv = guc_to_i915(guc);
563439
564− guc_read_update_log_buffer(guc);
440+ guc_read_update_log_buffer(log);
565441
566442 /*
567443 * Generally device is expected to be active only at this
568444 * time, so get/put should be really quick.
569445 */
570446 intel_runtime_pm_get(dev_priv);
571− guc_log_flush_complete(guc);
572− intel_runtime_pm_put(dev_priv);
573−}
574−
575−static void guc_flush_logs(struct intel_guc *guc)
576−{
577− struct drm_i915_private *dev_priv = guc_to_i915(guc);
578−
579− if (!USES_GUC_SUBMISSION(dev_priv) || !i915_modparams.guc_log_level)
580− return;
581−
582− /* First disable the interrupts, will be renabled afterwards */
583− mutex_lock(&dev_priv->drm.struct_mutex);
584− intel_runtime_pm_get(dev_priv);
585− gen9_disable_guc_interrupts(dev_priv);
586− intel_runtime_pm_put(dev_priv);
587− mutex_unlock(&dev_priv->drm.struct_mutex);
588−
589− /*
590− * Before initiating the forceful flush, wait for any pending/ongoing
591− * flush to complete otherwise forceful flush may not actually happen.
592− */
593− flush_work(&guc->log.runtime.flush_work);
594−
595− /* Ask GuC to update the log buffer state */
596− intel_runtime_pm_get(dev_priv);
597− guc_log_flush(guc);
447+ guc_action_flush_log_complete(guc);
598448 intel_runtime_pm_put(dev_priv);
599−
600− /* GuC would have updated log buffer by now, so capture it */
601− guc_log_capture_logs(guc);
602449 }
603450
604−int intel_guc_log_create(struct intel_guc *guc)
451+int intel_guc_log_create(struct intel_guc_log *log)
605452 {
453+ struct intel_guc *guc = log_to_guc(log);
606454 struct i915_vma *vma;
607455 unsigned long offset;
608456 u32 flags;
609457 int ret;
610458
611− GEM_BUG_ON(guc->log.vma);
612−
613− /*
614− * We require SSE 4.1 for fast reads from the GuC log buffer and
615− * it should be present on the chipsets supporting GuC based
616− * submisssions.
617− */
618− if (WARN_ON(!i915_has_memcpy_from_wc())) {
619− ret = -EINVAL;
620− goto err;
621− }
459+ GEM_BUG_ON(log->vma);
622460
623461 vma = intel_guc_allocate_vma(guc, GUC_LOG_SIZE);
624462 if (IS_ERR(vma)) {
@@ -626,13 +464,7 @@ int intel_guc_log_create(struct intel_guc *guc) · 1 unmodified line
626464 goto err;
627465 }
628466
629− guc->log.vma = vma;
630−
631− if (i915_modparams.guc_log_level) {
632− ret = guc_log_runtime_create(guc);
633− if (ret < 0)
634− goto err_vma;
635− }
467+ log->vma = vma;
636468
637469 /* each allocated unit is a page */
638470 flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
@@ -640,117 +472,159 @@ int intel_guc_log_create(struct intel_guc *guc) · 1 unmodified line
640472 (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
641473 (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
642474
643− offset = guc_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
644− guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
475+ offset = intel_guc_ggtt_offset(guc, vma) >> PAGE_SHIFT;
476+ log->flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
645477
646478 return 0;
647479
648−err_vma:
649− i915_vma_unpin_and_release(&guc->log.vma);
650480 err:
651481 /* logging will be off */
652482 i915_modparams.guc_log_level = 0;
653483 return ret;
654484 }
655485
656−void intel_guc_log_destroy(struct intel_guc *guc)
486+void intel_guc_log_destroy(struct intel_guc_log *log)
487+{
488+ i915_vma_unpin_and_release(&log->vma);
489+}
490+
491+int intel_guc_log_level_get(struct intel_guc_log *log)
657492 {
658− guc_log_runtime_destroy(guc);
659− i915_vma_unpin_and_release(&guc->log.vma);
493+ GEM_BUG_ON(!log->vma);
494+ GEM_BUG_ON(i915_modparams.guc_log_level < 0);
495+
496+ return i915_modparams.guc_log_level;
660497 }
661498
662−int intel_guc_log_control(struct intel_guc *guc, u64 control_val)
499+int intel_guc_log_level_set(struct intel_guc_log *log, u64 val)
663500 {
501+ struct intel_guc *guc = log_to_guc(log);
664502 struct drm_i915_private *dev_priv = guc_to_i915(guc);
665− bool enable_logging = control_val > 0;
666− u32 verbosity;
667503 int ret;
668504
669− if (!guc->log.vma)
670− return -ENODEV;
505+ BUILD_BUG_ON(GUC_LOG_VERBOSITY_MIN != 0);
506+ GEM_BUG_ON(!log->vma);
507+ GEM_BUG_ON(i915_modparams.guc_log_level < 0);
671508
672− BUILD_BUG_ON(GUC_LOG_VERBOSITY_MIN);
673− if (control_val > 1 + GUC_LOG_VERBOSITY_MAX)
509+ /*
510+ * GuC is recognizing log levels starting from 0 to max, we're using 0
511+ * as indication that logging should be disabled.
512+ */
513+ if (val < GUC_LOG_LEVEL_DISABLED || val > GUC_LOG_LEVEL_MAX)
674514 return -EINVAL;
675515
676− /* This combination doesn't make sense & won't have any effect */
677− if (!enable_logging && !i915_modparams.guc_log_level)
678− return 0;
516+ mutex_lock(&dev_priv->drm.struct_mutex);
679517
680− verbosity = enable_logging ? control_val - 1 : 0;
518+ if (i915_modparams.guc_log_level == val) {
519+ ret = 0;
520+ goto out_unlock;
521+ }
681522
682− ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
683− if (ret)
684− return ret;
685523 intel_runtime_pm_get(dev_priv);
686− ret = guc_log_control(guc, enable_logging, verbosity);
524+ ret = guc_action_control_log(guc, GUC_LOG_LEVEL_IS_VERBOSE(val),
525+ GUC_LOG_LEVEL_IS_ENABLED(val),
526+ GUC_LOG_LEVEL_TO_VERBOSITY(val));
687527 intel_runtime_pm_put(dev_priv);
528+ if (ret) {
529+ DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
530+ goto out_unlock;
531+ }
532+
533+ i915_modparams.guc_log_level = val;
534+
535+out_unlock:
688536 mutex_unlock(&dev_priv->drm.struct_mutex);
689537
690− if (ret < 0) {
691− DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret);
692− return ret;
693− }
538+ return ret;
539+}
694540
695− if (enable_logging) {
696− i915_modparams.guc_log_level = 1 + verbosity;
541+bool intel_guc_log_relay_enabled(const struct intel_guc_log *log)
542+{
543+ return log->relay.buf_addr;
544+}
697545
698− /*
699− * If log was disabled at boot time, then the relay channel file
700− * wouldn't have been created by now and interrupts also would
701− * not have been enabled. Try again now, just in case.
702− */
703− ret = guc_log_late_setup(guc);
704− if (ret < 0) {
705− DRM_DEBUG_DRIVER("GuC log late setup failed %d\n", ret);
706− return ret;
707− }
546+int intel_guc_log_relay_open(struct intel_guc_log *log)
547+{
548+ int ret;
708549
709− /* GuC logging is currently the only user of Guc2Host interrupts */
710− mutex_lock(&dev_priv->drm.struct_mutex);
711− intel_runtime_pm_get(dev_priv);
712− gen9_enable_guc_interrupts(dev_priv);
713− intel_runtime_pm_put(dev_priv);
714− mutex_unlock(&dev_priv->drm.struct_mutex);
715− } else {
716− /*
717− * Once logging is disabled, GuC won't generate logs & send an
718− * interrupt. But there could be some data in the log buffer
719− * which is yet to be captured. So request GuC to update the log
720− * buffer state and then collect the left over logs.
721− */
722− guc_flush_logs(guc);
550+ mutex_lock(&log->relay.lock);
723551
724− /* As logging is disabled, update log level to reflect that */
725− i915_modparams.guc_log_level = 0;
552+ if (intel_guc_log_relay_enabled(log)) {
553+ ret = -EEXIST;
554+ goto out_unlock;
726555 }
727556
728− return ret;
729−}
557+ /*
558+ * We require SSE 4.1 for fast reads from the GuC log buffer and
559+ * it should be present on the chipsets supporting GuC based
560+ * submisssions.
561+ */
562+ if (!i915_has_memcpy_from_wc()) {
563+ ret = -ENXIO;
564+ goto out_unlock;
565+ }
730566
731−void i915_guc_log_register(struct drm_i915_private *dev_priv)
732−{
733− if (!USES_GUC_SUBMISSION(dev_priv) || !i915_modparams.guc_log_level)
734− return;
567+ ret = guc_log_relay_create(log);
568+ if (ret)
569+ goto out_unlock;
570+
571+ ret = guc_log_map(log);
572+ if (ret)
573+ goto out_relay;
735574
736− guc_log_late_setup(&dev_priv->guc);
575+ mutex_unlock(&log->relay.lock);
576+
577+ guc_log_enable_flush_events(log);
578+
579+ /*
580+ * When GuC is logging without us relaying to userspace, we're ignoring
581+ * the flush notification. This means that we need to unconditionally
582+ * flush on relay enabling, since GuC only notifies us once.
583+ */
584+ queue_work(log->relay.flush_wq, &log->relay.flush_work);
585+
586+ return 0;
587+
588+out_relay:
589+ guc_log_relay_destroy(log);
590+out_unlock:
591+ mutex_unlock(&log->relay.lock);
592+
593+ return ret;
737594 }
738595
739−void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
596+void intel_guc_log_relay_flush(struct intel_guc_log *log)
740597 {
741− struct intel_guc *guc = &dev_priv->guc;
598+ struct intel_guc *guc = log_to_guc(log);
599+ struct drm_i915_private *i915 = guc_to_i915(guc);
600+
601+ /*
602+ * Before initiating the forceful flush, wait for any pending/ongoing
603+ * flush to complete otherwise forceful flush may not actually happen.
604+ */
605+ flush_work(&log->relay.flush_work);
742606
743− if (!USES_GUC_SUBMISSION(dev_priv))
744− return;
607+ intel_runtime_pm_get(i915);
608+ guc_action_flush_log(guc);
609+ intel_runtime_pm_put(i915);
745610
746− mutex_lock(&dev_priv->drm.struct_mutex);
747− /* GuC logging is currently the only user of Guc2Host interrupts */
748− intel_runtime_pm_get(dev_priv);
749− gen9_disable_guc_interrupts(dev_priv);
750− intel_runtime_pm_put(dev_priv);
611+ /* GuC would have updated log buffer by now, so capture it */
612+ guc_log_capture_logs(log);
613+}
751614
752− guc_log_runtime_destroy(guc);
753− mutex_unlock(&dev_priv->drm.struct_mutex);
615+void intel_guc_log_relay_close(struct intel_guc_log *log)
616+{
617+ guc_log_disable_flush_events(log);
618+ flush_work(&log->relay.flush_work);
619+
620+ mutex_lock(&log->relay.lock);
621+ GEM_BUG_ON(!intel_guc_log_relay_enabled(log));
622+ guc_log_unmap(log);
623+ guc_log_relay_destroy(log);
624+ mutex_unlock(&log->relay.lock);
625+}
754626
755− intel_guc_log_relay_destroy(guc);
627+void intel_guc_log_handle_flush_event(struct intel_guc_log *log)
628+{
629+ queue_work(log->relay.flush_wq, &log->relay.flush_work);
756630 }
drivers/gpu/drm/i915/intel_guc_log.h+40−19
@@ -25,11 +25,12 @@ · 24 unmodified lines
2525 #ifndef _INTEL_GUC_LOG_H_
2626 #define _INTEL_GUC_LOG_H_
2727
28+#include <linux/mutex.h>
29+#include <linux/relay.h>
2830 #include <linux/workqueue.h>
2931
3032 #include "intel_guc_fwif.h"
3133
32−struct drm_i915_private;
3334 struct intel_guc;
3435
3536 /*
@@ -39,33 +40,53 @@ struct intel_guc; · 3 unmodified lines
3940 #define GUC_LOG_SIZE ((1 + GUC_LOG_DPC_PAGES + 1 + GUC_LOG_ISR_PAGES + \
4041 1 + GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT)
4142
43+/*
44+ * While we're using plain log level in i915, GuC controls are much more...
45+ * "elaborate"? We have a couple of bits for verbosity, separate bit for actual
46+ * log enabling, and separate bit for default logging - which "conveniently"
47+ * ignores the enable bit.
48+ */
49+#define GUC_LOG_LEVEL_DISABLED 0
50+#define GUC_LOG_LEVEL_NON_VERBOSE 1
51+#define GUC_LOG_LEVEL_IS_ENABLED(x) ((x) > GUC_LOG_LEVEL_DISABLED)
52+#define GUC_LOG_LEVEL_IS_VERBOSE(x) ((x) > GUC_LOG_LEVEL_NON_VERBOSE)
53+#define GUC_LOG_LEVEL_TO_VERBOSITY(x) ({ \
54+ typeof(x) _x = (x); \
55+ GUC_LOG_LEVEL_IS_VERBOSE(_x) ? _x - 2 : 0; \
56+})
57+#define GUC_VERBOSITY_TO_LOG_LEVEL(x) ((x) + 2)
58+#define GUC_LOG_LEVEL_MAX GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX)
59+
4260 struct intel_guc_log {
4361 u32 flags;
4462 struct i915_vma *vma;
45− /* The runtime stuff gets created only when GuC logging gets enabled */
4663 struct {
4764 void *buf_addr;
4865 struct workqueue_struct *flush_wq;
4966 struct work_struct flush_work;
50− struct rchan *relay_chan;
51− /* To serialize the access to relay_chan */
52− struct mutex relay_lock;
53− } runtime;
67+ struct rchan *channel;
68+ struct mutex lock;
69+ u32 full_count;
70+ } relay;
5471 /* logging related stats */
55− u32 capture_miss_count;
56− u32 flush_interrupt_count;
57− u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
58− u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
59− u32 flush_count[GUC_MAX_LOG_BUFFER];
72+ struct {
73+ u32 sampled_overflow;
74+ u32 overflow;
75+ u32 flush;
76+ } stats[GUC_MAX_LOG_BUFFER];
6077 };
6178
62−int intel_guc_log_create(struct intel_guc *guc);
63−void intel_guc_log_destroy(struct intel_guc *guc);
64−void intel_guc_log_init_early(struct intel_guc *guc);
65−int intel_guc_log_relay_create(struct intel_guc *guc);
66−void intel_guc_log_relay_destroy(struct intel_guc *guc);
67−int intel_guc_log_control(struct intel_guc *guc, u64 control_val);
68−void i915_guc_log_register(struct drm_i915_private *dev_priv);
69−void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
79+void intel_guc_log_init_early(struct intel_guc_log *log);
80+int intel_guc_log_create(struct intel_guc_log *log);
81+void intel_guc_log_destroy(struct intel_guc_log *log);
82+
83+int intel_guc_log_level_get(struct intel_guc_log *log);
84+int intel_guc_log_level_set(struct intel_guc_log *log, u64 control_val);
85+bool intel_guc_log_relay_enabled(const struct intel_guc_log *log);
86+int intel_guc_log_relay_open(struct intel_guc_log *log);
87+void intel_guc_log_relay_flush(struct intel_guc_log *log);
88+void intel_guc_log_relay_close(struct intel_guc_log *log);
89+
90+void intel_guc_log_handle_flush_event(struct intel_guc_log *log);
7091
7192 #endif
drivers/gpu/drm/i915/intel_guc_reg.h+6−8
@@ -66,22 +66,20 @@ · 65 unmodified lines
6666 #define UOS_MOVE (1<<4)
6767 #define START_DMA (1<<0)
6868 #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
69+#define GUC_WOPCM_OFFSET_VALID (1<<0)
6970 #define HUC_LOADING_AGENT_VCR (0<<1)
7071 #define HUC_LOADING_AGENT_GUC (1<<1)
71−#define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
72+#define GUC_WOPCM_OFFSET_SHIFT 14
73+#define GUC_WOPCM_OFFSET_MASK (0x3ffff << GUC_WOPCM_OFFSET_SHIFT)
7274 #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
7375
7476 #define HUC_STATUS2 _MMIO(0xD3B0)
7577 #define HUC_FW_VERIFIED (1<<7)
7678
77−/* Defines WOPCM space available to GuC firmware */
7879 #define GUC_WOPCM_SIZE _MMIO(0xc050)
79−/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
80−#define GUC_WOPCM_TOP (0x80 << 12) /* 512KB */
81−#define BXT_GUC_WOPCM_RC6_RESERVED (0x10 << 12) /* 64KB */
82−
83−/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
84−#define GUC_GGTT_TOP 0xFEE00000
80+#define GUC_WOPCM_SIZE_LOCKED (1<<0)
81+#define GUC_WOPCM_SIZE_SHIFT 12
82+#define GUC_WOPCM_SIZE_MASK (0xfffff << GUC_WOPCM_SIZE_SHIFT)
8583
8684 #define GEN8_GT_PM_CONFIG _MMIO(0x138140)
8785 #define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)
drivers/gpu/drm/i915/intel_guc_submission.c+30−17
@@ -231,8 +231,8 @@ static int create_doorbell(struct intel_guc_client *client) · 230 unmodified lines
231231 if (ret) {
232232 __destroy_doorbell(client);
233233 __update_doorbell_desc(client, GUC_DOORBELL_INVALID);
234− DRM_ERROR("Couldn't create client %u doorbell: %d\n",
235− client->stage_id, ret);
234+ DRM_DEBUG_DRIVER("Couldn't create client %u doorbell: %d\n",
235+ client->stage_id, ret);
236236 return ret;
237237 }
238238
@@ -386,8 +386,8 @@ static void guc_stage_desc_init(struct intel_guc *guc, · 147 unmodified lines
386386 lrc->context_desc = lower_32_bits(ce->lrc_desc);
387387
388388 /* The state page is after PPHWSP */
389− lrc->ring_lrca =
390− guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
389+ lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
390+ LRC_STATE_PN * PAGE_SIZE;
391391
392392 /* XXX: In direct submission, the GuC wants the HW context id
393393 * here. In proxy submission, it wants the stage id
@@ -395,7 +395,7 @@ static void guc_stage_desc_init(struct intel_guc *guc, · 1 unmodified line
395395 lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
396396 (guc_engine_id << GUC_ELC_ENGINE_OFFSET);
397397
398− lrc->ring_begin = guc_ggtt_offset(ce->ring->vma);
398+ lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
399399 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
400400 lrc->ring_next_free_location = lrc->ring_begin;
401401 lrc->ring_current_tail_pointer_value = 0;
@@ -411,7 +411,7 @@ static void guc_stage_desc_init(struct intel_guc *guc, · 9 unmodified lines
411411 * The doorbell, process descriptor, and workqueue are all parts
412412 * of the client object, which the GuC will reference via the GGTT
413413 */
414− gfx_addr = guc_ggtt_offset(client->vma);
414+ gfx_addr = intel_guc_ggtt_offset(guc, client->vma);
415415 desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
416416 client->doorbell_offset;
417417 desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client));
@@ -584,7 +584,7 @@ static void inject_preempt_context(struct work_struct *work) · 166 unmodified lines
584584 data[3] = engine->guc_id;
585585 data[4] = guc->execbuf_client->priority;
586586 data[5] = guc->execbuf_client->stage_id;
587− data[6] = guc_ggtt_offset(guc->shared_data);
587+ data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
588588
589589 if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
590590 execlists_clear_active(&engine->execlists,
@@ -657,6 +657,16 @@ static void port_assign(struct execlist_port *port, struct i915_request *rq) · 66 unmodified lines
657657 port_set(port, i915_request_get(rq));
658658 }
659659
660+static inline int rq_prio(const struct i915_request *rq)
661+{
662+ return rq->priotree.priority;
663+}
664+
665+static inline int port_prio(const struct execlist_port *port)
666+{
667+ return rq_prio(port_request(port));
668+}
669+
660670 static void guc_dequeue(struct intel_engine_cs *engine)
661671 {
662672 struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -672,12 +682,12 @@ static void guc_dequeue(struct intel_engine_cs *engine) · 9 unmodified lines
672682 GEM_BUG_ON(rb_first(&execlists->queue) != rb);
673683
674684 if (port_isset(port)) {
675− if (engine->i915->preempt_context) {
685+ if (intel_engine_has_preemption(engine)) {
676686 struct guc_preempt_work *preempt_work =
677687 &engine->i915->guc.preempt_work[engine->id];
688+ int prio = execlists->queue_priority;
678689
679− if (execlists->queue_priority >
680− max(port_request(port)->priotree.priority, 0)) {
690+ if (__execlists_need_preempt(prio, port_prio(port))) {
681691 execlists_set_active(execlists,
682692 EXECLISTS_ACTIVE_PREEMPT);
683693 queue_work(engine->i915->guc.preempt_wq,
@@ -728,7 +738,7 @@ done: · 44 unmodified lines
728738 execlists->first = rb;
729739 if (submit) {
730740 port_assign(port, last);
731− execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
741+ execlists_user_begin(execlists, execlists->port);
732742 guc_submit(engine);
733743 }
734744
@@ -748,17 +758,20 @@ static void guc_submission_tasklet(unsigned long data) · 13 unmodified lines
748758 struct execlist_port *port = execlists->port;
749759 struct i915_request *rq;
750760
751− rq = port_request(&port[0]);
761+ rq = port_request(port);
752762 while (rq && i915_request_completed(rq)) {
753763 trace_i915_request_out(rq);
754764 i915_request_put(rq);
755765
756− execlists_port_complete(execlists, port);
757−
758− rq = port_request(&port[0]);
766+ port = execlists_port_complete(execlists, port);
767+ if (port_isset(port)) {
768+ execlists_user_begin(execlists, port);
769+ rq = port_request(port);
770+ } else {
771+ execlists_user_end(execlists);
772+ rq = NULL;
773+ }
759774 }
760− if (!rq)
761− execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
762775
763776 if (execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT) &&
764777 intel_read_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX) ==
drivers/gpu/drm/i915/intel_hangcheck.c+6−7
@@ -246,9 +246,8 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) · 245 unmodified lines
246246 */
247247 tmp = I915_READ_CTL(engine);
248248 if (tmp & RING_WAIT) {
249− i915_handle_error(dev_priv, BIT(engine->id),
250− "Kicking stuck wait on %s",
251− engine->name);
249+ i915_handle_error(dev_priv, BIT(engine->id), 0,
250+ "stuck wait on %s", engine->name);
252251 I915_WRITE_CTL(engine, tmp);
253252 return ENGINE_WAIT_KICK;
254253 }
@@ -258,8 +257,8 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) · 3 unmodified lines
258257 default:
259258 return ENGINE_DEAD;
260259 case 1:
261− i915_handle_error(dev_priv, ALL_ENGINES,
262− "Kicking stuck semaphore on %s",
260+ i915_handle_error(dev_priv, ALL_ENGINES, 0,
261+ "stuck semaphore on %s",
263262 engine->name);
264263 I915_WRITE_CTL(engine, tmp);
265264 return ENGINE_WAIT_KICK;
@@ -386,13 +385,13 @@ static void hangcheck_declare_hang(struct drm_i915_private *i915, · 120 unmodified lines
386385 if (stuck != hung)
387386 hung &= ~stuck;
388387 len = scnprintf(msg, sizeof(msg),
389− "%s on ", stuck == hung ? "No progress" : "Hang");
388+ "%s on ", stuck == hung ? "no progress" : "hang");
390389 for_each_engine_masked(engine, i915, hung, tmp)
391390 len += scnprintf(msg + len, sizeof(msg) - len,
392391 "%s, ", engine->name);
393392 msg[len-2] = '\0';
394393
395− return i915_handle_error(i915, hung, "%s", msg);
394+ return i915_handle_error(i915, hung, I915_ERROR_CAPTURE, "%s", msg);
396395 }
397396
398397 /*
drivers/gpu/drm/i915/intel_hdcp.c+132−53
@@ -37,6 +37,43 @@ static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port, · 36 unmodified lines
3737 return 0;
3838 }
3939
40+static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
41+{
42+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
43+ struct i915_power_well *power_well;
44+ enum i915_power_well_id id;
45+ bool enabled = false;
46+
47+ /*
48+ * On HSW and BDW, Display HW loads the Key as soon as Display resumes.
49+ * On all BXT+, SW can load the keys only when the PW#1 is turned on.
50+ */
51+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
52+ id = HSW_DISP_PW_GLOBAL;
53+ else
54+ id = SKL_DISP_PW_1;
55+
56+ mutex_lock(&power_domains->lock);
57+
58+ /* PG1 (power well #1) needs to be enabled */
59+ for_each_power_well(dev_priv, power_well) {
60+ if (power_well->id == id) {
61+ enabled = power_well->ops->is_enabled(dev_priv,
62+ power_well);
63+ break;
64+ }
65+ }
66+ mutex_unlock(&power_domains->lock);
67+
68+ /*
69+ * Another req for hdcp key loadability is enabled state of pll for
70+ * cdclk. Without active crtc we wont land here. So we are assuming that
71+ * cdclk is already on.
72+ */
73+
74+ return enabled;
75+}
76+
4077 static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
4178 {
4279 I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
@@ -142,53 +179,17 @@ bool intel_hdcp_is_ksv_valid(u8 *ksv) · 99 unmodified lines
142179 return true;
143180 }
144181
145−/* Implements Part 2 of the HDCP authorization procedure */
146182 static
147−int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
148− const struct intel_hdcp_shim *shim)
183+int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
184+ const struct intel_hdcp_shim *shim,
185+ u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
149186 {
150187 struct drm_i915_private *dev_priv;
151188 u32 vprime, sha_text, sha_leftovers, rep_ctl;
152− u8 bstatus[2], num_downstream, *ksv_fifo;
153189 int ret, i, j, sha_idx;
154190
155191 dev_priv = intel_dig_port->base.base.dev->dev_private;
156192
157− ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
158− if (ret) {
159− DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
160− return ret;
161− }
162−
163− ret = shim->read_bstatus(intel_dig_port, bstatus);
164− if (ret)
165− return ret;
166−
167− if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
168− DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
169− DRM_ERROR("Max Topology Limit Exceeded\n");
170− return -EPERM;
171− }
172−
173− /*
174− * When repeater reports 0 device count, HDCP1.4 spec allows disabling
175− * the HDCP encryption. That implies that repeater can't have its own
176− * display. As there is no consumption of encrypted content in the
177− * repeater with 0 downstream devices, we are failing the
178− * authentication.
179− */
180− num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
181− if (num_downstream == 0)
182− return -EINVAL;
183−
184− ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
185− if (!ksv_fifo)
186− return -ENOMEM;
187−
188− ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
189− if (ret)
190− return ret;
191−
192193 /* Process V' values from the receiver */
193194 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
194195 ret = shim->read_v_prime_part(intel_dig_port, i, &vprime);
@@ -353,7 +354,8 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port, · 158 unmodified lines
353354 return ret;
354355 sha_idx += sizeof(sha_text);
355356 } else {
356− DRM_ERROR("Invalid number of leftovers %d\n", sha_leftovers);
357+ DRM_DEBUG_KMS("Invalid number of leftovers %d\n",
358+ sha_leftovers);
357359 return -EINVAL;
358360 }
359361
@@ -381,17 +383,83 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port, · 21 unmodified lines
381383 if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
382384 HDCP_SHA1_COMPLETE,
383385 HDCP_SHA1_COMPLETE, 1)) {
384− DRM_ERROR("Timed out waiting for SHA1 complete\n");
386+ DRM_DEBUG_KMS("Timed out waiting for SHA1 complete\n");
385387 return -ETIMEDOUT;
386388 }
387389 if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
388− DRM_ERROR("SHA-1 mismatch, HDCP failed\n");
390+ DRM_DEBUG_KMS("SHA-1 mismatch, HDCP failed\n");
389391 return -ENXIO;
390392 }
391393
394+ return 0;
395+}
396+
397+/* Implements Part 2 of the HDCP authorization procedure */
398+static
399+int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
400+ const struct intel_hdcp_shim *shim)
401+{
402+ u8 bstatus[2], num_downstream, *ksv_fifo;
403+ int ret, i, tries = 3;
404+
405+ ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
406+ if (ret) {
407+ DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
408+ return ret;
409+ }
410+
411+ ret = shim->read_bstatus(intel_dig_port, bstatus);
412+ if (ret)
413+ return ret;
414+
415+ if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
416+ DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
417+ DRM_ERROR("Max Topology Limit Exceeded\n");
418+ return -EPERM;
419+ }
420+
421+ /*
422+ * When repeater reports 0 device count, HDCP1.4 spec allows disabling
423+ * the HDCP encryption. That implies that repeater can't have its own
424+ * display. As there is no consumption of encrypted content in the
425+ * repeater with 0 downstream devices, we are failing the
426+ * authentication.
427+ */
428+ num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
429+ if (num_downstream == 0)
430+ return -EINVAL;
431+
432+ ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
433+ if (!ksv_fifo)
434+ return -ENOMEM;
435+
436+ ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
437+ if (ret)
438+ goto err;
439+
440+ /*
441+ * When V prime mismatches, DP Spec mandates re-read of
442+ * V prime atleast twice.
443+ */
444+ for (i = 0; i < tries; i++) {
445+ ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
446+ ksv_fifo, num_downstream,
447+ bstatus);
448+ if (!ret)
449+ break;
450+ }
451+
452+ if (i == tries) {
453+ DRM_ERROR("V Prime validation failed.(%d)\n", ret);
454+ goto err;
455+ }
456+
392457 DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n",
393458 num_downstream);
394− return 0;
459+ ret = 0;
460+err:
461+ kfree(ksv_fifo);
462+ return ret;
395463 }
396464
397465 /* Implements Part 1 of the HDCP authorization procedure */
@@ -506,15 +574,26 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port, · 108 unmodified lines
506574 */
507575 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
508576
509− ri.reg = 0;
510− ret = shim->read_ri_prime(intel_dig_port, ri.shim);
511− if (ret)
512− return ret;
513− I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
577+ tries = 3;
514578
515− /* Wait for Ri prime match */
516− if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
517− (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
579+ /*
580+ * DP HDCP Spec mandates the two more reattempt to read R0, incase
581+ * of R0 mismatch.
582+ */
583+ for (i = 0; i < tries; i++) {
584+ ri.reg = 0;
585+ ret = shim->read_ri_prime(intel_dig_port, ri.shim);
586+ if (ret)
587+ return ret;
588+ I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
589+
590+ /* Wait for Ri prime match */
591+ if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
592+ (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
593+ break;
594+ }
595+
596+ if (i == tries) {
518597 DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
519598 I915_READ(PORT_HDCP_STATUS(port)));
520599 return -ETIMEDOUT;
@@ -580,8 +659,8 @@ static int _intel_hdcp_enable(struct intel_connector *connector) · 59 unmodified lines
580659 DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
581660 connector->base.name, connector->base.base.id);
582661
583− if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) {
584− DRM_ERROR("PG1 is disabled, cannot load keys\n");
662+ if (!hdcp_key_loadable(dev_priv)) {
663+ DRM_ERROR("HDCP key Load is not possible\n");
585664 return -ENXIO;
586665 }
587666
drivers/gpu/drm/i915/intel_hdmi.c+16−24
@@ -2082,41 +2082,33 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c · 2081 unmodified lines
20822082 * it enables scrambling. This should be called before enabling the HDMI
20832083 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
20842084 * detect a scrambled clock within 100 ms.
2085+ *
2086+ * Returns:
2087+ * True on success, false on failure.
20852088 */
2086−void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2089+bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
20872090 struct drm_connector *connector,
20882091 bool high_tmds_clock_ratio,
20892092 bool scrambling)
20902093 {
2094+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
20912095 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2092− struct drm_i915_private *dev_priv = connector->dev->dev_private;
20932096 struct drm_scrambling *sink_scrambling =
2094− &connector->display_info.hdmi.scdc.scrambling;
2095− struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
2096− intel_hdmi->ddc_bus);
2097− bool ret;
2097+ &connector->display_info.hdmi.scdc.scrambling;
2098+ struct i2c_adapter *adapter =
2099+ intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
20982100
20992101 if (!sink_scrambling->supported)
2100− return;
2101−
2102− DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
2103− encoder->base.name, connector->name);
2102+ return true;
21042103
2105− /* Set TMDS bit clock ratio to 1/40 or 1/10 */
2106− ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio);
2107− if (!ret) {
2108− DRM_ERROR("Set TMDS ratio failed\n");
2109− return;
2110− }
2111−
2112− /* Enable/disable sink scrambling */
2113− ret = drm_scdc_set_scrambling(adptr, scrambling);
2114− if (!ret) {
2115− DRM_ERROR("Set sink scrambling failed\n");
2116− return;
2117− }
2104+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2105+ connector->base.id, connector->name,
2106+ yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
21182107
2119− DRM_DEBUG_KMS("sink scrambling handled\n");
2108+ /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2109+ return drm_scdc_set_high_tmds_clock_ratio(adapter,
2110+ high_tmds_clock_ratio) &&
2111+ drm_scdc_set_scrambling(adapter, scrambling);
21202112 }
21212113
21222114 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
drivers/gpu/drm/i915/intel_hotplug.c+3−0
@@ -100,6 +100,8 @@ enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv, · 99 unmodified lines
100100 if (IS_CNL_WITH_PORT_F(dev_priv))
101101 return PORT_F;
102102 return PORT_E;
103+ case HPD_PORT_F:
104+ return PORT_F;
103105 default:
104106 return PORT_NONE; /* no port for this pin */
105107 }
@@ -132,6 +134,7 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, · 26 unmodified lines
132134 case PORT_F:
133135 if (IS_CNL_WITH_PORT_F(dev_priv))
134136 return HPD_PORT_E;
137+ return HPD_PORT_F;
135138 default:
136139 MISSING_CASE(port);
137140 return HPD_NONE;
drivers/gpu/drm/i915/intel_huc.c+28−2
@@ -55,7 +55,7 @@ int intel_huc_auth(struct intel_huc *huc) · 54 unmodified lines
5555 return -ENOEXEC;
5656
5757 vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
58− PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
58+ PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
5959 if (IS_ERR(vma)) {
6060 ret = PTR_ERR(vma);
6161 DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
@@ -63,7 +63,8 @@ int intel_huc_auth(struct intel_huc *huc) · 1 unmodified line
6363 }
6464
6565 ret = intel_guc_auth_huc(guc,
66− guc_ggtt_offset(vma) + huc->fw.rsa_offset);
66+ intel_guc_ggtt_offset(guc, vma) +
67+ huc->fw.rsa_offset);
6768 if (ret) {
6869 DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
6970 goto fail_unpin;
@@ -91,3 +92,28 @@ fail: · 21 unmodified lines
9192 DRM_ERROR("HuC: Authentication failed %d\n", ret);
9293 return ret;
9394 }
95+
96+/**
97+ * intel_huc_check_status() - check HuC status
98+ * @huc: intel_huc structure
99+ *
100+ * This function reads status register to verify if HuC
101+ * firmware was successfully loaded.
102+ *
103+ * Returns positive value if HuC firmware is loaded and verified
104+ * and -ENODEV if HuC is not present.
105+ */
106+int intel_huc_check_status(struct intel_huc *huc)
107+{
108+ struct drm_i915_private *dev_priv = huc_to_i915(huc);
109+ u32 status;
110+
111+ if (!HAS_HUC(dev_priv))
112+ return -ENODEV;
113+
114+ intel_runtime_pm_get(dev_priv);
115+ status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
116+ intel_runtime_pm_put(dev_priv);
117+
118+ return status;
119+}
drivers/gpu/drm/i915/intel_huc.h+7−0
@@ -37,5 +37,12 @@ struct intel_huc { · 36 unmodified lines
3737
3838 void intel_huc_init_early(struct intel_huc *huc);
3939 int intel_huc_auth(struct intel_huc *huc);
40+int intel_huc_check_status(struct intel_huc *huc);
41+
42+static inline int intel_huc_sanitize(struct intel_huc *huc)
43+{
44+ intel_uc_fw_sanitize(&huc->fw);
45+ return 0;
46+}
4047
4148 #endif
drivers/gpu/drm/i915/intel_huc_fw.c+4−4
@@ -118,7 +118,8 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma) · 117 unmodified lines
118118 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
119119
120120 /* Set the source address for the uCode */
121− offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
121+ offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
122+ huc_fw->header_offset;
122123 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
123124 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
124125
@@ -154,9 +155,8 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma) · 29 unmodified lines
154155 * Called from intel_uc_init_hw() during driver load, resume from sleep and
155156 * after a GPU reset. Note that HuC must be loaded before GuC.
156157 *
157− * The firmware image should have already been fetched into memory by the
158− * earlier call to intel_uc_init_fw(), so here we need to only check that
159− * fetch succeeded, and then transfer the image to the h/w.
158+ * The firmware image should have already been fetched into memory, so only
159+ * check that fetch succeeded, and then transfer the image to the h/w.
160160 *
161161 * Return: non-zero code on error
162162 */
drivers/gpu/drm/i915/intel_lrc.c+178−76
@@ -139,6 +139,7 @@ · 138 unmodified lines
139139 #include "i915_gem_render_state.h"
140140 #include "intel_lrc_reg.h"
141141 #include "intel_mocs.h"
142+#include "intel_workarounds.h"
142143
143144 #define RING_EXECLIST_QFULL (1 << 0x2)
144145 #define RING_EXECLIST1_VALID (1 << 0x3)
@@ -183,7 +184,8 @@ static inline bool need_preempt(const struct intel_engine_cs *engine, · 38 unmodified lines
183184 const struct i915_request *last,
184185 int prio)
185186 {
186− return engine->i915->preempt_context && prio > max(rq_prio(last), 0);
187+ return (intel_engine_has_preemption(engine) &&
188+ __execlists_need_preempt(prio, rq_prio(last)));
187189 }
188190
189191 /**
@@ -374,6 +376,19 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status) · 184 unmodified lines
374376 status, rq);
375377 }
376378
379+inline void
380+execlists_user_begin(struct intel_engine_execlists *execlists,
381+ const struct execlist_port *port)
382+{
383+ execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER);
384+}
385+
386+inline void
387+execlists_user_end(struct intel_engine_execlists *execlists)
388+{
389+ execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
390+}
391+
377392 static inline void
378393 execlists_context_schedule_in(struct i915_request *rq)
379394 {
@@ -454,10 +469,12 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) · 74 unmodified lines
454469 desc = execlists_update_context(rq);
455470 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
456471
457− GEM_TRACE("%s in[%d]: ctx=%d.%d, seqno=%x, prio=%d\n",
472+ GEM_TRACE("%s in[%d]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
458473 engine->name, n,
459474 port[n].context_id, count,
460475 rq->global_seqno,
476+ rq->fence.context, rq->fence.seqno,
477+ intel_engine_get_seqno(engine),
461478 rq_prio(rq));
462479 } else {
463480 GEM_BUG_ON(!n);
@@ -697,8 +714,27 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 233 unmodified lines
697714 if (p->priority != I915_PRIORITY_NORMAL)
698715 kmem_cache_free(engine->i915->priorities, p);
699716 }
717+
700718 done:
701− execlists->queue_priority = rb ? to_priolist(rb)->priority : INT_MIN;
719+ /*
720+ * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
721+ *
722+ * We choose queue_priority such that if we add a request of greater
723+ * priority than this, we kick the submission tasklet to decide on
724+ * the right order of submitting the requests to hardware. We must
725+ * also be prepared to reorder requests as they are in-flight on the
726+ * HW. We derive the queue_priority then as the first "hole" in
727+ * the HW submission ports and if there are no available slots,
728+ * the priority of the lowest executing request, i.e. last.
729+ *
730+ * When we do receive a higher priority request ready to run from the
731+ * user, see queue_request(), the queue_priority is bumped to that
732+ * request triggering preemption on the next dequeue (or subsequent
733+ * interrupt for secondary ports).
734+ */
735+ execlists->queue_priority =
736+ port != execlists->port ? rq_prio(last) : INT_MIN;
737+
702738 execlists->first = rb;
703739 if (submit)
704740 port_assign(port, last);
@@ -710,7 +746,7 @@ unlock: · 5 unmodified lines
710746 spin_unlock_irq(&engine->timeline->lock);
711747
712748 if (submit) {
713− execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
749+ execlists_user_begin(execlists, execlists->port);
714750 execlists_submit_ports(engine);
715751 }
716752
@@ -727,6 +763,13 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) · 10 unmodified lines
727763 while (num_ports-- && port_isset(port)) {
728764 struct i915_request *rq = port_request(port);
729765
766+ GEM_TRACE("%s:port%u global=%d (fence %llx:%d), (current %d)\n",
767+ rq->engine->name,
768+ (unsigned int)(port - execlists->port),
769+ rq->global_seqno,
770+ rq->fence.context, rq->fence.seqno,
771+ intel_engine_get_seqno(rq->engine));
772+
730773 GEM_BUG_ON(!execlists->active);
731774 intel_engine_context_out(rq->engine);
732775
@@ -741,7 +784,58 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) · 8 unmodified lines
741784 port++;
742785 }
743786
744− execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
787+ execlists_user_end(execlists);
788+}
789+
790+static void clear_gtiir(struct intel_engine_cs *engine)
791+{
792+ static const u8 gtiir[] = {
793+ [RCS] = 0,
794+ [BCS] = 0,
795+ [VCS] = 1,
796+ [VCS2] = 1,
797+ [VECS] = 3,
798+ };
799+ struct drm_i915_private *dev_priv = engine->i915;
800+ int i;
801+
802+ /* TODO: correctly reset irqs for gen11 */
803+ if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11))
804+ return;
805+
806+ GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
807+
808+ /*
809+ * Clear any pending interrupt state.
810+ *
811+ * We do it twice out of paranoia that some of the IIR are
812+ * double buffered, and so if we only reset it once there may
813+ * still be an interrupt pending.
814+ */
815+ for (i = 0; i < 2; i++) {
816+ I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
817+ engine->irq_keep_mask);
818+ POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
819+ }
820+ GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
821+ engine->irq_keep_mask);
822+}
823+
824+static void reset_irq(struct intel_engine_cs *engine)
825+{
826+ /* Mark all CS interrupts as complete */
827+ smp_store_mb(engine->execlists.active, 0);
828+ synchronize_hardirq(engine->i915->drm.irq);
829+
830+ clear_gtiir(engine);
831+
832+ /*
833+ * The port is checked prior to scheduling a tasklet, but
834+ * just in case we have suspended the tasklet to do the
835+ * wedging make sure that when it wakes, it decides there
836+ * is no work to do by clearing the irq_posted bit.
837+ */
838+ clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
745839 }
746840
747841 static void execlists_cancel_requests(struct intel_engine_cs *engine)
@@ -751,7 +845,8 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine) · 3 unmodified lines
751845 struct rb_node *rb;
752846 unsigned long flags;
753847
754− GEM_TRACE("%s\n", engine->name);
848+ GEM_TRACE("%s current %d\n",
849+ engine->name, intel_engine_get_seqno(engine));
755850
756851 /*
757852 * Before we call engine->cancel_requests(), we should have exclusive
@@ -771,6 +866,7 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine) · 13 unmodified lines
771866
772867 /* Cancel the requests on the HW and clear the ELSP tracker. */
773868 execlists_cancel_port_requests(execlists);
869+ reset_irq(engine);
774870
775871 spin_lock(&engine->timeline->lock);
776872
@@ -809,17 +905,6 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine) · 32 unmodified lines
809905
810906 spin_unlock(&engine->timeline->lock);
811907
812− /*
813− * The port is checked prior to scheduling a tasklet, but
814− * just in case we have suspended the tasklet to do the
815− * wedging make sure that when it wakes, it decides there
816− * is no work to do by clearing the irq_posted bit.
817− */
818− clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
819−
820− /* Mark all CS interrupts as complete */
821− execlists->active = 0;
822−
823908 local_irq_restore(flags);
824909 }
825910
@@ -831,7 +916,7 @@ static void execlists_submission_tasklet(unsigned long data) · 5 unmodified lines
831916 {
832917 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
833918 struct intel_engine_execlists * const execlists = &engine->execlists;
834− struct execlist_port * const port = execlists->port;
919+ struct execlist_port *port = execlists->port;
835920 struct drm_i915_private *dev_priv = engine->i915;
836921 bool fw = false;
837922
@@ -958,10 +1043,13 @@ static void execlists_submission_tasklet(unsigned long data) · 120 unmodified lines
9581043 EXECLISTS_ACTIVE_USER));
9591044
9601045 rq = port_unpack(port, &count);
961− GEM_TRACE("%s out[0]: ctx=%d.%d, seqno=%x, prio=%d\n",
1046+ GEM_TRACE("%s out[0]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
9621047 engine->name,
9631048 port->context_id, count,
9641049 rq ? rq->global_seqno : 0,
1050+ rq ? rq->fence.context : 0,
1051+ rq ? rq->fence.seqno : 0,
1052+ intel_engine_get_seqno(engine),
9651053 rq ? rq_prio(rq) : 0);
9661054
9671055 /* Check the context/desc id for this event matches */
@@ -969,10 +1057,28 @@ static void execlists_submission_tasklet(unsigned long data) · 1 unmodified line
9691057
9701058 GEM_BUG_ON(count == 0);
9711059 if (--count == 0) {
1060+ /*
1061+ * On the final event corresponding to the
1062+ * submission of this context, we expect either
1063+ * an element-switch event or a completion
1064+ * event (and on completion, the active-idle
1065+ * marker). No more preemptions, lite-restore
1066+ * or otherwise.
1067+ */
9721068 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
9731069 GEM_BUG_ON(port_isset(&port[1]) &&
9741070 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
1071+ GEM_BUG_ON(!port_isset(&port[1]) &&
1072+ !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
1073+
1074+ /*
1075+ * We rely on the hardware being strongly
1076+ * ordered, that the breadcrumb write is
1077+ * coherent (visible from the CPU) before the
1078+ * user interrupt and CSB is processed.
1079+ */
9751080 GEM_BUG_ON(!i915_request_completed(rq));
1081+
9761082 execlists_context_schedule_out(rq);
9771083 trace_i915_request_out(rq);
9781084 i915_request_put(rq);
@@ -980,17 +1086,14 @@ static void execlists_submission_tasklet(unsigned long data) · 1 unmodified line
9801086 GEM_TRACE("%s completed ctx=%d\n",
9811087 engine->name, port->context_id);
9821088
983− execlists_port_complete(execlists, port);
1089+ port = execlists_port_complete(execlists, port);
1090+ if (port_isset(port))
1091+ execlists_user_begin(execlists, port);
1092+ else
1093+ execlists_user_end(execlists);
9841094 } else {
9851095 port_set(port, port_pack(rq, count));
9861096 }
987−
988− /* After the final element, the hw should be idle */
989− GEM_BUG_ON(port_count(port) == 0 &&
990− !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
991− if (port_count(port) == 0)
992− execlists_clear_active(execlists,
993− EXECLISTS_ACTIVE_USER);
9941097 }
9951098
9961099 if (head != execlists->csb_head) {
@@ -1019,12 +1122,16 @@ static void queue_request(struct intel_engine_cs *engine, · 22 unmodified lines
10191122 list_add_tail(&pt->link, &lookup_priolist(engine, pt, prio)->requests);
10201123 }
10211124
1125+static void __submit_queue(struct intel_engine_cs *engine, int prio)
1126+{
1127+ engine->execlists.queue_priority = prio;
1128+ tasklet_hi_schedule(&engine->execlists.tasklet);
1129+}
1130+
10221131 static void submit_queue(struct intel_engine_cs *engine, int prio)
10231132 {
1024− if (prio > engine->execlists.queue_priority) {
1025− engine->execlists.queue_priority = prio;
1026− tasklet_hi_schedule(&engine->execlists.tasklet);
1027− }
1133+ if (prio > engine->execlists.queue_priority)
1134+ __submit_queue(engine, prio);
10281135 }
10291136
10301137 static void execlists_submit_request(struct i915_request *request)
@@ -1157,7 +1264,10 @@ static void execlists_schedule(struct i915_request *request, int prio) · 126 unmodified lines
11571264 __list_del_entry(&pt->link);
11581265 queue_request(engine, pt, prio);
11591266 }
1160− submit_queue(engine, prio);
1267+
1268+ if (prio > engine->execlists.queue_priority &&
1269+ i915_sw_fence_done(&pt_to_request(pt)->submit))
1270+ __submit_queue(engine, prio);
11611271 }
11621272
11631273 spin_unlock_irq(&engine->timeline->lock);
@@ -1224,6 +1334,7 @@ execlists_context_pin(struct intel_engine_cs *engine, · 60 unmodified lines
12241334 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
12251335 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
12261336 i915_ggtt_offset(ce->ring->vma);
1337+ ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head;
12271338
12281339 ce->state->obj->pin_global++;
12291340 i915_gem_context_get(ctx);
@@ -1574,14 +1685,6 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) · 344 unmodified lines
15741685 return ret;
15751686 }
15761687
1577−static u8 gtiir[] = {
1578− [RCS] = 0,
1579− [BCS] = 0,
1580− [VCS] = 1,
1581− [VCS2] = 1,
1582− [VECS] = 3,
1583−};
1584−
15851688 static void enable_execlists(struct intel_engine_cs *engine)
15861689 {
15871690 struct drm_i915_private *dev_priv = engine->i915;
@@ -1641,6 +1744,10 @@ static int gen8_init_render_ring(struct intel_engine_cs *engine) · 53 unmodified lines
16411744 if (ret)
16421745 return ret;
16431746
1747+ ret = intel_whitelist_workarounds_apply(engine);
1748+ if (ret)
1749+ return ret;
1750+
16441751 /* We need to disable the AsyncFlip performance optimisations in order
16451752 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
16461753 * programmed to '1' on all products.
@@ -1651,7 +1758,7 @@ static int gen8_init_render_ring(struct intel_engine_cs *engine) · 4 unmodified lines
16511758
16521759 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
16531760
1654− return init_workarounds_ring(engine);
1761+ return 0;
16551762 }
16561763
16571764 static int gen9_init_render_ring(struct intel_engine_cs *engine)
@@ -1662,32 +1769,11 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine) · 4 unmodified lines
16621769 if (ret)
16631770 return ret;
16641771
1665− return init_workarounds_ring(engine);
1666−}
1667−
1668−static void reset_irq(struct intel_engine_cs *engine)
1669−{
1670− struct drm_i915_private *dev_priv = engine->i915;
1671− int i;
1672−
1673− GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
1674−
1675− /*
1676− * Clear any pending interrupt state.
1677− *
1678− * We do it twice out of paranoia that some of the IIR are double
1679− * buffered, and if we only reset it once there may still be
1680− * an interrupt pending.
1681− */
1682− for (i = 0; i < 2; i++) {
1683− I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
1684− GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
1685− POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
1686− }
1687− GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
1688− (GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift));
1772+ ret = intel_whitelist_workarounds_apply(engine);
1773+ if (ret)
1774+ return ret;
16891775
1690− clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1776+ return 0;
16911777 }
16921778
16931779 static void reset_common_ring(struct intel_engine_cs *engine,
@@ -1697,14 +1783,13 @@ static void reset_common_ring(struct intel_engine_cs *engine, · 3 unmodified lines
16971783 struct intel_context *ce;
16981784 unsigned long flags;
16991785
1700− GEM_TRACE("%s seqno=%x\n",
1701− engine->name, request ? request->global_seqno : 0);
1786+ GEM_TRACE("%s request global=%x, current=%d\n",
1787+ engine->name, request ? request->global_seqno : 0,
1788+ intel_engine_get_seqno(engine));
17021789
17031790 /* See execlists_cancel_requests() for the irq/spinlock split. */
17041791 local_irq_save(flags);
17051792
1706− reset_irq(engine);
1707−
17081793 /*
17091794 * Catch up with any missed context-switch interrupts.
17101795 *
@@ -1715,15 +1800,13 @@ static void reset_common_ring(struct intel_engine_cs *engine, · 4 unmodified lines
17151800 * requests were completed.
17161801 */
17171802 execlists_cancel_port_requests(execlists);
1803+ reset_irq(engine);
17181804
17191805 /* Push back any incomplete requests for replay after the reset. */
17201806 spin_lock(&engine->timeline->lock);
17211807 __unwind_incomplete_requests(engine);
17221808 spin_unlock(&engine->timeline->lock);
17231809
1724− /* Mark all CS interrupts as complete */
1725− execlists->active = 0;
1726−
17271810 local_irq_restore(flags);
17281811
17291812 /*
@@ -2015,7 +2098,7 @@ static int gen8_init_rcs_context(struct i915_request *rq) · 285 unmodified lines
20152098 {
20162099 int ret;
20172100
2018− ret = intel_ring_workarounds_emit(rq);
2101+ ret = intel_ctx_workarounds_emit(rq);
20192102 if (ret)
20202103 return ret;
20212104
@@ -2075,11 +2158,13 @@ static void execlists_set_default_submission(struct intel_engine_cs *engine) · 53 unmodified lines
20752158 engine->unpark = NULL;
20762159
20772160 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
2161+ if (engine->i915->preempt_context)
2162+ engine->flags |= I915_ENGINE_HAS_PREEMPTION;
20782163
20792164 engine->i915->caps.scheduler =
20802165 I915_SCHEDULER_CAP_ENABLED |
20812166 I915_SCHEDULER_CAP_PRIORITY;
2082− if (engine->i915->preempt_context)
2167+ if (intel_engine_has_preemption(engine))
20832168 engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION;
20842169 }
20852170
@@ -2118,7 +2203,20 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) · 32 unmodified lines
21182203 static inline void
21192204 logical_ring_default_irqs(struct intel_engine_cs *engine)
21202205 {
2121− unsigned shift = engine->irq_shift;
2206+ unsigned int shift = 0;
2207+
2208+ if (INTEL_GEN(engine->i915) < 11) {
2209+ const u8 irq_shifts[] = {
2210+ [RCS] = GEN8_RCS_IRQ_SHIFT,
2211+ [BCS] = GEN8_BCS_IRQ_SHIFT,
2212+ [VCS] = GEN8_VCS1_IRQ_SHIFT,
2213+ [VCS2] = GEN8_VCS2_IRQ_SHIFT,
2214+ [VECS] = GEN8_VECS_IRQ_SHIFT,
2215+ };
2216+
2217+ shift = irq_shifts[engine->id];
2218+ }
2219+
21222220 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
21232221 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
21242222 }
@@ -2551,3 +2649,7 @@ void intel_lr_context_resume(struct drm_i915_private *dev_priv) · 426 unmodified lines
25512649 }
25522650 }
25532651 }
2652+
2653+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2654+#include "selftests/intel_lrc.c"
2655+#endif
drivers/gpu/drm/i915/intel_overlay.c+1−0
@@ -807,6 +807,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, · 806 unmodified lines
807807 ret = PTR_ERR(vma);
808808 goto out_pin_section;
809809 }
810+ intel_fb_obj_flush(new_bo, ORIGIN_DIRTYFB);
810811
811812 ret = i915_vma_put_fence(vma);
812813 if (ret)
drivers/gpu/drm/i915/intel_pipe_crc.c+46−7
@@ -569,7 +569,8 @@ unlock: · 568 unmodified lines
569569 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
570570 enum pipe pipe,
571571 enum intel_pipe_crc_source *source,
572− uint32_t *val)
572+ uint32_t *val,
573+ bool set_wa)
573574 {
574575 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
575576 *source = INTEL_PIPE_CRC_SOURCE_PF;
@@ -582,7 +583,7 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, · 6 unmodified lines
582583 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
583584 break;
584585 case INTEL_PIPE_CRC_SOURCE_PF:
585− if ((IS_HASWELL(dev_priv) ||
586+ if (set_wa && (IS_HASWELL(dev_priv) ||
586587 IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
587588 hsw_pipe_A_crc_wa(dev_priv, true);
588589
@@ -600,7 +601,8 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, · 11 unmodified lines
600601
601602 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
602603 enum pipe pipe,
603− enum intel_pipe_crc_source *source, u32 *val)
604+ enum intel_pipe_crc_source *source, u32 *val,
605+ bool set_wa)
604606 {
605607 if (IS_GEN2(dev_priv))
606608 return i8xx_pipe_crc_ctl_reg(source, val);
@@ -611,7 +613,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, · 4 unmodified lines
611613 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
612614 return ilk_pipe_crc_ctl_reg(source, val);
613615 else
614− return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
616+ return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa);
615617 }
616618
617619 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
@@ -636,7 +638,7 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv, · 18 unmodified lines
636638 return -EIO;
637639 }
638640
639− ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
641+ ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val, true);
640642 if (ret != 0)
641643 goto out;
642644
@@ -916,7 +918,7 @@ int intel_pipe_crc_create(struct drm_minor *minor) · 273 unmodified lines
916918 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
917919 size_t *values_cnt)
918920 {
919− struct drm_i915_private *dev_priv = crtc->dev->dev_private;
921+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
920922 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
921923 enum intel_display_power_domain power_domain;
922924 enum intel_pipe_crc_source source;
@@ -934,10 +936,11 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, · 11 unmodified lines
934936 return -EIO;
935937 }
936938
937− ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val);
939+ ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val, true);
938940 if (ret != 0)
939941 goto out;
940942
943+ pipe_crc->source = source;
941944 I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
942945 POSTING_READ(PIPE_CRC_CTL(crtc->index));
943946
@@ -959,3 +962,39 @@ out: · 15 unmodified lines
959962
960963 return ret;
961964 }
965+
966+void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc)
967+{
968+ struct drm_crtc *crtc = &intel_crtc->base;
969+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
970+ struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
971+ u32 val = 0;
972+
973+ if (!crtc->crc.opened)
974+ return;
975+
976+ if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val, false) < 0)
977+ return;
978+
979+ /* Don't need pipe_crc->lock here, IRQs are not generated. */
980+ pipe_crc->skipped = 0;
981+
982+ I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
983+ POSTING_READ(PIPE_CRC_CTL(crtc->index));
984+}
985+
986+void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc)
987+{
988+ struct drm_crtc *crtc = &intel_crtc->base;
989+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
990+ struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
991+
992+ /* Swallow crc's until we stop generating them. */
993+ spin_lock_irq(&pipe_crc->lock);
994+ pipe_crc->skipped = INT_MIN;
995+ spin_unlock_irq(&pipe_crc->lock);
996+
997+ I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
998+ POSTING_READ(PIPE_CRC_CTL(crtc->index));
999+ synchronize_irq(dev_priv->drm.irq);
1000+}
drivers/gpu/drm/i915/intel_pm.c+292−182
@@ -3825,6 +3825,44 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) · 3824 unmodified lines
38253825 entry->end += 1;
38263826 }
38273827
3828+static void
3829+skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
3830+ const enum pipe pipe,
3831+ const enum plane_id plane_id,
3832+ struct skl_ddb_allocation *ddb /* out */)
3833+{
3834+ u32 val, val2 = 0;
3835+ int fourcc, pixel_format;
3836+
3837+ /* Cursor doesn't support NV12/planar, so no extra calculation needed */
3838+ if (plane_id == PLANE_CURSOR) {
3839+ val = I915_READ(CUR_BUF_CFG(pipe));
3840+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3841+ return;
3842+ }
3843+
3844+ val = I915_READ(PLANE_CTL(pipe, plane_id));
3845+
3846+ /* No DDB allocated for disabled planes */
3847+ if (!(val & PLANE_CTL_ENABLE))
3848+ return;
3849+
3850+ pixel_format = val & PLANE_CTL_FORMAT_MASK;
3851+ fourcc = skl_format_to_fourcc(pixel_format,
3852+ val & PLANE_CTL_ORDER_RGBX,
3853+ val & PLANE_CTL_ALPHA_MASK);
3854+
3855+ val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3856+ val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
3857+
3858+ if (fourcc == DRM_FORMAT_NV12) {
3859+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
3860+ skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
3861+ } else {
3862+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3863+ }
3864+}
3865+
38283866 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
38293867 struct skl_ddb_allocation *ddb /* out */)
38303868 {
@@ -3841,16 +3879,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, · 10 unmodified lines
38413879 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
38423880 continue;
38433881
3844− for_each_plane_id_on_crtc(crtc, plane_id) {
3845− u32 val;
3846−
3847− if (plane_id != PLANE_CURSOR)
3848− val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3849− else
3850− val = I915_READ(CUR_BUF_CFG(pipe));
3851−
3852− skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3853− }
3882+ for_each_plane_id_on_crtc(crtc, plane_id)
3883+ skl_ddb_get_hw_plane_state(dev_priv, pipe,
3884+ plane_id, ddb);
38543885
38553886 intel_display_power_put(dev_priv, power_domain);
38563887 }
@@ -4009,9 +4040,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, · 152 unmodified lines
40094040 static unsigned int
40104041 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
40114042 const struct drm_plane_state *pstate,
4012− int y)
4043+ const int plane)
40134044 {
4014− struct intel_plane *plane = to_intel_plane(pstate->plane);
4045+ struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
40154046 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
40164047 uint32_t data_rate;
40174048 uint32_t width = 0, height = 0;
@@ -4025,9 +4056,9 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, · 7 unmodified lines
40254056 fb = pstate->fb;
40264057 format = fb->format->format;
40274058
4028− if (plane->id == PLANE_CURSOR)
4059+ if (intel_plane->id == PLANE_CURSOR)
40294060 return 0;
4030− if (y && format != DRM_FORMAT_NV12)
4061+ if (plane == 1 && format != DRM_FORMAT_NV12)
40314062 return 0;
40324063
40334064 /*
@@ -4038,19 +4069,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, · 4 unmodified lines
40384069 width = drm_rect_width(&intel_pstate->base.src) >> 16;
40394070 height = drm_rect_height(&intel_pstate->base.src) >> 16;
40404071
4041− /* for planar format */
4042− if (format == DRM_FORMAT_NV12) {
4043− if (y) /* y-plane data rate */
4044− data_rate = width * height *
4045− fb->format->cpp[0];
4046− else /* uv-plane data rate */
4047− data_rate = (width / 2) * (height / 2) *
4048− fb->format->cpp[1];
4049− } else {
4050− /* for packed formats */
4051− data_rate = width * height * fb->format->cpp[0];
4072+ /* UV plane does 1/2 pixel sub-sampling */
4073+ if (plane == 1 && format == DRM_FORMAT_NV12) {
4074+ width /= 2;
4075+ height /= 2;
40524076 }
40534077
4078+ data_rate = width * height * fb->format->cpp[plane];
4079+
40544080 down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
40554081
40564082 return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
@@ -4063,8 +4089,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, · 6 unmodified lines
40634089 */
40644090 static unsigned int
40654091 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
4066− unsigned *plane_data_rate,
4067− unsigned *plane_y_data_rate)
4092+ unsigned int *plane_data_rate,
4093+ unsigned int *uv_plane_data_rate)
40684094 {
40694095 struct drm_crtc_state *cstate = &intel_cstate->base;
40704096 struct drm_atomic_state *state = cstate->state;
@@ -4080,17 +4106,17 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate, · 9 unmodified lines
40804106 enum plane_id plane_id = to_intel_plane(plane)->id;
40814107 unsigned int rate;
40824108
4083− /* packed/uv */
4109+ /* packed/y */
40844110 rate = skl_plane_relative_data_rate(intel_cstate,
40854111 pstate, 0);
40864112 plane_data_rate[plane_id] = rate;
40874113
40884114 total_data_rate += rate;
40894115
4090− /* y-plane */
4116+ /* uv-plane */
40914117 rate = skl_plane_relative_data_rate(intel_cstate,
40924118 pstate, 1);
4093− plane_y_data_rate[plane_id] = rate;
4119+ uv_plane_data_rate[plane_id] = rate;
40944120
40954121 total_data_rate += rate;
40964122 }
@@ -4099,8 +4125,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate, · 2 unmodified lines
40994125 }
41004126
41014127 static uint16_t
4102−skl_ddb_min_alloc(const struct drm_plane_state *pstate,
4103− const int y)
4128+skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
41044129 {
41054130 struct drm_framebuffer *fb = pstate->fb;
41064131 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
@@ -4111,8 +4136,8 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, · 4 unmodified lines
41114136 if (WARN_ON(!fb))
41124137 return 0;
41134138
4114− /* For packed formats, no y-plane, return 0 */
4115− if (y && fb->format->format != DRM_FORMAT_NV12)
4139+ /* For packed formats, and uv-plane, return 0 */
4140+ if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
41164141 return 0;
41174142
41184143 /* For Non Y-tile return 8-blocks */
@@ -4131,15 +4156,12 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, · 12 unmodified lines
41314156 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
41324157
41334158 /* Halve UV plane width and height for NV12 */
4134− if (fb->format->format == DRM_FORMAT_NV12 && !y) {
4159+ if (plane == 1) {
41354160 src_w /= 2;
41364161 src_h /= 2;
41374162 }
41384163
4139− if (fb->format->format == DRM_FORMAT_NV12 && !y)
4140− plane_bpp = fb->format->cpp[1];
4141− else
4142− plane_bpp = fb->format->cpp[0];
4164+ plane_bpp = fb->format->cpp[plane];
41434165
41444166 if (drm_rotation_90_or_270(pstate->rotation)) {
41454167 switch (plane_bpp) {
@@ -4167,7 +4189,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, · 21 unmodified lines
41674189
41684190 static void
41694191 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
4170− uint16_t *minimum, uint16_t *y_minimum)
4192+ uint16_t *minimum, uint16_t *uv_minimum)
41714193 {
41724194 const struct drm_plane_state *pstate;
41734195 struct drm_plane *plane;
@@ -4182,7 +4204,7 @@ skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active, · 8 unmodified lines
41824204 continue;
41834205
41844206 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
4185− y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
4207+ uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
41864208 }
41874209
41884210 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
@@ -4200,17 +4222,17 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, · 11 unmodified lines
42004222 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
42014223 uint16_t alloc_size, start;
42024224 uint16_t minimum[I915_MAX_PLANES] = {};
4203− uint16_t y_minimum[I915_MAX_PLANES] = {};
4225+ uint16_t uv_minimum[I915_MAX_PLANES] = {};
42044226 unsigned int total_data_rate;
42054227 enum plane_id plane_id;
42064228 int num_active;
4207− unsigned plane_data_rate[I915_MAX_PLANES] = {};
4208− unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
4229+ unsigned int plane_data_rate[I915_MAX_PLANES] = {};
4230+ unsigned int uv_plane_data_rate[I915_MAX_PLANES] = {};
42094231 uint16_t total_min_blocks = 0;
42104232
42114233 /* Clear the partitioning for disabled planes. */
42124234 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4213− memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
4235+ memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
42144236
42154237 if (WARN_ON(!state))
42164238 return 0;
@@ -4225,7 +4247,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, · 8 unmodified lines
42254247 if (alloc_size == 0)
42264248 return 0;
42274249
4228− skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
4250+ skl_ddb_calc_min(cstate, num_active, minimum, uv_minimum);
42294251
42304252 /*
42314253 * 1. Allocate the mininum required blocks for each active plane
@@ -4235,7 +4257,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, · 3 unmodified lines
42354257
42364258 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
42374259 total_min_blocks += minimum[plane_id];
4238− total_min_blocks += y_minimum[plane_id];
4260+ total_min_blocks += uv_minimum[plane_id];
42394261 }
42404262
42414263 if (total_min_blocks > alloc_size) {
@@ -4257,14 +4279,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, · 15 unmodified lines
42574279 */
42584280 total_data_rate = skl_get_total_relative_data_rate(cstate,
42594281 plane_data_rate,
4260− plane_y_data_rate);
4282+ uv_plane_data_rate);
42614283 if (total_data_rate == 0)
42624284 return 0;
42634285
42644286 start = alloc->start;
42654287 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4266− unsigned int data_rate, y_data_rate;
4267− uint16_t plane_blocks, y_plane_blocks = 0;
4288+ unsigned int data_rate, uv_data_rate;
4289+ uint16_t plane_blocks, uv_plane_blocks;
42684290
42694291 if (plane_id == PLANE_CURSOR)
42704292 continue;
@@ -4288,21 +4310,20 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, · 17 unmodified lines
42884310
42894311 start += plane_blocks;
42904312
4291− /*
4292− * allocation for y_plane part of planar format:
4293− */
4294− y_data_rate = plane_y_data_rate[plane_id];
4313+ /* Allocate DDB for UV plane for planar format/NV12 */
4314+ uv_data_rate = uv_plane_data_rate[plane_id];
42954315
4296− y_plane_blocks = y_minimum[plane_id];
4297− y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
4298− total_data_rate);
4316+ uv_plane_blocks = uv_minimum[plane_id];
4317+ uv_plane_blocks += div_u64((uint64_t)alloc_size * uv_data_rate,
4318+ total_data_rate);
42994319
4300− if (y_data_rate) {
4301− ddb->y_plane[pipe][plane_id].start = start;
4302− ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
4320+ if (uv_data_rate) {
4321+ ddb->uv_plane[pipe][plane_id].start = start;
4322+ ddb->uv_plane[pipe][plane_id].end =
4323+ start + uv_plane_blocks;
43034324 }
43044325
4305− start += y_plane_blocks;
4326+ start += uv_plane_blocks;
43064327 }
43074328
43084329 return 0;
@@ -4398,7 +4419,7 @@ static int · 89 unmodified lines
43984419 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
43994420 struct intel_crtc_state *cstate,
44004421 const struct intel_plane_state *intel_pstate,
4401− struct skl_wm_params *wp)
4422+ struct skl_wm_params *wp, int plane_id)
44024423 {
44034424 struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
44044425 const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4411,6 +4432,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, · 6 unmodified lines
44114432 if (!intel_wm_plane_visible(cstate, intel_pstate))
44124433 return 0;
44134434
4435+ /* only NV12 format has two planes */
4436+ if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
4437+ DRM_DEBUG_KMS("Non NV12 format have single plane\n");
4438+ return -EINVAL;
4439+ }
4440+
44144441 wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
44154442 fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
44164443 fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4418,6 +4445,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, · 1 unmodified line
44184445 wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
44194446 wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
44204447 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4448+ wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
44214449
44224450 if (plane->id == PLANE_CURSOR) {
44234451 wp->width = intel_pstate->base.crtc_w;
@@ -4430,8 +4458,10 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, · 6 unmodified lines
44304458 wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
44314459 }
44324460
4433− wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
4434− fb->format->cpp[0];
4461+ if (plane_id == 1 && wp->is_planar)
4462+ wp->width /= 2;
4463+
4464+ wp->cpp = fb->format->cpp[plane_id];
44354465 wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
44364466 intel_pstate);
44374467
@@ -4499,9 +4529,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, · 61 unmodified lines
44994529 uint16_t ddb_allocation,
45004530 int level,
45014531 const struct skl_wm_params *wp,
4502− uint16_t *out_blocks, /* out */
4503− uint8_t *out_lines, /* out */
4504− bool *enabled /* out */)
4532+ const struct skl_wm_level *result_prev,
4533+ struct skl_wm_level *result /* out */)
45054534 {
45064535 const struct drm_plane_state *pstate = &intel_pstate->base;
45074536 uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4515,7 +4544,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, · 7 unmodified lines
45154544
45164545 if (latency == 0 ||
45174546 !intel_wm_plane_visible(cstate, intel_pstate)) {
4518− *enabled = false;
4547+ result->plane_en = false;
45194548 return 0;
45204549 }
45214550
@@ -4568,6 +4597,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, · 46 unmodified lines
45684597 } else {
45694598 res_blocks++;
45704599 }
4600+
4601+ /*
4602+ * Make sure result blocks for higher latency levels are atleast
4603+ * as high as level below the current level.
4604+ * Assumption in DDB algorithm optimization for special cases.
4605+ * Also covers Display WA #1125 for RC.
4606+ */
4607+ if (result_prev->plane_res_b > res_blocks)
4608+ res_blocks = result_prev->plane_res_b;
45714609 }
45724610
45734611 if (INTEL_GEN(dev_priv) >= 11) {
@@ -4596,7 +4634,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, · 22 unmodified lines
45964634 if ((level > 0 && res_lines > 31) ||
45974635 res_blocks >= ddb_allocation ||
45984636 min_disp_buf_needed >= ddb_allocation) {
4599− *enabled = false;
4637+ result->plane_en = false;
46004638
46014639 /*
46024640 * If there are no valid level 0 watermarks, then we can't
@@ -4615,10 +4653,21 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, · 12 unmodified lines
46154653 }
46164654 }
46174655
4656+ /*
4657+ * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
4658+ * disable wm level 1-7 on NV12 planes
4659+ */
4660+ if (wp->is_planar && level >= 1 &&
4661+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
4662+ IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
4663+ result->plane_en = false;
4664+ return 0;
4665+ }
4666+
46184667 /* The number of lines are ignored for the level 0 watermark. */
4619− *out_lines = level ? res_lines : 0;
4620− *out_blocks = res_blocks;
4621− *enabled = true;
4668+ result->plane_res_b = res_blocks;
4669+ result->plane_res_l = res_lines;
4670+ result->plane_en = true;
46224671
46234672 return 0;
46244673 }
@@ -4629,7 +4678,8 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv, · 4 unmodified lines
46294678 struct intel_crtc_state *cstate,
46304679 const struct intel_plane_state *intel_pstate,
46314680 const struct skl_wm_params *wm_params,
4632− struct skl_plane_wm *wm)
4681+ struct skl_plane_wm *wm,
4682+ int plane_id)
46334683 {
46344684 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
46354685 struct drm_plane *plane = intel_pstate->base.plane;
@@ -4637,15 +4687,26 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv, · 1 unmodified line
46374687 uint16_t ddb_blocks;
46384688 enum pipe pipe = intel_crtc->pipe;
46394689 int level, max_level = ilk_wm_max_level(dev_priv);
4690+ enum plane_id intel_plane_id = intel_plane->id;
46404691 int ret;
46414692
46424693 if (WARN_ON(!intel_pstate->base.fb))
46434694 return -EINVAL;
46444695
4645− ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
4696+ ddb_blocks = plane_id ?
4697+ skl_ddb_entry_size(&ddb->uv_plane[pipe][intel_plane_id]) :
4698+ skl_ddb_entry_size(&ddb->plane[pipe][intel_plane_id]);
46464699
46474700 for (level = 0; level <= max_level; level++) {
4648− struct skl_wm_level *result = &wm->wm[level];
4701+ struct skl_wm_level *result = plane_id ? &wm->uv_wm[level] :
4702+ &wm->wm[level];
4703+ struct skl_wm_level *result_prev;
4704+
4705+ if (level)
4706+ result_prev = plane_id ? &wm->uv_wm[level - 1] :
4707+ &wm->wm[level - 1];
4708+ else
4709+ result_prev = plane_id ? &wm->uv_wm[0] : &wm->wm[0];
46494710
46504711 ret = skl_compute_plane_wm(dev_priv,
46514712 cstate,
@@ -4653,13 +4714,15 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv, · 1 unmodified line
46534714 ddb_blocks,
46544715 level,
46554716 wm_params,
4656− &result->plane_res_b,
4657− &result->plane_res_l,
4658− &result->plane_en);
4717+ result_prev,
4718+ result);
46594719 if (ret)
46604720 return ret;
46614721 }
46624722
4723+ if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
4724+ wm->is_planar = true;
4725+
46634726 return 0;
46644727 }
46654728
@@ -4769,20 +4832,39 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, · 103 unmodified lines
47694832
47704833 wm = &pipe_wm->planes[plane_id];
47714834 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
4772− memset(&wm_params, 0, sizeof(struct skl_wm_params));
47734835
47744836 ret = skl_compute_plane_wm_params(dev_priv, cstate,
4775− intel_pstate, &wm_params);
4837+ intel_pstate, &wm_params, 0);
47764838 if (ret)
47774839 return ret;
47784840
47794841 ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
4780− intel_pstate, &wm_params, wm);
4842+ intel_pstate, &wm_params, wm, 0);
47814843 if (ret)
47824844 return ret;
4845+
47834846 skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
47844847 ddb_blocks, &wm->trans_wm);
4848+
4849+ /* uv plane watermarks must also be validated for NV12/Planar */
4850+ if (wm_params.is_planar) {
4851+ memset(&wm_params, 0, sizeof(struct skl_wm_params));
4852+ wm->is_planar = true;
4853+
4854+ ret = skl_compute_plane_wm_params(dev_priv, cstate,
4855+ intel_pstate,
4856+ &wm_params, 1);
4857+ if (ret)
4858+ return ret;
4859+
4860+ ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
4861+ intel_pstate, &wm_params,
4862+ wm, 1);
4863+ if (ret)
4864+ return ret;
4865+ }
47854866 }
4867+
47864868 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
47874869
47884870 return 0;
@@ -4833,10 +4915,21 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc, · 44 unmodified lines
48334915
48344916 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
48354917 &ddb->plane[pipe][plane_id]);
4836− if (INTEL_GEN(dev_priv) < 11)
4918+ if (INTEL_GEN(dev_priv) >= 11)
4919+ return skl_ddb_entry_write(dev_priv,
4920+ PLANE_BUF_CFG(pipe, plane_id),
4921+ &ddb->plane[pipe][plane_id]);
4922+ if (wm->is_planar) {
4923+ skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
4924+ &ddb->uv_plane[pipe][plane_id]);
48374925 skl_ddb_entry_write(dev_priv,
48384926 PLANE_NV12_BUF_CFG(pipe, plane_id),
4839− &ddb->y_plane[pipe][plane_id]);
4927+ &ddb->plane[pipe][plane_id]);
4928+ } else {
4929+ skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
4930+ &ddb->plane[pipe][plane_id]);
4931+ I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
4932+ }
48404933 }
48414934
48424935 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
@@ -4944,15 +5037,13 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate) · 101 unmodified lines
49445037 struct drm_plane *plane;
49455038 enum pipe pipe = intel_crtc->pipe;
49465039
4947− WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
4948−
49495040 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
49505041 enum plane_id plane_id = to_intel_plane(plane)->id;
49515042
49525043 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
49535044 &new_ddb->plane[pipe][plane_id]) &&
4954− skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
4955− &new_ddb->y_plane[pipe][plane_id]))
5045+ skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
5046+ &new_ddb->uv_plane[pipe][plane_id]))
49565047 continue;
49575048
49585049 plane_state = drm_atomic_get_plane_state(state, plane);
@@ -4966,69 +5057,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate) · 7 unmodified lines
49665057 static int
49675058 skl_compute_ddb(struct drm_atomic_state *state)
49685059 {
4969− struct drm_device *dev = state->dev;
4970− struct drm_i915_private *dev_priv = to_i915(dev);
5060+ const struct drm_i915_private *dev_priv = to_i915(state->dev);
49715061 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4972− struct intel_crtc *intel_crtc;
49735062 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4974− uint32_t realloc_pipes = pipes_modified(state);
4975− int ret;
4976−
4977− /*
4978− * If this is our first atomic update following hardware readout,
4979− * we can't trust the DDB that the BIOS programmed for us. Let's
4980− * pretend that all pipes switched active status so that we'll
4981− * ensure a full DDB recompute.
4982− */
4983− if (dev_priv->wm.distrust_bios_wm) {
4984− ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4985− state->acquire_ctx);
4986− if (ret)
4987− return ret;
4988−
4989− intel_state->active_pipe_changes = ~0;
4990−
4991− /*
4992− * We usually only initialize intel_state->active_crtcs if we
4993− * we're doing a modeset; make sure this field is always
4994− * initialized during the sanitization process that happens
4995− * on the first commit too.
4996− */
4997− if (!intel_state->modeset)
4998− intel_state->active_crtcs = dev_priv->active_crtcs;
4999− }
5000−
5001− /*
5002− * If the modeset changes which CRTC's are active, we need to
5003− * recompute the DDB allocation for *all* active pipes, even
5004− * those that weren't otherwise being modified in any way by this
5005− * atomic commit. Due to the shrinking of the per-pipe allocations
5006− * when new active CRTC's are added, it's possible for a pipe that
5007− * we were already using and aren't changing at all here to suddenly
5008− * become invalid if its DDB needs exceeds its new allocation.
5009− *
5010− * Note that if we wind up doing a full DDB recompute, we can't let
5011− * any other display updates race with this transaction, so we need
5012− * to grab the lock on *all* CRTC's.
5013− */
5014− if (intel_state->active_pipe_changes) {
5015− realloc_pipes = ~0;
5016− intel_state->wm_results.dirty_pipes = ~0;
5017− }
5063+ struct intel_crtc *crtc;
5064+ struct intel_crtc_state *cstate;
5065+ int ret, i;
50185066
5019− /*
5020− * We're not recomputing for the pipes not included in the commit, so
5021− * make sure we start with the current state.
5022− */
50235067 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
50245068
5025− for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
5026− struct intel_crtc_state *cstate;
5027−
5028− cstate = intel_atomic_get_crtc_state(state, intel_crtc);
5029− if (IS_ERR(cstate))
5030− return PTR_ERR(cstate);
5031−
5069+ for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
50325070 ret = skl_allocate_pipe_ddb(cstate, ddb);
50335071 if (ret)
50345072 return ret;
@@ -5042,12 +5080,12 @@ skl_compute_ddb(struct drm_atomic_state *state) · 7 unmodified lines
50425080 }
50435081
50445082 static void
5045−skl_copy_wm_for_pipe(struct skl_wm_values *dst,
5046− struct skl_wm_values *src,
5047− enum pipe pipe)
5083+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
5084+ struct skl_ddb_values *src,
5085+ enum pipe pipe)
50485086 {
5049− memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
5050− sizeof(dst->ddb.y_plane[pipe]));
5087+ memcpy(dst->ddb.uv_plane[pipe], src->ddb.uv_plane[pipe],
5088+ sizeof(dst->ddb.uv_plane[pipe]));
50515089 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
50525090 sizeof(dst->ddb.plane[pipe]));
50535091 }
@@ -5090,23 +5128,23 @@ skl_print_wm_changes(const struct drm_atomic_state *state) · 36 unmodified lines
50905128 }
50915129
50925130 static int
5093−skl_compute_wm(struct drm_atomic_state *state)
5131+skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
50945132 {
5095− struct drm_crtc *crtc;
5096− struct drm_crtc_state *cstate;
5097− struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5098− struct skl_wm_values *results = &intel_state->wm_results;
50995133 struct drm_device *dev = state->dev;
5100− struct skl_pipe_wm *pipe_wm;
5101− bool changed = false;
5134+ const struct drm_i915_private *dev_priv = to_i915(dev);
5135+ const struct drm_crtc *crtc;
5136+ const struct drm_crtc_state *cstate;
5137+ struct intel_crtc *intel_crtc;
5138+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5139+ uint32_t realloc_pipes = pipes_modified(state);
51025140 int ret, i;
51035141
51045142 /*
51055143 * When we distrust bios wm we always need to recompute to set the
51065144 * expected DDB allocations for each CRTC.
51075145 */
5108− if (to_i915(dev)->wm.distrust_bios_wm)
5109− changed = true;
5146+ if (dev_priv->wm.distrust_bios_wm)
5147+ (*changed) = true;
51105148
51115149 /*
51125150 * If this transaction isn't actually touching any CRTC's, don't
@@ -5117,14 +5155,86 @@ skl_compute_wm(struct drm_atomic_state *state) · 4 unmodified lines
51175155 * hold _all_ CRTC state mutexes.
51185156 */
51195157 for_each_new_crtc_in_state(state, crtc, cstate, i)
5120− changed = true;
5158+ (*changed) = true;
51215159
5122− if (!changed)
5160+ if (!*changed)
51235161 return 0;
51245162
5163+ /*
5164+ * If this is our first atomic update following hardware readout,
5165+ * we can't trust the DDB that the BIOS programmed for us. Let's
5166+ * pretend that all pipes switched active status so that we'll
5167+ * ensure a full DDB recompute.
5168+ */
5169+ if (dev_priv->wm.distrust_bios_wm) {
5170+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
5171+ state->acquire_ctx);
5172+ if (ret)
5173+ return ret;
5174+
5175+ intel_state->active_pipe_changes = ~0;
5176+
5177+ /*
5178+ * We usually only initialize intel_state->active_crtcs if we
5179+ * we're doing a modeset; make sure this field is always
5180+ * initialized during the sanitization process that happens
5181+ * on the first commit too.
5182+ */
5183+ if (!intel_state->modeset)
5184+ intel_state->active_crtcs = dev_priv->active_crtcs;
5185+ }
5186+
5187+ /*
5188+ * If the modeset changes which CRTC's are active, we need to
5189+ * recompute the DDB allocation for *all* active pipes, even
5190+ * those that weren't otherwise being modified in any way by this
5191+ * atomic commit. Due to the shrinking of the per-pipe allocations
5192+ * when new active CRTC's are added, it's possible for a pipe that
5193+ * we were already using and aren't changing at all here to suddenly
5194+ * become invalid if its DDB needs exceeds its new allocation.
5195+ *
5196+ * Note that if we wind up doing a full DDB recompute, we can't let
5197+ * any other display updates race with this transaction, so we need
5198+ * to grab the lock on *all* CRTC's.
5199+ */
5200+ if (intel_state->active_pipe_changes) {
5201+ realloc_pipes = ~0;
5202+ intel_state->wm_results.dirty_pipes = ~0;
5203+ }
5204+
5205+ /*
5206+ * We're not recomputing for the pipes not included in the commit, so
5207+ * make sure we start with the current state.
5208+ */
5209+ for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
5210+ struct intel_crtc_state *cstate;
5211+
5212+ cstate = intel_atomic_get_crtc_state(state, intel_crtc);
5213+ if (IS_ERR(cstate))
5214+ return PTR_ERR(cstate);
5215+ }
5216+
5217+ return 0;
5218+}
5219+
5220+static int
5221+skl_compute_wm(struct drm_atomic_state *state)
5222+{
5223+ struct drm_crtc *crtc;
5224+ struct drm_crtc_state *cstate;
5225+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5226+ struct skl_ddb_values *results = &intel_state->wm_results;
5227+ struct skl_pipe_wm *pipe_wm;
5228+ bool changed = false;
5229+ int ret, i;
5230+
51255231 /* Clear all dirty flags */
51265232 results->dirty_pipes = 0;
51275233
5234+ ret = skl_ddb_add_affected_pipes(state, &changed);
5235+ if (ret || !changed)
5236+ return ret;
5237+
51285238 ret = skl_compute_ddb(state);
51295239 if (ret)
51305240 return ret;
@@ -5197,8 +5307,8 @@ static void skl_initial_wm(struct intel_atomic_state *state, · 66 unmodified lines
51975307 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
51985308 struct drm_device *dev = intel_crtc->base.dev;
51995309 struct drm_i915_private *dev_priv = to_i915(dev);
5200− struct skl_wm_values *results = &state->wm_results;
5201− struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
5310+ struct skl_ddb_values *results = &state->wm_results;
5311+ struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
52025312 enum pipe pipe = intel_crtc->pipe;
52035313
52045314 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
@@ -5209,7 +5319,7 @@ static void skl_initial_wm(struct intel_atomic_state *state, · 4 unmodified lines
52095319 if (cstate->base.active_changed)
52105320 skl_atomic_update_crtc_wm(state, cstate);
52115321
5212− skl_copy_wm_for_pipe(hw_vals, results, pipe);
5322+ skl_copy_ddb_for_pipe(hw_vals, results, pipe);
52135323
52145324 mutex_unlock(&dev_priv->wm.wm_mutex);
52155325 }
@@ -5341,7 +5451,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc, · 125 unmodified lines
53415451 void skl_wm_get_hw_state(struct drm_device *dev)
53425452 {
53435453 struct drm_i915_private *dev_priv = to_i915(dev);
5344− struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
5454+ struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
53455455 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
53465456 struct drm_crtc *crtc;
53475457 struct intel_crtc *intel_crtc;
@@ -6572,7 +6682,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) · 1224 unmodified lines
65726682
65736683 rps->efficient_freq = rps->rp1_freq;
65746684 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
6575− IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6685+ IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
65766686 u32 ddcc_status = 0;
65776687
65786688 if (sandybridge_pcode_read(dev_priv,
@@ -6585,7 +6695,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) · 6 unmodified lines
65856695 rps->max_freq);
65866696 }
65876697
6588− if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6698+ if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
65896699 /* Store the frequency values in 16.66 MHZ units, which is
65906700 * the natural hardware unit for SKL
65916701 */
@@ -6890,15 +7000,18 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv) · 298 unmodified lines
68907000 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
68917001 {
68927002 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6893− int min_freq = 15;
7003+ const int min_freq = 15;
7004+ const int scaling_factor = 180;
68947005 unsigned int gpu_freq;
68957006 unsigned int max_ia_freq, min_ring_freq;
68967007 unsigned int max_gpu_freq, min_gpu_freq;
6897− int scaling_factor = 180;
68987008 struct cpufreq_policy *policy;
68997009
69007010 WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
69017011
7012+ if (rps->max_freq <= rps->min_freq)
7013+ return;
7014+
69027015 policy = cpufreq_cpu_get(0);
69037016 if (policy) {
69047017 max_ia_freq = policy->cpuinfo.max_freq;
@@ -6918,13 +7031,12 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) · 13 unmodified lines
69187031 /* convert DDR frequency from units of 266.6MHz to bandwidth */
69197032 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
69207033
6921− if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
7034+ min_gpu_freq = rps->min_freq;
7035+ max_gpu_freq = rps->max_freq;
7036+ if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
69227037 /* Convert GT frequency to 50 HZ units */
6923− min_gpu_freq = rps->min_freq / GEN9_FREQ_SCALER;
6924− max_gpu_freq = rps->max_freq / GEN9_FREQ_SCALER;
6925− } else {
6926− min_gpu_freq = rps->min_freq;
6927− max_gpu_freq = rps->max_freq;
7038+ min_gpu_freq /= GEN9_FREQ_SCALER;
7039+ max_gpu_freq /= GEN9_FREQ_SCALER;
69287040 }
69297041
69307042 /*
@@ -6933,10 +7045,10 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) · 2 unmodified lines
69337045 * the PCU should use as a reference to determine the ring frequency.
69347046 */
69357047 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
6936− int diff = max_gpu_freq - gpu_freq;
7048+ const int diff = max_gpu_freq - gpu_freq;
69377049 unsigned int ia_freq = 0, ring_freq = 0;
69387050
6939− if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
7051+ if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
69407052 /*
69417053 * ring_freq = 2 * GT. ring_freq is in 100MHz units
69427054 * No floor required for ring frequency on SKL.
@@ -8026,10 +8138,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) · 1083 unmodified lines
80268138 dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
80278139 intel_disable_gt_powersave(dev_priv);
80288140
8029− if (INTEL_GEN(dev_priv) < 11)
8030− gen6_reset_rps_interrupts(dev_priv);
8141+ if (INTEL_GEN(dev_priv) >= 11)
8142+ gen11_reset_rps_interrupts(dev_priv);
80318143 else
8032− WARN_ON_ONCE(1);
8144+ gen6_reset_rps_interrupts(dev_priv);
80338145 }
80348146
80358147 static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
@@ -8142,8 +8254,6 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv) · 106 unmodified lines
81428254 cherryview_enable_rps(dev_priv);
81438255 } else if (IS_VALLEYVIEW(dev_priv)) {
81448256 valleyview_enable_rps(dev_priv);
8145− } else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
8146− /* TODO */
81478257 } else if (INTEL_GEN(dev_priv) >= 9) {
81488258 gen9_enable_rps(dev_priv);
81498259 } else if (IS_BROADWELL(dev_priv)) {
drivers/gpu/drm/i915/intel_psr.c+169−158
@@ -93,7 +93,7 @@ static void psr_aux_io_power_put(struct intel_dp *intel_dp) · 92 unmodified lines
9393 intel_display_power_put(dev_priv, psr_aux_domain(intel_dp));
9494 }
9595
96−static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
96+static bool intel_dp_get_y_coord_required(struct intel_dp *intel_dp)
9797 {
9898 uint8_t psr_caps = 0;
9999
@@ -122,6 +122,18 @@ static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) · 22 unmodified lines
122122 return alpm_caps & DP_ALPM_CAP;
123123 }
124124
125+static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
126+{
127+ u8 val = 0;
128+
129+ if (drm_dp_dpcd_readb(&intel_dp->aux,
130+ DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
131+ val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
132+ else
133+ DRM_ERROR("Unable to get sink synchronization latency\n");
134+ return val;
135+}
136+
125137 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
126138 {
127139 struct drm_i915_private *dev_priv =
@@ -130,33 +142,36 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) · 2 unmodified lines
130142 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
131143 sizeof(intel_dp->psr_dpcd));
132144
133− if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
145+ if (intel_dp->psr_dpcd[0]) {
134146 dev_priv->psr.sink_support = true;
135147 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
136148 }
137149
138150 if (INTEL_GEN(dev_priv) >= 9 &&
139− (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
140− uint8_t frame_sync_cap;
151+ (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
152+ /*
153+ * All panels that supports PSR version 03h (PSR2 +
154+ * Y-coordinate) can handle Y-coordinates in VSC but we are
155+ * only sure that it is going to be used when required by the
156+ * panel. This way panel is capable to do selective update
157+ * without a aux frame sync.
158+ *
159+ * To support PSR version 02h and PSR version 03h without
160+ * Y-coordinate requirement panels we would need to enable
161+ * GTC first.
162+ */
163+ dev_priv->psr.sink_psr2_support =
164+ intel_dp_get_y_coord_required(intel_dp);
165+ DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
166+ ? "supported" : "not supported");
141167
142− dev_priv->psr.sink_support = true;
143− if (drm_dp_dpcd_readb(&intel_dp->aux,
144− DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
145− &frame_sync_cap) != 1)
146− frame_sync_cap = 0;
147− dev_priv->psr.aux_frame_sync = frame_sync_cap & DP_AUX_FRAME_SYNC_CAP;
148− /* PSR2 needs frame sync as well */
149− dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
150− DRM_DEBUG_KMS("PSR2 %s on sink",
151− dev_priv->psr.psr2_support ? "supported" : "not supported");
152−
153− if (dev_priv->psr.psr2_support) {
154− dev_priv->psr.y_cord_support =
155− intel_dp_get_y_cord_status(intel_dp);
168+ if (dev_priv->psr.sink_psr2_support) {
156169 dev_priv->psr.colorimetry_support =
157170 intel_dp_get_colorimetry_status(intel_dp);
158171 dev_priv->psr.alpm =
159172 intel_dp_get_alpm_status(intel_dp);
173+ dev_priv->psr.sink_sync_latency =
174+ intel_dp_get_sink_sync_latency(intel_dp);
160175 }
161176 }
162177 }
@@ -193,21 +208,17 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp, · 30 unmodified lines
193208 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
194209 struct edp_vsc_psr psr_vsc;
195210
196− if (dev_priv->psr.psr2_support) {
211+ if (dev_priv->psr.psr2_enabled) {
197212 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
198213 memset(&psr_vsc, 0, sizeof(psr_vsc));
199214 psr_vsc.sdp_header.HB0 = 0;
200215 psr_vsc.sdp_header.HB1 = 0x7;
201− if (dev_priv->psr.colorimetry_support &&
202− dev_priv->psr.y_cord_support) {
216+ if (dev_priv->psr.colorimetry_support) {
203217 psr_vsc.sdp_header.HB2 = 0x5;
204218 psr_vsc.sdp_header.HB3 = 0x13;
205− } else if (dev_priv->psr.y_cord_support) {
219+ } else {
206220 psr_vsc.sdp_header.HB2 = 0x4;
207221 psr_vsc.sdp_header.HB3 = 0xe;
208− } else {
209− psr_vsc.sdp_header.HB2 = 0x3;
210− psr_vsc.sdp_header.HB3 = 0xc;
211222 }
212223 } else {
213224 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
@@ -228,31 +239,12 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp) · 14 unmodified lines
228239 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
229240 }
230241
231−static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
232− enum port port)
233−{
234− if (INTEL_GEN(dev_priv) >= 9)
235− return DP_AUX_CH_CTL(port);
236− else
237− return EDP_PSR_AUX_CTL;
238−}
239−
240−static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
241− enum port port, int index)
242−{
243− if (INTEL_GEN(dev_priv) >= 9)
244− return DP_AUX_CH_DATA(port, index);
245− else
246− return EDP_PSR_AUX_DATA(index);
247−}
248−
249−static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
242+static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
250243 {
251244 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
252− struct drm_device *dev = dig_port->base.base.dev;
253− struct drm_i915_private *dev_priv = to_i915(dev);
254− uint32_t aux_clock_divider;
255− i915_reg_t aux_ctl_reg;
245+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
246+ u32 aux_clock_divider, aux_ctl;
247+ int i;
256248 static const uint8_t aux_msg[] = {
257249 [0] = DP_AUX_NATIVE_WRITE << 4,
258250 [1] = DP_SET_POWER >> 8,
@@ -260,41 +252,47 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) · 1 unmodified line
260252 [3] = 1 - 1,
261253 [4] = DP_SET_POWER_D0,
262254 };
263− enum port port = dig_port->base.port;
264− u32 aux_ctl;
265− int i;
255+ u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
256+ EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
257+ EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
258+ EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
266259
267260 BUILD_BUG_ON(sizeof(aux_msg) > 20);
261+ for (i = 0; i < sizeof(aux_msg); i += 4)
262+ I915_WRITE(EDP_PSR_AUX_DATA(i >> 2),
263+ intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
268264
269265 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
270266
271− /* Enable AUX frame sync at sink */
272− if (dev_priv->psr.aux_frame_sync)
273− drm_dp_dpcd_writeb(&intel_dp->aux,
274− DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
275− DP_AUX_FRAME_SYNC_ENABLE);
267+ /* Start with bits set for DDI_AUX_CTL register */
268+ aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
269+ aux_clock_divider);
270+
271+ /* Select only valid bits for SRD_AUX_CTL */
272+ aux_ctl &= psr_aux_mask;
273+ I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl);
274+}
275+
276+static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
277+{
278+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
279+ struct drm_device *dev = dig_port->base.base.dev;
280+ struct drm_i915_private *dev_priv = to_i915(dev);
281+ u8 dpcd_val = DP_PSR_ENABLE;
282+
276283 /* Enable ALPM at sink for psr2 */
277− if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
284+ if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
278285 drm_dp_dpcd_writeb(&intel_dp->aux,
279286 DP_RECEIVER_ALPM_CONFIG,
280287 DP_ALPM_ENABLE);
281− if (dev_priv->psr.link_standby)
282− drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
283− DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
284− else
285− drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
286− DP_PSR_ENABLE);
287−
288− aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
289288
290− /* Setup AUX registers */
291− for (i = 0; i < sizeof(aux_msg); i += 4)
292− I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
293− intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
289+ if (dev_priv->psr.psr2_enabled)
290+ dpcd_val |= DP_PSR_ENABLE_PSR2;
291+ if (dev_priv->psr.link_standby)
292+ dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
293+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
294294
295− aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
296− aux_clock_divider);
297− I915_WRITE(aux_ctl_reg, aux_ctl);
295+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
298296 }
299297
300298 static void vlv_psr_enable_source(struct intel_dp *intel_dp,
@@ -396,25 +394,17 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) · 95 unmodified lines
396394 * with the 5 or 6 idle patterns.
397395 */
398396 uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
399− uint32_t val;
400− uint8_t sink_latency;
401−
402− val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
397+ u32 val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
403398
404399 /* FIXME: selective update is probably totally broken because it doesn't
405400 * mesh at all with our frontbuffer tracking. And the hw alone isn't
406401 * good enough. */
407− val |= EDP_PSR2_ENABLE |
408− EDP_SU_TRACK_ENABLE;
409−
410− if (drm_dp_dpcd_readb(&intel_dp->aux,
411− DP_SYNCHRONIZATION_LATENCY_IN_SINK,
412− &sink_latency) == 1) {
413− sink_latency &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
414− } else {
415− sink_latency = 0;
402+ val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
403+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
404+ val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
416405 }
417− val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
406+
407+ val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
418408
419409 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
420410 val |= EDP_PSR2_TP2_TIME_2500;
@@ -440,7 +430,7 @@ static void hsw_psr_activate(struct intel_dp *intel_dp) · 19 unmodified lines
440430 */
441431
442432 /* psr1 and psr2 are mutually exclusive.*/
443− if (dev_priv->psr.psr2_support)
433+ if (dev_priv->psr.psr2_enabled)
444434 hsw_activate_psr2(intel_dp);
445435 else
446436 hsw_activate_psr1(intel_dp);
@@ -460,7 +450,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, · 13 unmodified lines
460450 * dynamically during PSR enable, and extracted from sink
461451 * caps during eDP detection.
462452 */
463− if (!dev_priv->psr.psr2_support)
453+ if (!dev_priv->psr.sink_psr2_support)
464454 return false;
465455
466456 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
@@ -478,15 +468,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, · 11 unmodified lines
478468 return false;
479469 }
480470
481− /*
482− * FIXME:enable psr2 only for y-cordinate psr2 panels
483− * After gtc implementation , remove this restriction.
484− */
485− if (!dev_priv->psr.y_cord_support) {
486− DRM_DEBUG_KMS("PSR2 not enabled, panel does not support Y coordinate\n");
487− return false;
488− }
489−
490471 return true;
491472 }
492473
@@ -568,7 +549,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp) · 75 unmodified lines
568549 struct drm_device *dev = intel_dig_port->base.base.dev;
569550 struct drm_i915_private *dev_priv = to_i915(dev);
570551
571− if (dev_priv->psr.psr2_support)
552+ if (dev_priv->psr.psr2_enabled)
572553 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
573554 else
574555 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
@@ -586,14 +567,24 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp, · 11 unmodified lines
586567 struct drm_device *dev = dig_port->base.base.dev;
587568 struct drm_i915_private *dev_priv = to_i915(dev);
588569 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
589− u32 chicken;
590570
591571 psr_aux_io_power_get(intel_dp);
592572
593− if (dev_priv->psr.psr2_support) {
594− chicken = PSR2_VSC_ENABLE_PROG_HEADER;
595− if (dev_priv->psr.y_cord_support)
596− chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
573+ /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
574+ * use hardcoded values PSR AUX transactions
575+ */
576+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
577+ hsw_psr_setup_aux(intel_dp);
578+
579+ if (dev_priv->psr.psr2_enabled) {
580+ u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
581+
582+ if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
583+ chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
584+ | PSR2_ADD_VERTICAL_LINE_COUNT);
585+
586+ else
587+ chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
597588 I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
598589
599590 I915_WRITE(EDP_PSR_DEBUG,
@@ -644,7 +635,7 @@ void intel_psr_enable(struct intel_dp *intel_dp, · 44 unmodified lines
644635 goto unlock;
645636 }
646637
647− dev_priv->psr.psr2_support = crtc_state->has_psr2;
638+ dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
648639 dev_priv->psr.busy_frontbuffer_bits = 0;
649640
650641 dev_priv->psr.setup_vsc(intel_dp, crtc_state);
@@ -714,12 +705,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp, · 63 unmodified lines
714705 i915_reg_t psr_status;
715706 u32 psr_status_mask;
716707
717− if (dev_priv->psr.aux_frame_sync)
718− drm_dp_dpcd_writeb(&intel_dp->aux,
719− DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
720− 0);
721−
722− if (dev_priv->psr.psr2_support) {
708+ if (dev_priv->psr.psr2_enabled) {
723709 psr_status = EDP_PSR2_STATUS;
724710 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
725711
@@ -743,7 +729,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp, · 17 unmodified lines
743729
744730 dev_priv->psr.active = false;
745731 } else {
746− if (dev_priv->psr.psr2_support)
732+ if (dev_priv->psr.psr2_enabled)
747733 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
748734 else
749735 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
@@ -789,53 +775,59 @@ void intel_psr_disable(struct intel_dp *intel_dp, · 39 unmodified lines
789775 cancel_delayed_work_sync(&dev_priv->psr.work);
790776 }
791777
792−static void intel_psr_work(struct work_struct *work)
778+static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
793779 {
794− struct drm_i915_private *dev_priv =
795− container_of(work, typeof(*dev_priv), psr.work.work);
796− struct intel_dp *intel_dp = dev_priv->psr.enabled;
797− struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
798− enum pipe pipe = to_intel_crtc(crtc)->pipe;
780+ struct intel_dp *intel_dp;
781+ i915_reg_t reg;
782+ u32 mask;
783+ int err;
784+
785+ intel_dp = dev_priv->psr.enabled;
786+ if (!intel_dp)
787+ return false;
799788
800− /* We have to make sure PSR is ready for re-enable
801− * otherwise it keeps disabled until next full enable/disable cycle.
802− * PSR might take some time to get fully disabled
803− * and be ready for re-enable.
804− */
805789 if (HAS_DDI(dev_priv)) {
806− if (dev_priv->psr.psr2_support) {
807− if (intel_wait_for_register(dev_priv,
808− EDP_PSR2_STATUS,
809− EDP_PSR2_STATUS_STATE_MASK,
810− 0,
811− 50)) {
812− DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n");
813− return;
814− }
790+ if (dev_priv->psr.psr2_enabled) {
791+ reg = EDP_PSR2_STATUS;
792+ mask = EDP_PSR2_STATUS_STATE_MASK;
815793 } else {
816− if (intel_wait_for_register(dev_priv,
817− EDP_PSR_STATUS,
818− EDP_PSR_STATUS_STATE_MASK,
819− 0,
820− 50)) {
821− DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
822− return;
823− }
794+ reg = EDP_PSR_STATUS;
795+ mask = EDP_PSR_STATUS_STATE_MASK;
824796 }
825797 } else {
826− if (intel_wait_for_register(dev_priv,
827− VLV_PSRSTAT(pipe),
828− VLV_EDP_PSR_IN_TRANS,
829− 0,
830− 1)) {
831− DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
832− return;
833− }
798+ struct drm_crtc *crtc =
799+ dp_to_dig_port(intel_dp)->base.base.crtc;
800+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
801+
802+ reg = VLV_PSRSTAT(pipe);
803+ mask = VLV_EDP_PSR_IN_TRANS;
834804 }
805+
806+ mutex_unlock(&dev_priv->psr.lock);
807+
808+ err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
809+ if (err)
810+ DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
811+
812+ /* After the unlocked wait, verify that PSR is still wanted! */
835813 mutex_lock(&dev_priv->psr.lock);
836− intel_dp = dev_priv->psr.enabled;
814+ return err == 0 && dev_priv->psr.enabled;
815+}
837816
838− if (!intel_dp)
817+static void intel_psr_work(struct work_struct *work)
818+{
819+ struct drm_i915_private *dev_priv =
820+ container_of(work, typeof(*dev_priv), psr.work.work);
821+
822+ mutex_lock(&dev_priv->psr.lock);
823+
824+ /*
825+ * We have to make sure PSR is ready for re-enable
826+ * otherwise it keeps disabled until next full enable/disable cycle.
827+ * PSR might take some time to get fully disabled
828+ * and be ready for re-enable.
829+ */
830+ if (!psr_wait_for_idle(dev_priv))
839831 goto unlock;
840832
841833 /*
@@ -846,7 +838,7 @@ static void intel_psr_work(struct work_struct *work) · 4 unmodified lines
846838 if (dev_priv->psr.busy_frontbuffer_bits)
847839 goto unlock;
848840
849− intel_psr_activate(intel_dp);
841+ intel_psr_activate(dev_priv->psr.enabled);
850842 unlock:
851843 mutex_unlock(&dev_priv->psr.lock);
852844 }
@@ -862,11 +854,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv) · 9 unmodified lines
862854 return;
863855
864856 if (HAS_DDI(dev_priv)) {
865− if (dev_priv->psr.aux_frame_sync)
866− drm_dp_dpcd_writeb(&intel_dp->aux,
867− DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
868− 0);
869− if (dev_priv->psr.psr2_support) {
857+ if (dev_priv->psr.psr2_enabled) {
870858 val = I915_READ(EDP_PSR2_CTL);
871859 WARN_ON(!(val & EDP_PSR2_ENABLE));
872860 I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
@@ -957,6 +945,7 @@ void intel_psr_single_frame_update(struct drm_i915_private *dev_priv, · 84 unmodified lines
957945 * intel_psr_invalidate - Invalidade PSR
958946 * @dev_priv: i915 device
959947 * @frontbuffer_bits: frontbuffer plane tracking bits
948+ * @origin: which operation caused the invalidate
960949 *
961950 * Since the hardware frontbuffer tracking has gaps we need to integrate
962951 * with the software frontbuffer tracking. This function gets called every
@@ -966,7 +955,7 @@ void intel_psr_single_frame_update(struct drm_i915_private *dev_priv, · 3 unmodified lines
966955 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
967956 */
968957 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
969− unsigned frontbuffer_bits)
958+ unsigned frontbuffer_bits, enum fb_op_origin origin)
970959 {
971960 struct drm_crtc *crtc;
972961 enum pipe pipe;
@@ -974,6 +963,9 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv, · 1 unmodified line
974963 if (!CAN_PSR(dev_priv))
975964 return;
976965
966+ if (dev_priv->psr.has_hw_tracking && origin == ORIGIN_FLIP)
967+ return;
968+
977969 mutex_lock(&dev_priv->psr.lock);
978970 if (!dev_priv->psr.enabled) {
979971 mutex_unlock(&dev_priv->psr.lock);
@@ -1014,6 +1006,9 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, · 34 unmodified lines
10141006 if (!CAN_PSR(dev_priv))
10151007 return;
10161008
1009+ if (dev_priv->psr.has_hw_tracking && origin == ORIGIN_FLIP)
1010+ return;
1011+
10171012 mutex_lock(&dev_priv->psr.lock);
10181013 if (!dev_priv->psr.enabled) {
10191014 mutex_unlock(&dev_priv->psr.lock);
@@ -1027,8 +1022,23 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, · 7 unmodified lines
10271022 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
10281023
10291024 /* By definition flush = invalidate + flush */
1030− if (frontbuffer_bits)
1031− intel_psr_exit(dev_priv);
1025+ if (frontbuffer_bits) {
1026+ if (dev_priv->psr.psr2_enabled ||
1027+ IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1028+ intel_psr_exit(dev_priv);
1029+ } else {
1030+ /*
1031+ * Display WA #0884: all
1032+ * This documented WA for bxt can be safely applied
1033+ * broadly so we can force HW tracking to exit PSR
1034+ * instead of disabling and re-enabling.
1035+ * Workaround tells us to write 0 to CUR_SURFLIVE_A,
1036+ * but it makes more sense write to the current active
1037+ * pipe.
1038+ */
1039+ I915_WRITE(CURSURFLIVE(pipe), 0);
1040+ }
1041+ }
10321042
10331043 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
10341044 if (!work_busy(&dev_priv->psr.work.work))
@@ -1090,6 +1100,7 @@ void intel_psr_init(struct drm_i915_private *dev_priv) · 55 unmodified lines
10901100 dev_priv->psr.activate = vlv_psr_activate;
10911101 dev_priv->psr.setup_vsc = vlv_psr_setup_vsc;
10921102 } else {
1103+ dev_priv->psr.has_hw_tracking = true;
10931104 dev_priv->psr.enable_source = hsw_psr_enable_source;
10941105 dev_priv->psr.disable_source = hsw_psr_disable;
10951106 dev_priv->psr.enable_sink = hsw_psr_enable_sink;
drivers/gpu/drm/i915/intel_ringbuffer.c+14−8
@@ -36,6 +36,7 @@ · 35 unmodified lines
3636 #include "i915_gem_render_state.h"
3737 #include "i915_trace.h"
3838 #include "intel_drv.h"
39+#include "intel_workarounds.h"
3940
4041 /* Rough estimate of the typical request size, performing a flush,
4142 * set-context and then emitting the batch.
@@ -599,7 +600,7 @@ static int intel_rcs_ctx_init(struct i915_request *rq) · 557 unmodified lines
599600 {
600601 int ret;
601602
602− ret = intel_ring_workarounds_emit(rq);
603+ ret = intel_ctx_workarounds_emit(rq);
603604 if (ret != 0)
604605 return ret;
605606
@@ -617,6 +618,10 @@ static int init_render_ring(struct intel_engine_cs *engine) · 11 unmodified lines
617618 if (ret)
618619 return ret;
619620
621+ ret = intel_whitelist_workarounds_apply(engine);
622+ if (ret)
623+ return ret;
624+
620625 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
621626 if (IS_GEN(dev_priv, 4, 6))
622627 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
@@ -658,7 +663,7 @@ static int init_render_ring(struct intel_engine_cs *engine) · 35 unmodified lines
658663 if (INTEL_GEN(dev_priv) >= 6)
659664 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
660665
661− return init_workarounds_ring(engine);
666+ return 0;
662667 }
663668
664669 static u32 *gen6_signal(struct i915_request *rq, u32 *cs)
@@ -1593,6 +1598,7 @@ static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes) · 928 unmodified lines
15931598 if (intel_ring_update_space(ring) >= bytes)
15941599 return 0;
15951600
1601+ GEM_BUG_ON(list_empty(&ring->request_list));
15961602 list_for_each_entry(target, &ring->request_list, ring_link) {
15971603 /* Would completion of this request free enough space? */
15981604 if (bytes <= __intel_ring_space(target->postfix,
@@ -1692,17 +1698,18 @@ u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords) · 93 unmodified lines
16921698 need_wrap &= ~1;
16931699 GEM_BUG_ON(need_wrap > ring->space);
16941700 GEM_BUG_ON(ring->emit + need_wrap > ring->size);
1701+ GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64)));
16951702
16961703 /* Fill the tail with MI_NOOP */
1697− memset(ring->vaddr + ring->emit, 0, need_wrap);
1698− ring->emit = 0;
1704+ memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64));
16991705 ring->space -= need_wrap;
1706+ ring->emit = 0;
17001707 }
17011708
17021709 GEM_BUG_ON(ring->emit > ring->size - bytes);
17031710 GEM_BUG_ON(ring->space < bytes);
17041711 cs = ring->vaddr + ring->emit;
1705− GEM_DEBUG_EXEC(memset(cs, POISON_INUSE, bytes));
1712+ GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs)));
17061713 ring->emit += bytes;
17071714 ring->space -= bytes;
17081715
@@ -1943,8 +1950,6 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, · 234 unmodified lines
19431950 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
19441951 struct intel_engine_cs *engine)
19451952 {
1946− engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
1947−
19481953 if (INTEL_GEN(dev_priv) >= 6) {
19491954 engine->irq_enable = gen6_irq_enable;
19501955 engine->irq_disable = gen6_irq_disable;
@@ -2029,6 +2034,8 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) · 78 unmodified lines
20292034 if (HAS_L3_DPF(dev_priv))
20302035 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
20312036
2037+ engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2038+
20322039 if (INTEL_GEN(dev_priv) >= 6) {
20332040 engine->init_context = intel_rcs_ctx_init;
20342041 engine->emit_flush = gen7_render_ring_flush;
@@ -2079,7 +2086,6 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) · 44 unmodified lines
20792086 engine->emit_flush = gen6_bsd_ring_flush;
20802087 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
20812088 } else {
2082− engine->mmio_base = BSD_RING_BASE;
20832089 engine->emit_flush = bsd_ring_flush;
20842090 if (IS_GEN5(dev_priv))
20852091 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
drivers/gpu/drm/i915/intel_ringbuffer.h+34−9
@@ -7,9 +7,11 @@ · 6 unmodified lines
77 #include "i915_gem_batch_pool.h"
88 #include "i915_gem_timeline.h"
99
10+#include "i915_reg.h"
1011 #include "i915_pmu.h"
1112 #include "i915_request.h"
1213 #include "i915_selftest.h"
14+#include "intel_gpu_commands.h"
1315
1416 struct drm_printer;
1517
@@ -84,7 +86,7 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a) · 68 unmodified lines
8486 }
8587
8688 #define I915_MAX_SLICES 3
87−#define I915_MAX_SUBSLICES 3
89+#define I915_MAX_SUBSLICES 8
8890
8991 #define instdone_slice_mask(dev_priv__) \
9092 (INTEL_GEN(dev_priv__) == 7 ? \
@@ -330,7 +332,6 @@ struct intel_engine_cs { · 239 unmodified lines
330332 u8 instance;
331333 u32 context_size;
332334 u32 mmio_base;
333− unsigned int irq_shift;
334335
335336 struct intel_ring *buffer;
336337 struct intel_timeline *timeline;
@@ -561,6 +562,7 @@ struct intel_engine_cs { · 224 unmodified lines
561562
562563 #define I915_ENGINE_NEEDS_CMD_PARSER BIT(0)
563564 #define I915_ENGINE_SUPPORTS_STATS BIT(1)
565+#define I915_ENGINE_HAS_PREEMPTION BIT(2)
564566 unsigned int flags;
565567
566568 /*
@@ -620,16 +622,29 @@ struct intel_engine_cs { · 53 unmodified lines
620622 } stats;
621623 };
622624
623−static inline bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine)
625+static inline bool
626+intel_engine_needs_cmd_parser(const struct intel_engine_cs *engine)
624627 {
625628 return engine->flags & I915_ENGINE_NEEDS_CMD_PARSER;
626629 }
627630
628−static inline bool intel_engine_supports_stats(struct intel_engine_cs *engine)
631+static inline bool
632+intel_engine_supports_stats(const struct intel_engine_cs *engine)
629633 {
630634 return engine->flags & I915_ENGINE_SUPPORTS_STATS;
631635 }
632636
637+static inline bool
638+intel_engine_has_preemption(const struct intel_engine_cs *engine)
639+{
640+ return engine->flags & I915_ENGINE_HAS_PREEMPTION;
641+}
642+
643+static inline bool __execlists_need_preempt(int prio, int last)
644+{
645+ return prio > max(0, last);
646+}
647+
633648 static inline void
634649 execlists_set_active(struct intel_engine_execlists *execlists,
635650 unsigned int bit)
@@ -637,6 +652,13 @@ execlists_set_active(struct intel_engine_execlists *execlists, · 1 unmodified line
637652 __set_bit(bit, (unsigned long *)&execlists->active);
638653 }
639654
655+static inline bool
656+execlists_set_active_once(struct intel_engine_execlists *execlists,
657+ unsigned int bit)
658+{
659+ return !__test_and_set_bit(bit, (unsigned long *)&execlists->active);
660+}
661+
640662 static inline void
641663 execlists_clear_active(struct intel_engine_execlists *execlists,
642664 unsigned int bit)
@@ -651,6 +673,10 @@ execlists_is_active(const struct intel_engine_execlists *execlists, · 8 unmodified lines
651673 return test_bit(bit, (unsigned long *)&execlists->active);
652674 }
653675
676+void execlists_user_begin(struct intel_engine_execlists *execlists,
677+ const struct execlist_port *port);
678+void execlists_user_end(struct intel_engine_execlists *execlists);
679+
654680 void
655681 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists);
656682
@@ -663,7 +689,7 @@ execlists_num_ports(const struct intel_engine_execlists * const execlists) · 6 unmodified lines
663689 return execlists->port_mask + 1;
664690 }
665691
666−static inline void
692+static inline struct execlist_port *
667693 execlists_port_complete(struct intel_engine_execlists * const execlists,
668694 struct execlist_port * const port)
669695 {
@@ -674,6 +700,8 @@ execlists_port_complete(struct intel_engine_execlists * const execlists, · 4 unmodified lines
674700
675701 memmove(port, port + 1, m * sizeof(struct execlist_port));
676702 memset(port + m, 0, sizeof(struct execlist_port));
703+
704+ return port;
677705 }
678706
679707 static inline unsigned int
@@ -857,9 +885,6 @@ static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine) · 177 unmodified lines
857885 return READ_ONCE(engine->timeline->seqno);
858886 }
859887
860−int init_workarounds_ring(struct intel_engine_cs *engine);
861−int intel_ring_workarounds_emit(struct i915_request *rq);
862−
863888 void intel_engine_get_instdone(struct intel_engine_cs *engine,
864889 struct intel_instdone *instdone);
865890
@@ -939,7 +964,7 @@ bool intel_engine_add_wait(struct intel_engine_cs *engine, · 73 unmodified lines
939964 struct intel_wait *wait);
940965 void intel_engine_remove_wait(struct intel_engine_cs *engine,
941966 struct intel_wait *wait);
942−void intel_engine_enable_signaling(struct i915_request *request, bool wakeup);
967+bool intel_engine_enable_signaling(struct i915_request *request, bool wakeup);
943968 void intel_engine_cancel_signaling(struct i915_request *request);
944969
945970 static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
drivers/gpu/drm/i915/intel_sprite.c+6−1
@@ -48,6 +48,7 @@ bool intel_format_is_yuv(u32 format) · 47 unmodified lines
4848 case DRM_FORMAT_UYVY:
4949 case DRM_FORMAT_VYUY:
5050 case DRM_FORMAT_YVYU:
51+ case DRM_FORMAT_NV12:
5152 return true;
5253 default:
5354 return false;
@@ -946,6 +947,7 @@ intel_check_sprite_plane(struct intel_plane *plane, · 892 unmodified lines
946947 int max_scale, min_scale;
947948 bool can_scale;
948949 int ret;
950+ uint32_t pixel_format = 0;
949951
950952 *src = drm_plane_state_src(&state->base);
951953 *dst = drm_plane_state_dest(&state->base);
@@ -969,11 +971,14 @@ intel_check_sprite_plane(struct intel_plane *plane, · 17 unmodified lines
969971
970972 /* setup can_scale, min_scale, max_scale */
971973 if (INTEL_GEN(dev_priv) >= 9) {
974+ if (state->base.fb)
975+ pixel_format = state->base.fb->format->format;
972976 /* use scaler when colorkey is not required */
973977 if (!state->ckey.flags) {
974978 can_scale = 1;
975979 min_scale = 1;
976− max_scale = skl_max_scale(crtc, crtc_state);
980+ max_scale =
981+ skl_max_scale(crtc, crtc_state, pixel_format);
977982 } else {
978983 can_scale = 0;
979984 min_scale = DRM_PLANE_HELPER_NO_SCALING;
drivers/gpu/drm/i915/intel_uc.c+66−66
@@ -69,13 +69,15 @@ static int __get_platform_enable_guc(struct drm_i915_private *dev_priv) · 68 unmodified lines
6969
7070 static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)
7171 {
72− int guc_log_level = 0; /* disabled */
72+ int guc_log_level;
7373
74− /* Enable if we're running on platform with GuC and debug config */
75− if (HAS_GUC(dev_priv) && intel_uc_is_using_guc() &&
76− (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
77− IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)))
78− guc_log_level = 1 + GUC_LOG_VERBOSITY_MAX;
74+ if (!HAS_GUC(dev_priv) || !intel_uc_is_using_guc())
75+ guc_log_level = GUC_LOG_LEVEL_DISABLED;
76+ else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
77+ IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
78+ guc_log_level = GUC_LOG_LEVEL_MAX;
79+ else
80+ guc_log_level = GUC_LOG_LEVEL_NON_VERBOSE;
7981
8082 /* Any platform specific fine-tuning can be done here */
8183
@@ -83,7 +85,7 @@ static int __get_default_guc_log_level(struct drm_i915_private *dev_priv) · 1 unmodified line
8385 }
8486
8587 /**
86− * intel_uc_sanitize_options - sanitize uC related modparam options
88+ * sanitize_options_early - sanitize uC related modparam options
8789 * @dev_priv: device private
8890 *
8991 * In case of "enable_guc" option this function will attempt to modify
@@ -99,7 +101,7 @@ static int __get_default_guc_log_level(struct drm_i915_private *dev_priv) · 9 unmodified lines
99101 * unless GuC is enabled on given platform and the driver is compiled with
100102 * debug config when this modparam will default to "enable(1..4)".
101103 */
102−void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
104+static void sanitize_options_early(struct drm_i915_private *dev_priv)
103105 {
104106 struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
105107 struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
@@ -142,51 +144,53 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) · 36 unmodified lines
142144 i915_modparams.guc_log_level = 0;
143145 }
144146
145− if (i915_modparams.guc_log_level > 1 + GUC_LOG_VERBOSITY_MAX) {
147+ if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) {
146148 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
147149 "guc_log_level", i915_modparams.guc_log_level,
148150 "verbosity too high");
149− i915_modparams.guc_log_level = 1 + GUC_LOG_VERBOSITY_MAX;
151+ i915_modparams.guc_log_level = GUC_LOG_LEVEL_MAX;
150152 }
151153
152− DRM_DEBUG_DRIVER("guc_log_level=%d (enabled:%s verbosity:%d)\n",
154+ DRM_DEBUG_DRIVER("guc_log_level=%d (enabled:%s, verbose:%s, verbosity:%d)\n",
153155 i915_modparams.guc_log_level,
154156 yesno(i915_modparams.guc_log_level),
155− i915_modparams.guc_log_level - 1);
157+ yesno(GUC_LOG_LEVEL_IS_VERBOSE(i915_modparams.guc_log_level)),
158+ GUC_LOG_LEVEL_TO_VERBOSITY(i915_modparams.guc_log_level));
156159
157160 /* Make sure that sanitization was done */
158161 GEM_BUG_ON(i915_modparams.enable_guc < 0);
159162 GEM_BUG_ON(i915_modparams.guc_log_level < 0);
160163 }
161164
162−void intel_uc_init_early(struct drm_i915_private *dev_priv)
165+void intel_uc_init_early(struct drm_i915_private *i915)
163166 {
164− intel_guc_init_early(&dev_priv->guc);
165− intel_huc_init_early(&dev_priv->huc);
166−}
167+ struct intel_guc *guc = &i915->guc;
168+ struct intel_huc *huc = &i915->huc;
167169
168−void intel_uc_init_fw(struct drm_i915_private *dev_priv)
169−{
170− if (!USES_GUC(dev_priv))
171− return;
170+ intel_guc_init_early(guc);
171+ intel_huc_init_early(huc);
172172
173− if (USES_HUC(dev_priv))
174− intel_uc_fw_fetch(dev_priv, &dev_priv->huc.fw);
173+ sanitize_options_early(i915);
175174
176− intel_uc_fw_fetch(dev_priv, &dev_priv->guc.fw);
175+ if (USES_GUC(i915))
176+ intel_uc_fw_fetch(i915, &guc->fw);
177+
178+ if (USES_HUC(i915))
179+ intel_uc_fw_fetch(i915, &huc->fw);
177180 }
178181
179−void intel_uc_fini_fw(struct drm_i915_private *dev_priv)
182+void intel_uc_cleanup_early(struct drm_i915_private *i915)
180183 {
181− if (!USES_GUC(dev_priv))
182− return;
184+ struct intel_guc *guc = &i915->guc;
185+ struct intel_huc *huc = &i915->huc;
183186
184− intel_uc_fw_fini(&dev_priv->guc.fw);
187+ if (USES_HUC(i915))
188+ intel_uc_fw_fini(&huc->fw);
185189
186− if (USES_HUC(dev_priv))
187− intel_uc_fw_fini(&dev_priv->huc.fw);
190+ if (USES_GUC(i915))
191+ intel_uc_fw_fini(&guc->fw);
188192
189− guc_free_load_err_log(&dev_priv->guc);
193+ guc_free_load_err_log(guc);
190194 }
191195
192196 /**
@@ -223,10 +227,13 @@ static int guc_enable_communication(struct intel_guc *guc) · 30 unmodified lines
223227 {
224228 struct drm_i915_private *dev_priv = guc_to_i915(guc);
225229
230+ gen9_enable_guc_interrupts(dev_priv);
231+
226232 if (HAS_GUC_CT(dev_priv))
227− return intel_guc_enable_ct(guc);
233+ return intel_guc_ct_enable(&guc->ct);
228234
229235 guc->send = intel_guc_send_mmio;
236+ guc->handler = intel_guc_to_host_event_handler_mmio;
230237 return 0;
231238 }
232239
@@ -235,9 +242,12 @@ static void guc_disable_communication(struct intel_guc *guc) · 2 unmodified lines
235242 struct drm_i915_private *dev_priv = guc_to_i915(guc);
236243
237244 if (HAS_GUC_CT(dev_priv))
238− intel_guc_disable_ct(guc);
245+ intel_guc_ct_disable(&guc->ct);
246+
247+ gen9_disable_guc_interrupts(dev_priv);
239248
240249 guc->send = intel_guc_send_nop;
250+ guc->handler = intel_guc_to_host_event_handler_nop;
241251 }
242252
243253 int intel_uc_init_misc(struct drm_i915_private *dev_priv)
@@ -248,24 +258,13 @@ int intel_uc_init_misc(struct drm_i915_private *dev_priv) · 4 unmodified lines
248258 if (!USES_GUC(dev_priv))
249259 return 0;
250260
251− ret = intel_guc_init_wq(guc);
252− if (ret) {
253− DRM_ERROR("Couldn't allocate workqueues for GuC\n");
254− goto err;
255− }
261+ intel_guc_init_ggtt_pin_bias(guc);
256262
257− ret = intel_guc_log_relay_create(guc);
258− if (ret) {
259− DRM_ERROR("Couldn't allocate relay for GuC log\n");
260− goto err_relay;
261− }
263+ ret = intel_guc_init_wq(guc);
264+ if (ret)
265+ return ret;
262266
263267 return 0;
264−
265−err_relay:
266− intel_guc_fini_wq(guc);
267−err:
268− return ret;
269268 }
270269
271270 void intel_uc_fini_misc(struct drm_i915_private *dev_priv)
@@ -276,8 +275,6 @@ void intel_uc_fini_misc(struct drm_i915_private *dev_priv) · 4 unmodified lines
276275 return;
277276
278277 intel_guc_fini_wq(guc);
279−
280− intel_guc_log_relay_destroy(guc);
281278 }
282279
283280 int intel_uc_init(struct drm_i915_private *dev_priv)
@@ -325,6 +322,24 @@ void intel_uc_fini(struct drm_i915_private *dev_priv) · 41 unmodified lines
325322 intel_guc_fini(guc);
326323 }
327324
325+void intel_uc_sanitize(struct drm_i915_private *i915)
326+{
327+ struct intel_guc *guc = &i915->guc;
328+ struct intel_huc *huc = &i915->huc;
329+
330+ if (!USES_GUC(i915))
331+ return;
332+
333+ GEM_BUG_ON(!HAS_GUC(i915));
334+
335+ guc_disable_communication(guc);
336+
337+ intel_huc_sanitize(huc);
338+ intel_guc_sanitize(guc);
339+
340+ __intel_uc_reset_hw(i915);
341+}
342+
328343 int intel_uc_init_hw(struct drm_i915_private *dev_priv)
329344 {
330345 struct intel_guc *guc = &dev_priv->guc;
@@ -336,14 +351,8 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) · 5 unmodified lines
336351
337352 GEM_BUG_ON(!HAS_GUC(dev_priv));
338353
339− guc_disable_communication(guc);
340354 gen9_reset_guc_interrupts(dev_priv);
341355
342− /* init WOPCM */
343− I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
344− I915_WRITE(DMA_GUC_WOPCM_OFFSET,
345− GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
346−
347356 /* WaEnableuKernelHeaderValidFix:skl */
348357 /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
349358 if (IS_GEN9(dev_priv))
@@ -390,12 +399,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) · 40 unmodified lines
390399 }
391400
392401 if (USES_GUC_SUBMISSION(dev_priv)) {
393− if (i915_modparams.guc_log_level)
394− gen9_enable_guc_interrupts(dev_priv);
395−
396402 ret = intel_guc_submission_enable(guc);
397403 if (ret)
398− goto err_interrupts;
404+ goto err_communication;
399405 }
400406
401407 dev_info(dev_priv->drm.dev, "GuC firmware version %u.%u\n",
@@ -410,8 +416,6 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) · 8 unmodified lines
410416 /*
411417 * We've failed to load the firmware :(
412418 */
413−err_interrupts:
414− gen9_disable_guc_interrupts(dev_priv);
415419 err_communication:
416420 guc_disable_communication(guc);
417421 err_log_capture:
@@ -441,9 +445,6 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv) · 23 unmodified lines
441445 intel_guc_submission_disable(guc);
442446
443447 guc_disable_communication(guc);
444−
445− if (USES_GUC_SUBMISSION(dev_priv))
446− gen9_disable_guc_interrupts(dev_priv);
447448 }
448449
449450 int intel_uc_suspend(struct drm_i915_private *i915)
@@ -479,8 +480,7 @@ int intel_uc_resume(struct drm_i915_private *i915) · 29 unmodified lines
479480 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
480481 return 0;
481482
482− if (i915_modparams.guc_log_level)
483− gen9_enable_guc_interrupts(i915);
483+ gen9_enable_guc_interrupts(i915);
484484
485485 err = intel_guc_resume(guc);
486486 if (err) {
drivers/gpu/drm/i915/intel_uc.h+2−3
@@ -28,13 +28,12 @@ · 27 unmodified lines
2828 #include "intel_huc.h"
2929 #include "i915_params.h"
3030
31−void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
3231 void intel_uc_init_early(struct drm_i915_private *dev_priv);
32+void intel_uc_cleanup_early(struct drm_i915_private *dev_priv);
3333 void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
34−void intel_uc_init_fw(struct drm_i915_private *dev_priv);
35−void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
3634 int intel_uc_init_misc(struct drm_i915_private *dev_priv);
3735 void intel_uc_fini_misc(struct drm_i915_private *dev_priv);
36+void intel_uc_sanitize(struct drm_i915_private *dev_priv);
3837 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
3938 void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
4039 int intel_uc_init(struct drm_i915_private *dev_priv);
drivers/gpu/drm/i915/intel_uc_fw.c+3−10
@@ -95,15 +95,6 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv, · 94 unmodified lines
9595 uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
9696 uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
9797
98− /* Header and uCode will be loaded to WOPCM */
99− size = uc_fw->header_size + uc_fw->ucode_size;
100− if (size > intel_guc_wopcm_size(dev_priv)) {
101− DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
102− intel_uc_fw_type_repr(uc_fw->type));
103− err = -E2BIG;
104− goto fail;
105− }
106−
10798 /* now RSA */
10899 if (css->key_size_dw != UOS_RSA_SCRATCH_COUNT) {
109100 DRM_WARN("%s: Mismatched firmware RSA key size (%u)\n",
@@ -209,6 +200,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, · 99 unmodified lines
209200 struct i915_vma *vma))
210201 {
211202 struct i915_vma *vma;
203+ u32 ggtt_pin_bias;
212204 int err;
213205
214206 DRM_DEBUG_DRIVER("%s fw load %s\n",
@@ -230,8 +222,9 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, · 15 unmodified lines
230222 goto fail;
231223 }
232224
225+ ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->guc.ggtt_pin_bias;
233226 vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
234− PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
227+ PIN_OFFSET_BIAS | ggtt_pin_bias);
235228 if (IS_ERR(vma)) {
236229 err = PTR_ERR(vma);
237230 DRM_DEBUG_DRIVER("%s fw ggtt-pin err=%d\n",
drivers/gpu/drm/i915/intel_uc_fw.h+22−0
@@ -115,6 +115,28 @@ static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw) · 114 unmodified lines
115115 return uc_fw->path != NULL;
116116 }
117117
118+static inline void intel_uc_fw_sanitize(struct intel_uc_fw *uc_fw)
119+{
120+ if (uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS)
121+ uc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
122+}
123+
124+/**
125+ * intel_uc_fw_get_upload_size() - Get size of firmware needed to be uploaded.
126+ * @uc_fw: uC firmware.
127+ *
128+ * Get the size of the firmware and header that will be uploaded to WOPCM.
129+ *
130+ * Return: Upload firmware size, or zero on firmware fetch failure.
131+ */
132+static inline u32 intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw)
133+{
134+ if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
135+ return 0;
136+
137+ return uc_fw->header_size + uc_fw->ucode_size;
138+}
139+
118140 void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
119141 struct intel_uc_fw *uc_fw);
120142 int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
drivers/gpu/drm/i915/intel_uncore.c+146−22
@@ -62,6 +62,11 @@ static inline void · 61 unmodified lines
6262 fw_domain_reset(struct drm_i915_private *i915,
6363 const struct intel_uncore_forcewake_domain *d)
6464 {
65+ /*
66+ * We don't really know if the powerwell for the forcewake domain we are
67+ * trying to reset here does exist at this point (engines could be fused
68+ * off in ICL+), so no waiting for acks
69+ */
6570 __raw_i915_write32(i915, d->reg_set, i915->uncore.fw_reset);
6671 }
6772
@@ -1353,6 +1358,23 @@ static void fw_domain_init(struct drm_i915_private *dev_priv, · 1285 unmodified lines
13531358 fw_domain_reset(dev_priv, d);
13541359 }
13551360
1361+static void fw_domain_fini(struct drm_i915_private *dev_priv,
1362+ enum forcewake_domain_id domain_id)
1363+{
1364+ struct intel_uncore_forcewake_domain *d;
1365+
1366+ if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1367+ return;
1368+
1369+ d = &dev_priv->uncore.fw_domain[domain_id];
1370+
1371+ WARN_ON(d->wake_count);
1372+ WARN_ON(hrtimer_cancel(&d->timer));
1373+ memset(d, 0, sizeof(*d));
1374+
1375+ dev_priv->uncore.fw_domains &= ~BIT(domain_id);
1376+}
1377+
13561378 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
13571379 {
13581380 if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
@@ -1565,6 +1587,40 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) · 206 unmodified lines
15651587 &dev_priv->uncore.pmic_bus_access_nb);
15661588 }
15671589
1590+/*
1591+ * We might have detected that some engines are fused off after we initialized
1592+ * the forcewake domains. Prune them, to make sure they only reference existing
1593+ * engines.
1594+ */
1595+void intel_uncore_prune(struct drm_i915_private *dev_priv)
1596+{
1597+ if (INTEL_GEN(dev_priv) >= 11) {
1598+ enum forcewake_domains fw_domains = dev_priv->uncore.fw_domains;
1599+ enum forcewake_domain_id domain_id;
1600+ int i;
1601+
1602+ for (i = 0; i < I915_MAX_VCS; i++) {
1603+ domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
1604+
1605+ if (HAS_ENGINE(dev_priv, _VCS(i)))
1606+ continue;
1607+
1608+ if (fw_domains & BIT(domain_id))
1609+ fw_domain_fini(dev_priv, domain_id);
1610+ }
1611+
1612+ for (i = 0; i < I915_MAX_VECS; i++) {
1613+ domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
1614+
1615+ if (HAS_ENGINE(dev_priv, _VECS(i)))
1616+ continue;
1617+
1618+ if (fw_domains & BIT(domain_id))
1619+ fw_domain_fini(dev_priv, domain_id);
1620+ }
1621+ }
1622+}
1623+
15681624 void intel_uncore_fini(struct drm_i915_private *dev_priv)
15691625 {
15701626 /* Paranoia: make sure we have disabled everything before we exit. */
@@ -1646,11 +1702,10 @@ static void gen3_stop_engine(struct intel_engine_cs *engine) · 75 unmodified lines
16461702 const i915_reg_t mode = RING_MI_MODE(base);
16471703
16481704 I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));
1649− if (intel_wait_for_register_fw(dev_priv,
1650− mode,
1651− MODE_IDLE,
1652− MODE_IDLE,
1653− 500))
1705+ if (__intel_wait_for_register_fw(dev_priv,
1706+ mode, MODE_IDLE, MODE_IDLE,
1707+ 500, 0,
1708+ NULL))
16541709 DRM_DEBUG_DRIVER("%s: timed out on STOP_RING\n",
16551710 engine->name);
16561711
@@ -1804,9 +1859,10 @@ static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, · 147 unmodified lines
18041859 __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
18051860
18061861 /* Wait for the device to ack the reset requests */
1807− err = intel_wait_for_register_fw(dev_priv,
1808− GEN6_GDRST, hw_domain_mask, 0,
1809− 500);
1862+ err = __intel_wait_for_register_fw(dev_priv,
1863+ GEN6_GDRST, hw_domain_mask, 0,
1864+ 500, 0,
1865+ NULL);
18101866 if (err)
18111867 DRM_DEBUG_DRIVER("Wait for 0x%08x engines reset failed\n",
18121868 hw_domain_mask);
@@ -1853,6 +1909,50 @@ static int gen6_reset_engines(struct drm_i915_private *dev_priv, · 40 unmodified lines
18531909 return gen6_hw_domain_reset(dev_priv, hw_mask);
18541910 }
18551911
1912+/**
1913+ * gen11_reset_engines - reset individual engines
1914+ * @dev_priv: i915 device
1915+ * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1916+ *
1917+ * This function will reset the individual engines that are set in engine_mask.
1918+ * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1919+ *
1920+ * Note: It is responsibility of the caller to handle the difference between
1921+ * asking full domain reset versus reset for all available individual engines.
1922+ *
1923+ * Returns 0 on success, nonzero on error.
1924+ */
1925+static int gen11_reset_engines(struct drm_i915_private *dev_priv,
1926+ unsigned engine_mask)
1927+{
1928+ struct intel_engine_cs *engine;
1929+ const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1930+ [RCS] = GEN11_GRDOM_RENDER,
1931+ [BCS] = GEN11_GRDOM_BLT,
1932+ [VCS] = GEN11_GRDOM_MEDIA,
1933+ [VCS2] = GEN11_GRDOM_MEDIA2,
1934+ [VCS3] = GEN11_GRDOM_MEDIA3,
1935+ [VCS4] = GEN11_GRDOM_MEDIA4,
1936+ [VECS] = GEN11_GRDOM_VECS,
1937+ [VECS2] = GEN11_GRDOM_VECS2,
1938+ };
1939+ u32 hw_mask;
1940+
1941+ BUILD_BUG_ON(VECS2 + 1 != I915_NUM_ENGINES);
1942+
1943+ if (engine_mask == ALL_ENGINES) {
1944+ hw_mask = GEN11_GRDOM_FULL;
1945+ } else {
1946+ unsigned int tmp;
1947+
1948+ hw_mask = 0;
1949+ for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1950+ hw_mask |= hw_engine_mask[engine->id];
1951+ }
1952+
1953+ return gen6_hw_domain_reset(dev_priv, hw_mask);
1954+}
1955+
18561956 /**
18571957 * __intel_wait_for_register_fw - wait until register matches expected state
18581958 * @dev_priv: the i915 device
@@ -1940,7 +2040,7 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv, · 81 unmodified lines
19402040 u32 reg_value;
19412041 int ret;
19422042
1943− might_sleep();
2043+ might_sleep_if(slow_timeout_ms);
19442044
19452045 spin_lock_irq(&dev_priv->uncore.lock);
19462046 intel_uncore_forcewake_get__locked(dev_priv, fw);
@@ -1952,7 +2052,7 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv, · 5 unmodified lines
19522052 intel_uncore_forcewake_put__locked(dev_priv, fw);
19532053 spin_unlock_irq(&dev_priv->uncore.lock);
19542054
1955− if (ret)
2055+ if (ret && slow_timeout_ms)
19562056 ret = __wait_for(reg_value = I915_READ_NOTRACE(reg),
19572057 (reg_value & mask) == value,
19582058 slow_timeout_ms * 1000, 10, 1000);
@@ -1971,11 +2071,12 @@ static int gen8_reset_engine_start(struct intel_engine_cs *engine) · 12 unmodified lines
19712071 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
19722072 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
19732073
1974− ret = intel_wait_for_register_fw(dev_priv,
1975− RING_RESET_CTL(engine->mmio_base),
1976− RESET_CTL_READY_TO_RESET,
1977− RESET_CTL_READY_TO_RESET,
1978− 700);
2074+ ret = __intel_wait_for_register_fw(dev_priv,
2075+ RING_RESET_CTL(engine->mmio_base),
2076+ RESET_CTL_READY_TO_RESET,
2077+ RESET_CTL_READY_TO_RESET,
2078+ 700, 0,
2079+ NULL);
19792080 if (ret)
19802081 DRM_ERROR("%s: reset request timeout\n", engine->name);
19812082
@@ -2000,7 +2101,10 @@ static int gen8_reset_engines(struct drm_i915_private *dev_priv, · 18 unmodified lines
20002101 if (gen8_reset_engine_start(engine))
20012102 goto not_ready;
20022103
2003− return gen6_reset_engines(dev_priv, engine_mask);
2104+ if (INTEL_GEN(dev_priv) >= 11)
2105+ return gen11_reset_engines(dev_priv, engine_mask);
2106+ else
2107+ return gen6_reset_engines(dev_priv, engine_mask);
20042108
20052109 not_ready:
20062110 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
@@ -2038,15 +2142,31 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) · 31 unmodified lines
20382142 int retry;
20392143 int ret;
20402144
2041− might_sleep();
2145+ /*
2146+ * We want to perform per-engine reset from atomic context (e.g.
2147+ * softirq), which imposes the constraint that we cannot sleep.
2148+ * However, experience suggests that spending a bit of time waiting
2149+ * for a reset helps in various cases, so for a full-device reset
2150+ * we apply the opposite rule and wait if we want to. As we should
2151+ * always follow up a failed per-engine reset with a full device reset,
2152+ * being a little faster, stricter and more error prone for the
2153+ * atomic case seems an acceptable compromise.
2154+ *
2155+ * Unfortunately this leads to a bimodal routine, when the goal was
2156+ * to have a single reset function that worked for resetting any
2157+ * number of engines simultaneously.
2158+ */
2159+ might_sleep_if(engine_mask == ALL_ENGINES);
20422160
2043− /* If the power well sleeps during the reset, the reset
2161+ /*
2162+ * If the power well sleeps during the reset, the reset
20442163 * request may be dropped and never completes (causing -EIO).
20452164 */
20462165 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20472166 for (retry = 0; retry < 3; retry++) {
20482167
2049− /* We stop engines, otherwise we might get failed reset and a
2168+ /*
2169+ * We stop engines, otherwise we might get failed reset and a
20502170 * dead gpu (on elk). Also as modern gpu as kbl can suffer
20512171 * from system hang if batchbuffer is progressing when
20522172 * the reset is issued, regardless of READY_TO_RESET ack.
@@ -2060,9 +2180,11 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) · 7 unmodified lines
20602180 i915_stop_engines(dev_priv, engine_mask);
20612181
20622182 ret = -ENODEV;
2063− if (reset)
2183+ if (reset) {
2184+ GEM_TRACE("engine_mask=%x\n", engine_mask);
20642185 ret = reset(dev_priv, engine_mask);
2065− if (ret != -ETIMEDOUT)
2186+ }
2187+ if (ret != -ETIMEDOUT || engine_mask != ALL_ENGINES)
20662188 break;
20672189
20682190 cond_resched();
@@ -2085,12 +2207,14 @@ bool intel_has_reset_engine(struct drm_i915_private *dev_priv) · 16 unmodified lines
20852207
20862208 int intel_reset_guc(struct drm_i915_private *dev_priv)
20872209 {
2210+ u32 guc_domain = INTEL_GEN(dev_priv) >= 11 ? GEN11_GRDOM_GUC :
2211+ GEN9_GRDOM_GUC;
20882212 int ret;
20892213
20902214 GEM_BUG_ON(!HAS_GUC(dev_priv));
20912215
20922216 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2093− ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
2217+ ret = gen6_hw_domain_reset(dev_priv, guc_domain);
20942218 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20952219
20962220 return ret;
drivers/gpu/drm/i915/intel_uncore.h+1−0
@@ -140,6 +140,7 @@ struct intel_uncore { · 139 unmodified lines
140140
141141 void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
142142 void intel_uncore_init(struct drm_i915_private *dev_priv);
143+void intel_uncore_prune(struct drm_i915_private *dev_priv);
143144 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
144145 bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
145146 void intel_uncore_fini(struct drm_i915_private *dev_priv);
drivers/gpu/drm/i915/intel_wopcm.c+275−0
@@ -0,0 +1,275 @@
1+/*
2+ * SPDX-License-Identifier: MIT
3+ *
4+ * Copyright © 2017-2018 Intel Corporation
5+ */
6+
7+#include "intel_wopcm.h"
8+#include "i915_drv.h"
9+
10+/**
11+ * DOC: WOPCM Layout
12+ *
13+ * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and
14+ * offset registers whose values are calculated and determined by HuC/GuC
15+ * firmware size and set of hardware requirements/restrictions as shown below:
16+ *
17+ * ::
18+ *
19+ * +=========> +====================+ <== WOPCM Top
20+ * ^ | HW contexts RSVD |
21+ * | +===> +====================+ <== GuC WOPCM Top
22+ * | ^ | |
23+ * | | | |
24+ * | | | |
25+ * | GuC | |
26+ * | WOPCM | |
27+ * | Size +--------------------+
28+ * WOPCM | | GuC FW RSVD |
29+ * | | +--------------------+
30+ * | | | GuC Stack RSVD |
31+ * | | +------------------- +
32+ * | v | GuC WOPCM RSVD |
33+ * | +===> +====================+ <== GuC WOPCM base
34+ * | | WOPCM RSVD |
35+ * | +------------------- + <== HuC Firmware Top
36+ * v | HuC FW |
37+ * +=========> +====================+ <== WOPCM Base
38+ *
39+ * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top.
40+ * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6
41+ * context).
42+ */
43+
44+/* Default WOPCM size 1MB. */
45+#define GEN9_WOPCM_SIZE (1024 * 1024)
46+/* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
47+#define WOPCM_RESERVED_SIZE (16 * 1024)
48+
49+/* 16KB reserved at the beginning of GuC WOPCM. */
50+#define GUC_WOPCM_RESERVED (16 * 1024)
51+/* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */
52+#define GUC_WOPCM_STACK_RESERVED (8 * 1024)
53+
54+/* GuC WOPCM Offset value needs to be aligned to 16KB. */
55+#define GUC_WOPCM_OFFSET_ALIGNMENT (1UL << GUC_WOPCM_OFFSET_SHIFT)
56+
57+/* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
58+#define BXT_WOPCM_RC6_CTX_RESERVED (24 * 1024)
59+/* 36KB WOPCM reserved at the end of WOPCM on CNL. */
60+#define CNL_WOPCM_HW_CTX_RESERVED (36 * 1024)
61+
62+/* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
63+#define GEN9_GUC_FW_RESERVED (128 * 1024)
64+#define GEN9_GUC_WOPCM_OFFSET (GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED)
65+
66+/**
67+ * intel_wopcm_init_early() - Early initialization of the WOPCM.
68+ * @wopcm: pointer to intel_wopcm.
69+ *
70+ * Setup the size of WOPCM which will be used by later on WOPCM partitioning.
71+ */
72+void intel_wopcm_init_early(struct intel_wopcm *wopcm)
73+{
74+ wopcm->size = GEN9_WOPCM_SIZE;
75+
76+ DRM_DEBUG_DRIVER("WOPCM size: %uKiB\n", wopcm->size / 1024);
77+}
78+
79+static inline u32 context_reserved_size(struct drm_i915_private *i915)
80+{
81+ if (IS_GEN9_LP(i915))
82+ return BXT_WOPCM_RC6_CTX_RESERVED;
83+ else if (INTEL_GEN(i915) >= 10)
84+ return CNL_WOPCM_HW_CTX_RESERVED;
85+ else
86+ return 0;
87+}
88+
89+static inline int gen9_check_dword_gap(u32 guc_wopcm_base, u32 guc_wopcm_size)
90+{
91+ u32 offset;
92+
93+ /*
94+ * GuC WOPCM size shall be at least a dword larger than the offset from
95+ * WOPCM base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET)
96+ * due to hardware limitation on Gen9.
97+ */
98+ offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET;
99+ if (offset > guc_wopcm_size ||
100+ (guc_wopcm_size - offset) < sizeof(u32)) {
101+ DRM_ERROR("GuC WOPCM size %uKiB is too small. %uKiB needed.\n",
102+ guc_wopcm_size / 1024,
103+ (u32)(offset + sizeof(u32)) / 1024);
104+ return -E2BIG;
105+ }
106+
107+ return 0;
108+}
109+
110+static inline int gen9_check_huc_fw_fits(u32 guc_wopcm_size, u32 huc_fw_size)
111+{
112+ /*
113+ * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
114+ * size to be larger than or equal to HuC firmware size. Otherwise,
115+ * firmware uploading would fail.
116+ */
117+ if (huc_fw_size > guc_wopcm_size - GUC_WOPCM_RESERVED) {
118+ DRM_ERROR("HuC FW (%uKiB) won't fit in GuC WOPCM (%uKiB).\n",
119+ huc_fw_size / 1024,
120+ (guc_wopcm_size - GUC_WOPCM_RESERVED) / 1024);
121+ return -E2BIG;
122+ }
123+
124+ return 0;
125+}
126+
127+static inline int check_hw_restriction(struct drm_i915_private *i915,
128+ u32 guc_wopcm_base, u32 guc_wopcm_size,
129+ u32 huc_fw_size)
130+{
131+ int err = 0;
132+
133+ if (IS_GEN9(i915))
134+ err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size);
135+
136+ if (!err &&
137+ (IS_GEN9(i915) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)))
138+ err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size);
139+
140+ return err;
141+}
142+
143+/**
144+ * intel_wopcm_init() - Initialize the WOPCM structure.
145+ * @wopcm: pointer to intel_wopcm.
146+ *
147+ * This function will partition WOPCM space based on GuC and HuC firmware sizes
148+ * and will allocate max remaining for use by GuC. This function will also
149+ * enforce platform dependent hardware restrictions on GuC WOPCM offset and
150+ * size. It will fail the WOPCM init if any of these checks were failed, so that
151+ * the following GuC firmware uploading would be aborted.
152+ *
153+ * Return: 0 on success, non-zero error code on failure.
154+ */
155+int intel_wopcm_init(struct intel_wopcm *wopcm)
156+{
157+ struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
158+ u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->guc.fw);
159+ u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw);
160+ u32 ctx_rsvd = context_reserved_size(i915);
161+ u32 guc_wopcm_base;
162+ u32 guc_wopcm_size;
163+ u32 guc_wopcm_rsvd;
164+ int err;
165+
166+ GEM_BUG_ON(!wopcm->size);
167+
168+ if (guc_fw_size >= wopcm->size) {
169+ DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
170+ guc_fw_size / 1024);
171+ return -E2BIG;
172+ }
173+
174+ if (huc_fw_size >= wopcm->size) {
175+ DRM_ERROR("HuC FW (%uKiB) is too big to fit in WOPCM.",
176+ huc_fw_size / 1024);
177+ return -E2BIG;
178+ }
179+
180+ guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
181+ GUC_WOPCM_OFFSET_ALIGNMENT);
182+ if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
183+ DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
184+ guc_wopcm_base / 1024);
185+ return -E2BIG;
186+ }
187+
188+ guc_wopcm_size = wopcm->size - guc_wopcm_base - ctx_rsvd;
189+ guc_wopcm_size &= GUC_WOPCM_SIZE_MASK;
190+
191+ DRM_DEBUG_DRIVER("Calculated GuC WOPCM Region: [%uKiB, %uKiB)\n",
192+ guc_wopcm_base / 1024, guc_wopcm_size / 1024);
193+
194+ guc_wopcm_rsvd = GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
195+ if ((guc_fw_size + guc_wopcm_rsvd) > guc_wopcm_size) {
196+ DRM_ERROR("Need %uKiB WOPCM for GuC, %uKiB available.\n",
197+ (guc_fw_size + guc_wopcm_rsvd) / 1024,
198+ guc_wopcm_size / 1024);
199+ return -E2BIG;
200+ }
201+
202+ err = check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size,
203+ huc_fw_size);
204+ if (err)
205+ return err;
206+
207+ wopcm->guc.base = guc_wopcm_base;
208+ wopcm->guc.size = guc_wopcm_size;
209+
210+ return 0;
211+}
212+
213+static inline int write_and_verify(struct drm_i915_private *dev_priv,
214+ i915_reg_t reg, u32 val, u32 mask,
215+ u32 locked_bit)
216+{
217+ u32 reg_val;
218+
219+ GEM_BUG_ON(val & ~mask);
220+
221+ I915_WRITE(reg, val);
222+
223+ reg_val = I915_READ(reg);
224+
225+ return (reg_val & mask) != (val | locked_bit) ? -EIO : 0;
226+}
227+
228+/**
229+ * intel_wopcm_init_hw() - Setup GuC WOPCM registers.
230+ * @wopcm: pointer to intel_wopcm.
231+ *
232+ * Setup the GuC WOPCM size and offset registers with the calculated values. It
233+ * will verify the register values to make sure the registers are locked with
234+ * correct values.
235+ *
236+ * Return: 0 on success. -EIO if registers were locked with incorrect values.
237+ */
238+int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
239+{
240+ struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm);
241+ u32 huc_agent;
242+ u32 mask;
243+ int err;
244+
245+ if (!USES_GUC(dev_priv))
246+ return 0;
247+
248+ GEM_BUG_ON(!HAS_GUC(dev_priv));
249+ GEM_BUG_ON(!wopcm->guc.size);
250+ GEM_BUG_ON(!wopcm->guc.base);
251+
252+ err = write_and_verify(dev_priv, GUC_WOPCM_SIZE, wopcm->guc.size,
253+ GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED,
254+ GUC_WOPCM_SIZE_LOCKED);
255+ if (err)
256+ goto err_out;
257+
258+ huc_agent = USES_HUC(dev_priv) ? HUC_LOADING_AGENT_GUC : 0;
259+ mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
260+ err = write_and_verify(dev_priv, DMA_GUC_WOPCM_OFFSET,
261+ wopcm->guc.base | huc_agent, mask,
262+ GUC_WOPCM_OFFSET_VALID);
263+ if (err)
264+ goto err_out;
265+
266+ return 0;
267+
268+err_out:
269+ DRM_ERROR("Failed to init WOPCM registers:\n");
270+ DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n",
271+ I915_READ(DMA_GUC_WOPCM_OFFSET));
272+ DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE));
273+
274+ return err;
275+}
drivers/gpu/drm/i915/intel_wopcm.h+31−0
@@ -0,0 +1,31 @@
1+/*
2+ * SPDX-License-Identifier: MIT
3+ *
4+ * Copyright © 2017-2018 Intel Corporation
5+ */
6+
7+#ifndef _INTEL_WOPCM_H_
8+#define _INTEL_WOPCM_H_
9+
10+#include <linux/types.h>
11+
12+/**
13+ * struct intel_wopcm - Overall WOPCM info and WOPCM regions.
14+ * @size: Size of overall WOPCM.
15+ * @guc: GuC WOPCM Region info.
16+ * @guc.base: GuC WOPCM base which is offset from WOPCM base.
17+ * @guc.size: Size of the GuC WOPCM region.
18+ */
19+struct intel_wopcm {
20+ u32 size;
21+ struct {
22+ u32 base;
23+ u32 size;
24+ } guc;
25+};
26+
27+void intel_wopcm_init_early(struct intel_wopcm *wopcm);
28+int intel_wopcm_init(struct intel_wopcm *wopcm);
29+int intel_wopcm_init_hw(struct intel_wopcm *wopcm);
30+
31+#endif
drivers/gpu/drm/i915/intel_workarounds.c+856−0
@@ -0,0 +1,856 @@
1+/*
2+ * SPDX-License-Identifier: MIT
3+ *
4+ * Copyright © 2014-2018 Intel Corporation
5+ */
6+
7+#include "i915_drv.h"
8+#include "intel_workarounds.h"
9+
10+/**
11+ * DOC: Hardware workarounds
12+ *
13+ * This file is intended as a central place to implement most [1]_ of the
14+ * required workarounds for hardware to work as originally intended. They fall
15+ * in five basic categories depending on how/when they are applied:
16+ *
17+ * - Workarounds that touch registers that are saved/restored to/from the HW
18+ * context image. The list is emitted (via Load Register Immediate commands)
19+ * everytime a new context is created.
20+ * - GT workarounds. The list of these WAs is applied whenever these registers
21+ * revert to default values (on GPU reset, suspend/resume [2]_, etc..).
22+ * - Display workarounds. The list is applied during display clock-gating
23+ * initialization.
24+ * - Workarounds that whitelist a privileged register, so that UMDs can manage
25+ * them directly. This is just a special case of a MMMIO workaround (as we
26+ * write the list of these to/be-whitelisted registers to some special HW
27+ * registers).
28+ * - Workaround batchbuffers, that get executed automatically by the hardware
29+ * on every HW context restore.
30+ *
31+ * .. [1] Please notice that there are other WAs that, due to their nature,
32+ * cannot be applied from a central place. Those are peppered around the rest
33+ * of the code, as needed.
34+ *
35+ * .. [2] Technically, some registers are powercontext saved & restored, so they
36+ * survive a suspend/resume. In practice, writing them again is not too
37+ * costly and simplifies things. We can revisit this in the future.
38+ *
39+ * Layout
40+ * ''''''
41+ *
42+ * Keep things in this file ordered by WA type, as per the above (context, GT,
43+ * display, register whitelist, batchbuffer). Then, inside each type, keep the
44+ * following order:
45+ *
46+ * - Infrastructure functions and macros
47+ * - WAs per platform in standard gen/chrono order
48+ * - Public functions to init or apply the given workaround type.
49+ */
50+
51+static int wa_add(struct drm_i915_private *dev_priv,
52+ i915_reg_t addr,
53+ const u32 mask, const u32 val)
54+{
55+ const unsigned int idx = dev_priv->workarounds.count;
56+
57+ if (WARN_ON(idx >= I915_MAX_WA_REGS))
58+ return -ENOSPC;
59+
60+ dev_priv->workarounds.reg[idx].addr = addr;
61+ dev_priv->workarounds.reg[idx].value = val;
62+ dev_priv->workarounds.reg[idx].mask = mask;
63+
64+ dev_priv->workarounds.count++;
65+
66+ return 0;
67+}
68+
69+#define WA_REG(addr, mask, val) do { \
70+ const int r = wa_add(dev_priv, (addr), (mask), (val)); \
71+ if (r) \
72+ return r; \
73+ } while (0)
74+
75+#define WA_SET_BIT_MASKED(addr, mask) \
76+ WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
77+
78+#define WA_CLR_BIT_MASKED(addr, mask) \
79+ WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
80+
81+#define WA_SET_FIELD_MASKED(addr, mask, value) \
82+ WA_REG(addr, (mask), _MASKED_FIELD(mask, value))
83+
84+static int gen8_ctx_workarounds_init(struct drm_i915_private *dev_priv)
85+{
86+ WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
87+
88+ /* WaDisableAsyncFlipPerfMode:bdw,chv */
89+ WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
90+
91+ /* WaDisablePartialInstShootdown:bdw,chv */
92+ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
93+ PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
94+
95+ /* Use Force Non-Coherent whenever executing a 3D context. This is a
96+ * workaround for for a possible hang in the unlikely event a TLB
97+ * invalidation occurs during a PSD flush.
98+ */
99+ /* WaForceEnableNonCoherent:bdw,chv */
100+ /* WaHdcDisableFetchWhenMasked:bdw,chv */
101+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
102+ HDC_DONOT_FETCH_MEM_WHEN_MASKED |
103+ HDC_FORCE_NON_COHERENT);
104+
105+ /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
106+ * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
107+ * polygons in the same 8x4 pixel/sample area to be processed without
108+ * stalling waiting for the earlier ones to write to Hierarchical Z
109+ * buffer."
110+ *
111+ * This optimization is off by default for BDW and CHV; turn it on.
112+ */
113+ WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
114+
115+ /* Wa4x4STCOptimizationDisable:bdw,chv */
116+ WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
117+
118+ /*
119+ * BSpec recommends 8x4 when MSAA is used,
120+ * however in practice 16x4 seems fastest.
121+ *
122+ * Note that PS/WM thread counts depend on the WIZ hashing
123+ * disable bit, which we don't touch here, but it's good
124+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
125+ */
126+ WA_SET_FIELD_MASKED(GEN7_GT_MODE,
127+ GEN6_WIZ_HASHING_MASK,
128+ GEN6_WIZ_HASHING_16x4);
129+
130+ return 0;
131+}
132+
133+static int bdw_ctx_workarounds_init(struct drm_i915_private *dev_priv)
134+{
135+ int ret;
136+
137+ ret = gen8_ctx_workarounds_init(dev_priv);
138+ if (ret)
139+ return ret;
140+
141+ /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
142+ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
143+
144+ /* WaDisableDopClockGating:bdw
145+ *
146+ * Also see the related UCGTCL1 write in broadwell_init_clock_gating()
147+ * to disable EUTC clock gating.
148+ */
149+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
150+ DOP_CLOCK_GATING_DISABLE);
151+
152+ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
153+ GEN8_SAMPLER_POWER_BYPASS_DIS);
154+
155+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
156+ /* WaForceContextSaveRestoreNonCoherent:bdw */
157+ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
158+ /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
159+ (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
160+
161+ return 0;
162+}
163+
164+static int chv_ctx_workarounds_init(struct drm_i915_private *dev_priv)
165+{
166+ int ret;
167+
168+ ret = gen8_ctx_workarounds_init(dev_priv);
169+ if (ret)
170+ return ret;
171+
172+ /* WaDisableThreadStallDopClockGating:chv */
173+ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
174+
175+ /* Improve HiZ throughput on CHV. */
176+ WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
177+
178+ return 0;
179+}
180+
181+static int gen9_ctx_workarounds_init(struct drm_i915_private *dev_priv)
182+{
183+ if (HAS_LLC(dev_priv)) {
184+ /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
185+ *
186+ * Must match Display Engine. See
187+ * WaCompressedResourceDisplayNewHashMode.
188+ */
189+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
190+ GEN9_PBE_COMPRESSED_HASH_SELECTION);
191+ WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
192+ GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
193+ }
194+
195+ /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
196+ /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
197+ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
198+ FLOW_CONTROL_ENABLE |
199+ PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
200+
201+ /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
202+ if (!IS_COFFEELAKE(dev_priv))
203+ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
204+ GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
205+
206+ /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
207+ /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
208+ WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
209+ GEN9_ENABLE_YV12_BUGFIX |
210+ GEN9_ENABLE_GPGPU_PREEMPTION);
211+
212+ /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
213+ /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
214+ WA_SET_BIT_MASKED(CACHE_MODE_1,
215+ GEN8_4x4_STC_OPTIMIZATION_DISABLE |
216+ GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
217+
218+ /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
219+ WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
220+ GEN9_CCS_TLB_PREFETCH_ENABLE);
221+
222+ /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
223+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
224+ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
225+ HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
226+
227+ /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
228+ * both tied to WaForceContextSaveRestoreNonCoherent
229+ * in some hsds for skl. We keep the tie for all gen9. The
230+ * documentation is a bit hazy and so we want to get common behaviour,
231+ * even though there is no clear evidence we would need both on kbl/bxt.
232+ * This area has been source of system hangs so we play it safe
233+ * and mimic the skl regardless of what bspec says.
234+ *
235+ * Use Force Non-Coherent whenever executing a 3D context. This
236+ * is a workaround for a possible hang in the unlikely event
237+ * a TLB invalidation occurs during a PSD flush.
238+ */
239+
240+ /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
241+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
242+ HDC_FORCE_NON_COHERENT);
243+
244+ /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
245+ if (IS_SKYLAKE(dev_priv) ||
246+ IS_KABYLAKE(dev_priv) ||
247+ IS_COFFEELAKE(dev_priv))
248+ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
249+ GEN8_SAMPLER_POWER_BYPASS_DIS);
250+
251+ /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
252+ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
253+
254+ /*
255+ * Supporting preemption with fine-granularity requires changes in the
256+ * batch buffer programming. Since we can't break old userspace, we
257+ * need to set our default preemption level to safe value. Userspace is
258+ * still able to use more fine-grained preemption levels, since in
259+ * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
260+ * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
261+ * not real HW workarounds, but merely a way to start using preemption
262+ * while maintaining old contract with userspace.
263+ */
264+
265+ /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
266+ WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
267+
268+ /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
269+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
270+ GEN9_PREEMPT_GPGPU_LEVEL_MASK,
271+ GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
272+
273+ return 0;
274+}
275+
276+static int skl_tune_iz_hashing(struct drm_i915_private *dev_priv)
277+{
278+ u8 vals[3] = { 0, 0, 0 };
279+ unsigned int i;
280+
281+ for (i = 0; i < 3; i++) {
282+ u8 ss;
283+
284+ /*
285+ * Only consider slices where one, and only one, subslice has 7
286+ * EUs
287+ */
288+ if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
289+ continue;
290+
291+ /*
292+ * subslice_7eu[i] != 0 (because of the check above) and
293+ * ss_max == 4 (maximum number of subslices possible per slice)
294+ *
295+ * -> 0 <= ss <= 3;
296+ */
297+ ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
298+ vals[i] = 3 - ss;
299+ }
300+
301+ if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
302+ return 0;
303+
304+ /* Tune IZ hashing. See intel_device_info_runtime_init() */
305+ WA_SET_FIELD_MASKED(GEN7_GT_MODE,
306+ GEN9_IZ_HASHING_MASK(2) |
307+ GEN9_IZ_HASHING_MASK(1) |
308+ GEN9_IZ_HASHING_MASK(0),
309+ GEN9_IZ_HASHING(2, vals[2]) |
310+ GEN9_IZ_HASHING(1, vals[1]) |
311+ GEN9_IZ_HASHING(0, vals[0]));
312+
313+ return 0;
314+}
315+
316+static int skl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
317+{
318+ int ret;
319+
320+ ret = gen9_ctx_workarounds_init(dev_priv);
321+ if (ret)
322+ return ret;
323+
324+ return skl_tune_iz_hashing(dev_priv);
325+}
326+
327+static int bxt_ctx_workarounds_init(struct drm_i915_private *dev_priv)
328+{
329+ int ret;
330+
331+ ret = gen9_ctx_workarounds_init(dev_priv);
332+ if (ret)
333+ return ret;
334+
335+ /* WaDisableThreadStallDopClockGating:bxt */
336+ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
337+ STALL_DOP_GATING_DISABLE);
338+
339+ /* WaToEnableHwFixForPushConstHWBug:bxt */
340+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
341+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
342+
343+ return 0;
344+}
345+
346+static int kbl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
347+{
348+ int ret;
349+
350+ ret = gen9_ctx_workarounds_init(dev_priv);
351+ if (ret)
352+ return ret;
353+
354+ /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
355+ if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
356+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
357+ HDC_FENCE_DEST_SLM_DISABLE);
358+
359+ /* WaToEnableHwFixForPushConstHWBug:kbl */
360+ if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
361+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
362+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
363+
364+ /* WaDisableSbeCacheDispatchPortSharing:kbl */
365+ WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
366+ GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
367+
368+ return 0;
369+}
370+
371+static int glk_ctx_workarounds_init(struct drm_i915_private *dev_priv)
372+{
373+ int ret;
374+
375+ ret = gen9_ctx_workarounds_init(dev_priv);
376+ if (ret)
377+ return ret;
378+
379+ /* WaToEnableHwFixForPushConstHWBug:glk */
380+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
381+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
382+
383+ return 0;
384+}
385+
386+static int cfl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
387+{
388+ int ret;
389+
390+ ret = gen9_ctx_workarounds_init(dev_priv);
391+ if (ret)
392+ return ret;
393+
394+ /* WaToEnableHwFixForPushConstHWBug:cfl */
395+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
396+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
397+
398+ /* WaDisableSbeCacheDispatchPortSharing:cfl */
399+ WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
400+ GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
401+
402+ return 0;
403+}
404+
405+static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
406+{
407+ /* WaForceContextSaveRestoreNonCoherent:cnl */
408+ WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
409+ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
410+
411+ /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
412+ if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
413+ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);
414+
415+ /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
416+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
417+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
418+
419+ /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */
420+ if (IS_CNL_REVID(dev_priv, 0, CNL_REVID_B0))
421+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
422+ GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
423+
424+ /* WaPushConstantDereferenceHoldDisable:cnl */
425+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
426+
427+ /* FtrEnableFastAnisoL1BankingFix:cnl */
428+ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
429+
430+ /* WaDisable3DMidCmdPreemption:cnl */
431+ WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
432+
433+ /* WaDisableGPGPUMidCmdPreemption:cnl */
434+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
435+ GEN9_PREEMPT_GPGPU_LEVEL_MASK,
436+ GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
437+
438+ /* WaDisableEarlyEOT:cnl */
439+ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
440+
441+ return 0;
442+}
443+
444+int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
445+{
446+ int err = 0;
447+
448+ dev_priv->workarounds.count = 0;
449+
450+ if (INTEL_GEN(dev_priv) < 8)
451+ err = 0;
452+ else if (IS_BROADWELL(dev_priv))
453+ err = bdw_ctx_workarounds_init(dev_priv);
454+ else if (IS_CHERRYVIEW(dev_priv))
455+ err = chv_ctx_workarounds_init(dev_priv);
456+ else if (IS_SKYLAKE(dev_priv))
457+ err = skl_ctx_workarounds_init(dev_priv);
458+ else if (IS_BROXTON(dev_priv))
459+ err = bxt_ctx_workarounds_init(dev_priv);
460+ else if (IS_KABYLAKE(dev_priv))
461+ err = kbl_ctx_workarounds_init(dev_priv);
462+ else if (IS_GEMINILAKE(dev_priv))
463+ err = glk_ctx_workarounds_init(dev_priv);
464+ else if (IS_COFFEELAKE(dev_priv))
465+ err = cfl_ctx_workarounds_init(dev_priv);
466+ else if (IS_CANNONLAKE(dev_priv))
467+ err = cnl_ctx_workarounds_init(dev_priv);
468+ else
469+ MISSING_CASE(INTEL_GEN(dev_priv));
470+ if (err)
471+ return err;
472+
473+ DRM_DEBUG_DRIVER("Number of context specific w/a: %d\n",
474+ dev_priv->workarounds.count);
475+ return 0;
476+}
477+
478+int intel_ctx_workarounds_emit(struct i915_request *rq)
479+{
480+ struct i915_workarounds *w = &rq->i915->workarounds;
481+ u32 *cs;
482+ int ret, i;
483+
484+ if (w->count == 0)
485+ return 0;
486+
487+ ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
488+ if (ret)
489+ return ret;
490+
491+ cs = intel_ring_begin(rq, (w->count * 2 + 2));
492+ if (IS_ERR(cs))
493+ return PTR_ERR(cs);
494+
495+ *cs++ = MI_LOAD_REGISTER_IMM(w->count);
496+ for (i = 0; i < w->count; i++) {
497+ *cs++ = i915_mmio_reg_offset(w->reg[i].addr);
498+ *cs++ = w->reg[i].value;
499+ }
500+ *cs++ = MI_NOOP;
501+
502+ intel_ring_advance(rq, cs);
503+
504+ ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
505+ if (ret)
506+ return ret;
507+
508+ return 0;
509+}
510+
511+static void bdw_gt_workarounds_apply(struct drm_i915_private *dev_priv)
512+{
513+}
514+
515+static void chv_gt_workarounds_apply(struct drm_i915_private *dev_priv)
516+{
517+}
518+
519+static void gen9_gt_workarounds_apply(struct drm_i915_private *dev_priv)
520+{
521+ /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
522+ I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
523+ _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
524+
525+ /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
526+ I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
527+ GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
528+
529+ /* WaDisableKillLogic:bxt,skl,kbl */
530+ if (!IS_COFFEELAKE(dev_priv))
531+ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
532+ ECOCHK_DIS_TLB);
533+
534+ if (HAS_LLC(dev_priv)) {
535+ /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
536+ *
537+ * Must match Display Engine. See
538+ * WaCompressedResourceDisplayNewHashMode.
539+ */
540+ I915_WRITE(MMCD_MISC_CTRL,
541+ I915_READ(MMCD_MISC_CTRL) |
542+ MMCD_PCLA |
543+ MMCD_HOTSPOT_EN);
544+ }
545+
546+ /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
547+ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
548+ BDW_DISABLE_HDC_INVALIDATION);
549+
550+ /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
551+ if (IS_GEN9_LP(dev_priv)) {
552+ u32 val = I915_READ(GEN8_L3SQCREG1);
553+
554+ val &= ~L3_PRIO_CREDITS_MASK;
555+ val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
556+ I915_WRITE(GEN8_L3SQCREG1, val);
557+ }
558+
559+ /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
560+ I915_WRITE(GEN8_L3SQCREG4,
561+ I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_FLUSH_COHERENT_LINES);
562+
563+ /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
564+ I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
565+ _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
566+}
567+
568+static void skl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
569+{
570+ gen9_gt_workarounds_apply(dev_priv);
571+
572+ /* WaEnableGapsTsvCreditFix:skl */
573+ I915_WRITE(GEN8_GARBCNTL,
574+ I915_READ(GEN8_GARBCNTL) | GEN9_GAPS_TSV_CREDIT_DISABLE);
575+
576+ /* WaDisableGafsUnitClkGating:skl */
577+ I915_WRITE(GEN7_UCGCTL4,
578+ I915_READ(GEN7_UCGCTL4) | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
579+
580+ /* WaInPlaceDecompressionHang:skl */
581+ if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
582+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
583+ I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
584+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
585+}
586+
587+static void bxt_gt_workarounds_apply(struct drm_i915_private *dev_priv)
588+{
589+ gen9_gt_workarounds_apply(dev_priv);
590+
591+ /* WaDisablePooledEuLoadBalancingFix:bxt */
592+ I915_WRITE(FF_SLICE_CS_CHICKEN2,
593+ _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
594+
595+ /* WaInPlaceDecompressionHang:bxt */
596+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
597+ I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
598+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
599+}
600+
601+static void kbl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
602+{
603+ gen9_gt_workarounds_apply(dev_priv);
604+
605+ /* WaEnableGapsTsvCreditFix:kbl */
606+ I915_WRITE(GEN8_GARBCNTL,
607+ I915_READ(GEN8_GARBCNTL) | GEN9_GAPS_TSV_CREDIT_DISABLE);
608+
609+ /* WaDisableDynamicCreditSharing:kbl */
610+ if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
611+ I915_WRITE(GAMT_CHKN_BIT_REG,
612+ I915_READ(GAMT_CHKN_BIT_REG) |
613+ GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
614+
615+ /* WaDisableGafsUnitClkGating:kbl */
616+ I915_WRITE(GEN7_UCGCTL4,
617+ I915_READ(GEN7_UCGCTL4) | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
618+
619+ /* WaInPlaceDecompressionHang:kbl */
620+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
621+ I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
622+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
623+}
624+
625+static void glk_gt_workarounds_apply(struct drm_i915_private *dev_priv)
626+{
627+ gen9_gt_workarounds_apply(dev_priv);
628+}
629+
630+static void cfl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
631+{
632+ gen9_gt_workarounds_apply(dev_priv);
633+
634+ /* WaEnableGapsTsvCreditFix:cfl */
635+ I915_WRITE(GEN8_GARBCNTL,
636+ I915_READ(GEN8_GARBCNTL) | GEN9_GAPS_TSV_CREDIT_DISABLE);
637+
638+ /* WaDisableGafsUnitClkGating:cfl */
639+ I915_WRITE(GEN7_UCGCTL4,
640+ I915_READ(GEN7_UCGCTL4) | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
641+
642+ /* WaInPlaceDecompressionHang:cfl */
643+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
644+ I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
645+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
646+}
647+
648+static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
649+{
650+ /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
651+ if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
652+ I915_WRITE(GAMT_CHKN_BIT_REG,
653+ I915_READ(GAMT_CHKN_BIT_REG) |
654+ GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
655+
656+ /* WaInPlaceDecompressionHang:cnl */
657+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
658+ I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
659+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
660+
661+ /* WaEnablePreemptionGranularityControlByUMD:cnl */
662+ I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
663+ _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
664+}
665+
666+void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
667+{
668+ if (INTEL_GEN(dev_priv) < 8)
669+ return;
670+ else if (IS_BROADWELL(dev_priv))
671+ bdw_gt_workarounds_apply(dev_priv);
672+ else if (IS_CHERRYVIEW(dev_priv))
673+ chv_gt_workarounds_apply(dev_priv);
674+ else if (IS_SKYLAKE(dev_priv))
675+ skl_gt_workarounds_apply(dev_priv);
676+ else if (IS_BROXTON(dev_priv))
677+ bxt_gt_workarounds_apply(dev_priv);
678+ else if (IS_KABYLAKE(dev_priv))
679+ kbl_gt_workarounds_apply(dev_priv);
680+ else if (IS_GEMINILAKE(dev_priv))
681+ glk_gt_workarounds_apply(dev_priv);
682+ else if (IS_COFFEELAKE(dev_priv))
683+ cfl_gt_workarounds_apply(dev_priv);
684+ else if (IS_CANNONLAKE(dev_priv))
685+ cnl_gt_workarounds_apply(dev_priv);
686+ else
687+ MISSING_CASE(INTEL_GEN(dev_priv));
688+}
689+
690+static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
691+ i915_reg_t reg)
692+{
693+ struct drm_i915_private *dev_priv = engine->i915;
694+ struct i915_workarounds *wa = &dev_priv->workarounds;
695+ const unsigned int index = wa->hw_whitelist_count[engine->id];
696+
697+ if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
698+ return -EINVAL;
699+
700+ I915_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
701+ i915_mmio_reg_offset(reg));
702+ wa->hw_whitelist_count[engine->id]++;
703+
704+ return 0;
705+}
706+
707+static int bdw_whitelist_workarounds_apply(struct intel_engine_cs *engine)
708+{
709+ return 0;
710+}
711+
712+static int chv_whitelist_workarounds_apply(struct intel_engine_cs *engine)
713+{
714+ return 0;
715+}
716+
717+static int gen9_whitelist_workarounds_apply(struct intel_engine_cs *engine)
718+{
719+ int ret;
720+
721+ /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
722+ ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
723+ if (ret)
724+ return ret;
725+
726+ /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
727+ ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
728+ if (ret)
729+ return ret;
730+
731+ /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
732+ ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
733+ if (ret)
734+ return ret;
735+
736+ return 0;
737+}
738+
739+static int skl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
740+{
741+ int ret;
742+
743+ ret = gen9_whitelist_workarounds_apply(engine);
744+ if (ret)
745+ return ret;
746+
747+ /* WaDisableLSQCROPERFforOCL:skl */
748+ ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
749+ if (ret)
750+ return ret;
751+
752+ return 0;
753+}
754+
755+static int bxt_whitelist_workarounds_apply(struct intel_engine_cs *engine)
756+{
757+ int ret;
758+
759+ ret = gen9_whitelist_workarounds_apply(engine);
760+ if (ret)
761+ return ret;
762+
763+ return 0;
764+}
765+
766+static int kbl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
767+{
768+ int ret;
769+
770+ ret = gen9_whitelist_workarounds_apply(engine);
771+ if (ret)
772+ return ret;
773+
774+ /* WaDisableLSQCROPERFforOCL:kbl */
775+ ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
776+ if (ret)
777+ return ret;
778+
779+ return 0;
780+}
781+
782+static int glk_whitelist_workarounds_apply(struct intel_engine_cs *engine)
783+{
784+ int ret;
785+
786+ ret = gen9_whitelist_workarounds_apply(engine);
787+ if (ret)
788+ return ret;
789+
790+ /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
791+ ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1);
792+ if (ret)
793+ return ret;
794+
795+ return 0;
796+}
797+
798+static int cfl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
799+{
800+ int ret;
801+
802+ ret = gen9_whitelist_workarounds_apply(engine);
803+ if (ret)
804+ return ret;
805+
806+ return 0;
807+}
808+
809+static int cnl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
810+{
811+ int ret;
812+
813+ /* WaEnablePreemptionGranularityControlByUMD:cnl */
814+ ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
815+ if (ret)
816+ return ret;
817+
818+ return 0;
819+}
820+
821+int intel_whitelist_workarounds_apply(struct intel_engine_cs *engine)
822+{
823+ struct drm_i915_private *dev_priv = engine->i915;
824+ int err = 0;
825+
826+ WARN_ON(engine->id != RCS);
827+
828+ dev_priv->workarounds.hw_whitelist_count[engine->id] = 0;
829+
830+ if (INTEL_GEN(dev_priv) < 8)
831+ err = 0;
832+ else if (IS_BROADWELL(dev_priv))
833+ err = bdw_whitelist_workarounds_apply(engine);
834+ else if (IS_CHERRYVIEW(dev_priv))
835+ err = chv_whitelist_workarounds_apply(engine);
836+ else if (IS_SKYLAKE(dev_priv))
837+ err = skl_whitelist_workarounds_apply(engine);
838+ else if (IS_BROXTON(dev_priv))
839+ err = bxt_whitelist_workarounds_apply(engine);
840+ else if (IS_KABYLAKE(dev_priv))
841+ err = kbl_whitelist_workarounds_apply(engine);
842+ else if (IS_GEMINILAKE(dev_priv))
843+ err = glk_whitelist_workarounds_apply(engine);
844+ else if (IS_COFFEELAKE(dev_priv))
845+ err = cfl_whitelist_workarounds_apply(engine);
846+ else if (IS_CANNONLAKE(dev_priv))
847+ err = cnl_whitelist_workarounds_apply(engine);
848+ else
849+ MISSING_CASE(INTEL_GEN(dev_priv));
850+ if (err)
851+ return err;
852+
853+ DRM_DEBUG_DRIVER("%s: Number of whitelist w/a: %d\n", engine->name,
854+ dev_priv->workarounds.hw_whitelist_count[engine->id]);
855+ return 0;
856+}
drivers/gpu/drm/i915/intel_workarounds.h+17−0
@@ -0,0 +1,17 @@
1+/*
2+ * SPDX-License-Identifier: MIT
3+ *
4+ * Copyright © 2014-2018 Intel Corporation
5+ */
6+
7+#ifndef _I915_WORKAROUNDS_H_
8+#define _I915_WORKAROUNDS_H_
9+
10+int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv);
11+int intel_ctx_workarounds_emit(struct i915_request *rq);
12+
13+void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
14+
15+int intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
16+
17+#endif
drivers/gpu/drm/i915/selftests/i915_live_selftests.h+1−0
@@ -20,4 +20,5 @@ selftest(evict, i915_gem_evict_live_selftests) · 19 unmodified lines
2020 selftest(hugepages, i915_gem_huge_page_live_selftests)
2121 selftest(contexts, i915_gem_context_live_selftests)
2222 selftest(hangcheck, intel_hangcheck_live_selftests)
23+selftest(execlists, intel_execlists_live_selftests)
2324 selftest(guc, intel_guc_live_selftest)
drivers/gpu/drm/i915/selftests/i915_mock_selftests.h+1−0
@@ -14,6 +14,7 @@ selftest(fence, i915_sw_fence_mock_selftests) · 13 unmodified lines
1414 selftest(scatterlist, scatterlist_mock_selftests)
1515 selftest(syncmap, i915_syncmap_mock_selftests)
1616 selftest(uncore, intel_uncore_mock_selftests)
17+selftest(engine, intel_engine_cs_mock_selftests)
1718 selftest(breadcrumbs, intel_breadcrumbs_mock_selftests)
1819 selftest(timelines, i915_gem_timeline_mock_selftests)
1920 selftest(requests, i915_request_mock_selftests)
drivers/gpu/drm/i915/selftests/intel_engine_cs.c+58−0
@@ -0,0 +1,58 @@
1+/*
2+ * SPDX-License-Identifier: GPL-2.0
3+ *
4+ * Copyright © 2018 Intel Corporation
5+ */
6+
7+#include "../i915_selftest.h"
8+
9+static int intel_mmio_bases_check(void *arg)
10+{
11+ int i, j;
12+
13+ for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
14+ const struct engine_info *info = &intel_engines[i];
15+ char name[INTEL_ENGINE_CS_MAX_NAME];
16+ u8 prev = U8_MAX;
17+
18+ __sprint_engine_name(name, info);
19+
20+ for (j = 0; j < MAX_MMIO_BASES; j++) {
21+ u8 gen = info->mmio_bases[j].gen;
22+ u32 base = info->mmio_bases[j].base;
23+
24+ if (gen >= prev) {
25+ pr_err("%s: %s: mmio base for gen %x "
26+ "is before the one for gen %x\n",
27+ __func__, name, prev, gen);
28+ return -EINVAL;
29+ }
30+
31+ if (gen == 0)
32+ break;
33+
34+ if (!base) {
35+ pr_err("%s: %s: invalid mmio base (%x) "
36+ "for gen %x at entry %u\n",
37+ __func__, name, base, gen, j);
38+ return -EINVAL;
39+ }
40+
41+ prev = gen;
42+ }
43+
44+ pr_info("%s: min gen supported for %s = %d\n",
45+ __func__, name, prev);
46+ }
47+
48+ return 0;
49+}
50+
51+int intel_engine_cs_mock_selftests(void)
52+{
53+ static const struct i915_subtest tests[] = {
54+ SUBTEST(intel_mmio_bases_check),
55+ };
56+
57+ return i915_subtests(tests, NULL);
58+}
drivers/gpu/drm/i915/selftests/intel_hangcheck.c+210−104
@@ -25,6 +25,7 @@ · 24 unmodified lines
2525 #include <linux/kthread.h>
2626
2727 #include "../i915_selftest.h"
28+#include "i915_random.h"
2829
2930 #include "mock_context.h"
3031 #include "mock_drm.h"
@@ -260,8 +261,11 @@ static void wedge_me(struct work_struct *work) · 229 unmodified lines
260261 {
261262 struct wedge_me *w = container_of(work, typeof(*w), work.work);
262263
263− pr_err("%pS timed out, cancelling all further testing.\n",
264− w->symbol);
264+ pr_err("%pS timed out, cancelling all further testing.\n", w->symbol);
265+
266+ GEM_TRACE("%pS timed out.\n", w->symbol);
267+ GEM_TRACE_DUMP();
268+
265269 i915_gem_set_wedged(w->i915);
266270 }
267271
@@ -318,7 +322,7 @@ static void hang_fini(struct hang *h) · 50 unmodified lines
318322 flush_test(h->i915, I915_WAIT_LOCKED);
319323 }
320324
321−static bool wait_for_hang(struct hang *h, struct i915_request *rq)
325+static bool wait_until_running(struct hang *h, struct i915_request *rq)
322326 {
323327 return !(wait_for_us(i915_seqno_passed(hws_seqno(h, rq),
324328 rq->fence.seqno),
@@ -433,7 +437,7 @@ static int igt_global_reset(void *arg) · 108 unmodified lines
433437 mutex_lock(&i915->drm.struct_mutex);
434438 reset_count = i915_reset_count(&i915->gpu_error);
435439
436− i915_reset(i915, I915_RESET_QUIET);
440+ i915_reset(i915, ALL_ENGINES, NULL);
437441
438442 if (i915_reset_count(&i915->gpu_error) == reset_count) {
439443 pr_err("No GPU reset recorded!\n");
@@ -483,6 +487,8 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active) · 43 unmodified lines
483487
484488 set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
485489 do {
490+ u32 seqno = intel_engine_get_seqno(engine);
491+
486492 if (active) {
487493 struct i915_request *rq;
488494
@@ -498,7 +504,7 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active) · 9 unmodified lines
498504 __i915_request_add(rq, true);
499505 mutex_unlock(&i915->drm.struct_mutex);
500506
501− if (!wait_for_hang(&h, rq)) {
507+ if (!wait_until_running(&h, rq)) {
502508 struct drm_printer p = drm_info_printer(i915->drm.dev);
503509
504510 pr_err("%s: Failed to start request %x, at %x\n",
@@ -511,14 +517,12 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active) · 6 unmodified lines
511517 break;
512518 }
513519
520+ GEM_BUG_ON(!rq->global_seqno);
521+ seqno = rq->global_seqno - 1;
514522 i915_request_put(rq);
515523 }
516524
517− engine->hangcheck.stalled = true;
518− engine->hangcheck.seqno =
519− intel_engine_get_seqno(engine);
520−
521− err = i915_reset_engine(engine, I915_RESET_QUIET);
525+ err = i915_reset_engine(engine, NULL);
522526 if (err) {
523527 pr_err("i915_reset_engine failed\n");
524528 break;
@@ -538,8 +542,6 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active) · 13 unmodified lines
538542 err = -EINVAL;
539543 break;
540544 }
541−
542− engine->hangcheck.stalled = false;
543545 } while (time_before(jiffies, end_time));
544546 clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
545547
@@ -573,11 +575,25 @@ static int igt_reset_active_engine(void *arg) · 27 unmodified lines
573575 return __igt_reset_engine(arg, true);
574576 }
575577
578+struct active_engine {
579+ struct task_struct *task;
580+ struct intel_engine_cs *engine;
581+ unsigned long resets;
582+ unsigned int flags;
583+};
584+
585+#define TEST_ACTIVE BIT(0)
586+#define TEST_OTHERS BIT(1)
587+#define TEST_SELF BIT(2)
588+#define TEST_PRIORITY BIT(3)
589+
576590 static int active_engine(void *data)
577591 {
578− struct intel_engine_cs *engine = data;
579− struct i915_request *rq[2] = {};
580− struct i915_gem_context *ctx[2];
592+ I915_RND_STATE(prng);
593+ struct active_engine *arg = data;
594+ struct intel_engine_cs *engine = arg->engine;
595+ struct i915_request *rq[8] = {};
596+ struct i915_gem_context *ctx[ARRAY_SIZE(rq)];
581597 struct drm_file *file;
582598 unsigned long count = 0;
583599 int err = 0;
@@ -586,25 +602,20 @@ static int active_engine(void *data) · 2 unmodified lines
586602 if (IS_ERR(file))
587603 return PTR_ERR(file);
588604
589− mutex_lock(&engine->i915->drm.struct_mutex);
590− ctx[0] = live_context(engine->i915, file);
591− mutex_unlock(&engine->i915->drm.struct_mutex);
592− if (IS_ERR(ctx[0])) {
593− err = PTR_ERR(ctx[0]);
594− goto err_file;
595− }
596−
597− mutex_lock(&engine->i915->drm.struct_mutex);
598− ctx[1] = live_context(engine->i915, file);
599− mutex_unlock(&engine->i915->drm.struct_mutex);
600− if (IS_ERR(ctx[1])) {
601− err = PTR_ERR(ctx[1]);
602− i915_gem_context_put(ctx[0]);
603− goto err_file;
605+ for (count = 0; count < ARRAY_SIZE(ctx); count++) {
606+ mutex_lock(&engine->i915->drm.struct_mutex);
607+ ctx[count] = live_context(engine->i915, file);
608+ mutex_unlock(&engine->i915->drm.struct_mutex);
609+ if (IS_ERR(ctx[count])) {
610+ err = PTR_ERR(ctx[count]);
611+ while (--count)
612+ i915_gem_context_put(ctx[count]);
613+ goto err_file;
614+ }
604615 }
605616
606617 while (!kthread_should_stop()) {
607− unsigned int idx = count++ & 1;
618+ unsigned int idx = count++ & (ARRAY_SIZE(rq) - 1);
608619 struct i915_request *old = rq[idx];
609620 struct i915_request *new;
610621
@@ -616,14 +627,28 @@ static int active_engine(void *data) · 5 unmodified lines
616627 break;
617628 }
618629
630+ if (arg->flags & TEST_PRIORITY)
631+ ctx[idx]->priority =
632+ i915_prandom_u32_max_state(512, &prng);
633+
619634 rq[idx] = i915_request_get(new);
620635 i915_request_add(new);
621636 mutex_unlock(&engine->i915->drm.struct_mutex);
622637
623638 if (old) {
624− i915_request_wait(old, 0, MAX_SCHEDULE_TIMEOUT);
639+ if (i915_request_wait(old, 0, HZ) < 0) {
640+ GEM_TRACE("%s timed out.\n", engine->name);
641+ GEM_TRACE_DUMP();
642+
643+ i915_gem_set_wedged(engine->i915);
644+ i915_request_put(old);
645+ err = -EIO;
646+ break;
647+ }
625648 i915_request_put(old);
626649 }
650+
651+ cond_resched();
627652 }
628653
629654 for (count = 0; count < ARRAY_SIZE(rq); count++)
@@ -634,8 +659,9 @@ err_file: · 4 unmodified lines
634659 return err;
635660 }
636661
637−static int __igt_reset_engine_others(struct drm_i915_private *i915,
638− bool active)
662+static int __igt_reset_engines(struct drm_i915_private *i915,
663+ const char *test_name,
664+ unsigned int flags)
639665 {
640666 struct intel_engine_cs *engine, *other;
641667 enum intel_engine_id id, tmp;
@@ -649,50 +675,61 @@ static int __igt_reset_engine_others(struct drm_i915_private *i915, · 7 unmodified lines
649675 if (!intel_has_reset_engine(i915))
650676 return 0;
651677
652− if (active) {
678+ if (flags & TEST_ACTIVE) {
653679 mutex_lock(&i915->drm.struct_mutex);
654680 err = hang_init(&h, i915);
655681 mutex_unlock(&i915->drm.struct_mutex);
656682 if (err)
657683 return err;
684+
685+ if (flags & TEST_PRIORITY)
686+ h.ctx->priority = 1024;
658687 }
659688
660689 for_each_engine(engine, i915, id) {
661− struct task_struct *threads[I915_NUM_ENGINES] = {};
662− unsigned long resets[I915_NUM_ENGINES];
690+ struct active_engine threads[I915_NUM_ENGINES] = {};
663691 unsigned long global = i915_reset_count(&i915->gpu_error);
664− unsigned long count = 0;
692+ unsigned long count = 0, reported;
665693 IGT_TIMEOUT(end_time);
666694
667− if (active && !intel_engine_can_store_dword(engine))
695+ if (flags & TEST_ACTIVE &&
696+ !intel_engine_can_store_dword(engine))
668697 continue;
669698
670699 memset(threads, 0, sizeof(threads));
671700 for_each_engine(other, i915, tmp) {
672701 struct task_struct *tsk;
673702
674− resets[tmp] = i915_reset_engine_count(&i915->gpu_error,
675− other);
703+ threads[tmp].resets =
704+ i915_reset_engine_count(&i915->gpu_error,
705+ other);
676706
677− if (other == engine)
707+ if (!(flags & TEST_OTHERS))
678708 continue;
679709
680− tsk = kthread_run(active_engine, other,
710+ if (other == engine && !(flags & TEST_SELF))
711+ continue;
712+
713+ threads[tmp].engine = other;
714+ threads[tmp].flags = flags;
715+
716+ tsk = kthread_run(active_engine, &threads[tmp],
681717 "igt/%s", other->name);
682718 if (IS_ERR(tsk)) {
683719 err = PTR_ERR(tsk);
684720 goto unwind;
685721 }
686722
687− threads[tmp] = tsk;
723+ threads[tmp].task = tsk;
688724 get_task_struct(tsk);
689725 }
690726
691727 set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
692728 do {
693− if (active) {
694− struct i915_request *rq;
729+ u32 seqno = intel_engine_get_seqno(engine);
730+ struct i915_request *rq = NULL;
695731
732+ if (flags & TEST_ACTIVE) {
696733 mutex_lock(&i915->drm.struct_mutex);
697734 rq = hang_create_request(&h, engine);
698735 if (IS_ERR(rq)) {
@@ -705,7 +742,7 @@ static int __igt_reset_engine_others(struct drm_i915_private *i915, · 6 unmodified lines
705742 __i915_request_add(rq, true);
706743 mutex_unlock(&i915->drm.struct_mutex);
707744
708− if (!wait_for_hang(&h, rq)) {
745+ if (!wait_until_running(&h, rq)) {
709746 struct drm_printer p = drm_info_printer(i915->drm.dev);
710747
711748 pr_err("%s: Failed to start request %x, at %x\n",
@@ -718,33 +755,34 @@ static int __igt_reset_engine_others(struct drm_i915_private *i915, · 6 unmodified lines
718755 break;
719756 }
720757
721− i915_request_put(rq);
758+ GEM_BUG_ON(!rq->global_seqno);
759+ seqno = rq->global_seqno - 1;
722760 }
723761
724− engine->hangcheck.stalled = true;
725− engine->hangcheck.seqno =
726− intel_engine_get_seqno(engine);
727−
728− err = i915_reset_engine(engine, I915_RESET_QUIET);
762+ err = i915_reset_engine(engine, NULL);
729763 if (err) {
730− pr_err("i915_reset_engine(%s:%s) failed, err=%d\n",
731− engine->name, active ? "active" : "idle", err);
764+ pr_err("i915_reset_engine(%s:%s): failed, err=%d\n",
765+ engine->name, test_name, err);
732766 break;
733767 }
734768
735− engine->hangcheck.stalled = false;
736769 count++;
770+
771+ if (rq) {
772+ i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
773+ i915_request_put(rq);
774+ }
737775 } while (time_before(jiffies, end_time));
738776 clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
739777 pr_info("i915_reset_engine(%s:%s): %lu resets\n",
740− engine->name, active ? "active" : "idle", count);
741−
742− if (i915_reset_engine_count(&i915->gpu_error, engine) -
743− resets[engine->id] != (active ? count : 0)) {
744− pr_err("i915_reset_engine(%s:%s): reset %lu times, but reported %lu\n",
745− engine->name, active ? "active" : "idle", count,
746− i915_reset_engine_count(&i915->gpu_error,
747− engine) - resets[engine->id]);
778+ engine->name, test_name, count);
779+
780+ reported = i915_reset_engine_count(&i915->gpu_error, engine);
781+ reported -= threads[engine->id].resets;
782+ if (reported != (flags & TEST_ACTIVE ? count : 0)) {
783+ pr_err("i915_reset_engine(%s:%s): reset %lu times, but reported %lu, expected %lu reported\n",
784+ engine->name, test_name, count, reported,
785+ (flags & TEST_ACTIVE ? count : 0));
748786 if (!err)
749787 err = -EINVAL;
750788 }
@@ -753,24 +791,26 @@ unwind: · 2 unmodified lines
753791 for_each_engine(other, i915, tmp) {
754792 int ret;
755793
756− if (!threads[tmp])
794+ if (!threads[tmp].task)
757795 continue;
758796
759− ret = kthread_stop(threads[tmp]);
797+ ret = kthread_stop(threads[tmp].task);
760798 if (ret) {
761799 pr_err("kthread for other engine %s failed, err=%d\n",
762800 other->name, ret);
763801 if (!err)
764802 err = ret;
765803 }
766− put_task_struct(threads[tmp]);
804+ put_task_struct(threads[tmp].task);
767805
768− if (resets[tmp] != i915_reset_engine_count(&i915->gpu_error,
769− other)) {
806+ if (other != engine &&
807+ threads[tmp].resets !=
808+ i915_reset_engine_count(&i915->gpu_error, other)) {
770809 pr_err("Innocent engine %s was reset (count=%ld)\n",
771810 other->name,
772811 i915_reset_engine_count(&i915->gpu_error,
773− other) - resets[tmp]);
812+ other) -
813+ threads[tmp].resets);
774814 if (!err)
775815 err = -EINVAL;
776816 }
@@ -794,7 +834,7 @@ unwind: · 17 unmodified lines
794834 if (i915_terminally_wedged(&i915->gpu_error))
795835 err = -EIO;
796836
797− if (active) {
837+ if (flags & TEST_ACTIVE) {
798838 mutex_lock(&i915->drm.struct_mutex);
799839 hang_fini(&h);
800840 mutex_unlock(&i915->drm.struct_mutex);
@@ -803,27 +843,56 @@ unwind: · 2 unmodified lines
803843 return err;
804844 }
805845
806−static int igt_reset_idle_engine_others(void *arg)
846+static int igt_reset_engines(void *arg)
807847 {
808− return __igt_reset_engine_others(arg, false);
809−}
848+ static const struct {
849+ const char *name;
850+ unsigned int flags;
851+ } phases[] = {
852+ { "idle", 0 },
853+ { "active", TEST_ACTIVE },
854+ { "others-idle", TEST_OTHERS },
855+ { "others-active", TEST_OTHERS | TEST_ACTIVE },
856+ {
857+ "others-priority",
858+ TEST_OTHERS | TEST_ACTIVE | TEST_PRIORITY
859+ },
860+ {
861+ "self-priority",
862+ TEST_OTHERS | TEST_ACTIVE | TEST_PRIORITY | TEST_SELF,
863+ },
864+ { }
865+ };
866+ struct drm_i915_private *i915 = arg;
867+ typeof(*phases) *p;
868+ int err;
810869
811−static int igt_reset_active_engine_others(void *arg)
812−{
813− return __igt_reset_engine_others(arg, true);
870+ for (p = phases; p->name; p++) {
871+ if (p->flags & TEST_PRIORITY) {
872+ if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
873+ continue;
874+ }
875+
876+ err = __igt_reset_engines(arg, p->name, p->flags);
877+ if (err)
878+ return err;
879+ }
880+
881+ return 0;
814882 }
815883
816−static u32 fake_hangcheck(struct i915_request *rq)
884+static u32 fake_hangcheck(struct i915_request *rq, u32 mask)
817885 {
818− u32 reset_count;
886+ struct i915_gpu_error *error = &rq->i915->gpu_error;
887+ u32 reset_count = i915_reset_count(error);
819888
820− rq->engine->hangcheck.stalled = true;
821− rq->engine->hangcheck.seqno = intel_engine_get_seqno(rq->engine);
889+ error->stalled_mask = mask;
822890
823− reset_count = i915_reset_count(&rq->i915->gpu_error);
891+ /* set_bit() must be after we have setup the backchannel (mask) */
892+ smp_mb__before_atomic();
893+ set_bit(I915_RESET_HANDOFF, &error->flags);
824894
825− set_bit(I915_RESET_HANDOFF, &rq->i915->gpu_error.flags);
826− wake_up_all(&rq->i915->gpu_error.wait_queue);
895+ wake_up_all(&error->wait_queue);
827896
828897 return reset_count;
829898 }
@@ -858,21 +927,20 @@ static int igt_wait_reset(void *arg) · 28 unmodified lines
858927 i915_request_get(rq);
859928 __i915_request_add(rq, true);
860929
861− if (!wait_for_hang(&h, rq)) {
930+ if (!wait_until_running(&h, rq)) {
862931 struct drm_printer p = drm_info_printer(i915->drm.dev);
863932
864933 pr_err("%s: Failed to start request %x, at %x\n",
865934 __func__, rq->fence.seqno, hws_seqno(&h, rq));
866935 intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
867936
868− i915_reset(i915, 0);
869937 i915_gem_set_wedged(i915);
870938
871939 err = -EIO;
872940 goto out_rq;
873941 }
874942
875− reset_count = fake_hangcheck(rq);
943+ reset_count = fake_hangcheck(rq, ALL_ENGINES);
876944
877945 timeout = i915_request_wait(rq, I915_WAIT_LOCKED, 10);
878946 if (timeout < 0) {
@@ -903,6 +971,23 @@ unlock: · 24 unmodified lines
903971 return err;
904972 }
905973
974+static int wait_for_others(struct drm_i915_private *i915,
975+ struct intel_engine_cs *exclude)
976+{
977+ struct intel_engine_cs *engine;
978+ enum intel_engine_id id;
979+
980+ for_each_engine(engine, i915, id) {
981+ if (engine == exclude)
982+ continue;
983+
984+ if (wait_for(intel_engine_is_idle(engine), 10))
985+ return -EIO;
986+ }
987+
988+ return 0;
989+}
990+
906991 static int igt_reset_queue(void *arg)
907992 {
908993 struct drm_i915_private *i915 = arg;
@@ -951,27 +1036,49 @@ static int igt_reset_queue(void *arg) · 42 unmodified lines
9511036 i915_request_get(rq);
9521037 __i915_request_add(rq, true);
9531038
954− if (!wait_for_hang(&h, prev)) {
1039+ /*
1040+ * XXX We don't handle resetting the kernel context
1041+ * very well. If we trigger a device reset twice in
1042+ * quick succession while the kernel context is
1043+ * executing, we may end up skipping the breadcrumb.
1044+ * This is really only a problem for the selftest as
1045+ * normally there is a large interlude between resets
1046+ * (hangcheck), or we focus on resetting just one
1047+ * engine and so avoid repeatedly resetting innocents.
1048+ */
1049+ err = wait_for_others(i915, engine);
1050+ if (err) {
1051+ pr_err("%s(%s): Failed to idle other inactive engines after device reset\n",
1052+ __func__, engine->name);
1053+ i915_request_put(rq);
1054+ i915_request_put(prev);
1055+
1056+ GEM_TRACE_DUMP();
1057+ i915_gem_set_wedged(i915);
1058+ goto fini;
1059+ }
1060+
1061+ if (!wait_until_running(&h, prev)) {
9551062 struct drm_printer p = drm_info_printer(i915->drm.dev);
9561063
957− pr_err("%s: Failed to start request %x, at %x\n",
958− __func__, prev->fence.seqno, hws_seqno(&h, prev));
959− intel_engine_dump(prev->engine, &p,
960− "%s\n", prev->engine->name);
1064+ pr_err("%s(%s): Failed to start request %x, at %x\n",
1065+ __func__, engine->name,
1066+ prev->fence.seqno, hws_seqno(&h, prev));
1067+ intel_engine_dump(engine, &p,
1068+ "%s\n", engine->name);
9611069
9621070 i915_request_put(rq);
9631071 i915_request_put(prev);
9641072
965− i915_reset(i915, 0);
9661073 i915_gem_set_wedged(i915);
9671074
9681075 err = -EIO;
9691076 goto fini;
9701077 }
9711078
972− reset_count = fake_hangcheck(prev);
1079+ reset_count = fake_hangcheck(prev, ENGINE_MASK(id));
9731080
974− i915_reset(i915, I915_RESET_QUIET);
1081+ i915_reset(i915, ENGINE_MASK(id), NULL);
9751082
9761083 GEM_BUG_ON(test_bit(I915_RESET_HANDOFF,
9771084 &i915->gpu_error.flags));
@@ -1044,7 +1151,7 @@ static int igt_handle_error(void *arg) · 66 unmodified lines
10441151 if (!intel_has_reset_engine(i915))
10451152 return 0;
10461153
1047− if (!intel_engine_can_store_dword(i915->engine[RCS]))
1154+ if (!engine || !intel_engine_can_store_dword(engine))
10481155 return 0;
10491156
10501157 mutex_lock(&i915->drm.struct_mutex);
@@ -1062,14 +1169,13 @@ static int igt_handle_error(void *arg) · 11 unmodified lines
10621169 i915_request_get(rq);
10631170 __i915_request_add(rq, true);
10641171
1065− if (!wait_for_hang(&h, rq)) {
1172+ if (!wait_until_running(&h, rq)) {
10661173 struct drm_printer p = drm_info_printer(i915->drm.dev);
10671174
10681175 pr_err("%s: Failed to start request %x, at %x\n",
10691176 __func__, rq->fence.seqno, hws_seqno(&h, rq));
10701177 intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
10711178
1072− i915_reset(i915, 0);
10731179 i915_gem_set_wedged(i915);
10741180
10751181 err = -EIO;
@@ -1081,10 +1187,7 @@ static int igt_handle_error(void *arg) · 5 unmodified lines
10811187 /* Temporarily disable error capture */
10821188 error = xchg(&i915->gpu_error.first_error, (void *)-1);
10831189
1084− engine->hangcheck.stalled = true;
1085− engine->hangcheck.seqno = intel_engine_get_seqno(engine);
1086−
1087− i915_handle_error(i915, intel_engine_flag(engine), "%s", __func__);
1190+ i915_handle_error(i915, ENGINE_MASK(engine->id), 0, NULL);
10881191
10891192 xchg(&i915->gpu_error.first_error, error);
10901193
@@ -1112,8 +1215,7 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) · 21 unmodified lines
11121215 SUBTEST(igt_hang_sanitycheck),
11131216 SUBTEST(igt_reset_idle_engine),
11141217 SUBTEST(igt_reset_active_engine),
1115− SUBTEST(igt_reset_idle_engine_others),
1116− SUBTEST(igt_reset_active_engine_others),
1218+ SUBTEST(igt_reset_engines),
11171219 SUBTEST(igt_wait_reset),
11181220 SUBTEST(igt_reset_queue),
11191221 SUBTEST(igt_handle_error),
@@ -1129,6 +1231,10 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) · 9 unmodified lines
11291231
11301232 err = i915_subtests(tests, i915);
11311233
1234+ mutex_lock(&i915->drm.struct_mutex);
1235+ flush_test(i915, I915_WAIT_LOCKED);
1236+ mutex_unlock(&i915->drm.struct_mutex);
1237+
11321238 i915_modparams.enable_hangcheck = saved_hangcheck;
11331239 intel_runtime_pm_put(i915);
11341240
drivers/gpu/drm/i915/selftests/intel_lrc.c+507−0
@@ -0,0 +1,507 @@
1+/*
2+ * SPDX-License-Identifier: MIT
3+ *
4+ * Copyright © 2018 Intel Corporation
5+ */
6+
7+#include "../i915_selftest.h"
8+
9+#include "mock_context.h"
10+
11+struct spinner {
12+ struct drm_i915_private *i915;
13+ struct drm_i915_gem_object *hws;
14+ struct drm_i915_gem_object *obj;
15+ u32 *batch;
16+ void *seqno;
17+};
18+
19+static int spinner_init(struct spinner *spin, struct drm_i915_private *i915)
20+{
21+ unsigned int mode;
22+ void *vaddr;
23+ int err;
24+
25+ GEM_BUG_ON(INTEL_GEN(i915) < 8);
26+
27+ memset(spin, 0, sizeof(*spin));
28+ spin->i915 = i915;
29+
30+ spin->hws = i915_gem_object_create_internal(i915, PAGE_SIZE);
31+ if (IS_ERR(spin->hws)) {
32+ err = PTR_ERR(spin->hws);
33+ goto err;
34+ }
35+
36+ spin->obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
37+ if (IS_ERR(spin->obj)) {
38+ err = PTR_ERR(spin->obj);
39+ goto err_hws;
40+ }
41+
42+ i915_gem_object_set_cache_level(spin->hws, I915_CACHE_LLC);
43+ vaddr = i915_gem_object_pin_map(spin->hws, I915_MAP_WB);
44+ if (IS_ERR(vaddr)) {
45+ err = PTR_ERR(vaddr);
46+ goto err_obj;
47+ }
48+ spin->seqno = memset(vaddr, 0xff, PAGE_SIZE);
49+
50+ mode = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
51+ vaddr = i915_gem_object_pin_map(spin->obj, mode);
52+ if (IS_ERR(vaddr)) {
53+ err = PTR_ERR(vaddr);
54+ goto err_unpin_hws;
55+ }
56+ spin->batch = vaddr;
57+
58+ return 0;
59+
60+err_unpin_hws:
61+ i915_gem_object_unpin_map(spin->hws);
62+err_obj:
63+ i915_gem_object_put(spin->obj);
64+err_hws:
65+ i915_gem_object_put(spin->hws);
66+err:
67+ return err;
68+}
69+
70+static unsigned int seqno_offset(u64 fence)
71+{
72+ return offset_in_page(sizeof(u32) * fence);
73+}
74+
75+static u64 hws_address(const struct i915_vma *hws,
76+ const struct i915_request *rq)
77+{
78+ return hws->node.start + seqno_offset(rq->fence.context);
79+}
80+
81+static int emit_recurse_batch(struct spinner *spin,
82+ struct i915_request *rq,
83+ u32 arbitration_command)
84+{
85+ struct i915_address_space *vm = &rq->ctx->ppgtt->base;
86+ struct i915_vma *hws, *vma;
87+ u32 *batch;
88+ int err;
89+
90+ vma = i915_vma_instance(spin->obj, vm, NULL);
91+ if (IS_ERR(vma))
92+ return PTR_ERR(vma);
93+
94+ hws = i915_vma_instance(spin->hws, vm, NULL);
95+ if (IS_ERR(hws))
96+ return PTR_ERR(hws);
97+
98+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
99+ if (err)
100+ return err;
101+
102+ err = i915_vma_pin(hws, 0, 0, PIN_USER);
103+ if (err)
104+ goto unpin_vma;
105+
106+ i915_vma_move_to_active(vma, rq, 0);
107+ if (!i915_gem_object_has_active_reference(vma->obj)) {
108+ i915_gem_object_get(vma->obj);
109+ i915_gem_object_set_active_reference(vma->obj);
110+ }
111+
112+ i915_vma_move_to_active(hws, rq, 0);
113+ if (!i915_gem_object_has_active_reference(hws->obj)) {
114+ i915_gem_object_get(hws->obj);
115+ i915_gem_object_set_active_reference(hws->obj);
116+ }
117+
118+ batch = spin->batch;
119+
120+ *batch++ = MI_STORE_DWORD_IMM_GEN4;
121+ *batch++ = lower_32_bits(hws_address(hws, rq));
122+ *batch++ = upper_32_bits(hws_address(hws, rq));
123+ *batch++ = rq->fence.seqno;
124+
125+ *batch++ = arbitration_command;
126+
127+ *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
128+ *batch++ = lower_32_bits(vma->node.start);
129+ *batch++ = upper_32_bits(vma->node.start);
130+ *batch++ = MI_BATCH_BUFFER_END; /* not reached */
131+
132+ i915_gem_chipset_flush(spin->i915);
133+
134+ err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, 0);
135+
136+ i915_vma_unpin(hws);
137+unpin_vma:
138+ i915_vma_unpin(vma);
139+ return err;
140+}
141+
142+static struct i915_request *
143+spinner_create_request(struct spinner *spin,
144+ struct i915_gem_context *ctx,
145+ struct intel_engine_cs *engine,
146+ u32 arbitration_command)
147+{
148+ struct i915_request *rq;
149+ int err;
150+
151+ rq = i915_request_alloc(engine, ctx);
152+ if (IS_ERR(rq))
153+ return rq;
154+
155+ err = emit_recurse_batch(spin, rq, arbitration_command);
156+ if (err) {
157+ __i915_request_add(rq, false);
158+ return ERR_PTR(err);
159+ }
160+
161+ return rq;
162+}
163+
164+static u32 hws_seqno(const struct spinner *spin, const struct i915_request *rq)
165+{
166+ u32 *seqno = spin->seqno + seqno_offset(rq->fence.context);
167+
168+ return READ_ONCE(*seqno);
169+}
170+
171+struct wedge_me {
172+ struct delayed_work work;
173+ struct drm_i915_private *i915;
174+ const void *symbol;
175+};
176+
177+static void wedge_me(struct work_struct *work)
178+{
179+ struct wedge_me *w = container_of(work, typeof(*w), work.work);
180+
181+ pr_err("%pS timed out, cancelling all further testing.\n", w->symbol);
182+
183+ GEM_TRACE("%pS timed out.\n", w->symbol);
184+ GEM_TRACE_DUMP();
185+
186+ i915_gem_set_wedged(w->i915);
187+}
188+
189+static void __init_wedge(struct wedge_me *w,
190+ struct drm_i915_private *i915,
191+ long timeout,
192+ const void *symbol)
193+{
194+ w->i915 = i915;
195+ w->symbol = symbol;
196+
197+ INIT_DELAYED_WORK_ONSTACK(&w->work, wedge_me);
198+ schedule_delayed_work(&w->work, timeout);
199+}
200+
201+static void __fini_wedge(struct wedge_me *w)
202+{
203+ cancel_delayed_work_sync(&w->work);
204+ destroy_delayed_work_on_stack(&w->work);
205+ w->i915 = NULL;
206+}
207+
208+#define wedge_on_timeout(W, DEV, TIMEOUT) \
209+ for (__init_wedge((W), (DEV), (TIMEOUT), __builtin_return_address(0)); \
210+ (W)->i915; \
211+ __fini_wedge((W)))
212+
213+static noinline int
214+flush_test(struct drm_i915_private *i915, unsigned int flags)
215+{
216+ struct wedge_me w;
217+
218+ cond_resched();
219+
220+ wedge_on_timeout(&w, i915, HZ)
221+ i915_gem_wait_for_idle(i915, flags);
222+
223+ return i915_terminally_wedged(&i915->gpu_error) ? -EIO : 0;
224+}
225+
226+static void spinner_end(struct spinner *spin)
227+{
228+ *spin->batch = MI_BATCH_BUFFER_END;
229+ i915_gem_chipset_flush(spin->i915);
230+}
231+
232+static void spinner_fini(struct spinner *spin)
233+{
234+ spinner_end(spin);
235+
236+ i915_gem_object_unpin_map(spin->obj);
237+ i915_gem_object_put(spin->obj);
238+
239+ i915_gem_object_unpin_map(spin->hws);
240+ i915_gem_object_put(spin->hws);
241+}
242+
243+static bool wait_for_spinner(struct spinner *spin, struct i915_request *rq)
244+{
245+ if (!wait_event_timeout(rq->execute,
246+ READ_ONCE(rq->global_seqno),
247+ msecs_to_jiffies(10)))
248+ return false;
249+
250+ return !(wait_for_us(i915_seqno_passed(hws_seqno(spin, rq),
251+ rq->fence.seqno),
252+ 10) &&
253+ wait_for(i915_seqno_passed(hws_seqno(spin, rq),
254+ rq->fence.seqno),
255+ 1000));
256+}
257+
258+static int live_sanitycheck(void *arg)
259+{
260+ struct drm_i915_private *i915 = arg;
261+ struct intel_engine_cs *engine;
262+ struct i915_gem_context *ctx;
263+ enum intel_engine_id id;
264+ struct spinner spin;
265+ int err = -ENOMEM;
266+
267+ if (!HAS_LOGICAL_RING_CONTEXTS(i915))
268+ return 0;
269+
270+ mutex_lock(&i915->drm.struct_mutex);
271+
272+ if (spinner_init(&spin, i915))
273+ goto err_unlock;
274+
275+ ctx = kernel_context(i915);
276+ if (!ctx)
277+ goto err_spin;
278+
279+ for_each_engine(engine, i915, id) {
280+ struct i915_request *rq;
281+
282+ rq = spinner_create_request(&spin, ctx, engine, MI_NOOP);
283+ if (IS_ERR(rq)) {
284+ err = PTR_ERR(rq);
285+ goto err_ctx;
286+ }
287+
288+ i915_request_add(rq);
289+ if (!wait_for_spinner(&spin, rq)) {
290+ GEM_TRACE("spinner failed to start\n");
291+ GEM_TRACE_DUMP();
292+ i915_gem_set_wedged(i915);
293+ err = -EIO;
294+ goto err_ctx;
295+ }
296+
297+ spinner_end(&spin);
298+ if (flush_test(i915, I915_WAIT_LOCKED)) {
299+ err = -EIO;
300+ goto err_ctx;
301+ }
302+ }
303+
304+ err = 0;
305+err_ctx:
306+ kernel_context_close(ctx);
307+err_spin:
308+ spinner_fini(&spin);
309+err_unlock:
310+ flush_test(i915, I915_WAIT_LOCKED);
311+ mutex_unlock(&i915->drm.struct_mutex);
312+ return err;
313+}
314+
315+static int live_preempt(void *arg)
316+{
317+ struct drm_i915_private *i915 = arg;
318+ struct i915_gem_context *ctx_hi, *ctx_lo;
319+ struct spinner spin_hi, spin_lo;
320+ struct intel_engine_cs *engine;
321+ enum intel_engine_id id;
322+ int err = -ENOMEM;
323+
324+ if (!HAS_LOGICAL_RING_PREEMPTION(i915))
325+ return 0;
326+
327+ mutex_lock(&i915->drm.struct_mutex);
328+
329+ if (spinner_init(&spin_hi, i915))
330+ goto err_unlock;
331+
332+ if (spinner_init(&spin_lo, i915))
333+ goto err_spin_hi;
334+
335+ ctx_hi = kernel_context(i915);
336+ if (!ctx_hi)
337+ goto err_spin_lo;
338+ ctx_hi->priority = I915_CONTEXT_MAX_USER_PRIORITY;
339+
340+ ctx_lo = kernel_context(i915);
341+ if (!ctx_lo)
342+ goto err_ctx_hi;
343+ ctx_lo->priority = I915_CONTEXT_MIN_USER_PRIORITY;
344+
345+ for_each_engine(engine, i915, id) {
346+ struct i915_request *rq;
347+
348+ rq = spinner_create_request(&spin_lo, ctx_lo, engine,
349+ MI_ARB_CHECK);
350+ if (IS_ERR(rq)) {
351+ err = PTR_ERR(rq);
352+ goto err_ctx_lo;
353+ }
354+
355+ i915_request_add(rq);
356+ if (!wait_for_spinner(&spin_lo, rq)) {
357+ GEM_TRACE("lo spinner failed to start\n");
358+ GEM_TRACE_DUMP();
359+ i915_gem_set_wedged(i915);
360+ err = -EIO;
361+ goto err_ctx_lo;
362+ }
363+
364+ rq = spinner_create_request(&spin_hi, ctx_hi, engine,
365+ MI_ARB_CHECK);
366+ if (IS_ERR(rq)) {
367+ spinner_end(&spin_lo);
368+ err = PTR_ERR(rq);
369+ goto err_ctx_lo;
370+ }
371+
372+ i915_request_add(rq);
373+ if (!wait_for_spinner(&spin_hi, rq)) {
374+ GEM_TRACE("hi spinner failed to start\n");
375+ GEM_TRACE_DUMP();
376+ i915_gem_set_wedged(i915);
377+ err = -EIO;
378+ goto err_ctx_lo;
379+ }
380+
381+ spinner_end(&spin_hi);
382+ spinner_end(&spin_lo);
383+ if (flush_test(i915, I915_WAIT_LOCKED)) {
384+ err = -EIO;
385+ goto err_ctx_lo;
386+ }
387+ }
388+
389+ err = 0;
390+err_ctx_lo:
391+ kernel_context_close(ctx_lo);
392+err_ctx_hi:
393+ kernel_context_close(ctx_hi);
394+err_spin_lo:
395+ spinner_fini(&spin_lo);
396+err_spin_hi:
397+ spinner_fini(&spin_hi);
398+err_unlock:
399+ flush_test(i915, I915_WAIT_LOCKED);
400+ mutex_unlock(&i915->drm.struct_mutex);
401+ return err;
402+}
403+
404+static int live_late_preempt(void *arg)
405+{
406+ struct drm_i915_private *i915 = arg;
407+ struct i915_gem_context *ctx_hi, *ctx_lo;
408+ struct spinner spin_hi, spin_lo;
409+ struct intel_engine_cs *engine;
410+ enum intel_engine_id id;
411+ int err = -ENOMEM;
412+
413+ if (!HAS_LOGICAL_RING_PREEMPTION(i915))
414+ return 0;
415+
416+ mutex_lock(&i915->drm.struct_mutex);
417+
418+ if (spinner_init(&spin_hi, i915))
419+ goto err_unlock;
420+
421+ if (spinner_init(&spin_lo, i915))
422+ goto err_spin_hi;
423+
424+ ctx_hi = kernel_context(i915);
425+ if (!ctx_hi)
426+ goto err_spin_lo;
427+
428+ ctx_lo = kernel_context(i915);
429+ if (!ctx_lo)
430+ goto err_ctx_hi;
431+
432+ for_each_engine(engine, i915, id) {
433+ struct i915_request *rq;
434+
435+ rq = spinner_create_request(&spin_lo, ctx_lo, engine,
436+ MI_ARB_CHECK);
437+ if (IS_ERR(rq)) {
438+ err = PTR_ERR(rq);
439+ goto err_ctx_lo;
440+ }
441+
442+ i915_request_add(rq);
443+ if (!wait_for_spinner(&spin_lo, rq)) {
444+ pr_err("First context failed to start\n");
445+ goto err_wedged;
446+ }
447+
448+ rq = spinner_create_request(&spin_hi, ctx_hi, engine, MI_NOOP);
449+ if (IS_ERR(rq)) {
450+ spinner_end(&spin_lo);
451+ err = PTR_ERR(rq);
452+ goto err_ctx_lo;
453+ }
454+
455+ i915_request_add(rq);
456+ if (wait_for_spinner(&spin_hi, rq)) {
457+ pr_err("Second context overtook first?\n");
458+ goto err_wedged;
459+ }
460+
461+ engine->schedule(rq, I915_PRIORITY_MAX);
462+
463+ if (!wait_for_spinner(&spin_hi, rq)) {
464+ pr_err("High priority context failed to preempt the low priority context\n");
465+ GEM_TRACE_DUMP();
466+ goto err_wedged;
467+ }
468+
469+ spinner_end(&spin_hi);
470+ spinner_end(&spin_lo);
471+ if (flush_test(i915, I915_WAIT_LOCKED)) {
472+ err = -EIO;
473+ goto err_ctx_lo;
474+ }
475+ }
476+
477+ err = 0;
478+err_ctx_lo:
479+ kernel_context_close(ctx_lo);
480+err_ctx_hi:
481+ kernel_context_close(ctx_hi);
482+err_spin_lo:
483+ spinner_fini(&spin_lo);
484+err_spin_hi:
485+ spinner_fini(&spin_hi);
486+err_unlock:
487+ flush_test(i915, I915_WAIT_LOCKED);
488+ mutex_unlock(&i915->drm.struct_mutex);
489+ return err;
490+
491+err_wedged:
492+ spinner_end(&spin_hi);
493+ spinner_end(&spin_lo);
494+ i915_gem_set_wedged(i915);
495+ err = -EIO;
496+ goto err_ctx_lo;
497+}
498+
499+int intel_execlists_live_selftests(struct drm_i915_private *i915)
500+{
501+ static const struct i915_subtest tests[] = {
502+ SUBTEST(live_sanitycheck),
503+ SUBTEST(live_preempt),
504+ SUBTEST(live_late_preempt),
505+ };
506+ return i915_subtests(tests, i915);
507+}
include/drm/drm_dp_helper.h+10−0
@@ -478,6 +478,7 @@ · 477 unmodified lines
478478 # define DP_PSR_FRAME_CAPTURE (1 << 3)
479479 # define DP_PSR_SELECTIVE_UPDATE (1 << 4)
480480 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
481+# define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */
481482
482483 #define DP_ADAPTER_CTRL 0x1a0
483484 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
@@ -794,6 +795,15 @@ · 310 unmodified lines
794795 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
795796 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
796797
798+#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
799+# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
800+# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
801+# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
802+# define DP_SU_VALID (1 << 3) /* eDP 1.4 */
803+# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
804+# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
805+# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
806+
797807 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
798808 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
799809

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