ASoC: Updates for v6.2 This is a fairly sedate release for the core code, but there's been a lot of driver work especially around the x86 platforms and device tree updates: - More cleanups of the DAPM code from Morimoto-san. - Factoring out of mapping hw_params onto SoundWire configuration by Charles Keepax. - The ever ongoing overhauls of the Intel DSP code continue, including support for loading libraries and probes with IPC4 on SOF. - Support for more sample formats on JZ4740. - Lots of device tree conversions and fixups. - Support for Allwinner D1, a range of AMD and Intel systems, Mediatek systems with multiple DMICs, Nuvoton NAU8318, NXP fsl_rpmsg and i.MX93, Qualcomm AudioReach Enable, MFC and SAL, RealTek RT1318 and Rockchip RK3588 There's more cross tree updates than usual, though all fairly minor: - Some OMAP board file updates that were depedencies for removing their providers in ASoC, as part of a wider effort removing the support for the relevant OMAP platforms. - A new I2C API required for updates to the new I2C probe API. - A DRM update making use of a new API for fixing the capabilities advertised via hdmi-codec. Since this is being sent early I might send some more stuff if you've not yet sent your pull request and there's more come in.
Showing the changes to include/uapi (16 of 2021 files). Show all
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| @@ -763,6 +763,8 @@ struct drm_amdgpu_cs_chunk_data { · 762 unmodified lines | ||
| 763 | 763 | #define AMDGPU_INFO_FW_MES_KIQ 0x19 |
| 764 | 764 | /* Subquery id: Query MES firmware version */ |
| 765 | 765 | #define AMDGPU_INFO_FW_MES 0x1a |
| 766 | + /* Subquery id: Query IMU firmware version */ | |
| 767 | + #define AMDGPU_INFO_FW_IMU 0x1b | |
| 766 | 768 | |
| 767 | 769 | /* number of bytes moved for TTM migration */ |
| 768 | 770 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f |
| @@ -235,25 +235,29 @@ struct drm_panfrost_madvise { · 234 unmodified lines | ||
| 235 | 235 | #define PANFROSTDUMP_BUF_BO (PANFROSTDUMP_BUF_BOMAP + 1) |
| 236 | 236 | #define PANFROSTDUMP_BUF_TRAILER (PANFROSTDUMP_BUF_BO + 1) |
| 237 | 237 | |
| 238 | +/* | |
| 239 | + * This structure is the native endianness of the dumping machine, tools can | |
| 240 | + * detect the endianness by looking at the value in 'magic'. | |
| 241 | + */ | |
| 238 | 242 | struct panfrost_dump_object_header { |
| 239 | − __le32 magic; | |
| 240 | − __le32 type; | |
| 241 | − __le32 file_size; | |
| 242 | − __le32 file_offset; | |
| 243 | + __u32 magic; | |
| 244 | + __u32 type; | |
| 245 | + __u32 file_size; | |
| 246 | + __u32 file_offset; | |
| 243 | 247 | |
| 244 | 248 | union { |
| 245 | − struct pan_reg_hdr { | |
| 246 | − __le64 jc; | |
| 247 | − __le32 gpu_id; | |
| 248 | − __le32 major; | |
| 249 | − __le32 minor; | |
| 250 | − __le64 nbos; | |
| 249 | + struct { | |
| 250 | + __u64 jc; | |
| 251 | + __u32 gpu_id; | |
| 252 | + __u32 major; | |
| 253 | + __u32 minor; | |
| 254 | + __u64 nbos; | |
| 251 | 255 | } reghdr; |
| 252 | 256 | |
| 253 | − struct pan_bomap_hdr { | |
| 254 | − __le32 valid; | |
| 255 | − __le64 iova; | |
| 256 | − __le32 data[2]; | |
| 257 | + struct { | |
| 258 | + __u32 valid; | |
| 259 | + __u64 iova; | |
| 260 | + __u32 data[2]; | |
| 257 | 261 | } bomap; |
| 258 | 262 | |
| 259 | 263 | /* |
| @@ -261,14 +265,14 @@ struct panfrost_dump_object_header { · 1 unmodified line | ||
| 261 | 265 | * with new fields and also keep it 512-byte aligned |
| 262 | 266 | */ |
| 263 | 267 | |
| 264 | − __le32 sizer[496]; | |
| 268 | + __u32 sizer[496]; | |
| 265 | 269 | }; |
| 266 | 270 | }; |
| 267 | 271 | |
| 268 | 272 | /* Registers object, an array of these */ |
| 269 | 273 | struct panfrost_dump_registers { |
| 270 | − __le32 reg; | |
| 271 | − __le32 value; | |
| 274 | + __u32 reg; | |
| 275 | + __u32 value; | |
| 272 | 276 | }; |
| 273 | 277 | |
| 274 | 278 | #if defined(__cplusplus) |
| @@ -187,7 +187,7 @@ · 186 unmodified lines | ||
| 187 | 187 | #define AUDIT_MAX_KEY_LEN 256 |
| 188 | 188 | #define AUDIT_BITMASK_SIZE 64 |
| 189 | 189 | #define AUDIT_WORD(nr) ((__u32)((nr)/32)) |
| 190 | −#define AUDIT_BIT(nr) (1 << ((nr) - AUDIT_WORD(nr)*32)) | |
| 190 | +#define AUDIT_BIT(nr) (1U << ((nr) - AUDIT_WORD(nr)*32)) | |
| 191 | 191 | |
| 192 | 192 | #define AUDIT_SYSCALL_CLASSES 16 |
| 193 | 193 | #define AUDIT_CLASS_DIR_WRITE 0 |
| @@ -426,7 +426,7 @@ struct vfs_ns_cap_data { · 425 unmodified lines | ||
| 426 | 426 | */ |
| 427 | 427 | |
| 428 | 428 | #define CAP_TO_INDEX(x) ((x) >> 5) /* 1 << 5 == bits in __u32 */ |
| 429 | −#define CAP_TO_MASK(x) (1 << ((x) & 31)) /* mask for indexed __u32 */ | |
| 429 | +#define CAP_TO_MASK(x) (1U << ((x) & 31)) /* mask for indexed __u32 */ | |
| 430 | 430 | |
| 431 | 431 | |
| 432 | 432 | #endif /* _UAPI_LINUX_CAPABILITY_H */ |
| @@ -1568,6 +1568,20 @@ static inline void cec_ops_request_short_audio_descriptor(const struct cec_msg * · 1567 unmodified lines | ||
| 1568 | 1568 | } |
| 1569 | 1569 | } |
| 1570 | 1570 | |
| 1571 | +static inline void cec_msg_set_audio_volume_level(struct cec_msg *msg, | |
| 1572 | + __u8 audio_volume_level) | |
| 1573 | +{ | |
| 1574 | + msg->len = 3; | |
| 1575 | + msg->msg[1] = CEC_MSG_SET_AUDIO_VOLUME_LEVEL; | |
| 1576 | + msg->msg[2] = audio_volume_level; | |
| 1577 | +} | |
| 1578 | + | |
| 1579 | +static inline void cec_ops_set_audio_volume_level(const struct cec_msg *msg, | |
| 1580 | + __u8 *audio_volume_level) | |
| 1581 | +{ | |
| 1582 | + *audio_volume_level = msg->msg[2]; | |
| 1583 | +} | |
| 1584 | + | |
| 1571 | 1585 | |
| 1572 | 1586 | /* Audio Rate Control Feature */ |
| 1573 | 1587 | static inline void cec_msg_set_audio_rate(struct cec_msg *msg, |
| @@ -768,6 +768,7 @@ struct cec_event { · 767 unmodified lines | ||
| 768 | 768 | #define CEC_OP_FEAT_DEV_HAS_SET_AUDIO_RATE 0x08 |
| 769 | 769 | #define CEC_OP_FEAT_DEV_SINK_HAS_ARC_TX 0x04 |
| 770 | 770 | #define CEC_OP_FEAT_DEV_SOURCE_HAS_ARC_RX 0x02 |
| 771 | +#define CEC_OP_FEAT_DEV_HAS_SET_AUDIO_VOLUME_LEVEL 0x01 | |
| 771 | 772 | |
| 772 | 773 | #define CEC_MSG_GIVE_FEATURES 0xa5 /* HDMI 2.0 */ |
| 773 | 774 | |
| @@ -1059,6 +1060,7 @@ struct cec_event { · 285 unmodified lines | ||
| 1059 | 1060 | #define CEC_OP_AUD_FMT_ID_CEA861 0 |
| 1060 | 1061 | #define CEC_OP_AUD_FMT_ID_CEA861_CXT 1 |
| 1061 | 1062 | |
| 1063 | +#define CEC_MSG_SET_AUDIO_VOLUME_LEVEL 0x73 | |
| 1062 | 1064 | |
| 1063 | 1065 | /* Audio Rate Control Feature */ |
| 1064 | 1066 | #define CEC_MSG_SET_AUDIO_RATE 0x9a |
| @@ -29,6 +29,7 @@ enum idxd_scmd_stat { · 28 unmodified lines | ||
| 29 | 29 | IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, |
| 30 | 30 | IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, |
| 31 | 31 | IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, |
| 32 | + IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000, | |
| 32 | 33 | }; |
| 33 | 34 | |
| 34 | 35 | #define IDXD_SCMD_SOFTERR_MASK 0x80000000 |
| @@ -20,6 +20,7 @@ · 19 unmodified lines | ||
| 20 | 20 | #define _UAPI_LINUX_IN_H |
| 21 | 21 | |
| 22 | 22 | #include <linux/types.h> |
| 23 | +#include <linux/stddef.h> | |
| 23 | 24 | #include <linux/libc-compat.h> |
| 24 | 25 | #include <linux/socket.h> |
| 25 | 26 | |
| @@ -222,7 +222,7 @@ enum io_uring_op { · 221 unmodified lines | ||
| 222 | 222 | |
| 223 | 223 | /* |
| 224 | 224 | * sqe->uring_cmd_flags |
| 225 | − * IORING_URING_CMD_FIXED use registered buffer; pass thig flag | |
| 225 | + * IORING_URING_CMD_FIXED use registered buffer; pass this flag | |
| 226 | 226 | * along with setting sqe->buf_index. |
| 227 | 227 | */ |
| 228 | 228 | #define IORING_URING_CMD_FIXED (1U << 0) |
| @@ -100,8 +100,10 @@ struct iphdr { · 99 unmodified lines | ||
| 100 | 100 | __u8 ttl; |
| 101 | 101 | __u8 protocol; |
| 102 | 102 | __sum16 check; |
| 103 | − __be32 saddr; | |
| 104 | − __be32 daddr; | |
| 103 | + __struct_group(/* no tag */, addrs, /* no attrs */, | |
| 104 | + __be32 saddr; | |
| 105 | + __be32 daddr; | |
| 106 | + ); | |
| 105 | 107 | /*The options start here. */ |
| 106 | 108 | }; |
| 107 | 109 | |
| @@ -130,8 +130,10 @@ struct ipv6hdr { · 129 unmodified lines | ||
| 130 | 130 | __u8 nexthdr; |
| 131 | 131 | __u8 hop_limit; |
| 132 | 132 | |
| 133 | − struct in6_addr saddr; | |
| 134 | − struct in6_addr daddr; | |
| 133 | + __struct_group(/* no tag */, addrs, /* no attrs */, | |
| 134 | + struct in6_addr saddr; | |
| 135 | + struct in6_addr daddr; | |
| 136 | + ); | |
| 135 | 137 | }; |
| 136 | 138 | |
| 137 | 139 | |
| @@ -1337,7 +1337,7 @@ union perf_mem_data_src { · 1336 unmodified lines | ||
| 1337 | 1337 | #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ |
| 1338 | 1338 | #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ |
| 1339 | 1339 | /* 5-0x8 available */ |
| 1340 | −#define PERF_MEM_LVLNUM_EXTN_MEM 0x09 /* Extension memory */ | |
| 1340 | +#define PERF_MEM_LVLNUM_CXL 0x09 /* CXL */ | |
| 1341 | 1341 | #define PERF_MEM_LVLNUM_IO 0x0a /* I/O */ |
| 1342 | 1342 | #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ |
| 1343 | 1343 | #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ |
| @@ -117,7 +117,46 @@ · 116 unmodified lines | ||
| 117 | 117 | /* |
| 118 | 118 | * Defect Pixel Cluster Correction |
| 119 | 119 | */ |
| 120 | −#define RKISP1_CIF_ISP_DPCC_METHODS_MAX 3 | |
| 120 | +#define RKISP1_CIF_ISP_DPCC_METHODS_MAX 3 | |
| 121 | + | |
| 122 | +#define RKISP1_CIF_ISP_DPCC_MODE_STAGE1_ENABLE (1U << 2) | |
| 123 | + | |
| 124 | +#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_INCL_G_CENTER (1U << 0) | |
| 125 | +#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_INCL_RB_CENTER (1U << 1) | |
| 126 | +#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_G_3X3 (1U << 2) | |
| 127 | +#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_RB_3X3 (1U << 3) | |
| 128 | + | |
| 129 | +/* 0-2 for sets 1-3 */ | |
| 130 | +#define RKISP1_CIF_ISP_DPCC_SET_USE_STAGE1_USE_SET(n) ((n) << 0) | |
| 131 | +#define RKISP1_CIF_ISP_DPCC_SET_USE_STAGE1_USE_FIX_SET (1U << 3) | |
| 132 | + | |
| 133 | +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_PG_GREEN_ENABLE (1U << 0) | |
| 134 | +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_LC_GREEN_ENABLE (1U << 1) | |
| 135 | +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RO_GREEN_ENABLE (1U << 2) | |
| 136 | +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RND_GREEN_ENABLE (1U << 3) | |
| 137 | +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RG_GREEN_ENABLE (1U << 4) | |
| 138 | +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_PG_RED_BLUE_ENABLE (1U << 8) | |
| 139 | +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_LC_RED_BLUE_ENABLE (1U << 9) | |
| 140 | +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RO_RED_BLUE_ENABLE (1U << 10) | |
| 141 | +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RND_RED_BLUE_ENABLE (1U << 11) | |
| 142 | +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RG_RED_BLUE_ENABLE (1U << 12) | |
| 143 | + | |
| 144 | +#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_G(v) ((v) << 0) | |
| 145 | +#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_RB(v) ((v) << 8) | |
| 146 | +#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_G(v) ((v) << 0) | |
| 147 | +#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_RB(v) ((v) << 8) | |
| 148 | +#define RKISP1_CIF_ISP_DPCC_PG_FAC_G(v) ((v) << 0) | |
| 149 | +#define RKISP1_CIF_ISP_DPCC_PG_FAC_RB(v) ((v) << 8) | |
| 150 | +#define RKISP1_CIF_ISP_DPCC_RND_THRESH_G(v) ((v) << 0) | |
| 151 | +#define RKISP1_CIF_ISP_DPCC_RND_THRESH_RB(v) ((v) << 8) | |
| 152 | +#define RKISP1_CIF_ISP_DPCC_RG_FAC_G(v) ((v) << 0) | |
| 153 | +#define RKISP1_CIF_ISP_DPCC_RG_FAC_RB(v) ((v) << 8) | |
| 154 | + | |
| 155 | +#define RKISP1_CIF_ISP_DPCC_RO_LIMITS_n_G(n, v) ((v) << ((n) * 4)) | |
| 156 | +#define RKISP1_CIF_ISP_DPCC_RO_LIMITS_n_RB(n, v) ((v) << ((n) * 4 + 2)) | |
| 157 | + | |
| 158 | +#define RKISP1_CIF_ISP_DPCC_RND_OFFS_n_G(n, v) ((v) << ((n) * 4)) | |
| 159 | +#define RKISP1_CIF_ISP_DPCC_RND_OFFS_n_RB(n, v) ((v) << ((n) * 4 + 2)) | |
| 121 | 160 | |
| 122 | 161 | /* |
| 123 | 162 | * Denoising pre filter |
| @@ -249,16 +288,20 @@ struct rkisp1_cif_isp_bls_config { · 125 unmodified lines | ||
| 249 | 288 | }; |
| 250 | 289 | |
| 251 | 290 | /** |
| 252 | − * struct rkisp1_cif_isp_dpcc_methods_config - Methods Configuration used by DPCC | |
| 291 | + * struct rkisp1_cif_isp_dpcc_methods_config - DPCC methods set configuration | |
| 253 | 292 | * |
| 254 | − * Methods Configuration used by Defect Pixel Cluster Correction | |
| 293 | + * This structure stores the configuration of one set of methods for the DPCC | |
| 294 | + * algorithm. Multiple methods can be selected in each set (independently for | |
| 295 | + * the Green and Red/Blue components) through the @method field, the result is | |
| 296 | + * the logical AND of all enabled methods. The remaining fields set thresholds | |
| 297 | + * and factors for each method. | |
| 255 | 298 | * |
| 256 | − * @method: Method enable bits | |
| 257 | − * @line_thresh: Line threshold | |
| 258 | − * @line_mad_fac: Line MAD factor | |
| 259 | − * @pg_fac: Peak gradient factor | |
| 260 | − * @rnd_thresh: Rank Neighbor Difference threshold | |
| 261 | − * @rg_fac: Rank gradient factor | |
| 299 | + * @method: Method enable bits (RKISP1_CIF_ISP_DPCC_METHODS_SET_*) | |
| 300 | + * @line_thresh: Line threshold (RKISP1_CIF_ISP_DPCC_LINE_THRESH_*) | |
| 301 | + * @line_mad_fac: Line Mean Absolute Difference factor (RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_*) | |
| 302 | + * @pg_fac: Peak gradient factor (RKISP1_CIF_ISP_DPCC_PG_FAC_*) | |
| 303 | + * @rnd_thresh: Rank Neighbor Difference threshold (RKISP1_CIF_ISP_DPCC_RND_THRESH_*) | |
| 304 | + * @rg_fac: Rank gradient factor (RKISP1_CIF_ISP_DPCC_RG_FAC_*) | |
| 262 | 305 | */ |
| 263 | 306 | struct rkisp1_cif_isp_dpcc_methods_config { |
| 264 | 307 | __u32 method; |
| @@ -272,14 +315,16 @@ struct rkisp1_cif_isp_dpcc_methods_config { · 7 unmodified lines | ||
| 272 | 315 | /** |
| 273 | 316 | * struct rkisp1_cif_isp_dpcc_config - Configuration used by DPCC |
| 274 | 317 | * |
| 275 | − * Configuration used by Defect Pixel Cluster Correction | |
| 318 | + * Configuration used by Defect Pixel Cluster Correction. Three sets of methods | |
| 319 | + * can be configured and selected through the @set_use field. The result is the | |
| 320 | + * logical OR of all enabled sets. | |
| 276 | 321 | * |
| 277 | − * @mode: dpcc output mode | |
| 278 | − * @output_mode: whether use hard coded methods | |
| 279 | − * @set_use: stage1 methods set | |
| 280 | − * @methods: methods config | |
| 281 | − * @ro_limits: rank order limits | |
| 282 | − * @rnd_offs: differential rank offsets for rank neighbor difference | |
| 322 | + * @mode: DPCC mode (RKISP1_CIF_ISP_DPCC_MODE_*) | |
| 323 | + * @output_mode: Interpolation output mode (RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_*) | |
| 324 | + * @set_use: Methods sets selection (RKISP1_CIF_ISP_DPCC_SET_USE_*) | |
| 325 | + * @methods: Methods sets configuration | |
| 326 | + * @ro_limits: Rank order limits (RKISP1_CIF_ISP_DPCC_RO_LIMITS_*) | |
| 327 | + * @rnd_offs: Differential rank offsets for rank neighbor difference (RKISP1_CIF_ISP_DPCC_RND_OFFS_*) | |
| 283 | 328 | */ |
| 284 | 329 | struct rkisp1_cif_isp_dpcc_config { |
| 285 | 330 | __u32 mode; |
| @@ -1601,7 +1601,8 @@ struct v4l2_bt_timings { · 1600 unmodified lines | ||
| 1601 | 1601 | ((bt)->width + V4L2_DV_BT_BLANKING_WIDTH(bt)) |
| 1602 | 1602 | #define V4L2_DV_BT_BLANKING_HEIGHT(bt) \ |
| 1603 | 1603 | ((bt)->vfrontporch + (bt)->vsync + (bt)->vbackporch + \ |
| 1604 | − (bt)->il_vfrontporch + (bt)->il_vsync + (bt)->il_vbackporch) | |
| 1604 | + ((bt)->interlaced ? \ | |
| 1605 | + ((bt)->il_vfrontporch + (bt)->il_vsync + (bt)->il_vbackporch) : 0)) | |
| 1605 | 1606 | #define V4L2_DV_BT_FRAME_HEIGHT(bt) \ |
| 1606 | 1607 | ((bt)->height + V4L2_DV_BT_BLANKING_HEIGHT(bt)) |
| 1607 | 1608 | |
| @@ -191,6 +191,33 @@ enum ar_event_types { · 190 unmodified lines | ||
| 191 | 191 | #define AR_TKN_U32_MODULE_SRC_INSTANCE_ID 208 |
| 192 | 192 | #define AR_TKN_U32_MODULE_DST_INSTANCE_ID 209 |
| 193 | 193 | |
| 194 | +#define AR_TKN_U32_MODULE_SRC_OP_PORT_ID1 210 | |
| 195 | +#define AR_TKN_U32_MODULE_DST_IN_PORT_ID1 211 | |
| 196 | +#define AR_TKN_U32_MODULE_DST_INSTANCE_ID1 212 | |
| 197 | + | |
| 198 | +#define AR_TKN_U32_MODULE_SRC_OP_PORT_ID2 213 | |
| 199 | +#define AR_TKN_U32_MODULE_DST_IN_PORT_ID2 214 | |
| 200 | +#define AR_TKN_U32_MODULE_DST_INSTANCE_ID2 215 | |
| 201 | + | |
| 202 | +#define AR_TKN_U32_MODULE_SRC_OP_PORT_ID3 216 | |
| 203 | +#define AR_TKN_U32_MODULE_DST_IN_PORT_ID3 217 | |
| 204 | +#define AR_TKN_U32_MODULE_DST_INSTANCE_ID3 218 | |
| 205 | + | |
| 206 | +#define AR_TKN_U32_MODULE_SRC_OP_PORT_ID4 219 | |
| 207 | +#define AR_TKN_U32_MODULE_DST_IN_PORT_ID4 220 | |
| 208 | +#define AR_TKN_U32_MODULE_DST_INSTANCE_ID4 221 | |
| 209 | + | |
| 210 | +#define AR_TKN_U32_MODULE_SRC_OP_PORT_ID5 222 | |
| 211 | +#define AR_TKN_U32_MODULE_DST_IN_PORT_ID5 223 | |
| 212 | +#define AR_TKN_U32_MODULE_DST_INSTANCE_ID5 224 | |
| 213 | + | |
| 214 | +#define AR_TKN_U32_MODULE_SRC_OP_PORT_ID6 225 | |
| 215 | +#define AR_TKN_U32_MODULE_DST_IN_PORT_ID6 226 | |
| 216 | +#define AR_TKN_U32_MODULE_DST_INSTANCE_ID6 227 | |
| 217 | + | |
| 218 | +#define AR_TKN_U32_MODULE_SRC_OP_PORT_ID7 228 | |
| 219 | +#define AR_TKN_U32_MODULE_DST_IN_PORT_ID7 229 | |
| 220 | +#define AR_TKN_U32_MODULE_DST_INSTANCE_ID7 230 | |
| 194 | 221 | |
| 195 | 222 | #define AR_TKN_U32_MODULE_HW_IF_IDX 250 |
| 196 | 223 | #define AR_TKN_U32_MODULE_HW_IF_TYPE 251 |
| @@ -88,6 +88,15 @@ · 87 unmodified lines | ||
| 88 | 88 | #define SOF_TKN_COMP_CPC 406 |
| 89 | 89 | #define SOF_TKN_COMP_IS_PAGES 409 |
| 90 | 90 | #define SOF_TKN_COMP_NUM_AUDIO_FORMATS 410 |
| 91 | +#define SOF_TKN_COMP_NUM_SINK_PINS 411 | |
| 92 | +#define SOF_TKN_COMP_NUM_SOURCE_PINS 412 | |
| 93 | +/* | |
| 94 | + * The token for sink/source pin binding, it specifies the widget | |
| 95 | + * name that the sink/source pin is connected from/to. | |
| 96 | + */ | |
| 97 | +#define SOF_TKN_COMP_SINK_PIN_BINDING_WNAME 413 | |
| 98 | +#define SOF_TKN_COMP_SRC_PIN_BINDING_WNAME 414 | |
| 99 | + | |
| 91 | 100 | |
| 92 | 101 | /* SSP */ |
| 93 | 102 | #define SOF_TKN_INTEL_SSP_CLKS_CONTROL 500 |
| @@ -189,4 +198,9 @@ · 95 unmodified lines | ||
| 189 | 198 | /* COPIER */ |
| 190 | 199 | #define SOF_TKN_INTEL_COPIER_NODE_TYPE 1980 |
| 191 | 200 | |
| 201 | +/* ACP I2S */ | |
| 202 | +#define SOF_TKN_AMD_ACPI2S_RATE 1700 | |
| 203 | +#define SOF_TKN_AMD_ACPI2S_CH 1701 | |
| 204 | +#define SOF_TKN_AMD_ACPI2S_TDM_MODE 1702 | |
| 205 | + | |
| 192 | 206 | #endif |