lael-labs/linux

Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml+83−0

@@ -0,0 +1,83 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Allwinner F1C100s USB PHY
	8
	9	maintainers:
	10	- Chen-Yu Tsai <wens@csie.org>
	11	- Maxime Ripard <mripard@kernel.org>
	12
	13	properties:
	14	"#phy-cells":
	15	const: 1
	16
	17	compatible:
	18	const: allwinner,suniv-f1c100s-usb-phy
	19
	20	reg:
	21	maxItems: 1
	22	description: PHY Control registers
	23
	24	reg-names:
	25	const: phy_ctrl
	26
	27	clocks:
	28	maxItems: 1
	29	description: USB OTG PHY bus clock
	30
	31	clock-names:
	32	const: usb0_phy
	33
	34	resets:
	35	maxItems: 1
	36	description: USB OTG reset
	37
	38	reset-names:
	39	const: usb0_reset
	40
	41	usb0_id_det-gpios:
	42	maxItems: 1
	43	description: GPIO to the USB OTG ID pin
	44
	45	usb0_vbus_det-gpios:
	46	maxItems: 1
	47	description: GPIO to the USB OTG VBUS detect pin
	48
	49	usb0_vbus_power-supply:
	50	description: Power supply to detect the USB OTG VBUS
	51
	52	usb0_vbus-supply:
	53	description: Regulator controlling USB OTG VBUS
	54
	55	required:
	56	- "#phy-cells"
	57	- compatible
	58	- clocks
	59	- clock-names
	60	- reg
	61	- reg-names
	62	- resets
	63	- reset-names
	64
	65	additionalProperties: false
	66
	67	examples:
	68	- \|
	69	#include <dt-bindings/gpio/gpio.h>
	70	#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
	71	#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
	72
	73	phy@1c13400 {
	74	compatible = "allwinner,suniv-f1c100s-usb-phy";
	75	reg = <0x01c13400 0x10>;
	76	reg-names = "phy_ctrl";
	77	clocks = <&ccu CLK_USB_PHY0>;
	78	clock-names = "usb0_phy";
	79	resets = <&ccu RST_USB_PHY0>;
	80	reset-names = "usb0_reset";
	81	#phy-cells = <1>;
	82	usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
	83	};

Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml+5−0

   "#phy-cells":
     const: 1
+  phy-supply:
+    description:
+      Phandle to a regulator that provides power to the PHY. This
+      regulator will be managed during the PHY power on/off sequence.
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml+56−0

@@ -0,0 +1,56 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/phy/amlogic,meson-gxl-usb2-phy.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Amlogic Meson GXL USB2 PHY
	8
	9	maintainers:
	10	- Neil Armstrong <neil.armstrong@linaro.org>
	11
	12	properties:
	13	compatible:
	14	const: amlogic,meson-gxl-usb2-phy
	15
	16	reg:
	17	maxItems: 1
	18
	19	clocks:
	20	maxItems: 1
	21
	22	clock-names:
	23	items:
	24	- const: phy
	25
	26	resets:
	27	maxItems: 1
	28
	29	reset-names:
	30	items:
	31	- const: phy
	32
	33	"#phy-cells":
	34	const: 0
	35
	36	phy-supply: true
	37
	38	required:
	39	- compatible
	40	- reg
	41	- "#phy-cells"
	42
	43	additionalProperties: false
	44
	45	examples:
	46	- \|
	47	phy@78000 {
	48	compatible = "amlogic,meson-gxl-usb2-phy";
	49	reg = <0x78000 0x20>;
	50	clocks = <&xtal>;
	51	clock-names = "phy";
	52	resets = <&phy_reset>;
	53	reset-names = "phy";
	54	#phy-cells = <0>;
	55	phy-supply = <&usb2_supply>;
	56	};

Documentation/devicetree/bindings/phy/mediatek,tphy.yaml+1−0

@@ -79,6 +79,7 @@ properties: · 78 unmodified lines
79	- enum:	79	- enum:
80	- mediatek,mt2712-tphy	80	- mediatek,mt2712-tphy
81	- mediatek,mt7629-tphy	81	- mediatek,mt7629-tphy
		82	- mediatek,mt7986-tphy
82	- mediatek,mt8183-tphy	83	- mediatek,mt8183-tphy
83	- mediatek,mt8186-tphy	84	- mediatek,mt8186-tphy
84	- mediatek,mt8192-tphy	85	- mediatek,mt8192-tphy

Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt+0−21

@@ -1,21 +0,0 @@
1	* Amlogic Meson GXL and GXM USB2 PHY binding
2
3	Required properties:
4	- compatible: Should be "amlogic,meson-gxl-usb2-phy"
5	- reg: The base address and length of the registers
6	- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
7
8	Optional properties:
9	- clocks: a phandle to the clock of this PHY
10	- clock-names: must be "phy"
11	- resets: a phandle to the reset line of this PHY
12	- reset-names: must be "phy"
13	- phy-supply: see phy-bindings.txt in this directory
14
15
16	Example:
17	usb2_phy0: phy@78000 {
18	compatible = "amlogic,meson-gxl-usb2-phy";
19	#phy-cells = <0>;
20	reg = <0x0 0x78000 0x0 0x20>;
21	};

Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt+0−779

@@ -1,779 +0,0 @@
1	Device tree binding for NVIDIA Tegra XUSB pad controller
2	========================================================
3
4	The Tegra XUSB pad controller manages a set of I/O lanes (with differential
5	signals) which connect directly to pins/pads on the SoC package. Each lane
6	is controlled by a HW block referred to as a "pad" in the Tegra hardware
7	documentation. Each such "pad" may control either one or multiple lanes,
8	and thus contains any logic common to all its lanes. Each lane can be
9	separately configured and powered up.
10
11	Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12	super-speed USB. Other lanes are for various types of low-speed, full-speed
13	or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14	contains a software-configurable mux that sits between the I/O controller
15	ports (e.g. PCIe) and the lanes.
16
17	In addition to per-lane configuration, USB 3.0 ports may require additional
18	settings on a per-board basis.
19
20	Pads will be represented as children of the top-level XUSB pad controller
21	device tree node. Each lane exposed by the pad will be represented by its
22	own subnode and can be referenced by users of the lane using the standard
23	PHY bindings, as described by the phy-bindings.txt file in this directory.
24
25	The Tegra hardware documentation refers to the connection between the XUSB
26	pad controller and the XUSB controller as "ports". This is confusing since
27	"port" is typically used to denote the physical USB receptacle. The device
28	tree binding in this document uses the term "port" to refer to the logical
29	abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
30	for the USB signal, the VBUS power supply, the USB 2.0 companion port for
31	USB 3.0 receptacles, ...).
32
33	Required properties:
34	--------------------
35	- compatible: Must be:
36	- Tegra124: "nvidia,tegra124-xusb-padctl"
37	- Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
38	- Tegra210: "nvidia,tegra210-xusb-padctl"
39	- Tegra186: "nvidia,tegra186-xusb-padctl"
40	- Tegra194: "nvidia,tegra194-xusb-padctl"
41	- reg: Physical base address and length of the controller's registers.
42	- resets: Must contain an entry for each entry in reset-names.
43	- reset-names: Must include the following entries:
44	- "padctl"
45
46	For Tegra124:
47	- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
48	- avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
49	- avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
50	- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
51
52	For Tegra210:
53	- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
54	- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
55	- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
56	- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
57	- nvidia,pmc: phandle and specifier referring to the Tegra210 PMC node.
58
59	For Tegra186:
60	- avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
61	power supply. Must supply 1.8 V.
62	- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
63	3.3 V.
64	- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
65	- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
66
67	For Tegra194:
68	- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
69	3.3 V.
70	- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
71
72	Pad nodes:
73	==========
74
75	A required child node named "pads" contains a list of subnodes, one for each
76	of the pads exposed by the XUSB pad controller. Each pad may need additional
77	resources that can be referenced in its pad node.
78
79	The "status" property is used to enable or disable the use of a pad. If set
80	to "disabled", the pad will not be used on the given board. In order to use
81	the pad and any of its lanes, this property must be set to "okay".
82
83	For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
84	and sata. No extra resources are required for operation of these pads.
85
86	For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
87	a description of the properties of each pad.
88
89	UTMI pad:
90	---------
91
92	Required properties:
93	- clocks: Must contain an entry for each entry in clock-names.
94	- clock-names: Must contain the following entries:
95	- "trk": phandle and specifier referring to the USB2 tracking clock
96
97	HSIC pad:
98	---------
99
100	Required properties:
101	- clocks: Must contain an entry for each entry in clock-names.
102	- clock-names: Must contain the following entries:
103	- "trk": phandle and specifier referring to the HSIC tracking clock
104
105	PCIe pad:
106	---------
107
108	Required properties:
109	- clocks: Must contain an entry for each entry in clock-names.
110	- clock-names: Must contain the following entries:
111	- "pll": phandle and specifier referring to the PLLE
112	- resets: Must contain an entry for each entry in reset-names.
113	- reset-names: Must contain the following entries:
114	- "phy": reset for the PCIe UPHY block
115
116	SATA pad:
117	---------
118
119	Required properties:
120	- resets: Must contain an entry for each entry in reset-names.
121	- reset-names: Must contain the following entries:
122	- "phy": reset for the SATA UPHY block
123
124
125	PHY nodes:
126	==========
127
128	Each pad node has a child named "lanes" that contains one or more children of
129	its own, each representing one of the lanes controlled by the pad.
130
131	Required properties:
132	--------------------
133	- status: Defines the operation status of the PHY. Valid values are:
134	- "disabled": the PHY is disabled
135	- "okay": the PHY is enabled
136	- #phy-cells: Should be 0. Since each lane represents a single PHY, there is
137	no need for an additional specifier.
138	- nvidia,function: The output function of the PHY. See below for a list of
139	valid functions per SoC generation.
140
141	For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
142	- usb2: usb2-0, usb2-1, usb2-2
143	- functions: "snps", "xusb", "uart"
144	- ulpi: ulpi-0
145	- functions: "snps", "xusb"
146	- hsic: hsic-0, hsic-1
147	- functions: "snps", "xusb"
148	- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
149	- functions: "pcie", "usb3-ss"
150	- sata: sata-0
151	- functions: "usb3-ss", "sata"
152
153	For Tegra210, the list of valid PHY nodes is given below:
154	- usb2: usb2-0, usb2-1, usb2-2, usb2-3
155	- functions: "snps", "xusb", "uart"
156	- hsic: hsic-0, hsic-1
157	- functions: "snps", "xusb"
158	- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
159	- functions: "pcie-x1", "usb3-ss", "pcie-x4"
160	- sata: sata-0
161	- functions: "usb3-ss", "sata"
162
163	For Tegra194, the list of valid PHY nodes is given below:
164	- usb2: usb2-0, usb2-1, usb2-2, usb2-3
165	- functions: "xusb"
166	- usb3: usb3-0, usb3-1, usb3-2, usb3-3
167	- functions: "xusb"
168
169	Port nodes:
170	===========
171
172	A required child node named "ports" contains a list of all the ports exposed
173	by the XUSB pad controller. Per-port configuration is only required for USB.
174
175	USB2 ports:
176	-----------
177
178	Required properties:
179	- status: Defines the operation status of the port. Valid values are:
180	- "disabled": the port is disabled
181	- "okay": the port is enabled
182	- mode: A string that determines the mode in which to run the port. Valid
183	values are:
184	- "host": for USB host mode
185	- "device": for USB device mode
186	- "otg": for USB OTG mode
187
188	Required properties for OTG/Peripheral capable USB2 ports:
189	- usb-role-switch: Boolean property to indicate that the port support OTG or
190	peripheral mode. If present, the port supports switching between USB host
191	and peripheral roles. Connector should be added as subnode.
192	See usb/usb-conn-gpio.txt.
193
194	Optional properties:
195	- nvidia,internal: A boolean property whose presence determines that a port
196	is internal. In the absence of this property the port is considered to be
197	external.
198	- vbus-supply: phandle to a regulator supplying the VBUS voltage.
199
200	ULPI ports:
201	-----------
202
203	Optional properties:
204	- status: Defines the operation status of the port. Valid values are:
205	- "disabled": the port is disabled
206	- "okay": the port is enabled
207	- nvidia,internal: A boolean property whose presence determines that a port
208	is internal. In the absence of this property the port is considered to be
209	external.
210	- vbus-supply: phandle to a regulator supplying the VBUS voltage.
211
212	HSIC ports:
213	-----------
214
215	Required properties:
216	- status: Defines the operation status of the port. Valid values are:
217	- "disabled": the port is disabled
218	- "okay": the port is enabled
219
220	Optional properties:
221	- vbus-supply: phandle to a regulator supplying the VBUS voltage.
222
223	Super-speed USB ports:
224	----------------------
225
226	Required properties:
227	- status: Defines the operation status of the port. Valid values are:
228	- "disabled": the port is disabled
229	- "okay": the port is enabled
230	- nvidia,usb2-companion: A single cell that specifies the physical port number
231	to map this super-speed USB port to. The range of valid port numbers varies
232	with the SoC generation:
233	- 0-2: for Tegra124 and Tegra132
234	- 0-3: for Tegra210
235
236	Optional properties:
237	- nvidia,internal: A boolean property whose presence determines that a port
238	is internal. In the absence of this property the port is considered to be
239	external.
240
241	- maximum-speed: Only for Tegra194. A string property that specifies maximum
242	supported speed of a usb3 port. Valid values are:
243	- "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
244	- "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
245
246	For Tegra124 and Tegra132, the XUSB pad controller exposes the following
247	ports:
248	- 3x USB2: usb2-0, usb2-1, usb2-2
249	- 1x ULPI: ulpi-0
250	- 2x HSIC: hsic-0, hsic-1
251	- 2x super-speed USB: usb3-0, usb3-1
252
253	For Tegra210, the XUSB pad controller exposes the following ports:
254	- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
255	- 2x HSIC: hsic-0, hsic-1
256	- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
257
258	For Tegra194, the XUSB pad controller exposes the following ports:
259	- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
260	- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
261
262	Examples:
263	=========
264
265	Tegra124 and Tegra132:
266	----------------------
267
268	SoC include:
269
270	padctl@7009f000 {
271	/* for Tegra124 */
272	compatible = "nvidia,tegra124-xusb-padctl";
273	/* for Tegra132 */
274	compatible = "nvidia,tegra132-xusb-padctl",
275	"nvidia,tegra124-xusb-padctl";
276	reg = <0x0 0x7009f000 0x0 0x1000>;
277	resets = <&tegra_car 142>;
278	reset-names = "padctl";
279
280	pads {
281	usb2 {
282	status = "disabled";
283
284	lanes {
285	usb2-0 {
286	status = "disabled";
287	#phy-cells = <0>;
288	};
289
290	usb2-1 {
291	status = "disabled";
292	#phy-cells = <0>;
293	};
294
295	usb2-2 {
296	status = "disabled";
297	#phy-cells = <0>;
298	};
299	};
300	};
301
302	ulpi {
303	status = "disabled";
304
305	lanes {
306	ulpi-0 {
307	status = "disabled";
308	#phy-cells = <0>;
309	};
310	};
311	};
312
313	hsic {
314	status = "disabled";
315
316	lanes {
317	hsic-0 {
318	status = "disabled";
319	#phy-cells = <0>;
320	};
321
322	hsic-1 {
323	status = "disabled";
324	#phy-cells = <0>;
325	};
326	};
327	};
328
329	pcie {
330	status = "disabled";
331
332	lanes {
333	pcie-0 {
334	status = "disabled";
335	#phy-cells = <0>;
336	};
337
338	pcie-1 {
339	status = "disabled";
340	#phy-cells = <0>;
341	};
342
343	pcie-2 {
344	status = "disabled";
345	#phy-cells = <0>;
346	};
347
348	pcie-3 {
349	status = "disabled";
350	#phy-cells = <0>;
351	};
352
353	pcie-4 {
354	status = "disabled";
355	#phy-cells = <0>;
356	};
357	};
358	};
359
360	sata {
361	status = "disabled";
362
363	lanes {
364	sata-0 {
365	status = "disabled";
366	#phy-cells = <0>;
367	};
368	};
369	};
370	};
371
372	ports {
373	usb2-0 {
374	status = "disabled";
375	};
376
377	usb2-1 {
378	status = "disabled";
379	};
380
381	usb2-2 {
382	status = "disabled";
383	};
384
385	ulpi-0 {
386	status = "disabled";
387	};
388
389	hsic-0 {
390	status = "disabled";
391	};
392
393	hsic-1 {
394	status = "disabled";
395	};
396
397	usb3-0 {
398	status = "disabled";
399	};
400
401	usb3-1 {
402	status = "disabled";
403	};
404	};
405	};
406
407	Board file:
408
409	padctl@7009f000 {
410	status = "okay";
411
412	pads {
413	usb2 {
414	status = "okay";
415
416	lanes {
417	usb2-0 {
418	nvidia,function = "xusb";
419	status = "okay";
420	};
421
422	usb2-1 {
423	nvidia,function = "xusb";
424	status = "okay";
425	};
426
427	usb2-2 {
428	nvidia,function = "xusb";
429	status = "okay";
430	};
431	};
432	};
433
434	pcie {
435	status = "okay";
436
437	lanes {
438	pcie-0 {
439	nvidia,function = "usb3-ss";
440	status = "okay";
441	};
442
443	pcie-2 {
444	nvidia,function = "pcie";
445	status = "okay";
446	};
447
448	pcie-4 {
449	nvidia,function = "pcie";
450	status = "okay";
451	};
452	};
453	};
454
455	sata {
456	status = "okay";
457
458	lanes {
459	sata-0 {
460	nvidia,function = "sata";
461	status = "okay";
462	};
463	};
464	};
465	};
466
467	ports {
468	/* Micro A/B */
469	usb2-0 {
470	status = "okay";
471	mode = "otg";
472	};
473
474	/* Mini PCIe */
475	usb2-1 {
476	status = "okay";
477	mode = "host";
478	};
479
480	/* USB3 */
481	usb2-2 {
482	status = "okay";
483	mode = "host";
484
485	vbus-supply = <&vdd_usb3_vbus>;
486	};
487
488	usb3-0 {
489	nvidia,port = <2>;
490	status = "okay";
491	};
492	};
493	};
494
495	Tegra210:
496	---------
497
498	SoC include:
499
500	padctl@7009f000 {
501	compatible = "nvidia,tegra210-xusb-padctl";
502	reg = <0x0 0x7009f000 0x0 0x1000>;
503	resets = <&tegra_car 142>;
504	reset-names = "padctl";
505
506	status = "disabled";
507
508	pads {
509	usb2 {
510	clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
511	clock-names = "trk";
512	status = "disabled";
513
514	lanes {
515	usb2-0 {
516	status = "disabled";
517	#phy-cells = <0>;
518	};
519
520	usb2-1 {
521	status = "disabled";
522	#phy-cells = <0>;
523	};
524
525	usb2-2 {
526	status = "disabled";
527	#phy-cells = <0>;
528	};
529
530	usb2-3 {
531	status = "disabled";
532	#phy-cells = <0>;
533	};
534	};
535	};
536
537	hsic {
538	clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
539	clock-names = "trk";
540	status = "disabled";
541
542	lanes {
543	hsic-0 {
544	status = "disabled";
545	#phy-cells = <0>;
546	};
547
548	hsic-1 {
549	status = "disabled";
550	#phy-cells = <0>;
551	};
552	};
553	};
554
555	pcie {
556	clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
557	clock-names = "pll";
558	resets = <&tegra_car 205>;
559	reset-names = "phy";
560	status = "disabled";
561
562	lanes {
563	pcie-0 {
564	status = "disabled";
565	#phy-cells = <0>;
566	};
567
568	pcie-1 {
569	status = "disabled";
570	#phy-cells = <0>;
571	};
572
573	pcie-2 {
574	status = "disabled";
575	#phy-cells = <0>;
576	};
577
578	pcie-3 {
579	status = "disabled";
580	#phy-cells = <0>;
581	};
582
583	pcie-4 {
584	status = "disabled";
585	#phy-cells = <0>;
586	};
587
588	pcie-5 {
589	status = "disabled";
590	#phy-cells = <0>;
591	};
592
593	pcie-6 {
594	status = "disabled";
595	#phy-cells = <0>;
596	};
597	};
598	};
599
600	sata {
601	clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
602	clock-names = "pll";
603	resets = <&tegra_car 204>;
604	reset-names = "phy";
605	status = "disabled";
606
607	lanes {
608	sata-0 {
609	status = "disabled";
610	#phy-cells = <0>;
611	};
612	};
613	};
614	};
615
616	ports {
617	usb2-0 {
618	status = "disabled";
619	};
620
621	usb2-1 {
622	status = "disabled";
623	};
624
625	usb2-2 {
626	status = "disabled";
627	};
628
629	usb2-3 {
630	status = "disabled";
631	};
632
633	hsic-0 {
634	status = "disabled";
635	};
636
637	hsic-1 {
638	status = "disabled";
639	};
640
641	usb3-0 {
642	status = "disabled";
643	};
644
645	usb3-1 {
646	status = "disabled";
647	};
648
649	usb3-2 {
650	status = "disabled";
651	};
652
653	usb3-3 {
654	status = "disabled";
655	};
656	};
657	};
658
659	Board file:
660
661	padctl@7009f000 {
662	status = "okay";
663
664	pads {
665	usb2 {
666	status = "okay";
667
668	lanes {
669	usb2-0 {
670	nvidia,function = "xusb";
671	status = "okay";
672	};
673
674	usb2-1 {
675	nvidia,function = "xusb";
676	status = "okay";
677	};
678
679	usb2-2 {
680	nvidia,function = "xusb";
681	status = "okay";
682	};
683
684	usb2-3 {
685	nvidia,function = "xusb";
686	status = "okay";
687	};
688	};
689	};
690
691	pcie {
692	status = "okay";
693
694	lanes {
695	pcie-0 {
696	nvidia,function = "pcie-x1";
697	status = "okay";
698	};
699
700	pcie-1 {
701	nvidia,function = "pcie-x4";
702	status = "okay";
703	};
704
705	pcie-2 {
706	nvidia,function = "pcie-x4";
707	status = "okay";
708	};
709
710	pcie-3 {
711	nvidia,function = "pcie-x4";
712	status = "okay";
713	};
714
715	pcie-4 {
716	nvidia,function = "pcie-x4";
717	status = "okay";
718	};
719
720	pcie-5 {
721	nvidia,function = "usb3-ss";
722	status = "okay";
723	};
724
725	pcie-6 {
726	nvidia,function = "usb3-ss";
727	status = "okay";
728	};
729	};
730	};
731
732	sata {
733	status = "okay";
734
735	lanes {
736	sata-0 {
737	nvidia,function = "sata";
738	status = "okay";
739	};
740	};
741	};
742	};
743
744	ports {
745	usb2-0 {
746	status = "okay";
747	mode = "otg";
748	};
749
750	usb2-1 {
751	status = "okay";
752	vbus-supply = <&vdd_5v0_rtl>;
753	mode = "host";
754	};
755
756	usb2-2 {
757	status = "okay";
758	vbus-supply = <&vdd_usb_vbus>;
759	mode = "host";
760	};
761
762	usb2-3 {
763	status = "okay";
764	mode = "host";
765	};
766
767	usb3-0 {
768	status = "okay";
769	nvidia,lanes = "pcie-6";
770	nvidia,port = <1>;
771	};
772
773	usb3-1 {
774	status = "okay";
775	nvidia,lanes = "pcie-5";
776	nvidia,port = <2>;
777	};
778	};
779	};

Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml+654−0

@@ -0,0 +1,654 @@
	1	# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra124 XUSB pad controller
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	description: \|
	14	The Tegra XUSB pad controller manages a set of I/O lanes (with differential
	15	signals) which connect directly to pins/pads on the SoC package. Each lane
	16	is controlled by a HW block referred to as a "pad" in the Tegra hardware
	17	documentation. Each such "pad" may control either one or multiple lanes,
	18	and thus contains any logic common to all its lanes. Each lane can be
	19	separately configured and powered up.
	20
	21	Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
	22	super-speed USB. Other lanes are for various types of low-speed, full-speed
	23	or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
	24	contains a software-configurable mux that sits between the I/O controller
	25	ports (e.g. PCIe) and the lanes.
	26
	27	In addition to per-lane configuration, USB 3.0 ports may require additional
	28	settings on a per-board basis.
	29
	30	Pads will be represented as children of the top-level XUSB pad controller
	31	device tree node. Each lane exposed by the pad will be represented by its
	32	own subnode and can be referenced by users of the lane using the standard
	33	PHY bindings, as described by the phy-bindings.txt file in this directory.
	34
	35	The Tegra hardware documentation refers to the connection between the XUSB
	36	pad controller and the XUSB controller as "ports". This is confusing since
	37	"port" is typically used to denote the physical USB receptacle. The device
	38	tree binding in this document uses the term "port" to refer to the logical
	39	abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
	40	for the USB signal, the VBUS power supply, the USB 2.0 companion port for
	41	USB 3.0 receptacles, ...).
	42
	43	properties:
	44	compatible:
	45	oneOf:
	46	- enum:
	47	- nvidia,tegra124-xusb-padctl
	48
	49	- items:
	50	- const: nvidia,tegra132-xusb-padctl
	51	- const: nvidia,tegra124-xusb-padctl
	52
	53	reg:
	54	maxItems: 1
	55
	56	interrupts:
	57	items:
	58	- description: XUSB pad controller interrupt
	59
	60	resets:
	61	items:
	62	- description: pad controller reset
	63
	64	reset-names:
	65	items:
	66	- const: padctl
	67
	68	avdd-pll-utmip-supply:
	69	description: UTMI PLL power supply. Must supply 1.8 V.
	70
	71	avdd-pll-erefe-supply:
	72	description: PLLE reference PLL power supply. Must supply 1.05 V.
	73
	74	avdd-pex-pll-supply:
	75	description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
	76
	77	hvdd-pex-pll-e-supply:
	78	description: High-voltage PLLE power supply. Must supply 3.3 V.
	79
	80	pads:
	81	description: A required child node named "pads" contains a list of
	82	subnodes, one for each of the pads exposed by the XUSB pad controller.
	83	Each pad may need additional resources that can be referenced in its
	84	pad node.
	85
	86	The "status" property is used to enable or disable the use of a pad.
	87	If set to "disabled", the pad will not be used on the given board. In
	88	order to use the pad and any of its lanes, this property must be set
	89	to "okay" or be absent.
	90	type: object
	91	additionalProperties: false
	92	properties:
	93	usb2:
	94	type: object
	95	additionalProperties: false
	96	properties:
	97	clocks:
	98	items:
	99	- description: USB2 tracking clock
	100
	101	clock-names:
	102	items:
	103	- const: trk
	104
	105	lanes:
	106	type: object
	107	additionalProperties: false
	108	properties:
	109	usb2-0:
	110	type: object
	111	additionalProperties: false
	112	properties:
	113	"#phy-cells":
	114	const: 0
	115
	116	nvidia,function:
	117	description: Function selection for this lane.
	118	$ref: /schemas/types.yaml#/definitions/string
	119	enum: [ snps, xusb, uart ]
	120
	121	usb2-1:
	122	type: object
	123	additionalProperties: false
	124	properties:
	125	"#phy-cells":
	126	const: 0
	127
	128	nvidia,function:
	129	description: Function selection for this lane.
	130	$ref: /schemas/types.yaml#/definitions/string
	131	enum: [ snps, xusb, uart ]
	132
	133	usb2-2:
	134	type: object
	135	additionalProperties: false
	136	properties:
	137	"#phy-cells":
	138	const: 0
	139
	140	nvidia,function:
	141	description: Function selection for this lane.
	142	$ref: /schemas/types.yaml#/definitions/string
	143	enum: [ snps, xusb, uart ]
	144
	145	ulpi:
	146	type: object
	147	additionalProperties: false
	148	properties:
	149	lanes:
	150	type: object
	151	additionalProperties: false
	152	properties:
	153	ulpi-0:
	154	type: object
	155	additionalProperties: false
	156	properties:
	157	"#phy-cells":
	158	const: 0
	159
	160	nvidia,function:
	161	description: Function selection for this lane.
	162	$ref: /schemas/types.yaml#/definitions/string
	163	enum: [ snps, xusb ]
	164
	165	hsic:
	166	type: object
	167	additionalProperties: false
	168	properties:
	169	clocks:
	170	items:
	171	- description: HSIC tracking clock
	172
	173	clock-names:
	174	items:
	175	- const: trk
	176
	177	lanes:
	178	type: object
	179	additionalProperties: false
	180	properties:
	181	hsic-0:
	182	type: object
	183	additionalProperties: false
	184	properties:
	185	"#phy-cells":
	186	const: 0
	187
	188	nvidia,function:
	189	description: Function selection for this lane.
	190	$ref: /schemas/types.yaml#/definitions/string
	191	enum: [ snps, xusb ]
	192
	193	hsic-1:
	194	type: object
	195	additionalProperties: false
	196	properties:
	197	"#phy-cells":
	198	const: 0
	199
	200	nvidia,function:
	201	description: Function selection for this lane.
	202	$ref: /schemas/types.yaml#/definitions/string
	203	enum: [ snps, xusb ]
	204
	205	pcie:
	206	type: object
	207	additionalProperties: false
	208	properties:
	209	clocks:
	210	items:
	211	- description: PLLE clock
	212
	213	clock-names:
	214	items:
	215	- const: pll
	216
	217	resets:
	218	items:
	219	- description: reset for the PCIe UPHY block
	220
	221	reset-names:
	222	items:
	223	- const: phy
	224
	225	lanes:
	226	type: object
	227	additionalProperties: false
	228	properties:
	229	pcie-0:
	230	type: object
	231	additionalProperties: false
	232	properties:
	233	"#phy-cells":
	234	const: 0
	235
	236	nvidia,function:
	237	description: Function selection for this lane.
	238	$ref: /schemas/types.yaml#/definitions/string
	239	enum: [ pcie, usb3-ss ]
	240
	241	pcie-1:
	242	type: object
	243	additionalProperties: false
	244	properties:
	245	"#phy-cells":
	246	const: 0
	247
	248	nvidia,function:
	249	description: Function selection for this lane.
	250	$ref: /schemas/types.yaml#/definitions/string
	251	enum: [ pcie, usb3-ss ]
	252
	253	pcie-2:
	254	type: object
	255	additionalProperties: false
	256	properties:
	257	"#phy-cells":
	258	const: 0
	259
	260	nvidia,function:
	261	description: Function selection for this lane.
	262	$ref: /schemas/types.yaml#/definitions/string
	263	enum: [ pcie, usb3-ss ]
	264
	265	pcie-3:
	266	type: object
	267	additionalProperties: false
	268	properties:
	269	"#phy-cells":
	270	const: 0
	271
	272	nvidia,function:
	273	description: Function selection for this lane.
	274	$ref: /schemas/types.yaml#/definitions/string
	275	enum: [ pcie, usb3-ss ]
	276
	277	pcie-4:
	278	type: object
	279	additionalProperties: false
	280	properties:
	281	"#phy-cells":
	282	const: 0
	283
	284	nvidia,function:
	285	description: Function selection for this lane.
	286	$ref: /schemas/types.yaml#/definitions/string
	287	enum: [ pcie, usb3-ss ]
	288
	289	sata:
	290	type: object
	291	additionalProperties: false
	292	properties:
	293	resets:
	294	items:
	295	- description: reset for the SATA UPHY block
	296
	297	reset-names:
	298	items:
	299	- const: phy
	300
	301	lanes:
	302	type: object
	303	additionalProperties: false
	304	properties:
	305	sata-0:
	306	type: object
	307	additionalProperties: false
	308	properties:
	309	"#phy-cells":
	310	const: 0
	311
	312	nvidia,function:
	313	description: Function selection for this lane.
	314	$ref: /schemas/types.yaml#/definitions/string
	315	enum: [ sata, usb3-ss ]
	316
	317	ports:
	318	description: A required child node named "ports" contains a list of
	319	subnodes, one for each of the ports exposed by the XUSB pad controller.
	320	Each port may need additional resources that can be referenced in its
	321	port node.
	322
	323	The "status" property is used to enable or disable the use of a port.
	324	If set to "disabled", the port will not be used on the given board. In
	325	order to use the port, this property must be set to "okay".
	326	type: object
	327	additionalProperties: false
	328	properties:
	329	usb2-0:
	330	type: object
	331	additionalProperties: false
	332	properties:
	333	# no need to further describe this because the connector will
	334	# match on gpio-usb-b-connector or usb-b-connector and cause
	335	# that binding to be selected for the subnode
	336	connector:
	337	type: object
	338
	339	mode:
	340	description: A string that determines the mode in which to
	341	run the port.
	342	$ref: /schemas/types.yaml#/definitions/string
	343	enum: [ host, peripheral, otg ]
	344
	345	nvidia,internal:
	346	description: A boolean property whose presence determines
	347	that a port is internal. In the absence of this property
	348	the port is considered to be external.
	349	$ref: /schemas/types.yaml#/definitions/flag
	350
	351	usb-role-switch:
	352	description: \|
	353	A boolean property whole presence indicates that the port
	354	supports OTG or peripheral mode. If present, the port
	355	supports switching between USB host and peripheral roles.
	356	A connector must be added as a subnode in that case.
	357
	358	See ../connector/usb-connector.yaml.
	359
	360	vbus-supply:
	361	description: A phandle to the regulator supplying the VBUS
	362	voltage.
	363
	364	usb2-1:
	365	type: object
	366	additionalProperties: false
	367	properties:
	368	# no need to further describe this because the connector will
	369	# match on gpio-usb-b-connector or usb-b-connector and cause
	370	# that binding to be selected for the subnode
	371	connector:
	372	type: object
	373
	374	mode:
	375	description: A string that determines the mode in which to
	376	run the port.
	377	$ref: /schemas/types.yaml#/definitions/string
	378	enum: [ host, peripheral, otg ]
	379
	380	nvidia,internal:
	381	description: A boolean property whose presence determines
	382	that a port is internal. In the absence of this property
	383	the port is considered to be external.
	384	$ref: /schemas/types.yaml#/definitions/flag
	385
	386	usb-role-switch:
	387	description: \|
	388	A boolean property whole presence indicates that the port
	389	supports OTG or peripheral mode. If present, the port
	390	supports switching between USB host and peripheral roles.
	391	A connector must be added as a subnode in that case.
	392
	393	See ../connector/usb-connector.yaml.
	394
	395	vbus-supply:
	396	description: A phandle to the regulator supplying the VBUS
	397	voltage.
	398
	399	usb2-2:
	400	type: object
	401	additionalProperties: false
	402	properties:
	403	# no need to further describe this because the connector will
	404	# match on gpio-usb-b-connector or usb-b-connector and cause
	405	# that binding to be selected for the subnode
	406	connector:
	407	type: object
	408
	409	mode:
	410	description: A string that determines the mode in which to
	411	run the port.
	412	$ref: /schemas/types.yaml#/definitions/string
	413	enum: [ host, peripheral, otg ]
	414
	415	nvidia,internal:
	416	description: A boolean property whose presence determines
	417	that a port is internal. In the absence of this property
	418	the port is considered to be external.
	419	$ref: /schemas/types.yaml#/definitions/flag
	420
	421	usb-role-switch:
	422	description: \|
	423	A boolean property whole presence indicates that the port
	424	supports OTG or peripheral mode. If present, the port
	425	supports switching between USB host and peripheral roles.
	426	A connector must be added as a subnode in that case.
	427
	428	See ../connector/usb-connector.yaml.
	429
	430	vbus-supply:
	431	description: A phandle to the regulator supplying the VBUS
	432	voltage.
	433
	434	ulpi-0:
	435	type: object
	436	additionalProperties: false
	437	properties:
	438	nvidia,internal:
	439	description: A boolean property whose presence determines
	440	that a port is internal. In the absence of this property
	441	the port is considered to be external.
	442	$ref: /schemas/types.yaml#/definitions/flag
	443
	444	vbus-supply:
	445	description: A phandle to the regulator supplying the VBUS
	446	voltage.
	447
	448	hsic-0:
	449	type: object
	450	additionalProperties: false
	451	properties:
	452	vbus-supply:
	453	description: A phandle to the regulator supplying the VBUS
	454	voltage.
	455
	456	hsic-1:
	457	type: object
	458	additionalProperties: false
	459	properties:
	460	vbus-supply:
	461	description: A phandle to the regulator supplying the VBUS
	462	voltage.
	463
	464	usb3-0:
	465	type: object
	466	additionalProperties: false
	467	properties:
	468	nvidia,internal:
	469	description: A boolean property whose presence determines
	470	that a port is internal. In the absence of this property
	471	the port is considered to be external.
	472	$ref: /schemas/types.yaml#/definitions/flag
	473
	474	nvidia,usb2-companion:
	475	description: A single cell that specifies the physical port
	476	number to map this super-speed USB port to. The range of
	477	valid port numbers varies with the SoC generation.
	478	$ref: /schemas/types.yaml#/definitions/uint32
	479	enum: [ 0, 1, 2 ]
	480
	481	vbus-supply:
	482	description: A phandle to the regulator supplying the VBUS
	483	voltage.
	484
	485	usb3-1:
	486	type: object
	487	additionalProperties: false
	488	properties:
	489	nvidia,internal:
	490	description: A boolean property whose presence determines
	491	that a port is internal. In the absence of this property
	492	the port is considered to be external.
	493	$ref: /schemas/types.yaml#/definitions/flag
	494
	495	nvidia,usb2-companion:
	496	description: A single cell that specifies the physical port
	497	number to map this super-speed USB port to. The range of
	498	valid port numbers varies with the SoC generation.
	499	$ref: /schemas/types.yaml#/definitions/uint32
	500	enum: [ 0, 1, 2 ]
	501
	502	vbus-supply:
	503	description: A phandle to the regulator supplying the VBUS
	504	voltage.
	505
	506	additionalProperties: false
	507
	508	required:
	509	- compatible
	510	- reg
	511	- resets
	512	- reset-names
	513	- avdd-pll-utmip-supply
	514	- avdd-pll-erefe-supply
	515	- avdd-pex-pll-supply
	516	- hvdd-pex-pll-e-supply
	517
	518	examples:
	519	# Tegra124 and Tegra132
	520	- \|
	521	#include <dt-bindings/interrupt-controller/arm-gic.h>
	522
	523	padctl@7009f000 {
	524	compatible = "nvidia,tegra124-xusb-padctl";
	525	reg = <0x7009f000 0x1000>;
	526	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	527	resets = <&tegra_car 142>;
	528	reset-names = "padctl";
	529
	530	avdd-pll-utmip-supply = <&vddio_1v8>;
	531	avdd-pll-erefe-supply = <&avdd_1v05_run>;
	532	avdd-pex-pll-supply = <&vdd_1v05_run>;
	533	hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
	534
	535	pads {
	536	usb2 {
	537	lanes {
	538	usb2-0 {
	539	nvidia,function = "xusb";
	540	#phy-cells = <0>;
	541	};
	542
	543	usb2-1 {
	544	nvidia,function = "xusb";
	545	#phy-cells = <0>;
	546	};
	547
	548	usb2-2 {
	549	nvidia,function = "xusb";
	550	#phy-cells = <0>;
	551	};
	552	};
	553	};
	554
	555	ulpi {
	556	lanes {
	557	ulpi-0 {
	558	status = "disabled";
	559	#phy-cells = <0>;
	560	};
	561	};
	562	};
	563
	564	hsic {
	565	lanes {
	566	hsic-0 {
	567	status = "disabled";
	568	#phy-cells = <0>;
	569	};
	570
	571	hsic-1 {
	572	status = "disabled";
	573	#phy-cells = <0>;
	574	};
	575	};
	576	};
	577
	578	pcie {
	579	lanes {
	580	pcie-0 {
	581	nvidia,function = "usb3-ss";
	582	#phy-cells = <0>;
	583	};
	584
	585	pcie-1 {
	586	status = "disabled";
	587	#phy-cells = <0>;
	588	};
	589
	590	pcie-2 {
	591	nvidia,function = "pcie";
	592	#phy-cells = <0>;
	593	};
	594
	595	pcie-3 {
	596	status = "disabled";
	597	#phy-cells = <0>;
	598	};
	599
	600	pcie-4 {
	601	nvidia,function = "pcie";
	602	#phy-cells = <0>;
	603	};
	604	};
	605	};
	606
	607	sata {
	608	lanes {
	609	sata-0 {
	610	nvidia,function = "sata";
	611	#phy-cells = <0>;
	612	};
	613	};
	614	};
	615	};
	616
	617	ports {
	618	/* Micro A/B */
	619	usb2-0 {
	620	mode = "otg";
	621	};
	622
	623	/* Mini PCIe */
	624	usb2-1 {
	625	mode = "host";
	626	};
	627
	628	/* USB3 */
	629	usb2-2 {
	630	vbus-supply = <&vdd_usb3_vbus>;
	631	mode = "host";
	632	};
	633
	634	ulpi-0 {
	635	status = "disabled";
	636	};
	637
	638	hsic-0 {
	639	status = "disabled";
	640	};
	641
	642	hsic-1 {
	643	status = "disabled";
	644	};
	645
	646	usb3-0 {
	647	nvidia,usb2-companion = <2>;
	648	};
	649
	650	usb3-1 {
	651	status = "disabled";
	652	};
	653	};
	654	};

Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml+544−0

@@ -0,0 +1,544 @@
	1	# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra186 XUSB pad controller
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	description: \|
	14	The Tegra XUSB pad controller manages a set of I/O lanes (with differential
	15	signals) which connect directly to pins/pads on the SoC package. Each lane
	16	is controlled by a HW block referred to as a "pad" in the Tegra hardware
	17	documentation. Each such "pad" may control either one or multiple lanes,
	18	and thus contains any logic common to all its lanes. Each lane can be
	19	separately configured and powered up.
	20
	21	Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
	22	super-speed USB. Other lanes are for various types of low-speed, full-speed
	23	or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
	24	contains a software-configurable mux that sits between the I/O controller
	25	ports (e.g. PCIe) and the lanes.
	26
	27	In addition to per-lane configuration, USB 3.0 ports may require additional
	28	settings on a per-board basis.
	29
	30	Pads will be represented as children of the top-level XUSB pad controller
	31	device tree node. Each lane exposed by the pad will be represented by its
	32	own subnode and can be referenced by users of the lane using the standard
	33	PHY bindings, as described by the phy-bindings.txt file in this directory.
	34
	35	The Tegra hardware documentation refers to the connection between the XUSB
	36	pad controller and the XUSB controller as "ports". This is confusing since
	37	"port" is typically used to denote the physical USB receptacle. The device
	38	tree binding in this document uses the term "port" to refer to the logical
	39	abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
	40	for the USB signal, the VBUS power supply, the USB 2.0 companion port for
	41	USB 3.0 receptacles, ...).
	42
	43	properties:
	44	compatible:
	45	const: nvidia,tegra186-xusb-padctl
	46
	47	reg:
	48	items:
	49	- description: pad controller registers
	50	- description: AO registers
	51
	52	interrupts:
	53	items:
	54	- description: XUSB pad controller interrupt
	55
	56	reg-names:
	57	items:
	58	- const: padctl
	59	- const: ao
	60
	61	resets:
	62	items:
	63	- description: pad controller reset
	64
	65	reset-names:
	66	items:
	67	- const: padctl
	68
	69	avdd-pll-erefeut-supply:
	70	description: UPHY brick and reference clock as well as UTMI PHY
	71	power supply. Must supply 1.8 V.
	72
	73	avdd-usb-supply:
	74	description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must
	75	supply 3.3 V.
	76
	77	vclamp-usb-supply:
	78	description: Bias rail for USB pad. Must supply 1.8 V.
	79
	80	vddio-hsic-supply:
	81	description: HSIC PHY power supply. Must supply 1.2 V.
	82
	83	pads:
	84	description: A required child node named "pads" contains a list of
	85	subnodes, one for each of the pads exposed by the XUSB pad controller.
	86	Each pad may need additional resources that can be referenced in its
	87	pad node.
	88
	89	The "status" property is used to enable or disable the use of a pad.
	90	If set to "disabled", the pad will not be used on the given board. In
	91	order to use the pad and any of its lanes, this property must be set
	92	to "okay" or be absent.
	93	type: object
	94	additionalProperties: false
	95	properties:
	96	usb2:
	97	type: object
	98	additionalProperties: false
	99	properties:
	100	clocks:
	101	items:
	102	- description: USB2 tracking clock
	103
	104	clock-names:
	105	items:
	106	- const: trk
	107
	108	lanes:
	109	type: object
	110	additionalProperties: false
	111	properties:
	112	usb2-0:
	113	type: object
	114	additionalProperties: false
	115	properties:
	116	"#phy-cells":
	117	const: 0
	118
	119	nvidia,function:
	120	description: Function selection for this lane.
	121	$ref: /schemas/types.yaml#/definitions/string
	122	enum: [ xusb ]
	123
	124	usb2-1:
	125	type: object
	126	additionalProperties: false
	127	properties:
	128	"#phy-cells":
	129	const: 0
	130
	131	nvidia,function:
	132	description: Function selection for this lane.
	133	$ref: /schemas/types.yaml#/definitions/string
	134	enum: [ xusb ]
	135
	136	usb2-2:
	137	type: object
	138	additionalProperties: false
	139	properties:
	140	"#phy-cells":
	141	const: 0
	142
	143	nvidia,function:
	144	description: Function selection for this lane.
	145	$ref: /schemas/types.yaml#/definitions/string
	146	enum: [ xusb ]
	147
	148	hsic:
	149	type: object
	150	additionalProperties: false
	151	properties:
	152	clocks:
	153	items:
	154	- description: HSIC tracking clock
	155
	156	clock-names:
	157	items:
	158	- const: trk
	159
	160	lanes:
	161	type: object
	162	additionalProperties: false
	163	properties:
	164	hsic-0:
	165	type: object
	166	additionalProperties: false
	167	properties:
	168	"#phy-cells":
	169	const: 0
	170
	171	nvidia,function:
	172	description: Function selection for this lane.
	173	$ref: /schemas/types.yaml#/definitions/string
	174	enum: [ xusb ]
	175
	176	usb3:
	177	type: object
	178	additionalProperties: false
	179	properties:
	180	lanes:
	181	type: object
	182	additionalProperties: false
	183	properties:
	184	usb3-0:
	185	type: object
	186	additionalProperties: false
	187	properties:
	188	"#phy-cells":
	189	const: 0
	190
	191	nvidia,function:
	192	description: Function selection for this lane.
	193	$ref: /schemas/types.yaml#/definitions/string
	194	enum: [ xusb ]
	195
	196	usb3-1:
	197	type: object
	198	additionalProperties: false
	199	properties:
	200	"#phy-cells":
	201	const: 0
	202
	203	nvidia,function:
	204	description: Function selection for this lane.
	205	$ref: /schemas/types.yaml#/definitions/string
	206	enum: [ xusb ]
	207
	208	usb3-2:
	209	type: object
	210	additionalProperties: false
	211	properties:
	212	"#phy-cells":
	213	const: 0
	214
	215	nvidia,function:
	216	description: Function selection for this lane.
	217	$ref: /schemas/types.yaml#/definitions/string
	218	enum: [ xusb ]
	219
	220	ports:
	221	description: A required child node named "ports" contains a list of
	222	subnodes, one for each of the ports exposed by the XUSB pad controller.
	223	Each port may need additional resources that can be referenced in its
	224	port node.
	225
	226	The "status" property is used to enable or disable the use of a port.
	227	If set to "disabled", the port will not be used on the given board. In
	228	order to use the port, this property must be set to "okay".
	229	type: object
	230	additionalProperties: false
	231	properties:
	232	usb2-0:
	233	type: object
	234	additionalProperties: false
	235	properties:
	236	# no need to further describe this because the connector will
	237	# match on gpio-usb-b-connector or usb-b-connector and cause
	238	# that binding to be selected for the subnode
	239	connector:
	240	type: object
	241
	242	mode:
	243	description: A string that determines the mode in which to
	244	run the port.
	245	$ref: /schemas/types.yaml#/definitions/string
	246	enum: [ host, peripheral, otg ]
	247
	248	nvidia,internal:
	249	description: A boolean property whose presence determines
	250	that a port is internal. In the absence of this property
	251	the port is considered to be external.
	252	$ref: /schemas/types.yaml#/definitions/flag
	253
	254	usb-role-switch:
	255	description: \|
	256	A boolean property whole presence indicates that the port
	257	supports OTG or peripheral mode. If present, the port
	258	supports switching between USB host and peripheral roles.
	259	A connector must be added as a subnode in that case.
	260
	261	See ../connector/usb-connector.yaml.
	262
	263	vbus-supply:
	264	description: A phandle to the regulator supplying the VBUS
	265	voltage.
	266
	267	dependencies:
	268	usb-role-switch: [ connector ]
	269
	270	usb2-1:
	271	type: object
	272	additionalProperties: false
	273	properties:
	274	# no need to further describe this because the connector will
	275	# match on gpio-usb-b-connector or usb-b-connector and cause
	276	# that binding to be selected for the subnode
	277	connector:
	278	type: object
	279
	280	mode:
	281	description: A string that determines the mode in which to
	282	run the port.
	283	$ref: /schemas/types.yaml#/definitions/string
	284	enum: [ host, peripheral, otg ]
	285
	286	nvidia,internal:
	287	description: A boolean property whose presence determines
	288	that a port is internal. In the absence of this property
	289	the port is considered to be external.
	290	$ref: /schemas/types.yaml#/definitions/flag
	291
	292	usb-role-switch:
	293	description: \|
	294	A boolean property whole presence indicates that the port
	295	supports OTG or peripheral mode. If present, the port
	296	supports switching between USB host and peripheral roles.
	297	A connector must be added as a subnode in that case.
	298
	299	See ../connector/usb-connector.yaml.
	300
	301	vbus-supply:
	302	description: A phandle to the regulator supplying the VBUS
	303	voltage.
	304
	305	dependencies:
	306	usb-role-switch: [ connector ]
	307
	308	usb2-2:
	309	type: object
	310	additionalProperties: false
	311	properties:
	312	# no need to further describe this because the connector will
	313	# match on gpio-usb-b-connector or usb-b-connector and cause
	314	# that binding to be selected for the subnode
	315	connector:
	316	type: object
	317
	318	mode:
	319	description: A string that determines the mode in which to
	320	run the port.
	321	$ref: /schemas/types.yaml#/definitions/string
	322	enum: [ host, peripheral, otg ]
	323
	324	nvidia,internal:
	325	description: A boolean property whose presence determines
	326	that a port is internal. In the absence of this property
	327	the port is considered to be external.
	328	$ref: /schemas/types.yaml#/definitions/flag
	329
	330	usb-role-switch:
	331	description: \|
	332	A boolean property whole presence indicates that the port
	333	supports OTG or peripheral mode. If present, the port
	334	supports switching between USB host and peripheral roles.
	335	A connector must be added as a subnode in that case.
	336
	337	See ../connector/usb-connector.yaml.
	338
	339	vbus-supply:
	340	description: A phandle to the regulator supplying the VBUS
	341	voltage.
	342
	343	dependencies:
	344	usb-role-switch: [ connector ]
	345
	346	hsic-0:
	347	type: object
	348	additionalProperties: false
	349
	350	usb3-0:
	351	type: object
	352	additionalProperties: false
	353	properties:
	354	nvidia,internal:
	355	description: A boolean property whose presence determines
	356	that a port is internal. In the absence of this property
	357	the port is considered to be external.
	358	$ref: /schemas/types.yaml#/definitions/flag
	359
	360	nvidia,usb2-companion:
	361	description: A single cell that specifies the physical port
	362	number to map this super-speed USB port to. The range of
	363	valid port numbers varies with the SoC generation.
	364	$ref: /schemas/types.yaml#/definitions/uint32
	365	enum: [ 0, 1, 2, 3 ]
	366
	367	vbus-supply:
	368	description: A phandle to the regulator supplying the VBUS
	369	voltage.
	370
	371	usb3-1:
	372	type: object
	373	additionalProperties: false
	374	properties:
	375	nvidia,internal:
	376	description: A boolean property whose presence determines
	377	that a port is internal. In the absence of this property
	378	the port is considered to be external.
	379	$ref: /schemas/types.yaml#/definitions/flag
	380
	381	nvidia,usb2-companion:
	382	description: A single cell that specifies the physical port
	383	number to map this super-speed USB port to. The range of
	384	valid port numbers varies with the SoC generation.
	385	$ref: /schemas/types.yaml#/definitions/uint32
	386	enum: [ 0, 1, 2, 3 ]
	387
	388	vbus-supply:
	389	description: A phandle to the regulator supplying the VBUS
	390	voltage.
	391
	392	usb3-2:
	393	type: object
	394	additionalProperties: false
	395	properties:
	396	nvidia,internal:
	397	description: A boolean property whose presence determines
	398	that a port is internal. In the absence of this property
	399	the port is considered to be external.
	400	$ref: /schemas/types.yaml#/definitions/flag
	401
	402	nvidia,usb2-companion:
	403	description: A single cell that specifies the physical port
	404	number to map this super-speed USB port to. The range of
	405	valid port numbers varies with the SoC generation.
	406	$ref: /schemas/types.yaml#/definitions/uint32
	407	enum: [ 0, 1, 2, 3 ]
	408
	409	vbus-supply:
	410	description: A phandle to the regulator supplying the VBUS
	411	voltage.
	412
	413	additionalProperties: false
	414
	415	required:
	416	- compatible
	417	- reg
	418	- resets
	419	- reset-names
	420	- avdd-pll-erefeut-supply
	421	- avdd-usb-supply
	422	- vclamp-usb-supply
	423	- vddio-hsic-supply
	424
	425	examples:
	426	- \|
	427	#include <dt-bindings/clock/tegra186-clock.h>
	428	#include <dt-bindings/gpio/tegra186-gpio.h>
	429	#include <dt-bindings/interrupt-controller/arm-gic.h>
	430	#include <dt-bindings/reset/tegra186-reset.h>
	431
	432	padctl@3520000 {
	433	compatible = "nvidia,tegra186-xusb-padctl";
	434	reg = <0x03520000 0x1000>,
	435	<0x03540000 0x1000>;
	436	reg-names = "padctl", "ao";
	437	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	438
	439	resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
	440	reset-names = "padctl";
	441
	442	avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
	443	avdd-usb-supply = <&vdd_3v3_sys>;
	444	vclamp-usb-supply = <&vdd_1v8>;
	445	vddio-hsic-supply = <&gnd>;
	446
	447	pads {
	448	usb2 {
	449	clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
	450	clock-names = "trk";
	451
	452	lanes {
	453	usb2-0 {
	454	nvidia,function = "xusb";
	455	#phy-cells = <0>;
	456	};
	457
	458	usb2-1 {
	459	nvidia,function = "xusb";
	460	#phy-cells = <0>;
	461	};
	462
	463	usb2-2 {
	464	nvidia,function = "xusb";
	465	#phy-cells = <0>;
	466	};
	467	};
	468	};
	469
	470	hsic {
	471	clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
	472	clock-names = "trk";
	473	status = "disabled";
	474
	475	lanes {
	476	hsic-0 {
	477	status = "disabled";
	478	#phy-cells = <0>;
	479	};
	480	};
	481	};
	482
	483	usb3 {
	484	lanes {
	485	usb3-0 {
	486	nvidia,function = "xusb";
	487	#phy-cells = <0>;
	488	};
	489
	490	usb3-1 {
	491	nvidia,function = "xusb";
	492	#phy-cells = <0>;
	493	};
	494
	495	usb3-2 {
	496	nvidia,function = "xusb";
	497	#phy-cells = <0>;
	498	};
	499	};
	500	};
	501	};
	502
	503	ports {
	504	usb2-0 {
	505	mode = "otg";
	506	vbus-supply = <&vdd_usb0>;
	507	usb-role-switch;
	508
	509	connector {
	510	compatible = "gpio-usb-b-connector",
	511	"usb-b-connector";
	512	label = "micro-USB";
	513	type = "micro";
	514	vbus-gpios = <&gpio TEGRA186_MAIN_GPIO(X, 7) GPIO_ACTIVE_LOW>;
	515	id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
	516	};
	517	};
	518
	519	usb2-1 {
	520	vbus-supply = <&vdd_usb1>;
	521	mode = "host";
	522	};
	523
	524	usb2-2 {
	525	status = "disabled";
	526	};
	527
	528	hsic-0 {
	529	status = "disabled";
	530	};
	531
	532	usb3-0 {
	533	nvidia,usb2-companion = <1>;
	534	};
	535
	536	usb3-1 {
	537	status = "disabled";
	538	};
	539
	540	usb3-2 {
	541	status = "disabled";
	542	};
	543	};
	544	};

Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml+632−0

@@ -0,0 +1,632 @@
	1	# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra194 XUSB pad controller
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	description: \|
	14	The Tegra XUSB pad controller manages a set of I/O lanes (with differential
	15	signals) which connect directly to pins/pads on the SoC package. Each lane
	16	is controlled by a HW block referred to as a "pad" in the Tegra hardware
	17	documentation. Each such "pad" may control either one or multiple lanes,
	18	and thus contains any logic common to all its lanes. Each lane can be
	19	separately configured and powered up.
	20
	21	Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
	22	super-speed USB. Other lanes are for various types of low-speed, full-speed
	23	or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
	24	contains a software-configurable mux that sits between the I/O controller
	25	ports (e.g. PCIe) and the lanes.
	26
	27	In addition to per-lane configuration, USB 3.0 ports may require additional
	28	settings on a per-board basis.
	29
	30	Pads will be represented as children of the top-level XUSB pad controller
	31	device tree node. Each lane exposed by the pad will be represented by its
	32	own subnode and can be referenced by users of the lane using the standard
	33	PHY bindings, as described by the phy-bindings.txt file in this directory.
	34
	35	The Tegra hardware documentation refers to the connection between the XUSB
	36	pad controller and the XUSB controller as "ports". This is confusing since
	37	"port" is typically used to denote the physical USB receptacle. The device
	38	tree binding in this document uses the term "port" to refer to the logical
	39	abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
	40	for the USB signal, the VBUS power supply, the USB 2.0 companion port for
	41	USB 3.0 receptacles, ...).
	42
	43	properties:
	44	compatible:
	45	enum:
	46	- nvidia,tegra194-xusb-padctl
	47	- nvidia,tegra234-xusb-padctl
	48
	49	reg:
	50	items:
	51	- description: pad controller registers
	52	- description: AO registers
	53
	54	reg-names:
	55	items:
	56	- const: padctl
	57	- const: ao
	58
	59	interrupts:
	60	items:
	61	- description: XUSB pad controller interrupt
	62
	63	resets:
	64	items:
	65	- description: pad controller reset
	66
	67	reset-names:
	68	items:
	69	- const: padctl
	70
	71	avdd-usb-supply:
	72	description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must
	73	supply 3.3 V.
	74
	75	vclamp-usb-supply:
	76	description: Bias rail for USB pad. Must supply 1.8 V.
	77
	78	pads:
	79	description: A required child node named "pads" contains a list of
	80	subnodes, one for each of the pads exposed by the XUSB pad controller.
	81	Each pad may need additional resources that can be referenced in its
	82	pad node.
	83
	84	The "status" property is used to enable or disable the use of a pad.
	85	If set to "disabled", the pad will not be used on the given board. In
	86	order to use the pad and any of its lanes, this property must be set
	87	to "okay" or absent.
	88	type: object
	89	additionalProperties: false
	90	properties:
	91	usb2:
	92	type: object
	93	additionalProperties: false
	94	properties:
	95	clocks:
	96	items:
	97	- description: USB2 tracking clock
	98
	99	clock-names:
	100	items:
	101	- const: trk
	102
	103	lanes:
	104	type: object
	105	additionalProperties: false
	106	properties:
	107	usb2-0:
	108	type: object
	109	additionalProperties: false
	110	properties:
	111	"#phy-cells":
	112	const: 0
	113
	114	nvidia,function:
	115	description: Function selection for this lane.
	116	$ref: /schemas/types.yaml#/definitions/string
	117	enum: [ xusb ]
	118
	119	usb2-1:
	120	type: object
	121	additionalProperties: false
	122	properties:
	123	"#phy-cells":
	124	const: 0
	125
	126	nvidia,function:
	127	description: Function selection for this lane.
	128	$ref: /schemas/types.yaml#/definitions/string
	129	enum: [ xusb ]
	130
	131	usb2-2:
	132	type: object
	133	additionalProperties: false
	134	properties:
	135	"#phy-cells":
	136	const: 0
	137
	138	nvidia,function:
	139	description: Function selection for this lane.
	140	$ref: /schemas/types.yaml#/definitions/string
	141	enum: [ xusb ]
	142
	143	usb2-3:
	144	type: object
	145	additionalProperties: false
	146	properties:
	147	"#phy-cells":
	148	const: 0
	149
	150	nvidia,function:
	151	description: Function selection for this lane.
	152	$ref: /schemas/types.yaml#/definitions/string
	153	enum: [ xusb ]
	154
	155	usb3:
	156	type: object
	157	additionalProperties: false
	158	properties:
	159	lanes:
	160	type: object
	161	additionalProperties: false
	162	properties:
	163	usb3-0:
	164	type: object
	165	additionalProperties: false
	166	properties:
	167	"#phy-cells":
	168	const: 0
	169
	170	nvidia,function:
	171	description: Function selection for this lane.
	172	$ref: /schemas/types.yaml#/definitions/string
	173	enum: [ xusb ]
	174
	175	usb3-1:
	176	type: object
	177	additionalProperties: false
	178	properties:
	179	"#phy-cells":
	180	const: 0
	181
	182	nvidia,function:
	183	description: Function selection for this lane.
	184	$ref: /schemas/types.yaml#/definitions/string
	185	enum: [ xusb ]
	186
	187	usb3-2:
	188	type: object
	189	additionalProperties: false
	190	properties:
	191	"#phy-cells":
	192	const: 0
	193
	194	nvidia,function:
	195	description: Function selection for this lane.
	196	$ref: /schemas/types.yaml#/definitions/string
	197	enum: [ xusb ]
	198
	199	usb3-3:
	200	type: object
	201	additionalProperties: false
	202	properties:
	203	"#phy-cells":
	204	const: 0
	205
	206	nvidia,function:
	207	description: Function selection for this lane.
	208	$ref: /schemas/types.yaml#/definitions/string
	209	enum: [ xusb ]
	210
	211	ports:
	212	description: A required child node named "ports" contains a list of
	213	subnodes, one for each of the ports exposed by the XUSB pad controller.
	214	Each port may need additional resources that can be referenced in its
	215	port node.
	216
	217	The "status" property is used to enable or disable the use of a port.
	218	If set to "disabled", the port will not be used on the given board. In
	219	order to use the port, this property must be set to "okay".
	220	type: object
	221	additionalProperties: false
	222	properties:
	223	usb2-0:
	224	type: object
	225	additionalProperties: false
	226	properties:
	227	# no need to further describe this because the connector will
	228	# match on gpio-usb-b-connector or usb-b-connector and cause
	229	# that binding to be selected for the subnode
	230	connector:
	231	type: object
	232
	233	mode:
	234	description: A string that determines the mode in which to
	235	run the port.
	236	$ref: /schemas/types.yaml#/definitions/string
	237	enum: [ host, peripheral, otg ]
	238
	239	nvidia,internal:
	240	description: A boolean property whose presence determines
	241	that a port is internal. In the absence of this property
	242	the port is considered to be external.
	243	$ref: /schemas/types.yaml#/definitions/flag
	244
	245	usb-role-switch:
	246	description: \|
	247	A boolean property whole presence indicates that the port
	248	supports OTG or peripheral mode. If present, the port
	249	supports switching between USB host and peripheral roles.
	250	A connector must be added as a subnode in that case.
	251
	252	See ../connector/usb-connector.yaml.
	253
	254	vbus-supply:
	255	description: A phandle to the regulator supplying the VBUS
	256	voltage.
	257
	258	dependencies:
	259	usb-role-switch: [ connector ]
	260
	261	usb2-1:
	262	type: object
	263	additionalProperties: false
	264	properties:
	265	# no need to further describe this because the connector will
	266	# match on gpio-usb-b-connector or usb-b-connector and cause
	267	# that binding to be selected for the subnode
	268	connector:
	269	type: object
	270
	271	mode:
	272	description: A string that determines the mode in which to
	273	run the port.
	274	$ref: /schemas/types.yaml#/definitions/string
	275	enum: [ host, peripheral, otg ]
	276
	277	nvidia,internal:
	278	description: A boolean property whose presence determines
	279	that a port is internal. In the absence of this property
	280	the port is considered to be external.
	281	$ref: /schemas/types.yaml#/definitions/flag
	282
	283	usb-role-switch:
	284	description: \|
	285	A boolean property whole presence indicates that the port
	286	supports OTG or peripheral mode. If present, the port
	287	supports switching between USB host and peripheral roles.
	288	A connector must be added as a subnode in that case.
	289
	290	See ../connector/usb-connector.yaml.
	291
	292	vbus-supply:
	293	description: A phandle to the regulator supplying the VBUS
	294	voltage.
	295
	296	dependencies:
	297	usb-role-switch: [ connector ]
	298
	299	usb2-2:
	300	type: object
	301	additionalProperties: false
	302	properties:
	303	# no need to further describe this because the connector will
	304	# match on gpio-usb-b-connector or usb-b-connector and cause
	305	# that binding to be selected for the subnode
	306	connector:
	307	type: object
	308
	309	mode:
	310	description: A string that determines the mode in which to
	311	run the port.
	312	$ref: /schemas/types.yaml#/definitions/string
	313	enum: [ host, peripheral, otg ]
	314
	315	nvidia,internal:
	316	description: A boolean property whose presence determines
	317	that a port is internal. In the absence of this property
	318	the port is considered to be external.
	319	$ref: /schemas/types.yaml#/definitions/flag
	320
	321	usb-role-switch:
	322	description: \|
	323	A boolean property whole presence indicates that the port
	324	supports OTG or peripheral mode. If present, the port
	325	supports switching between USB host and peripheral roles.
	326	A connector must be added as a subnode in that case.
	327
	328	See ../connector/usb-connector.yaml.
	329
	330	vbus-supply:
	331	description: A phandle to the regulator supplying the VBUS
	332	voltage.
	333
	334	dependencies:
	335	usb-role-switch: [ connector ]
	336
	337	usb2-3:
	338	type: object
	339	additionalProperties: false
	340	properties:
	341	# no need to further describe this because the connector will
	342	# match on gpio-usb-b-connector or usb-b-connector and cause
	343	# that binding to be selected for the subnode
	344	connector:
	345	type: object
	346
	347	mode:
	348	description: A string that determines the mode in which to
	349	run the port.
	350	$ref: /schemas/types.yaml#/definitions/string
	351	enum: [ host, peripheral, otg ]
	352
	353	nvidia,internal:
	354	description: A boolean property whose presence determines
	355	that a port is internal. In the absence of this property
	356	the port is considered to be external.
	357	$ref: /schemas/types.yaml#/definitions/flag
	358
	359	usb-role-switch:
	360	description: \|
	361	A boolean property whole presence indicates that the port
	362	supports OTG or peripheral mode. If present, the port
	363	supports switching between USB host and peripheral roles.
	364	A connector must be added as a subnode in that case.
	365
	366	See ../connector/usb-connector.yaml.
	367
	368	vbus-supply:
	369	description: A phandle to the regulator supplying the VBUS
	370	voltage.
	371
	372	dependencies:
	373	usb-role-switch: [ connector ]
	374
	375	usb3-0:
	376	type: object
	377	additionalProperties: false
	378	properties:
	379	maximum-speed:
	380	description: A string property that specifies the maximum
	381	supported speed of a USB3 port.
	382	$ref: /schemas/types.yaml#/definitions/string
	383	oneOf:
	384	- description: The USB3 port supports USB 3.1 Gen 2 speed.
	385	This is the default.
	386	const: super-speed-plus
	387	- description: The USB3 port supports USB 3.1 Gen 1 speed
	388	only.
	389	const: super-speed
	390
	391	nvidia,internal:
	392	description: A boolean property whose presence determines
	393	that a port is internal. In the absence of this property
	394	the port is considered to be external.
	395	$ref: /schemas/types.yaml#/definitions/flag
	396
	397	nvidia,usb2-companion:
	398	description: A single cell that specifies the physical port
	399	number to map this super-speed USB port to. The range of
	400	valid port numbers varies with the SoC generation.
	401	$ref: /schemas/types.yaml#/definitions/uint32
	402	enum: [ 0, 1, 2, 3 ]
	403
	404	vbus-supply:
	405	description: A phandle to the regulator supplying the VBUS
	406	voltage.
	407
	408	usb3-1:
	409	type: object
	410	additionalProperties: false
	411	properties:
	412	maximum-speed:
	413	description: A string property that specifies the maximum
	414	supported speed of a USB3 port.
	415	$ref: /schemas/types.yaml#/definitions/string
	416	oneOf:
	417	- description: The USB3 port supports USB 3.1 Gen 2 speed.
	418	This is the default.
	419	const: super-speed-plus
	420	- description: The USB3 port supports USB 3.1 Gen 1 speed
	421	only.
	422	const: super-speed
	423
	424	nvidia,internal:
	425	description: A boolean property whose presence determines
	426	that a port is internal. In the absence of this property
	427	the port is considered to be external.
	428	$ref: /schemas/types.yaml#/definitions/flag
	429
	430	nvidia,usb2-companion:
	431	description: A single cell that specifies the physical port
	432	number to map this super-speed USB port to. The range of
	433	valid port numbers varies with the SoC generation.
	434	$ref: /schemas/types.yaml#/definitions/uint32
	435	enum: [ 0, 1, 2, 3 ]
	436
	437	vbus-supply:
	438	description: A phandle to the regulator supplying the VBUS
	439	voltage.
	440
	441	usb3-2:
	442	type: object
	443	additionalProperties: false
	444	properties:
	445	maximum-speed:
	446	description: A string property that specifies the maximum
	447	supported speed of a USB3 port.
	448	$ref: /schemas/types.yaml#/definitions/string
	449	oneOf:
	450	- description: The USB3 port supports USB 3.1 Gen 2 speed.
	451	This is the default.
	452	const: super-speed-plus
	453	- description: The USB3 port supports USB 3.1 Gen 1 speed
	454	only.
	455	const: super-speed
	456
	457	nvidia,internal:
	458	description: A boolean property whose presence determines
	459	that a port is internal. In the absence of this property
	460	the port is considered to be external.
	461	$ref: /schemas/types.yaml#/definitions/flag
	462
	463	nvidia,usb2-companion:
	464	description: A single cell that specifies the physical port
	465	number to map this super-speed USB port to. The range of
	466	valid port numbers varies with the SoC generation.
	467	$ref: /schemas/types.yaml#/definitions/uint32
	468	enum: [ 0, 1, 2, 3 ]
	469
	470	vbus-supply:
	471	description: A phandle to the regulator supplying the VBUS
	472	voltage.
	473
	474	usb3-3:
	475	type: object
	476	additionalProperties: false
	477	properties:
	478	maximum-speed:
	479	description: A string property that specifies the maximum
	480	supported speed of a USB3 port.
	481	$ref: /schemas/types.yaml#/definitions/string
	482	oneOf:
	483	- description: The USB3 port supports USB 3.1 Gen 2 speed.
	484	This is the default.
	485	const: super-speed-plus
	486	- description: The USB3 port supports USB 3.1 Gen 1 speed
	487	only.
	488	const: super-speed
	489
	490	nvidia,internal:
	491	description: A boolean property whose presence determines
	492	that a port is internal. In the absence of this property
	493	the port is considered to be external.
	494	$ref: /schemas/types.yaml#/definitions/flag
	495
	496	nvidia,usb2-companion:
	497	description: A single cell that specifies the physical port
	498	number to map this super-speed USB port to. The range of
	499	valid port numbers varies with the SoC generation.
	500	$ref: /schemas/types.yaml#/definitions/uint32
	501	enum: [ 0, 1, 2, 3 ]
	502
	503	vbus-supply:
	504	description: A phandle to the regulator supplying the VBUS
	505	voltage.
	506
	507	additionalProperties: false
	508
	509	required:
	510	- compatible
	511	- reg
	512	- resets
	513	- reset-names
	514	- avdd-usb-supply
	515	- vclamp-usb-supply
	516
	517	examples:
	518	- \|
	519	#include <dt-bindings/clock/tegra194-clock.h>
	520	#include <dt-bindings/gpio/tegra194-gpio.h>
	521	#include <dt-bindings/interrupt-controller/arm-gic.h>
	522	#include <dt-bindings/reset/tegra194-reset.h>
	523
	524	padctl@3520000 {
	525	compatible = "nvidia,tegra194-xusb-padctl";
	526	reg = <0x03520000 0x1000>,
	527	<0x03540000 0x1000>;
	528	reg-names = "padctl", "ao";
	529	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	530
	531	resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
	532	reset-names = "padctl";
	533
	534	avdd-usb-supply = <&vdd_usb_3v3>;
	535	vclamp-usb-supply = <&vdd_1v8ao>;
	536
	537	pads {
	538	usb2 {
	539	clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
	540	clock-names = "trk";
	541
	542	lanes {
	543	usb2-0 {
	544	nvidia,function = "xusb";
	545	status = "disabled";
	546	#phy-cells = <0>;
	547	};
	548
	549	usb2-1 {
	550	nvidia,function = "xusb";
	551	#phy-cells = <0>;
	552	};
	553
	554	usb2-2 {
	555	nvidia,function = "xusb";
	556	status = "disabled";
	557	#phy-cells = <0>;
	558	};
	559
	560	usb2-3 {
	561	nvidia,function = "xusb";
	562	#phy-cells = <0>;
	563	};
	564	};
	565	};
	566
	567	usb3 {
	568	lanes {
	569	usb3-0 {
	570	nvidia,function = "xusb";
	571	#phy-cells = <0>;
	572	};
	573
	574	usb3-1 {
	575	nvidia,function = "xusb";
	576	status = "disabled";
	577	#phy-cells = <0>;
	578	};
	579
	580	usb3-2 {
	581	nvidia,function = "xusb";
	582	status = "disabled";
	583	#phy-cells = <0>;
	584	};
	585
	586	usb3-3 {
	587	nvidia,function = "xusb";
	588	#phy-cells = <0>;
	589	};
	590	};
	591	};
	592	};
	593
	594	ports {
	595	usb2-0 {
	596	status = "disabled";
	597	};
	598
	599	usb2-1 {
	600	vbus-supply = <&vdd_5v0_sys>;
	601	mode = "host";
	602	};
	603
	604	usb2-2 {
	605	status = "disabled";
	606	};
	607
	608	usb2-3 {
	609	vbus-supply = <&vdd_5v_sata>;
	610	mode = "host";
	611	};
	612
	613	usb3-0 {
	614	vbus-supply = <&vdd_5v0_sys>;
	615	nvidia,usb2-companion = <1>;
	616	};
	617
	618	usb3-1 {
	619	status = "disabled";
	620	};
	621
	622	usb3-2 {
	623	status = "disabled";
	624	};
	625
	626	usb3-3 {
	627	maximum-speed = "super-speed";
	628	vbus-supply = <&vdd_5v0_sys>;
	629	nvidia,usb2-companion = <3>;
	630	};
	631	};
	632	};

Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml+786−0

@@ -0,0 +1,786 @@
	1	# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra210 XUSB pad controller
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	description: \|
	14	The Tegra XUSB pad controller manages a set of I/O lanes (with differential
	15	signals) which connect directly to pins/pads on the SoC package. Each lane
	16	is controlled by a HW block referred to as a "pad" in the Tegra hardware
	17	documentation. Each such "pad" may control either one or multiple lanes,
	18	and thus contains any logic common to all its lanes. Each lane can be
	19	separately configured and powered up.
	20
	21	Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
	22	super-speed USB. Other lanes are for various types of low-speed, full-speed
	23	or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
	24	contains a software-configurable mux that sits between the I/O controller
	25	ports (e.g. PCIe) and the lanes.
	26
	27	In addition to per-lane configuration, USB 3.0 ports may require additional
	28	settings on a per-board basis.
	29
	30	Pads will be represented as children of the top-level XUSB pad controller
	31	device tree node. Each lane exposed by the pad will be represented by its
	32	own subnode and can be referenced by users of the lane using the standard
	33	PHY bindings, as described by the phy-bindings.txt file in this directory.
	34
	35	The Tegra hardware documentation refers to the connection between the XUSB
	36	pad controller and the XUSB controller as "ports". This is confusing since
	37	"port" is typically used to denote the physical USB receptacle. The device
	38	tree binding in this document uses the term "port" to refer to the logical
	39	abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
	40	for the USB signal, the VBUS power supply, the USB 2.0 companion port for
	41	USB 3.0 receptacles, ...).
	42
	43	properties:
	44	compatible:
	45	const: nvidia,tegra210-xusb-padctl
	46
	47	reg:
	48	maxItems: 1
	49
	50	resets:
	51	items:
	52	- description: pad controller reset
	53
	54	interrupts:
	55	items:
	56	- description: XUSB pad controller interrupt
	57
	58	reset-names:
	59	items:
	60	- const: padctl
	61
	62	avdd-pll-utmip-supply:
	63	description: UTMI PLL power supply. Must supply 1.8 V.
	64
	65	avdd-pll-uerefe-supply:
	66	description: PLLE reference PLL power supply. Must supply 1.05 V.
	67
	68	dvdd-pex-pll-supply:
	69	description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
	70
	71	hvdd-pex-pll-e-supply:
	72	description: High-voltage PLLE power supply. Must supply 1.8 V.
	73
	74	nvidia,pmc:
	75	description: phandle to the Tegra Power Management Controller (PMC) node
	76	$ref: /schemas/types.yaml#/definitions/phandle
	77
	78	pads:
	79	description: A required child node named "pads" contains a list of
	80	subnodes, one for each of the pads exposed by the XUSB pad controller.
	81	Each pad may need additional resources that can be referenced in its
	82	pad node.
	83
	84	The "status" property is used to enable or disable the use of a pad.
	85	If set to "disabled", the pad will not be used on the given board. In
	86	order to use the pad and any of its lanes, this property must be set
	87	to "okay" or be absent.
	88	type: object
	89	additionalProperties: false
	90	properties:
	91	usb2:
	92	type: object
	93	additionalProperties: false
	94	properties:
	95	clocks:
	96	items:
	97	- description: USB2 tracking clock
	98
	99	clock-names:
	100	items:
	101	- const: trk
	102
	103	lanes:
	104	type: object
	105	additionalProperties: false
	106	properties:
	107	usb2-0:
	108	type: object
	109	additionalProperties: false
	110	properties:
	111	"#phy-cells":
	112	const: 0
	113
	114	nvidia,function:
	115	description: Function selection for this lane.
	116	$ref: /schemas/types.yaml#/definitions/string
	117	enum: [ snps, xusb, uart ]
	118
	119	usb2-1:
	120	type: object
	121	additionalProperties: false
	122	properties:
	123	"#phy-cells":
	124	const: 0
	125
	126	nvidia,function:
	127	description: Function selection for this lane.
	128	$ref: /schemas/types.yaml#/definitions/string
	129	enum: [ snps, xusb, uart ]
	130
	131	usb2-2:
	132	type: object
	133	additionalProperties: false
	134	properties:
	135	"#phy-cells":
	136	const: 0
	137
	138	nvidia,function:
	139	description: Function selection for this lane.
	140	$ref: /schemas/types.yaml#/definitions/string
	141	enum: [ snps, xusb, uart ]
	142
	143	usb2-3:
	144	type: object
	145	additionalProperties: false
	146	properties:
	147	"#phy-cells":
	148	const: 0
	149
	150	nvidia,function:
	151	description: Function selection for this lane.
	152	$ref: /schemas/types.yaml#/definitions/string
	153	enum: [ snps, xusb, uart ]
	154
	155	hsic:
	156	type: object
	157	additionalProperties: false
	158	properties:
	159	clocks:
	160	items:
	161	- description: HSIC tracking clock
	162
	163	clock-names:
	164	items:
	165	- const: trk
	166
	167	lanes:
	168	type: object
	169	additionalProperties: false
	170	properties:
	171	hsic-0:
	172	type: object
	173	additionalProperties: false
	174	properties:
	175	"#phy-cells":
	176	const: 0
	177
	178	nvidia,function:
	179	description: Function selection for this lane.
	180	$ref: /schemas/types.yaml#/definitions/string
	181	enum: [ snps, xusb ]
	182
	183	hsic-1:
	184	type: object
	185	additionalProperties: false
	186	properties:
	187	"#phy-cells":
	188	const: 0
	189
	190	nvidia,function:
	191	description: Function selection for this lane.
	192	$ref: /schemas/types.yaml#/definitions/string
	193	enum: [ snps, xusb ]
	194
	195	pcie:
	196	type: object
	197	additionalProperties: false
	198	properties:
	199	clocks:
	200	items:
	201	- description: PCIe PLL clock source
	202
	203	clock-names:
	204	items:
	205	- const: pll
	206
	207	resets:
	208	items:
	209	- description: PCIe PHY reset
	210
	211	reset-names:
	212	items:
	213	- const: phy
	214
	215	lanes:
	216	type: object
	217	additionalProperties: false
	218	properties:
	219	pcie-0:
	220	type: object
	221	additionalProperties: false
	222	properties:
	223	"#phy-cells":
	224	const: 0
	225
	226	nvidia,function:
	227	description: Function selection for this lane.
	228	$ref: /schemas/types.yaml#/definitions/string
	229	enum: [ pcie-x1, usb3-ss, pcie-x4 ]
	230
	231	pcie-1:
	232	type: object
	233	additionalProperties: false
	234	properties:
	235	"#phy-cells":
	236	const: 0
	237
	238	nvidia,function:
	239	description: Function selection for this lane.
	240	$ref: /schemas/types.yaml#/definitions/string
	241	enum: [ pcie-x1, usb3-ss, pcie-x4 ]
	242
	243	pcie-2:
	244	type: object
	245	additionalProperties: false
	246	properties:
	247	"#phy-cells":
	248	const: 0
	249
	250	nvidia,function:
	251	description: Function selection for this lane.
	252	$ref: /schemas/types.yaml#/definitions/string
	253	enum: [ pcie-x1, usb3-ss, pcie-x4 ]
	254
	255	pcie-3:
	256	type: object
	257	additionalProperties: false
	258	properties:
	259	"#phy-cells":
	260	const: 0
	261
	262	nvidia,function:
	263	description: Function selection for this lane.
	264	$ref: /schemas/types.yaml#/definitions/string
	265	enum: [ pcie-x1, usb3-ss, pcie-x4 ]
	266
	267	pcie-4:
	268	type: object
	269	additionalProperties: false
	270	properties:
	271	"#phy-cells":
	272	const: 0
	273
	274	nvidia,function:
	275	description: Function selection for this lane.
	276	$ref: /schemas/types.yaml#/definitions/string
	277	enum: [ pcie-x1, usb3-ss, pcie-x4 ]
	278
	279	pcie-5:
	280	type: object
	281	additionalProperties: false
	282	properties:
	283	"#phy-cells":
	284	const: 0
	285
	286	nvidia,function:
	287	description: Function selection for this lane.
	288	$ref: /schemas/types.yaml#/definitions/string
	289	enum: [ pcie-x1, usb3-ss, pcie-x4 ]
	290
	291	pcie-6:
	292	type: object
	293	additionalProperties: false
	294	properties:
	295	"#phy-cells":
	296	const: 0
	297
	298	nvidia,function:
	299	description: Function selection for this lane.
	300	$ref: /schemas/types.yaml#/definitions/string
	301	enum: [ pcie-x1, usb3-ss, pcie-x4 ]
	302
	303	sata:
	304	type: object
	305	additionalProperties: false
	306	properties:
	307	clocks:
	308	items:
	309	- description: SATA PLL clock source
	310
	311	clock-names:
	312	items:
	313	- const: pll
	314
	315	resets:
	316	items:
	317	- description: SATA PHY reset
	318
	319	reset-names:
	320	items:
	321	- const: phy
	322
	323	lanes:
	324	type: object
	325	additionalProperties: false
	326	properties:
	327	sata-0:
	328	type: object
	329	additionalProperties: false
	330	properties:
	331	"#phy-cells":
	332	const: 0
	333
	334	nvidia,function:
	335	description: Function selection for this lane.
	336	$ref: /schemas/types.yaml#/definitions/string
	337	enum: [ usb3-ss, sata ]
	338
	339	ports:
	340	description: A required child node named "ports" contains a list of
	341	subnodes, one for each of the ports exposed by the XUSB pad controller.
	342	Each port may need additional resources that can be referenced in its
	343	port node.
	344
	345	The "status" property is used to enable or disable the use of a port.
	346	If set to "disabled", the port will not be used on the given board. In
	347	order to use the port, this property must be set to "okay".
	348	type: object
	349	additionalProperties: false
	350	properties:
	351	usb2-0:
	352	type: object
	353	additionalProperties: false
	354	properties:
	355	# no need to further describe this because the connector will
	356	# match on gpio-usb-b-connector or usb-b-connector and cause
	357	# that binding to be selected for the subnode
	358	connector:
	359	type: object
	360
	361	mode:
	362	description: A string that determines the mode in which to
	363	run the port.
	364	$ref: /schemas/types.yaml#/definitions/string
	365	enum: [ host, peripheral, otg ]
	366
	367	nvidia,internal:
	368	description: A boolean property whose presence determines
	369	that a port is internal. In the absence of this property
	370	the port is considered to be external.
	371	$ref: /schemas/types.yaml#/definitions/flag
	372
	373	usb-role-switch:
	374	description: \|
	375	A boolean property whole presence indicates that the port
	376	supports OTG or peripheral mode. If present, the port
	377	supports switching between USB host and peripheral roles.
	378	A connector must be added as a subnode in that case.
	379
	380	See ../connector/usb-connector.yaml.
	381
	382	vbus-supply:
	383	description: A phandle to the regulator supplying the VBUS
	384	voltage.
	385
	386	dependencies:
	387	usb-role-switch: [ connector ]
	388
	389	usb2-1:
	390	type: object
	391	additionalProperties: false
	392	properties:
	393	# no need to further describe this because the connector will
	394	# match on gpio-usb-b-connector or usb-b-connector and cause
	395	# that binding to be selected for the subnode
	396	connector:
	397	type: object
	398
	399	mode:
	400	description: A string that determines the mode in which to
	401	run the port.
	402	$ref: /schemas/types.yaml#/definitions/string
	403	enum: [ host, peripheral, otg ]
	404
	405	nvidia,internal:
	406	description: A boolean property whose presence determines
	407	that a port is internal. In the absence of this property
	408	the port is considered to be external.
	409	$ref: /schemas/types.yaml#/definitions/flag
	410
	411	usb-role-switch:
	412	description: \|
	413	A boolean property whole presence indicates that the port
	414	supports OTG or peripheral mode. If present, the port
	415	supports switching between USB host and peripheral roles.
	416	A connector must be added as a subnode in that case.
	417
	418	See ../connector/usb-connector.yaml.
	419
	420	vbus-supply:
	421	description: A phandle to the regulator supplying the VBUS
	422	voltage.
	423
	424	dependencies:
	425	usb-role-switch: [ connector ]
	426
	427	usb2-2:
	428	type: object
	429	additionalProperties: false
	430	properties:
	431	# no need to further describe this because the connector will
	432	# match on gpio-usb-b-connector or usb-b-connector and cause
	433	# that binding to be selected for the subnode
	434	connector:
	435	type: object
	436
	437	mode:
	438	description: A string that determines the mode in which to
	439	run the port.
	440	$ref: /schemas/types.yaml#/definitions/string
	441	enum: [ host, peripheral, otg ]
	442
	443	nvidia,internal:
	444	description: A boolean property whose presence determines
	445	that a port is internal. In the absence of this property
	446	the port is considered to be external.
	447	$ref: /schemas/types.yaml#/definitions/flag
	448
	449	usb-role-switch:
	450	description: \|
	451	A boolean property whole presence indicates that the port
	452	supports OTG or peripheral mode. If present, the port
	453	supports switching between USB host and peripheral roles.
	454	A connector must be added as a subnode in that case.
	455
	456	See ../connector/usb-connector.yaml.
	457
	458	vbus-supply:
	459	description: A phandle to the regulator supplying the VBUS
	460	voltage.
	461
	462	dependencies:
	463	usb-role-switch: [ connector ]
	464
	465	usb2-3:
	466	type: object
	467	additionalProperties: false
	468	properties:
	469	# no need to further describe this because the connector will
	470	# match on gpio-usb-b-connector or usb-b-connector and cause
	471	# that binding to be selected for the subnode
	472	connector:
	473	type: object
	474
	475	mode:
	476	description: A string that determines the mode in which to
	477	run the port.
	478	$ref: /schemas/types.yaml#/definitions/string
	479	enum: [ host, peripheral, otg ]
	480
	481	nvidia,internal:
	482	description: A boolean property whose presence determines
	483	that a port is internal. In the absence of this property
	484	the port is considered to be external.
	485	$ref: /schemas/types.yaml#/definitions/flag
	486
	487	usb-role-switch:
	488	description: \|
	489	A boolean property whole presence indicates that the port
	490	supports OTG or peripheral mode. If present, the port
	491	supports switching between USB host and peripheral roles.
	492	A connector must be added as a subnode in that case.
	493
	494	See ../connector/usb-connector.yaml.
	495
	496	vbus-supply:
	497	description: A phandle to the regulator supplying the VBUS
	498	voltage.
	499
	500	dependencies:
	501	usb-role-switch: [ connector ]
	502
	503	hsic-0:
	504	type: object
	505	additionalProperties: false
	506	properties:
	507	vbus-supply:
	508	description: A phandle to the regulator supplying the VBUS
	509	voltage.
	510
	511	hsic-1:
	512	type: object
	513	additionalProperties: false
	514	properties:
	515	vbus-supply:
	516	description: A phandle to the regulator supplying the VBUS
	517	voltage.
	518
	519	usb3-0:
	520	type: object
	521	additionalProperties: false
	522	properties:
	523	nvidia,internal:
	524	description: A boolean property whose presence determines
	525	that a port is internal. In the absence of this property
	526	the port is considered to be external.
	527	$ref: /schemas/types.yaml#/definitions/flag
	528
	529	nvidia,usb2-companion:
	530	description: A single cell that specifies the physical port
	531	number to map this super-speed USB port to. The range of
	532	valid port numbers varies with the SoC generation.
	533	$ref: /schemas/types.yaml#/definitions/uint32
	534	enum: [ 0, 1, 2, 3 ]
	535
	536	vbus-supply:
	537	description: A phandle to the regulator supplying the VBUS
	538	voltage.
	539
	540	usb3-1:
	541	type: object
	542	additionalProperties: false
	543	properties:
	544	nvidia,internal:
	545	description: A boolean property whose presence determines
	546	that a port is internal. In the absence of this property
	547	the port is considered to be external.
	548	$ref: /schemas/types.yaml#/definitions/flag
	549
	550	nvidia,usb2-companion:
	551	description: A single cell that specifies the physical port
	552	number to map this super-speed USB port to. The range of
	553	valid port numbers varies with the SoC generation.
	554	$ref: /schemas/types.yaml#/definitions/uint32
	555	enum: [ 0, 1, 2, 3 ]
	556
	557	vbus-supply:
	558	description: A phandle to the regulator supplying the VBUS
	559	voltage.
	560
	561	usb3-2:
	562	type: object
	563	additionalProperties: false
	564	properties:
	565	nvidia,internal:
	566	description: A boolean property whose presence determines
	567	that a port is internal. In the absence of this property
	568	the port is considered to be external.
	569	$ref: /schemas/types.yaml#/definitions/flag
	570
	571	nvidia,usb2-companion:
	572	description: A single cell that specifies the physical port
	573	number to map this super-speed USB port to. The range of
	574	valid port numbers varies with the SoC generation.
	575	$ref: /schemas/types.yaml#/definitions/uint32
	576	enum: [ 0, 1, 2, 3 ]
	577
	578	vbus-supply:
	579	description: A phandle to the regulator supplying the VBUS
	580	voltage.
	581
	582	usb3-3:
	583	type: object
	584	additionalProperties: false
	585	properties:
	586	nvidia,internal:
	587	description: A boolean property whose presence determines
	588	that a port is internal. In the absence of this property
	589	the port is considered to be external.
	590	$ref: /schemas/types.yaml#/definitions/flag
	591
	592	nvidia,usb2-companion:
	593	description: A single cell that specifies the physical port
	594	number to map this super-speed USB port to. The range of
	595	valid port numbers varies with the SoC generation.
	596	$ref: /schemas/types.yaml#/definitions/uint32
	597	enum: [ 0, 1, 2, 3 ]
	598
	599	vbus-supply:
	600	description: A phandle to the regulator supplying the VBUS
	601	voltage.
	602
	603	additionalProperties: false
	604
	605	required:
	606	- avdd-pll-utmip-supply
	607	- avdd-pll-uerefe-supply
	608	- dvdd-pex-pll-supply
	609	- hvdd-pex-pll-e-supply
	610
	611	examples:
	612	- \|
	613	#include <dt-bindings/clock/tegra210-car.h>
	614	#include <dt-bindings/gpio/tegra-gpio.h>
	615	#include <dt-bindings/interrupt-controller/arm-gic.h>
	616
	617	padctl@7009f000 {
	618	compatible = "nvidia,tegra210-xusb-padctl";
	619	reg = <0x7009f000 0x1000>;
	620	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	621	resets = <&tegra_car 142>;
	622	reset-names = "padctl";
	623
	624	avdd-pll-utmip-supply = <&vdd_1v8>;
	625	avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
	626	dvdd-pex-pll-supply = <&vdd_pex_1v05>;
	627	hvdd-pex-pll-e-supply = <&vdd_1v8>;
	628
	629	pads {
	630	usb2 {
	631	clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
	632	clock-names = "trk";
	633
	634	lanes {
	635	usb2-0 {
	636	nvidia,function = "xusb";
	637	#phy-cells = <0>;
	638	};
	639
	640	usb2-1 {
	641	nvidia,function = "xusb";
	642	#phy-cells = <0>;
	643	};
	644
	645	usb2-2 {
	646	nvidia,function = "xusb";
	647	#phy-cells = <0>;
	648	};
	649
	650	usb2-3 {
	651	nvidia,function = "xusb";
	652	#phy-cells = <0>;
	653	};
	654	};
	655	};
	656
	657	hsic {
	658	clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
	659	clock-names = "trk";
	660	status = "disabled";
	661
	662	lanes {
	663	hsic-0 {
	664	status = "disabled";
	665	#phy-cells = <0>;
	666	};
	667
	668	hsic-1 {
	669	status = "disabled";
	670	#phy-cells = <0>;
	671	};
	672	};
	673	};
	674
	675	pcie {
	676	clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
	677	clock-names = "pll";
	678	resets = <&tegra_car 205>;
	679	reset-names = "phy";
	680
	681	lanes {
	682	pcie-0 {
	683	nvidia,function = "pcie-x1";
	684	#phy-cells = <0>;
	685	};
	686
	687	pcie-1 {
	688	nvidia,function = "pcie-x4";
	689	#phy-cells = <0>;
	690	};
	691
	692	pcie-2 {
	693	nvidia,function = "pcie-x4";
	694	#phy-cells = <0>;
	695	};
	696
	697	pcie-3 {
	698	nvidia,function = "pcie-x4";
	699	#phy-cells = <0>;
	700	};
	701
	702	pcie-4 {
	703	nvidia,function = "pcie-x4";
	704	#phy-cells = <0>;
	705	};
	706
	707	pcie-5 {
	708	nvidia,function = "usb3-ss";
	709	#phy-cells = <0>;
	710	};
	711
	712	pcie-6 {
	713	nvidia,function = "usb3-ss";
	714	#phy-cells = <0>;
	715	};
	716	};
	717	};
	718
	719	sata {
	720	clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
	721	clock-names = "pll";
	722	resets = <&tegra_car 204>;
	723	reset-names = "phy";
	724
	725	lanes {
	726	sata-0 {
	727	nvidia,function = "sata";
	728	#phy-cells = <0>;
	729	};
	730	};
	731	};
	732	};
	733
	734	ports {
	735	usb2-0 {
	736	mode = "peripheral";
	737	usb-role-switch;
	738
	739	connector {
	740	compatible = "gpio-usb-b-connector",
	741	"usb-b-connector";
	742	label = "micro-USB";
	743	type = "micro";
	744	vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_LOW>;
	745	};
	746	};
	747
	748	usb2-1 {
	749	vbus-supply = <&vdd_5v0_rtl>;
	750	mode = "host";
	751	};
	752
	753	usb2-2 {
	754	vbus-supply = <&vdd_usb_vbus>;
	755	mode = "host";
	756	};
	757
	758	usb2-3 {
	759	mode = "host";
	760	};
	761
	762	hsic-0 {
	763	status = "disabled";
	764	};
	765
	766	hsic-1 {
	767	status = "disabled";
	768	};
	769
	770	usb3-0 {
	771	nvidia,usb2-companion = <1>;
	772	};
	773
	774	usb3-1 {
	775	nvidia,usb2-companion = <2>;
	776	};
	777
	778	usb3-2 {
	779	status = "disabled";
	780	};
	781
	782	usb3-3 {
	783	status = "disabled";
	784	};
	785	};
	786	};

Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml+3−0

@@ -75,6 +75,9 @@ patternProperties: · 74 unmodified lines
75	minItems: 3	75	minItems: 3
76	maxItems: 6	76	maxItems: 6
77		77
		78	"#clock-cells":
		79	const: 1
		80
78	"#phy-cells":	81	"#phy-cells":
79	const: 0	82	const: 0
80		83

Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml+3−0

       - qcom,sdm845-qmp-usb3-uni-phy
       - qcom,sdx55-qmp-usb3-uni-phy
       - qcom,sdx65-qmp-usb3-uni-phy
+      - qcom,sm6115-qmp-usb3-phy
       - qcom,sm8150-qmp-usb3-phy
       - qcom,sm8150-qmp-usb3-uni-phy
       - qcom,sm8250-qmp-usb3-phy
           contains:
             enum:
               - qcom,qcm2290-qmp-usb3-phy
+              - qcom,sm6115-qmp-usb3-phy
     then:
       properties:
         clocks:
               - qcom,sc8180x-qmp-usb3-phy
               - qcom,sdx55-qmp-usb3-uni-phy
               - qcom,sdx65-qmp-usb3-uni-phy
+              - qcom,sm6115-qmp-usb3-phy
               - qcom,sm8150-qmp-usb3-uni-phy
               - qcom,sm8250-qmp-usb3-phy
     then:

Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml+86−0

@@ -0,0 +1,86 @@
	1	# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm PCIe2 PHY controller
	8
	9	maintainers:
	10	- Vinod Koul <vkoul@kernel.org>
	11
	12	description:
	13	The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
	14	platforms.
	15
	16	properties:
	17	compatible:
	18	items:
	19	- const: qcom,qcs404-pcie2-phy
	20	- const: qcom,pcie2-phy
	21
	22	reg:
	23	items:
	24	- description: PHY register set
	25
	26	clocks:
	27	items:
	28	- description: a clock-specifier pair for the "pipe" clock
	29
	30	clock-output-names:
	31	maxItems: 1
	32
	33	"#clock-cells":
	34	const: 0
	35
	36	"#phy-cells":
	37	const: 0
	38
	39	vdda-vp-supply:
	40	description: low voltage regulator
	41
	42	vdda-vph-supply:
	43	description: high voltage regulator
	44
	45	resets:
	46	maxItems: 2
	47
	48	reset-names:
	49	items:
	50	- const: phy
	51	- const: pipe
	52
	53	required:
	54	- compatible
	55	- reg
	56	- clocks
	57	- clock-output-names
	58	- "#clock-cells"
	59	- "#phy-cells"
	60	- vdda-vp-supply
	61	- vdda-vph-supply
	62	- resets
	63	- reset-names
	64
	65	additionalProperties: false
	66
	67	examples:
	68	- \|
	69	#include <dt-bindings/clock/qcom,gcc-qcs404.h>
	70	phy@7786000 {
	71	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
	72	reg = <0x07786000 0xb8>;
	73
	74	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
	75	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
	76	<&gcc GCC_PCIE_0_PIPE_ARES>;
	77	reset-names = "phy", "pipe";
	78
	79	vdda-vp-supply = <&vreg_l3_1p05>;
	80	vdda-vph-supply = <&vreg_l5_1p8>;
	81
	82	clock-output-names = "pcie_0_pipe_clk";
	83	#clock-cells = <0>;
	84	#phy-cells = <0>;
	85	};
	86	...

Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml+85−75

@@ -82,81 +82,74 @@ properties: · 81 unmodified lines
82	Phandle to TCSR syscon register region.	82	Phandle to TCSR syscon register region.
83	$ref: /schemas/types.yaml#/definitions/phandle	83	$ref: /schemas/types.yaml#/definitions/phandle
84		84
85	if:	85	qcom,imp-res-offset-value:
86	properties:	86	description:
87	compatible:	87	It is a 6 bit value that specifies offset to be
88	contains:	88	added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
89	const: qcom,qusb2-v2-phy	89	tuning parameter that may vary for different boards of same SOC.
90	then:	90	$ref: /schemas/types.yaml#/definitions/uint32
91	properties:	91	minimum: 0
92	qcom,imp-res-offset-value:	92	maximum: 63
93	description:	93	default: 0
94	It is a 6 bit value that specifies offset to be	94
95	added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY	95	qcom,bias-ctrl-value:
96	tuning parameter that may vary for different boards of same SOC.	96	description:
97	$ref: /schemas/types.yaml#/definitions/uint32	97	It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
98	minimum: 0	98	tuning parameter that may vary for different boards of same SOC.
99	maximum: 63	99	$ref: /schemas/types.yaml#/definitions/uint32
100	default: 0	100	minimum: 0
101		101	maximum: 63
102	qcom,bias-ctrl-value:	102	default: 32
103	description:	103
104	It is a 6 bit value that specifies bias-ctrl-value. It is a PHY	104	qcom,charge-ctrl-value:
105	tuning parameter that may vary for different boards of same SOC.	105	description:
106	$ref: /schemas/types.yaml#/definitions/uint32	106	It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
107	minimum: 0	107	tuning parameter that may vary for different boards of same SOC.
108	maximum: 63	108	$ref: /schemas/types.yaml#/definitions/uint32
109	default: 32	109	minimum: 0
110		110	maximum: 3
111	qcom,charge-ctrl-value:	111	default: 0
112	description:	112
113	It is a 2 bit value that specifies charge-ctrl-value. It is a PHY	113	qcom,hstx-trim-value:
114	tuning parameter that may vary for different boards of same SOC.	114	description:
115	$ref: /schemas/types.yaml#/definitions/uint32	115	It is a 4 bit value that specifies tuning for HSTX
116	minimum: 0	116	output current.
117	maximum: 3	117	Possible range is - 15mA to 24mA (stepsize of 600 uA).
118	default: 0	118	See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
119		119	$ref: /schemas/types.yaml#/definitions/uint32
120	qcom,hstx-trim-value:	120	minimum: 0
121	description:	121	maximum: 15
122	It is a 4 bit value that specifies tuning for HSTX	122	default: 3
123	output current.	123
124	Possible range is - 15mA to 24mA (stepsize of 600 uA).	124	qcom,preemphasis-level:
125	See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.	125	description:
126	$ref: /schemas/types.yaml#/definitions/uint32	126	It is a 2 bit value that specifies pre-emphasis level.
127	minimum: 0	127	Possible range is 0 to 15% (stepsize of 5%).
128	maximum: 15	128	See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
129	default: 3	129	$ref: /schemas/types.yaml#/definitions/uint32
130		130	minimum: 0
131	qcom,preemphasis-level:	131	maximum: 3
132	description:	132	default: 2
133	It is a 2 bit value that specifies pre-emphasis level.	133
134	Possible range is 0 to 15% (stepsize of 5%).	134	qcom,preemphasis-width:
135	See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.	135	description:
136	$ref: /schemas/types.yaml#/definitions/uint32	136	It is a 1 bit value that specifies how long the HSTX
137	minimum: 0	137	pre-emphasis (specified using qcom,preemphasis-level) must be in
138	maximum: 3	138	effect. Duration could be half-bit of full-bit.
139	default: 2	139	See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
140		140	$ref: /schemas/types.yaml#/definitions/uint32
141	qcom,preemphasis-width:	141	minimum: 0
142	description:	142	maximum: 1
143	It is a 1 bit value that specifies how long the HSTX	143	default: 0
144	pre-emphasis (specified using qcom,preemphasis-level) must be in	144
145	effect. Duration could be half-bit of full-bit.	145	qcom,hsdisc-trim-value:
146	See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.	146	description:
147	$ref: /schemas/types.yaml#/definitions/uint32	147	It is a 2 bit value tuning parameter that control disconnect
148	minimum: 0	148	threshold and may vary for different boards of same SOC.
149	maximum: 1	149	$ref: /schemas/types.yaml#/definitions/uint32
150	default: 0	150	minimum: 0
151		151	maximum: 3
152	qcom,hsdisc-trim-value:	152	default: 0
153	description:
154	It is a 2 bit value tuning parameter that control disconnect
155	threshold and may vary for different boards of same SOC.
156	$ref: /schemas/types.yaml#/definitions/uint32
157	minimum: 0
158	maximum: 3
159	default: 0
160		153
161	required:	154	required:
162	- compatible	155	- compatible
@@ -169,6 +162,23 @@ required: · 6 unmodified lines
169	- vdda-phy-dpdm-supply	162	- vdda-phy-dpdm-supply
170	- resets	163	- resets
171		164
		165	allOf:
		166	- if:
		167	not:
		168	properties:
		169	compatible:
		170	contains:
		171	const: qcom,qusb2-v2-phy
		172	then:
		173	properties:
		174	qcom,imp-res-offset-value: false
		175	qcom,bias-ctrl-value: false
		176	qcom,charge-ctrl-value: false
		177	qcom,hstx-trim-value: false
		178	qcom,preemphasis-level: false
		179	qcom,preemphasis-width: false
		180	qcom,hsdisc-trim-value: false
		181
172	additionalProperties: false	182	additionalProperties: false
173		183
174	examples:	184	examples:

Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml+73−16

@@ -19,12 +19,17 @@ maintainers: · 18 unmodified lines
19		19
20	properties:	20	properties:
21	compatible:	21	compatible:
22	enum:	22	oneOf:
23	- qcom,sc7180-qmp-usb3-dp-phy	23	- enum:
24	- qcom,sc7280-qmp-usb3-dp-phy	24	- qcom,sc7180-qmp-usb3-dp-phy
25	- qcom,sc8180x-qmp-usb3-dp-phy	25	- qcom,sc8180x-qmp-usb3-dp-phy
26	- qcom,sdm845-qmp-usb3-dp-phy	26	- qcom,sdm845-qmp-usb3-dp-phy
27	- qcom,sm8250-qmp-usb3-dp-phy	27	- qcom,sm8250-qmp-usb3-dp-phy
		28	- items:
		29	- enum:
		30	- qcom,sc7280-qmp-usb3-dp-phy
		31	- const: qcom,sm8250-qmp-usb3-dp-phy
		32
28	reg:	33	reg:
29	items:	34	items:
30	- description: Address and length of PHY's USB serdes block.	35	- description: Address and length of PHY's USB serdes block.
@@ -46,18 +51,12 @@ properties: · 15 unmodified lines
46	ranges: true	51	ranges: true
47		52
48	clocks:	53	clocks:
49	items:	54	minItems: 3
50	- description: Phy aux clock.	55	maxItems: 4
51	- description: Phy config clock.
52	- description: 19.2 MHz ref clk.
53	- description: Phy common block aux clock.
54		56
55	clock-names:	57	clock-names:
56	items:	58	minItems: 3
57	- const: aux	59	maxItems: 4
58	- const: cfg_ahb
59	- const: ref
60	- const: com_aux
61		60
62	power-domains:	61	power-domains:
63	maxItems: 1	62	maxItems: 1
@@ -166,6 +165,64 @@ required: · 102 unmodified lines
166	- vdda-phy-supply	165	- vdda-phy-supply
167	- vdda-pll-supply	166	- vdda-pll-supply
168		167
		168	allOf:
		169	- if:
		170	properties:
		171	compatible:
		172	enum:
		173	- qcom,sc7180-qmp-usb3-dp-phy
		174	- qcom,sdm845-qmp-usb3-dp-phy
		175	then:
		176	properties:
		177	clocks:
		178	items:
		179	- description: Phy aux clock
		180	- description: Phy config clock
		181	- description: 19.2 MHz ref clk
		182	- description: Phy common block aux clock
		183	clock-names:
		184	items:
		185	- const: aux
		186	- const: cfg_ahb
		187	- const: ref
		188	- const: com_aux
		189
		190	- if:
		191	properties:
		192	compatible:
		193	enum:
		194	- qcom,sc8180x-qmp-usb3-dp-phy
		195	then:
		196	properties:
		197	clocks:
		198	items:
		199	- description: Phy aux clock
		200	- description: 19.2 MHz ref clk
		201	- description: Phy common block aux clock
		202	clock-names:
		203	items:
		204	- const: aux
		205	- const: ref
		206	- const: com_aux
		207
		208	- if:
		209	properties:
		210	compatible:
		211	enum:
		212	- qcom,sm8250-qmp-usb3-dp-phy
		213	then:
		214	properties:
		215	clocks:
		216	items:
		217	- description: Phy aux clock
		218	- description: Board XO source
		219	- description: Phy common block aux clock
		220	clock-names:
		221	items:
		222	- const: aux
		223	- const: ref_clk_src
		224	- const: com_aux
		225
169	additionalProperties: false	226	additionalProperties: false
170		227
171	examples:	228	examples:

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml+51−1

@@ -19,15 +19,20 @@ properties: · 18 unmodified lines
19	- qcom,sc8280xp-qmp-gen3x1-pcie-phy	19	- qcom,sc8280xp-qmp-gen3x1-pcie-phy
20	- qcom,sc8280xp-qmp-gen3x2-pcie-phy	20	- qcom,sc8280xp-qmp-gen3x2-pcie-phy
21	- qcom,sc8280xp-qmp-gen3x4-pcie-phy	21	- qcom,sc8280xp-qmp-gen3x4-pcie-phy
		22	- qcom,sm8350-qmp-gen3x1-pcie-phy
		23	- qcom,sm8550-qmp-gen3x2-pcie-phy
		24	- qcom,sm8550-qmp-gen4x2-pcie-phy
22		25
23	reg:	26	reg:
24	minItems: 1	27	minItems: 1
25	maxItems: 2	28	maxItems: 2
26		29
27	clocks:	30	clocks:
		31	minItems: 5
28	maxItems: 6	32	maxItems: 6
29		33
30	clock-names:	34	clock-names:
		35	minItems: 5
31	items:	36	items:
32	- const: aux	37	- const: aux
33	- const: cfg_ahb	38	- const: cfg_ahb
@@ -40,16 +45,21 @@ properties: · 6 unmodified lines
40	maxItems: 1	45	maxItems: 1
41		46
42	resets:	47	resets:
43	maxItems: 1	48	minItems: 1
		49	maxItems: 2
44		50
45	reset-names:	51	reset-names:
		52	minItems: 1
46	items:	53	items:
47	- const: phy	54	- const: phy
		55	- const: phy_nocsr
48		56
49	vdda-phy-supply: true	57	vdda-phy-supply: true
50		58
51	vdda-pll-supply: true	59	vdda-pll-supply: true
52		60
		61	vdda-qref-supply: true
		62
53	qcom,4ln-config-sel:	63	qcom,4ln-config-sel:
54	description: PCIe 4-lane configuration	64	description: PCIe 4-lane configuration
55	$ref: /schemas/types.yaml#/definitions/phandle-array	65	$ref: /schemas/types.yaml#/definitions/phandle-array
@@ -104,6 +114,46 @@ allOf: · 48 unmodified lines
104	reg:	114	reg:
105	maxItems: 1	115	maxItems: 1
106		116
		117	- if:
		118	properties:
		119	compatible:
		120	contains:
		121	enum:
		122	- qcom,sm8350-qmp-gen3x1-pcie-phy
		123	- qcom,sm8550-qmp-gen3x2-pcie-phy
		124	- qcom,sm8550-qmp-gen4x2-pcie-phy
		125	then:
		126	properties:
		127	clocks:
		128	maxItems: 5
		129	clock-names:
		130	maxItems: 5
		131	else:
		132	properties:
		133	clocks:
		134	minItems: 6
		135	clock-names:
		136	minItems: 6
		137
		138	- if:
		139	properties:
		140	compatible:
		141	contains:
		142	enum:
		143	- qcom,sm8550-qmp-gen4x2-pcie-phy
		144	then:
		145	properties:
		146	resets:
		147	minItems: 2
		148	reset-names:
		149	minItems: 2
		150	else:
		151	properties:
		152	resets:
		153	maxItems: 1
		154	reset-names:
		155	maxItems: 1
		156
107	examples:	157	examples:
108	- \|	158	- \|
109	#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>	159	#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml+5−0

   compatible:
     enum:
       - qcom,sc8280xp-qmp-ufs-phy
+      - qcom,sm6125-qmp-ufs-phy
+      - qcom,sm8550-qmp-ufs-phy
   reg:
     maxItems: 1
   vdda-pll-supply: true
+  "#clock-cells":
+    const: 1
   "#phy-cells":
     const: 0

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml+4−0

   compatible:
     enum:
       - qcom,sc8280xp-qmp-usb43dp-phy
+      - qcom,sm6350-qmp-usb3-dp-phy
+      - qcom,sm8350-qmp-usb3-dp-phy
+      - qcom,sm8450-qmp-usb3-dp-phy
+      - qcom,sm8550-qmp-usb3-dp-phy
   reg:
     maxItems: 1

Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml+79−0

@@ -0,0 +1,79 @@
	1	# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm SNPS eUSB2 phy controller
	8
	9	maintainers:
	10	- Abel Vesa <abel.vesa@linaro.org>
	11
	12	description:
	13	eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
	14
	15	properties:
	16	compatible:
	17	const: qcom,sm8550-snps-eusb2-phy
	18
	19	reg:
	20	maxItems: 1
	21
	22	"#phy-cells":
	23	const: 0
	24
	25	clocks:
	26	items:
	27	- description: ref
	28
	29	clock-names:
	30	items:
	31	- const: ref
	32
	33	resets:
	34	maxItems: 1
	35
	36	phys:
	37	maxItems: 1
	38	description:
	39	Phandle to eUSB2 to USB 2.0 repeater
	40
	41	vdd-supply:
	42	description:
	43	Phandle to 0.88V regulator supply to PHY digital circuit.
	44
	45	vdda12-supply:
	46	description:
	47	Phandle to 1.2V regulator supply to PHY refclk pll block.
	48
	49	required:
	50	- compatible
	51	- reg
	52	- "#phy-cells"
	53	- clocks
	54	- clock-names
	55	- vdd-supply
	56	- vdda12-supply
	57	- resets
	58
	59	additionalProperties: false
	60
	61	examples:
	62	- \|
	63	#include <dt-bindings/clock/qcom,sm8550-gcc.h>
	64	#include <dt-bindings/clock/qcom,rpmh.h>
	65	#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
	66
	67	usb_1_hsphy: phy@88e3000 {
	68	compatible = "qcom,sm8550-snps-eusb2-phy";
	69	reg = <0x88e3000 0x154>;
	70	#phy-cells = <0>;
	71
	72	clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
	73	clock-names = "ref";
	74
	75	vdd-supply = <&vreg_l1e_0p88>;
	76	vdda12-supply = <&vreg_l3e_1p2>;
	77
	78	resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
	79	};

Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml+52−0

@@ -0,0 +1,52 @@
	1	# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-repeater.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm Synopsis eUSB2 to USB 2.0 repeater
	8
	9	maintainers:
	10	- Abel Vesa <abel.vesa@linaro.org>
	11
	12	description:
	13	eUSB2 repeater converts between eUSB2 and USB 2.0 signaling levels and
	14	allows a eUSB2 PHY to connect to legacy USB 2.0 products
	15
	16	properties:
	17	compatible:
	18	const: qcom,pm8550b-eusb2-repeater
	19
	20	reg:
	21	maxItems: 1
	22
	23	"#phy-cells":
	24	const: 0
	25
	26	vdd18-supply: true
	27
	28	vdd3-supply: true
	29
	30	required:
	31	- compatible
	32	- reg
	33	- "#phy-cells"
	34
	35	additionalProperties: false
	36
	37	examples:
	38	- \|
	39	#include <dt-bindings/spmi/spmi.h>
	40
	41	pmic@7 {
	42	reg = <0x7 SPMI_USID>;
	43	#address-cells = <1>;
	44	#size-cells = <0>;
	45
	46	pm8550b_eusb2_repeater: phy@fd00 {
	47	compatible = "qcom,pm8550b-eusb2-repeater";
	48	reg = <0xfd00>;
	49	#phy-cells = <0>;
	50	};
	51	};
	52	...

Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt+0−65

@@ -1,65 +0,0 @@
1	Qualcomm's USB HSIC PHY
2
3	PROPERTIES
4
5	- compatible:
6	Usage: required
7	Value type: <string>
8	Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
9	following:
10
11	"qcom,usb-hsic-phy-mdm9615"
12	"qcom,usb-hsic-phy-msm8974"
13
14	- #phy-cells:
15	Usage: required
16	Value type: <u32>
17	Definition: Should contain 0
18
19	- clocks:
20	Usage: required
21	Value type: <prop-encoded-array>
22	Definition: Should contain clock specifier for phy, calibration and
23	a calibration sleep clock
24
25	- clock-names:
26	Usage: required
27	Value type: <stringlist>
28	Definition: Should contain "phy, "cal" and "cal_sleep"
29
30	- pinctrl-names:
31	Usage: required
32	Value type: <stringlist>
33	Definition: Should contain "init" and "default" in that order
34
35	- pinctrl-0:
36	Usage: required
37	Value type: <prop-encoded-array>
38	Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch
39	free state
40
41	- pinctrl-1:
42	Usage: required
43	Value type: <prop-encoded-array>
44	Definition: List of pinctrl settings to apply to mux out the HSIC pins
45
46	EXAMPLE
47
48	usb-controller {
49	ulpi {
50	phy {
51	compatible = "qcom,usb-hsic-phy-msm8974",
52	"qcom,usb-hsic-phy";
53	#phy-cells = <0>;
54	pinctrl-names = "init", "default";
55	pinctrl-0 = <&hsic_sleep>;
56	pinctrl-1 = <&hsic_default>;
57	clocks = <&gcc GCC_USB_HSIC_CLK>,
58	<&gcc GCC_USB_HSIC_IO_CAL_CLK>,
59	<&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
60	clock-names = "phy", "cal", "cal_sleep";
61	assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>;
62	assigned-clock-rates = <960000>;
63	};
64	};
65	};

Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml+67−0

@@ -0,0 +1,67 @@
	1	# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm USB HSIC PHY Controller
	8
	9	maintainers:
	10	- Bjorn Andersson <andersson@kernel.org>
	11	- Vinod Koul <vkoul@kernel.org>
	12
	13	properties:
	14	compatible:
	15	items:
	16	- enum:
	17	- qcom,usb-hsic-phy-mdm9615
	18	- qcom,usb-hsic-phy-msm8974
	19	- const: qcom,usb-hsic-phy
	20
	21	clocks:
	22	maxItems: 3
	23
	24	clock-names:
	25	items:
	26	- const: phy
	27	- const: cal
	28	- const: cal_sleep
	29
	30	"#phy-cells":
	31	const: 0
	32
	33	pinctrl-0: true
	34	pinctrl-1: true
	35
	36	pinctrl-names:
	37	items:
	38	- const: init
	39	- const: default
	40
	41	required:
	42	- compatible
	43	- clocks
	44	- clock-names
	45	- "#phy-cells"
	46	- pinctrl-0
	47	- pinctrl-1
	48	- pinctrl-names
	49
	50	additionalProperties: false
	51
	52	examples:
	53	- \|
	54	#include <dt-bindings/clock/qcom,gcc-msm8974.h>
	55
	56	phy {
	57	compatible = "qcom,usb-hsic-phy-msm8974",
	58	"qcom,usb-hsic-phy";
	59	clocks = <&gcc GCC_USB_HSIC_CLK>,
	60	<&gcc GCC_USB_HSIC_IO_CAL_CLK>,
	61	<&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
	62	clock-names = "phy", "cal", "cal_sleep";
	63	#phy-cells = <0>;
	64	pinctrl-names = "init", "default";
	65	pinctrl-0 = <&hsic_sleep>;
	66	pinctrl-1 = <&hsic_default>;
	67	};

Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml+20−13

@@ -14,18 +14,25 @@ description: \| · 13 unmodified lines
14		14
15	properties:	15	properties:
16	compatible:	16	compatible:
17	enum:	17	oneOf:
18	- qcom,usb-snps-hs-5nm-phy	18	- enum:
19	- qcom,usb-snps-hs-7nm-phy	19	- qcom,sc8180x-usb-hs-phy
20	- qcom,sc7280-usb-hs-phy	20	- qcom,usb-snps-femto-v2-phy
21	- qcom,sc8180x-usb-hs-phy	21	- items:
22	- qcom,sc8280xp-usb-hs-phy	22	- enum:
23	- qcom,sm6375-usb-hs-phy	23	- qcom,sc8280xp-usb-hs-phy
24	- qcom,sm8150-usb-hs-phy	24	- const: qcom,usb-snps-hs-5nm-phy
25	- qcom,sm8250-usb-hs-phy	25	- items:
26	- qcom,sm8350-usb-hs-phy	26	- enum:
27	- qcom,sm8450-usb-hs-phy	27	- qcom,sc7280-usb-hs-phy
28	- qcom,usb-snps-femto-v2-phy	28	- qcom,sdx55-usb-hs-phy
		29	- qcom,sdx65-usb-hs-phy
		30	- qcom,sm6375-usb-hs-phy
		31	- qcom,sm8150-usb-hs-phy
		32	- qcom,sm8250-usb-hs-phy
		33	- qcom,sm8350-usb-hs-phy
		34	- qcom,sm8450-usb-hs-phy
		35	- const: qcom,usb-snps-hs-7nm-phy
29		36
30	reg:	37	reg:
31	maxItems: 1	38	maxItems: 1
@@ -160,7 +167,7 @@ examples: · 128 unmodified lines
160	#include <dt-bindings/clock/qcom,rpmh.h>	167	#include <dt-bindings/clock/qcom,rpmh.h>
161	#include <dt-bindings/clock/qcom,gcc-sm8150.h>	168	#include <dt-bindings/clock/qcom,gcc-sm8150.h>
162	phy@88e2000 {	169	phy@88e2000 {
163	compatible = "qcom,sm8150-usb-hs-phy";	170	compatible = "qcom,sm8150-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy";
164	reg = <0x088e2000 0x400>;	171	reg = <0x088e2000 0x400>;
165	#phy-cells = <0>;	172	#phy-cells = <0>;
166		173

Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt+0−42

@@ -1,42 +0,0 @@
1	Qualcomm PCIe2 PHY controller
2	=============================
3
4	The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
5	platforms.
6
7	Required properties:
8	- compatible: compatible list, should be:
9	"qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
10
11	- reg: offset and length of the PHY register set.
12	- #phy-cells: must be 0.
13
14	- clocks: a clock-specifier pair for the "pipe" clock
15
16	- vdda-vp-supply: phandle to low voltage regulator
17	- vdda-vph-supply: phandle to high voltage regulator
18
19	- resets: reset-specifier pairs for the "phy" and "pipe" resets
20	- reset-names: list of resets, should contain:
21	"phy" and "pipe"
22
23	- clock-output-names: name of the outgoing clock signal from the PHY PLL
24	- #clock-cells: must be 0
25
26	Example:
27	phy@7786000 {
28	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
29	reg = <0x07786000 0xb8>;
30
31	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
32	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
33	<&gcc GCC_PCIE_0_PIPE_ARES>;
34	reset-names = "phy", "pipe";
35
36	vdda-vp-supply = <&vreg_l3_1p05>;
37	vdda-vph-supply = <&vreg_l5_1p8>;
38
39	clock-output-names = "pcie_0_pipe_clk";
40	#clock-cells = <0>;
41	#phy-cells = <0>;
42	};

Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml+1−0

@@ -15,6 +15,7 @@ properties: · 14 unmodified lines
15		15
16	compatible:	16	compatible:
17	enum:	17	enum:
		18	- nxp,tjr1443
18	- ti,tcan1042	19	- ti,tcan1042
19	- ti,tcan1043	20	- ti,tcan1043
20		21

Documentation/driver-api/phy/phy.rst+14−10

 ::
 	struct phy *phy_get(struct device *dev, const char *string);
-	struct phy *phy_optional_get(struct device *dev, const char *string);
 	struct phy *devm_phy_get(struct device *dev, const char *string);
 	struct phy *devm_phy_optional_get(struct device *dev,
 					  const char *string);
+	struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
+				    const char *con_id);
+	struct phy *devm_of_phy_optional_get(struct device *dev,
+					     struct device_node *np,
+					     const char *con_id);
 	struct phy *devm_of_phy_get_by_index(struct device *dev,
 					     struct device_node *np,
 					     int index);
-phy_get, phy_optional_get, devm_phy_get and devm_phy_optional_get can
+phy_get, devm_phy_get and devm_phy_optional_get can be used to get the PHY.
-be used to get the PHY. In the case of dt boot, the string arguments
+In the case of dt boot, the string arguments
 should contain the phy name as given in the dt data and in the case of
 non-dt boot, it should contain the label of the PHY.  The two
 devm_phy_get associates the device with the PHY using devres on
 successful PHY get. On driver detach, release function is invoked on
-the devres data and devres data is freed. phy_optional_get and
+the devres data and devres data is freed.
-devm_phy_optional_get should be used when the phy is optional. These
+The _optional_get variants should be used when the phy is optional. These
-two functions will never return -ENODEV, but instead returns NULL when
+functions will never return -ENODEV, but instead return NULL when
-the phy cannot be found.Some generic drivers, such as ehci, may use multiple
+the phy cannot be found.
-phys and for such drivers referencing phy(s) by name(s) does not make sense. In
+Some generic drivers, such as ehci, may use multiple phys. In this case,
-this case, devm_of_phy_get_by_index can be used to get a phy reference based on
+devm_of_phy_get or devm_of_phy_get_by_index can be used to get a phy
-the index.
+reference based on name or index.
 It should be noted that NULL is a valid phy reference. All phy
 consumer calls on the NULL phy become NOPs. That is the release calls,

drivers/net/ethernet/freescale/fman/fman_memac.c+4−5

 	else
 		memac->sgmii_pcs = pcs;
-	memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes");
+	memac->serdes = devm_of_phy_optional_get(mac_dev->dev, mac_node,
-	err = PTR_ERR(memac->serdes);
+						 "serdes");
-	if (err == -ENODEV || err == -ENOSYS) {
+	if (!memac->serdes) {
 		dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");
-		memac->serdes = NULL;
 	} else if (IS_ERR(memac->serdes)) {
-		dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
+		err = PTR_ERR(memac->serdes);
 		goto _return_fm_mac_free;
 	}

drivers/net/ethernet/microchip/lan966x/lan966x_main.c+2−3

 		lan966x->ports[p]->config.portmode = phy_mode;
 		lan966x->ports[p]->fwnode = fwnode_handle_get(portnp);
-		serdes = devm_of_phy_get(lan966x->dev, to_of_node(portnp), NULL);
+		serdes = devm_of_phy_optional_get(lan966x->dev,
-		if (PTR_ERR(serdes) == -ENODEV)
+						  to_of_node(portnp), NULL);
-			serdes = NULL;
 		if (IS_ERR(serdes)) {
 			err = PTR_ERR(serdes);
 			goto cleanup_ports;

drivers/pci/controller/pci-tegra.c+1−4

 	if (!name)
 		return ERR_PTR(-ENOMEM);
-	phy = devm_of_phy_get(dev, np, name);
+	phy = devm_of_phy_optional_get(dev, np, name);
 	kfree(name);
-	if (PTR_ERR(phy) == -ENODEV)
-		phy = NULL;
 	return phy;
 }

drivers/phy/allwinner/phy-sun4i-usb.c+24−35

 #define DEBOUNCE_TIME			msecs_to_jiffies(50)
 #define POLL_TIME			msecs_to_jiffies(250)
-enum sun4i_usb_phy_type {
-	sun4i_a10_phy,
-	sun6i_a31_phy,
-	sun8i_a33_phy,
-	sun8i_a83t_phy,
-	sun8i_h3_phy,
-	sun8i_r40_phy,
-	sun8i_v3s_phy,
-	sun50i_a64_phy,
-	sun50i_h6_phy,
-};
 struct sun4i_usb_phy_cfg {
 	int num_phys;
 	int hsic_index;
-	enum sun4i_usb_phy_type type;
 	u32 disc_thresh;
 	u32 hci_phy_ctl_clear;
 	u8 phyctl_offset;
 	bool dedicated_clocks;
 	bool phy0_dual_route;
 	bool needs_phy2_siddq;
+	bool siddq_in_base;
+	bool poll_vbusen;
 	int missing_phys;
 };
 		SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 	/* A83T USB2 is HSIC */
-	if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2)
+	if (phy_data->cfg->hsic_index &&
+	    phy->index == phy_data->cfg->hsic_index)
 		bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
 			SUNXI_HSIC;
 		writel(val, phy->pmu + REG_HCI_PHY_CTL);
 	}
-	if (data->cfg->type == sun8i_a83t_phy ||
+	if (data->cfg->siddq_in_base) {
-	    data->cfg->type == sun50i_h6_phy) {
 		if (phy->index == 0) {
 			val = readl(data->base + data->cfg->phyctl_offset);
 			val |= PHY_CTL_VBUSVLDEXT;
 	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
 	if (phy->index == 0) {
-		if (data->cfg->type == sun8i_a83t_phy ||
+		if (data->cfg->siddq_in_base) {
-		    data->cfg->type == sun50i_h6_phy) {
 			void __iomem *phyctl = data->base +
 				data->cfg->phyctl_offset;
 	 * vbus using the N_VBUSEN pin on the pmic, so we must poll
 	 * when using the pmic for vbus-det _and_ we're driving vbus.
 	 */
-	if ((data->cfg->type == sun6i_a31_phy ||
+	if (data->cfg->poll_vbusen && data->vbus_power_supply &&
-	     data->cfg->type == sun8i_a33_phy) &&
+	    data->phys[0].regulator_on)
-	    data->vbus_power_supply && data->phys[0].regulator_on)
 		return true;
 	return false;
 	return 0;
 }
+static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
+	.num_phys = 1,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
+};
 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 	.num_phys = 3,
-	.type = sun4i_a10_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 	.num_phys = 2,
-	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 	.num_phys = 3,
-	.type = sun6i_a31_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = true,
+	.poll_vbusen = true,
 };
 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 	.num_phys = 3,
-	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 	.num_phys = 2,
-	.type = sun6i_a31_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = true,
+	.poll_vbusen = true,
 };
 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 	.num_phys = 2,
-	.type = sun8i_a33_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
+	.poll_vbusen = true,
 };
 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 	.num_phys = 3,
 	.hsic_index = 2,
-	.type = sun8i_a83t_phy,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
+	.siddq_in_base = true,
 };
 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.num_phys = 4,
-	.type = sun8i_h3_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
 	.num_phys = 3,
-	.type = sun8i_r40_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 	.num_phys = 1,
-	.type = sun8i_v3s_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
 	.num_phys = 2,
-	.type = sun50i_h6_phy,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
 	.phy0_dual_route = true,
+	.siddq_in_base = true,
 };
 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.num_phys = 2,
-	.type = sun50i_a64_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 	.num_phys = 4,
-	.type = sun50i_h6_phy,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 	.phy0_dual_route = true,
 	.missing_phys = BIT(1) | BIT(2),
+	.siddq_in_base = true,
 };
 static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
 	.num_phys = 4,
-	.type = sun50i_h6_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 	.phy0_dual_route = true,
 	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
 	.needs_phy2_siddq = true,
+	.siddq_in_base = true,
 };
 static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	  .data = &sun50i_a64_cfg},
 	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
 	{ .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
+	{ .compatible = "allwinner,suniv-f1c100s-usb-phy",
+	  .data = &suniv_f1c100s_cfg },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);

drivers/phy/mediatek/phy-mtk-io.h+2−2

@@ -39,8 +39,8 @@ static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val) · 38 unmodified lines
39	/* field @mask shall be constant and continuous */	39	/* field @mask shall be constant and continuous */
40	#define mtk_phy_update_field(reg, mask, val) \	40	#define mtk_phy_update_field(reg, mask, val) \
41	({ \	41	({ \
42	typeof(mask) mask_ = (mask); \	42	BUILD_BUG_ON_MSG(!__builtin_constant_p(mask), "mask is not constant"); \
43	mtk_phy_update_bits(reg, mask_, FIELD_PREP(mask_, val)); \	43	mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); \
44	})	44	})
45		45
46	#endif	46	#endif

drivers/phy/phy-can-transceiver.c+4−0

 		.compatible = "ti,tcan1043",
 		.data = &tcan1043_drvdata
 	},
+	{
+		.compatible = "nxp,tjr1443",
+		.data = &tcan1043_drvdata
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, can_transceiver_phy_ids);

drivers/phy/phy-core.c+30−21

 }
 EXPORT_SYMBOL_GPL(phy_get);
-/**
- * phy_optional_get() - lookup and obtain a reference to an optional phy.
- * @dev: device that requests this phy
- * @string: the phy name as given in the dt data or the name of the controller
- * port for non-dt case
- *
- * Returns the phy driver, after getting a refcount to it; or
- * NULL if there is no such phy.  The caller is responsible for
- * calling phy_put() to release that count.
- */
-struct phy *phy_optional_get(struct device *dev, const char *string)
-{
-	struct phy *phy = phy_get(dev, string);
-	if (PTR_ERR(phy) == -ENODEV)
-		phy = NULL;
-	return phy;
-}
-EXPORT_SYMBOL_GPL(phy_optional_get);
 /**
  * devm_phy_get() - lookup and obtain a reference to a phy.
  * @dev: device that requests this phy
 }
 EXPORT_SYMBOL_GPL(devm_of_phy_get);
+/**
+ * devm_of_phy_optional_get() - lookup and obtain a reference to an optional
+ * phy.
+ * @dev: device that requests this phy
+ * @np: node containing the phy
+ * @con_id: name of the phy from device's point of view
+ *
+ * Gets the phy using of_phy_get(), and associates a device with it using
+ * devres. On driver detach, release function is invoked on the devres data,
+ * then, devres data is freed.  This differs to devm_of_phy_get() in
+ * that if the phy does not exist, it is not considered an error and
+ * -ENODEV will not be returned. Instead the NULL phy is returned,
+ * which can be passed to all other phy consumer calls.
+ */
+struct phy *devm_of_phy_optional_get(struct device *dev, struct device_node *np,
+				     const char *con_id)
+{
+	struct phy *phy = devm_of_phy_get(dev, np, con_id);
+	if (PTR_ERR(phy) == -ENODEV)
+		phy = NULL;
+	if (IS_ERR(phy))
+		dev_err_probe(dev, PTR_ERR(phy), "failed to get PHY %pOF:%s",
+			      np, con_id);
+	return phy;
+}
+EXPORT_SYMBOL_GPL(devm_of_phy_optional_get);
 /**
  * devm_of_phy_get_by_index() - lookup and obtain a reference to a phy by index.
  * @dev: device that requests this phy

drivers/phy/qualcomm/Kconfig+64−4

@@ -50,14 +50,56 @@ config PHY_QCOM_PCIE2 · 49 unmodified lines
50	Enable this to support the Qualcomm PCIe PHY, used with the Synopsys	50	Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
51	based PCIe controller.	51	based PCIe controller.
52		52
53	config PHY_QCOM_QMP	53	menuconfig PHY_QCOM_QMP
54	tristate "Qualcomm QMP PHY Driver"	54	tristate "Qualcomm QMP PHY Drivers"
55	depends on OF && COMMON_CLK && (ARCH_QCOM \|\| COMPILE_TEST)	55	depends on OF && COMMON_CLK && (ARCH_QCOM \|\| COMPILE_TEST)
		56
		57	if PHY_QCOM_QMP
		58
		59	config PHY_QCOM_QMP_COMBO
		60	tristate "Qualcomm QMP Combo PHY Driver"
		61	default PHY_QCOM_QMP
56	select GENERIC_PHY	62	select GENERIC_PHY
57	select MFD_SYSCON	63	select MFD_SYSCON
58	help	64	help
59	Enable this to support the QMP PHY transceiver that is used	65	Enable this to support the QMP Combo PHY transceiver that is used
60	with controllers such as PCIe, UFS, and USB on Qualcomm chips.	66	with USB3 and DisplayPort controllers on Qualcomm chips.
		67
		68	config PHY_QCOM_QMP_PCIE
		69	tristate "Qualcomm QMP PCIe PHY Driver"
		70	depends on PCI \|\| COMPILE_TEST
		71	select GENERIC_PHY
		72	default PHY_QCOM_QMP
		73	help
		74	Enable this to support the QMP PCIe PHY transceiver that is used
		75	with PCIe controllers on Qualcomm chips.
		76
		77	config PHY_QCOM_QMP_PCIE_8996
		78	tristate "Qualcomm QMP PCIe 8996 PHY Driver"
		79	depends on PCI \|\| COMPILE_TEST
		80	select GENERIC_PHY
		81	default PHY_QCOM_QMP
		82	help
		83	Enable this to support the QMP PCIe PHY transceiver that is used
		84	with PCIe controllers on Qualcomm msm8996 chips.
		85
		86	config PHY_QCOM_QMP_UFS
		87	tristate "Qualcomm QMP UFS PHY Driver"
		88	select GENERIC_PHY
		89	default PHY_QCOM_QMP
		90	help
		91	Enable this to support the QMP UFS PHY transceiver that is used
		92	with UFS controllers on Qualcomm chips.
		93
		94	config PHY_QCOM_QMP_USB
		95	tristate "Qualcomm QMP USB PHY Driver"
		96	select GENERIC_PHY
		97	default PHY_QCOM_QMP
		98	help
		99	Enable this to support the QMP USB PHY transceiver that is used
		100	with USB3 controllers on Qualcomm chips.
		101
		102	endif # PHY_QCOM_QMP
61		103
62	config PHY_QCOM_QUSB2	104	config PHY_QCOM_QUSB2
63	tristate "Qualcomm QUSB2 PHY Driver"	105	tristate "Qualcomm QUSB2 PHY Driver"
@@ -70,6 +112,24 @@ config PHY_QCOM_QUSB2 · 6 unmodified lines
70	PHY which is usually paired with either the ChipIdea or Synopsys DWC3	112	PHY which is usually paired with either the ChipIdea or Synopsys DWC3
71	USB IPs on MSM SOCs.	113	USB IPs on MSM SOCs.
72		114
		115	config PHY_QCOM_SNPS_EUSB2
		116	tristate "Qualcomm SNPS eUSB2 PHY Driver"
		117	depends on OF && (ARCH_QCOM \|\| COMPILE_TEST)
		118	select GENERIC_PHY
		119	help
		120	Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm
		121	chipsets. The PHY is paired with a Synopsys DWC3 USB controller
		122	on Qualcomm SOCs.
		123
		124	config PHY_QCOM_EUSB2_REPEATER
		125	tristate "Qualcomm SNPS eUSB2 Repeater Driver"
		126	depends on OF && (ARCH_QCOM \|\| COMPILE_TEST)
		127	select GENERIC_PHY
		128	help
		129	Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
		130	PMICs. The repeater is paired with a Synopsys eUSB2 Phy
		131	on Qualcomm SOCs.
		132
73	config PHY_QCOM_USB_HS	133	config PHY_QCOM_USB_HS
74	tristate "Qualcomm USB HS PHY module"	134	tristate "Qualcomm USB HS PHY module"
75	depends on USB_ULPI_BUS	135	depends on USB_ULPI_BUS

drivers/phy/qualcomm/Makefile+8−6

@@ -5,14 +5,16 @@ obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o · 4 unmodified lines
5	obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o	5	obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
6	obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o	6	obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
7	obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o	7	obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
8	obj-$(CONFIG_PHY_QCOM_QMP) += \	8
9	phy-qcom-qmp-combo.o \	9	obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o
10	phy-qcom-qmp-pcie.o \	10	obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
11	phy-qcom-qmp-pcie-msm8996.o \	11	obj-$(CONFIG_PHY_QCOM_QMP_PCIE_8996) += phy-qcom-qmp-pcie-msm8996.o
12	phy-qcom-qmp-ufs.o \	12	obj-$(CONFIG_PHY_QCOM_QMP_UFS) += phy-qcom-qmp-ufs.o
13	phy-qcom-qmp-usb.o	13	obj-$(CONFIG_PHY_QCOM_QMP_USB) += phy-qcom-qmp-usb.o
14		14
15	obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o	15	obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
		16	obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o
		17	obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER) += phy-qcom-eusb2-repeater.o
16	obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o	18	obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
17	obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o	19	obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
18	obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o	20	obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o

drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c+259−0

@@ -0,0 +1,259 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#include <linux/module.h>
	7	#include <linux/platform_device.h>
	8	#include <linux/regulator/consumer.h>
	9	#include <linux/regmap.h>
	10	#include <linux/of.h>
	11	#include <linux/of_device.h>
	12	#include <linux/phy/phy.h>
	13
	14	/* eUSB2 status registers */
	15	#define EUSB2_RPTR_STATUS 0x08
	16	#define RPTR_OK BIT(7)
	17
	18	/* eUSB2 control registers */
	19	#define EUSB2_EN_CTL1 0x46
	20	#define EUSB2_RPTR_EN BIT(7)
	21
	22	#define EUSB2_FORCE_EN_5 0xe8
	23	#define F_CLK_19P2M_EN BIT(6)
	24
	25	#define EUSB2_FORCE_VAL_5 0xeD
	26	#define V_CLK_19P2M_EN BIT(6)
	27
	28	#define EUSB2_TUNE_IUSB2 0x51
	29	#define EUSB2_TUNE_SQUELCH_U 0x54
	30	#define EUSB2_TUNE_USB2_PREEM 0x57
	31
	32	#define QCOM_EUSB2_REPEATER_INIT_CFG(o, v) \
	33	{ \
	34	.offset = o, \
	35	.val = v, \
	36	}
	37
	38	struct eusb2_repeater_init_tbl {
	39	unsigned int offset;
	40	unsigned int val;
	41	};
	42
	43	struct eusb2_repeater_cfg {
	44	const struct eusb2_repeater_init_tbl *init_tbl;
	45	int init_tbl_num;
	46	const char * const *vreg_list;
	47	int num_vregs;
	48	};
	49
	50	struct eusb2_repeater {
	51	struct device *dev;
	52	struct regmap *regmap;
	53	struct phy *phy;
	54	struct regulator_bulk_data *vregs;
	55	const struct eusb2_repeater_cfg *cfg;
	56	u16 base;
	57	enum phy_mode mode;
	58	};
	59
	60	static const char * const pm8550b_vreg_l[] = {
	61	"vdd18", "vdd3",
	62	};
	63
	64	static const struct eusb2_repeater_init_tbl pm8550b_init_tbl[] = {
	65	QCOM_EUSB2_REPEATER_INIT_CFG(EUSB2_TUNE_IUSB2, 0x8),
	66	QCOM_EUSB2_REPEATER_INIT_CFG(EUSB2_TUNE_SQUELCH_U, 0x3),
	67	QCOM_EUSB2_REPEATER_INIT_CFG(EUSB2_TUNE_USB2_PREEM, 0x5),
	68	};
	69
	70	static const struct eusb2_repeater_cfg pm8550b_eusb2_cfg = {
	71	.init_tbl = pm8550b_init_tbl,
	72	.init_tbl_num = ARRAY_SIZE(pm8550b_init_tbl),
	73	.vreg_list = pm8550b_vreg_l,
	74	.num_vregs = ARRAY_SIZE(pm8550b_vreg_l),
	75	};
	76
	77	static int eusb2_repeater_init_vregs(struct eusb2_repeater *rptr)
	78	{
	79	int num = rptr->cfg->num_vregs;
	80	struct device *dev = rptr->dev;
	81	int i;
	82
	83	rptr->vregs = devm_kcalloc(dev, num, sizeof(*rptr->vregs), GFP_KERNEL);
	84	if (!rptr->vregs)
	85	return -ENOMEM;
	86
	87	for (i = 0; i < num; i++)
	88	rptr->vregs[i].supply = rptr->cfg->vreg_list[i];
	89
	90	return devm_regulator_bulk_get(dev, num, rptr->vregs);
	91	}
	92
	93	static int eusb2_repeater_init(struct phy *phy)
	94	{
	95	struct eusb2_repeater *rptr = phy_get_drvdata(phy);
	96	const struct eusb2_repeater_init_tbl *init_tbl = rptr->cfg->init_tbl;
	97	int num = rptr->cfg->init_tbl_num;
	98	u32 val;
	99	int ret;
	100	int i;
	101
	102	ret = regulator_bulk_enable(rptr->cfg->num_vregs, rptr->vregs);
	103	if (ret)
	104	return ret;
	105
	106	regmap_update_bits(rptr->regmap, rptr->base + EUSB2_EN_CTL1,
	107	EUSB2_RPTR_EN, EUSB2_RPTR_EN);
	108
	109	for (i = 0; i < num; i++)
	110	regmap_update_bits(rptr->regmap,
	111	rptr->base + init_tbl[i].offset,
	112	init_tbl[i].val, init_tbl[i].val);
	113
	114	ret = regmap_read_poll_timeout(rptr->regmap,
	115	rptr->base + EUSB2_RPTR_STATUS, val,
	116	val & RPTR_OK, 10, 5);
	117	if (ret)
	118	dev_err(rptr->dev, "initialization timed-out\n");
	119
	120	return ret;
	121	}
	122
	123	static int eusb2_repeater_set_mode(struct phy *phy,
	124	enum phy_mode mode, int submode)
	125	{
	126	struct eusb2_repeater *rptr = phy_get_drvdata(phy);
	127
	128	switch (mode) {
	129	case PHY_MODE_USB_HOST:
	130	/*
	131	* CM.Lx is prohibited when repeater is already into Lx state as
	132	* per eUSB 1.2 Spec. Below implement software workaround until
	133	* PHY and controller is fixing seen observation.
	134	*/
	135	regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_EN_5,
	136	F_CLK_19P2M_EN, F_CLK_19P2M_EN);
	137	regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_VAL_5,
	138	V_CLK_19P2M_EN, V_CLK_19P2M_EN);
	139	break;
	140	case PHY_MODE_USB_DEVICE:
	141	/*
	142	* In device mode clear host mode related workaround as there
	143	* is no repeater reset available, and enable/disable of
	144	* repeater doesn't clear previous value due to shared
	145	* regulators (say host <-> device mode switch).
	146	*/
	147	regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_EN_5,
	148	F_CLK_19P2M_EN, 0);
	149	regmap_update_bits(rptr->regmap, rptr->base + EUSB2_FORCE_VAL_5,
	150	V_CLK_19P2M_EN, 0);
	151	break;
	152	default:
	153	return -EINVAL;
	154	}
	155
	156	return 0;
	157	}
	158
	159	static int eusb2_repeater_exit(struct phy *phy)
	160	{
	161	struct eusb2_repeater *rptr = phy_get_drvdata(phy);
	162
	163	return regulator_bulk_disable(rptr->cfg->num_vregs, rptr->vregs);
	164	}
	165
	166	static const struct phy_ops eusb2_repeater_ops = {
	167	.init = eusb2_repeater_init,
	168	.exit = eusb2_repeater_exit,
	169	.set_mode = eusb2_repeater_set_mode,
	170	.owner = THIS_MODULE,
	171	};
	172
	173	static int eusb2_repeater_probe(struct platform_device *pdev)
	174	{
	175	struct eusb2_repeater *rptr;
	176	struct device *dev = &pdev->dev;
	177	struct phy_provider *phy_provider;
	178	struct device_node *np = dev->of_node;
	179	u32 res;
	180	int ret;
	181
	182	rptr = devm_kzalloc(dev, sizeof(*rptr), GFP_KERNEL);
	183	if (!rptr)
	184	return -ENOMEM;
	185
	186	rptr->dev = dev;
	187	dev_set_drvdata(dev, rptr);
	188
	189	rptr->cfg = of_device_get_match_data(dev);
	190	if (!rptr->cfg)
	191	return -EINVAL;
	192
	193	rptr->regmap = dev_get_regmap(dev->parent, NULL);
	194	if (!rptr->regmap)
	195	return -ENODEV;
	196
	197	ret = of_property_read_u32(np, "reg", &res);
	198	if (ret < 0)
	199	return ret;
	200
	201	rptr->base = res;
	202
	203	ret = eusb2_repeater_init_vregs(rptr);
	204	if (ret < 0) {
	205	dev_err(dev, "unable to get supplies\n");
	206	return ret;
	207	}
	208
	209	rptr->phy = devm_phy_create(dev, np, &eusb2_repeater_ops);
	210	if (IS_ERR(rptr->phy)) {
	211	dev_err(dev, "failed to create PHY: %d\n", ret);
	212	return PTR_ERR(rptr->phy);
	213	}
	214
	215	phy_set_drvdata(rptr->phy, rptr);
	216
	217	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	218	if (IS_ERR(phy_provider))
	219	return PTR_ERR(phy_provider);
	220
	221	dev_info(dev, "Registered Qcom-eUSB2 repeater\n");
	222
	223	return 0;
	224	}
	225
	226	static int eusb2_repeater_remove(struct platform_device *pdev)
	227	{
	228	struct eusb2_repeater *rptr = platform_get_drvdata(pdev);
	229
	230	if (!rptr)
	231	return 0;
	232
	233	eusb2_repeater_exit(rptr->phy);
	234
	235	return 0;
	236	}
	237
	238	static const struct of_device_id eusb2_repeater_of_match_table[] = {
	239	{
	240	.compatible = "qcom,pm8550b-eusb2-repeater",
	241	.data = &pm8550b_eusb2_cfg,
	242	},
	243	{ },
	244	};
	245	MODULE_DEVICE_TABLE(of, eusb2_repeater_of_match_table);
	246
	247	static struct platform_driver eusb2_repeater_driver = {
	248	.probe = eusb2_repeater_probe,
	249	.remove = eusb2_repeater_remove,
	250	.driver = {
	251	.name = "qcom-eusb2-repeater",
	252	.of_match_table = eusb2_repeater_of_match_table,
	253	},
	254	};
	255
	256	module_platform_driver(eusb2_repeater_driver);
	257
	258	MODULE_DESCRIPTION("Qualcomm PMIC eUSB2 Repeater driver");
	259	MODULE_LICENSE("GPL");

drivers/phy/qualcomm/phy-qcom-pcie2.c+5−1

 	fixed->fixed_rate = 250000000;
 	fixed->hw.init = &init;
-	return devm_clk_hw_register(qphy->dev, &fixed->hw);
+	ret = devm_clk_hw_register(qphy->dev, &fixed->hw);
+	if (ret < 0)
+		return ret;
+	return devm_of_clk_add_hw_provider(qphy->dev, of_clk_hw_simple_get, &fixed->hw);
 }
 static int qcom_pcie2_phy_probe(struct platform_device *pdev)

drivers/phy/qualcomm/phy-qcom-qmp-combo.c+724−26

@@ -23,6 +23,10 @@ · 22 unmodified lines
23	#include <dt-bindings/phy/phy-qcom-qmp.h>	23	#include <dt-bindings/phy/phy-qcom-qmp.h>
24		24
25	#include "phy-qcom-qmp.h"	25	#include "phy-qcom-qmp.h"
		26	#include "phy-qcom-qmp-pcs-misc-v3.h"
		27	#include "phy-qcom-qmp-pcs-usb-v4.h"
		28	#include "phy-qcom-qmp-pcs-usb-v5.h"
		29	#include "phy-qcom-qmp-pcs-usb-v6.h"
26		30
27	/* QPHY_SW_RESET bit */	31	/* QPHY_SW_RESET bit */
28	#define SW_RESET BIT(0)	32	#define SW_RESET BIT(0)
@@ -56,9 +60,6 @@ · 27 unmodified lines
56	/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */	60	/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
57	#define IRQ_CLEAR BIT(0)	61	#define IRQ_CLEAR BIT(0)
58		62
59	/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
60	#define RCVR_DETECT BIT(0)
61
62	/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */	63	/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
63	#define CLAMP_EN BIT(0) /* enables i/o clamp_n */	64	#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
64		65
@@ -96,31 +97,29 @@ enum qphy_reg_layout { · 31 unmodified lines
96	QPHY_PCS_STATUS,	97	QPHY_PCS_STATUS,
97	QPHY_PCS_AUTONOMOUS_MODE_CTRL,	98	QPHY_PCS_AUTONOMOUS_MODE_CTRL,
98	QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,	99	QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
99	QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
100	QPHY_PCS_POWER_DOWN_CONTROL,	100	QPHY_PCS_POWER_DOWN_CONTROL,
101	/* Keep last to ensure regs_layout arrays are properly initialized */	101	/* Keep last to ensure regs_layout arrays are properly initialized */
102	QPHY_LAYOUT_SIZE	102	QPHY_LAYOUT_SIZE
103	};	103	};
104		104
105	static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {	105	static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
106	[QPHY_SW_RESET] = 0x00,	106	[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
107	[QPHY_START_CTRL] = 0x08,	107	[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
108	[QPHY_PCS_STATUS] = 0x174,	108	[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
109	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,	109	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
110	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,	110	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
111	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,	111	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
112	[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
113	};	112	};
114		113
115	static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {	114	static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
116	[QPHY_SW_RESET] = 0x00,	115	[QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
117	[QPHY_START_CTRL] = 0x44,	116	[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
118	[QPHY_PCS_STATUS] = 0x14,	117	[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
119	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,	118	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
120		119
121	/* In PCS_USB */	120	/* In PCS_USB */
122	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,	121	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
123	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,	122	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
124	};	123	};
125		124
126	static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {	125	static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
@@ -311,6 +310,70 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { · 184 unmodified lines
311	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),	310	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
312	};	311	};
313		312
		313	static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
		314	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
		315	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
		316	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
		317	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
		318	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
		319	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
		320	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
		321	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
		322	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
		323	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
		324	};
		325
		326	static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
		327	/* FLL settings */
		328	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
		329	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
		330	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
		331	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
		332	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
		333
		334	/* Lock Det settings */
		335	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
		336	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
		337	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
		338	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
		339
		340	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
		341	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
		342	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
		343	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
		344	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
		345	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
		346	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
		347	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
		348	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
		349	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
		350	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
		351	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
		352	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
		353	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
		354	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
		355	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
		356	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
		357	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
		358	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
		359
		360	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
		361	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
		362	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
		363	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
		364	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
		365	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
		366	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
		367	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
		368	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
		369	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
		370	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
		371	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
		372
		373	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
		374	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
		375	};
		376
314	static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {	377	static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
315	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),	378	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
316	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),	379	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
@@ -494,6 +557,223 @@ static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { · 177 unmodified lines
494	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),	557	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
495	};	558	};
496		559
		560	static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
		561	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
		562	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
		563	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
		564	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
		565	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
		566	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
		567	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
		568	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
		569	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
		570	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
		571	};
		572
		573	static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
		574	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
		575	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
		576	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
		577	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
		578	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
		579	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
		580	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
		581	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
		582	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
		583	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
		584	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
		585	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
		586	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
		587	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
		588	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
		589	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
		590	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
		591	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
		592	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
		593	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
		594	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
		595	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
		596	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
		597	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
		598	QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
		599	QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
		600	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
		601	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
		602	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
		603	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
		604	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
		605	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
		606	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
		607	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
		608	QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
		609	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
		610	QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
		611	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
		612	};
		613
		614	static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
		615	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
		616	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
		617	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
		618	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
		619	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
		620	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
		621	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
		622	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
		623	QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
		624	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
		625	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
		626	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
		627	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
		628	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
		629	};
		630
		631	static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
		632	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
		633	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
		634	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
		635	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
		636	};
		637
		638	static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = {
		639	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
		640	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
		641	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
		642	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
		643	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
		644	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
		645	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
		646	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
		647	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41),
		648	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
		649	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
		650	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75),
		651	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
		652	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
		653	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
		654	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
		655	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
		656	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
		657	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
		658	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
		659	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
		660	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
		661	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
		662	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
		663	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
		664	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
		665	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
		666	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
		667	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
		668	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
		669	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75),
		670	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
		671	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
		672	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
		673	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
		674	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
		675	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
		676	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
		677	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
		678	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
		679	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
		680	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
		681	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
		682	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
		683	QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
		684	QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
		685	QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
		686	QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
		687	};
		688
		689	static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = {
		690	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
		691	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
		692	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
		693	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
		694	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
		695	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
		696	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
		697	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
		698	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
		699	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
		700	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
		701	};
		702
		703	static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = {
		704	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
		705	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
		706	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
		707	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
		708	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
		709	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
		710	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
		711	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
		712	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
		713	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
		714	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
		715	QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
		716	QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
		717	QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
		718	QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
		719	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
		720	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
		721	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
		722	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
		723	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
		724	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
		725	QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
		726	QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
		727	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
		728	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
		729	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
		730	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
		731	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
		732	QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
		733	QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
		734	QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
		735	QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
		736	QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
		737	QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
		738
		739	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1),
		740	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1),
		741	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1),
		742	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1),
		743	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1),
		744
		745	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2),
		746	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2),
		747	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2),
		748	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2),
		749	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2),
		750	};
		751
		752	static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
		753	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
		754	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
		755	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
		756	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
		757	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
		758	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RX_SIGDET_LVL, 0x99),
		759	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
		760	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
		761	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_CDR_RESET_TIME, 0x0a),
		762	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
		763	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
		764	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
		765	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b),
		766	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10),
		767	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
		768	};
		769
		770	static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
		771	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
		772	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
		773	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
		774	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
		775	};
		776
497	static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {	777	static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
498	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),	778	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
499	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),	779	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
@@ -600,6 +880,20 @@ static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { · 100 unmodified lines
600	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),	880	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
601	};	881	};
602		882
		883	static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = {
		884	QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40),
		885	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
		886	QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b),
		887	QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f),
		888	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03),
		889	QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f),
		890	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
		891	QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00),
		892	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
		893	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
		894	QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04),
		895	};
		896
603	static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {	897	static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {
604	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),	898	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),
605	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),	899	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),
@@ -615,6 +909,91 @@ static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { · 9 unmodified lines
615	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),	909	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),
616	};	910	};
617		911
		912	static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = {
		913	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
		914	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
		915	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
		916	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
		917	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
		918	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
		919	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
		920	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
		921	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
		922	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
		923	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
		924	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
		925	QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
		926	QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
		927	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
		928	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
		929	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
		930	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
		931	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
		932	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
		933	};
		934
		935	static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
		936	QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),
		937	QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
		938	QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b),
		939	QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f),
		940	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03),
		941	QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f),
		942	QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
		943	QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00),
		944	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c),
		945	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
		946	QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),
		947	};
		948
		949	static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {
		950	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
		951	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
		952	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
		953	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
		954	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
		955	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
		956	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
		957	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
		958	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
		959	};
		960
		961	static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = {
		962	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
		963	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
		964	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
		965	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
		966	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
		967	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
		968	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
		969	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
		970	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
		971	};
		972
		973	static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = {
		974	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
		975	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
		976	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00),
		977	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
		978	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
		979	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
		980	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
		981	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
		982	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
		983	};
		984
		985	static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = {
		986	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
		987	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
		988	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
		989	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
		990	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
		991	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
		992	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
		993	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
		994	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
		995	};
		996
618	static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {	997	static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
619	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),	998	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
620	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),	999	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
@@ -768,6 +1147,27 @@ static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { · 147 unmodified lines
768	{ 0x1f, 0xff, 0xff, 0xff }	1147	{ 0x1f, 0xff, 0xff, 0xff }
769	};	1148	};
770		1149
		1150	static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = {
		1151	{ 0x00, 0x0c, 0x15, 0x1b },
		1152	{ 0x02, 0x0e, 0x16, 0xff },
		1153	{ 0x02, 0x11, 0xff, 0xff },
		1154	{ 0x04, 0xff, 0xff, 0xff }
		1155	};
		1156
		1157	static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = {
		1158	{ 0x00, 0x0d, 0x14, 0x1a },
		1159	{ 0x00, 0x0e, 0x15, 0xff },
		1160	{ 0x00, 0x0d, 0xff, 0xff },
		1161	{ 0x03, 0xff, 0xff, 0xff }
		1162	};
		1163
		1164	static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = {
		1165	{ 0x08, 0x0f, 0x16, 0x1f },
		1166	{ 0x11, 0x1e, 0x1f, 0xff },
		1167	{ 0x16, 0x1f, 0xff, 0xff },
		1168	{ 0x1f, 0xff, 0xff, 0xff }
		1169	};
		1170
771	static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {	1171	static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {
772	{ 0x20, 0x2c, 0x35, 0x3b },	1172	{ 0x20, 0x2c, 0x35, 0x3b },
773	{ 0x22, 0x2e, 0x36, 0xff },	1173	{ 0x22, 0x2e, 0x36, 0xff },
@@ -796,6 +1196,13 @@ static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { · 22 unmodified lines
796	{ 0x3f, 0xff, 0xff, 0xff }	1196	{ 0x3f, 0xff, 0xff, 0xff }
797	};	1197	};
798		1198
		1199	static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = {
		1200	{ 0x20, 0x2d, 0x34, 0x3a },
		1201	{ 0x20, 0x2e, 0x35, 0xff },
		1202	{ 0x20, 0x2e, 0xff, 0xff },
		1203	{ 0x22, 0xff, 0xff, 0xff }
		1204	};
		1205
799	struct qmp_combo;	1206	struct qmp_combo;
800		1207
801	struct qmp_combo_offsets {	1208	struct qmp_combo_offsets {
@@ -809,6 +1216,8 @@ struct qmp_combo_offsets { · 7 unmodified lines
809	u16 usb3_pcs;	1216	u16 usb3_pcs;
810	u16 usb3_pcs_usb;	1217	u16 usb3_pcs_usb;
811	u16 dp_serdes;	1218	u16 dp_serdes;
		1219	u16 dp_txa;
		1220	u16 dp_txb;
812	u16 dp_dp_phy;	1221	u16 dp_dp_phy;
813	};	1222	};
814		1223
@@ -928,6 +1337,9 @@ static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); · 113 unmodified lines
928		1337
929	static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp);	1338	static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp);
930		1339
		1340	static void qmp_v6_dp_aux_init(struct qmp_combo *qmp);
		1341	static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp);
		1342
931	static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)	1343	static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
932	{	1344	{
933	u32 reg;	1345	u32 reg;
@@ -975,6 +1387,21 @@ static const char * const sc7180_usb3phy_reset_l[] = { · 41 unmodified lines
975	"phy",	1387	"phy",
976	};	1388	};
977		1389
		1390	static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
		1391	.com = 0x0000,
		1392	.txa = 0x1200,
		1393	.rxa = 0x1400,
		1394	.txb = 0x1600,
		1395	.rxb = 0x1800,
		1396	.usb3_serdes = 0x1000,
		1397	.usb3_pcs_misc = 0x1a00,
		1398	.usb3_pcs = 0x1c00,
		1399	.dp_serdes = 0x2000,
		1400	.dp_txa = 0x2200,
		1401	.dp_txb = 0x2600,
		1402	.dp_dp_phy = 0x2a00,
		1403	};
		1404
978	static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {	1405	static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
979	.com = 0x0000,	1406	.com = 0x0000,
980	.txa = 0x0400,	1407	.txa = 0x0400,
@@ -989,6 +1416,22 @@ static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { · 8 unmodified lines
989	.dp_dp_phy = 0x2200,	1416	.dp_dp_phy = 0x2200,
990	};	1417	};
991		1418
		1419	static const struct qmp_combo_offsets qmp_combo_offsets_v6 = {
		1420	.com = 0x0000,
		1421	.txa = 0x1200,
		1422	.rxa = 0x1400,
		1423	.txb = 0x1600,
		1424	.rxb = 0x1800,
		1425	.usb3_serdes = 0x1000,
		1426	.usb3_pcs_misc = 0x1a00,
		1427	.usb3_pcs = 0x1c00,
		1428	.usb3_pcs_usb = 0x1f00,
		1429	.dp_serdes = 0x2000,
		1430	.dp_txa = 0x2200,
		1431	.dp_txb = 0x2600,
		1432	.dp_dp_phy = 0x2a00,
		1433	};
		1434
992	static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {	1435	static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
993	.serdes_tbl = qmp_v3_usb3_serdes_tbl,	1436	.serdes_tbl = qmp_v3_usb3_serdes_tbl,
994	.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),	1437	.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
@@ -1172,6 +1615,51 @@ static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { · 177 unmodified lines
1172	.regs = qmp_v4_usb3phy_regs_layout,	1615	.regs = qmp_v4_usb3phy_regs_layout,
1173	};	1616	};
1174		1617
		1618	static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
		1619	.offsets = &qmp_combo_offsets_v3,
		1620
		1621	.serdes_tbl = qmp_v3_usb3_serdes_tbl,
		1622	.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
		1623	.tx_tbl = qmp_v3_usb3_tx_tbl,
		1624	.tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
		1625	.rx_tbl = sm6350_usb3_rx_tbl,
		1626	.rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl),
		1627	.pcs_tbl = sm6350_usb3_pcs_tbl,
		1628	.pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl),
		1629
		1630	.dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
		1631	.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
		1632	.dp_tx_tbl = qmp_v3_dp_tx_tbl,
		1633	.dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
		1634
		1635	.serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
		1636	.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
		1637	.serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
		1638	.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
		1639	.serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
		1640	.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
		1641	.serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
		1642	.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
		1643
		1644	.swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
		1645	.pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
		1646	.swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
		1647	.pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
		1648
		1649	.dp_aux_init = qmp_v3_dp_aux_init,
		1650	.configure_dp_tx = qmp_v3_configure_dp_tx,
		1651	.configure_dp_phy = qmp_v3_configure_dp_phy,
		1652	.calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
		1653
		1654	.clk_list = qmp_v4_phy_clk_l,
		1655	.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
		1656	.reset_list = msm8996_usb3phy_reset_l,
		1657	.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
		1658	.vreg_list = qmp_phy_vreg_l,
		1659	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
		1660	.regs = qmp_v3_usb3phy_regs_layout,
		1661	};
		1662
1175	static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {	1663	static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
1176	.serdes_tbl = sm8150_usb3_serdes_tbl,	1664	.serdes_tbl = sm8150_usb3_serdes_tbl,
1177	.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),	1665	.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
@@ -1220,6 +1708,102 @@ static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { · 42 unmodified lines
1220	.has_pwrdn_delay = true,	1708	.has_pwrdn_delay = true,
1221	};	1709	};
1222		1710
		1711	static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
		1712	.offsets = &qmp_combo_offsets_v3,
		1713
		1714	.serdes_tbl = sm8150_usb3_serdes_tbl,
		1715	.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
		1716	.tx_tbl = sm8350_usb3_tx_tbl,
		1717	.tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
		1718	.rx_tbl = sm8350_usb3_rx_tbl,
		1719	.rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
		1720	.pcs_tbl = sm8350_usb3_pcs_tbl,
		1721	.pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
		1722	.pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl,
		1723	.pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
		1724
		1725	.dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
		1726	.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
		1727	.dp_tx_tbl = qmp_v5_dp_tx_tbl,
		1728	.dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl),
		1729
		1730	.serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
		1731	.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
		1732	.serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
		1733	.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
		1734	.serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
		1735	.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
		1736	.serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
		1737	.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
		1738
		1739	.swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr,
		1740	.pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr,
		1741	.swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
		1742	.pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2,
		1743
		1744	.dp_aux_init = qmp_v4_dp_aux_init,
		1745	.configure_dp_tx = qmp_v4_configure_dp_tx,
		1746	.configure_dp_phy = qmp_v4_configure_dp_phy,
		1747	.calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
		1748
		1749	.clk_list = qmp_v4_phy_clk_l,
		1750	.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
		1751	.reset_list = msm8996_usb3phy_reset_l,
		1752	.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
		1753	.vreg_list = qmp_phy_vreg_l,
		1754	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
		1755	.regs = qmp_v4_usb3phy_regs_layout,
		1756
		1757	.has_pwrdn_delay = true,
		1758	};
		1759
		1760	static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
		1761	.offsets = &qmp_combo_offsets_v6,
		1762
		1763	.serdes_tbl = sm8550_usb3_serdes_tbl,
		1764	.serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
		1765	.tx_tbl = sm8550_usb3_tx_tbl,
		1766	.tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl),
		1767	.rx_tbl = sm8550_usb3_rx_tbl,
		1768	.rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl),
		1769	.pcs_tbl = sm8550_usb3_pcs_tbl,
		1770	.pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
		1771	.pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl,
		1772	.pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
		1773
		1774	.dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
		1775	.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
		1776	.dp_tx_tbl = qmp_v6_dp_tx_tbl,
		1777	.dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
		1778
		1779	.serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
		1780	.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
		1781	.serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
		1782	.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
		1783	.serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
		1784	.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
		1785	.serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
		1786	.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
		1787
		1788	.swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
		1789	.pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
		1790	.swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
		1791	.pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
		1792
		1793	.dp_aux_init = qmp_v6_dp_aux_init,
		1794	.configure_dp_tx = qmp_v4_configure_dp_tx,
		1795	.configure_dp_phy = qmp_v6_configure_dp_phy,
		1796	.calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
		1797
		1798	.regs = qmp_v4_usb3phy_regs_layout,
		1799	.clk_list = qmp_v4_phy_clk_l,
		1800	.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
		1801	.reset_list = msm8996_usb3phy_reset_l,
		1802	.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
		1803	.vreg_list = qmp_phy_vreg_l,
		1804	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
		1805	};
		1806
1223	static void qmp_combo_configure_lane(void __iomem *base,	1807	static void qmp_combo_configure_lane(void __iomem *base,
1224	const struct qmp_phy_init_tbl tbl[],	1808	const struct qmp_phy_init_tbl tbl[],
1225	int num,	1809	int num,
@@ -1530,6 +2114,33 @@ static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) · 304 unmodified lines
1530	qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);	2114	qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
1531	}	2115	}
1532		2116
		2117	static void qmp_v6_dp_aux_init(struct qmp_combo *qmp)
		2118	{
		2119	writel(DP_PHY_PD_CTL_PWRDN \| DP_PHY_PD_CTL_PSR_PWRDN \| DP_PHY_PD_CTL_AUX_PWRDN \|
		2120	DP_PHY_PD_CTL_PLL_PWRDN \| DP_PHY_PD_CTL_DP_CLAMP_EN,
		2121	qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
		2122
		2123	/* Turn on BIAS current for PHY/PLL */
		2124	writel(0x17, qmp->dp_serdes + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
		2125
		2126	writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
		2127	writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
		2128	writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
		2129	writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
		2130	writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
		2131	writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
		2132	writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
		2133	writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
		2134	writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
		2135	writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
		2136	qmp->dp_aux_cfg = 0;
		2137
		2138	writel(PHY_AUX_STOP_ERR_MASK \| PHY_AUX_DEC_ERR_MASK \|
		2139	PHY_AUX_SYNC_ERR_MASK \| PHY_AUX_ALIGN_ERR_MASK \|
		2140	PHY_AUX_REQ_ERR_MASK,
		2141	qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
		2142	}
		2143
1533	static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)	2144	static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
1534	{	2145	{
1535	/* Program default values before writing proper values */	2146	/* Program default values before writing proper values */
@@ -1543,7 +2154,10 @@ static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) · 7 unmodified lines
1543	QSERDES_V4_TX_TX_EMP_POST1_LVL);	2154	QSERDES_V4_TX_TX_EMP_POST1_LVL);
1544	}	2155	}
1545		2156
1546	static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp)	2157	static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp,
		2158	unsigned int com_resetm_ctrl_reg,
		2159	unsigned int com_c_ready_status_reg,
		2160	unsigned int dp_phy_status_reg)
1547	{	2161	{
1548	const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;	2162	const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1549	u32 phy_vco_div, status;	2163	u32 phy_vco_div, status;
@@ -1590,9 +2204,9 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) · 40 unmodified lines
1590	writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);	2204	writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1591	writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);	2205	writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1592		2206
1593	writel(0x20, qmp->dp_serdes + QSERDES_V4_COM_RESETSM_CNTRL);	2207	writel(0x20, qmp->dp_serdes + com_resetm_ctrl_reg);
1594		2208
1595	if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_C_READY_STATUS,	2209	if (readl_poll_timeout(qmp->dp_serdes + com_c_ready_status_reg,
1596	status,	2210	status,
1597	((status & BIT(0)) > 0),	2211	((status & BIT(0)) > 0),
1598	500,	2212	500,
@@ -1615,14 +2229,14 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) · 16 unmodified lines
1615		2229
1616	writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);	2230	writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1617		2231
1618	if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,	2232	if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg,
1619	status,	2233	status,
1620	((status & BIT(0)) > 0),	2234	((status & BIT(0)) > 0),
1621	500,	2235	500,
1622	10000))	2236	10000))
1623	return -ETIMEDOUT;	2237	return -ETIMEDOUT;
1624		2238
1625	if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,	2239	if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg,
1626	status,	2240	status,
1627	((status & BIT(1)) > 0),	2241	((status & BIT(1)) > 0),
1628	500,	2242	500,
@@ -1640,7 +2254,9 @@ static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) · 11 unmodified lines
1640	u32 status;	2254	u32 status;
1641	int ret;	2255	int ret;
1642		2256
1643	ret = qmp_v45_configure_dp_phy(qmp);	2257	ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL,
		2258	QSERDES_V4_COM_C_READY_STATUS,
		2259	QSERDES_V4_DP_PHY_STATUS);
1644	if (ret < 0)	2260	if (ret < 0)
1645	return ret;	2261	return ret;
1646		2262
@@ -1702,7 +2318,9 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) · 55 unmodified lines
1702	u32 status;	2318	u32 status;
1703	int ret;	2319	int ret;
1704		2320
1705	ret = qmp_v45_configure_dp_phy(qmp);	2321	ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL,
		2322	QSERDES_V4_COM_C_READY_STATUS,
		2323	QSERDES_V4_DP_PHY_STATUS);
1706	if (ret < 0)	2324	if (ret < 0)
1707	return ret;	2325	return ret;
1708		2326
@@ -1751,6 +2369,65 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) · 42 unmodified lines
1751	return 0;	2369	return 0;
1752	}	2370	}
1753		2371
		2372	static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp)
		2373	{
		2374	const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
		2375	u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
		2376	bool reverse = false;
		2377	u32 status;
		2378	int ret;
		2379
		2380	ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V6_COM_RESETSM_CNTRL,
		2381	QSERDES_V6_COM_C_READY_STATUS,
		2382	QSERDES_V6_DP_PHY_STATUS);
		2383	if (ret < 0)
		2384	return ret;
		2385
		2386	if (dp_opts->lanes == 1) {
		2387	bias0_en = reverse ? 0x3e : 0x1a;
		2388	drvr0_en = reverse ? 0x13 : 0x10;
		2389	bias1_en = reverse ? 0x15 : 0x3e;
		2390	drvr1_en = reverse ? 0x10 : 0x13;
		2391	} else if (dp_opts->lanes == 2) {
		2392	bias0_en = reverse ? 0x3f : 0x15;
		2393	drvr0_en = 0x10;
		2394	bias1_en = reverse ? 0x15 : 0x3f;
		2395	drvr1_en = 0x10;
		2396	} else {
		2397	bias0_en = 0x3f;
		2398	bias1_en = 0x3f;
		2399	drvr0_en = 0x10;
		2400	drvr1_en = 0x10;
		2401	}
		2402
		2403	writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
		2404	writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
		2405	writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
		2406	writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
		2407
		2408	writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
		2409	udelay(2000);
		2410	writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
		2411
		2412	if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V6_DP_PHY_STATUS,
		2413	status,
		2414	((status & BIT(1)) > 0),
		2415	500,
		2416	10000))
		2417	return -ETIMEDOUT;
		2418
		2419	writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);
		2420	writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);
		2421
		2422	writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
		2423	writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
		2424
		2425	writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
		2426	writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
		2427
		2428	return 0;
		2429	}
		2430
1754	/*	2431	/*
1755	* We need to calibrate the aux setting here as many times	2432	* We need to calibrate the aux setting here as many times
1756	* as the caller tries	2433	* as the caller tries
@@ -2641,8 +3318,13 @@ static int qmp_combo_parse_dt(struct qmp_combo *qmp) · 884 unmodified lines
2641	qmp->pcs_usb = base + offs->usb3_pcs_usb;	3318	qmp->pcs_usb = base + offs->usb3_pcs_usb;
2642		3319
2643	qmp->dp_serdes = base + offs->dp_serdes;	3320	qmp->dp_serdes = base + offs->dp_serdes;
2644	qmp->dp_tx = base + offs->txa;	3321	if (offs->dp_txa) {
2645	qmp->dp_tx2 = base + offs->txb;	3322	qmp->dp_tx = base + offs->dp_txa;
		3323	qmp->dp_tx2 = base + offs->dp_txb;
		3324	} else {
		3325	qmp->dp_tx = base + offs->txa;
		3326	qmp->dp_tx2 = base + offs->txb;
		3327	}
2646	qmp->dp_dp_phy = base + offs->dp_dp_phy;	3328	qmp->dp_dp_phy = base + offs->dp_dp_phy;
2647		3329
2648	qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe");	3330	qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe");
@@ -2789,10 +3471,26 @@ static const struct of_device_id qmp_combo_of_match_table[] = { · 140 unmodified lines
2789	.compatible = "qcom,sdm845-qmp-usb3-dp-phy",	3471	.compatible = "qcom,sdm845-qmp-usb3-dp-phy",
2790	.data = &sdm845_usb3dpphy_cfg,	3472	.data = &sdm845_usb3dpphy_cfg,
2791	},	3473	},
		3474	{
		3475	.compatible = "qcom,sm6350-qmp-usb3-dp-phy",
		3476	.data = &sm6350_usb3dpphy_cfg,
		3477	},
2792	{	3478	{
2793	.compatible = "qcom,sm8250-qmp-usb3-dp-phy",	3479	.compatible = "qcom,sm8250-qmp-usb3-dp-phy",
2794	.data = &sm8250_usb3dpphy_cfg,	3480	.data = &sm8250_usb3dpphy_cfg,
2795	},	3481	},
		3482	{
		3483	.compatible = "qcom,sm8350-qmp-usb3-dp-phy",
		3484	.data = &sm8350_usb3dpphy_cfg,
		3485	},
		3486	{
		3487	.compatible = "qcom,sm8450-qmp-usb3-dp-phy",
		3488	.data = &sm8350_usb3dpphy_cfg,
		3489	},
		3490	{
		3491	.compatible = "qcom,sm8550-qmp-usb3-dp-phy",
		3492	.data = &sm8550_usb3dpphy_cfg,
		3493	},
2796	{ }	3494	{ }
2797	};	3495	};
2798	MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table);	3496	MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table);

drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c+3−3

@@ -84,9 +84,9 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { · 83 unmodified lines
84	[QPHY_COM_POWER_DOWN_CONTROL] = 0x404,	84	[QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
85	[QPHY_COM_START_CONTROL] = 0x408,	85	[QPHY_COM_START_CONTROL] = 0x408,
86	[QPHY_COM_PCS_READY_STATUS] = 0x448,	86	[QPHY_COM_PCS_READY_STATUS] = 0x448,
87	[QPHY_SW_RESET] = 0x00,	87	[QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
88	[QPHY_START_CTRL] = 0x08,	88	[QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
89	[QPHY_PCS_STATUS] = 0x174,	89	[QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
90	};	90	};
91		91
92	static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {	92	static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c+535−53

@@ -24,6 +24,14 @@ · 23 unmodified lines
24	#include <linux/slab.h>	24	#include <linux/slab.h>
25		25
26	#include "phy-qcom-qmp.h"	26	#include "phy-qcom-qmp.h"
		27	#include "phy-qcom-qmp-pcs-misc-v3.h"
		28	#include "phy-qcom-qmp-pcs-pcie-v4.h"
		29	#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
		30	#include "phy-qcom-qmp-pcs-pcie-v5.h"
		31	#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
		32	#include "phy-qcom-qmp-pcs-pcie-v6.h"
		33	#include "phy-qcom-qmp-pcs-pcie-v6_20.h"
		34	#include "phy-qcom-qmp-pcie-qhp.h"
27		35
28	/* QPHY_SW_RESET bit */	36	/* QPHY_SW_RESET bit */
29	#define SW_RESET BIT(0)	37	#define SW_RESET BIT(0)
@@ -74,25 +82,18 @@ enum qphy_reg_layout { · 44 unmodified lines
74	QPHY_LAYOUT_SIZE	82	QPHY_LAYOUT_SIZE
75	};	83	};
76		84
77	static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {	85	static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
78	[QPHY_SW_RESET] = 0x00,	86	[QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
79	[QPHY_START_CTRL] = 0x44,	87	[QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
80	[QPHY_PCS_STATUS] = 0x14,	88	[QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
81	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,	89	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
82	};	90	};
83		91
84	static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {	92	static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
85	[QPHY_SW_RESET] = 0x00,	93	[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
86	[QPHY_START_CTRL] = 0x08,	94	[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
87	[QPHY_PCS_STATUS] = 0x174,	95	[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
88	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,	96	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
89	};
90
91	static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
92	[QPHY_SW_RESET] = 0x00,
93	[QPHY_START_CTRL] = 0x08,
94	[QPHY_PCS_STATUS] = 0x174,
95	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
96	};	97	};
97		98
98	static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {	99	static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -102,11 +103,18 @@ static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { · 3 unmodified lines
102	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,	103	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
103	};	104	};
104		105
105	static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {	106	static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
106	[QPHY_SW_RESET] = 0x00,	107	[QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
107	[QPHY_START_CTRL] = 0x44,	108	[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
108	[QPHY_PCS_STATUS] = 0x14,	109	[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
109	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,	110	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
		111	};
		112
		113	static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
		114	[QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
		115	[QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
		116	[QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
		117	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
110	};	118	};
111		119
112	static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {	120	static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
@@ -1216,7 +1224,7 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { · 1103 unmodified lines
1216	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),	1224	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1217	};	1225	};
1218		1226
1219	static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {	1227	static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
1220	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),	1228	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1221	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),	1229	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1222	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),	1230	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
@@ -1250,7 +1258,6 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { · 27 unmodified lines
1250	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),	1258	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1251	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),	1259	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1252	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),	1260	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1253	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
1254	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),	1261	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1255	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),	1262	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1256	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),	1263	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
@@ -1261,6 +1268,10 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { · 4 unmodified lines
1261	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),	1268	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1262	};	1269	};
1263		1270
		1271	static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
		1272	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
		1273	};
		1274
1264	static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {	1275	static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
1265	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),	1276	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1266	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),	1277	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
@@ -1269,11 +1280,9 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { · 2 unmodified lines
1269	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),	1280	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
1270	};	1281	};
1271		1282
1272	static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {	1283	static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = {
1273	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),	1284	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1274	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),	1285	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1275	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1276	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1277	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),	1286	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1278	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),	1287	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1279	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),	1288	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
@@ -1281,20 +1290,25 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { · 1 unmodified line
1281	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),	1290	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1282	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),	1291	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1283	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),	1292	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1284	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
1285	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1286	QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),	1293	QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1287	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),	1294	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1288	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),	1295	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1289	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1290	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),	1296	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1291	QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),	1297	QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
		1298	};
		1299
		1300	static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {
		1301	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
		1302	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
		1303	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
		1304	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
		1305	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1292	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),	1306	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
1293	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),	1307	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
1294	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),	1308	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1295	};	1309	};
1296		1310
1297	static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {	1311	static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = {
1298	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),	1312	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
1299	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),	1313	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1300	QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),	1314	QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
@@ -1307,6 +1321,40 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { · 6 unmodified lines
1307	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),	1321	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1308	};	1322	};
1309		1323
		1324	static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
		1325	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
		1326	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
		1327	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
		1328	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
		1329	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
		1330	};
		1331
		1332	static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
		1333	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
		1334	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
		1335	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
		1336	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
		1337	};
		1338
		1339	static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
		1340	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
		1341	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
		1342	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
		1343	};
		1344
		1345	static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
		1346	QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
		1347	QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
		1348	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
		1349	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
		1350	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
		1351	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
		1352	};
		1353
		1354	static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
		1355	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
		1356	};
		1357
1310	static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {	1358	static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
1311	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),	1359	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1312	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),	1360	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
@@ -1458,6 +1506,234 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = · 145 unmodified lines
1458	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),	1506	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
1459	};	1507	};
1460		1508
		1509	static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = {
		1510	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
		1511	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
		1512	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
		1513	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
		1514	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
		1515	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93),
		1516	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
		1517	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
		1518	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
		1519	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
		1520	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
		1521	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
		1522	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
		1523	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
		1524	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
		1525	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
		1526	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
		1527	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
		1528	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
		1529	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
		1530	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
		1531	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
		1532	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
		1533	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
		1534	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34),
		1535	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
		1536	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
		1537	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
		1538	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
		1539	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
		1540	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
		1541	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
		1542	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
		1543	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
		1544	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
		1545	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
		1546	QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
		1547	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
		1548	};
		1549
		1550	static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = {
		1551	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15),
		1552	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
		1553	QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02),
		1554	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
		1555	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18),
		1556	};
		1557
		1558	static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {
		1559	QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
		1560	QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11),
		1561	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
		1562	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf),
		1563	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7),
		1564	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea),
		1565	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
		1566	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
		1567	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
		1568	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a),
		1569	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89),
		1570	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
		1571	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94),
		1572	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
		1573	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
		1574	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
		1575	QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0),
		1576	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
		1577	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
		1578	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
		1579	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
		1580	QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
		1581	QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c),
		1582	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
		1583	QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
		1584	};
		1585
		1586	static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {
		1587	QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05),
		1588	QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77),
		1589	QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b),
		1590	QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f),
		1591	QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c),
		1592	};
		1593
		1594	static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
		1595	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
		1596	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
		1597	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
		1598	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
		1599	};
		1600
		1601	static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {
		1602	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
		1603	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
		1604	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
		1605	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
		1606	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
		1607	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
		1608	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
		1609	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
		1610	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
		1611	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
		1612	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
		1613	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
		1614	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
		1615	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
		1616	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
		1617	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
		1618	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
		1619	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
		1620	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
		1621	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
		1622	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
		1623	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
		1624	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
		1625	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
		1626	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
		1627	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
		1628	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
		1629	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
		1630	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
		1631	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
		1632	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
		1633	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
		1634	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
		1635	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
		1636	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
		1637	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
		1638	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
		1639	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
		1640	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
		1641	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
		1642	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
		1643	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
		1644	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
		1645	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
		1646	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
		1647	};
		1648
		1649	static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
		1650	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
		1651	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe),
		1652	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
		1653	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
		1654	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
		1655	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
		1656	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
		1657	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
		1658	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
		1659	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
		1660	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
		1661	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
		1662	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
		1663	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
		1664	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
		1665	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
		1666	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
		1667	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
		1668	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
		1669	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
		1670	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
		1671	};
		1672
		1673	static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
		1674	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
		1675	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
		1676	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
		1677	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00),
		1678	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
		1679	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
		1680	};
		1681
		1682	static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
		1683	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
		1684	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
		1685	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
		1686	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
		1687	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
		1688	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
		1689	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
		1690	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
		1691	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
		1692	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
		1693	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
		1694	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
		1695	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
		1696	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
		1697	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
		1698	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
		1699	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
		1700	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
		1701	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
		1702	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
		1703	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
		1704	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb),
		1705	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb),
		1706	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0),
		1707	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
		1708	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
		1709	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
		1710	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
		1711	};
		1712
		1713	static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
		1714	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
		1715	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25),
		1716	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
		1717	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
		1718	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
		1719	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
		1720	};
		1721
		1722	static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
		1723	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
		1724	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
		1725	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
		1726	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
		1727	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
		1728	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
		1729	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
		1730	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
		1731	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
		1732	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
		1733	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
		1734	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
		1735	};
		1736
1461	struct qmp_pcie_offsets {	1737	struct qmp_pcie_offsets {
1462	u16 serdes;	1738	u16 serdes;
1463	u16 pcs;	1739	u16 pcs;
@@ -1466,6 +1742,7 @@ struct qmp_pcie_offsets { · 2 unmodified lines
1466	u16 rx;	1742	u16 rx;
1467	u16 tx2;	1743	u16 tx2;
1468	u16 rx2;	1744	u16 rx2;
		1745	u16 ln_shrd;
1469	};	1746	};
1470		1747
1471	struct qmp_phy_cfg_tbls {	1748	struct qmp_phy_cfg_tbls {
@@ -1479,6 +1756,8 @@ struct qmp_phy_cfg_tbls { · 7 unmodified lines
1479	int pcs_num;	1756	int pcs_num;
1480	const struct qmp_phy_init_tbl *pcs_misc;	1757	const struct qmp_phy_init_tbl *pcs_misc;
1481	int pcs_misc_num;	1758	int pcs_misc_num;
		1759	const struct qmp_phy_init_tbl *ln_shrd;
		1760	int ln_shrd_num;
1482	};	1761	};
1483		1762
1484	/* struct qmp_phy_cfg - per-PHY initialization config */	1763	/* struct qmp_phy_cfg - per-PHY initialization config */
@@ -1521,6 +1800,8 @@ struct qmp_phy_cfg { · 36 unmodified lines
1521		1800
1522	bool skip_start_delay;	1801	bool skip_start_delay;
1523		1802
		1803	bool has_nocsr_reset;
		1804
1524	/* QMP PHY pipe clock interface rate */	1805	/* QMP PHY pipe clock interface rate */
1525	unsigned long pipe_clock_rate;	1806	unsigned long pipe_clock_rate;
1526	};	1807	};
@@ -1538,6 +1819,7 @@ struct qmp_pcie { · 11 unmodified lines
1538	void __iomem *rx;	1819	void __iomem *rx;
1539	void __iomem *tx2;	1820	void __iomem *tx2;
1540	void __iomem *rx2;	1821	void __iomem *rx2;
		1822	void __iomem *ln_shrd;
1541		1823
1542	void __iomem *port_b;	1824	void __iomem *port_b;
1543		1825
@@ -1546,6 +1828,7 @@ struct qmp_pcie { · 2 unmodified lines
1546	int num_pipe_clks;	1828	int num_pipe_clks;
1547		1829
1548	struct reset_control_bulk_data *resets;	1830	struct reset_control_bulk_data *resets;
		1831	struct reset_control *nocsr_reset;
1549	struct regulator_bulk_data *vregs;	1832	struct regulator_bulk_data *vregs;
1550		1833
1551	struct phy *phy;	1834	struct phy *phy;
@@ -1600,6 +1883,10 @@ static const char * const qmp_phy_vreg_l[] = { · 48 unmodified lines
1600	"vdda-phy", "vdda-pll",	1883	"vdda-phy", "vdda-pll",
1601	};	1884	};
1602		1885
		1886	static const char * const sm8550_qmp_phy_vreg_l[] = {
		1887	"vdda-phy", "vdda-pll", "vdda-qref",
		1888	};
		1889
1603	/* list of resets */	1890	/* list of resets */
1604	static const char * const ipq8074_pciephy_reset_l[] = {	1891	static const char * const ipq8074_pciephy_reset_l[] = {
1605	"phy", "common",	1892	"phy", "common",
@@ -1619,6 +1906,17 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { · 13 unmodified lines
1619	.rx2 = 0x1800,	1906	.rx2 = 0x1800,
1620	};	1907	};
1621		1908
		1909	static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
		1910	.serdes = 0x1000,
		1911	.pcs = 0x1200,
		1912	.pcs_misc = 0x1400,
		1913	.tx = 0x0000,
		1914	.rx = 0x0200,
		1915	.tx2 = 0x0800,
		1916	.rx2 = 0x0a00,
		1917	.ln_shrd = 0x0e00,
		1918	};
		1919
1622	static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {	1920	static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
1623	.lanes = 1,	1921	.lanes = 1,
1624		1922
@@ -1638,7 +1936,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { · 13 unmodified lines
1638	.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),	1936	.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1639	.vreg_list = NULL,	1937	.vreg_list = NULL,
1640	.num_vregs = 0,	1938	.num_vregs = 0,
1641	.regs = pciephy_regs_layout,	1939	.regs = pciephy_v2_regs_layout,
1642		1940
1643	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	1941	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
1644	.phy_status = PHYSTATUS,	1942	.phy_status = PHYSTATUS,
@@ -1665,7 +1963,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { · 20 unmodified lines
1665	.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),	1963	.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1666	.vreg_list = NULL,	1964	.vreg_list = NULL,
1667	.num_vregs = 0,	1965	.num_vregs = 0,
1668	.regs = ipq_pciephy_gen3_regs_layout,	1966	.regs = pciephy_v4_regs_layout,
1669		1967
1670	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	1968	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
1671	.phy_status = PHYSTATUS,	1969	.phy_status = PHYSTATUS,
@@ -1694,7 +1992,7 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { · 22 unmodified lines
1694	.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),	1992	.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1695	.vreg_list = NULL,	1993	.vreg_list = NULL,
1696	.num_vregs = 0,	1994	.num_vregs = 0,
1697	.regs = ipq_pciephy_gen3_regs_layout,	1995	.regs = pciephy_v4_regs_layout,
1698		1996
1699	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	1997	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
1700	.phy_status = PHYSTATUS,	1998	.phy_status = PHYSTATUS,
@@ -1721,7 +2019,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { · 20 unmodified lines
1721	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),	2019	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1722	.vreg_list = qmp_phy_vreg_l,	2020	.vreg_list = qmp_phy_vreg_l,
1723	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	2021	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1724	.regs = sdm845_qmp_pciephy_regs_layout,	2022	.regs = pciephy_v3_regs_layout,
1725		2023
1726	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	2024	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
1727	.phy_status = PHYSTATUS,	2025	.phy_status = PHYSTATUS,
@@ -1783,7 +2081,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { · 55 unmodified lines
1783	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),	2081	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1784	.vreg_list = qmp_phy_vreg_l,	2082	.vreg_list = qmp_phy_vreg_l,
1785	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	2083	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1786	.regs = sm8250_pcie_regs_layout,	2084	.regs = pciephy_v4_regs_layout,
1787		2085
1788	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	2086	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
1789	.phy_status = PHYSTATUS,	2087	.phy_status = PHYSTATUS,
@@ -1820,7 +2118,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { · 30 unmodified lines
1820	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),	2118	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1821	.vreg_list = qmp_phy_vreg_l,	2119	.vreg_list = qmp_phy_vreg_l,
1822	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	2120	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1823	.regs = sm8250_pcie_regs_layout,	2121	.regs = pciephy_v4_regs_layout,
1824		2122
1825	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	2123	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
1826	.phy_status = PHYSTATUS,	2124	.phy_status = PHYSTATUS,
@@ -1845,7 +2143,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { · 18 unmodified lines
1845	.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),	2143	.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1846	.vreg_list = qmp_phy_vreg_l,	2144	.vreg_list = qmp_phy_vreg_l,
1847	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	2145	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1848	.regs = pciephy_regs_layout,	2146	.regs = pciephy_v3_regs_layout,
1849		2147
1850	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	2148	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
1851	.phy_status = PHYSTATUS,	2149	.phy_status = PHYSTATUS,
@@ -1874,7 +2172,7 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { · 22 unmodified lines
1874	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),	2172	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1875	.vreg_list = qmp_phy_vreg_l,	2173	.vreg_list = qmp_phy_vreg_l,
1876	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	2174	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1877	.regs = sm8250_pcie_regs_layout,	2175	.regs = pciephy_v4_regs_layout,
1878		2176
1879	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	2177	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
1880	.phy_status = PHYSTATUS,	2178	.phy_status = PHYSTATUS,
@@ -1909,7 +2207,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { · 28 unmodified lines
1909	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),	2207	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1910	.vreg_list = qmp_phy_vreg_l,	2208	.vreg_list = qmp_phy_vreg_l,
1911	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	2209	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1912	.regs = sm8250_pcie_regs_layout,	2210	.regs = pciephy_v5_regs_layout,
1913		2211
1914	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	2212	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
1915	.phy_status = PHYSTATUS,	2213	.phy_status = PHYSTATUS,
@@ -1944,7 +2242,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { · 28 unmodified lines
1944	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),	2242	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1945	.vreg_list = qmp_phy_vreg_l,	2243	.vreg_list = qmp_phy_vreg_l,
1946	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	2244	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1947	.regs = sm8250_pcie_regs_layout,	2245	.regs = pciephy_v5_regs_layout,
1948		2246
1949	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	2247	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
1950	.phy_status = PHYSTATUS,	2248	.phy_status = PHYSTATUS,
@@ -1982,7 +2280,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { · 31 unmodified lines
1982	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),	2280	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1983	.vreg_list = qmp_phy_vreg_l,	2281	.vreg_list = qmp_phy_vreg_l,
1984	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	2282	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1985	.regs = sm8250_pcie_regs_layout,	2283	.regs = pciephy_v5_regs_layout,
1986		2284
1987	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	2285	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
1988	.phy_status = PHYSTATUS,	2286	.phy_status = PHYSTATUS,
@@ -2009,34 +2307,116 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { · 20 unmodified lines
2009	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),	2307	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2010	.vreg_list = qmp_phy_vreg_l,	2308	.vreg_list = qmp_phy_vreg_l,
2011	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	2309	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2012	.regs = sm8250_pcie_regs_layout,	2310	.regs = pciephy_v4_regs_layout,
2013		2311
2014	.pwrdn_ctrl = SW_PWRDN,	2312	.pwrdn_ctrl = SW_PWRDN,
2015	.phy_status = PHYSTATUS_4_20,	2313	.phy_status = PHYSTATUS_4_20,
2016	};	2314	};
2017		2315
		2316	static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
		2317	.lanes = 1,
		2318
		2319	.offsets = &qmp_pcie_offsets_v5,
		2320
		2321	.tbls = {
		2322	.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
		2323	.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
		2324	.tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
		2325	.tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
		2326	.rx = sm8450_qmp_gen3_pcie_rx_tbl,
		2327	.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
		2328	.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
		2329	.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
		2330	.pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
		2331	.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
		2332	},
		2333
		2334	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
		2335	.serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
		2336	.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
		2337	.rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
		2338	.rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
		2339	},
		2340
		2341	.clk_list = sc8280xp_pciephy_clk_l,
		2342	.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
		2343	.reset_list = sdm845_pciephy_reset_l,
		2344	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
		2345	.vreg_list = qmp_phy_vreg_l,
		2346	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
		2347	.regs = pciephy_v5_regs_layout,
		2348
		2349	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
		2350	.phy_status = PHYSTATUS,
		2351	};
		2352
		2353	static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
		2354	.lanes = 2,
		2355
		2356	.offsets = &qmp_pcie_offsets_v5,
		2357
		2358	.tbls = {
		2359	.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
		2360	.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
		2361	.tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
		2362	.tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
		2363	.rx = sm8450_qmp_gen3_pcie_rx_tbl,
		2364	.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
		2365	.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
		2366	.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
		2367	.pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
		2368	.pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
		2369	},
		2370
		2371	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
		2372	.rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
		2373	.rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
		2374	.pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
		2375	.pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
		2376	},
		2377
		2378	.clk_list = sc8280xp_pciephy_clk_l,
		2379	.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
		2380	.reset_list = sdm845_pciephy_reset_l,
		2381	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
		2382	.vreg_list = qmp_phy_vreg_l,
		2383	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
		2384	.regs = pciephy_v5_regs_layout,
		2385
		2386	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
		2387	.phy_status = PHYSTATUS,
		2388	};
		2389
2018	static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {	2390	static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
2019	.lanes = 1,	2391	.lanes = 1,
2020		2392
2021	.tbls = {	2393	.tbls = {
2022	.serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl,	2394	.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2023	.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),	2395	.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2024	.tx = sm8450_qmp_gen3x1_pcie_tx_tbl,	2396	.tx = sm8450_qmp_gen3x1_pcie_tx_tbl,
2025	.tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),	2397	.tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
2026	.rx = sm8450_qmp_gen3x1_pcie_rx_tbl,	2398	.rx = sm8450_qmp_gen3_pcie_rx_tbl,
2027	.rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),	2399	.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2028	.pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl,	2400	.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2029	.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),	2401	.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2030	.pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,	2402	.pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
2031	.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),	2403	.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
2032	},	2404	},
		2405
		2406	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
		2407	.serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
		2408	.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
		2409	.rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl,
		2410	.rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),
		2411	},
		2412
2033	.clk_list = sdm845_pciephy_clk_l,	2413	.clk_list = sdm845_pciephy_clk_l,
2034	.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),	2414	.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
2035	.reset_list = sdm845_pciephy_reset_l,	2415	.reset_list = sdm845_pciephy_reset_l,
2036	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),	2416	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2037	.vreg_list = qmp_phy_vreg_l,	2417	.vreg_list = qmp_phy_vreg_l,
2038	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	2418	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2039	.regs = sm8250_pcie_regs_layout,	2419	.regs = pciephy_v5_regs_layout,
2040		2420
2041	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	2421	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
2042	.phy_status = PHYSTATUS,	2422	.phy_status = PHYSTATUS,
@@ -2078,12 +2458,73 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { · 35 unmodified lines
2078	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),	2458	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2079	.vreg_list = qmp_phy_vreg_l,	2459	.vreg_list = qmp_phy_vreg_l,
2080	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	2460	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2081	.regs = sm8250_pcie_regs_layout,	2461	.regs = pciephy_v5_regs_layout,
2082		2462
2083	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,	2463	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
2084	.phy_status = PHYSTATUS_4_20,	2464	.phy_status = PHYSTATUS_4_20,
2085	};	2465	};
2086		2466
		2467	static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
		2468	.lanes = 2,
		2469
		2470	.offsets = &qmp_pcie_offsets_v5,
		2471
		2472	.tbls = {
		2473	.serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl,
		2474	.serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl),
		2475	.tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
		2476	.tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
		2477	.rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
		2478	.rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
		2479	.pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
		2480	.pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
		2481	.pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
		2482	.pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
		2483	},
		2484	.clk_list = sc8280xp_pciephy_clk_l,
		2485	.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
		2486	.reset_list = sdm845_pciephy_reset_l,
		2487	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
		2488	.vreg_list = qmp_phy_vreg_l,
		2489	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
		2490	.regs = pciephy_v5_regs_layout,
		2491
		2492	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
		2493	.phy_status = PHYSTATUS,
		2494	};
		2495
		2496	static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
		2497	.lanes = 2,
		2498
		2499	.offsets = &qmp_pcie_offsets_v6_20,
		2500
		2501	.tbls = {
		2502	.serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl,
		2503	.serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
		2504	.tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
		2505	.tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
		2506	.rx = sm8550_qmp_gen4x2_pcie_rx_tbl,
		2507	.rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl),
		2508	.pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
		2509	.pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
		2510	.pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
		2511	.pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
		2512	.ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
		2513	.ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
		2514	},
		2515	.clk_list = sc8280xp_pciephy_clk_l,
		2516	.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
		2517	.reset_list = sdm845_pciephy_reset_l,
		2518	.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
		2519	.vreg_list = sm8550_qmp_phy_vreg_l,
		2520	.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
		2521	.regs = pciephy_v5_regs_layout,
		2522
		2523	.pwrdn_ctrl = SW_PWRDN \| REFCLK_DRV_DSBL,
		2524	.phy_status = PHYSTATUS_4_20,
		2525	.has_nocsr_reset = true,
		2526	};
		2527
2087	static void qmp_pcie_configure_lane(void __iomem *base,	2528	static void qmp_pcie_configure_lane(void __iomem *base,
2088	const struct qmp_phy_init_tbl tbl[],	2529	const struct qmp_phy_init_tbl tbl[],
2089	int num,	2530	int num,
@@ -2138,6 +2579,7 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c · 48 unmodified lines
2138	void __iomem *rx2 = qmp->rx2;	2579	void __iomem *rx2 = qmp->rx2;
2139	void __iomem *pcs = qmp->pcs;	2580	void __iomem *pcs = qmp->pcs;
2140	void __iomem *pcs_misc = qmp->pcs_misc;	2581	void __iomem *pcs_misc = qmp->pcs_misc;
		2582	void __iomem *ln_shrd = qmp->ln_shrd;
2141		2583
2142	if (!tbls)	2584	if (!tbls)
2143	return;	2585	return;
@@ -2159,6 +2601,8 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c · 15 unmodified lines
2159	qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);	2601	qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
2160	qmp_pcie_init_port_b(qmp, tbls);	2602	qmp_pcie_init_port_b(qmp, tbls);
2161	}	2603	}
		2604
		2605	qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
2162	}	2606	}
2163		2607
2164	static int qmp_pcie_init(struct phy *phy)	2608	static int qmp_pcie_init(struct phy *phy)
@@ -2179,12 +2623,18 @@ static int qmp_pcie_init(struct phy *phy) · 14 unmodified lines
2179	goto err_disable_regulators;	2623	goto err_disable_regulators;
2180	}	2624	}
2181		2625
		2626	ret = reset_control_assert(qmp->nocsr_reset);
		2627	if (ret) {
		2628	dev_err(qmp->dev, "no-csr reset assert failed\n");
		2629	goto err_assert_reset;
		2630	}
		2631
2182	usleep_range(200, 300);	2632	usleep_range(200, 300);
2183		2633
2184	ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);	2634	ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2185	if (ret) {	2635	if (ret) {
2186	dev_err(qmp->dev, "reset deassert failed\n");	2636	dev_err(qmp->dev, "reset deassert failed\n");
2187	goto err_disable_regulators;	2637	goto err_assert_reset;
2188	}	2638	}
2189		2639
2190	ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);	2640	ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
@@ -2240,6 +2690,12 @@ static int qmp_pcie_power_on(struct phy *phy) · 49 unmodified lines
2240	if (ret)	2690	if (ret)
2241	return ret;	2691	return ret;
2242		2692
		2693	ret = reset_control_deassert(qmp->nocsr_reset);
		2694	if (ret) {
		2695	dev_err(qmp->dev, "no-csr reset deassert failed\n");
		2696	goto err_disable_pipe_clk;
		2697	}
		2698
2243	/* Pull PHY out of reset state */	2699	/* Pull PHY out of reset state */
2244	qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);	2700	qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2245		2701
@@ -2373,6 +2829,13 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) · 127 unmodified lines
2373	if (ret)	2829	if (ret)
2374	return dev_err_probe(dev, ret, "failed to get resets\n");	2830	return dev_err_probe(dev, ret, "failed to get resets\n");
2375		2831
		2832	if (cfg->has_nocsr_reset) {
		2833	qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");
		2834	if (IS_ERR(qmp->nocsr_reset))
		2835	return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
		2836	"failed to get no-csr reset\n");
		2837	}
		2838
2376	return 0;	2839	return 0;
2377	}	2840	}
2378		2841
@@ -2595,11 +3058,18 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) · 216 unmodified lines
2595	return PTR_ERR(qmp->port_b);	3058	return PTR_ERR(qmp->port_b);
2596	}	3059	}
2597		3060
		3061	if (cfg->tbls.ln_shrd)
		3062	qmp->ln_shrd = base + offs->ln_shrd;
		3063
2598	qmp->num_pipe_clks = 2;	3064	qmp->num_pipe_clks = 2;
2599	qmp->pipe_clks[0].id = "pipe";	3065	qmp->pipe_clks[0].id = "pipe";
2600	qmp->pipe_clks[1].id = "pipediv2";	3066	qmp->pipe_clks[1].id = "pipediv2";
2601		3067
2602	ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks);	3068	ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
		3069	if (ret)
		3070	return ret;
		3071
		3072	ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
2603	if (ret)	3073	if (ret)
2604	return ret;	3074	return ret;
2605		3075
@@ -2719,12 +3189,24 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { · 113 unmodified lines
2719	}, {	3189	}, {
2720	.compatible = "qcom,sm8250-qmp-modem-pcie-phy",	3190	.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
2721	.data = &sm8250_qmp_gen3x2_pciephy_cfg,	3191	.data = &sm8250_qmp_gen3x2_pciephy_cfg,
		3192	}, {
		3193	.compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
		3194	.data = &sm8350_qmp_gen3x1_pciephy_cfg,
		3195	}, {
		3196	.compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
		3197	.data = &sm8350_qmp_gen3x2_pciephy_cfg,
2722	}, {	3198	}, {
2723	.compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",	3199	.compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
2724	.data = &sm8450_qmp_gen3x1_pciephy_cfg,	3200	.data = &sm8450_qmp_gen3x1_pciephy_cfg,
2725	}, {	3201	}, {
2726	.compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",	3202	.compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
2727	.data = &sm8450_qmp_gen4x2_pciephy_cfg,	3203	.data = &sm8450_qmp_gen4x2_pciephy_cfg,
		3204	}, {
		3205	.compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
		3206	.data = &sm8550_qmp_gen3x2_pciephy_cfg,
		3207	}, {
		3208	.compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
		3209	.data = &sm8550_qmp_gen4x2_pciephy_cfg,
2728	},	3210	},
2729	{ },	3211	{ },
2730	};	3212	};

drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h+15−0

@@ -0,0 +1,15 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_
	7	#define QCOM_PHY_QMP_PCS_PCIE_V6_H_
	8
	9	/* Only for QMP V6 PHY - PCIE have different offsets than V5 */
	10	#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
	11	#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14
	12	#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
	13	#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
	14
	15	#endif

drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h+23−0

@@ -0,0 +1,23 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
	7	#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
	8
	9	/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */
	10	#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
	11	#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
	12	#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
	13	#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
	14	#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
	15	#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
	16	#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
	17	#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
	18	#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184
	19	#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c
	20	#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac
	21	#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0
	22
	23	#endif

drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h+25−0

@@ -0,0 +1,25 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2017, The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_PCS_UFS_V2_H_
	7	#define QCOM_PHY_QMP_PCS_UFS_V2_H_
	8
	9	#define QPHY_V2_PCS_UFS_PHY_START 0x000
	10	#define QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL 0x004
	11
	12	#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034
	13	#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038
	14	#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c
	15	#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL 0x040
	16
	17	#define QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
	18	#define QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL 0x13c
	19	#define QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME 0x140
	20	#define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148
	21	#define QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND 0x154
	22
	23	#define QPHY_V2_PCS_UFS_READY_STATUS 0x168
	24
	25	#endif

drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h+3−0

 #ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_
 #define QCOM_PHY_QMP_PCS_UFS_V3_H_
+#define QPHY_V3_PCS_UFS_PHY_START			0x000
+#define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL		0x004
 #define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL		0x02c
 #define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL		0x034
 #define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL		0x134
 #define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME		0x138
 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1			0x13c
 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2			0x140
+#define QPHY_V3_PCS_UFS_READY_STATUS			0x160
 #define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1		0x1bc
 #define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1		0x1c4

drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h+5−0

 #define QCOM_PHY_QMP_PCS_UFS_V5_H_
 /* Only for QMP V5 PHY - UFS PCS registers */
+#define QPHY_V5_PCS_UFS_PHY_START			0x000
+#define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL		0x004
+#define QPHY_V5_PCS_UFS_SW_RESET			0x008
 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB	0x00c
 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB	0x010
 #define QPHY_V5_PCS_UFS_PLL_CNTL			0x02c
 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL		0x030
 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL		0x038
+#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL		0x060
 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY		0x074
 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY		0x0b4
 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL		0x124
 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2			0x158
 #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND		0x160
 #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND			0x168
+#define QPHY_V5_PCS_UFS_READY_STATUS			0x180
 #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1		0x1d8
 #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1		0x1e0

drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h+31−0

@@ -0,0 +1,31 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_
	7	#define QCOM_PHY_QMP_PCS_UFS_V6_H_
	8
	9	/* Only for QMP V6 PHY - UFS PCS registers */
	10	#define QPHY_V6_PCS_UFS_PHY_START 0x000
	11	#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
	12	#define QPHY_V6_PCS_UFS_SW_RESET 0x008
	13	#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
	14	#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
	15	#define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
	16	#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
	17	#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
	18	#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
	19	#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
	20	#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
	21	#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
	22	#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
	23	#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
	24	#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c
	25	#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x178
	26	#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x174
	27	#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
	28	#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
	29	#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
	30
	31	#endif

drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h+31−0

@@ -0,0 +1,31 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2022, The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_PCS_USB_V6_H_
	7	#define QCOM_PHY_QMP_PCS_USB_V6_H_
	8
	9	/* Only for QMP V6 PHY - USB3 have different offsets than V5 */
	10	#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1 0xc4
	11	#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2 0xc8
	12	#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3 0xcc
	13	#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6 0xd8
	14	#define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
	15	#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1 0x90
	16	#define QPHY_USB_V6_PCS_RX_SIGDET_LVL 0x188
	17	#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
	18	#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
	19	#define QPHY_USB_V6_PCS_CDR_RESET_TIME 0x1b0
	20	#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0
	21	#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4
	22	#define QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
	23	#define QPHY_USB_V6_PCS_EQ_CONFIG1 0x1dc
	24	#define QPHY_USB_V6_PCS_EQ_CONFIG5 0x1ec
	25
	26	#define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
	27	#define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
	28	#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
	29	#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
	30
	31	#endif

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h+8−11

@@ -7,13 +7,11 @@ · 6 unmodified lines
7	#define QCOM_PHY_QMP_PCS_V2_H_	7	#define QCOM_PHY_QMP_PCS_V2_H_
8		8
9	/* Only for QMP V2 PHY - PCS registers */	9	/* Only for QMP V2 PHY - PCS registers */
		10	#define QPHY_V2_PCS_SW_RESET 0x000
10	#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004	11	#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
		12	#define QPHY_V2_PCS_START_CONTROL 0x008
11	#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024	13	#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
12	#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028	14	#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
13	#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034
14	#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038
15	#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c
16	#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040
17	#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054	15	#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
18	#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058	16	#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
19	#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060	17	#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
@@ -30,17 +28,16 @@ · 10 unmodified lines
30	#define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8	28	#define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8
31	#define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc	29	#define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc
32	#define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0	30	#define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0
33		31	#define QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL 0x0d4
34	/* UFS only ? */	32	#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0d8
35	#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc	33	#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS 0x178
36	#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c	34	#define QPHY_V2_PCS_USB_PCS_STATUS 0x17c /* USB */
37	#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
38	#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
39	#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
40	#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8	35	#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
41	#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac	36	#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
42	#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8	37	#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
43	#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc	38	#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
44	#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0	39	#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
45		40
		41	#define QPHY_V2_PCS_PCI_PCS_STATUS 0x174 /* PCI */
		42
46	#endif	43	#endif

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h+4−0

 #define QCOM_PHY_QMP_PCS_V5_H_
 /* Only for QMP V5 PHY - USB/PCIe PCS registers */
+#define QPHY_V5_PCS_SW_RESET				0x000
+#define QPHY_V5_PCS_PCS_STATUS1				0x014
+#define QPHY_V5_PCS_POWER_DOWN_CONTROL			0x040
+#define QPHY_V5_PCS_START_CONTROL			0x044
 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1			0x0c4
 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2			0x0c8
 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3			0x0cc

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h+16−0

@@ -0,0 +1,16 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_PCS_V6_H_
	7	#define QCOM_PHY_QMP_PCS_V6_H_
	8
	9	/* Only for QMP V6 PHY - USB/PCIe PCS registers */
	10	#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
	11	#define QPHY_V6_PCS_RX_SIGDET_LVL 0x188
	12	#define QPHY_V6_PCS_RATE_SLEW_CNTRL1 0x198
	13	#define QPHY_V6_PCS_EQ_CONFIG2 0x1e0
	14	#define QPHY_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
	15
	16	#endif

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h+18−0

@@ -0,0 +1,18 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_PCS_V6_20_H_
	7	#define QCOM_PHY_QMP_PCS_V6_20_H_
	8
	9	/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */
	10	#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
	11	#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
	12	#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
	13	#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc
	14	#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0
	15	#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8
	16	#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
	17
	18	#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h+82−0

@@ -0,0 +1,82 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_QSERDES_COM_V6_H_
	7	#define QCOM_PHY_QMP_QSERDES_COM_V6_H_
	8
	9	/* Only for QMP V6 PHY - QSERDES COM registers */
	10
	11	#define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00
	12	#define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04
	13	#define QSERDES_V6_COM_CP_CTRL_MODE1 0x10
	14	#define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14
	15	#define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18
	16	#define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c
	17	#define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20
	18	#define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24
	19	#define QSERDES_V6_COM_DEC_START_MODE1 0x28
	20	#define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c
	21	#define QSERDES_V6_COM_DIV_FRAC_START1_MODE1 0x30
	22	#define QSERDES_V6_COM_DIV_FRAC_START2_MODE1 0x34
	23	#define QSERDES_V6_COM_DIV_FRAC_START3_MODE1 0x38
	24	#define QSERDES_V6_COM_HSCLK_SEL_1 0x3c
	25	#define QSERDES_V6_COM_VCO_TUNE1_MODE1 0x48
	26	#define QSERDES_V6_COM_VCO_TUNE2_MODE1 0x4c
	27	#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
	28	#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
	29	#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
	30	#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
	31	#define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0 0x60
	32	#define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0 0x64
	33	#define QSERDES_V6_COM_CP_CTRL_MODE0 0x70
	34	#define QSERDES_V6_COM_PLL_RCTRL_MODE0 0x74
	35	#define QSERDES_V6_COM_PLL_CCTRL_MODE0 0x78
	36	#define QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0 0x7c
	37	#define QSERDES_V6_COM_LOCK_CMP1_MODE0 0x80
	38	#define QSERDES_V6_COM_LOCK_CMP2_MODE0 0x84
	39	#define QSERDES_V6_COM_DEC_START_MODE0 0x88
	40	#define QSERDES_V6_COM_DEC_START_MSB_MODE0 0x8c
	41	#define QSERDES_V6_COM_DIV_FRAC_START1_MODE0 0x90
	42	#define QSERDES_V6_COM_DIV_FRAC_START2_MODE0 0x94
	43	#define QSERDES_V6_COM_DIV_FRAC_START3_MODE0 0x98
	44	#define QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1 0x9c
	45	#define QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0 0xa0
	46	#define QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0 0xa4
	47	#define QSERDES_V6_COM_VCO_TUNE1_MODE0 0xa8
	48	#define QSERDES_V6_COM_VCO_TUNE2_MODE0 0xac
	49	#define QSERDES_V6_COM_BG_TIMER 0xbc
	50	#define QSERDES_V6_COM_SSC_EN_CENTER 0xc0
	51	#define QSERDES_V6_COM_SSC_PER1 0xcc
	52	#define QSERDES_V6_COM_SSC_PER2 0xd0
	53	#define QSERDES_V6_COM_PLL_POST_DIV_MUX 0xd8
	54	#define QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN 0xdc
	55	#define QSERDES_V6_COM_CLK_ENABLE1 0xe0
	56	#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
	57	#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
	58	#define QSERDES_V6_COM_PLL_IVCO 0xf4
	59	#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
	60	#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
	61	#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
	62	#define QSERDES_V6_COM_LOCK_CMP_CFG 0x124
	63	#define QSERDES_V6_COM_VCO_TUNE_CTRL 0x13c
	64	#define QSERDES_V6_COM_VCO_TUNE_MAP 0x140
	65	#define QSERDES_V6_COM_VCO_TUNE_INITVAL2 0x148
	66	#define QSERDES_V6_COM_CLK_SELECT 0x164
	67	#define QSERDES_V6_COM_CORE_CLK_EN 0x170
	68	#define QSERDES_V6_COM_CMN_CONFIG_1 0x174
	69	#define QSERDES_V6_COM_SVS_MODE_CLK_SEL 0x17c
	70	#define QSERDES_V6_COM_CMN_MISC_1 0x184
	71	#define QSERDES_V6_COM_CMN_MODE 0x188
	72	#define QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL 0x198
	73	#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4
	74	#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8
	75	#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac
	76	#define QSERDES_V6_COM_ADDITIONAL_MISC 0x1b4
	77	#define QSERDES_V6_COM_ADDITIONAL_MISC_2 0x1b8
	78	#define QSERDES_V6_COM_ADDITIONAL_MISC_3 0x1bc
	79	#define QSERDES_V6_COM_CMN_STATUS 0x1d0
	80	#define QSERDES_V6_COM_C_READY_STATUS 0x1f8
	81
	82	#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h+1−1

@@ -135,6 +135,6 @@ · 134 unmodified lines
135	#define QSERDES_COM_CMN_MISC2 0x1b8	135	#define QSERDES_COM_CMN_MISC2 0x1b8
136	#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc	136	#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
137	#define QSERDES_COM_CORECLK_DIV_MODE2 0x1c0	137	#define QSERDES_COM_CORECLK_DIV_MODE2 0x1c0
138	#define QSERDES_COM_CMN_RSVD5 0x1c0	138	#define QSERDES_COM_CMN_RSVD5 0x1c4
139		139
140	#endif	140	#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h+32−0

@@ -0,0 +1,32 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
	7	#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
	8
	9	#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
	10	#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
	11	#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
	12	#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
	13	#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
	14	#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
	15	#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
	16	#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
	17	#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
	18	#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
	19	#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8
	20	#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec
	21	#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0
	22	#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4
	23	#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8
	24	#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc
	25	#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100
	26	#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104
	27	#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c
	28	#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114
	29	#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c
	30	#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128
	31
	32	#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h+30−0

@@ -0,0 +1,30 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
	7	#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
	8
	9	#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28
	10	#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
	11	#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
	12	#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
	13
	14	#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
	15	#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
	16	#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
	17	#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
	18	#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
	19	#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
	20	#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220
	21	#define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238
	22	#define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244
	23	#define QSERDES_UFS_V6_RX_MODE_RATE3_B3 0x25c
	24	#define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260
	25	#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
	26	#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
	27	#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
	28	#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
	29
	30	#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h+0−5

 #define QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_
 /* Only for QMP V5 5NM PHY - TX registers */
-#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX		0x30
-#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX		0x34
-#define QSERDES_V5_5NM_TX_LANE_MODE_1				0x78
-#define QSERDES_V5_5NM_TX_LANE_MODE_2				0x7c
-#define QSERDES_V5_5NM_TX_LANE_MODE_3				0x80
 #define QSERDES_V5_5NM_TX_BIST_MODE_LANENO			0x00
 #define QSERDES_V5_5NM_TX_BIST_INVERT				0x04
 #define QSERDES_V5_5NM_TX_CLKBUF_ENABLE				0x08

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h+77−0

@@ -0,0 +1,77 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
	7	#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
	8
	9	#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
	10	#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
	11	#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
	12	#define QSERDES_V6_TX_TX_BAND 0x24
	13	#define QSERDES_V6_TX_INTERFACE_SELECT 0x2c
	14	#define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34
	15	#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
	16	#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
	17	#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40
	18	#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
	19	#define QSERDES_V6_TX_BIST_PATTERN7 0x7c
	20	#define QSERDES_V6_TX_LANE_MODE_1 0x84
	21	#define QSERDES_V6_TX_LANE_MODE_3 0x8c
	22	#define QSERDES_V6_TX_LANE_MODE_4 0x90
	23	#define QSERDES_V6_TX_LANE_MODE_5 0x94
	24	#define QSERDES_V6_TX_RCV_DETECT_LVL_2 0xa4
	25	#define QSERDES_V6_TX_TRAN_DRVR_EMP_EN 0xc0
	26	#define QSERDES_V6_TX_TX_INTERFACE_MODE 0xc4
	27	#define QSERDES_V6_TX_VMODE_CTRL1 0xc8
	28	#define QSERDES_V6_TX_PI_QEC_CTRL 0xe4
	29
	30	#define QSERDES_V6_RX_UCDR_FO_GAIN 0x08
	31	#define QSERDES_V6_RX_UCDR_SO_GAIN 0x14
	32	#define QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN 0x30
	33	#define QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34
	34	#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c
	35	#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40
	36	#define QSERDES_V6_RX_UCDR_PI_CONTROLS 0x44
	37	#define QSERDES_V6_RX_UCDR_SB2_THRESH1 0x4c
	38	#define QSERDES_V6_RX_UCDR_SB2_THRESH2 0x50
	39	#define QSERDES_V6_RX_UCDR_SB2_GAIN1 0x54
	40	#define QSERDES_V6_RX_UCDR_SB2_GAIN2 0x58
	41	#define QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE 0x60
	42	#define QSERDES_V6_RX_TX_ADAPT_POST_THRESH 0xcc
	43	#define QSERDES_V6_RX_VGA_CAL_CNTRL1 0xd4
	44	#define QSERDES_V6_RX_VGA_CAL_CNTRL2 0xd8
	45	#define QSERDES_V6_RX_GM_CAL 0xdc
	46	#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2 0xec
	47	#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0
	48	#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4
	49	#define QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW 0xf8
	50	#define QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH 0xfc
	51	#define QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
	52	#define QSERDES_V6_RX_SIDGET_ENABLES 0x118
	53	#define QSERDES_V6_RX_SIGDET_CNTRL 0x11c
	54	#define QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL 0x124
	55	#define QSERDES_V6_RX_RX_MODE_00_LOW 0x15c
	56	#define QSERDES_V6_RX_RX_MODE_00_HIGH 0x160
	57	#define QSERDES_V6_RX_RX_MODE_00_HIGH2 0x164
	58	#define QSERDES_V6_RX_RX_MODE_00_HIGH3 0x168
	59	#define QSERDES_V6_RX_RX_MODE_00_HIGH4 0x16c
	60	#define QSERDES_V6_RX_RX_MODE_01_LOW 0x170
	61	#define QSERDES_V6_RX_RX_MODE_01_HIGH 0x174
	62	#define QSERDES_V6_RX_RX_MODE_01_HIGH2 0x178
	63	#define QSERDES_V6_RX_RX_MODE_01_HIGH3 0x17c
	64	#define QSERDES_V6_RX_RX_MODE_01_HIGH4 0x180
	65	#define QSERDES_V6_RX_RX_MODE_10_LOW 0x184
	66	#define QSERDES_V6_RX_RX_MODE_10_HIGH 0x188
	67	#define QSERDES_V6_RX_RX_MODE_10_HIGH2 0x18c
	68	#define QSERDES_V6_RX_RX_MODE_10_HIGH3 0x190
	69	#define QSERDES_V6_RX_RX_MODE_10_HIGH4 0x194
	70	#define QSERDES_V6_RX_DFE_EN_TIMER 0x1a0
	71	#define QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
	72	#define QSERDES_V6_RX_DCC_CTRL1 0x1a8
	73	#define QSERDES_V6_RX_VTH_CODE 0x1b0
	74	#define QSERDES_V6_RX_SIGDET_CAL_CTRL1 0x1e4
	75	#define QSERDES_V6_RX_SIGDET_CAL_TRIM 0x1f8
	76
	77	#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h+45−0

@@ -0,0 +1,45 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#ifndef QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_
	7	#define QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_
	8
	9	#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
	10	#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
	11	#define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
	12	#define QSERDES_V6_20_TX_LANE_MODE_1 0x78
	13	#define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
	14	#define QSERDES_V6_20_TX_LANE_MODE_3 0x80
	15
	16	#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
	17	#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
	18	#define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20
	19	#define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34
	20	#define QSERDES_V6_20_RX_IVCM_CAL_CTRL2 0x9c
	21	#define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET 0xa0
	22	#define QSERDES_V6_20_RX_DFE_3 0xb4
	23	#define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8
	24	#define QSERDES_V6_20_RX_GM_CAL 0x10c
	25	#define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120
	26	#define QSERDES_V6_20_RX_SIGDET_ENABLES 0x148
	27	#define QSERDES_V6_20_RX_PHPRE_CTRL 0x188
	28	#define QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x194
	29	#define QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc
	30	#define QSERDES_V6_20_RX_MODE_RATE2_B0 0x1f4
	31	#define QSERDES_V6_20_RX_MODE_RATE2_B1 0x1f8
	32	#define QSERDES_V6_20_RX_MODE_RATE2_B2 0x1fc
	33	#define QSERDES_V6_20_RX_MODE_RATE2_B3 0x200
	34	#define QSERDES_V6_20_RX_MODE_RATE2_B4 0x204
	35	#define QSERDES_V6_20_RX_MODE_RATE2_B5 0x208
	36	#define QSERDES_V6_20_RX_MODE_RATE2_B6 0x20c
	37	#define QSERDES_V6_20_RX_MODE_RATE3_B0 0x210
	38	#define QSERDES_V6_20_RX_MODE_RATE3_B1 0x214
	39	#define QSERDES_V6_20_RX_MODE_RATE3_B2 0x218
	40	#define QSERDES_V6_20_RX_MODE_RATE3_B3 0x21c
	41	#define QSERDES_V6_20_RX_MODE_RATE3_B4 0x220
	42	#define QSERDES_V6_20_RX_MODE_RATE3_B5 0x224
	43	#define QSERDES_V6_20_RX_MODE_RATE3_B6 0x228
	44
	45	#endif

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c+538−150

@@ -20,7 +20,15 @@ · 19 unmodified lines
20	#include <linux/reset.h>	20	#include <linux/reset.h>
21	#include <linux/slab.h>	21	#include <linux/slab.h>
22		22
		23	#include <ufs/unipro.h>
23	#include "phy-qcom-qmp.h"	24	#include "phy-qcom-qmp.h"
		25	#include "phy-qcom-qmp-pcs-ufs-v2.h"
		26	#include "phy-qcom-qmp-pcs-ufs-v3.h"
		27	#include "phy-qcom-qmp-pcs-ufs-v4.h"
		28	#include "phy-qcom-qmp-pcs-ufs-v5.h"
		29	#include "phy-qcom-qmp-pcs-ufs-v6.h"
		30
		31	#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
24		32
25	/* QPHY_SW_RESET bit */	33	/* QPHY_SW_RESET bit */
26	#define SW_RESET BIT(0)	34	#define SW_RESET BIT(0)
@@ -69,32 +77,40 @@ enum qphy_reg_layout { · 42 unmodified lines
69	QPHY_LAYOUT_SIZE	77	QPHY_LAYOUT_SIZE
70	};	78	};
71		79
72	static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {	80	static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
73	[QPHY_START_CTRL] = 0x00,	81	[QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
74	[QPHY_PCS_READY_STATUS] = 0x168,	82	[QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
75	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,	83	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
76	};
77
78	static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
79	[QPHY_START_CTRL] = 0x00,
80	[QPHY_PCS_READY_STATUS] = 0x160,
81	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
82	};	84	};
83		85
84	static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {	86	static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
85	[QPHY_START_CTRL] = 0x00,	87	[QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START,
86	[QPHY_PCS_READY_STATUS] = 0x168,	88	[QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS,
87	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,	89	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
88	};	90	};
89		91
90	static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {	92	static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
91	[QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,	93	[QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
92	[QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,	94	[QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
93	[QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,	95	[QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
94	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,	96	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
95	};	97	};
96		98
97	static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {	99	static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
		100	[QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START,
		101	[QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS,
		102	[QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET,
		103	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
		104	};
		105
		106	static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
		107	[QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START,
		108	[QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS,
		109	[QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET,
		110	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
		111	};
		112
		113	static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
98	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),	114	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
99	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),	115	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
100	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),	116	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
@@ -143,12 +159,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { · 42 unmodified lines
143	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),	159	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
144	};	160	};
145		161
146	static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {	162	static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = {
147	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),	163	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
148	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),	164	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
149	};	165	};
150		166
151	static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {	167	static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {
152	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),	168	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
153	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),	169	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
154	QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),	170	QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
@@ -162,7 +178,7 @@ static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { · 7 unmodified lines
162	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),	178	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
163	};	179	};
164		180
165	static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {	181	static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
166	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),	182	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
167	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),	183	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
168	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),	184	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
@@ -213,17 +229,18 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { · 44 unmodified lines
213	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),	229	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
214	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),	230	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
215	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),	231	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
		232	};
216		233
217	/* Rate B */	234	static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
218	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),	235	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
219	};	236	};
220		237
221	static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {	238	static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {
222	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),	239	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
223	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),	240	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
224	};	241	};
225		242
226	static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {	243	static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {
227	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),	244	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
228	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),	245	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
229	QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),	246	QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
@@ -241,19 +258,19 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { · 11 unmodified lines
241	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),	258	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
242	};	259	};
243		260
244	static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {	261	static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {
245	QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15),	262	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15),
246	QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d),	263	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
247	QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f),	264	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
248	QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),	265	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
249	QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),	266	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
250	QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SYM_RESYNC_CTRL, 0x03),	267	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
251	QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),	268	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
252	QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),	269	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
253	QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */	270	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
254	};	271	};
255		272
256	static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {	273	static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
257	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),	274	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
258	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),	275	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
259	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),	276	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
@@ -290,18 +307,19 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { · 30 unmodified lines
290	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),	307	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
291	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),	308	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
292	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),	309	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
		310	};
293		311
294	/* Rate B */	312	static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
295	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),	313	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
296	};	314	};
297		315
298	static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {	316	static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {
299	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),	317	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
300	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),	318	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
301	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),	319	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
302	};	320	};
303		321
304	static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {	322	static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {
305	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),	323	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
306	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),	324	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
307	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),	325	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
@@ -320,7 +338,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { · 12 unmodified lines
320	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),	338	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
321	};	339	};
322		340
323	static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {	341	static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
324	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),	342	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
325	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),	343	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
326	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),	344	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
@@ -331,7 +349,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { · 4 unmodified lines
331	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),	349	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
332	};	350	};
333		351
334	static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {	352	static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
335	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),	353	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
336	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),	354	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
337	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),	355	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
@@ -356,12 +374,13 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { · 18 unmodified lines
356	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),	374	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
357	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),	375	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
358	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),	376	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
		377	};
359		378
360	/* Rate B */	379	static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
361	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),	380	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
362	};	381	};
363		382
364	static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {	383	static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
365	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),	384	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
366	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),	385	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
367	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),	386	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
@@ -370,7 +389,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { · 2 unmodified lines
370	QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),	389	QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
371	};	390	};
372		391
373	static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {	392	static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
		393	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
		394	};
		395
		396	static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
374	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),	397	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
375	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),	398	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
376	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),	399	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
@@ -405,10 +428,28 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { · 28 unmodified lines
405	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),	428	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
406	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),	429	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
407	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),	430	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
		431	};
408		432
		433	static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
		434	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
		435	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
		436	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
		437	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
		438	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
		439	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
		440	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
		441	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
		442	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
		443	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
		444	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
		445	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
		446	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
		447	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
		448	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
		449	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
409	};	450	};
410		451
411	static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {	452	static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
412	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),	453	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
413	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),	454	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
414	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),	455	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
@@ -418,7 +459,40 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { · 3 unmodified lines
418	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),	459	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
419	};	460	};
420		461
421	static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {	462	static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
		463	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
		464	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
		465	};
		466
		467	static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
		468	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
		469	};
		470
		471	static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
		472	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
		473	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
		474	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
		475	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
		476	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
		477	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
		478	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
		479	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
		480	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
		481	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
		482	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
		483	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
		484	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
		485	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
		486	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
		487	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
		488	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
		489	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
		490	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
		491	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
		492	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
		493	};
		494
		495	static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
422	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),	496	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
423	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),	497	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
424	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),	498	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
@@ -443,12 +517,13 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { · 18 unmodified lines
443	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),	517	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
444	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),	518	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
445	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),	519	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
		520	};
446		521
447	/* Rate B */	522	static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
448	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),	523	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
449	};	524	};
450		525
451	static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {	526	static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {
452	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),	527	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
453	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),	528	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
454	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),	529	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
@@ -460,7 +535,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { · 5 unmodified lines
460	QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),	535	QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
461	};	536	};
462		537
463	static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {	538	static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {
464	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),	539	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
465	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),	540	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
466	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),	541	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
@@ -500,24 +575,100 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { · 33 unmodified lines
500	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),	575	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
501	};	576	};
502		577
503	static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {	578	static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
504	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),	579	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
505	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),	580	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
506	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),	581	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
507	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),	582	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
508	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),	583	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
509	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),	584	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
510	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
511	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
512	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
513	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
514	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
515	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
516	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
517	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),	585	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
518	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),	586	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
519	};	587	};
520		588
		589	static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = {
		590	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),
		591	};
		592
		593	static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = {
		594	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),
		595	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),
		596	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
		597	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
		598	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
		599	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),
		600	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),
		601	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
		602	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),
		603	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),
		604	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
		605	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),
		606	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),
		607	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),
		608	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),
		609	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),
		610	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),
		611	};
		612
		613	static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {
		614	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
		615	};
		616
		617	static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
		618	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
		619	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
		620	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
		621	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
		622	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
		623	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
		624	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
		625	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
		626	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
		627	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
		628	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
		629	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
		630	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
		631	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
		632	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
		633	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
		634	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
		635	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
		636	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
		637	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
		638	};
		639
		640	static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
		641	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
		642	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
		643	};
		644
		645	static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
		646	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
		647	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
		648	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
		649
		650	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
		651	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
		652	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
		653	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
		654
		655	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
		656	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
		657
		658	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
		659	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
		660	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
		661	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
		662	};
		663
		664	static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
		665	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
		666	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
		667	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
		668	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
		669	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
		670	};
		671
521	struct qmp_ufs_offsets {	672	struct qmp_ufs_offsets {
522	u16 serdes;	673	u16 serdes;
523	u16 pcs;	674	u16 pcs;
@@ -527,21 +678,30 @@ struct qmp_ufs_offsets { · 3 unmodified lines
527	u16 rx2;	678	u16 rx2;
528	};	679	};
529		680
		681	struct qmp_phy_cfg_tbls {
		682	/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
		683	const struct qmp_phy_init_tbl *serdes;
		684	int serdes_num;
		685	const struct qmp_phy_init_tbl *tx;
		686	int tx_num;
		687	const struct qmp_phy_init_tbl *rx;
		688	int rx_num;
		689	const struct qmp_phy_init_tbl *pcs;
		690	int pcs_num;
		691	};
		692
530	/* struct qmp_phy_cfg - per-PHY initialization config */	693	/* struct qmp_phy_cfg - per-PHY initialization config */
531	struct qmp_phy_cfg {	694	struct qmp_phy_cfg {
532	int lanes;	695	int lanes;
533		696
534	const struct qmp_ufs_offsets *offsets;	697	const struct qmp_ufs_offsets *offsets;
535		698
536	/* Init sequence for PHY blocks - serdes, tx, rx, pcs */	699	/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
537	const struct qmp_phy_init_tbl *serdes_tbl;	700	const struct qmp_phy_cfg_tbls tbls;
538	int serdes_tbl_num;	701	/* Additional sequence for HS Series B */
539	const struct qmp_phy_init_tbl *tx_tbl;	702	const struct qmp_phy_cfg_tbls tbls_hs_b;
540	int tx_tbl_num;	703	/* Additional sequence for HS G4 */
541	const struct qmp_phy_init_tbl *rx_tbl;	704	const struct qmp_phy_cfg_tbls tbls_hs_g4;
542	int rx_tbl_num;
543	const struct qmp_phy_init_tbl *pcs_tbl;
544	int pcs_tbl_num;
545		705
546	/* clock ids to be requested */	706	/* clock ids to be requested */
547	const char * const *clk_list;	707	const char * const *clk_list;
@@ -575,6 +735,8 @@ struct qmp_ufs { · 27 unmodified lines
575	struct reset_control *ufs_reset;	735	struct reset_control *ufs_reset;
576		736
577	struct phy *phy;	737	struct phy *phy;
		738	u32 mode;
		739	u32 submode;
578	};	740	};
579		741
580	static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)	742	static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
@@ -620,7 +782,7 @@ static const char * const qmp_phy_vreg_l[] = { · 39 unmodified lines
620	"vdda-phy", "vdda-pll",	782	"vdda-phy", "vdda-pll",
621	};	783	};
622		784
623	static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {	785	static const struct qmp_ufs_offsets qmp_ufs_offsets = {
624	.serdes = 0,	786	.serdes = 0,
625	.pcs = 0xc00,	787	.pcs = 0xc00,
626	.tx = 0x400,	788	.tx = 0x400,
@@ -629,15 +791,26 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = { · 2 unmodified lines
629	.rx2 = 0xa00,	791	.rx2 = 0xa00,
630	};	792	};
631		793
632	static const struct qmp_phy_cfg msm8996_ufs_cfg = {	794	static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
		795	.serdes = 0,
		796	.pcs = 0x0400,
		797	.tx = 0x1000,
		798	.rx = 0x1200,
		799	.tx2 = 0x1800,
		800	.rx2 = 0x1a00,
		801	};
		802
		803	static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
633	.lanes = 1,	804	.lanes = 1,
634		805
635	.serdes_tbl = msm8996_ufs_serdes_tbl,	806	.tbls = {
636	.serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),	807	.serdes = msm8996_ufsphy_serdes,
637	.tx_tbl = msm8996_ufs_tx_tbl,	808	.serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
638	.tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),	809	.tx = msm8996_ufsphy_tx,
639	.rx_tbl = msm8996_ufs_rx_tbl,	810	.tx_num = ARRAY_SIZE(msm8996_ufsphy_tx),
640	.rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),	811	.rx = msm8996_ufsphy_rx,
		812	.rx_num = ARRAY_SIZE(msm8996_ufsphy_rx),
		813	},
641		814
642	.clk_list = msm8996_ufs_phy_clk_l,	815	.clk_list = msm8996_ufs_phy_clk_l,
643	.num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),	816	.num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
@@ -645,7 +818,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { · 1 unmodified line
645	.vreg_list = qmp_phy_vreg_l,	818	.vreg_list = qmp_phy_vreg_l,
646	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	819	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
647		820
648	.regs = msm8996_ufsphy_regs_layout,	821	.regs = ufsphy_v2_regs_layout,
649		822
650	.no_pcs_sw_reset = true,	823	.no_pcs_sw_reset = true,
651	};	824	};
@@ -653,39 +826,59 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { · 1 unmodified line
653	static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {	826	static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
654	.lanes = 2,	827	.lanes = 2,
655		828
656	.offsets = &qmp_ufs_offsets_v5,	829	.offsets = &qmp_ufs_offsets,
657		830
658	.serdes_tbl = sm8350_ufsphy_serdes_tbl,	831	.tbls = {
659	.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),	832	.serdes = sm8350_ufsphy_serdes,
660	.tx_tbl = sm8350_ufsphy_tx_tbl,	833	.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
661	.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),	834	.tx = sm8350_ufsphy_tx,
662	.rx_tbl = sm8350_ufsphy_rx_tbl,	835	.tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
663	.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),	836	.rx = sm8350_ufsphy_rx,
664	.pcs_tbl = sm8350_ufsphy_pcs_tbl,	837	.rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
665	.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),	838	.pcs = sm8350_ufsphy_pcs,
		839	.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
		840	},
		841	.tbls_hs_b = {
		842	.serdes = sm8350_ufsphy_hs_b_serdes,
		843	.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
		844	},
		845	.tbls_hs_g4 = {
		846	.tx = sm8350_ufsphy_g4_tx,
		847	.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
		848	.rx = sm8350_ufsphy_g4_rx,
		849	.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
		850	.pcs = sm8350_ufsphy_g4_pcs,
		851	.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
		852	},
666	.clk_list = sdm845_ufs_phy_clk_l,	853	.clk_list = sdm845_ufs_phy_clk_l,
667	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),	854	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
668	.vreg_list = qmp_phy_vreg_l,	855	.vreg_list = qmp_phy_vreg_l,
669	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	856	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
670	.regs = sm8150_ufsphy_regs_layout,	857	.regs = ufsphy_v5_regs_layout,
671	};	858	};
672		859
673	static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {	860	static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
674	.lanes = 2,	861	.lanes = 2,
675		862
676	.serdes_tbl = sdm845_ufsphy_serdes_tbl,	863	.tbls = {
677	.serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),	864	.serdes = sdm845_ufsphy_serdes,
678	.tx_tbl = sdm845_ufsphy_tx_tbl,	865	.serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
679	.tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),	866	.tx = sdm845_ufsphy_tx,
680	.rx_tbl = sdm845_ufsphy_rx_tbl,	867	.tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
681	.rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),	868	.rx = sdm845_ufsphy_rx,
682	.pcs_tbl = sdm845_ufsphy_pcs_tbl,	869	.rx_num = ARRAY_SIZE(sdm845_ufsphy_rx),
683	.pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),	870	.pcs = sdm845_ufsphy_pcs,
		871	.pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
		872	},
		873	.tbls_hs_b = {
		874	.serdes = sdm845_ufsphy_hs_b_serdes,
		875	.serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
		876	},
684	.clk_list = sdm845_ufs_phy_clk_l,	877	.clk_list = sdm845_ufs_phy_clk_l,
685	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),	878	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
686	.vreg_list = qmp_phy_vreg_l,	879	.vreg_list = qmp_phy_vreg_l,
687	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	880	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
688	.regs = sdm845_ufsphy_regs_layout,	881	.regs = ufsphy_v3_regs_layout,
689		882
690	.no_pcs_sw_reset = true,	883	.no_pcs_sw_reset = true,
691	};	884	};
@@ -693,19 +886,27 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { · 1 unmodified line
693	static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {	886	static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
694	.lanes = 1,	887	.lanes = 1,
695		888
696	.serdes_tbl = sm6115_ufsphy_serdes_tbl,	889	.offsets = &qmp_ufs_offsets,
697	.serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),	890
698	.tx_tbl = sm6115_ufsphy_tx_tbl,	891	.tbls = {
699	.tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),	892	.serdes = sm6115_ufsphy_serdes,
700	.rx_tbl = sm6115_ufsphy_rx_tbl,	893	.serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
701	.rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),	894	.tx = sm6115_ufsphy_tx,
702	.pcs_tbl = sm6115_ufsphy_pcs_tbl,	895	.tx_num = ARRAY_SIZE(sm6115_ufsphy_tx),
703	.pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),	896	.rx = sm6115_ufsphy_rx,
		897	.rx_num = ARRAY_SIZE(sm6115_ufsphy_rx),
		898	.pcs = sm6115_ufsphy_pcs,
		899	.pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
		900	},
		901	.tbls_hs_b = {
		902	.serdes = sm6115_ufsphy_hs_b_serdes,
		903	.serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
		904	},
704	.clk_list = sdm845_ufs_phy_clk_l,	905	.clk_list = sdm845_ufs_phy_clk_l,
705	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),	906	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
706	.vreg_list = qmp_phy_vreg_l,	907	.vreg_list = qmp_phy_vreg_l,
707	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	908	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
708	.regs = sm6115_ufsphy_regs_layout,	909	.regs = ufsphy_v2_regs_layout,
709		910
710	.no_pcs_sw_reset = true,	911	.no_pcs_sw_reset = true,
711	};	912	};
@@ -713,55 +914,151 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { · 1 unmodified line
713	static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {	914	static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
714	.lanes = 2,	915	.lanes = 2,
715		916
716	.serdes_tbl = sm8150_ufsphy_serdes_tbl,	917	.tbls = {
717	.serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),	918	.serdes = sm8150_ufsphy_serdes,
718	.tx_tbl = sm8150_ufsphy_tx_tbl,	919	.serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
719	.tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),	920	.tx = sm8150_ufsphy_tx,
720	.rx_tbl = sm8150_ufsphy_rx_tbl,	921	.tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
721	.rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),	922	.rx = sm8150_ufsphy_rx,
722	.pcs_tbl = sm8150_ufsphy_pcs_tbl,	923	.rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
723	.pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),	924	.pcs = sm8150_ufsphy_pcs,
		925	.pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
		926	},
		927	.tbls_hs_b = {
		928	.serdes = sm8150_ufsphy_hs_b_serdes,
		929	.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
		930	},
		931	.tbls_hs_g4 = {
		932	.tx = sm8150_ufsphy_hs_g4_tx,
		933	.tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
		934	.rx = sm8150_ufsphy_hs_g4_rx,
		935	.rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
		936	.pcs = sm8150_ufsphy_hs_g4_pcs,
		937	.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
		938	},
		939	.clk_list = sdm845_ufs_phy_clk_l,
		940	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
		941	.vreg_list = qmp_phy_vreg_l,
		942	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
		943	.regs = ufsphy_v4_regs_layout,
		944	};
		945
		946	static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
		947	.lanes = 2,
		948
		949	.tbls = {
		950	.serdes = sm8150_ufsphy_serdes,
		951	.serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
		952	.tx = sm8150_ufsphy_tx,
		953	.tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
		954	.rx = sm8150_ufsphy_rx,
		955	.rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
		956	.pcs = sm8150_ufsphy_pcs,
		957	.pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
		958	},
		959	.tbls_hs_b = {
		960	.serdes = sm8150_ufsphy_hs_b_serdes,
		961	.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
		962	},
		963	.tbls_hs_g4 = {
		964	.tx = sm8250_ufsphy_hs_g4_tx,
		965	.tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
		966	.rx = sm8250_ufsphy_hs_g4_rx,
		967	.rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
		968	.pcs = sm8150_ufsphy_hs_g4_pcs,
		969	.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
		970	},
724	.clk_list = sdm845_ufs_phy_clk_l,	971	.clk_list = sdm845_ufs_phy_clk_l,
725	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),	972	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
726	.vreg_list = qmp_phy_vreg_l,	973	.vreg_list = qmp_phy_vreg_l,
727	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	974	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
728	.regs = sm8150_ufsphy_regs_layout,	975	.regs = ufsphy_v4_regs_layout,
729	};	976	};
730		977
731	static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {	978	static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
732	.lanes = 2,	979	.lanes = 2,
733		980
734	.serdes_tbl = sm8350_ufsphy_serdes_tbl,	981	.tbls = {
735	.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),	982	.serdes = sm8350_ufsphy_serdes,
736	.tx_tbl = sm8350_ufsphy_tx_tbl,	983	.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
737	.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),	984	.tx = sm8350_ufsphy_tx,
738	.rx_tbl = sm8350_ufsphy_rx_tbl,	985	.tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
739	.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),	986	.rx = sm8350_ufsphy_rx,
740	.pcs_tbl = sm8350_ufsphy_pcs_tbl,	987	.rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
741	.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),	988	.pcs = sm8350_ufsphy_pcs,
		989	.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
		990	},
		991	.tbls_hs_b = {
		992	.serdes = sm8350_ufsphy_hs_b_serdes,
		993	.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
		994	},
		995	.tbls_hs_g4 = {
		996	.tx = sm8350_ufsphy_g4_tx,
		997	.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
		998	.rx = sm8350_ufsphy_g4_rx,
		999	.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
		1000	.pcs = sm8350_ufsphy_g4_pcs,
		1001	.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
		1002	},
742	.clk_list = sdm845_ufs_phy_clk_l,	1003	.clk_list = sdm845_ufs_phy_clk_l,
743	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),	1004	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
744	.vreg_list = qmp_phy_vreg_l,	1005	.vreg_list = qmp_phy_vreg_l,
745	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	1006	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
746	.regs = sm8150_ufsphy_regs_layout,	1007	.regs = ufsphy_v5_regs_layout,
747	};	1008	};
748		1009
749	static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {	1010	static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
750	.lanes = 2,	1011	.lanes = 2,
751		1012
752	.serdes_tbl = sm8350_ufsphy_serdes_tbl,	1013	.tbls = {
753	.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),	1014	.serdes = sm8350_ufsphy_serdes,
754	.tx_tbl = sm8350_ufsphy_tx_tbl,	1015	.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
755	.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),	1016	.tx = sm8350_ufsphy_tx,
756	.rx_tbl = sm8350_ufsphy_rx_tbl,	1017	.tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
757	.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),	1018	.rx = sm8350_ufsphy_rx,
758	.pcs_tbl = sm8350_ufsphy_pcs_tbl,	1019	.rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
759	.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),	1020	.pcs = sm8350_ufsphy_pcs,
		1021	.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
		1022	},
		1023	.tbls_hs_b = {
		1024	.serdes = sm8350_ufsphy_hs_b_serdes,
		1025	.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
		1026	},
		1027	.tbls_hs_g4 = {
		1028	.tx = sm8350_ufsphy_g4_tx,
		1029	.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
		1030	.rx = sm8350_ufsphy_g4_rx,
		1031	.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
		1032	.pcs = sm8350_ufsphy_g4_pcs,
		1033	.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
		1034	},
760	.clk_list = sm8450_ufs_phy_clk_l,	1035	.clk_list = sm8450_ufs_phy_clk_l,
761	.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),	1036	.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
762	.vreg_list = qmp_phy_vreg_l,	1037	.vreg_list = qmp_phy_vreg_l,
763	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	1038	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
764	.regs = sm8150_ufsphy_regs_layout,	1039	.regs = ufsphy_v5_regs_layout,
		1040	};
		1041
		1042	static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
		1043	.lanes = 2,
		1044
		1045	.offsets = &qmp_ufs_offsets_v6,
		1046
		1047	.tbls = {
		1048	.serdes = sm8550_ufsphy_serdes,
		1049	.serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes),
		1050	.tx = sm8550_ufsphy_tx,
		1051	.tx_num = ARRAY_SIZE(sm8550_ufsphy_tx),
		1052	.rx = sm8550_ufsphy_rx,
		1053	.rx_num = ARRAY_SIZE(sm8550_ufsphy_rx),
		1054	.pcs = sm8550_ufsphy_pcs,
		1055	.pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
		1056	},
		1057	.clk_list = sdm845_ufs_phy_clk_l,
		1058	.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
		1059	.vreg_list = qmp_phy_vreg_l,
		1060	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
		1061	.regs = ufsphy_v6_regs_layout,
765	};	1062	};
766		1063
767	static void qmp_ufs_configure_lane(void __iomem *base,	1064	static void qmp_ufs_configure_lane(void __iomem *base,
@@ -790,16 +1087,46 @@ static void qmp_ufs_configure(void __iomem *base, · 22 unmodified lines
790	qmp_ufs_configure_lane(base, tbl, num, 0xff);	1087	qmp_ufs_configure_lane(base, tbl, num, 0xff);
791	}	1088	}
792		1089
793	static int qmp_ufs_serdes_init(struct qmp_ufs *qmp)	1090	static void qmp_ufs_serdes_init(struct qmp_ufs qmp, const struct qmp_phy_cfg_tbls tbls)
794	{	1091	{
795	const struct qmp_phy_cfg *cfg = qmp->cfg;
796	void __iomem *serdes = qmp->serdes;	1092	void __iomem *serdes = qmp->serdes;
797	const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
798	int serdes_tbl_num = cfg->serdes_tbl_num;
799		1093
800	qmp_ufs_configure(serdes, serdes_tbl, serdes_tbl_num);	1094	qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num);
		1095	}
801		1096
802	return 0;	1097	static void qmp_ufs_lanes_init(struct qmp_ufs qmp, const struct qmp_phy_cfg_tbls tbls)
		1098	{
		1099	const struct qmp_phy_cfg *cfg = qmp->cfg;
		1100	void __iomem *tx = qmp->tx;
		1101	void __iomem *rx = qmp->rx;
		1102
		1103	qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
		1104	qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
		1105
		1106	if (cfg->lanes >= 2) {
		1107	qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
		1108	qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
		1109	}
		1110	}
		1111
		1112	static void qmp_ufs_pcs_init(struct qmp_ufs qmp, const struct qmp_phy_cfg_tbls tbls)
		1113	{
		1114	void __iomem *pcs = qmp->pcs;
		1115
		1116	qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
		1117	}
		1118
		1119	static void qmp_ufs_init_registers(struct qmp_ufs qmp, const struct qmp_phy_cfg cfg)
		1120	{
		1121	qmp_ufs_serdes_init(qmp, &cfg->tbls);
		1122	if (qmp->mode == PHY_MODE_UFS_HS_B)
		1123	qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
		1124	qmp_ufs_lanes_init(qmp, &cfg->tbls);
		1125	if (qmp->submode == UFS_HS_G4)
		1126	qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
		1127	qmp_ufs_pcs_init(qmp, &cfg->tbls);
		1128	if (qmp->submode == UFS_HS_G4)
		1129	qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
803	}	1130	}
804		1131
805	static int qmp_ufs_com_init(struct qmp_ufs *qmp)	1132	static int qmp_ufs_com_init(struct qmp_ufs *qmp)
@@ -886,25 +1213,12 @@ static int qmp_ufs_power_on(struct phy *phy) · 80 unmodified lines
886	{	1213	{
887	struct qmp_ufs *qmp = phy_get_drvdata(phy);	1214	struct qmp_ufs *qmp = phy_get_drvdata(phy);
888	const struct qmp_phy_cfg *cfg = qmp->cfg;	1215	const struct qmp_phy_cfg *cfg = qmp->cfg;
889	void __iomem *tx = qmp->tx;
890	void __iomem *rx = qmp->rx;
891	void __iomem *pcs = qmp->pcs;	1216	void __iomem *pcs = qmp->pcs;
892	void __iomem *status;	1217	void __iomem *status;
893	unsigned int val;	1218	unsigned int val;
894	int ret;	1219	int ret;
895		1220
896	qmp_ufs_serdes_init(qmp);	1221	qmp_ufs_init_registers(qmp, cfg);
897
898	/* Tx, Rx, and PCS configurations */
899	qmp_ufs_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
900	qmp_ufs_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
901
902	if (cfg->lanes >= 2) {
903	qmp_ufs_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
904	qmp_ufs_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
905	}
906
907	qmp_ufs_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
908		1222
909	ret = reset_control_deassert(qmp->ufs_reset);	1223	ret = reset_control_deassert(qmp->ufs_reset);
910	if (ret)	1224	if (ret)
@@ -981,9 +1295,20 @@ static int qmp_ufs_disable(struct phy *phy) · 70 unmodified lines
981	return qmp_ufs_exit(phy);	1295	return qmp_ufs_exit(phy);
982	}	1296	}
983		1297
		1298	static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
		1299	{
		1300	struct qmp_ufs *qmp = phy_get_drvdata(phy);
		1301
		1302	qmp->mode = mode;
		1303	qmp->submode = submode;
		1304
		1305	return 0;
		1306	}
		1307
984	static const struct phy_ops qcom_qmp_ufs_phy_ops = {	1308	static const struct phy_ops qcom_qmp_ufs_phy_ops = {
985	.power_on = qmp_ufs_enable,	1309	.power_on = qmp_ufs_enable,
986	.power_off = qmp_ufs_disable,	1310	.power_off = qmp_ufs_disable,
		1311	.set_mode = qmp_ufs_set_mode,
987	.owner = THIS_MODULE,	1312	.owner = THIS_MODULE,
988	};	1313	};
989		1314
@@ -1021,6 +1346,59 @@ static int qmp_ufs_clk_init(struct qmp_ufs *qmp) · 31 unmodified lines
1021	return devm_clk_bulk_get(dev, num, qmp->clks);	1346	return devm_clk_bulk_get(dev, num, qmp->clks);
1022	}	1347	}
1023		1348
		1349	static void qmp_ufs_clk_release_provider(void *res)
		1350	{
		1351	of_clk_del_provider(res);
		1352	}
		1353
		1354	#define UFS_SYMBOL_CLOCKS 3
		1355
		1356	static int qmp_ufs_register_clocks(struct qmp_ufs qmp, struct device_node np)
		1357	{
		1358	struct clk_hw_onecell_data *clk_data;
		1359	struct clk_hw *hw;
		1360	char name[64];
		1361	int ret;
		1362
		1363	clk_data = devm_kzalloc(qmp->dev,
		1364	struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
		1365	GFP_KERNEL);
		1366	if (!clk_data)
		1367	return -ENOMEM;
		1368
		1369	clk_data->num = UFS_SYMBOL_CLOCKS;
		1370
		1371	snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
		1372	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
		1373	if (IS_ERR(hw))
		1374	return PTR_ERR(hw);
		1375
		1376	clk_data->hws[0] = hw;
		1377
		1378	snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
		1379	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
		1380	if (IS_ERR(hw))
		1381	return PTR_ERR(hw);
		1382
		1383	clk_data->hws[1] = hw;
		1384
		1385	snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
		1386	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
		1387	if (IS_ERR(hw))
		1388	return PTR_ERR(hw);
		1389
		1390	clk_data->hws[2] = hw;
		1391
		1392	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
		1393	if (ret)
		1394	return ret;
		1395
		1396	/*
		1397	* Roll a devm action because the clock provider can be a child node.
		1398	*/
		1399	return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np);
		1400	}
		1401
1024	static int qmp_ufs_parse_dt_legacy(struct qmp_ufs qmp, struct device_node np)	1402	static int qmp_ufs_parse_dt_legacy(struct qmp_ufs qmp, struct device_node np)
1025	{	1403	{
1026	struct platform_device *pdev = to_platform_device(qmp->dev);	1404	struct platform_device *pdev = to_platform_device(qmp->dev);
@@ -1133,6 +1511,10 @@ static int qmp_ufs_probe(struct platform_device *pdev) · 106 unmodified lines
1133	if (ret)	1511	if (ret)
1134	goto err_node_put;	1512	goto err_node_put;
1135		1513
		1514	ret = qmp_ufs_register_clocks(qmp, np);
		1515	if (ret)
		1516	goto err_node_put;
		1517
1136	qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);	1518	qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
1137	if (IS_ERR(qmp->phy)) {	1519	if (IS_ERR(qmp->phy)) {
1138	ret = PTR_ERR(qmp->phy);	1520	ret = PTR_ERR(qmp->phy);
@@ -1156,7 +1538,7 @@ err_node_put: · 17 unmodified lines
1156	static const struct of_device_id qmp_ufs_of_match_table[] = {	1538	static const struct of_device_id qmp_ufs_of_match_table[] = {
1157	{	1539	{
1158	.compatible = "qcom,msm8996-qmp-ufs-phy",	1540	.compatible = "qcom,msm8996-qmp-ufs-phy",
1159	.data = &msm8996_ufs_cfg,	1541	.data = &msm8996_ufsphy_cfg,
1160	}, {	1542	}, {
1161	.compatible = "qcom,msm8998-qmp-ufs-phy",	1543	.compatible = "qcom,msm8998-qmp-ufs-phy",
1162	.data = &sdm845_ufsphy_cfg,	1544	.data = &sdm845_ufsphy_cfg,
@@ -1172,6 +1554,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { · 9 unmodified lines
1172	}, {	1554	}, {
1173	.compatible = "qcom,sm6115-qmp-ufs-phy",	1555	.compatible = "qcom,sm6115-qmp-ufs-phy",
1174	.data = &sm6115_ufsphy_cfg,	1556	.data = &sm6115_ufsphy_cfg,
		1557	}, {
		1558	.compatible = "qcom,sm6125-qmp-ufs-phy",
		1559	.data = &sm6115_ufsphy_cfg,
1175	}, {	1560	}, {
1176	.compatible = "qcom,sm6350-qmp-ufs-phy",	1561	.compatible = "qcom,sm6350-qmp-ufs-phy",
1177	.data = &sdm845_ufsphy_cfg,	1562	.data = &sdm845_ufsphy_cfg,
@@ -1180,13 +1565,16 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { · 2 unmodified lines
1180	.data = &sm8150_ufsphy_cfg,	1565	.data = &sm8150_ufsphy_cfg,
1181	}, {	1566	}, {
1182	.compatible = "qcom,sm8250-qmp-ufs-phy",	1567	.compatible = "qcom,sm8250-qmp-ufs-phy",
1183	.data = &sm8150_ufsphy_cfg,	1568	.data = &sm8250_ufsphy_cfg,
1184	}, {	1569	}, {
1185	.compatible = "qcom,sm8350-qmp-ufs-phy",	1570	.compatible = "qcom,sm8350-qmp-ufs-phy",
1186	.data = &sm8350_ufsphy_cfg,	1571	.data = &sm8350_ufsphy_cfg,
1187	}, {	1572	}, {
1188	.compatible = "qcom,sm8450-qmp-ufs-phy",	1573	.compatible = "qcom,sm8450-qmp-ufs-phy",
1189	.data = &sm8450_ufsphy_cfg,	1574	.data = &sm8450_ufsphy_cfg,
		1575	}, {
		1576	.compatible = "qcom,sm8550-qmp-ufs-phy",
		1577	.data = &sm8550_ufsphy_cfg,
1190	},	1578	},
1191	{ },	1579	{ },
1192	};	1580	};

drivers/phy/qualcomm/phy-qcom-qmp-usb.c+41−42

@@ -21,6 +21,9 @@ · 20 unmodified lines
21	#include <linux/slab.h>	21	#include <linux/slab.h>
22		22
23	#include "phy-qcom-qmp.h"	23	#include "phy-qcom-qmp.h"
		24	#include "phy-qcom-qmp-pcs-misc-v3.h"
		25	#include "phy-qcom-qmp-pcs-usb-v4.h"
		26	#include "phy-qcom-qmp-pcs-usb-v5.h"
24		27
25	/* QPHY_SW_RESET bit */	28	/* QPHY_SW_RESET bit */
26	#define SW_RESET BIT(0)	29	#define SW_RESET BIT(0)
@@ -54,9 +57,6 @@ · 27 unmodified lines
54	/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */	57	/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
55	#define IRQ_CLEAR BIT(0)	58	#define IRQ_CLEAR BIT(0)
56		59
57	/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
58	#define RCVR_DETECT BIT(0)
59
60	/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */	60	/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
61	#define CLAMP_EN BIT(0) /* enables i/o clamp_n */	61	#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
62		62
@@ -94,53 +94,49 @@ enum qphy_reg_layout { · 31 unmodified lines
94	QPHY_PCS_STATUS,	94	QPHY_PCS_STATUS,
95	QPHY_PCS_AUTONOMOUS_MODE_CTRL,	95	QPHY_PCS_AUTONOMOUS_MODE_CTRL,
96	QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,	96	QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
97	QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
98	QPHY_PCS_POWER_DOWN_CONTROL,	97	QPHY_PCS_POWER_DOWN_CONTROL,
99	/* PCS_MISC registers */
100	QPHY_PCS_MISC_TYPEC_CTRL,
101	/* Keep last to ensure regs_layout arrays are properly initialized */	98	/* Keep last to ensure regs_layout arrays are properly initialized */
102	QPHY_LAYOUT_SIZE	99	QPHY_LAYOUT_SIZE
103	};	100	};
104		101
105	static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {	102	static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
106	[QPHY_SW_RESET] = 0x00,	103	[QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
107	[QPHY_START_CTRL] = 0x08,	104	[QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
108	[QPHY_PCS_STATUS] = 0x17c,	105	[QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS,
109	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,	106	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,
110	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,	107	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,
111	[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,	108	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
112	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
113	};	109	};
114		110
115	static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {	111	static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
116	[QPHY_SW_RESET] = 0x00,	112	[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
117	[QPHY_START_CTRL] = 0x08,	113	[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
118	[QPHY_PCS_STATUS] = 0x174,	114	[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
119	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,	115	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
120	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,	116	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
121	[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,	117	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
122	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
123	};	118	};
124		119
125	static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {	120	static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
126	[QPHY_SW_RESET] = 0x00,	121	[QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
127	[QPHY_START_CTRL] = 0x44,	122	[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
128	[QPHY_PCS_STATUS] = 0x14,	123	[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
129	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,	124	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
130		125
131	/* In PCS_USB */	126	/* In PCS_USB */
132	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,	127	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
133	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,	128	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
134	};	129	};
135		130
136	static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {	131	static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
137	[QPHY_SW_RESET] = 0x00,	132	[QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
138	[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,	133	[QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
139	[QPHY_START_CTRL] = 0x08,	134	[QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
140	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,	135	[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
141	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,	136
142	[QPHY_PCS_STATUS] = 0x174,	137	/* In PCS_USB */
143	[QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,	138	[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
		139	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
144	};	140	};
145		141
146	static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {	142	static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
@@ -1265,7 +1261,7 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { · 1118 unmodified lines
1265		1261
1266	static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {	1262	static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
1267	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),	1263	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1268	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),	1264	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1269	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),	1265	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1270	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),	1266	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1271	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),	1267	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
@@ -1607,7 +1603,7 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { · 335 unmodified lines
1607	.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),	1603	.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1608	.vreg_list = qmp_phy_vreg_l,	1604	.vreg_list = qmp_phy_vreg_l,
1609	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	1605	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1610	.regs = usb3phy_regs_layout,	1606	.regs = qmp_v2_usb3phy_regs_layout,
1611	};	1607	};
1612		1608
1613	static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {	1609	static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
@@ -1675,7 +1671,7 @@ static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { · 61 unmodified lines
1675	.num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),	1671	.num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1676	.vreg_list = qmp_phy_vreg_l,	1672	.vreg_list = qmp_phy_vreg_l,
1677	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	1673	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1678	.regs = qmp_v4_usb3phy_regs_layout,	1674	.regs = qmp_v5_usb3phy_regs_layout,
1679	};	1675	};
1680		1676
1681	static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {	1677	static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
@@ -1866,7 +1862,7 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { · 184 unmodified lines
1866	.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),	1862	.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1867	.vreg_list = qmp_phy_vreg_l,	1863	.vreg_list = qmp_phy_vreg_l,
1868	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	1864	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1869	.regs = qmp_v4_usb3phy_regs_layout,	1865	.regs = qmp_v5_usb3phy_regs_layout,
1870	.pcs_usb_offset = 0x1000,	1866	.pcs_usb_offset = 0x1000,
1871		1867
1872	.has_pwrdn_delay = true,	1868	.has_pwrdn_delay = true,
@@ -1891,7 +1887,7 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { · 18 unmodified lines
1891	.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),	1887	.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1892	.vreg_list = qmp_phy_vreg_l,	1888	.vreg_list = qmp_phy_vreg_l,
1893	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	1889	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1894	.regs = qmp_v4_usb3phy_regs_layout,	1890	.regs = qmp_v5_usb3phy_regs_layout,
1895	.pcs_usb_offset = 0x300,	1891	.pcs_usb_offset = 0x300,
1896		1892
1897	.has_pwrdn_delay = true,	1893	.has_pwrdn_delay = true,
@@ -1917,7 +1913,7 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { · 19 unmodified lines
1917	.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),	1913	.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1918	.vreg_list = qmp_phy_vreg_l,	1914	.vreg_list = qmp_phy_vreg_l,
1919	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	1915	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1920	.regs = qmp_v4_usb3phy_regs_layout,	1916	.regs = qmp_v5_usb3phy_regs_layout,
1921	.pcs_usb_offset = 0x1000,	1917	.pcs_usb_offset = 0x1000,
1922		1918
1923	.has_pwrdn_delay = true,	1919	.has_pwrdn_delay = true,
@@ -1940,7 +1936,7 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { · 16 unmodified lines
1940	.num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),	1936	.num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1941	.vreg_list = qmp_phy_vreg_l,	1937	.vreg_list = qmp_phy_vreg_l,
1942	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),	1938	.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1943	.regs = qcm2290_usb3phy_regs_layout,	1939	.regs = qmp_v3_usb3phy_regs_layout,
1944	};	1940	};
1945		1941
1946	static void qmp_usb_configure_lane(void __iomem *base,	1942	static void qmp_usb_configure_lane(void __iomem *base,
@@ -2622,6 +2618,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = { · 675 unmodified lines
2622	}, {	2618	}, {
2623	.compatible = "qcom,sdx65-qmp-usb3-uni-phy",	2619	.compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2624	.data = &sdx65_usb3_uniphy_cfg,	2620	.data = &sdx65_usb3_uniphy_cfg,
		2621	}, {
		2622	.compatible = "qcom,sm6115-qmp-usb3-phy",
		2623	.data = &qcm2290_usb3phy_cfg,
2625	}, {	2624	}, {
2626	.compatible = "qcom,sm8150-qmp-usb3-phy",	2625	.compatible = "qcom,sm8150-qmp-usb3-phy",
2627	.data = &sm8150_usb3phy_cfg,	2626	.data = &sm8150_usb3phy_cfg,

drivers/phy/qualcomm/phy-qcom-qmp.h+12−11

 #include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
 #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
+#include "phy-qcom-qmp-qserdes-com-v6.h"
+#include "phy-qcom-qmp-qserdes-txrx-v6.h"
+#include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
+#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
 #include "phy-qcom-qmp-qserdes-pll.h"
 #include "phy-qcom-qmp-pcs-v2.h"
 #include "phy-qcom-qmp-pcs-v3.h"
-#include "phy-qcom-qmp-pcs-misc-v3.h"
-#include "phy-qcom-qmp-pcs-ufs-v3.h"
 #include "phy-qcom-qmp-pcs-v4.h"
-#include "phy-qcom-qmp-pcs-pcie-v4.h"
-#include "phy-qcom-qmp-pcs-usb-v4.h"
-#include "phy-qcom-qmp-pcs-ufs-v4.h"
 #include "phy-qcom-qmp-pcs-v4_20.h"
-#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
 #include "phy-qcom-qmp-pcs-v5.h"
 #include "phy-qcom-qmp-pcs-v5_20.h"
-#include "phy-qcom-qmp-pcs-pcie-v5.h"
-#include "phy-qcom-qmp-pcs-usb-v5.h"
-#include "phy-qcom-qmp-pcs-ufs-v5.h"
-#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
+#include "phy-qcom-qmp-pcs-v6.h"
-#include "phy-qcom-qmp-pcie-qhp.h"
+#include "phy-qcom-qmp-pcs-v6_20.h"
 /* Only for QMP V3 & V4 PHY - DP COM registers */
 #define QPHY_V3_DP_COM_PHY_MODE_CTRL			0x00
 #define QPHY_V4_PCS_MISC_TYPEC_STATUS			0x10
 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS		0x14
+/* Only for QMP V6 PHY - DP PHY registers */
+#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS		0x0e0
+#define QSERDES_V6_DP_PHY_STATUS			0x0e4
 #endif

drivers/phy/qualcomm/phy-qcom-snps-eusb2.c+441−0

@@ -0,0 +1,441 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2023, Linaro Limited
	4	*/
	5
	6	#include <linux/bitfield.h>
	7	#include <linux/clk.h>
	8	#include <linux/delay.h>
	9	#include <linux/iopoll.h>
	10	#include <linux/phy/phy.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/regulator/consumer.h>
	13	#include <linux/reset.h>
	14
	15	#define USB_PHY_UTMI_CTRL0 (0x3c)
	16	#define SLEEPM BIT(0)
	17	#define OPMODE_MASK GENMASK(4, 3)
	18	#define OPMODE_NONDRIVING BIT(3)
	19
	20	#define USB_PHY_UTMI_CTRL5 (0x50)
	21	#define POR BIT(1)
	22
	23	#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
	24	#define PHY_ENABLE BIT(0)
	25	#define SIDDQ_SEL BIT(1)
	26	#define SIDDQ BIT(2)
	27	#define RETENABLEN BIT(3)
	28	#define FSEL_MASK GENMASK(6, 4)
	29	#define FSEL_19_2_MHZ_VAL (0x0)
	30	#define FSEL_38_4_MHZ_VAL (0x4)
	31
	32	#define USB_PHY_CFG_CTRL_1 (0x58)
	33	#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1)
	34
	35	#define USB_PHY_CFG_CTRL_2 (0x5c)
	36	#define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0)
	37	#define DIV_7_0_19_2_MHZ_VAL (0x90)
	38	#define DIV_7_0_38_4_MHZ_VAL (0xc8)
	39
	40	#define USB_PHY_CFG_CTRL_3 (0x60)
	41	#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0)
	42	#define DIV_11_8_19_2_MHZ_VAL (0x1)
	43	#define DIV_11_8_38_4_MHZ_VAL (0x0)
	44
	45	#define PHY_CFG_PLL_REF_DIV GENMASK(7, 4)
	46	#define PLL_REF_DIV_VAL (0x0)
	47
	48	#define USB_PHY_HS_PHY_CTRL2 (0x64)
	49	#define VBUSVLDEXT0 BIT(0)
	50	#define USB2_SUSPEND_N BIT(2)
	51	#define USB2_SUSPEND_N_SEL BIT(3)
	52	#define VBUS_DET_EXT_SEL BIT(4)
	53
	54	#define USB_PHY_CFG_CTRL_4 (0x68)
	55	#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0)
	56	#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2)
	57
	58	#define USB_PHY_CFG_CTRL_5 (0x6c)
	59	#define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0)
	60	#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6)
	61
	62	#define USB_PHY_CFG_CTRL_6 (0x70)
	63	#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0)
	64
	65	#define USB_PHY_CFG_CTRL_7 (0x74)
	66
	67	#define USB_PHY_CFG_CTRL_8 (0x78)
	68	#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0)
	69	#define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2)
	70	#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3)
	71	#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6)
	72
	73	#define USB_PHY_CFG_CTRL_9 (0x7c)
	74	#define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0)
	75	#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3)
	76	#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5)
	77	#define PHY_CFG_RCAL_BYPASS BIT(7)
	78
	79	#define USB_PHY_CFG_CTRL_10 (0x80)
	80
	81	#define USB_PHY_CFG0 (0x94)
	82	#define DATAPATH_CTRL_OVERRIDE_EN BIT(0)
	83	#define CMN_CTRL_OVERRIDE_EN BIT(1)
	84
	85	#define UTMI_PHY_CMN_CTRL0 (0x98)
	86	#define TESTBURNIN BIT(6)
	87
	88	#define USB_PHY_FSEL_SEL (0xb8)
	89	#define FSEL_SEL BIT(0)
	90
	91	#define USB_PHY_APB_ACCESS_CMD (0x130)
	92	#define RW_ACCESS BIT(0)
	93	#define APB_START_CMD BIT(1)
	94	#define APB_LOGIC_RESET BIT(2)
	95
	96	#define USB_PHY_APB_ACCESS_STATUS (0x134)
	97	#define ACCESS_DONE BIT(0)
	98	#define TIMED_OUT BIT(1)
	99	#define ACCESS_ERROR BIT(2)
	100	#define ACCESS_IN_PROGRESS BIT(3)
	101
	102	#define USB_PHY_APB_ADDRESS (0x138)
	103	#define APB_REG_ADDR_MASK GENMASK(7, 0)
	104
	105	#define USB_PHY_APB_WRDATA_LSB (0x13c)
	106	#define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0)
	107
	108	#define USB_PHY_APB_WRDATA_MSB (0x140)
	109	#define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4)
	110
	111	#define USB_PHY_APB_RDDATA_LSB (0x144)
	112	#define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0)
	113
	114	#define USB_PHY_APB_RDDATA_MSB (0x148)
	115	#define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4)
	116
	117	static const char * const eusb2_hsphy_vreg_names[] = {
	118	"vdd", "vdda12",
	119	};
	120
	121	#define EUSB2_NUM_VREGS ARRAY_SIZE(eusb2_hsphy_vreg_names)
	122
	123	struct qcom_snps_eusb2_hsphy {
	124	struct phy *phy;
	125	void __iomem *base;
	126
	127	struct clk *ref_clk;
	128	struct reset_control *phy_reset;
	129
	130	struct regulator_bulk_data vregs[EUSB2_NUM_VREGS];
	131
	132	enum phy_mode mode;
	133
	134	struct phy *repeater;
	135	};
	136
	137	static int qcom_snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode)
	138	{
	139	struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
	140
	141	phy->mode = mode;
	142
	143	return phy_set_mode_ext(phy->repeater, mode, submode);
	144	}
	145
	146	static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset,
	147	u32 mask, u32 val)
	148	{
	149	u32 reg;
	150
	151	reg = readl_relaxed(base + offset);
	152	reg &= ~mask;
	153	reg \|= val & mask;
	154	writel_relaxed(reg, base + offset);
	155
	156	/* Ensure above write is completed */
	157	readl_relaxed(base + offset);
	158	}
	159
	160	static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_hsphy *phy)
	161	{
	162	/* default parameters: tx pre-emphasis */
	163	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
	164	PHY_CFG_TX_PREEMP_TUNE_MASK,
	165	FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0));
	166
	167	/* tx rise/fall time */
	168	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
	169	PHY_CFG_TX_RISE_TUNE_MASK,
	170	FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2));
	171
	172	/* source impedance adjustment */
	173	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
	174	PHY_CFG_TX_RES_TUNE_MASK,
	175	FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1));
	176
	177	/* dc voltage level adjustement */
	178	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8,
	179	PHY_CFG_TX_HS_VREF_TUNE_MASK,
	180	FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3));
	181
	182	/* transmitter HS crossover adjustement */
	183	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8,
	184	PHY_CFG_TX_HS_XV_TUNE_MASK,
	185	FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0));
	186	}
	187
	188	static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_hsphy *phy)
	189	{
	190	unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk);
	191
	192	switch (ref_clk_freq) {
	193	case 19200000:
	194	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
	195	FSEL_MASK,
	196	FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL));
	197
	198	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2,
	199	PHY_CFG_PLL_FB_DIV_7_0_MASK,
	200	DIV_7_0_19_2_MHZ_VAL);
	201
	202	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
	203	PHY_CFG_PLL_FB_DIV_11_8_MASK,
	204	DIV_11_8_19_2_MHZ_VAL);
	205	break;
	206
	207	case 38400000:
	208	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
	209	FSEL_MASK,
	210	FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL));
	211
	212	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2,
	213	PHY_CFG_PLL_FB_DIV_7_0_MASK,
	214	DIV_7_0_38_4_MHZ_VAL);
	215
	216	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
	217	PHY_CFG_PLL_FB_DIV_11_8_MASK,
	218	DIV_11_8_38_4_MHZ_VAL);
	219	break;
	220
	221	default:
	222	dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
	223	return -EINVAL;
	224	}
	225
	226	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
	227	PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL);
	228
	229	return 0;
	230	}
	231
	232	static int qcom_snps_eusb2_hsphy_init(struct phy *p)
	233	{
	234	struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
	235	int ret;
	236
	237	ret = regulator_bulk_enable(ARRAY_SIZE(phy->vregs), phy->vregs);
	238	if (ret)
	239	return ret;
	240
	241	ret = phy_init(phy->repeater);
	242	if (ret) {
	243	dev_err(&p->dev, "repeater init failed. %d\n", ret);
	244	goto disable_vreg;
	245	}
	246
	247	ret = clk_prepare_enable(phy->ref_clk);
	248	if (ret) {
	249	dev_err(&p->dev, "failed to enable ref clock, %d\n", ret);
	250	goto disable_vreg;
	251	}
	252
	253	ret = reset_control_assert(phy->phy_reset);
	254	if (ret) {
	255	dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret);
	256	goto disable_ref_clk;
	257	}
	258
	259	usleep_range(100, 150);
	260
	261	ret = reset_control_deassert(phy->phy_reset);
	262	if (ret) {
	263	dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret);
	264	goto disable_ref_clk;
	265	}
	266
	267	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG0,
	268	CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN);
	269
	270	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, POR);
	271
	272	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
	273	PHY_ENABLE \| RETENABLEN, PHY_ENABLE \| RETENABLEN);
	274
	275	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_APB_ACCESS_CMD,
	276	APB_LOGIC_RESET, APB_LOGIC_RESET);
	277
	278	qcom_snps_eusb2_hsphy_write_mask(phy->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0);
	279
	280	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_FSEL_SEL,
	281	FSEL_SEL, FSEL_SEL);
	282
	283	/* update ref_clk related registers */
	284	ret = qcom_eusb2_ref_clk_init(phy);
	285	if (ret)
	286	goto disable_ref_clk;
	287
	288	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_1,
	289	PHY_CFG_PLL_CPBIAS_CNTRL_MASK,
	290	FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1));
	291
	292	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4,
	293	PHY_CFG_PLL_INT_CNTRL_MASK,
	294	FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8));
	295
	296	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4,
	297	PHY_CFG_PLL_GMP_CNTRL_MASK,
	298	FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1));
	299
	300	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5,
	301	PHY_CFG_PLL_PROP_CNTRL_MASK,
	302	FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10));
	303
	304	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_6,
	305	PHY_CFG_PLL_VCO_CNTRL_MASK,
	306	FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0));
	307
	308	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5,
	309	PHY_CFG_PLL_VREF_TUNE_MASK,
	310	FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1));
	311
	312	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
	313	VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL);
	314
	315	/* set default parameters */
	316	qcom_eusb2_default_parameters(phy);
	317
	318	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
	319	USB2_SUSPEND_N_SEL \| USB2_SUSPEND_N,
	320	USB2_SUSPEND_N_SEL \| USB2_SUSPEND_N);
	321
	322	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM);
	323
	324	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
	325	SIDDQ_SEL, SIDDQ_SEL);
	326
	327	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
	328	SIDDQ, 0);
	329
	330	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, 0);
	331
	332	qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
	333	USB2_SUSPEND_N_SEL, 0);
	334
	335	return 0;
	336
	337	disable_ref_clk:
	338	clk_disable_unprepare(phy->ref_clk);
	339
	340	disable_vreg:
	341	regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
	342
	343	return ret;
	344	}
	345
	346	static int qcom_snps_eusb2_hsphy_exit(struct phy *p)
	347	{
	348	struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
	349
	350	clk_disable_unprepare(phy->ref_clk);
	351
	352	regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
	353
	354	phy_exit(phy->repeater);
	355
	356	return 0;
	357	}
	358
	359	static const struct phy_ops qcom_snps_eusb2_hsphy_ops = {
	360	.init = qcom_snps_eusb2_hsphy_init,
	361	.exit = qcom_snps_eusb2_hsphy_exit,
	362	.set_mode = qcom_snps_eusb2_hsphy_set_mode,
	363	.owner = THIS_MODULE,
	364	};
	365
	366	static int qcom_snps_eusb2_hsphy_probe(struct platform_device *pdev)
	367	{
	368	struct device *dev = &pdev->dev;
	369	struct device_node *np = dev->of_node;
	370	struct qcom_snps_eusb2_hsphy *phy;
	371	struct phy_provider *phy_provider;
	372	struct phy *generic_phy;
	373	int ret, i;
	374	int num;
	375
	376	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
	377	if (!phy)
	378	return -ENOMEM;
	379
	380	phy->base = devm_platform_ioremap_resource(pdev, 0);
	381	if (IS_ERR(phy->base))
	382	return PTR_ERR(phy->base);
	383
	384	phy->phy_reset = devm_reset_control_get_exclusive(dev, NULL);
	385	if (IS_ERR(phy->phy_reset))
	386	return PTR_ERR(phy->phy_reset);
	387
	388	phy->ref_clk = devm_clk_get(dev, "ref");
	389	if (IS_ERR(phy->ref_clk))
	390	return dev_err_probe(dev, PTR_ERR(phy->ref_clk),
	391	"failed to get ref clk\n");
	392
	393	num = ARRAY_SIZE(phy->vregs);
	394	for (i = 0; i < num; i++)
	395	phy->vregs[i].supply = eusb2_hsphy_vreg_names[i];
	396
	397	ret = devm_regulator_bulk_get(dev, num, phy->vregs);
	398	if (ret)
	399	return dev_err_probe(dev, ret,
	400	"failed to get regulator supplies\n");
	401
	402	phy->repeater = devm_of_phy_get_by_index(dev, np, 0);
	403	if (IS_ERR(phy->repeater))
	404	return dev_err_probe(dev, PTR_ERR(phy->repeater),
	405	"failed to get repeater\n");
	406
	407	generic_phy = devm_phy_create(dev, NULL, &qcom_snps_eusb2_hsphy_ops);
	408	if (IS_ERR(generic_phy)) {
	409	dev_err(dev, "failed to create phy %d\n", ret);
	410	return PTR_ERR(generic_phy);
	411	}
	412
	413	dev_set_drvdata(dev, phy);
	414	phy_set_drvdata(generic_phy, phy);
	415
	416	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	417	if (IS_ERR(phy_provider))
	418	return PTR_ERR(phy_provider);
	419
	420	dev_info(dev, "Registered Qcom-eUSB2 phy\n");
	421
	422	return 0;
	423	}
	424
	425	static const struct of_device_id qcom_snps_eusb2_hsphy_of_match_table[] = {
	426	{ .compatible = "qcom,sm8550-snps-eusb2-phy", },
	427	{ },
	428	};
	429	MODULE_DEVICE_TABLE(of, qcom_snps_eusb2_hsphy_of_match_table);
	430
	431	static struct platform_driver qcom_snps_eusb2_hsphy_driver = {
	432	.probe = qcom_snps_eusb2_hsphy_probe,
	433	.driver = {
	434	.name = "qcom-snps-eusb2-hsphy",
	435	.of_match_table = qcom_snps_eusb2_hsphy_of_match_table,
	436	},
	437	};
	438
	439	module_platform_driver(qcom_snps_eusb2_hsphy_driver);
	440	MODULE_DESCRIPTION("Qualcomm SNPS eUSB2 HS PHY driver");
	441	MODULE_LICENSE("GPL");

drivers/phy/renesas/r8a779f0-ether-serdes.c+30−35

 #define R8A779F0_ETH_SERDES_BANK_SELECT		0x03fc
 #define R8A779F0_ETH_SERDES_TIMEOUT_US		100000
 #define R8A779F0_ETH_SERDES_NUM_RETRY_LINKUP	3
-#define R8A779F0_ETH_SERDES_NUM_RETRY_INIT	3
 struct r8a779f0_eth_serdes_drv_data;
 struct r8a779f0_eth_serdes_channel {
 	if (ret)
 		return ret;
-	ret = r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0);
+	return r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0);
+}
+static int r8a779f0_eth_serdes_init(struct phy *p)
+{
+	struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
+	int ret;
+	ret = r8a779f0_eth_serdes_hw_init(channel);
+	if (!ret)
+		channel->dd->initialized = true;
+	return ret;
+}
+static int r8a779f0_eth_serdes_hw_init_late(struct r8a779f0_eth_serdes_channel
+*channel)
+{
+	int ret;
+	ret = r8a779f0_eth_serdes_chan_setting(channel);
 	if (ret)
 		return ret;
-	for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
+	ret = r8a779f0_eth_serdes_chan_speed(channel);
-		ret = r8a779f0_eth_serdes_chan_setting(&dd->channel[i]);
+	if (ret)
-		if (ret)
+		return ret;
-			return ret;
-	}
-	for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
-		ret = r8a779f0_eth_serdes_chan_speed(&dd->channel[i]);
-		if (ret)
-			return ret;
-	}
-	for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
+	r8a779f0_eth_serdes_write32(channel->addr, 0x03c0, 0x380, 0x0000);
-		r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03c0, 0x380, 0x0000);
-	for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
-		r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0000);
-	for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
+	r8a779f0_eth_serdes_write32(channel->addr, 0x03d0, 0x380, 0x0000);
-		ret = r8a779f0_eth_serdes_monitor_linkup(&dd->channel[i]);
-		if (ret)
-			return ret;
-	}
-	return 0;
+	return r8a779f0_eth_serdes_monitor_linkup(channel);
 }
-static int r8a779f0_eth_serdes_init(struct phy *p)
+static int r8a779f0_eth_serdes_power_on(struct phy *p)
 {
 	struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
-	int i, ret;
-	for (i = 0; i < R8A779F0_ETH_SERDES_NUM_RETRY_INIT; i++) {
+	return r8a779f0_eth_serdes_hw_init_late(channel);
-		ret = r8a779f0_eth_serdes_hw_init(channel);
-		if (!ret) {
-			channel->dd->initialized = true;
-			break;
-		}
-		usleep_range(1000, 2000);
-	}
-	return ret;
 }
 static int r8a779f0_eth_serdes_set_mode(struct phy *p, enum phy_mode mode,
 static const struct phy_ops r8a779f0_eth_serdes_ops = {
 	.init		= r8a779f0_eth_serdes_init,
+	.power_on	= r8a779f0_eth_serdes_power_on,
 	.set_mode	= r8a779f0_eth_serdes_set_mode,
 	.set_speed	= r8a779f0_eth_serdes_set_speed,
 };

drivers/phy/rockchip/phy-rockchip-typec.c+3−4

 	struct extcon_dev *edev = tcphy->extcon;
 	union extcon_property_value property;
 	unsigned int id;
-	bool ufp, dp;
 	u8 mode;
-	int ret;
+	int ret, ufp, dp;
 	if (!edev)
 		return MODE_DFP_USB;
 	mode = MODE_DFP_USB;
 	id = EXTCON_USB_HOST;
-	if (ufp) {
+	if (ufp > 0) {
 		mode = MODE_UFP_USB;
 		id = EXTCON_USB;
-	} else if (dp) {
+	} else if (dp > 0) {
 		mode = MODE_DFP_DP;
 		id = EXTCON_DISP_DP;

drivers/phy/tegra/xusb.c+17−0

@@ -718,6 +718,22 @@ static int tegra_xusb_setup_usb_role_switch(struct tegra_xusb_port *port) · 717 unmodified lines
718	return err;	718	return err;
719	}	719	}
720		720
		721	static void tegra_xusb_parse_usb_role_default_mode(struct tegra_xusb_port *port)
		722	{
		723	enum usb_role role = USB_ROLE_NONE;
		724	enum usb_dr_mode mode = usb_get_role_switch_default_mode(&port->dev);
		725
		726	if (mode == USB_DR_MODE_HOST)
		727	role = USB_ROLE_HOST;
		728	else if (mode == USB_DR_MODE_PERIPHERAL)
		729	role = USB_ROLE_DEVICE;
		730
		731	if (role != USB_ROLE_NONE) {
		732	usb_role_switch_set_role(port->usb_role_sw, role);
		733	dev_dbg(&port->dev, "usb role default mode is %s", modes[mode]);
		734	}
		735	}
		736
721	static int tegra_xusb_usb2_port_parse_dt(struct tegra_xusb_usb2_port *usb2)	737	static int tegra_xusb_usb2_port_parse_dt(struct tegra_xusb_usb2_port *usb2)
722	{	738	{
723	struct tegra_xusb_port *port = &usb2->base;	739	struct tegra_xusb_port *port = &usb2->base;
@@ -747,6 +763,7 @@ static int tegra_xusb_usb2_port_parse_dt(struct tegra_xusb_usb2_port *usb2) · 23 unmodified lines
747	err = tegra_xusb_setup_usb_role_switch(port);	763	err = tegra_xusb_setup_usb_role_switch(port);
748	if (err < 0)	764	if (err < 0)
749	return err;	765	return err;
		766	tegra_xusb_parse_usb_role_default_mode(port);
750	} else {	767	} else {
751	dev_err(&port->dev, "usb-role-switch not found for %s mode",	768	dev_err(&port->dev, "usb-role-switch not found for %s mode",
752	modes[usb2->mode]);	769	modes[usb2->mode]);

drivers/phy/ti/phy-j721e-wiz.c+56−10

@@ -58,6 +58,14 @@ enum wiz_lane_standard_mode { · 57 unmodified lines
58	LANE_MODE_GEN4,	58	LANE_MODE_GEN4,
59	};	59	};
60		60
		61	/*
		62	* List of master lanes used for lane swapping
		63	*/
		64	enum wiz_typec_master_lane {
		65	LANE0 = 0,
		66	LANE2 = 2,
		67	};
		68
61	enum wiz_refclk_mux_sel {	69	enum wiz_refclk_mux_sel {
62	PLL0_REFCLK,	70	PLL0_REFCLK,
63	PLL1_REFCLK,	71	PLL1_REFCLK,
@@ -194,6 +202,9 @@ static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { · 130 unmodified lines
194	static const struct reg_field typec_ln10_swap =	202	static const struct reg_field typec_ln10_swap =
195	REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);	203	REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
196		204
		205	static const struct reg_field typec_ln23_swap =
		206	REG_FIELD(WIZ_SERDES_TYPEC, 31, 31);
		207
197	struct wiz_clk_mux {	208	struct wiz_clk_mux {
198	struct clk_hw hw;	209	struct clk_hw hw;
199	struct regmap_field *field;	210	struct regmap_field *field;
@@ -367,6 +378,7 @@ struct wiz { · 167 unmodified lines
367	struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];	378	struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
368	struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];	379	struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
369	struct regmap_field *typec_ln10_swap;	380	struct regmap_field *typec_ln10_swap;
		381	struct regmap_field *typec_ln23_swap;
370	struct regmap_field *sup_legacy_clk_override;	382	struct regmap_field *sup_legacy_clk_override;
371		383
372	struct device *dev;	384	struct device *dev;
@@ -376,6 +388,7 @@ struct wiz { · 3 unmodified lines
376	struct gpio_desc *gpio_typec_dir;	388	struct gpio_desc *gpio_typec_dir;
377	int typec_dir_delay;	389	int typec_dir_delay;
378	u32 lane_phy_type[WIZ_MAX_LANES];	390	u32 lane_phy_type[WIZ_MAX_LANES];
		391	u32 master_lane_num[WIZ_MAX_LANES];
379	struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];	392	struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
380	struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS];	393	struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
381	struct clk_onecell_data clk_data;	394	struct clk_onecell_data clk_data;
@@ -675,6 +688,13 @@ static int wiz_regfield_init(struct wiz *wiz) · 293 unmodified lines
675	return PTR_ERR(wiz->typec_ln10_swap);	688	return PTR_ERR(wiz->typec_ln10_swap);
676	}	689	}
677		690
		691	wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,
		692	typec_ln23_swap);
		693	if (IS_ERR(wiz->typec_ln23_swap)) {
		694	dev_err(dev, "LN23_SWAP reg field init failed\n");
		695	return PTR_ERR(wiz->typec_ln23_swap);
		696	}
		697
678	wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);	698	wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
679	if (IS_ERR(wiz->phy_en_refclk)) {	699	if (IS_ERR(wiz->phy_en_refclk)) {
680	dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");	700	dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
@@ -1234,15 +1254,39 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, · 553 unmodified lines
1234	struct wiz *wiz = dev_get_drvdata(dev);	1254	struct wiz *wiz = dev_get_drvdata(dev);
1235	int ret;	1255	int ret;
1236		1256
1237	/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */	1257	if (id == 0) {
1238	if (id == 0 && wiz->gpio_typec_dir) {	1258	/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
1239	if (wiz->typec_dir_delay)	1259	if (wiz->gpio_typec_dir) {
1240	msleep_interruptible(wiz->typec_dir_delay);	1260	if (wiz->typec_dir_delay)
1241		1261	msleep_interruptible(wiz->typec_dir_delay);
1242	if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))	1262
1243	regmap_field_write(wiz->typec_ln10_swap, 1);	1263	if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1244	else	1264	regmap_field_write(wiz->typec_ln10_swap, 1);
1245	regmap_field_write(wiz->typec_ln10_swap, 0);	1265	else
		1266	regmap_field_write(wiz->typec_ln10_swap, 0);
		1267	} else {
		1268	/* if no typec-dir gpio is specified and PHY type is USB3
		1269	* with master lane number is '0' or '2', then set LN10 or
		1270	* LN23 SWAP bit to '1' respectively.
		1271	*/
		1272	u32 num_lanes = wiz->num_lanes;
		1273	int i;
		1274
		1275	for (i = 0; i < num_lanes; i++) {
		1276	if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
		1277	switch (wiz->master_lane_num[i]) {
		1278	case LANE0:
		1279	regmap_field_write(wiz->typec_ln10_swap, 1);
		1280	break;
		1281	case LANE2:
		1282	regmap_field_write(wiz->typec_ln23_swap, 1);
		1283	break;
		1284	default:
		1285	break;
		1286	}
		1287	}
		1288	}
		1289	}
1246	}	1290	}
1247		1291
1248	if (id == 0) {	1292	if (id == 0) {
@@ -1386,8 +1430,10 @@ static int wiz_get_lane_phy_types(struct device dev, struct wiz wiz) · 137 unmodified lines
1386	dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,	1430	dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
1387	reg, reg + num_lanes - 1, phy_type);	1431	reg, reg + num_lanes - 1, phy_type);
1388		1432
1389	for (i = reg; i < reg + num_lanes; i++)	1433	for (i = reg; i < reg + num_lanes; i++) {
		1434	wiz->master_lane_num[i] = reg;
1390	wiz->lane_phy_type[i] = phy_type;	1435	wiz->lane_phy_type[i] = phy_type;
		1436	}
1391	}	1437	}
1392		1438
1393	return 0;	1439	return 0;

drivers/usb/host/ehci-exynos.c+6−17

 			return -EINVAL;
 		}
-		phy = devm_of_phy_get(dev, child, NULL);
+		phy = devm_of_phy_optional_get(dev, child, NULL);
 		exynos_ehci->phy[phy_number] = phy;
 		if (IS_ERR(phy)) {
-			ret = PTR_ERR(phy);
+			of_node_put(child);
-			if (ret == -EPROBE_DEFER) {
+			return PTR_ERR(phy);
-				of_node_put(child);
-				return ret;
-			} else if (ret != -ENOSYS && ret != -ENODEV) {
-				dev_err(dev,
-					"Error retrieving usb2 phy: %d\n", ret);
-				of_node_put(child);
-				return ret;
-			}
 		}
 	}
 	int ret = 0;
 	for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
-		if (!IS_ERR(exynos_ehci->phy[i]))
+		ret = phy_power_on(exynos_ehci->phy[i]);
-			ret = phy_power_on(exynos_ehci->phy[i]);
 	if (ret)
 		for (i--; i >= 0; i--)
-			if (!IS_ERR(exynos_ehci->phy[i]))
+			phy_power_off(exynos_ehci->phy[i]);
-				phy_power_off(exynos_ehci->phy[i]);
 	return ret;
 }
 	int i;
 	for (i = 0; i < PHY_NUMBER; i++)
-		if (!IS_ERR(exynos_ehci->phy[i]))
+		phy_power_off(exynos_ehci->phy[i]);
-			phy_power_off(exynos_ehci->phy[i]);
 }
 static void exynos_setup_vbus_gpio(struct device *dev)

drivers/usb/host/ohci-exynos.c+6−17

 			return -EINVAL;
 		}
-		phy = devm_of_phy_get(dev, child, NULL);
+		phy = devm_of_phy_optional_get(dev, child, NULL);
 		exynos_ohci->phy[phy_number] = phy;
 		if (IS_ERR(phy)) {
-			ret = PTR_ERR(phy);
+			of_node_put(child);
-			if (ret == -EPROBE_DEFER) {
+			return PTR_ERR(phy);
-				of_node_put(child);
-				return ret;
-			} else if (ret != -ENOSYS && ret != -ENODEV) {
-				dev_err(dev,
-					"Error retrieving usb2 phy: %d\n", ret);
-				of_node_put(child);
-				return ret;
-			}
 		}
 	}
 	int ret = 0;
 	for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
-		if (!IS_ERR(exynos_ohci->phy[i]))
+		ret = phy_power_on(exynos_ohci->phy[i]);
-			ret = phy_power_on(exynos_ohci->phy[i]);
 	if (ret)
 		for (i--; i >= 0; i--)
-			if (!IS_ERR(exynos_ohci->phy[i]))
+			phy_power_off(exynos_ohci->phy[i]);
-				phy_power_off(exynos_ohci->phy[i]);
 	return ret;
 }
 	int i;
 	for (i = 0; i < PHY_NUMBER; i++)
-		if (!IS_ERR(exynos_ohci->phy[i]))
+		phy_power_off(exynos_ohci->phy[i]);
-			phy_power_off(exynos_ohci->phy[i]);
 }
 static int exynos_ohci_probe(struct platform_device *pdev)

include/linux/phy/phy.h+9−7

 	phy->attrs.bus_width = bus_width;
 }
 struct phy *phy_get(struct device *dev, const char *string);
-struct phy *phy_optional_get(struct device *dev, const char *string);
 struct phy *devm_phy_get(struct device *dev, const char *string);
 struct phy *devm_phy_optional_get(struct device *dev, const char *string);
 struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
 			    const char *con_id);
+struct phy *devm_of_phy_optional_get(struct device *dev, struct device_node *np,
+				     const char *con_id);
 struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np,
 				     int index);
 void of_phy_put(struct phy *phy);
 	return ERR_PTR(-ENOSYS);
 }
-static inline struct phy *phy_optional_get(struct device *dev,
-					   const char *string)
-{
-	return ERR_PTR(-ENOSYS);
-}
 static inline struct phy *devm_phy_get(struct device *dev, const char *string)
 {
 	return ERR_PTR(-ENOSYS);
 	return ERR_PTR(-ENOSYS);
 }
+static inline struct phy *devm_of_phy_optional_get(struct device *dev,
+						   struct device_node *np,
+						   const char *con_id)
+{
+	return NULL;
+}
 static inline struct phy *devm_of_phy_get_by_index(struct device *dev,
 						   struct device_node *np,
 						   int index)

Merge tag 'phy-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Keyboard shortcuts

General

Issues and pull requests

Issues, pull requests and Inbox

Repository code