Not all chipsets have an internal buffer delaying the visibility of writes via the GGTT being visible by other physical paths, but we use a very heavy workaround for all. We only need to apply that workarounds to the chipsets we know suffer from the delay and the resulting coherency issue. Similarly, the same inconsistent coherency fouls up our ABI promise that a write into a mmap_gtt is immediately visible to others. Since the HW has made that a lie, let userspace know when that contract is broken. (Not that userspace would want to use mmap_gtt on those chipsets for other performance reasons...)
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| @@ -529,6 +529,28 @@ typedef struct drm_i915_irq_wait { · 528 unmodified lines | ||
| 529 | 529 | */ |
| 530 | 530 | #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 |
| 531 | 531 | |
| 532 | +/* | |
| 533 | + * Once upon a time we supposed that writes through the GGTT would be | |
| 534 | + * immediately in physical memory (once flushed out of the CPU path). However, | |
| 535 | + * on a few different processors and chipsets, this is not necessarily the case | |
| 536 | + * as the writes appear to be buffered internally. Thus a read of the backing | |
| 537 | + * storage (physical memory) via a different path (with different physical tags | |
| 538 | + * to the indirect write via the GGTT) will see stale values from before | |
| 539 | + * the GGTT write. Inside the kernel, we can for the most part keep track of | |
| 540 | + * the different read/write domains in use (e.g. set-domain), but the assumption | |
| 541 | + * of coherency is baked into the ABI, hence reporting its true state in this | |
| 542 | + * parameter. | |
| 543 | + * | |
| 544 | + * Reports true when writes via mmap_gtt are immediately visible following an | |
| 545 | + * lfence to flush the WCB. | |
| 546 | + * | |
| 547 | + * Reports false when writes via mmap_gtt are indeterminately delayed in an in | |
| 548 | + * internal buffer and are _not_ immediately visible to third parties accessing | |
| 549 | + * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC | |
| 550 | + * communications channel when reporting false is strongly disadvised. | |
| 551 | + */ | |
| 552 | +#define I915_PARAM_MMAP_GTT_COHERENT 52 | |
| 553 | + | |
| 532 | 554 | typedef struct drm_i915_getparam { |
| 533 | 555 | __s32 param; |
| 534 | 556 | /* |