DG2 clear color render compression uses Tile4 layout. Therefore, we need to define a new format modifier for uAPI to support clear color rendering. v2: Display version is fixed. [Imre] KDoc is enhanced for cc modifier. [Nanley & Lionel] v3: Split out the modifier addition to a separate patch. Clarify the modifier layout description.
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| @@ -605,6 +605,20 @@ extern "C" { · 604 unmodified lines | ||
| 605 | 605 | */ |
| 606 | 606 | #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) |
| 607 | 607 | |
| 608 | +/* | |
| 609 | + * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. | |
| 610 | + * | |
| 611 | + * The main surface is Tile 4 and at plane index 0. The CCS data is stored | |
| 612 | + * outside of the GEM object in a reserved memory area dedicated for the | |
| 613 | + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The | |
| 614 | + * main surface pitch is required to be a multiple of four Tile 4 widths. The | |
| 615 | + * clear color is stored at plane index 1 and the pitch should be ignored. The | |
| 616 | + * format of the 256 bits of clear color data matches the one used for the | |
| 617 | + * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description | |
| 618 | + * for details. | |
| 619 | + */ | |
| 620 | +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) | |
| 621 | + | |
| 608 | 622 | /* |
| 609 | 623 | * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks |
| 610 | 624 | * |