Pull drm updates from Dave Airlie: "This is the main drm pull request for 4.14 merge window. I'm sending this early, as my continuing journey into fatherhood is occurring really soon now, I'm going to be mostly useless for the next couple of weeks, though I may be able to read email, I doubt I'll be doing much patch applications or git sending. If anything urgent pops up I've asked Daniel/Jani/Alex/Sean to try and direct stuff towards you. Outside drm changes: Some rcar-du updates that touch the V4L tree, all acks should be in place. It adds one export to the radix tree code for new i915 use case. There are some minor AGP cleanups (don't see that too often). Changes to the vbox driver in staging to avoid breaking compilation. Summary: core: - Atomic helper fixes - Atomic UAPI fixes - Add YCBCR 4:2:0 support - Drop set_busid hook - Refactor fb_helper locking - Remove a bunch of internal APIs - Add a bunch of better default handlers - Format modifier/blob plane property added - More internal header refactoring - Make more internal API names consistent - Enhanced syncobj APIs (wait/signal/reset/create signalled) bridge: - Add Synopsys Designware MIPI DSI host bridge driver tiny: - Add Pervasive Displays RePaper displays - Add support for LEGO MINDSTORMS EV3 LCD i915: - Lots of GEN10/CNL support patches - drm syncobj support - Skylake+ watermark refactoring - GVT vGPU 48-bit ppgtt support - GVT performance improvements - NOA change ioctl - CCS (color compression) scanout support - GPU reset improvements amdgpu: - Initial hugepage support - BO migration logic rework - Vega10 improvements - Powerplay fixes - Stop reprogramming the MC - Fixes for ACP audio on stoney - SR-IOV fixes/improvements - Command submission overhead improvements amdkfd: - Non-dGPU upstreaming patches - Scratch VA ioctl - Image tiling modes - Update PM4 headers for new firmware - Drop all BUG_ONs. nouveau: - GP108 modesetting support. - Disable MSI on big endian. vmwgfx: - Add fence fd support. msm: - Runtime PM improvements exynos: - NV12MT support - Refactor KMS drivers imx-drm: - Lock scanout channel to improve memory bw - Cleanups etnaviv: - GEM object population fixes tegra: - Prep work for Tegra186 support - PRIME mmap support sunxi: - HDMI support improvements - HDMI CEC support omapdrm: - HDMI hotplug IRQ support - Big driver cleanup - OMAP5 DSI support rcar-du: - vblank fixes - VSP1 updates arcgpu: - Minor fixes stm: - Add STM32 DSI controller driver dw_hdmi: - Add support for Rockchip RK3399 - HDMI CEC support atmel-hlcdc: - Add 8-bit color support vc4: - Atomic fixes - New ioctl to attach a label to a buffer object - HDMI CEC support - Allow userspace to dictate rendering order on submit ioctl" * tag 'drm-for-v4.14' of git://people.freedesktop.org/~airlied/linux: (1074 commits) drm/syncobj: Add a signal ioctl (v3) drm/syncobj: Add a reset ioctl (v3) drm/syncobj: Add a syncobj_array_find helper drm/syncobj: Allow wait for submit and signal behavior (v5) drm/syncobj: Add a CREATE_SIGNALED flag drm/syncobj: Add a callback mechanism for replace_fence (v3) drm/syncobj: add sync obj wait interface. (v8) i915: Use drm_syncobj_fence_get drm/syncobj: Add a race-free drm_syncobj_fence_get helper (v2) drm/syncobj: Rename fence_get to find_fence drm: kirin: Add mode_valid logic to avoid mode clocks we can't generate drm/vmwgfx: Bump the version for fence FD support drm/vmwgfx: Add export fence to file descriptor support drm/vmwgfx: Add support for imported Fence File Descriptor drm/vmwgfx: Prepare to support fence fd drm/vmwgfx: Fix incorrect command header offset at restart drm/vmwgfx: Support the NOP_ERROR command drm/vmwgfx: Restart command buffers after errors drm/vmwgfx: Move irq bottom half processing to threads drm/vmwgfx: Don't use drm_irq_[un]install ...
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| @@ -23,27 +23,27 @@ extern "C" { · 22 unmodified lines | |||
| 23 | DRM_##dir(DRM_COMMAND_BASE + DRM_ARMADA_##name, struct drm_armada_##str) | 23 | DRM_##dir(DRM_COMMAND_BASE + DRM_ARMADA_##name, struct drm_armada_##str) |
| 24 | 24 | ||
| 25 | struct drm_armada_gem_create { | 25 | struct drm_armada_gem_create { |
| 26 | uint32_t handle; | 26 | __u32 handle; |
| 27 | uint32_t size; | 27 | __u32 size; |
| 28 | }; | 28 | }; |
| 29 | #define DRM_IOCTL_ARMADA_GEM_CREATE \ | 29 | #define DRM_IOCTL_ARMADA_GEM_CREATE \ |
| 30 | ARMADA_IOCTL(IOWR, GEM_CREATE, gem_create) | 30 | ARMADA_IOCTL(IOWR, GEM_CREATE, gem_create) |
| 31 | 31 | ||
| 32 | struct drm_armada_gem_mmap { | 32 | struct drm_armada_gem_mmap { |
| 33 | uint32_t handle; | 33 | __u32 handle; |
| 34 | uint32_t pad; | 34 | __u32 pad; |
| 35 | uint64_t offset; | 35 | __u64 offset; |
| 36 | uint64_t size; | 36 | __u64 size; |
| 37 | uint64_t addr; | 37 | __u64 addr; |
| 38 | }; | 38 | }; |
| 39 | #define DRM_IOCTL_ARMADA_GEM_MMAP \ | 39 | #define DRM_IOCTL_ARMADA_GEM_MMAP \ |
| 40 | ARMADA_IOCTL(IOWR, GEM_MMAP, gem_mmap) | 40 | ARMADA_IOCTL(IOWR, GEM_MMAP, gem_mmap) |
| 41 | 41 | ||
| 42 | struct drm_armada_gem_pwrite { | 42 | struct drm_armada_gem_pwrite { |
| 43 | uint64_t ptr; | 43 | __u64 ptr; |
| 44 | uint32_t handle; | 44 | __u32 handle; |
| 45 | uint32_t offset; | 45 | __u32 offset; |
| 46 | uint32_t size; | 46 | __u32 size; |
| 47 | }; | 47 | }; |
| 48 | #define DRM_IOCTL_ARMADA_GEM_PWRITE \ | 48 | #define DRM_IOCTL_ARMADA_GEM_PWRITE \ |
| 49 | ARMADA_IOCTL(IOW, GEM_PWRITE, gem_pwrite) | 49 | ARMADA_IOCTL(IOW, GEM_PWRITE, gem_pwrite) |
| @@ -700,6 +700,7 @@ struct drm_prime_handle { · 699 unmodified lines | |||
| 700 | 700 | ||
| 701 | struct drm_syncobj_create { | 701 | struct drm_syncobj_create { |
| 702 | __u32 handle; | 702 | __u32 handle; |
| 703 | #define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0) | ||
| 703 | __u32 flags; | 704 | __u32 flags; |
| 704 | }; | 705 | }; |
| 705 | 706 | ||
| @@ -718,6 +719,24 @@ struct drm_syncobj_handle { · 12 unmodified lines | |||
| 718 | __u32 pad; | 719 | __u32 pad; |
| 719 | }; | 720 | }; |
| 720 | 721 | ||
| 722 | #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) | ||
| 723 | #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) | ||
| 724 | struct drm_syncobj_wait { | ||
| 725 | __u64 handles; | ||
| 726 | /* absolute timeout */ | ||
| 727 | __s64 timeout_nsec; | ||
| 728 | __u32 count_handles; | ||
| 729 | __u32 flags; | ||
| 730 | __u32 first_signaled; /* only valid when not waiting all */ | ||
| 731 | __u32 pad; | ||
| 732 | }; | ||
| 733 | |||
| 734 | struct drm_syncobj_array { | ||
| 735 | __u64 handles; | ||
| 736 | __u32 count_handles; | ||
| 737 | __u32 pad; | ||
| 738 | }; | ||
| 739 | |||
| 721 | #if defined(__cplusplus) | 740 | #if defined(__cplusplus) |
| 722 | } | 741 | } |
| 723 | #endif | 742 | #endif |
| @@ -840,6 +859,9 @@ extern "C" { · 116 unmodified lines | |||
| 840 | #define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) | 859 | #define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) |
| 841 | #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) | 860 | #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) |
| 842 | #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) | 861 | #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) |
| 862 | #define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) | ||
| 863 | #define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) | ||
| 864 | #define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) | ||
| 843 | 865 | ||
| 844 | /** | 866 | /** |
| 845 | * Device specific ioctls should only be in their respective headers | 867 | * Device specific ioctls should only be in their respective headers |
| @@ -185,6 +185,8 @@ extern "C" { · 184 unmodified lines | |||
| 185 | #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 | 185 | #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 |
| 186 | /* add more to the end as needed */ | 186 | /* add more to the end as needed */ |
| 187 | 187 | ||
| 188 | #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) | ||
| 189 | |||
| 188 | #define fourcc_mod_code(vendor, val) \ | 190 | #define fourcc_mod_code(vendor, val) \ |
| 189 | ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) | 191 | ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) |
| 190 | 192 | ||
| @@ -196,6 +198,15 @@ extern "C" { · 5 unmodified lines | |||
| 196 | * authoritative source for all of these. | 198 | * authoritative source for all of these. |
| 197 | */ | 199 | */ |
| 198 | 200 | ||
| 201 | /* | ||
| 202 | * Invalid Modifier | ||
| 203 | * | ||
| 204 | * This modifier can be used as a sentinel to terminate the format modifiers | ||
| 205 | * list, or to initialize a variable with an invalid modifier. It might also be | ||
| 206 | * used to report an error back to userspace for certain APIs. | ||
| 207 | */ | ||
| 208 | #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) | ||
| 209 | |||
| 199 | /* | 210 | /* |
| 200 | * Linear Layout | 211 | * Linear Layout |
| 201 | * | 212 | * |
| @@ -252,6 +263,26 @@ extern "C" { · 50 unmodified lines | |||
| 252 | */ | 263 | */ |
| 253 | #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) | 264 | #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) |
| 254 | 265 | ||
| 266 | /* | ||
| 267 | * Intel color control surface (CCS) for render compression | ||
| 268 | * | ||
| 269 | * The framebuffer format must be one of the 8:8:8:8 RGB formats. | ||
| 270 | * The main surface will be plane index 0 and must be Y/Yf-tiled, | ||
| 271 | * the CCS will be plane index 1. | ||
| 272 | * | ||
| 273 | * Each CCS tile matches a 1024x512 pixel area of the main surface. | ||
| 274 | * To match certain aspects of the 3D hardware the CCS is | ||
| 275 | * considered to be made up of normal 128Bx32 Y tiles, Thus | ||
| 276 | * the CCS pitch must be specified in multiples of 128 bytes. | ||
| 277 | * | ||
| 278 | * In reality the CCS tile appears to be a 64Bx64 Y tile, composed | ||
| 279 | * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. | ||
| 280 | * But that fact is not relevant unless the memory is accessed | ||
| 281 | * directly. | ||
| 282 | */ | ||
| 283 | #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) | ||
| 284 | #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) | ||
| 285 | |||
| 255 | /* | 286 | /* |
| 256 | * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks | 287 | * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks |
| 257 | * | 288 | * |
| @@ -712,6 +712,56 @@ struct drm_mode_atomic { · 711 unmodified lines | |||
| 712 | __u64 user_data; | 712 | __u64 user_data; |
| 713 | }; | 713 | }; |
| 714 | 714 | ||
| 715 | struct drm_format_modifier_blob { | ||
| 716 | #define FORMAT_BLOB_CURRENT 1 | ||
| 717 | /* Version of this blob format */ | ||
| 718 | __u32 version; | ||
| 719 | |||
| 720 | /* Flags */ | ||
| 721 | __u32 flags; | ||
| 722 | |||
| 723 | /* Number of fourcc formats supported */ | ||
| 724 | __u32 count_formats; | ||
| 725 | |||
| 726 | /* Where in this blob the formats exist (in bytes) */ | ||
| 727 | __u32 formats_offset; | ||
| 728 | |||
| 729 | /* Number of drm_format_modifiers */ | ||
| 730 | __u32 count_modifiers; | ||
| 731 | |||
| 732 | /* Where in this blob the modifiers exist (in bytes) */ | ||
| 733 | __u32 modifiers_offset; | ||
| 734 | |||
| 735 | /* __u32 formats[] */ | ||
| 736 | /* struct drm_format_modifier modifiers[] */ | ||
| 737 | }; | ||
| 738 | |||
| 739 | struct drm_format_modifier { | ||
| 740 | /* Bitmask of formats in get_plane format list this info applies to. The | ||
| 741 | * offset allows a sliding window of which 64 formats (bits). | ||
| 742 | * | ||
| 743 | * Some examples: | ||
| 744 | * In today's world with < 65 formats, and formats 0, and 2 are | ||
| 745 | * supported | ||
| 746 | * 0x0000000000000005 | ||
| 747 | * ^-offset = 0, formats = 5 | ||
| 748 | * | ||
| 749 | * If the number formats grew to 128, and formats 98-102 are | ||
| 750 | * supported with the modifier: | ||
| 751 | * | ||
| 752 | * 0x0000003c00000000 0000000000000000 | ||
| 753 | * ^ | ||
| 754 | * |__offset = 64, formats = 0x3c00000000 | ||
| 755 | * | ||
| 756 | */ | ||
| 757 | __u64 formats; | ||
| 758 | __u32 offset; | ||
| 759 | __u32 pad; | ||
| 760 | |||
| 761 | /* The modifier that applies to the >get_plane format list bitmask. */ | ||
| 762 | __u64 modifier; | ||
| 763 | }; | ||
| 764 | |||
| 715 | /** | 765 | /** |
| 716 | * Create a new 'blob' data property, copying length bytes from data pointer, | 766 | * Create a new 'blob' data property, copying length bytes from data pointer, |
| 717 | * and returning new blob ID. | 767 | * and returning new blob ID. |
| @@ -260,6 +260,8 @@ typedef struct _drm_i915_sarea { · 259 unmodified lines | |||
| 260 | #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 | 260 | #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 |
| 261 | #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 | 261 | #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 |
| 262 | #define DRM_I915_PERF_OPEN 0x36 | 262 | #define DRM_I915_PERF_OPEN 0x36 |
| 263 | #define DRM_I915_PERF_ADD_CONFIG 0x37 | ||
| 264 | #define DRM_I915_PERF_REMOVE_CONFIG 0x38 | ||
| 263 | 265 | ||
| 264 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | 266 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) |
| 265 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) | 267 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) |
| @@ -315,6 +317,8 @@ typedef struct _drm_i915_sarea { · 49 unmodified lines | |||
| 315 | #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) | 317 | #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) |
| 316 | #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) | 318 | #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) |
| 317 | #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) | 319 | #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) |
| 320 | #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) | ||
| 321 | #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) | ||
| 318 | 322 | ||
| 319 | /* Allow drivers to submit batchbuffers directly to hardware, relying | 323 | /* Allow drivers to submit batchbuffers directly to hardware, relying |
| 320 | * on the security mechanisms provided by hardware. | 324 | * on the security mechanisms provided by hardware. |
| @@ -431,6 +435,11 @@ typedef struct drm_i915_irq_wait { · 110 unmodified lines | |||
| 431 | */ | 435 | */ |
| 432 | #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 | 436 | #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 |
| 433 | 437 | ||
| 438 | /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of | ||
| 439 | * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. | ||
| 440 | */ | ||
| 441 | #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 | ||
| 442 | |||
| 434 | typedef struct drm_i915_getparam { | 443 | typedef struct drm_i915_getparam { |
| 435 | __s32 param; | 444 | __s32 param; |
| 436 | /* | 445 | /* |
| @@ -812,6 +821,17 @@ struct drm_i915_gem_exec_object2 { · 375 unmodified lines | |||
| 812 | __u64 rsvd2; | 821 | __u64 rsvd2; |
| 813 | }; | 822 | }; |
| 814 | 823 | ||
| 824 | struct drm_i915_gem_exec_fence { | ||
| 825 | /** | ||
| 826 | * User's handle for a drm_syncobj to wait on or signal. | ||
| 827 | */ | ||
| 828 | __u32 handle; | ||
| 829 | |||
| 830 | #define I915_EXEC_FENCE_WAIT (1<<0) | ||
| 831 | #define I915_EXEC_FENCE_SIGNAL (1<<1) | ||
| 832 | __u32 flags; | ||
| 833 | }; | ||
| 834 | |||
| 815 | struct drm_i915_gem_execbuffer2 { | 835 | struct drm_i915_gem_execbuffer2 { |
| 816 | /** | 836 | /** |
| 817 | * List of gem_exec_object2 structs | 837 | * List of gem_exec_object2 structs |
| @@ -826,7 +846,11 @@ struct drm_i915_gem_execbuffer2 { · 8 unmodified lines | |||
| 826 | __u32 DR1; | 846 | __u32 DR1; |
| 827 | __u32 DR4; | 847 | __u32 DR4; |
| 828 | __u32 num_cliprects; | 848 | __u32 num_cliprects; |
| 829 | /** This is a struct drm_clip_rect *cliprects */ | 849 | /** |
| 850 | * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY | ||
| 851 | * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a | ||
| 852 | * struct drm_i915_gem_exec_fence *fences. | ||
| 853 | */ | ||
| 830 | __u64 cliprects_ptr; | 854 | __u64 cliprects_ptr; |
| 831 | #define I915_EXEC_RING_MASK (7<<0) | 855 | #define I915_EXEC_RING_MASK (7<<0) |
| 832 | #define I915_EXEC_DEFAULT (0<<0) | 856 | #define I915_EXEC_DEFAULT (0<<0) |
| @@ -927,7 +951,14 @@ struct drm_i915_gem_execbuffer2 { · 94 unmodified lines | |||
| 927 | * element). | 951 | * element). |
| 928 | */ | 952 | */ |
| 929 | #define I915_EXEC_BATCH_FIRST (1<<18) | 953 | #define I915_EXEC_BATCH_FIRST (1<<18) |
| 930 | #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_BATCH_FIRST<<1)) | 954 | |
| 955 | /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr | ||
| 956 | * define an array of i915_gem_exec_fence structures which specify a set of | ||
| 957 | * dma fences to wait upon or signal. | ||
| 958 | */ | ||
| 959 | #define I915_EXEC_FENCE_ARRAY (1<<19) | ||
| 960 | |||
| 961 | #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) | ||
| 931 | 962 | ||
| 932 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) | 963 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
| 933 | #define i915_execbuffer2_set_context_id(eb2, context) \ | 964 | #define i915_execbuffer2_set_context_id(eb2, context) \ |
| @@ -1467,6 +1498,22 @@ enum drm_i915_perf_record_type { · 533 unmodified lines | |||
| 1467 | DRM_I915_PERF_RECORD_MAX /* non-ABI */ | 1498 | DRM_I915_PERF_RECORD_MAX /* non-ABI */ |
| 1468 | }; | 1499 | }; |
| 1469 | 1500 | ||
| 1501 | /** | ||
| 1502 | * Structure to upload perf dynamic configuration into the kernel. | ||
| 1503 | */ | ||
| 1504 | struct drm_i915_perf_oa_config { | ||
| 1505 | /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ | ||
| 1506 | char uuid[36]; | ||
| 1507 | |||
| 1508 | __u32 n_mux_regs; | ||
| 1509 | __u32 n_boolean_regs; | ||
| 1510 | __u32 n_flex_regs; | ||
| 1511 | |||
| 1512 | __u64 __user mux_regs_ptr; | ||
| 1513 | __u64 __user boolean_regs_ptr; | ||
| 1514 | __u64 __user flex_regs_ptr; | ||
| 1515 | }; | ||
| 1516 | |||
| 1470 | #if defined(__cplusplus) | 1517 | #if defined(__cplusplus) |
| 1471 | } | 1518 | } |
| 1472 | #endif | 1519 | #endif |
| @@ -80,8 +80,8 @@ struct drm_qxl_reloc { · 79 unmodified lines | |||
| 80 | }; | 80 | }; |
| 81 | 81 | ||
| 82 | struct drm_qxl_command { | 82 | struct drm_qxl_command { |
| 83 | __u64 __user command; /* void* */ | 83 | __u64 command; /* void* */ |
| 84 | __u64 __user relocs; /* struct drm_qxl_reloc* */ | 84 | __u64 relocs; /* struct drm_qxl_reloc* */ |
| 85 | __u32 type; | 85 | __u32 type; |
| 86 | __u32 command_size; | 86 | __u32 command_size; |
| 87 | __u32 relocs_num; | 87 | __u32 relocs_num; |
| @@ -91,7 +91,7 @@ struct drm_qxl_command { · 3 unmodified lines | |||
| 91 | struct drm_qxl_execbuffer { | 91 | struct drm_qxl_execbuffer { |
| 92 | __u32 flags; /* for future use */ | 92 | __u32 flags; /* for future use */ |
| 93 | __u32 commands_num; | 93 | __u32 commands_num; |
| 94 | __u64 __user commands; /* struct drm_qxl_command* */ | 94 | __u64 commands; /* struct drm_qxl_command* */ |
| 95 | }; | 95 | }; |
| 96 | 96 | ||
| 97 | struct drm_qxl_update_area { | 97 | struct drm_qxl_update_area { |
| @@ -40,6 +40,7 @@ extern "C" { · 39 unmodified lines | |||
| 40 | #define DRM_VC4_GET_PARAM 0x07 | 40 | #define DRM_VC4_GET_PARAM 0x07 |
| 41 | #define DRM_VC4_SET_TILING 0x08 | 41 | #define DRM_VC4_SET_TILING 0x08 |
| 42 | #define DRM_VC4_GET_TILING 0x09 | 42 | #define DRM_VC4_GET_TILING 0x09 |
| 43 | #define DRM_VC4_LABEL_BO 0x0a | ||
| 43 | 44 | ||
| 44 | #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) | 45 | #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) |
| 45 | #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) | 46 | #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) |
| @@ -51,6 +52,7 @@ extern "C" { · 5 unmodified lines | |||
| 51 | #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) | 52 | #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) |
| 52 | #define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) | 53 | #define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) |
| 53 | #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) | 54 | #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) |
| 55 | #define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) | ||
| 54 | 56 | ||
| 55 | struct drm_vc4_submit_rcl_surface { | 57 | struct drm_vc4_submit_rcl_surface { |
| 56 | __u32 hindex; /* Handle index, or ~0 if not present. */ | 58 | __u32 hindex; /* Handle index, or ~0 if not present. */ |
| @@ -153,6 +155,16 @@ struct drm_vc4_submit_cl { · 96 unmodified lines | |||
| 153 | __u32 pad:24; | 155 | __u32 pad:24; |
| 154 | 156 | ||
| 155 | #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) | 157 | #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) |
| 158 | /* By default, the kernel gets to choose the order that the tiles are | ||
| 159 | * rendered in. If this is set, then the tiles will be rendered in a | ||
| 160 | * raster order, with the right-to-left vs left-to-right and | ||
| 161 | * top-to-bottom vs bottom-to-top dictated by | ||
| 162 | * VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping | ||
| 163 | * blits to be implemented using the 3D engine. | ||
| 164 | */ | ||
| 165 | #define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1) | ||
| 166 | #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2) | ||
| 167 | #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3) | ||
| 156 | __u32 flags; | 168 | __u32 flags; |
| 157 | 169 | ||
| 158 | /* Returned value of the seqno of this render job (for the | 170 | /* Returned value of the seqno of this render job (for the |
| @@ -292,6 +304,7 @@ struct drm_vc4_get_hang_state { · 133 unmodified lines | |||
| 292 | #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 | 304 | #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 |
| 293 | #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 | 305 | #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 |
| 294 | #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 | 306 | #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 |
| 307 | #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 | ||
| 295 | 308 | ||
| 296 | struct drm_vc4_get_param { | 309 | struct drm_vc4_get_param { |
| 297 | __u32 param; | 310 | __u32 param; |
| @@ -311,6 +324,15 @@ struct drm_vc4_set_tiling { · 13 unmodified lines | |||
| 311 | __u64 modifier; | 324 | __u64 modifier; |
| 312 | }; | 325 | }; |
| 313 | 326 | ||
| 327 | /** | ||
| 328 | * struct drm_vc4_label_bo - Attach a name to a BO for debug purposes. | ||
| 329 | */ | ||
| 330 | struct drm_vc4_label_bo { | ||
| 331 | __u32 handle; | ||
| 332 | __u32 len; | ||
| 333 | __u64 name; | ||
| 334 | }; | ||
| 335 | |||
| 314 | #if defined(__cplusplus) | 336 | #if defined(__cplusplus) |
| 315 | } | 337 | } |
| 316 | #endif | 338 | #endif |
| @@ -297,13 +297,17 @@ union drm_vmw_surface_reference_arg { · 296 unmodified lines | |||
| 297 | * @version: Allows expanding the execbuf ioctl parameters without breaking | 297 | * @version: Allows expanding the execbuf ioctl parameters without breaking |
| 298 | * backwards compatibility, since user-space will always tell the kernel | 298 | * backwards compatibility, since user-space will always tell the kernel |
| 299 | * which version it uses. | 299 | * which version it uses. |
| 300 | * @flags: Execbuf flags. None currently. | 300 | * @flags: Execbuf flags. |
| 301 | * @imported_fence_fd: FD for a fence imported from another device | ||
| 301 | * | 302 | * |
| 302 | * Argument to the DRM_VMW_EXECBUF Ioctl. | 303 | * Argument to the DRM_VMW_EXECBUF Ioctl. |
| 303 | */ | 304 | */ |
| 304 | 305 | ||
| 305 | #define DRM_VMW_EXECBUF_VERSION 2 | 306 | #define DRM_VMW_EXECBUF_VERSION 2 |
| 306 | 307 | ||
| 308 | #define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0) | ||
| 309 | #define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1) | ||
| 310 | |||
| 307 | struct drm_vmw_execbuf_arg { | 311 | struct drm_vmw_execbuf_arg { |
| 308 | __u64 commands; | 312 | __u64 commands; |
| 309 | __u32 command_size; | 313 | __u32 command_size; |
| @@ -312,7 +316,7 @@ struct drm_vmw_execbuf_arg { · 2 unmodified lines | |||
| 312 | __u32 version; | 316 | __u32 version; |
| 313 | __u32 flags; | 317 | __u32 flags; |
| 314 | __u32 context_handle; | 318 | __u32 context_handle; |
| 315 | __u32 pad64; | 319 | __s32 imported_fence_fd; |
| 316 | }; | 320 | }; |
| 317 | 321 | ||
| 318 | /** | 322 | /** |
| @@ -328,6 +332,7 @@ struct drm_vmw_execbuf_arg { · 9 unmodified lines | |||
| 328 | * @passed_seqno: The highest seqno number processed by the hardware | 332 | * @passed_seqno: The highest seqno number processed by the hardware |
| 329 | * so far. This can be used to mark user-space fence objects as signaled, and | 333 | * so far. This can be used to mark user-space fence objects as signaled, and |
| 330 | * to determine whether a fence seqno might be stale. | 334 | * to determine whether a fence seqno might be stale. |
| 335 | * @fd: FD associated with the fence, -1 if not exported | ||
| 331 | * @error: This member should've been set to -EFAULT on submission. | 336 | * @error: This member should've been set to -EFAULT on submission. |
| 332 | * The following actions should be take on completion: | 337 | * The following actions should be take on completion: |
| 333 | * error == -EFAULT: Fence communication failed. The host is synchronized. | 338 | * error == -EFAULT: Fence communication failed. The host is synchronized. |
| @@ -345,7 +350,7 @@ struct drm_vmw_fence_rep { · 11 unmodified lines | |||
| 345 | __u32 mask; | 350 | __u32 mask; |
| 346 | __u32 seqno; | 351 | __u32 seqno; |
| 347 | __u32 passed_seqno; | 352 | __u32 passed_seqno; |
| 348 | __u32 pad64; | 353 | __s32 fd; |
| 349 | __s32 error; | 354 | __s32 error; |
| 350 | }; | 355 | }; |
| 351 | 356 | ||
| @@ -232,6 +232,35 @@ struct kfd_ioctl_wait_events_args { · 231 unmodified lines | |||
| 232 | uint32_t wait_result; /* from KFD */ | 232 | uint32_t wait_result; /* from KFD */ |
| 233 | }; | 233 | }; |
| 234 | 234 | ||
| 235 | struct kfd_ioctl_set_scratch_backing_va_args { | ||
| 236 | uint64_t va_addr; /* to KFD */ | ||
| 237 | uint32_t gpu_id; /* to KFD */ | ||
| 238 | uint32_t pad; | ||
| 239 | }; | ||
| 240 | |||
| 241 | struct kfd_ioctl_get_tile_config_args { | ||
| 242 | /* to KFD: pointer to tile array */ | ||
| 243 | uint64_t tile_config_ptr; | ||
| 244 | /* to KFD: pointer to macro tile array */ | ||
| 245 | uint64_t macro_tile_config_ptr; | ||
| 246 | /* to KFD: array size allocated by user mode | ||
| 247 | * from KFD: array size filled by kernel | ||
| 248 | */ | ||
| 249 | uint32_t num_tile_configs; | ||
| 250 | /* to KFD: array size allocated by user mode | ||
| 251 | * from KFD: array size filled by kernel | ||
| 252 | */ | ||
| 253 | uint32_t num_macro_tile_configs; | ||
| 254 | |||
| 255 | uint32_t gpu_id; /* to KFD */ | ||
| 256 | uint32_t gb_addr_config; /* from KFD */ | ||
| 257 | uint32_t num_banks; /* from KFD */ | ||
| 258 | uint32_t num_ranks; /* from KFD */ | ||
| 259 | /* struct size can be extended later if needed | ||
| 260 | * without breaking ABI compatibility | ||
| 261 | */ | ||
| 262 | }; | ||
| 263 | |||
| 235 | #define AMDKFD_IOCTL_BASE 'K' | 264 | #define AMDKFD_IOCTL_BASE 'K' |
| 236 | #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) | 265 | #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) |
| 237 | #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) | 266 | #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) |
| @@ -286,7 +315,13 @@ struct kfd_ioctl_wait_events_args { · 48 unmodified lines | |||
| 286 | #define AMDKFD_IOC_DBG_WAVE_CONTROL \ | 315 | #define AMDKFD_IOC_DBG_WAVE_CONTROL \ |
| 287 | AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) | 316 | AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) |
| 288 | 317 | ||
| 318 | #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \ | ||
| 319 | AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) | ||
| 320 | |||
| 321 | #define AMDKFD_IOC_GET_TILE_CONFIG \ | ||
| 322 | AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) | ||
| 323 | |||
| 289 | #define AMDKFD_COMMAND_START 0x01 | 324 | #define AMDKFD_COMMAND_START 0x01 |
| 290 | #define AMDKFD_COMMAND_END 0x11 | 325 | #define AMDKFD_COMMAND_END 0x13 |
| 291 | 326 | ||
| 292 | #endif | 327 | #endif |