Few Qualcomm platforms such as, sdm845 have an additional outer cache called as System cache, aka. Last level cache (LLC) that allows non-coherent devices to upgrade to using caching. This cache sits right before the DDR, and is tightly coupled with the memory controller. The clients using this cache request their slices from this system cache, make it active, and can then start using it. There is a fundamental assumption that non-coherent devices can't access caches. This change adds an exception where they *can* use some level of cache despite still being non-coherent overall. The coherent devices that use cacheable memory, and CPU make use of this system cache by default. Looking at memory types, we have following - a) Normal uncached :- MAIR 0x44, inner non-cacheable, outer non-cacheable; b) Normal cached :- MAIR 0xff, inner read write-back non-transient, outer read write-back non-transient; attribute setting for coherenet I/O devices. and, for non-coherent i/o devices that can allocate in system cache another type gets added - c) Normal sys-cached :- MAIR 0xf4, inner non-cacheable, outer read write-back non-transient Coherent I/O devices use system cache by marking the memory as normal cached. Non-coherent I/O devices should mark the memory as normal sys-cached in page tables to use system cache.
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| @@ -41,6 +41,12 @@ · 40 unmodified lines | ||
| 41 | 41 | * if the IOMMU page table format is equivalent. |
| 42 | 42 | */ |
| 43 | 43 | #define IOMMU_PRIV (1 << 5) |
| 44 | +/* | |
| 45 | + * Non-coherent masters on few Qualcomm SoCs can use this page protection flag | |
| 46 | + * to set correct cacheability attributes to use an outer level of cache - | |
| 47 | + * last level cache, aka system cache. | |
| 48 | + */ | |
| 49 | +#define IOMMU_QCOM_SYS_CACHE (1 << 6) | |
| 44 | 50 | |
| 45 | 51 | struct iommu_ops; |
| 46 | 52 | struct iommu_group; |