Pull RISC-v updates from Palmer Dabbelt: - Support for pointer masking in userspace - Support for probing vector misaligned access performance - Support for qspinlock on systems with Zacas and Zabha * tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (38 commits) RISC-V: Remove unnecessary include from compat.h riscv: Fix default misaligned access trap riscv: Add qspinlock support dt-bindings: riscv: Add Ziccrse ISA extension description riscv: Add ISA extension parsing for Ziccrse asm-generic: ticket-lock: Add separate ticket-lock.h asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock riscv: Implement xchg8/16() using Zabha riscv: Implement arch_cmpxchg128() using Zacas riscv: Improve zacas fully-ordered cmpxchg() riscv: Implement cmpxchg8/16() using Zabha dt-bindings: riscv: Add Zabha ISA extension description riscv: Implement cmpxchg32/64() using Zacas riscv: Do not fail to build on byte/halfword operations with Zawrs riscv: Move cpufeature.h macros into their own header KVM: riscv: selftests: Add Smnpm and Ssnpm to get-reg-list test RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests riscv: hwprobe: Export the Supm ISA extension riscv: selftests: Add a pointer masking test riscv: Allow ptrace control of the tagged address ABI ...
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| @@ -451,6 +451,7 @@ typedef struct elf64_shdr { · 450 unmodified lines | ||
| 451 | 451 | #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ |
| 452 | 452 | #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ |
| 453 | 453 | #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ |
| 454 | +#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */ | |
| 454 | 455 | #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ |
| 455 | 456 | #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ |
| 456 | 457 | #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */ |