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MIPS, Perf-events: Work with irq_work

This is the MIPS part of the following commit by Peter Zijlstra: - e360adbe29241a0194e10e20595360dd7b98a2b3 irq_work: Add generic hardirq context callbacks Provide a mechanism that allows running code in IRQ context. It is most useful for NMI code that needs to interact with the rest of the system -- like wakeup a task to drain buffers. Perf currently has such a mechanism, so extract that and provide it as a generic feature, independent of perf so that others may also benefit. The IRQ context callback is generated through self-IPIs where possible, or on architectures like powerpc the decrementer (the built-in timer facility) is set to generate an interrupt immediately. Architectures that don't have anything like this get to do with a callback from the timer tick. These architectures can call irq_work_run() at the tail of any IRQ handlers that might enqueue such work (like the perf IRQ handler) to avoid undue latencies in processing the work. For MIPSXX, we need to call irq_work_run() at the tail of the perf IRQ handler as described above.

Deng-Cheng Zhu committed 15 years ago

Commit 91f01731 parent efe8dc53 files · +3 −12Browse files

Unified · Split

3 files
  1. arch/mips/Kconfig +1 −0
  2. arch/mips/include/asm/perf_event.h +1 −11
  3. arch/mips/kernel/perf_event_mipsxx.c +1 −1
arch/mips/Kconfig+1−0
@@ -4,6 +4,7 @@ config MIPS · 3 unmodified lines
4 select HAVE_GENERIC_DMA_COHERENT4 select HAVE_GENERIC_DMA_COHERENT
5 select HAVE_IDE5 select HAVE_IDE
6 select HAVE_OPROFILE6 select HAVE_OPROFILE
7 select HAVE_IRQ_WORK
7 select HAVE_PERF_EVENTS8 select HAVE_PERF_EVENTS
8 select PERF_USE_VMALLOC9 select PERF_USE_VMALLOC
9 select HAVE_ARCH_KGDB10 select HAVE_ARCH_KGDB
arch/mips/include/asm/perf_event.h+1−11
@@ -11,15 +11,5 @@ · 10 unmodified lines
11 11
12#ifndef __MIPS_PERF_EVENT_H__12#ifndef __MIPS_PERF_EVENT_H__
13#define __MIPS_PERF_EVENT_H__13#define __MIPS_PERF_EVENT_H__
14 14/* Leave it empty here. The file is required by linux/perf_event.h */
15/*
16 * MIPS performance counters do not raise NMI upon overflow, a regular
17 * interrupt will be signaled. Hence we can do the pending perf event
18 * work at the tail of the irq handler.
19 */
20static inline void
21set_perf_event_pending(void)
22{
23}
24
25#endif /* __MIPS_PERF_EVENT_H__ */15#endif /* __MIPS_PERF_EVENT_H__ */
arch/mips/kernel/perf_event_mipsxx.c+1−1
@@ -696,7 +696,7 @@ static int mipsxx_pmu_handle_shared_irq(void) · 695 unmodified lines
696 * interrupt, not NMI.696 * interrupt, not NMI.
697 */697 */
698 if (handled == IRQ_HANDLED)698 if (handled == IRQ_HANDLED)
699 perf_event_do_pending();699 irq_work_run();
700 700
701#ifdef CONFIG_MIPS_MT_SMP701#ifdef CONFIG_MIPS_MT_SMP
702 read_unlock(&pmuint_rwlock);702 read_unlock(&pmuint_rwlock);

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