lael-labs/linux

Documentation/devicetree/bindings/serial/fsl-lpuart.yaml+3−1

           - fsl,imx8qxp-lpuart
           - fsl,imxrt1050-lpuart
       - items:
-          - const: fsl,imx8ulp-lpuart
+          - enum:
+              - fsl,imx93-lpuart
+              - fsl,imx8ulp-lpuart
           - const: fsl,imx7ulp-lpuart
       - items:
           - enum:

Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml+86−0

@@ -0,0 +1,86 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: "http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#"
	5	$schema: "http://devicetree.org/meta-schemas/core.yaml#"
	6
	7	title: Qualcomm Geni based QUP UART interface
	8
	9	maintainers:
	10	- Andy Gross <agross@kernel.org>
	11	- Bjorn Andersson <bjorn.andersson@linaro.org>
	12
	13	allOf:
	14	- $ref: /schemas/serial/serial.yaml#
	15
	16	properties:
	17	compatible:
	18	enum:
	19	- qcom,geni-uart
	20	- qcom,geni-debug-uart
	21
	22	clocks:
	23	maxItems: 1
	24
	25	clock-names:
	26	const: se
	27
	28	interconnects:
	29	maxItems: 2
	30
	31	interconnect-names:
	32	items:
	33	- const: qup-core
	34	- const: qup-config
	35
	36	interrupts:
	37	minItems: 1
	38	items:
	39	- description: UART core irq
	40	- description: Wakeup irq (RX GPIO)
	41
	42	operating-points-v2: true
	43
	44	pinctrl-0: true
	45	pinctrl-1: true
	46
	47	pinctrl-names:
	48	minItems: 1
	49	items:
	50	- const: default
	51	- const: sleep
	52
	53	power-domains:
	54	maxItems: 1
	55
	56	reg:
	57	maxItems: 1
	58
	59	required:
	60	- compatible
	61	- clocks
	62	- clock-names
	63	- interrupts
	64	- reg
	65
	66	unevaluatedProperties: false
	67
	68	examples:
	69	- \|
	70	#include <dt-bindings/interrupt-controller/arm-gic.h>
	71	#include <dt-bindings/clock/qcom,gcc-sc7180.h>
	72	#include <dt-bindings/interconnect/qcom,sc7180.h>
	73
	74	serial@a88000 {
	75	compatible = "qcom,geni-uart";
	76	reg = <0xa88000 0x7000>;
	77	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	78	clock-names = "se";
	79	clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
	80	pinctrl-0 = <&qup_uart0_default>;
	81	pinctrl-names = "default";
	82	interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
	83	<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
	84	interconnect-names = "qup-core", "qup-config";
	85	};
	86	...

Documentation/devicetree/bindings/serial/renesas,em-uart.yaml+31−6

@@ -9,12 +9,16 @@ title: Renesas EMMA Mobile UART Interface · 8 unmodified lines
9	maintainers:	9	maintainers:
10	- Magnus Damm <magnus.damm@gmail.com>	10	- Magnus Damm <magnus.damm@gmail.com>
11		11
12	allOf:
13	- $ref: serial.yaml#
14
15	properties:	12	properties:
16	compatible:	13	compatible:
17	const: renesas,em-uart	14	oneOf:
		15	- items:
		16	- enum:
		17	- renesas,r9a09g011-uart # RZ/V2M
		18	- const: renesas,em-uart # generic EMMA Mobile compatible UART
		19
		20	- items:
		21	- const: renesas,em-uart # generic EMMA Mobile compatible UART
18		22
19	reg:	23	reg:
20	maxItems: 1	24	maxItems: 1
@@ -23,10 +27,31 @@ properties: · 2 unmodified lines
23	maxItems: 1	27	maxItems: 1
24		28
25	clocks:	29	clocks:
26	maxItems: 1	30	minItems: 1
		31	items:
		32	- description: UART functional clock
		33	- description: Internal clock to access the registers
27		34
28	clock-names:	35	clock-names:
29	const: sclk	36	minItems: 1
		37	items:
		38	- const: sclk
		39	- const: pclk
		40
		41	allOf:
		42	- $ref: serial.yaml#
		43
		44	- if:
		45	properties:
		46	compatible:
		47	contains:
		48	const: renesas,r9a09g011-uart
		49	then:
		50	properties:
		51	clocks:
		52	minItems: 2
		53	clock-names:
		54	minItems: 2
30		55
31	required:	56	required:
32	- compatible	57	- compatible

Documentation/devicetree/bindings/serial/renesas,hscif.yaml+8−1

               - renesas,hscif-r8a77980     # R-Car V3H
               - renesas,hscif-r8a77990     # R-Car E3
               - renesas,hscif-r8a77995     # R-Car D3
-              - renesas,hscif-r8a779a0     # R-Car V3U
           - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2
           - const: renesas,hscif           # generic HSCIF compatible UART
+      - items:
+          - enum:
+              - renesas,hscif-r8a779a0     # R-Car V3U
+              - renesas,hscif-r8a779g0     # R-Car V4H
+          - const: renesas,rcar-gen4-hscif # R-Car Gen4
+          - const: renesas,hscif           # generic HSCIF compatible UART
   reg:
     maxItems: 1
         enum:
           - renesas,rcar-gen2-hscif
           - renesas,rcar-gen3-hscif
+          - renesas,rcar-gen4-hscif
 then:
   required:
     - resets

Documentation/devicetree/bindings/serial/renesas,scif.yaml+1−1

               - renesas,scif-r8a77980     # R-Car V3H
               - renesas,scif-r8a77990     # R-Car E3
               - renesas,scif-r8a77995     # R-Car D3
-              - renesas,scif-r8a779a0     # R-Car V3U
           - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
           - const: renesas,scif           # generic SCIF compatible UART
       - items:
           - enum:
+              - renesas,scif-r8a779a0     # R-Car V3U
               - renesas,scif-r8a779f0     # R-Car S4-8
           - const: renesas,rcar-gen4-scif # R-Car Gen4
           - const: renesas,scif           # generic SCIF compatible UART

Documentation/devicetree/bindings/serial/rs485.yaml+5−0

     description: drive RTS low when sending (default is high).
     $ref: /schemas/types.yaml#/definitions/flag
+  rs485-rx-active-high:
+    description: Polarity of receiver enable signal (when separate from RTS).
+      True indicates active high (default is low).
+    $ref: /schemas/types.yaml#/definitions/flag
   linux,rs485-enabled-at-boot-time:
     description: enables the rs485 feature at boot time. It can be disabled
       later with proper ioctl.

Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml+4−1

@@ -20,7 +20,10 @@ properties: · 19 unmodified lines
20	maxItems: 1	20	maxItems: 1
21		21
22	clocks:	22	clocks:
23	minItems: 1	23	maxItems: 1
		24
		25	resets:
		26	maxItems: 1
24		27
25	auto-flow-control:	28	auto-flow-control:
26	description: enable automatic flow control support.	29	description: enable automatic flow control support.

Documentation/driver-api/index.rst+1−0

@@ -101,6 +101,7 @@ available subsections can be seen below. · 100 unmodified lines
101	surface_aggregator/index	101	surface_aggregator/index
102	switchtec	102	switchtec
103	sync_file	103	sync_file
		104	tty/index
104	vfio-mediated-device	105	vfio-mediated-device
105	vfio	106	vfio
106	vfio-pci-device-specific-driver-acceptance	107	vfio-pci-device-specific-driver-acceptance

Documentation/driver-api/serial/driver.rst+1−1

@@ -311,7 +311,7 @@ hardware. · 310 unmodified lines
311	This call must not sleep	311	This call must not sleep
312		312
313	set_ldisc(port,termios)	313	set_ldisc(port,termios)
314	Notifier for discipline change. See Documentation/tty/tty_ldisc.rst.	314	Notifier for discipline change. See ../tty/tty_ldisc.rst.
315		315
316	Locking: caller holds tty_port->mutex	316	Locking: caller holds tty_port->mutex
317		317

Documentation/driver-api/serial/index.rst+0−2

@@ -16,8 +16,6 @@ Serial drivers · 15 unmodified lines
16	.. toctree::	16	.. toctree::
17	:maxdepth: 1	17	:maxdepth: 1
18		18
19	moxa-smartio
20	n_gsm
21	serial-iso7816	19	serial-iso7816
22	serial-rs485	20	serial-rs485
23		21

Documentation/driver-api/serial/n_gsm.rst+0−159

@@ -1,159 +0,0 @@
1	==============================
2	GSM 0710 tty multiplexor HOWTO
3	==============================
4
5	This line discipline implements the GSM 07.10 multiplexing protocol
6	detailed in the following 3GPP document:
7
8	https://www.3gpp.org/ftp/Specs/archive/07_series/07.10/0710-720.zip
9
10	This document give some hints on how to use this driver with GPRS and 3G
11	modems connected to a physical serial port.
12
13	How to use it
14	-------------
15	1. config initiator
16	^^^^^^^^^^^^^^^^^^^^^
17
18	1.1 initialize the modem in 0710 mux mode (usually AT+CMUX= command) through
19	its serial port. Depending on the modem used, you can pass more or less
20	parameters to this command.
21
22	1.2 switch the serial line to using the n_gsm line discipline by using
23	TIOCSETD ioctl.
24
25	1.3 configure the mux using GSMIOC_GETCONF / GSMIOC_SETCONF ioctl.
26
27	1.4 obtain base gsmtty number for the used serial port.
28
29	Major parts of the initialization program :
30	(a good starting point is util-linux-ng/sys-utils/ldattach.c)::
31
32	#include <stdio.h>
33	#include <stdint.h>
34	#include <linux/gsmmux.h>
35	#include <linux/tty.h>
36	#define DEFAULT_SPEED B115200
37	#define SERIAL_PORT /dev/ttyS0
38
39	int ldisc = N_GSM0710;
40	struct gsm_config c;
41	struct termios configuration;
42	uint32_t first;
43
44	/* open the serial port connected to the modem */
45	fd = open(SERIAL_PORT, O_RDWR \| O_NOCTTY \| O_NDELAY);
46
47	/* configure the serial port : speed, flow control ... */
48
49	/* send the AT commands to switch the modem to CMUX mode
50	and check that it's successful (should return OK) */
51	write(fd, "AT+CMUX=0\r", 10);
52
53	/* experience showed that some modems need some time before
54	being able to answer to the first MUX packet so a delay
55	may be needed here in some case */
56	sleep(3);
57
58	/* use n_gsm line discipline */
59	ioctl(fd, TIOCSETD, &ldisc);
60
61	/* get n_gsm configuration */
62	ioctl(fd, GSMIOC_GETCONF, &c);
63	/* we are initiator and need encoding 0 (basic) */
64	c.initiator = 1;
65	c.encapsulation = 0;
66	/* our modem defaults to a maximum size of 127 bytes */
67	c.mru = 127;
68	c.mtu = 127;
69	/* set the new configuration */
70	ioctl(fd, GSMIOC_SETCONF, &c);
71	/* get first gsmtty device node */
72	ioctl(fd, GSMIOC_GETFIRST, &first);
73	printf("first muxed line: /dev/gsmtty%i\n", first);
74
75	/* and wait for ever to keep the line discipline enabled */
76	daemon(0,0);
77	pause();
78
79	1.5 use these devices as plain serial ports.
80
81	for example, it's possible:
82
83	- and to use gnokii to send / receive SMS on ttygsm1
84	- to use ppp to establish a datalink on ttygsm2
85
86	1.6 first close all virtual ports before closing the physical port.
87
88	Note that after closing the physical port the modem is still in multiplexing
89	mode. This may prevent a successful re-opening of the port later. To avoid
90	this situation either reset the modem if your hardware allows that or send
91	a disconnect command frame manually before initializing the multiplexing mode
92	for the second time. The byte sequence for the disconnect command frame is::
93
94	0xf9, 0x03, 0xef, 0x03, 0xc3, 0x16, 0xf9.
95
96	2. config requester
97	^^^^^^^^^^^^^^^^^^^^^
98
99	2.1 receive string "AT+CMUX= command" through its serial port,initialize
100	mux mode config
101
102	2.2 switch the serial line to using the n_gsm line discipline by using
103	TIOCSETD ioctl.
104
105	2.3 configure the mux using GSMIOC_GETCONF / GSMIOC_SETCONF ioctl.
106
107	2.4 obtain base gsmtty number for the used serial port::
108
109	#include <stdio.h>
110	#include <stdint.h>
111	#include <linux/gsmmux.h>
112	#include <linux/tty.h>
113	#define DEFAULT_SPEED B115200
114	#define SERIAL_PORT /dev/ttyS0
115
116	int ldisc = N_GSM0710;
117	struct gsm_config c;
118	struct termios configuration;
119	uint32_t first;
120
121	/* open the serial port */
122	fd = open(SERIAL_PORT, O_RDWR \| O_NOCTTY \| O_NDELAY);
123
124	/* configure the serial port : speed, flow control ... */
125
126	/* get serial data and check "AT+CMUX=command" parameter ... */
127
128	/* use n_gsm line discipline */
129	ioctl(fd, TIOCSETD, &ldisc);
130
131	/* get n_gsm configuration */
132	ioctl(fd, GSMIOC_GETCONF, &c);
133	/* we are requester and need encoding 0 (basic) */
134	c.initiator = 0;
135	c.encapsulation = 0;
136	/* our modem defaults to a maximum size of 127 bytes */
137	c.mru = 127;
138	c.mtu = 127;
139	/* set the new configuration */
140	ioctl(fd, GSMIOC_SETCONF, &c);
141	/* get first gsmtty device node */
142	ioctl(fd, GSMIOC_GETFIRST, &first);
143	printf("first muxed line: /dev/gsmtty%i\n", first);
144
145	/* and wait for ever to keep the line discipline enabled */
146	daemon(0,0);
147	pause();
148
149	Additional Documentation
150	------------------------
151	More practical details on the protocol and how it's supported by industrial
152	modems can be found in the following documents :
153
154	- http://www.telit.com/module/infopool/download.php?id=616
155	- http://www.u-blox.com/images/downloads/Product_Docs/LEON-G100-G200-MuxImplementation_ApplicationNote_%28GSM%20G1-CS-10002%29.pdf
156	- http://www.sierrawireless.com/Support/Downloads/AirPrime/WMP_Series/~/media/Support_Downloads/AirPrime/Application_notes/CMUX_Feature_Application_Note-Rev004.ashx
157	- http://wm.sim.com/sim/News/photo/2010721161442.pdf
158
159	11-03-08 - Eric Bénard - <eric@eukrea.com>

Documentation/driver-api/tty/index.rstrenamed from Documentation/tty/index.rst+16−6

    tty_struct
    tty_ldisc
    tty_buffer
-   n_tty
    tty_internals
 Writing TTY Driver
 ==================
 Before one starts writing a TTY driver, they must consider
-:doc:`Serial <../driver-api/serial/driver>` and :doc:`USB Serial
+:doc:`Serial <../serial/driver>` and :doc:`USB Serial <../../usb/usb-serial>`
-<../usb/usb-serial>` layers
+layers first. Drivers for serial devices can often use one of these specific
-first. Drivers for serial devices can often use one of these specific layers to
+layers to implement a serial driver. Only special devices should be handled
-implement a serial driver. Only special devices should be handled directly by
+directly by the TTY Layer. If you are about to write such a driver, read on.
-the TTY Layer. If you are about to write such a driver, read on.
 A *typical* sequence a TTY driver performs is as follows:
 Steps regarding driver, i.e. 1., 3., and 5. are described in detail in
 :doc:`tty_driver`. For the other two (devices handling), look into
 :doc:`tty_port`.
+Other Documentation
+===================
+Miscellaneous documentation can be further found in these documents:
+.. toctree::
+   :maxdepth: 2
+   moxa-smartio
+   n_gsm
+   n_tty

Documentation/driver-api/tty/moxa-smartio.rstrenamed from Documentation/driver-api/serial/moxa-smartio.rst+0−0

File renamed without changes.

Documentation/driver-api/tty/n_gsm.rst+153−0

@@ -0,0 +1,153 @@
	1	==============================
	2	GSM 0710 tty multiplexor HOWTO
	3	==============================
	4
	5	.. contents:: :local:
	6
	7	This line discipline implements the GSM 07.10 multiplexing protocol
	8	detailed in the following 3GPP document:
	9
	10	https://www.3gpp.org/ftp/Specs/archive/07_series/07.10/0710-720.zip
	11
	12	This document give some hints on how to use this driver with GPRS and 3G
	13	modems connected to a physical serial port.
	14
	15	How to use it
	16	=============
	17
	18	Config Initiator
	19	----------------
	20
	21	#. Initialize the modem in 0710 mux mode (usually ``AT+CMUX=`` command) through
	22	its serial port. Depending on the modem used, you can pass more or less
	23	parameters to this command.
	24
	25	#. Switch the serial line to using the n_gsm line discipline by using
	26	``TIOCSETD`` ioctl.
	27
	28	#. Configure the mux using ``GSMIOC_GETCONF``/``GSMIOC_SETCONF`` ioctl.
	29
	30	#. Obtain base gsmtty number for the used serial port.
	31
	32	Major parts of the initialization program
	33	(a good starting point is util-linux-ng/sys-utils/ldattach.c)::
	34
	35	#include <stdio.h>
	36	#include <stdint.h>
	37	#include <linux/gsmmux.h>
	38	#include <linux/tty.h>
	39
	40	#define DEFAULT_SPEED B115200
	41	#define SERIAL_PORT /dev/ttyS0
	42
	43	int ldisc = N_GSM0710;
	44	struct gsm_config c;
	45	struct termios configuration;
	46	uint32_t first;
	47
	48	/* open the serial port connected to the modem */
	49	fd = open(SERIAL_PORT, O_RDWR \| O_NOCTTY \| O_NDELAY);
	50
	51	/* configure the serial port : speed, flow control ... */
	52
	53	/* send the AT commands to switch the modem to CMUX mode
	54	and check that it's successful (should return OK) */
	55	write(fd, "AT+CMUX=0\r", 10);
	56
	57	/* experience showed that some modems need some time before
	58	being able to answer to the first MUX packet so a delay
	59	may be needed here in some case */
	60	sleep(3);
	61
	62	/* use n_gsm line discipline */
	63	ioctl(fd, TIOCSETD, &ldisc);
	64
	65	/* get n_gsm configuration */
	66	ioctl(fd, GSMIOC_GETCONF, &c);
	67	/* we are initiator and need encoding 0 (basic) */
	68	c.initiator = 1;
	69	c.encapsulation = 0;
	70	/* our modem defaults to a maximum size of 127 bytes */
	71	c.mru = 127;
	72	c.mtu = 127;
	73	/* set the new configuration */
	74	ioctl(fd, GSMIOC_SETCONF, &c);
	75	/* get first gsmtty device node */
	76	ioctl(fd, GSMIOC_GETFIRST, &first);
	77	printf("first muxed line: /dev/gsmtty%i\n", first);
	78
	79	/* and wait for ever to keep the line discipline enabled */
	80	daemon(0,0);
	81	pause();
	82
	83	#. Use these devices as plain serial ports.
	84
	85	For example, it's possible:
	86
	87	- to use gnokii to send / receive SMS on ``ttygsm1``
	88	- to use ppp to establish a datalink on ``ttygsm2``
	89
	90	#. First close all virtual ports before closing the physical port.
	91
	92	Note that after closing the physical port the modem is still in multiplexing
	93	mode. This may prevent a successful re-opening of the port later. To avoid
	94	this situation either reset the modem if your hardware allows that or send
	95	a disconnect command frame manually before initializing the multiplexing mode
	96	for the second time. The byte sequence for the disconnect command frame is::
	97
	98	0xf9, 0x03, 0xef, 0x03, 0xc3, 0x16, 0xf9
	99
	100	Config Requester
	101	----------------
	102
	103	#. Receive ``AT+CMUX=`` command through its serial port, initialize mux mode
	104	config.
	105
	106	#. Switch the serial line to using the n_gsm line discipline by using
	107	``TIOCSETD`` ioctl.
	108
	109	#. Configure the mux using ``GSMIOC_GETCONF``/``GSMIOC_SETCONF`` ioctl.
	110
	111	#. Obtain base gsmtty number for the used serial port::
	112
	113	#include <stdio.h>
	114	#include <stdint.h>
	115	#include <linux/gsmmux.h>
	116	#include <linux/tty.h>
	117	#define DEFAULT_SPEED B115200
	118	#define SERIAL_PORT /dev/ttyS0
	119
	120	int ldisc = N_GSM0710;
	121	struct gsm_config c;
	122	struct termios configuration;
	123	uint32_t first;
	124
	125	/* open the serial port */
	126	fd = open(SERIAL_PORT, O_RDWR \| O_NOCTTY \| O_NDELAY);
	127
	128	/* configure the serial port : speed, flow control ... */
	129
	130	/* get serial data and check "AT+CMUX=command" parameter ... */
	131
	132	/* use n_gsm line discipline */
	133	ioctl(fd, TIOCSETD, &ldisc);
	134
	135	/* get n_gsm configuration */
	136	ioctl(fd, GSMIOC_GETCONF, &c);
	137	/* we are requester and need encoding 0 (basic) */
	138	c.initiator = 0;
	139	c.encapsulation = 0;
	140	/* our modem defaults to a maximum size of 127 bytes */
	141	c.mru = 127;
	142	c.mtu = 127;
	143	/* set the new configuration */
	144	ioctl(fd, GSMIOC_SETCONF, &c);
	145	/* get first gsmtty device node */
	146	ioctl(fd, GSMIOC_GETFIRST, &first);
	147	printf("first muxed line: /dev/gsmtty%i\n", first);
	148
	149	/* and wait for ever to keep the line discipline enabled */
	150	daemon(0,0);
	151	pause();
	152
	153	11-03-08 - Eric Bénard - <eric@eukrea.com>

Documentation/driver-api/tty/n_tty.rstrenamed from Documentation/tty/n_tty.rst+0−0

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Documentation/driver-api/tty/tty_buffer.rstrenamed from Documentation/tty/tty_buffer.rst+0−0

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Documentation/driver-api/tty/tty_driver.rstrenamed from Documentation/tty/tty_driver.rst+0−0

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Documentation/driver-api/tty/tty_internals.rstrenamed from Documentation/tty/tty_internals.rst+0−0

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Documentation/driver-api/tty/tty_ldisc.rstrenamed from Documentation/tty/tty_ldisc.rst+0−0

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Documentation/driver-api/tty/tty_port.rstrenamed from Documentation/tty/tty_port.rst+0−0

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Documentation/driver-api/tty/tty_struct.rstrenamed from Documentation/tty/tty_struct.rst+0−0

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Documentation/firmware-guide/acpi/enumeration.rst+25−0

@@ -389,6 +389,31 @@ descriptors once the device is released. · 388 unmodified lines
389	See Documentation/firmware-guide/acpi/gpio-properties.rst for more information	389	See Documentation/firmware-guide/acpi/gpio-properties.rst for more information
390	about the _DSD binding related to GPIOs.	390	about the _DSD binding related to GPIOs.
391		391
		392	RS-485 support
		393	==============
		394
		395	ACPI _DSD (Device Specific Data) can be used to describe RS-485 capability
		396	of UART.
		397
		398	For example::
		399
		400	Device (DEV)
		401	{
		402	...
		403
		404	// ACPI 5.1 _DSD used for RS-485 capabilities
		405	Name (_DSD, Package ()
		406	{
		407	ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
		408	Package ()
		409	{
		410	Package () {"rs485-rts-active-low", Zero},
		411	Package () {"rs485-rx-active-high", Zero},
		412	Package () {"rs485-rx-during-tx", Zero},
		413	}
		414	})
		415	...
		416
392	MFD devices	417	MFD devices
393	===========	418	===========
394		419

Documentation/index.rst+0−1

@@ -136,7 +136,6 @@ needed). · 135 unmodified lines
136	misc-devices/index	136	misc-devices/index
137	scheduler/index	137	scheduler/index
138	mhi/index	138	mhi/index
139	tty/index
140	peci/index	139	peci/index
141		140
142	Architecture-agnostic documentation	141	Architecture-agnostic documentation

Documentation/misc-devices/index.rst+1−0

@@ -25,6 +25,7 @@ fit into other categories. · 24 unmodified lines
25	isl29003	25	isl29003
26	lis3lv02d	26	lis3lv02d
27	max6875	27	max6875
		28	oxsemi-tornado
28	pci-endpoint-test	29	pci-endpoint-test
29	spear-pcie-gadget	30	spear-pcie-gadget
30	uacce	31	uacce

Documentation/misc-devices/oxsemi-tornado.rst+131−0

@@ -0,0 +1,131 @@
	1	.. SPDX-License-Identifier: GPL-2.0
	2
	3	====================================================================
	4	Notes on Oxford Semiconductor PCIe (Tornado) 950 serial port devices
	5	====================================================================
	6
	7	Oxford Semiconductor PCIe (Tornado) 950 serial port devices are driven
	8	by a fixed 62.5MHz clock input derived from the 100MHz PCI Express clock.
	9
	10	The baud rate produced by the baud generator is obtained from this input
	11	frequency by dividing it by the clock prescaler, which can be set to any
	12	value from 1 to 63.875 in increments of 0.125, and then the usual 16-bit
	13	divisor is used as with the original 8250, to divide the frequency by a
	14	value from 1 to 65535. Finally a programmable oversampling rate is used
	15	that can take any value from 4 to 16 to divide the frequency further and
	16	determine the actual baud rate used. Baud rates from 15625000bps down
	17	to 0.933bps can be obtained this way.
	18
	19	By default the oversampling rate is set to 16 and the clock prescaler is
	20	set to 33.875, meaning that the frequency to be used as the reference
	21	for the usual 16-bit divisor is 115313.653, which is close enough to the
	22	frequency of 115200 used by the original 8250 for the same values to be
	23	used for the divisor to obtain the requested baud rates by software that
	24	is unaware of the extra clock controls available.
	25
	26	The oversampling rate is programmed with the TCR register and the clock
	27	prescaler is programmed with the CPR/CPR2 register pair [OX200]_ [OX952]_
	28	[OX954]_ [OX958]_. To switch away from the default value of 33.875 for
	29	the prescaler the enhanced mode has to be explicitly enabled though, by
	30	setting bit 4 of the EFR. In that mode setting bit 7 in the MCR enables
	31	the prescaler or otherwise it is bypassed as if the value of 1 was used.
	32	Additionally writing any value to CPR clears CPR2 for compatibility with
	33	old software written for older conventional PCI Oxford Semiconductor
	34	devices that do not have the extra prescaler's 9th bit in CPR2, so the
	35	CPR/CPR2 register pair has to be programmed in the right order.
	36
	37	By using these parameters rates from 15625000bps down to 1bps can be
	38	obtained, with either exact or highly-accurate actual bit rates for
	39	standard and many non-standard rates.
	40
	41	Here are the figures for the standard and some non-standard baud rates
	42	(including those quoted in Oxford Semiconductor documentation), giving
	43	the requested rate (r), the actual rate yielded (a) and its deviation
	44	from the requested rate (d), and the values of the oversampling rate
	45	(tcr), the clock prescaler (cpr) and the divisor (div) produced by the
	46	new ``get_divisor`` handler:
	47
	48	::
	49
	50	r: 15625000, a: 15625000.00, d: 0.0000%, tcr: 4, cpr: 1.000, div: 1
	51	r: 12500000, a: 12500000.00, d: 0.0000%, tcr: 5, cpr: 1.000, div: 1
	52	r: 10416666, a: 10416666.67, d: 0.0000%, tcr: 6, cpr: 1.000, div: 1
	53	r: 8928571, a: 8928571.43, d: 0.0000%, tcr: 7, cpr: 1.000, div: 1
	54	r: 7812500, a: 7812500.00, d: 0.0000%, tcr: 8, cpr: 1.000, div: 1
	55	r: 4000000, a: 4000000.00, d: 0.0000%, tcr: 5, cpr: 3.125, div: 1
	56	r: 3686400, a: 3676470.59, d: -0.2694%, tcr: 8, cpr: 2.125, div: 1
	57	r: 3500000, a: 3496503.50, d: -0.0999%, tcr: 13, cpr: 1.375, div: 1
	58	r: 3000000, a: 2976190.48, d: -0.7937%, tcr: 14, cpr: 1.500, div: 1
	59	r: 2500000, a: 2500000.00, d: 0.0000%, tcr: 10, cpr: 2.500, div: 1
	60	r: 2000000, a: 2000000.00, d: 0.0000%, tcr: 10, cpr: 3.125, div: 1
	61	r: 1843200, a: 1838235.29, d: -0.2694%, tcr: 16, cpr: 2.125, div: 1
	62	r: 1500000, a: 1492537.31, d: -0.4975%, tcr: 5, cpr: 8.375, div: 1
	63	r: 1152000, a: 1152073.73, d: 0.0064%, tcr: 14, cpr: 3.875, div: 1
	64	r: 921600, a: 919117.65, d: -0.2694%, tcr: 16, cpr: 2.125, div: 2
	65	r: 576000, a: 576036.87, d: 0.0064%, tcr: 14, cpr: 3.875, div: 2
	66	r: 460800, a: 460829.49, d: 0.0064%, tcr: 7, cpr: 3.875, div: 5
	67	r: 230400, a: 230414.75, d: 0.0064%, tcr: 14, cpr: 3.875, div: 5
	68	r: 115200, a: 115207.37, d: 0.0064%, tcr: 14, cpr: 1.250, div: 31
	69	r: 57600, a: 57603.69, d: 0.0064%, tcr: 8, cpr: 3.875, div: 35
	70	r: 38400, a: 38402.46, d: 0.0064%, tcr: 14, cpr: 3.875, div: 30
	71	r: 19200, a: 19201.23, d: 0.0064%, tcr: 8, cpr: 3.875, div: 105
	72	r: 9600, a: 9600.06, d: 0.0006%, tcr: 9, cpr: 1.125, div: 643
	73	r: 4800, a: 4799.98, d: -0.0004%, tcr: 7, cpr: 2.875, div: 647
	74	r: 2400, a: 2400.02, d: 0.0008%, tcr: 9, cpr: 2.250, div: 1286
	75	r: 1200, a: 1200.00, d: 0.0000%, tcr: 14, cpr: 2.875, div: 1294
	76	r: 300, a: 300.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 7215
	77	r: 200, a: 200.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 15625
	78	r: 150, a: 150.00, d: 0.0000%, tcr: 13, cpr: 2.250, div: 14245
	79	r: 134, a: 134.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 16153
	80	r: 110, a: 110.00, d: 0.0000%, tcr: 12, cpr: 1.000, div: 47348
	81	r: 75, a: 75.00, d: 0.0000%, tcr: 4, cpr: 5.875, div: 35461
	82	r: 50, a: 50.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 62500
	83	r: 25, a: 25.00, d: 0.0000%, tcr: 16, cpr: 2.500, div: 62500
	84	r: 4, a: 4.00, d: 0.0000%, tcr: 16, cpr: 20.000, div: 48828
	85	r: 2, a: 2.00, d: 0.0000%, tcr: 16, cpr: 40.000, div: 48828
	86	r: 1, a: 1.00, d: 0.0000%, tcr: 16, cpr: 63.875, div: 61154
	87
	88	With the baud base set to 15625000 and the unsigned 16-bit UART_DIV_MAX
	89	limitation imposed by ``serial8250_get_baud_rate`` standard baud rates
	90	below 300bps become unavailable in the regular way, e.g. the rate of
	91	200bps requires the baud base to be divided by 78125 and that is beyond
	92	the unsigned 16-bit range. The historic spd_cust feature can still be
	93	used by encoding the values for, the prescaler, the oversampling rate
	94	and the clock divisor (DLM/DLL) as follows to obtain such rates if so
	95	required:
	96
	97	::
	98
	99	31 29 28 20 19 16 15 0
	100	+-----+-----------------+-------+-------------------------------+
	101	\|0 0 0\| CPR2:CPR \| TCR \| DLM:DLL \|
	102	+-----+-----------------+-------+-------------------------------+
	103
	104	Use a value such encoded for the ``custom_divisor`` field along with the
	105	ASYNC_SPD_CUST flag set in the ``flags`` field in ``struct serial_struct``
	106	passed with the TIOCSSERIAL ioctl(2), such as with the setserial(8)
	107	utility and its ``divisor`` and ``spd_cust`` parameters, and then select
	108	the baud rate of 38400bps. Note that the value of 0 in TCR sets the
	109	oversampling rate to 16 and prescaler values below 1 in CPR2/CPR are
	110	clamped by the driver to 1.
	111
	112	For example the value of 0x1f4004e2 will set CPR2/CPR, TCR and DLM/DLL
	113	respectively to 0x1f4, 0x0 and 0x04e2, choosing the prescaler value,
	114	the oversampling rate and the clock divisor of 62.500, 16 and 1250
	115	respectively. These parameters will set the baud rate for the serial
	116	port to 62500000 / 62.500 / 1250 / 16 = 50bps.
	117
	118	Maciej W. Rozycki <macro@orcam.me.uk>
	119
	120	.. [OX200] "OXPCIe200 PCI Express Multi-Port Bridge", Oxford Semiconductor,
	121	Inc., DS-0045, 10 Nov 2008, Section "950 Mode", pp. 64-65
	122
	123	.. [OX952] "OXPCIe952 PCI Express Bridge to Dual Serial & Parallel Port",
	124	Oxford Semiconductor, Inc., DS-0046, Mar 06 08, Section "950 Mode",
	125	p. 20
	126
	127	.. [OX954] "OXPCIe954 PCI Express Bridge to Quad Serial Port", Oxford
	128	Semiconductor, Inc., DS-0047, Feb 08, Section "950 Mode", p. 20
	129
	130	.. [OX958] "OXPCIe958 PCI Express Bridge to Octal Serial Port", Oxford
	131	Semiconductor, Inc., DS-0048, Feb 08, Section "950 Mode", p. 20

MAINTAINERS+1−1

@@ -13411,7 +13411,7 @@ F: drivers/net/phy/motorcomm.c · 13410 unmodified lines
13411	MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD	13411	MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD
13412	M: Jiri Slaby <jirislaby@kernel.org>	13412	M: Jiri Slaby <jirislaby@kernel.org>
13413	S: Maintained	13413	S: Maintained
13414	F: Documentation/driver-api/serial/moxa-smartio.rst	13414	F: Documentation/driver-api/tty/moxa-smartio.rst
13415	F: drivers/tty/mxser.*	13415	F: drivers/tty/mxser.*
13416		13416
13417	MR800 AVERMEDIA USB FM RADIO DRIVER	13417	MR800 AVERMEDIA USB FM RADIO DRIVER

arch/alpha/include/uapi/asm/termbits.h+79−135

@@ -2,10 +2,8 @@ · 1 unmodified line
2	#ifndef _ALPHA_TERMBITS_H	2	#ifndef _ALPHA_TERMBITS_H
3	#define _ALPHA_TERMBITS_H	3	#define _ALPHA_TERMBITS_H
4		4
5	#include <linux/posix_types.h>	5	#include <asm-generic/termbits-common.h>
6		6
7	typedef unsigned char cc_t;
8	typedef unsigned int speed_t;
9	typedef unsigned int tcflag_t;	7	typedef unsigned int tcflag_t;
10		8
11	/*	9	/*
@@ -53,76 +51,58 @@ struct ktermios { · 41 unmodified lines
53	};	51	};
54		52
55	/* c_cc characters */	53	/* c_cc characters */
56	#define VEOF 0	54	#define VEOF 0
57	#define VEOL 1	55	#define VEOL 1
58	#define VEOL2 2	56	#define VEOL2 2
59	#define VERASE 3	57	#define VERASE 3
60	#define VWERASE 4	58	#define VWERASE 4
61	#define VKILL 5	59	#define VKILL 5
62	#define VREPRINT 6	60	#define VREPRINT 6
63	#define VSWTC 7	61	#define VSWTC 7
64	#define VINTR 8	62	#define VINTR 8
65	#define VQUIT 9	63	#define VQUIT 9
66	#define VSUSP 10	64	#define VSUSP 10
67	#define VSTART 12	65	#define VSTART 12
68	#define VSTOP 13	66	#define VSTOP 13
69	#define VLNEXT 14	67	#define VLNEXT 14
70	#define VDISCARD 15	68	#define VDISCARD 15
71	#define VMIN 16	69	#define VMIN 16
72	#define VTIME 17	70	#define VTIME 17
73		71
74	/* c_iflag bits */	72	/* c_iflag bits */
75	#define IGNBRK 0000001	73	#define IXON 0x0200
76	#define BRKINT 0000002	74	#define IXOFF 0x0400
77	#define IGNPAR 0000004	75	#define IUCLC 0x1000
78	#define PARMRK 0000010	76	#define IMAXBEL 0x2000
79	#define INPCK 0000020	77	#define IUTF8 0x4000
80	#define ISTRIP 0000040
81	#define INLCR 0000100
82	#define IGNCR 0000200
83	#define ICRNL 0000400
84	#define IXON 0001000
85	#define IXOFF 0002000
86	#define IXANY 0004000
87	#define IUCLC 0010000
88	#define IMAXBEL 0020000
89	#define IUTF8 0040000
90		78
91	/* c_oflag bits */	79	/* c_oflag bits */
92	#define OPOST 0000001	80	#define ONLCR 0x00002
93	#define ONLCR 0000002	81	#define OLCUC 0x00004
94	#define OLCUC 0000004	82	#define NLDLY 0x00300
95		83	#define NL0 0x00000
96	#define OCRNL 0000010	84	#define NL1 0x00100
97	#define ONOCR 0000020	85	#define NL2 0x00200
98	#define ONLRET 0000040	86	#define NL3 0x00300
99		87	#define TABDLY 0x00c00
100	#define OFILL 00000100	88	#define TAB0 0x00000
101	#define OFDEL 00000200	89	#define TAB1 0x00400
102	#define NLDLY 00001400	90	#define TAB2 0x00800
103	#define NL0 00000000	91	#define TAB3 0x00c00
104	#define NL1 00000400	92	#define CRDLY 0x03000
105	#define NL2 00001000	93	#define CR0 0x00000
106	#define NL3 00001400	94	#define CR1 0x01000
107	#define TABDLY 00006000	95	#define CR2 0x02000
108	#define TAB0 00000000	96	#define CR3 0x03000
109	#define TAB1 00002000	97	#define FFDLY 0x04000
110	#define TAB2 00004000	98	#define FF0 0x00000
111	#define TAB3 00006000	99	#define FF1 0x04000
112	#define CRDLY 00030000	100	#define BSDLY 0x08000
113	#define CR0 00000000	101	#define BS0 0x00000
114	#define CR1 00010000	102	#define BS1 0x08000
115	#define CR2 00020000	103	#define VTDLY 0x10000
116	#define CR3 00030000	104	#define VT0 0x00000
117	#define FFDLY 00040000	105	#define VT1 0x10000
118	#define FF0 00000000
119	#define FF1 00040000
120	#define BSDLY 00100000
121	#define BS0 00000000
122	#define BS1 00100000
123	#define VTDLY 00200000
124	#define VT0 00000000
125	#define VT1 00200000
126	/*	106	/*
127	* Should be equivalent to TAB3, see description of TAB3 in	107	* Should be equivalent to TAB3, see description of TAB3 in
128	* POSIX.1-2008, Ch. 11.2.3 "Output Modes"	108	* POSIX.1-2008, Ch. 11.2.3 "Output Modes"
@@ -130,61 +110,36 @@ struct ktermios { · 1 unmodified line
130	#define XTABS TAB3	110	#define XTABS TAB3
131		111
132	/* c_cflag bit meaning */	112	/* c_cflag bit meaning */
133	#define CBAUD 0000037	113	#define CBAUD 0x0000001f
134	#define B0 0000000 /* hang up */	114	#define CBAUDEX 0x00000000
135	#define B50 0000001	115	#define BOTHER 0x0000001f
136	#define B75 0000002	116	#define B57600 0x00000010
137	#define B110 0000003	117	#define B115200 0x00000011
138	#define B134 0000004	118	#define B230400 0x00000012
139	#define B150 0000005	119	#define B460800 0x00000013
140	#define B200 0000006	120	#define B500000 0x00000014
141	#define B300 0000007	121	#define B576000 0x00000015
142	#define B600 0000010	122	#define B921600 0x00000016
143	#define B1200 0000011	123	#define B1000000 0x00000017
144	#define B1800 0000012	124	#define B1152000 0x00000018
145	#define B2400 0000013	125	#define B1500000 0x00000019
146	#define B4800 0000014	126	#define B2000000 0x0000001a
147	#define B9600 0000015	127	#define B2500000 0x0000001b
148	#define B19200 0000016	128	#define B3000000 0x0000001c
149	#define B38400 0000017	129	#define B3500000 0x0000001d
150	#define EXTA B19200	130	#define B4000000 0x0000001e
151	#define EXTB B38400	131	#define CSIZE 0x00000300
152	#define CBAUDEX 0000000	132	#define CS5 0x00000000
153	#define B57600 00020	133	#define CS6 0x00000100
154	#define B115200 00021	134	#define CS7 0x00000200
155	#define B230400 00022	135	#define CS8 0x00000300
156	#define B460800 00023	136	#define CSTOPB 0x00000400
157	#define B500000 00024	137	#define CREAD 0x00000800
158	#define B576000 00025	138	#define PARENB 0x00001000
159	#define B921600 00026	139	#define PARODD 0x00002000
160	#define B1000000 00027	140	#define HUPCL 0x00004000
161	#define B1152000 00030	141	#define CLOCAL 0x00008000
162	#define B1500000 00031	142	#define CIBAUD 0x001f0000
163	#define B2000000 00032
164	#define B2500000 00033
165	#define B3000000 00034
166	#define B3500000 00035
167	#define B4000000 00036
168	#define BOTHER 00037
169
170	#define CSIZE 00001400
171	#define CS5 00000000
172	#define CS6 00000400
173	#define CS7 00001000
174	#define CS8 00001400
175
176	#define CSTOPB 00002000
177	#define CREAD 00004000
178	#define PARENB 00010000
179	#define PARODD 00020000
180	#define HUPCL 00040000
181
182	#define CLOCAL 00100000
183	#define CMSPAR 010000000000 /* mark or space (stick) parity */
184	#define CRTSCTS 020000000000 /* flow control */
185
186	#define CIBAUD 07600000
187	#define IBSHIFT 16
188		143
189	/* c_lflag bits */	144	/* c_lflag bits */
190	#define ISIG 0x00000080	145	#define ISIG 0x00000080
@@ -204,17 +159,6 @@ struct ktermios { · 13 unmodified lines
204	#define IEXTEN 0x00000400	159	#define IEXTEN 0x00000400
205	#define EXTPROC 0x10000000	160	#define EXTPROC 0x10000000
206		161
207	/* Values for the ACTION argument to `tcflow'. */
208	#define TCOOFF 0
209	#define TCOON 1
210	#define TCIOFF 2
211	#define TCION 3
212
213	/* Values for the QUEUE_SELECTOR argument to `tcflush'. */
214	#define TCIFLUSH 0
215	#define TCOFLUSH 1
216	#define TCIOFLUSH 2
217
218	/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'. */	162	/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'. */
219	#define TCSANOW 0	163	#define TCSANOW 0
220	#define TCSADRAIN 1	164	#define TCSADRAIN 1

arch/mips/include/uapi/asm/termbits.h+99−150

@@ -11,11 +11,9 @@ · 10 unmodified lines
11	#ifndef _ASM_TERMBITS_H	11	#ifndef _ASM_TERMBITS_H
12	#define _ASM_TERMBITS_H	12	#define _ASM_TERMBITS_H
13		13
14	#include <linux/posix_types.h>	14	#include <asm-generic/termbits-common.h>
15		15
16	typedef unsigned char cc_t;	16	typedef unsigned int tcflag_t;
17	typedef unsigned int speed_t;
18	typedef unsigned int tcflag_t;
19		17
20	/*	18	/*
21	* The ABI says nothing about NCC but seems to use NCCS as	19	* The ABI says nothing about NCC but seems to use NCCS as
@@ -54,175 +52,126 @@ struct ktermios { · 32 unmodified lines
54	};	52	};
55		53
56	/* c_cc characters */	54	/* c_cc characters */
57	#define VINTR 0 /* Interrupt character [ISIG]. */	55	#define VINTR 0 /* Interrupt character [ISIG] */
58	#define VQUIT 1 /* Quit character [ISIG]. */	56	#define VQUIT 1 /* Quit character [ISIG] */
59	#define VERASE 2 /* Erase character [ICANON]. */	57	#define VERASE 2 /* Erase character [ICANON] */
60	#define VKILL 3 /* Kill-line character [ICANON]. */	58	#define VKILL 3 /* Kill-line character [ICANON] */
61	#define VMIN 4 /* Minimum number of bytes read at once [!ICANON]. */	59	#define VMIN 4 /* Minimum number of bytes read at once [!ICANON] */
62	#define VTIME 5 /* Time-out value (tenths of a second) [!ICANON]. */	60	#define VTIME 5 /* Time-out value (tenths of a second) [!ICANON] */
63	#define VEOL2 6 /* Second EOL character [ICANON]. */	61	#define VEOL2 6 /* Second EOL character [ICANON] */
64	#define VSWTC 7 /* ??? */	62	#define VSWTC 7 /* ??? */
65	#define VSWTCH VSWTC	63	#define VSWTCH VSWTC
66	#define VSTART 8 /* Start (X-ON) character [IXON, IXOFF]. */	64	#define VSTART 8 /* Start (X-ON) character [IXON, IXOFF] */
67	#define VSTOP 9 /* Stop (X-OFF) character [IXON, IXOFF]. */	65	#define VSTOP 9 /* Stop (X-OFF) character [IXON, IXOFF] */
68	#define VSUSP 10 /* Suspend character [ISIG]. */	66	#define VSUSP 10 /* Suspend character [ISIG] */
69	#if 0	67	#if 0
70	/*	68	/*
71	* VDSUSP is not supported	69	* VDSUSP is not supported
72	*/	70	*/
73	#define VDSUSP 11 /* Delayed suspend character [ISIG]. */	71	#define VDSUSP 11 /* Delayed suspend character [ISIG] */
74	#endif	72	#endif
75	#define VREPRINT 12 /* Reprint-line character [ICANON]. */	73	#define VREPRINT 12 /* Reprint-line character [ICANON] */
76	#define VDISCARD 13 /* Discard character [IEXTEN]. */	74	#define VDISCARD 13 /* Discard character [IEXTEN] */
77	#define VWERASE 14 /* Word-erase character [ICANON]. */	75	#define VWERASE 14 /* Word-erase character [ICANON] */
78	#define VLNEXT 15 /* Literal-next character [IEXTEN]. */	76	#define VLNEXT 15 /* Literal-next character [IEXTEN] */
79	#define VEOF 16 /* End-of-file character [ICANON]. */	77	#define VEOF 16 /* End-of-file character [ICANON] */
80	#define VEOL 17 /* End-of-line character [ICANON]. */	78	#define VEOL 17 /* End-of-line character [ICANON] */
81		79
82	/* c_iflag bits */	80	/* c_iflag bits */
83	#define IGNBRK 0000001 /* Ignore break condition. */	81	#define IUCLC 0x0200 /* Map upper case to lower case on input */
84	#define BRKINT 0000002 /* Signal interrupt on break. */	82	#define IXON 0x0400 /* Enable start/stop output control */
85	#define IGNPAR 0000004 /* Ignore characters with parity errors. */	83	#define IXOFF 0x1000 /* Enable start/stop input control */
86	#define PARMRK 0000010 /* Mark parity and framing errors. */	84	#define IMAXBEL 0x2000 /* Ring bell when input queue is full */
87	#define INPCK 0000020 /* Enable input parity check. */	85	#define IUTF8 0x4000 /* Input is UTF-8 */
88	#define ISTRIP 0000040 /* Strip 8th bit off characters. */
89	#define INLCR 0000100 /* Map NL to CR on input. */
90	#define IGNCR 0000200 /* Ignore CR. */
91	#define ICRNL 0000400 /* Map CR to NL on input. */
92	#define IUCLC 0001000 /* Map upper case to lower case on input. */
93	#define IXON 0002000 /* Enable start/stop output control. */
94	#define IXANY 0004000 /* Any character will restart after stop. */
95	#define IXOFF 0010000 /* Enable start/stop input control. */
96	#define IMAXBEL 0020000 /* Ring bell when input queue is full. */
97	#define IUTF8 0040000 /* Input is UTF-8 */
98		86
99	/* c_oflag bits */	87	/* c_oflag bits */
100	#define OPOST 0000001 /* Perform output processing. */	88	#define OLCUC 0x00002 /* Map lower case to upper case on output */
101	#define OLCUC 0000002 /* Map lower case to upper case on output. */	89	#define ONLCR 0x00004 /* Map NL to CR-NL on output */
102	#define ONLCR 0000004 /* Map NL to CR-NL on output. */	90	#define NLDLY 0x00100
103	#define OCRNL 0000010	91	#define NL0 0x00000
104	#define ONOCR 0000020	92	#define NL1 0x00100
105	#define ONLRET 0000040	93	#define CRDLY 0x00600
106	#define OFILL 0000100	94	#define CR0 0x00000
107	#define OFDEL 0000200	95	#define CR1 0x00200
108	#define NLDLY 0000400	96	#define CR2 0x00400
109	#define NL0 0000000	97	#define CR3 0x00600
110	#define NL1 0000400	98	#define TABDLY 0x01800
111	#define CRDLY 0003000	99	#define TAB0 0x00000
112	#define CR0 0000000	100	#define TAB1 0x00800
113	#define CR1 0001000	101	#define TAB2 0x01000
114	#define CR2 0002000	102	#define TAB3 0x01800
115	#define CR3 0003000	103	#define XTABS 0x01800
116	#define TABDLY 0014000	104	#define BSDLY 0x02000
117	#define TAB0 0000000	105	#define BS0 0x00000
118	#define TAB1 0004000	106	#define BS1 0x02000
119	#define TAB2 0010000	107	#define VTDLY 0x04000
120	#define TAB3 0014000	108	#define VT0 0x00000
121	#define XTABS 0014000	109	#define VT1 0x04000
122	#define BSDLY 0020000	110	#define FFDLY 0x08000
123	#define BS0 0000000	111	#define FF0 0x00000
124	#define BS1 0020000	112	#define FF1 0x08000
125	#define VTDLY 0040000
126	#define VT0 0000000
127	#define VT1 0040000
128	#define FFDLY 0100000
129	#define FF0 0000000
130	#define FF1 0100000
131	/*	113	/*
132	#define PAGEOUT ???	114	#define PAGEOUT ???
133	#define WRAP ???	115	#define WRAP ???
134	*/	116	*/
135		117
136	/* c_cflag bit meaning */	118	/* c_cflag bit meaning */
137	#define CBAUD 0010017	119	#define CBAUD 0x0000100f
138	#define B0 0000000 /* hang up */	120	#define CSIZE 0x00000030 /* Number of bits per byte (mask) */
139	#define B50 0000001	121	#define CS5 0x00000000 /* 5 bits per byte */
140	#define B75 0000002	122	#define CS6 0x00000010 /* 6 bits per byte */
141	#define B110 0000003	123	#define CS7 0x00000020 /* 7 bits per byte */
142	#define B134 0000004	124	#define CS8 0x00000030 /* 8 bits per byte */
143	#define B150 0000005	125	#define CSTOPB 0x00000040 /* Two stop bits instead of one */
144	#define B200 0000006	126	#define CREAD 0x00000080 /* Enable receiver */
145	#define B300 0000007	127	#define PARENB 0x00000100 /* Parity enable */
146	#define B600 0000010	128	#define PARODD 0x00000200 /* Odd parity instead of even */
147	#define B1200 0000011	129	#define HUPCL 0x00000400 /* Hang up on last close */
148	#define B1800 0000012	130	#define CLOCAL 0x00000800 /* Ignore modem status lines */
149	#define B2400 0000013	131	#define CBAUDEX 0x00001000
150	#define B4800 0000014	132	#define BOTHER 0x00001000
151	#define B9600 0000015	133	#define B57600 0x00001001
152	#define B19200 0000016	134	#define B115200 0x00001002
153	#define B38400 0000017	135	#define B230400 0x00001003
154	#define EXTA B19200	136	#define B460800 0x00001004
155	#define EXTB B38400	137	#define B500000 0x00001005
156	#define CSIZE 0000060 /* Number of bits per byte (mask). */	138	#define B576000 0x00001006
157	#define CS5 0000000 /* 5 bits per byte. */	139	#define B921600 0x00001007
158	#define CS6 0000020 /* 6 bits per byte. */	140	#define B1000000 0x00001008
159	#define CS7 0000040 /* 7 bits per byte. */	141	#define B1152000 0x00001009
160	#define CS8 0000060 /* 8 bits per byte. */	142	#define B1500000 0x0000100a
161	#define CSTOPB 0000100 /* Two stop bits instead of one. */	143	#define B2000000 0x0000100b
162	#define CREAD 0000200 /* Enable receiver. */	144	#define B2500000 0x0000100c
163	#define PARENB 0000400 /* Parity enable. */	145	#define B3000000 0x0000100d
164	#define PARODD 0001000 /* Odd parity instead of even. */	146	#define B3500000 0x0000100e
165	#define HUPCL 0002000 /* Hang up on last close. */	147	#define B4000000 0x0000100f
166	#define CLOCAL 0004000 /* Ignore modem status lines. */	148	#define CIBAUD 0x100f0000 /* input baud rate */
167	#define CBAUDEX 0010000
168	#define BOTHER 0010000
169	#define B57600 0010001
170	#define B115200 0010002
171	#define B230400 0010003
172	#define B460800 0010004
173	#define B500000 0010005
174	#define B576000 0010006
175	#define B921600 0010007
176	#define B1000000 0010010
177	#define B1152000 0010011
178	#define B1500000 0010012
179	#define B2000000 0010013
180	#define B2500000 0010014
181	#define B3000000 0010015
182	#define B3500000 0010016
183	#define B4000000 0010017
184	#define CIBAUD 002003600000 /* input baud rate */
185	#define CMSPAR 010000000000 /* mark or space (stick) parity */
186	#define CRTSCTS 020000000000 /* flow control */
187
188	#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
189		149
190	/* c_lflag bits */	150	/* c_lflag bits */
191	#define ISIG 0000001 /* Enable signals. */	151	#define ISIG 0x00001 /* Enable signals */
192	#define ICANON 0000002 /* Do erase and kill processing. */	152	#define ICANON 0x00002 /* Do erase and kill processing */
193	#define XCASE 0000004	153	#define XCASE 0x00004
194	#define ECHO 0000010 /* Enable echo. */	154	#define ECHO 0x00008 /* Enable echo */
195	#define ECHOE 0000020 /* Visual erase for ERASE. */	155	#define ECHOE 0x00010 /* Visual erase for ERASE */
196	#define ECHOK 0000040 /* Echo NL after KILL. */	156	#define ECHOK 0x00020 /* Echo NL after KILL */
197	#define ECHONL 0000100 /* Echo NL even if ECHO is off. */	157	#define ECHONL 0x00040 /* Echo NL even if ECHO is off */
198	#define NOFLSH 0000200 /* Disable flush after interrupt. */	158	#define NOFLSH 0x00080 /* Disable flush after interrupt */
199	#define IEXTEN 0000400 /* Enable DISCARD and LNEXT. */	159	#define IEXTEN 0x00100 /* Enable DISCARD and LNEXT */
200	#define ECHOCTL 0001000 /* Echo control characters as ^X. */	160	#define ECHOCTL 0x00200 /* Echo control characters as ^X */
201	#define ECHOPRT 0002000 /* Hardcopy visual erase. */	161	#define ECHOPRT 0x00400 /* Hardcopy visual erase */
202	#define ECHOKE 0004000 /* Visual erase for KILL. */	162	#define ECHOKE 0x00800 /* Visual erase for KILL */
203	#define FLUSHO 0020000	163	#define FLUSHO 0x02000
204	#define PENDIN 0040000 /* Retype pending input (state). */	164	#define PENDIN 0x04000 /* Retype pending input (state) */
205	#define TOSTOP 0100000 /* Send SIGTTOU for background output. */	165	#define TOSTOP 0x08000 /* Send SIGTTOU for background output */
206	#define ITOSTOP TOSTOP	166	#define ITOSTOP TOSTOP
207	#define EXTPROC 0200000 /* External processing on pty */	167	#define EXTPROC 0x10000 /* External processing on pty */
208		168
209	/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */	169	/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
210	#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */	170	#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
211		171
212	/* tcflow() and TCXONC use these */
213	#define TCOOFF 0 /* Suspend output. */
214	#define TCOON 1 /* Restart suspended output. */
215	#define TCIOFF 2 /* Send a STOP character. */
216	#define TCION 3 /* Send a START character. */
217
218	/* tcflush() and TCFLSH use these */
219	#define TCIFLUSH 0 /* Discard data received but not yet read. */
220	#define TCOFLUSH 1 /* Discard data written but not yet sent. */
221	#define TCIOFLUSH 2 /* Discard all pending data. */
222
223	/* tcsetattr uses these */	172	/* tcsetattr uses these */
224	#define TCSANOW TCSETS /* Change immediately. */	173	#define TCSANOW TCSETS /* Change immediately */
225	#define TCSADRAIN TCSETSW /* Change when pending output is written. */	174	#define TCSADRAIN TCSETSW /* Change when pending output is written */
226	#define TCSAFLUSH TCSETSF /* Flush pending input before changing. */	175	#define TCSAFLUSH TCSETSF /* Flush pending input before changing */
227		176
228	#endif /* _ASM_TERMBITS_H */	177	#endif /* _ASM_TERMBITS_H */

arch/parisc/include/uapi/asm/termbits.h+94−147

@@ -2,10 +2,8 @@ · 1 unmodified line
2	#ifndef __ARCH_PARISC_TERMBITS_H__	2	#ifndef __ARCH_PARISC_TERMBITS_H__
3	#define __ARCH_PARISC_TERMBITS_H__	3	#define __ARCH_PARISC_TERMBITS_H__
4		4
5	#include <linux/posix_types.h>	5	#include <asm-generic/termbits-common.h>
6		6
7	typedef unsigned char cc_t;
8	typedef unsigned int speed_t;
9	typedef unsigned int tcflag_t;	7	typedef unsigned int tcflag_t;
10		8
11	#define NCCS 19	9	#define NCCS 19
@@ -41,158 +39,107 @@ struct ktermios { · 29 unmodified lines
41	};	39	};
42		40
43	/* c_cc characters */	41	/* c_cc characters */
44	#define VINTR 0	42	#define VINTR 0
45	#define VQUIT 1	43	#define VQUIT 1
46	#define VERASE 2	44	#define VERASE 2
47	#define VKILL 3	45	#define VKILL 3
48	#define VEOF 4	46	#define VEOF 4
49	#define VTIME 5	47	#define VTIME 5
50	#define VMIN 6	48	#define VMIN 6
51	#define VSWTC 7	49	#define VSWTC 7
52	#define VSTART 8	50	#define VSTART 8
53	#define VSTOP 9	51	#define VSTOP 9
54	#define VSUSP 10	52	#define VSUSP 10
55	#define VEOL 11	53	#define VEOL 11
56	#define VREPRINT 12	54	#define VREPRINT 12
57	#define VDISCARD 13	55	#define VDISCARD 13
58	#define VWERASE 14	56	#define VWERASE 14
59	#define VLNEXT 15	57	#define VLNEXT 15
60	#define VEOL2 16	58	#define VEOL2 16
61
62		59
63	/* c_iflag bits */	60	/* c_iflag bits */
64	#define IGNBRK 0000001	61	#define IUCLC 0x0200
65	#define BRKINT 0000002	62	#define IXON 0x0400
66	#define IGNPAR 0000004	63	#define IXOFF 0x1000
67	#define PARMRK 0000010	64	#define IMAXBEL 0x4000
68	#define INPCK 0000020	65	#define IUTF8 0x8000
69	#define ISTRIP 0000040
70	#define INLCR 0000100
71	#define IGNCR 0000200
72	#define ICRNL 0000400
73	#define IUCLC 0001000
74	#define IXON 0002000
75	#define IXANY 0004000
76	#define IXOFF 0010000
77	#define IMAXBEL 0040000
78	#define IUTF8 0100000
79		66
80	/* c_oflag bits */	67	/* c_oflag bits */
81	#define OPOST 0000001	68	#define OLCUC 0x00002
82	#define OLCUC 0000002	69	#define ONLCR 0x00004
83	#define ONLCR 0000004	70	#define NLDLY 0x00100
84	#define OCRNL 0000010	71	#define NL0 0x00000
85	#define ONOCR 0000020	72	#define NL1 0x00100
86	#define ONLRET 0000040	73	#define CRDLY 0x00600
87	#define OFILL 0000100	74	#define CR0 0x00000
88	#define OFDEL 0000200	75	#define CR1 0x00200
89	#define NLDLY 0000400	76	#define CR2 0x00400
90	#define NL0 0000000	77	#define CR3 0x00600
91	#define NL1 0000400	78	#define TABDLY 0x01800
92	#define CRDLY 0003000	79	#define TAB0 0x00000
93	#define CR0 0000000	80	#define TAB1 0x00800
94	#define CR1 0001000	81	#define TAB2 0x01000
95	#define CR2 0002000	82	#define TAB3 0x01800
96	#define CR3 0003000	83	#define XTABS 0x01800
97	#define TABDLY 0014000	84	#define BSDLY 0x02000
98	#define TAB0 0000000	85	#define BS0 0x00000
99	#define TAB1 0004000	86	#define BS1 0x02000
100	#define TAB2 0010000	87	#define VTDLY 0x04000
101	#define TAB3 0014000	88	#define VT0 0x00000
102	#define XTABS 0014000	89	#define VT1 0x04000
103	#define BSDLY 0020000	90	#define FFDLY 0x08000
104	#define BS0 0000000	91	#define FF0 0x00000
105	#define BS1 0020000	92	#define FF1 0x08000
106	#define VTDLY 0040000
107	#define VT0 0000000
108	#define VT1 0040000
109	#define FFDLY 0100000
110	#define FF0 0000000
111	#define FF1 0100000
112		93
113	/* c_cflag bit meaning */	94	/* c_cflag bit meaning */
114	#define CBAUD 0010017	95	#define CBAUD 0x0000100f
115	#define B0 0000000 /* hang up */	96	#define CSIZE 0x00000030
116	#define B50 0000001	97	#define CS5 0x00000000
117	#define B75 0000002	98	#define CS6 0x00000010
118	#define B110 0000003	99	#define CS7 0x00000020
119	#define B134 0000004	100	#define CS8 0x00000030
120	#define B150 0000005	101	#define CSTOPB 0x00000040
121	#define B200 0000006	102	#define CREAD 0x00000080
122	#define B300 0000007	103	#define PARENB 0x00000100
123	#define B600 0000010	104	#define PARODD 0x00000200
124	#define B1200 0000011	105	#define HUPCL 0x00000400
125	#define B1800 0000012	106	#define CLOCAL 0x00000800
126	#define B2400 0000013	107	#define CBAUDEX 0x00001000
127	#define B4800 0000014	108	#define BOTHER 0x00001000
128	#define B9600 0000015	109	#define B57600 0x00001001
129	#define B19200 0000016	110	#define B115200 0x00001002
130	#define B38400 0000017	111	#define B230400 0x00001003
131	#define EXTA B19200	112	#define B460800 0x00001004
132	#define EXTB B38400	113	#define B500000 0x00001005
133	#define CSIZE 0000060	114	#define B576000 0x00001006
134	#define CS5 0000000	115	#define B921600 0x00001007
135	#define CS6 0000020	116	#define B1000000 0x00001008
136	#define CS7 0000040	117	#define B1152000 0x00001009
137	#define CS8 0000060	118	#define B1500000 0x0000100a
138	#define CSTOPB 0000100	119	#define B2000000 0x0000100b
139	#define CREAD 0000200	120	#define B2500000 0x0000100c
140	#define PARENB 0000400	121	#define B3000000 0x0000100d
141	#define PARODD 0001000	122	#define B3500000 0x0000100e
142	#define HUPCL 0002000	123	#define B4000000 0x0000100f
143	#define CLOCAL 0004000	124	#define CIBAUD 0x100f0000 /* input baud rate */
144	#define CBAUDEX 0010000
145	#define BOTHER 0010000
146	#define B57600 0010001
147	#define B115200 0010002
148	#define B230400 0010003
149	#define B460800 0010004
150	#define B500000 0010005
151	#define B576000 0010006
152	#define B921600 0010007
153	#define B1000000 0010010
154	#define B1152000 0010011
155	#define B1500000 0010012
156	#define B2000000 0010013
157	#define B2500000 0010014
158	#define B3000000 0010015
159	#define B3500000 0010016
160	#define B4000000 0010017
161	#define CIBAUD 002003600000 /* input baud rate */
162	#define CMSPAR 010000000000 /* mark or space (stick) parity */
163	#define CRTSCTS 020000000000 /* flow control */
164
165	#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
166
167		125
168	/* c_lflag bits */	126	/* c_lflag bits */
169	#define ISIG 0000001	127	#define ISIG 0x00001
170	#define ICANON 0000002	128	#define ICANON 0x00002
171	#define XCASE 0000004	129	#define XCASE 0x00004
172	#define ECHO 0000010	130	#define ECHO 0x00008
173	#define ECHOE 0000020	131	#define ECHOE 0x00010
174	#define ECHOK 0000040	132	#define ECHOK 0x00020
175	#define ECHONL 0000100	133	#define ECHONL 0x00040
176	#define NOFLSH 0000200	134	#define NOFLSH 0x00080
177	#define TOSTOP 0000400	135	#define TOSTOP 0x00100
178	#define ECHOCTL 0001000	136	#define ECHOCTL 0x00200
179	#define ECHOPRT 0002000	137	#define ECHOPRT 0x00400
180	#define ECHOKE 0004000	138	#define ECHOKE 0x00800
181	#define FLUSHO 0010000	139	#define FLUSHO 0x01000
182	#define PENDIN 0040000	140	#define PENDIN 0x04000
183	#define IEXTEN 0100000	141	#define IEXTEN 0x08000
184	#define EXTPROC 0200000	142	#define EXTPROC 0x10000
185
186	/* tcflow() and TCXONC use these */
187	#define TCOOFF 0
188	#define TCOON 1
189	#define TCIOFF 2
190	#define TCION 3
191
192	/* tcflush() and TCFLSH use these */
193	#define TCIFLUSH 0
194	#define TCOFLUSH 1
195	#define TCIOFLUSH 2
196		143
197	/* tcsetattr uses these */	144	/* tcsetattr uses these */
198	#define TCSANOW 0	145	#define TCSANOW 0

arch/powerpc/include/uapi/asm/termbits.h+64−118

@@ -9,8 +9,8 @@ · 8 unmodified lines
9	* 2 of the License, or (at your option) any later version.	9	* 2 of the License, or (at your option) any later version.
10	*/	10	*/
11		11
12	typedef unsigned char cc_t;	12	#include <asm-generic/termbits-common.h>
13	typedef unsigned int speed_t;	13
14	typedef unsigned int tcflag_t;	14	typedef unsigned int tcflag_t;
15		15
16	/*	16	/*
@@ -64,115 +64,72 @@ struct ktermios { · 47 unmodified lines
64	#define VDISCARD 16	64	#define VDISCARD 16
65		65
66	/* c_iflag bits */	66	/* c_iflag bits */
67	#define IGNBRK 0000001	67	#define IXON 0x0200
68	#define BRKINT 0000002	68	#define IXOFF 0x0400
69	#define IGNPAR 0000004	69	#define IUCLC 0x1000
70	#define PARMRK 0000010	70	#define IMAXBEL 0x2000
71	#define INPCK 0000020	71	#define IUTF8 0x4000
72	#define ISTRIP 0000040
73	#define INLCR 0000100
74	#define IGNCR 0000200
75	#define ICRNL 0000400
76	#define IXON 0001000
77	#define IXOFF 0002000
78	#define IXANY 0004000
79	#define IUCLC 0010000
80	#define IMAXBEL 0020000
81	#define IUTF8 0040000
82		72
83	/* c_oflag bits */	73	/* c_oflag bits */
84	#define OPOST 0000001	74	#define ONLCR 0x00002
85	#define ONLCR 0000002	75	#define OLCUC 0x00004
86	#define OLCUC 0000004	76	#define NLDLY 0x00300
87		77	#define NL0 0x00000
88	#define OCRNL 0000010	78	#define NL1 0x00100
89	#define ONOCR 0000020	79	#define NL2 0x00200
90	#define ONLRET 0000040	80	#define NL3 0x00300
91		81	#define TABDLY 0x00c00
92	#define OFILL 00000100	82	#define TAB0 0x00000
93	#define OFDEL 00000200	83	#define TAB1 0x00400
94	#define NLDLY 00001400	84	#define TAB2 0x00800
95	#define NL0 00000000	85	#define TAB3 0x00c00
96	#define NL1 00000400	86	#define XTABS 0x00c00 /* required by POSIX to == TAB3 */
97	#define NL2 00001000	87	#define CRDLY 0x03000
98	#define NL3 00001400	88	#define CR0 0x00000
99	#define TABDLY 00006000	89	#define CR1 0x01000
100	#define TAB0 00000000	90	#define CR2 0x02000
101	#define TAB1 00002000	91	#define CR3 0x03000
102	#define TAB2 00004000	92	#define FFDLY 0x04000
103	#define TAB3 00006000	93	#define FF0 0x00000
104	#define XTABS 00006000 /* required by POSIX to == TAB3 */	94	#define FF1 0x04000
105	#define CRDLY 00030000	95	#define BSDLY 0x08000
106	#define CR0 00000000	96	#define BS0 0x00000
107	#define CR1 00010000	97	#define BS1 0x08000
108	#define CR2 00020000	98	#define VTDLY 0x10000
109	#define CR3 00030000	99	#define VT0 0x00000
110	#define FFDLY 00040000	100	#define VT1 0x10000
111	#define FF0 00000000
112	#define FF1 00040000
113	#define BSDLY 00100000
114	#define BS0 00000000
115	#define BS1 00100000
116	#define VTDLY 00200000
117	#define VT0 00000000
118	#define VT1 00200000
119		101
120	/* c_cflag bit meaning */	102	/* c_cflag bit meaning */
121	#define CBAUD 0000377	103	#define CBAUD 0x000000ff
122	#define B0 0000000 /* hang up */	104	#define CBAUDEX 0x00000000
123	#define B50 0000001	105	#define BOTHER 0x0000001f
124	#define B75 0000002	106	#define B57600 0x00000010
125	#define B110 0000003	107	#define B115200 0x00000011
126	#define B134 0000004	108	#define B230400 0x00000012
127	#define B150 0000005	109	#define B460800 0x00000013
128	#define B200 0000006	110	#define B500000 0x00000014
129	#define B300 0000007	111	#define B576000 0x00000015
130	#define B600 0000010	112	#define B921600 0x00000016
131	#define B1200 0000011	113	#define B1000000 0x00000017
132	#define B1800 0000012	114	#define B1152000 0x00000018
133	#define B2400 0000013	115	#define B1500000 0x00000019
134	#define B4800 0000014	116	#define B2000000 0x0000001a
135	#define B9600 0000015	117	#define B2500000 0x0000001b
136	#define B19200 0000016	118	#define B3000000 0x0000001c
137	#define B38400 0000017	119	#define B3500000 0x0000001d
138	#define EXTA B19200	120	#define B4000000 0x0000001e
139	#define EXTB B38400	121	#define CSIZE 0x00000300
140	#define CBAUDEX 0000000	122	#define CS5 0x00000000
141	#define B57600 00020	123	#define CS6 0x00000100
142	#define B115200 00021	124	#define CS7 0x00000200
143	#define B230400 00022	125	#define CS8 0x00000300
144	#define B460800 00023	126	#define CSTOPB 0x00000400
145	#define B500000 00024	127	#define CREAD 0x00000800
146	#define B576000 00025	128	#define PARENB 0x00001000
147	#define B921600 00026	129	#define PARODD 0x00002000
148	#define B1000000 00027	130	#define HUPCL 0x00004000
149	#define B1152000 00030	131	#define CLOCAL 0x00008000
150	#define B1500000 00031	132	#define CIBAUD 0x00ff0000
151	#define B2000000 00032
152	#define B2500000 00033
153	#define B3000000 00034
154	#define B3500000 00035
155	#define B4000000 00036
156	#define BOTHER 00037
157
158	#define CIBAUD 077600000
159	#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
160
161	#define CSIZE 00001400
162	#define CS5 00000000
163	#define CS6 00000400
164	#define CS7 00001000
165	#define CS8 00001400
166
167	#define CSTOPB 00002000
168	#define CREAD 00004000
169	#define PARENB 00010000
170	#define PARODD 00020000
171	#define HUPCL 00040000
172
173	#define CLOCAL 00100000
174	#define CMSPAR 010000000000 /* mark or space (stick) parity */
175	#define CRTSCTS 020000000000 /* flow control */
176		133
177	/* c_lflag bits */	134	/* c_lflag bits */
178	#define ISIG 0x00000080	135	#define ISIG 0x00000080
@@ -192,17 +149,6 @@ struct ktermios { · 13 unmodified lines
192	#define IEXTEN 0x00000400	149	#define IEXTEN 0x00000400
193	#define EXTPROC 0x10000000	150	#define EXTPROC 0x10000000
194		151
195	/* Values for the ACTION argument to `tcflow'. */
196	#define TCOOFF 0
197	#define TCOON 1
198	#define TCIOFF 2
199	#define TCION 3
200
201	/* Values for the QUEUE_SELECTOR argument to `tcflush'. */
202	#define TCIFLUSH 0
203	#define TCOFLUSH 1
204	#define TCIOFLUSH 2
205
206	/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'. */	152	/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'. */
207	#define TCSANOW 0	153	#define TCSANOW 0
208	#define TCSADRAIN 1	154	#define TCSADRAIN 1

arch/sparc/include/uapi/asm/termbits.h+84−139

@@ -2,15 +2,12 @@ · 1 unmodified line
2	#ifndef _UAPI_SPARC_TERMBITS_H	2	#ifndef _UAPI_SPARC_TERMBITS_H
3	#define _UAPI_SPARC_TERMBITS_H	3	#define _UAPI_SPARC_TERMBITS_H
4		4
5	#include <linux/posix_types.h>	5	#include <asm-generic/termbits-common.h>
6
7	typedef unsigned char cc_t;
8	typedef unsigned int speed_t;
9		6
10	#if defined(__sparc__) && defined(__arch64__)	7	#if defined(__sparc__) && defined(__arch64__)
11	typedef unsigned int tcflag_t;	8	typedef unsigned int tcflag_t;
12	#else	9	#else
13	typedef unsigned long tcflag_t;	10	typedef unsigned long tcflag_t;
14	#endif	11	#endif
15		12
16	#define NCC 8	13	#define NCC 8
@@ -61,21 +58,19 @@ struct ktermios { · 44 unmodified lines
61	};	58	};
62		59
63	/* c_cc characters */	60	/* c_cc characters */
64	#define VINTR 0	61	#define VINTR 0
65	#define VQUIT 1	62	#define VQUIT 1
66	#define VERASE 2	63	#define VERASE 2
67	#define VKILL 3	64	#define VKILL 3
68	#define VEOF 4	65	#define VEOF 4
69	#define VEOL 5	66	#define VEOL 5
70	#define VEOL2 6	67	#define VEOL2 6
71	#define VSWTC 7	68	#define VSWTC 7
72	#define VSTART 8	69	#define VSTART 8
73	#define VSTOP 9	70	#define VSTOP 9
74
75
76		71
77	#define VSUSP 10	72	#define VSUSP 10
78	#define VDSUSP 11 /* SunOS POSIX nicety I do believe... */	73	#define VDSUSP 11 /* SunOS POSIX nicety I do believe... */
79	#define VREPRINT 12	74	#define VREPRINT 12
80	#define VDISCARD 13	75	#define VDISCARD 13
81	#define VWERASE 14	76	#define VWERASE 14
@@ -90,121 +85,83 @@ struct ktermios { · 8 unmodified lines
90	#endif	85	#endif
91		86
92	/* c_iflag bits */	87	/* c_iflag bits */
93	#define IGNBRK 0x00000001	88	#define IUCLC 0x0200
94	#define BRKINT 0x00000002	89	#define IXON 0x0400
95	#define IGNPAR 0x00000004	90	#define IXOFF 0x1000
96	#define PARMRK 0x00000008	91	#define IMAXBEL 0x2000
97	#define INPCK 0x00000010	92	#define IUTF8 0x4000
98	#define ISTRIP 0x00000020
99	#define INLCR 0x00000040
100	#define IGNCR 0x00000080
101	#define ICRNL 0x00000100
102	#define IUCLC 0x00000200
103	#define IXON 0x00000400
104	#define IXANY 0x00000800
105	#define IXOFF 0x00001000
106	#define IMAXBEL 0x00002000
107	#define IUTF8 0x00004000
108		93
109	/* c_oflag bits */	94	/* c_oflag bits */
110	#define OPOST 0x00000001	95	#define OLCUC 0x00002
111	#define OLCUC 0x00000002	96	#define ONLCR 0x00004
112	#define ONLCR 0x00000004	97	#define NLDLY 0x00100
113	#define OCRNL 0x00000008	98	#define NL0 0x00000
114	#define ONOCR 0x00000010	99	#define NL1 0x00100
115	#define ONLRET 0x00000020	100	#define CRDLY 0x00600
116	#define OFILL 0x00000040	101	#define CR0 0x00000
117	#define OFDEL 0x00000080	102	#define CR1 0x00200
118	#define NLDLY 0x00000100	103	#define CR2 0x00400
119	#define NL0 0x00000000	104	#define CR3 0x00600
120	#define NL1 0x00000100	105	#define TABDLY 0x01800
121	#define CRDLY 0x00000600	106	#define TAB0 0x00000
122	#define CR0 0x00000000	107	#define TAB1 0x00800
123	#define CR1 0x00000200	108	#define TAB2 0x01000
124	#define CR2 0x00000400	109	#define TAB3 0x01800
125	#define CR3 0x00000600	110	#define XTABS 0x01800
126	#define TABDLY 0x00001800	111	#define BSDLY 0x02000
127	#define TAB0 0x00000000	112	#define BS0 0x00000
128	#define TAB1 0x00000800	113	#define BS1 0x02000
129	#define TAB2 0x00001000	114	#define VTDLY 0x04000
130	#define TAB3 0x00001800	115	#define VT0 0x00000
131	#define XTABS 0x00001800	116	#define VT1 0x04000
132	#define BSDLY 0x00002000	117	#define FFDLY 0x08000
133	#define BS0 0x00000000	118	#define FF0 0x00000
134	#define BS1 0x00002000	119	#define FF1 0x08000
135	#define VTDLY 0x00004000	120	#define PAGEOUT 0x10000 /* SUNOS specific */
136	#define VT0 0x00000000	121	#define WRAP 0x20000 /* SUNOS specific */
137	#define VT1 0x00004000
138	#define FFDLY 0x00008000
139	#define FF0 0x00000000
140	#define FF1 0x00008000
141	#define PAGEOUT 0x00010000 /* SUNOS specific */
142	#define WRAP 0x00020000 /* SUNOS specific */
143		122
144	/* c_cflag bit meaning */	123	/* c_cflag bit meaning */
145	#define CBAUD 0x0000100f	124	#define CBAUD 0x0000100f
146	#define B0 0x00000000 /* hang up */	125	#define CSIZE 0x00000030
147	#define B50 0x00000001	126	#define CS5 0x00000000
148	#define B75 0x00000002	127	#define CS6 0x00000010
149	#define B110 0x00000003	128	#define CS7 0x00000020
150	#define B134 0x00000004	129	#define CS8 0x00000030
151	#define B150 0x00000005	130	#define CSTOPB 0x00000040
152	#define B200 0x00000006	131	#define CREAD 0x00000080
153	#define B300 0x00000007	132	#define PARENB 0x00000100
154	#define B600 0x00000008	133	#define PARODD 0x00000200
155	#define B1200 0x00000009	134	#define HUPCL 0x00000400
156	#define B1800 0x0000000a	135	#define CLOCAL 0x00000800
157	#define B2400 0x0000000b	136	#define CBAUDEX 0x00001000
158	#define B4800 0x0000000c
159	#define B9600 0x0000000d
160	#define B19200 0x0000000e
161	#define B38400 0x0000000f
162	#define EXTA B19200
163	#define EXTB B38400
164	#define CSIZE 0x00000030
165	#define CS5 0x00000000
166	#define CS6 0x00000010
167	#define CS7 0x00000020
168	#define CS8 0x00000030
169	#define CSTOPB 0x00000040
170	#define CREAD 0x00000080
171	#define PARENB 0x00000100
172	#define PARODD 0x00000200
173	#define HUPCL 0x00000400
174	#define CLOCAL 0x00000800
175	#define CBAUDEX 0x00001000
176	/* We'll never see these speeds with the Zilogs, but for completeness... */	137	/* We'll never see these speeds with the Zilogs, but for completeness... */
177	#define BOTHER 0x00001000	138	#define BOTHER 0x00001000
178	#define B57600 0x00001001	139	#define B57600 0x00001001
179	#define B115200 0x00001002	140	#define B115200 0x00001002
180	#define B230400 0x00001003	141	#define B230400 0x00001003
181	#define B460800 0x00001004	142	#define B460800 0x00001004
182	/* This is what we can do with the Zilogs. */	143	/* This is what we can do with the Zilogs. */
183	#define B76800 0x00001005	144	#define B76800 0x00001005
184	/* This is what we can do with the SAB82532. */	145	/* This is what we can do with the SAB82532. */
185	#define B153600 0x00001006	146	#define B153600 0x00001006
186	#define B307200 0x00001007	147	#define B307200 0x00001007
187	#define B614400 0x00001008	148	#define B614400 0x00001008
188	#define B921600 0x00001009	149	#define B921600 0x00001009
189	/* And these are the rest... */	150	/* And these are the rest... */
190	#define B500000 0x0000100a	151	#define B500000 0x0000100a
191	#define B576000 0x0000100b	152	#define B576000 0x0000100b
192	#define B1000000 0x0000100c	153	#define B1000000 0x0000100c
193	#define B1152000 0x0000100d	154	#define B1152000 0x0000100d
194	#define B1500000 0x0000100e	155	#define B1500000 0x0000100e
195	#define B2000000 0x0000100f	156	#define B2000000 0x0000100f
196	/* These have totally bogus values and nobody uses them	157	/* These have totally bogus values and nobody uses them
197	so far. Later on we'd have to use say 0x10000x and	158	so far. Later on we'd have to use say 0x10000x and
198	adjust CBAUD constant and drivers accordingly.	159	adjust CBAUD constant and drivers accordingly.
199	#define B2500000 0x00001010	160	#define B2500000 0x00001010
200	#define B3000000 0x00001011	161	#define B3000000 0x00001011
201	#define B3500000 0x00001012	162	#define B3500000 0x00001012
202	#define B4000000 0x00001013 */	163	#define B4000000 0x00001013 */
203	#define CIBAUD 0x100f0000 /* input baud rate (not used) */	164	#define CIBAUD 0x100f0000 /* input baud rate (not used) */
204	#define CMSPAR 0x40000000 /* mark or space (stick) parity */
205	#define CRTSCTS 0x80000000 /* flow control */
206
207	#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
208		165
209	/* c_lflag bits */	166	/* c_lflag bits */
210	#define ISIG 0x00000001	167	#define ISIG 0x00000001
@@ -219,7 +176,7 @@ struct ktermios { · 8 unmodified lines
219	#define ECHOCTL 0x00000200	176	#define ECHOCTL 0x00000200
220	#define ECHOPRT 0x00000400	177	#define ECHOPRT 0x00000400
221	#define ECHOKE 0x00000800	178	#define ECHOKE 0x00000800
222	#define DEFECHO 0x00001000 /* SUNOS thing, what is it? */	179	#define DEFECHO 0x00001000 /* SUNOS thing, what is it? */
223	#define FLUSHO 0x00002000	180	#define FLUSHO 0x00002000
224	#define PENDIN 0x00004000	181	#define PENDIN 0x00004000
225	#define IEXTEN 0x00008000	182	#define IEXTEN 0x00008000
@@ -244,21 +201,9 @@ struct ktermios { · 18 unmodified lines
244	/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */	201	/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
245	#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */	202	#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
246		203
247
248	/* tcflow() and TCXONC use these */
249	#define TCOOFF 0
250	#define TCOON 1
251	#define TCIOFF 2
252	#define TCION 3
253
254	/* tcflush() and TCFLSH use these */
255	#define TCIFLUSH 0
256	#define TCOFLUSH 1
257	#define TCIOFLUSH 2
258
259	/* tcsetattr uses these */	204	/* tcsetattr uses these */
260	#define TCSANOW 0	205	#define TCSANOW 0
261	#define TCSADRAIN 1	206	#define TCSADRAIN 1
262	#define TCSAFLUSH 2	207	#define TCSAFLUSH 2
263		208
264	#endif /* _UAPI_SPARC_TERMBITS_H */	209	#endif /* _UAPI_SPARC_TERMBITS_H */

drivers/char/Kconfig+2−1

@@ -18,7 +18,8 @@ config TTY_PRINTK · 17 unmodified lines
18	The feature is useful to inline user messages with kernel	18	The feature is useful to inline user messages with kernel
19	messages.	19	messages.
20	In order to use this feature, you should output user messages	20	In order to use this feature, you should output user messages
21	to /dev/ttyprintk or redirect console to this TTY.	21	to /dev/ttyprintk or redirect console to this TTY, or boot
		22	the kernel with console=ttyprintk.
22		23
23	If unsure, say N.	24	If unsure, say N.
24		25

drivers/char/pcmcia/synclink_cs.c+5−3

@@ -1418,7 +1418,11 @@ static void mgslpc_change_params(MGSLPC_INFO info, struct tty_struct tty) · 1417 unmodified lines
1418	info->serial_signals &= ~(SerialSignal_RTS \| SerialSignal_DTR);	1418	info->serial_signals &= ~(SerialSignal_RTS \| SerialSignal_DTR);
1419		1419
1420	/* byte size and parity */	1420	/* byte size and parity */
1421		1421	if ((cflag & CSIZE) != CS8) {
		1422	cflag &= ~CSIZE;
		1423	cflag \|= CS7;
		1424	tty->termios.c_cflag = cflag;
		1425	}
1422	info->params.data_bits = tty_get_char_size(cflag);	1426	info->params.data_bits = tty_get_char_size(cflag);
1423		1427
1424	if (cflag & CSTOPB)	1428	if (cflag & CSTOPB)
@@ -1432,10 +1436,8 @@ static void mgslpc_change_params(MGSLPC_INFO info, struct tty_struct tty) · 7 unmodified lines
1432	info->params.parity = ASYNC_PARITY_ODD;	1436	info->params.parity = ASYNC_PARITY_ODD;
1433	else	1437	else
1434	info->params.parity = ASYNC_PARITY_EVEN;	1438	info->params.parity = ASYNC_PARITY_EVEN;
1435	#ifdef CMSPAR
1436	if (cflag & CMSPAR)	1439	if (cflag & CMSPAR)
1437	info->params.parity = ASYNC_PARITY_SPACE;	1440	info->params.parity = ASYNC_PARITY_SPACE;
1438	#endif
1439	}	1441	}
1440		1442
1441	/* calculate number of jiffies to transmit a full	1443	/* calculate number of jiffies to transmit a full

drivers/char/ttyprintk.c+16−0

  * of the boot process, for example.
  */
+#include <linux/console.h>
 #include <linux/device.h>
 #include <linux/serial.h>
 #include <linux/tty.h>
 static struct tty_driver *ttyprintk_driver;
+static struct tty_driver *ttyprintk_console_device(struct console *c,
+						   int *index)
+{
+	*index = 0;
+	return ttyprintk_driver;
+}
+static struct console ttyprintk_console = {
+	.name = "ttyprintk",
+	.device = ttyprintk_console_device,
+};
 static int __init ttyprintk_init(void)
 {
 	int ret;
 		goto error;
 	}
+	register_console(&ttyprintk_console);
 	return 0;
 error:
 static void __exit ttyprintk_exit(void)
 {
+	unregister_console(&ttyprintk_console);
 	tty_unregister_driver(ttyprintk_driver);
 	tty_driver_kref_put(ttyprintk_driver);
 	tty_port_destroy(&tpk_port.port);

drivers/tty/amiserial.c+0−2

 	}
 	if (!(cflag & PARODD))
 		cval |= UART_LCR_EPAR;
-#ifdef CMSPAR
 	if (cflag & CMSPAR)
 		cval |= UART_LCR_SPAR;
-#endif
 	/* Determine divisor based on baud rate */
 	baud = tty_get_baud_rate(tty);

drivers/tty/goldfish.c+2−0

 err_tty_register_device_failed:
 	free_irq(irq, qtty);
 err_dec_line_count:
+	tty_port_destroy(&qtty->port);
 	goldfish_tty_current_line_count--;
 	if (goldfish_tty_current_line_count == 0)
 		goldfish_tty_delete_driver();
 	iounmap(qtty->base);
 	qtty->base = NULL;
 	free_irq(qtty->irq, pdev);
+	tty_port_destroy(&qtty->port);
 	goldfish_tty_current_line_count--;
 	if (goldfish_tty_current_line_count == 0)
 		goldfish_tty_delete_driver();

drivers/tty/hvc/Kconfig+19−0

@@ -87,6 +87,25 @@ config HVC_DCC · 86 unmodified lines
87	driver. This console is used through a JTAG only on ARM. If you don't have	87	driver. This console is used through a JTAG only on ARM. If you don't have
88	a JTAG then you probably don't want this option.	88	a JTAG then you probably don't want this option.
89		89
		90	config HVC_DCC_SERIALIZE_SMP
		91	bool "Use DCC only on CPU core 0"
		92	depends on SMP && HVC_DCC
		93	help
		94	This is a DEBUG option to serialize all console input and output to CPU 0.
		95	Some external debuggers, do not handle reads/writes from/to DCC on more
		96	than one CPU core. Each core has its own DCC device registers, so when a
		97	CPU core reads or writes from/to DCC, it only accesses its own DCC device.
		98	Since kernel code can run on any CPU core, every time the kernel wants to
		99	write to the console, it might write to a different DCC.
		100
		101	In SMP mode, external debuggers create multiple windows, and each window
		102	shows the DCC output only from that core's DCC. The result is that
		103	console output is either lost or scattered across windows.
		104
		105	Enable this option only if you are sure that you do not need features like
		106	CPU hotplug to work. For example, during early chipset bringups without
		107	debug serial console support. If unsure, say N.
		108
90	config HVC_RISCV_SBI	109	config HVC_RISCV_SBI
91	bool "RISC-V SBI console support"	110	bool "RISC-V SBI console support"
92	depends on RISCV_SBI_V01	111	depends on RISCV_SBI_V01

drivers/tty/hvc/hvc_dcc.c+190−4

@@ -1,10 +1,15 @@
1	// SPDX-License-Identifier: GPL-2.0	1	// SPDX-License-Identifier: GPL-2.0
2	/* Copyright (c) 2010, 2014 The Linux Foundation. All rights reserved. */	2	/* Copyright (c) 2010, 2014, 2022 The Linux Foundation. All rights reserved. */
3		3
4	#include <linux/console.h>	4	#include <linux/console.h>
		5	#include <linux/cpu.h>
		6	#include <linux/cpumask.h>
5	#include <linux/init.h>	7	#include <linux/init.h>
		8	#include <linux/kfifo.h>
6	#include <linux/serial.h>	9	#include <linux/serial.h>
7	#include <linux/serial_core.h>	10	#include <linux/serial_core.h>
		11	#include <linux/smp.h>
		12	#include <linux/spinlock.h>
8		13
9	#include <asm/dcc.h>	14	#include <asm/dcc.h>
10	#include <asm/processor.h>	15	#include <asm/processor.h>
@@ -15,6 +20,15 @@ · 4 unmodified lines
15	#define DCC_STATUS_RX (1 << 30)	20	#define DCC_STATUS_RX (1 << 30)
16	#define DCC_STATUS_TX (1 << 29)	21	#define DCC_STATUS_TX (1 << 29)
17		22
		23	#define DCC_INBUF_SIZE 128
		24	#define DCC_OUTBUF_SIZE 1024
		25
		26	/* Lock to serialize access to DCC fifo */
		27	static DEFINE_SPINLOCK(dcc_lock);
		28
		29	static DEFINE_KFIFO(inbuf, unsigned char, DCC_INBUF_SIZE);
		30	static DEFINE_KFIFO(outbuf, unsigned char, DCC_OUTBUF_SIZE);
		31
18	static void dcc_uart_console_putchar(struct uart_port *port, unsigned char ch)	32	static void dcc_uart_console_putchar(struct uart_port *port, unsigned char ch)
19	{	33	{
20	while (__dcc_getstatus() & DCC_STATUS_TX)	34	while (__dcc_getstatus() & DCC_STATUS_TX)
@@ -67,24 +81,176 @@ static int hvc_dcc_get_chars(uint32_t vt, char *buf, int count) · 46 unmodified lines
67	return i;	81	return i;
68	}	82	}
69		83
		84	/*
		85	* Check if the DCC is enabled. If CONFIG_HVC_DCC_SERIALIZE_SMP is enabled,
		86	* then we assume then this function will be called first on core0. That way,
		87	* dcc_core0_available will be true only if it's available on core0.
		88	*/
70	static bool hvc_dcc_check(void)	89	static bool hvc_dcc_check(void)
71	{	90	{
72	unsigned long time = jiffies + (HZ / 10);	91	unsigned long time = jiffies + (HZ / 10);
		92	static bool dcc_core0_available;
		93
		94	/*
		95	* If we're not on core 0, but we previously confirmed that DCC is
		96	* active, then just return true.
		97	*/
		98	int cpu = get_cpu();
		99
		100	if (IS_ENABLED(CONFIG_HVC_DCC_SERIALIZE_SMP) && cpu && dcc_core0_available) {
		101	put_cpu();
		102	return true;
		103	}
		104
		105	put_cpu();
73		106
74	/* Write a test character to check if it is handled */	107	/* Write a test character to check if it is handled */
75	__dcc_putchar('\n');	108	__dcc_putchar('\n');
76		109
77	while (time_is_after_jiffies(time)) {	110	while (time_is_after_jiffies(time)) {
78	if (!(__dcc_getstatus() & DCC_STATUS_TX))	111	if (!(__dcc_getstatus() & DCC_STATUS_TX)) {
		112	dcc_core0_available = true;
79	return true;	113	return true;
		114	}
80	}	115	}
81		116
82	return false;	117	return false;
83	}	118	}
84		119
		120	/*
		121	* Workqueue function that writes the output FIFO to the DCC on core 0.
		122	*/
		123	static void dcc_put_work(struct work_struct *work)
		124	{
		125	unsigned char ch;
		126	unsigned long irqflags;
		127
		128	spin_lock_irqsave(&dcc_lock, irqflags);
		129
		130	/* While there's data in the output FIFO, write it to the DCC */
		131	while (kfifo_get(&outbuf, &ch))
		132	hvc_dcc_put_chars(0, &ch, 1);
		133
		134	/* While we're at it, check for any input characters */
		135	while (!kfifo_is_full(&inbuf)) {
		136	if (!hvc_dcc_get_chars(0, &ch, 1))
		137	break;
		138	kfifo_put(&inbuf, ch);
		139	}
		140
		141	spin_unlock_irqrestore(&dcc_lock, irqflags);
		142	}
		143
		144	static DECLARE_WORK(dcc_pwork, dcc_put_work);
		145
		146	/*
		147	* Workqueue function that reads characters from DCC and puts them into the
		148	* input FIFO.
		149	*/
		150	static void dcc_get_work(struct work_struct *work)
		151	{
		152	unsigned char ch;
		153	unsigned long irqflags;
		154
		155	/*
		156	* Read characters from DCC and put them into the input FIFO, as
		157	* long as there is room and we have characters to read.
		158	*/
		159	spin_lock_irqsave(&dcc_lock, irqflags);
		160
		161	while (!kfifo_is_full(&inbuf)) {
		162	if (!hvc_dcc_get_chars(0, &ch, 1))
		163	break;
		164	kfifo_put(&inbuf, ch);
		165	}
		166	spin_unlock_irqrestore(&dcc_lock, irqflags);
		167	}
		168
		169	static DECLARE_WORK(dcc_gwork, dcc_get_work);
		170
		171	/*
		172	* Write characters directly to the DCC if we're on core 0 and the FIFO
		173	* is empty, or write them to the FIFO if we're not.
		174	*/
		175	static int hvc_dcc0_put_chars(u32 vt, const char *buf, int count)
		176	{
		177	int len;
		178	unsigned long irqflags;
		179
		180	if (!IS_ENABLED(CONFIG_HVC_DCC_SERIALIZE_SMP))
		181	return hvc_dcc_put_chars(vt, buf, count);
		182
		183	spin_lock_irqsave(&dcc_lock, irqflags);
		184	if (smp_processor_id() \|\| (!kfifo_is_empty(&outbuf))) {
		185	len = kfifo_in(&outbuf, buf, count);
		186	spin_unlock_irqrestore(&dcc_lock, irqflags);
		187
		188	/*
		189	* We just push data to the output FIFO, so schedule the
		190	* workqueue that will actually write that data to DCC.
		191	* CPU hotplug is disabled in dcc_init so CPU0 cannot be
		192	* offlined after the cpu online check.
		193	*/
		194	if (cpu_online(0))
		195	schedule_work_on(0, &dcc_pwork);
		196
		197	return len;
		198	}
		199
		200	/*
		201	* If we're already on core 0, and the FIFO is empty, then just
		202	* write the data to DCC.
		203	*/
		204	len = hvc_dcc_put_chars(vt, buf, count);
		205	spin_unlock_irqrestore(&dcc_lock, irqflags);
		206
		207	return len;
		208	}
		209
		210	/*
		211	* Read characters directly from the DCC if we're on core 0 and the FIFO
		212	* is empty, or read them from the FIFO if we're not.
		213	*/
		214	static int hvc_dcc0_get_chars(u32 vt, char *buf, int count)
		215	{
		216	int len;
		217	unsigned long irqflags;
		218
		219	if (!IS_ENABLED(CONFIG_HVC_DCC_SERIALIZE_SMP))
		220	return hvc_dcc_get_chars(vt, buf, count);
		221
		222	spin_lock_irqsave(&dcc_lock, irqflags);
		223
		224	if (smp_processor_id() \|\| (!kfifo_is_empty(&inbuf))) {
		225	len = kfifo_out(&inbuf, buf, count);
		226	spin_unlock_irqrestore(&dcc_lock, irqflags);
		227
		228	/*
		229	* If the FIFO was empty, there may be characters in the DCC
		230	* that we haven't read yet. Schedule a workqueue to fill
		231	* the input FIFO, so that the next time this function is
		232	* called, we'll have data. CPU hotplug is disabled in dcc_init
		233	* so CPU0 cannot be offlined after the cpu online check.
		234	*/
		235	if (!len && cpu_online(0))
		236	schedule_work_on(0, &dcc_gwork);
		237
		238	return len;
		239	}
		240
		241	/*
		242	* If we're already on core 0, and the FIFO is empty, then just
		243	* read the data from DCC.
		244	*/
		245	len = hvc_dcc_get_chars(vt, buf, count);
		246	spin_unlock_irqrestore(&dcc_lock, irqflags);
		247
		248	return len;
		249	}
		250
85	static const struct hv_ops hvc_dcc_get_put_ops = {	251	static const struct hv_ops hvc_dcc_get_put_ops = {
86	.get_chars = hvc_dcc_get_chars,	252	.get_chars = hvc_dcc0_get_chars,
87	.put_chars = hvc_dcc_put_chars,	253	.put_chars = hvc_dcc0_put_chars,
88	};	254	};
89		255
90	static int __init hvc_dcc_console_init(void)	256	static int __init hvc_dcc_console_init(void)
@@ -108,6 +274,26 @@ static int __init hvc_dcc_init(void) · 17 unmodified lines
108	if (!hvc_dcc_check())	274	if (!hvc_dcc_check())
109	return -ENODEV;	275	return -ENODEV;
110		276
		277	if (IS_ENABLED(CONFIG_HVC_DCC_SERIALIZE_SMP)) {
		278	pr_warn("\n");
		279	pr_warn("********************************************************************\n");
		280	pr_warn(" NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE \n");
		281	pr_warn(" \n");
		282	pr_warn(" HVC_DCC_SERIALIZE_SMP SUPPORT HAS BEEN ENABLED IN THIS KERNEL \n");
		283	pr_warn(" \n");
		284	pr_warn(" This means that this is a DEBUG kernel and unsafe for \n");
		285	pr_warn(" production use and has important feature like CPU hotplug \n");
		286	pr_warn(" disabled. \n");
		287	pr_warn(" \n");
		288	pr_warn(" If you see this message and you are not debugging the \n");
		289	pr_warn(" kernel, report this immediately to your vendor! \n");
		290	pr_warn(" \n");
		291	pr_warn(" NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE \n");
		292	pr_warn("********************************************************************\n");
		293
		294	cpu_hotplug_disable();
		295	}
		296
111	p = hvc_alloc(0, 0, &hvc_dcc_get_put_ops, 128);	297	p = hvc_alloc(0, 0, &hvc_dcc_get_put_ops, 128);
112		298
113	return PTR_ERR_OR_ZERO(p);	299	return PTR_ERR_OR_ZERO(p);

drivers/tty/hvc/hvc_opal.c+3−3

 #include <linux/slab.h>
 #include <linux/console.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/export.h>
 #include <linux/interrupt.h>
 #include <asm/hvconsole.h>
-#include <asm/prom.h>
 #include <asm/firmware.h>
 #include <asm/hvsi.h>
 #include <asm/udbg.h>
 		 * path, so we hard wire it
 		 */
 		opal = of_find_node_by_path("/ibm,opal/consoles");
-		if (opal)
+		if (opal) {
 			pr_devel("hvc_opal: Found consoles in new location\n");
-		if (!opal) {
+		} else {
 			opal = of_find_node_by_path("/ibm,opal");
 			if (opal)
 				pr_devel("hvc_opal: "

drivers/tty/hvc/hvc_vio.c+1−1

 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/console.h>
+#include <linux/of.h>
 #include <asm/hvconsole.h>
 #include <asm/vio.h>
-#include <asm/prom.h>
 #include <asm/hvsi.h>
 #include <asm/udbg.h>
 #include <asm/machdep.h>

drivers/tty/hvc/hvcs.c+2−3

@@ -581,10 +581,9 @@ static int hvcs_io(struct hvcs_struct *hvcsd) · 580 unmodified lines
581		581
582	spin_unlock_irqrestore(&hvcsd->lock, flags);	582	spin_unlock_irqrestore(&hvcsd->lock, flags);
583	/* This is synch -- FIXME :js: it is not! */	583	/* This is synch -- FIXME :js: it is not! */
584	if(got)	584	if (got)
585	tty_flip_buffer_push(&hvcsd->port);	585	tty_flip_buffer_push(&hvcsd->port);
586		586	else {
587	if (!got) {
588	/* Do this _after_ the flip_buffer_push */	587	/* Do this _after_ the flip_buffer_push */
589	spin_lock_irqsave(&hvcsd->lock, flags);	588	spin_lock_irqsave(&hvcsd->lock, flags);
590	vio_enable_interrupts(hvcsd->vdev);	589	vio_enable_interrupts(hvcsd->vdev);

drivers/tty/hvc/hvsi.c+1−1

 #include <linux/module.h>
 #include <linux/major.h>
 #include <linux/kernel.h>
+#include <linux/of_irq.h>
 #include <linux/spinlock.h>
 #include <linux/sysrq.h>
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 #include <asm/hvcall.h>
 #include <asm/hvconsole.h>
-#include <asm/prom.h>
 #include <linux/uaccess.h>
 #include <asm/vio.h>
 #include <asm/param.h>

drivers/tty/mxser.c+2−3

 	outb(quot >> 8, info->ioaddr + UART_DLM);	/* MS of divisor */
 	outb(cval, info->ioaddr + UART_LCR);	/* reset DLAB */
-#ifdef BOTHER
 	if (C_BAUD(tty) == BOTHER) {
 		quot = MXSER_BAUD_BASE % newspd;
 		quot *= 8;
 			quot /= newspd;
 		mxser_set_must_enum_value(info->ioaddr, quot);
-	} else
+	} else {
-#endif
 		mxser_set_must_enum_value(info->ioaddr, 0);
+	}
 	return 0;
 }

drivers/tty/n_gsm.c+24−13

 	return modembits;
 }
+static void gsm_hex_dump_bytes(const char *fname, const u8 *data,
+			       unsigned long len)
+{
+	char *prefix;
+	if (!fname) {
+		print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, data, len,
+			       true);
+		return;
+	}
+	prefix = kasprintf(GFP_KERNEL, "%s: ", fname);
+	if (!prefix)
+		return;
+	print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 16, 1, data, len,
+		       true);
+	kfree(prefix);
+}
 /**
  *	gsm_print_packet	-	display a frame for debug
  *	@hdr: header to print before decode
 	else
 		pr_cont("(F)");
-	print_hex_dump_bytes("", DUMP_PREFIX_NONE, data, dlen);
+	gsm_hex_dump_bytes(NULL, data, dlen);
 }
 		}
 		if (debug & 4)
-			print_hex_dump_bytes("gsm_data_kick: ",
+			gsm_hex_dump_bytes(__func__, gsm->txframe, len);
-					     DUMP_PREFIX_OFFSET,
-					     gsm->txframe, len);
 		if (gsmld_output(gsm, gsm->txframe, len) <= 0)
 			break;
 		/* FIXME: Can eliminate one SOF in many more cases */
 	*--dp = msg->ctrl;
 	if (gsm->initiator)
-		*--dp = (msg->addr << 2) | 2 | EA;
+		*--dp = (msg->addr << 2) | CR | EA;
 	else
 		*--dp = (msg->addr << 2) | EA;
 	*fcs = gsm_fcs_add_block(INIT_FCS, dp , msg->data - dp);
 	case UI|PF:
 	case UIH:
 	case UIH|PF:
-#if 0
-		if (cr)
-			goto invalid;
-#endif
 		if (dlci == NULL || dlci->state != DLCI_OPEN) {
 			gsm_command(gsm, address, DM|PF);
 			return;
 		return -ENOSPC;
 	}
 	if (debug & 4)
-		print_hex_dump_bytes("gsmld_output: ", DUMP_PREFIX_OFFSET,
+		gsm_hex_dump_bytes(__func__, data, len);
-				     data, len);
 	return gsm->tty->ops->write(gsm->tty, data, len);
 }
 	char flags = TTY_NORMAL;
 	if (debug & 4)
-		print_hex_dump_bytes("gsmld_receive: ", DUMP_PREFIX_OFFSET,
+		gsm_hex_dump_bytes(__func__, cp, count);
-				     cp, count);
 	for (; count; count--, cp++) {
 		if (fp)

drivers/tty/n_tty.c+61−12

@@ -1220,21 +1220,34 @@ n_tty_receive_signal_char(struct tty_struct *tty, int signal, unsigned char c) · 1219 unmodified lines
1220	process_echoes(tty);	1220	process_echoes(tty);
1221	}	1221	}
1222		1222
		1223	static bool n_tty_is_char_flow_ctrl(struct tty_struct *tty, unsigned char c)
		1224	{
		1225	return c == START_CHAR(tty) \|\| c == STOP_CHAR(tty);
		1226	}
		1227
		1228	/* Returns true if c is consumed as flow-control character */
		1229	static bool n_tty_receive_char_flow_ctrl(struct tty_struct *tty, unsigned char c)
		1230	{
		1231	if (!n_tty_is_char_flow_ctrl(tty, c))
		1232	return false;
		1233
		1234	if (c == START_CHAR(tty)) {
		1235	start_tty(tty);
		1236	process_echoes(tty);
		1237	return true;
		1238	}
		1239
		1240	/* STOP_CHAR */
		1241	stop_tty(tty);
		1242	return true;
		1243	}
		1244
1223	static void n_tty_receive_char_special(struct tty_struct *tty, unsigned char c)	1245	static void n_tty_receive_char_special(struct tty_struct *tty, unsigned char c)
1224	{	1246	{
1225	struct n_tty_data *ldata = tty->disc_data;	1247	struct n_tty_data *ldata = tty->disc_data;
1226		1248
1227	if (I_IXON(tty)) {	1249	if (I_IXON(tty) && n_tty_receive_char_flow_ctrl(tty, c))
1228	if (c == START_CHAR(tty)) {	1250	return;
1229	start_tty(tty);
1230	process_echoes(tty);
1231	return;
1232	}
1233	if (c == STOP_CHAR(tty)) {
1234	stop_tty(tty);
1235	return;
1236	}
1237	}
1238		1251
1239	if (L_ISIG(tty)) {	1252	if (L_ISIG(tty)) {
1240	if (c == INTR_CHAR(tty)) {	1253	if (c == INTR_CHAR(tty)) {
@@ -1975,6 +1988,35 @@ static bool canon_copy_from_read_buf(struct tty_struct *tty, · 734 unmodified lines
1975	return ldata->read_tail != canon_head;	1988	return ldata->read_tail != canon_head;
1976	}	1989	}
1977		1990
		1991	/*
		1992	* If we finished a read at the exact location of an
		1993	* EOF (special EOL character that's a __DISABLED_CHAR)
		1994	* in the stream, silently eat the EOF.
		1995	*/
		1996	static void canon_skip_eof(struct tty_struct *tty)
		1997	{
		1998	struct n_tty_data *ldata = tty->disc_data;
		1999	size_t tail, canon_head;
		2000
		2001	canon_head = smp_load_acquire(&ldata->canon_head);
		2002	tail = ldata->read_tail;
		2003
		2004	// No data?
		2005	if (tail == canon_head)
		2006	return;
		2007
		2008	// See if the tail position is EOF in the circular buffer
		2009	tail &= (N_TTY_BUF_SIZE - 1);
		2010	if (!test_bit(tail, ldata->read_flags))
		2011	return;
		2012	if (read_buf(ldata, tail) != __DISABLED_CHAR)
		2013	return;
		2014
		2015	// Clear the EOL bit, skip the EOF char.
		2016	clear_bit(tail, ldata->read_flags);
		2017	smp_store_release(&ldata->read_tail, ldata->read_tail + 1);
		2018	}
		2019
1978	/**	2020	/**
1979	* job_control - check job control	2021	* job_control - check job control
1980	* @tty: tty	2022	* @tty: tty
@@ -2045,7 +2087,14 @@ static ssize_t n_tty_read(struct tty_struct tty, struct file file, · 64 unmodified lines
2045	*/	2087	*/
2046	if (*cookie) {	2088	if (*cookie) {
2047	if (ldata->icanon && !L_EXTPROC(tty)) {	2089	if (ldata->icanon && !L_EXTPROC(tty)) {
2048	if (canon_copy_from_read_buf(tty, &kb, &nr))	2090	/*
		2091	* If we have filled the user buffer, see
		2092	* if we should skip an EOF character before
		2093	* releasing the lock and returning done.
		2094	*/
		2095	if (!nr)
		2096	canon_skip_eof(tty);
		2097	else if (canon_copy_from_read_buf(tty, &kb, &nr))
2049	return kb - kbuf;	2098	return kb - kbuf;
2050	} else {	2099	} else {
2051	if (copy_from_read_buf(tty, &kb, &nr))	2100	if (copy_from_read_buf(tty, &kb, &nr))

drivers/tty/serial/8250/8250.h+41−0

@@ -17,6 +17,8 @@ · 16 unmodified lines
17	struct uart_8250_dma {	17	struct uart_8250_dma {
18	int (tx_dma)(struct uart_8250_port p);	18	int (tx_dma)(struct uart_8250_port p);
19	int (rx_dma)(struct uart_8250_port p);	19	int (rx_dma)(struct uart_8250_port p);
		20	void (prepare_tx_dma)(struct uart_8250_port p);
		21	void (prepare_rx_dma)(struct uart_8250_port p);
20		22
21	/* Filter function */	23	/* Filter function */
22	dma_filter_fn fn;	24	dma_filter_fn fn;
@@ -83,6 +85,7 @@ struct serial8250_config { · 60 unmodified lines
83	#define UART_CAP_MINI BIT(17) /* Mini UART on BCM283X family lacks:	85	#define UART_CAP_MINI BIT(17) /* Mini UART on BCM283X family lacks:
84	* STOP PARITY EPAR SPAR WLEN5 WLEN6	86	* STOP PARITY EPAR SPAR WLEN5 WLEN6
85	*/	87	*/
		88	#define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */
86		89
87	#define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */	90	#define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */
88	#define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */	91	#define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */
@@ -120,6 +123,28 @@ static inline void serial_out(struct uart_8250_port *up, int offset, int value) · 31 unmodified lines
120	up->port.serial_out(&up->port, offset, value);	123	up->port.serial_out(&up->port, offset, value);
121	}	124	}
122		125
		126	/*
		127	* For the 16C950
		128	*/
		129	static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
		130	{
		131	serial_out(up, UART_SCR, offset);
		132	serial_out(up, UART_ICR, value);
		133	}
		134
		135	static unsigned int __maybe_unused serial_icr_read(struct uart_8250_port *up,
		136	int offset)
		137	{
		138	unsigned int value;
		139
		140	serial_icr_write(up, UART_ACR, up->acr \| UART_ACR_ICRRD);
		141	serial_out(up, UART_SCR, offset);
		142	value = serial_in(up, UART_ICR);
		143	serial_icr_write(up, UART_ACR, up->acr);
		144
		145	return value;
		146	}
		147
123	void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p);	148	void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p);
124		149
125	static inline int serial_dl_read(struct uart_8250_port *up)	150	static inline int serial_dl_read(struct uart_8250_port *up)
@@ -302,6 +327,22 @@ extern int serial8250_rx_dma(struct uart_8250_port *); · 176 unmodified lines
302	extern void serial8250_rx_dma_flush(struct uart_8250_port *);	327	extern void serial8250_rx_dma_flush(struct uart_8250_port *);
303	extern int serial8250_request_dma(struct uart_8250_port *);	328	extern int serial8250_request_dma(struct uart_8250_port *);
304	extern void serial8250_release_dma(struct uart_8250_port *);	329	extern void serial8250_release_dma(struct uart_8250_port *);
		330
		331	static inline void serial8250_do_prepare_tx_dma(struct uart_8250_port *p)
		332	{
		333	struct uart_8250_dma *dma = p->dma;
		334
		335	if (dma->prepare_tx_dma)
		336	dma->prepare_tx_dma(p);
		337	}
		338
		339	static inline void serial8250_do_prepare_rx_dma(struct uart_8250_port *p)
		340	{
		341	struct uart_8250_dma *dma = p->dma;
		342
		343	if (dma->prepare_rx_dma)
		344	dma->prepare_rx_dma(p);
		345	}
305	#else	346	#else
306	static inline int serial8250_tx_dma(struct uart_8250_port *p)	347	static inline int serial8250_tx_dma(struct uart_8250_port *p)
307	{	348	{

drivers/tty/serial/8250/8250_aspeed_vuart.c+2−0

@@ -429,6 +429,8 @@ static int aspeed_vuart_probe(struct platform_device *pdev) · 428 unmodified lines
429	timer_setup(&vuart->unthrottle_timer, aspeed_vuart_unthrottle_exp, 0);	429	timer_setup(&vuart->unthrottle_timer, aspeed_vuart_unthrottle_exp, 0);
430		430
431	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	431	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		432	if (!res)
		433	return -EINVAL;
432		434
433	memset(&port, 0, sizeof(port));	435	memset(&port, 0, sizeof(port));
434	port.port.private_data = vuart;	436	port.port.private_data = vuart;

drivers/tty/serial/8250/8250_core.c+0−1

@@ -32,7 +32,6 @@ · 31 unmodified lines
32	#include <linux/mutex.h>	32	#include <linux/mutex.h>
33	#include <linux/slab.h>	33	#include <linux/slab.h>
34	#include <linux/uaccess.h>	34	#include <linux/uaccess.h>
35	#include <linux/pm_runtime.h>
36	#include <linux/io.h>	35	#include <linux/io.h>
37	#ifdef CONFIG_SPARC	36	#ifdef CONFIG_SPARC
38	#include <linux/sunserialcore.h>	37	#include <linux/sunserialcore.h>

drivers/tty/serial/8250/8250_dma.c+5−2

 		uart_write_wakeup(&p->port);
 	ret = serial8250_tx_dma(p);
-	if (ret)
+	if (ret || !dma->tx_running)
 		serial8250_set_THRI(p);
 	spin_unlock_irqrestore(&p->port.lock, flags);
 	if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
 		/* We have been called from __dma_tx_complete() */
-		serial8250_rpm_put_tx(p);
 		return 0;
 	}
 	dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
+	serial8250_do_prepare_tx_dma(p);
 	desc = dmaengine_prep_slave_single(dma->txchan,
 					   dma->tx_addr + xmit->tail,
 					   dma->tx_size, DMA_MEM_TO_DEV,
 	if (dma->rx_running)
 		return 0;
+	serial8250_do_prepare_rx_dma(p);
 	desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
 					   dma->rx_size, DMA_DEV_TO_MEM,
 					   DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

drivers/tty/serial/8250/8250_dw.c+149−80

@@ -12,13 +12,13 @@ · 11 unmodified lines
12	#include <linux/delay.h>	12	#include <linux/delay.h>
13	#include <linux/device.h>	13	#include <linux/device.h>
14	#include <linux/io.h>	14	#include <linux/io.h>
		15	#include <linux/mod_devicetable.h>
15	#include <linux/module.h>	16	#include <linux/module.h>
16	#include <linux/serial_8250.h>	17	#include <linux/serial_8250.h>
17	#include <linux/serial_reg.h>	18	#include <linux/serial_reg.h>
18	#include <linux/of.h>	19	#include <linux/of.h>
19	#include <linux/of_irq.h>
20	#include <linux/of_platform.h>
21	#include <linux/platform_device.h>	20	#include <linux/platform_device.h>
		21	#include <linux/property.h>
22	#include <linux/workqueue.h>	22	#include <linux/workqueue.h>
23	#include <linux/notifier.h>	23	#include <linux/notifier.h>
24	#include <linux/slab.h>	24	#include <linux/slab.h>
@@ -33,30 +33,28 @@ · 8 unmodified lines
33		33
34	/* Offsets for the DesignWare specific registers */	34	/* Offsets for the DesignWare specific registers */
35	#define DW_UART_USR 0x1f /* UART Status Register */	35	#define DW_UART_USR 0x1f /* UART Status Register */
		36	#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
		37
		38	#define OCTEON_UART_USR 0x27 /* UART Status Register */
		39
		40	#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
		41	#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
36		42
37	/* DesignWare specific register fields */	43	/* DesignWare specific register fields */
38	#define DW_UART_MCR_SIRE BIT(6)	44	#define DW_UART_MCR_SIRE BIT(6)
39		45
40	struct dw8250_data {	46	/* Renesas specific register fields */
41	struct dw8250_port_data data;	47	#define RZN1_UART_xDMACR_DMA_EN BIT(0)
		48	#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
		49	#define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)
		50	#define RZN1_UART_xDMACR_8_WORD_BURST (3 << 1)
		51	#define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
42		52
43	u8 usr_reg;	53	/* Quirks */
44	int msr_mask_on;	54	#define DW_UART_QUIRK_OCTEON BIT(0)
45	int msr_mask_off;	55	#define DW_UART_QUIRK_ARMADA_38X BIT(1)
46	struct clk *clk;	56	#define DW_UART_QUIRK_SKIP_SET_RATE BIT(2)
47	struct clk *pclk;	57	#define DW_UART_QUIRK_IS_DMA_FC BIT(3)
48	struct notifier_block clk_notifier;
49	struct work_struct clk_work;
50	struct reset_control *rst;
51
52	unsigned int skip_autocfg:1;
53	unsigned int uart_16550_compatible:1;
54	};
55
56	static inline struct dw8250_data to_dw8250_data(struct dw8250_port_data data)
57	{
58	return container_of(data, struct dw8250_data, data);
59	}
60		58
61	static inline struct dw8250_data clk_to_dw8250_data(struct notifier_block nb)	59	static inline struct dw8250_data clk_to_dw8250_data(struct notifier_block nb)
62	{	60	{
@@ -238,6 +236,8 @@ static int dw8250_handle_irq(struct uart_port *p) · 175 unmodified lines
238	struct uart_8250_port *up = up_to_u8250p(p);	236	struct uart_8250_port *up = up_to_u8250p(p);
239	struct dw8250_data *d = to_dw8250_data(p->private_data);	237	struct dw8250_data *d = to_dw8250_data(p->private_data);
240	unsigned int iir = p->serial_in(p, UART_IIR);	238	unsigned int iir = p->serial_in(p, UART_IIR);
		239	bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
		240	unsigned int quirks = d->pdata->quirks;
241	unsigned int status;	241	unsigned int status;
242	unsigned long flags;	242	unsigned long flags;
243		243
@@ -251,7 +251,7 @@ static int dw8250_handle_irq(struct uart_port *p) · 7 unmodified lines
251	* This problem has only been observed so far when not in DMA mode	251	* This problem has only been observed so far when not in DMA mode
252	* so we limit the workaround only to non-DMA mode.	252	* so we limit the workaround only to non-DMA mode.
253	*/	253	*/
254	if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {	254	if (!up->dma && rx_timeout) {
255	spin_lock_irqsave(&p->lock, flags);	255	spin_lock_irqsave(&p->lock, flags);
256	status = p->serial_in(p, UART_LSR);	256	status = p->serial_in(p, UART_LSR);
257		257
@@ -261,12 +261,21 @@ static int dw8250_handle_irq(struct uart_port *p) · 3 unmodified lines
261	spin_unlock_irqrestore(&p->lock, flags);	261	spin_unlock_irqrestore(&p->lock, flags);
262	}	262	}
263		263
		264	/* Manually stop the Rx DMA transfer when acting as flow controller */
		265	if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
		266	status = p->serial_in(p, UART_LSR);
		267	if (status & (UART_LSR_DR \| UART_LSR_BI)) {
		268	dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
		269	dw8250_writel_ext(p, DW_UART_DMASA, 1);
		270	}
		271	}
		272
264	if (serial8250_handle_irq(p, iir))	273	if (serial8250_handle_irq(p, iir))
265	return 1;	274	return 1;
266		275
267	if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {	276	if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
268	/* Clear the USR */	277	/* Clear the USR */
269	(void)p->serial_in(p, d->usr_reg);	278	(void)p->serial_in(p, d->pdata->usr_reg);
270		279
271	return 1;	280	return 1;
272	}	281	}
@@ -384,11 +393,48 @@ static bool dw8250_idma_filter(struct dma_chan chan, void param) · 111 unmodified lines
384	return param == chan->device->dev;	393	return param == chan->device->dev;
385	}	394	}
386		395
		396	static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
		397	{
		398	if (max_burst >= 8)
		399	return RZN1_UART_xDMACR_8_WORD_BURST;
		400	else if (max_burst >= 4)
		401	return RZN1_UART_xDMACR_4_WORD_BURST;
		402	else
		403	return RZN1_UART_xDMACR_1_WORD_BURST;
		404	}
		405
		406	static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
		407	{
		408	struct uart_port *up = &p->port;
		409	struct uart_8250_dma *dma = p->dma;
		410	u32 val;
		411
		412	dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);
		413	val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) \|
		414	RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) \|
		415	RZN1_UART_xDMACR_DMA_EN;
		416	dw8250_writel_ext(up, RZN1_UART_TDMACR, val);
		417	}
		418
		419	static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
		420	{
		421	struct uart_port *up = &p->port;
		422	struct uart_8250_dma *dma = p->dma;
		423	u32 val;
		424
		425	dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);
		426	val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) \|
		427	RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) \|
		428	RZN1_UART_xDMACR_DMA_EN;
		429	dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
		430	}
		431
387	static void dw8250_quirks(struct uart_port p, struct dw8250_data data)	432	static void dw8250_quirks(struct uart_port p, struct dw8250_data data)
388	{	433	{
389	struct device_node *np = p->dev->of_node;	434	struct device_node *np = p->dev->of_node;
390		435
391	if (np) {	436	if (np) {
		437	unsigned int quirks = data->pdata->quirks;
392	int id;	438	int id;
393		439
394	/* get index of serial line, if found in DT aliases */	440	/* get index of serial line, if found in DT aliases */
@@ -396,12 +442,11 @@ static void dw8250_quirks(struct uart_port p, struct dw8250_data data) · 1 unmodified line
396	if (id >= 0)	442	if (id >= 0)
397	p->line = id;	443	p->line = id;
398	#ifdef CONFIG_64BIT	444	#ifdef CONFIG_64BIT
399	if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {	445	if (quirks & DW_UART_QUIRK_OCTEON) {
400	p->serial_in = dw8250_serial_inq;	446	p->serial_in = dw8250_serial_inq;
401	p->serial_out = dw8250_serial_outq;	447	p->serial_out = dw8250_serial_outq;
402	p->flags = UPF_SKIP_TEST \| UPF_SHARE_IRQ \| UPF_FIXED_TYPE;	448	p->flags = UPF_SKIP_TEST \| UPF_SHARE_IRQ \| UPF_FIXED_TYPE;
403	p->type = PORT_OCTEON;	449	p->type = PORT_OCTEON;
404	data->usr_reg = 0x27;
405	data->skip_autocfg = true;	450	data->skip_autocfg = true;
406	}	451	}
407	#endif	452	#endif
@@ -412,10 +457,16 @@ static void dw8250_quirks(struct uart_port p, struct dw8250_data data) · 4 unmodified lines
412	p->serial_out = dw8250_serial_out32be;	457	p->serial_out = dw8250_serial_out32be;
413	}	458	}
414		459
415	if (of_device_is_compatible(np, "marvell,armada-38x-uart"))	460	if (quirks & DW_UART_QUIRK_ARMADA_38X)
416	p->serial_out = dw8250_serial_out38x;	461	p->serial_out = dw8250_serial_out38x;
417	if (of_device_is_compatible(np, "starfive,jh7100-uart"))	462	if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
418	p->set_termios = dw8250_do_set_termios;	463	p->set_termios = dw8250_do_set_termios;
		464	if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
		465	data->data.dma.txconf.device_fc = 1;
		466	data->data.dma.rxconf.device_fc = 1;
		467	data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
		468	data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
		469	}
419		470
420	} else if (acpi_dev_present("APMC0D08", NULL, -1)) {	471	} else if (acpi_dev_present("APMC0D08", NULL, -1)) {
421	p->iotype = UPIO_MEM32;	472	p->iotype = UPIO_MEM32;
@@ -433,21 +484,30 @@ static void dw8250_quirks(struct uart_port p, struct dw8250_data data) · 11 unmodified lines
433	}	484	}
434	}	485	}
435		486
		487	static void dw8250_clk_disable_unprepare(void *data)
		488	{
		489	clk_disable_unprepare(data);
		490	}
		491
		492	static void dw8250_reset_control_assert(void *data)
		493	{
		494	reset_control_assert(data);
		495	}
		496
436	static int dw8250_probe(struct platform_device *pdev)	497	static int dw8250_probe(struct platform_device *pdev)
437	{	498	{
438	struct uart_8250_port uart = {}, *up = &uart;	499	struct uart_8250_port uart = {}, *up = &uart;
439	struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
440	struct uart_port *p = &up->port;	500	struct uart_port *p = &up->port;
441	struct device *dev = &pdev->dev;	501	struct device *dev = &pdev->dev;
442	struct dw8250_data *data;	502	struct dw8250_data *data;
		503	struct resource *regs;
443	int irq;	504	int irq;
444	int err;	505	int err;
445	u32 val;	506	u32 val;
446		507
447	if (!regs) {	508	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
448	dev_err(dev, "no registers defined\n");	509	if (!regs)
449	return -EINVAL;	510	return dev_err_probe(dev, -EINVAL, "no registers defined\n");
450	}
451		511
452	irq = platform_get_irq(pdev, 0);	512	irq = platform_get_irq(pdev, 0);
453	if (irq < 0)	513	if (irq < 0)
@@ -476,7 +536,7 @@ static int dw8250_probe(struct platform_device *pdev) · 22 unmodified lines
476	return -ENOMEM;	536	return -ENOMEM;
477		537
478	data->data.dma.fn = dw8250_fallback_dma_filter;	538	data->data.dma.fn = dw8250_fallback_dma_filter;
479	data->usr_reg = DW_UART_USR;	539	data->pdata = device_get_match_data(p->dev);
480	p->private_data = &data->data;	540	p->private_data = &data->data;
481		541
482	data->uart_16550_compatible = device_property_read_bool(dev,	542	data->uart_16550_compatible = device_property_read_bool(dev,
@@ -532,37 +592,41 @@ static int dw8250_probe(struct platform_device *pdev) · 49 unmodified lines
532		592
533	err = clk_prepare_enable(data->clk);	593	err = clk_prepare_enable(data->clk);
534	if (err)	594	if (err)
535	dev_warn(dev, "could not enable optional baudclk: %d\n", err);	595	return dev_err_probe(dev, err, "could not enable optional baudclk\n");
		596
		597	err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->clk);
		598	if (err)
		599	return err;
536		600
537	if (data->clk)	601	if (data->clk)
538	p->uartclk = clk_get_rate(data->clk);	602	p->uartclk = clk_get_rate(data->clk);
539		603
540	/* If no clock rate is defined, fail. */	604	/* If no clock rate is defined, fail. */
541	if (!p->uartclk) {	605	if (!p->uartclk)
542	dev_err(dev, "clock rate not defined\n");	606	return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");
543	err = -EINVAL;
544	goto err_clk;
545	}
546		607
547	data->pclk = devm_clk_get_optional(dev, "apb_pclk");	608	data->pclk = devm_clk_get_optional(dev, "apb_pclk");
548	if (IS_ERR(data->pclk)) {	609	if (IS_ERR(data->pclk))
549	err = PTR_ERR(data->pclk);	610	return PTR_ERR(data->pclk);
550	goto err_clk;
551	}
552		611
553	err = clk_prepare_enable(data->pclk);	612	err = clk_prepare_enable(data->pclk);
554	if (err) {	613	if (err)
555	dev_err(dev, "could not enable apb_pclk\n");	614	return dev_err_probe(dev, err, "could not enable apb_pclk\n");
556	goto err_clk;	615
557	}	616	err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->pclk);
		617	if (err)
		618	return err;
558		619
559	data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);	620	data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
560	if (IS_ERR(data->rst)) {	621	if (IS_ERR(data->rst))
561	err = PTR_ERR(data->rst);	622	return PTR_ERR(data->rst);
562	goto err_pclk;	623
563	}
564	reset_control_deassert(data->rst);	624	reset_control_deassert(data->rst);
565		625
		626	err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);
		627	if (err)
		628	return err;
		629
566	dw8250_quirks(p, data);	630	dw8250_quirks(p, data);
567		631
568	/* If the Busy Functionality is not implemented, don't handle it */	632	/* If the Busy Functionality is not implemented, don't handle it */
@@ -580,10 +644,8 @@ static int dw8250_probe(struct platform_device *pdev) · 11 unmodified lines
580	}	644	}
581		645
582	data->data.line = serial8250_register_8250_port(up);	646	data->data.line = serial8250_register_8250_port(up);
583	if (data->data.line < 0) {	647	if (data->data.line < 0)
584	err = data->data.line;	648	return data->data.line;
585	goto err_reset;
586	}
587		649
588	/*	650	/*
589	* Some platforms may provide a reference clock shared between several	651	* Some platforms may provide a reference clock shared between several
@@ -593,9 +655,8 @@ static int dw8250_probe(struct platform_device *pdev) · 3 unmodified lines
593	if (data->clk) {	655	if (data->clk) {
594	err = clk_notifier_register(data->clk, &data->clk_notifier);	656	err = clk_notifier_register(data->clk, &data->clk_notifier);
595	if (err)	657	if (err)
596	dev_warn(p->dev, "Failed to set the clock notifier\n");	658	return dev_err_probe(dev, err, "Failed to set the clock notifier\n");
597	else	659	queue_work(system_unbound_wq, &data->clk_work);
598	queue_work(system_unbound_wq, &data->clk_work);
599	}	660	}
600		661
601	platform_set_drvdata(pdev, data);	662	platform_set_drvdata(pdev, data);
@@ -604,17 +665,6 @@ static int dw8250_probe(struct platform_device *pdev) · 2 unmodified lines
604	pm_runtime_enable(dev);	665	pm_runtime_enable(dev);
605		666
606	return 0;	667	return 0;
607
608	err_reset:
609	reset_control_assert(data->rst);
610
611	err_pclk:
612	clk_disable_unprepare(data->pclk);
613
614	err_clk:
615	clk_disable_unprepare(data->clk);
616
617	return err;
618	}	668	}
619		669
620	static int dw8250_remove(struct platform_device *pdev)	670	static int dw8250_remove(struct platform_device *pdev)
@@ -632,12 +682,6 @@ static int dw8250_remove(struct platform_device *pdev) · 11 unmodified lines
632		682
633	serial8250_unregister_port(data->data.line);	683	serial8250_unregister_port(data->data.line);
634		684
635	reset_control_assert(data->rst);
636
637	clk_disable_unprepare(data->pclk);
638
639	clk_disable_unprepare(data->clk);
640
641	pm_runtime_disable(dev);	685	pm_runtime_disable(dev);
642	pm_runtime_put_noidle(dev);	686	pm_runtime_put_noidle(dev);
643		687
@@ -693,12 +737,37 @@ static const struct dev_pm_ops dw8250_pm_ops = { · 49 unmodified lines
693	SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)	737	SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
694	};	738	};
695		739
		740	static const struct dw8250_platform_data dw8250_dw_apb = {
		741	.usr_reg = DW_UART_USR,
		742	};
		743
		744	static const struct dw8250_platform_data dw8250_octeon_3860_data = {
		745	.usr_reg = OCTEON_UART_USR,
		746	.quirks = DW_UART_QUIRK_OCTEON,
		747	};
		748
		749	static const struct dw8250_platform_data dw8250_armada_38x_data = {
		750	.usr_reg = DW_UART_USR,
		751	.quirks = DW_UART_QUIRK_ARMADA_38X,
		752	};
		753
		754	static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
		755	.usr_reg = DW_UART_USR,
		756	.cpr_val = 0x00012f32,
		757	.quirks = DW_UART_QUIRK_IS_DMA_FC,
		758	};
		759
		760	static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
		761	.usr_reg = DW_UART_USR,
		762	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
		763	};
		764
696	static const struct of_device_id dw8250_of_match[] = {	765	static const struct of_device_id dw8250_of_match[] = {
697	{ .compatible = "snps,dw-apb-uart" },	766	{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
698	{ .compatible = "cavium,octeon-3860-uart" },	767	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
699	{ .compatible = "marvell,armada-38x-uart" },	768	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
700	{ .compatible = "renesas,rzn1-uart" },	769	{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
701	{ .compatible = "starfive,jh7100-uart" },	770	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
702	{ /* Sentinel */ }	771	{ /* Sentinel */ }
703	};	772	};
704	MODULE_DEVICE_TABLE(of, dw8250_of_match);	773	MODULE_DEVICE_TABLE(of, dw8250_of_match);

drivers/tty/serial/8250/8250_dwlib.c+96−20

@@ -2,19 +2,32 @@ · 1 unmodified line
2	/* Synopsys DesignWare 8250 library. */	2	/* Synopsys DesignWare 8250 library. */
3		3
4	#include <linux/bitops.h>	4	#include <linux/bitops.h>
		5	#include <linux/bitfield.h>
5	#include <linux/device.h>	6	#include <linux/device.h>
6	#include <linux/io.h>
7	#include <linux/kernel.h>	7	#include <linux/kernel.h>
		8	#include <linux/property.h>
8	#include <linux/serial_8250.h>	9	#include <linux/serial_8250.h>
9	#include <linux/serial_core.h>	10	#include <linux/serial_core.h>
10		11
11	#include "8250_dwlib.h"	12	#include "8250_dwlib.h"
12		13
13	/* Offsets for the DesignWare specific registers */	14	/* Offsets for the DesignWare specific registers */
		15	#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
		16	#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
		17	#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
14	#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */	18	#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
15	#define DW_UART_CPR 0xf4 /* Component Parameter Register */	19	#define DW_UART_CPR 0xf4 /* Component Parameter Register */
16	#define DW_UART_UCV 0xf8 /* UART Component Version */	20	#define DW_UART_UCV 0xf8 /* UART Component Version */
17		21
		22	/* Transceiver Control Register bits */
		23	#define DW_UART_TCR_RS485_EN BIT(0)
		24	#define DW_UART_TCR_RE_POL BIT(1)
		25	#define DW_UART_TCR_DE_POL BIT(2)
		26	#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
		27	#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
		28	#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
		29	#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
		30
18	/* Component Parameter Register bits */	31	/* Component Parameter Register bits */
19	#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)	32	#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
20	#define DW_UART_CPR_AFCE_MODE (1 << 4)	33	#define DW_UART_CPR_AFCE_MODE (1 << 4)
@@ -32,21 +45,6 @@ · 11 unmodified lines
32	/* Helper for FIFO size calculation */	45	/* Helper for FIFO size calculation */
33	#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)	46	#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
34		47
35	static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
36	{
37	if (p->iotype == UPIO_MEM32BE)
38	return ioread32be(p->membase + offset);
39	return readl(p->membase + offset);
40	}
41
42	static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
43	{
44	if (p->iotype == UPIO_MEM32BE)
45	iowrite32be(reg, p->membase + offset);
46	else
47	writel(reg, p->membase + offset);
48	}
49
50	/*	48	/*
51	* divisor = div(I) + div(F)	49	* divisor = div(I) + div(F)
52	* "I" means integer, "F" means fractional	50	* "I" means integer, "F" means fractional
@@ -87,11 +85,87 @@ void dw8250_do_set_termios(struct uart_port p, struct ktermios termios, struct · 34 unmodified lines
87	}	85	}
88	EXPORT_SYMBOL_GPL(dw8250_do_set_termios);	86	EXPORT_SYMBOL_GPL(dw8250_do_set_termios);
89		87
		88	static int dw8250_rs485_config(struct uart_port p, struct serial_rs485 rs485)
		89	{
		90	u32 tcr;
		91
		92	tcr = dw8250_readl_ext(p, DW_UART_TCR);
		93	tcr &= ~DW_UART_TCR_XFER_MODE;
		94
		95	if (rs485->flags & SER_RS485_ENABLED) {
		96	/* Clear unsupported flags. */
		97	rs485->flags &= SER_RS485_ENABLED \| SER_RS485_RX_DURING_TX \|
		98	SER_RS485_RTS_ON_SEND \| SER_RS485_RTS_AFTER_SEND;
		99	tcr \|= DW_UART_TCR_RS485_EN;
		100
		101	if (rs485->flags & SER_RS485_RX_DURING_TX) {
		102	tcr \|= DW_UART_TCR_XFER_MODE_DE_DURING_RE;
		103	} else {
		104	/* HW does not support same DE level for tx and rx */
		105	if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
		106	!(rs485->flags & SER_RS485_RTS_AFTER_SEND))
		107	return -EINVAL;
		108
		109	tcr \|= DW_UART_TCR_XFER_MODE_DE_OR_RE;
		110	}
		111	dw8250_writel_ext(p, DW_UART_DE_EN, 1);
		112	dw8250_writel_ext(p, DW_UART_RE_EN, 1);
		113	} else {
		114	rs485->flags = 0;
		115
		116	tcr &= ~DW_UART_TCR_RS485_EN;
		117	}
		118
		119	/* Reset to default polarity */
		120	tcr \|= DW_UART_TCR_DE_POL;
		121	tcr &= ~DW_UART_TCR_RE_POL;
		122
		123	if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
		124	tcr &= ~DW_UART_TCR_DE_POL;
		125	if (device_property_read_bool(p->dev, "rs485-rx-active-high"))
		126	tcr \|= DW_UART_TCR_RE_POL;
		127
		128	dw8250_writel_ext(p, DW_UART_TCR, tcr);
		129
		130	rs485->delay_rts_before_send = 0;
		131	rs485->delay_rts_after_send = 0;
		132
		133	p->rs485 = *rs485;
		134
		135	return 0;
		136	}
		137
		138	/*
		139	* Tests if RE_EN register can have non-zero value to see if RS-485 HW support
		140	* is present.
		141	*/
		142	static bool dw8250_detect_rs485_hw(struct uart_port *p)
		143	{
		144	u32 reg;
		145
		146	dw8250_writel_ext(p, DW_UART_RE_EN, 1);
		147	reg = dw8250_readl_ext(p, DW_UART_RE_EN);
		148	dw8250_writel_ext(p, DW_UART_RE_EN, 0);
		149	return reg;
		150	}
		151
90	void dw8250_setup_port(struct uart_port *p)	152	void dw8250_setup_port(struct uart_port *p)
91	{	153	{
		154	struct dw8250_port_data *pd = p->private_data;
		155	struct dw8250_data *data = to_dw8250_data(pd);
92	struct uart_8250_port *up = up_to_u8250p(p);	156	struct uart_8250_port *up = up_to_u8250p(p);
93	u32 reg;	157	u32 reg;
94		158
		159	pd->hw_rs485_support = dw8250_detect_rs485_hw(p);
		160	if (pd->hw_rs485_support) {
		161	p->rs485_config = dw8250_rs485_config;
		162	} else {
		163	p->rs485_config = serial8250_em485_config;
		164	up->rs485_start_tx = serial8250_em485_start_tx;
		165	up->rs485_stop_tx = serial8250_em485_stop_tx;
		166	}
		167	up->capabilities \|= UART_CAP_NOTEMT;
		168
95	/*	169	/*
96	* If the Component Version Register returns zero, we know that	170	* If the Component Version Register returns zero, we know that
97	* ADDITIONAL_FEATURES are not enabled. No need to go any further.	171	* ADDITIONAL_FEATURES are not enabled. No need to go any further.
@@ -108,14 +182,16 @@ void dw8250_setup_port(struct uart_port *p) · 10 unmodified lines
108	dw8250_writel_ext(p, DW_UART_DLF, 0);	182	dw8250_writel_ext(p, DW_UART_DLF, 0);
109		183
110	if (reg) {	184	if (reg) {
111	struct dw8250_port_data *d = p->private_data;	185	pd->dlf_size = fls(reg);
112
113	d->dlf_size = fls(reg);
114	p->get_divisor = dw8250_get_divisor;	186	p->get_divisor = dw8250_get_divisor;
115	p->set_divisor = dw8250_set_divisor;	187	p->set_divisor = dw8250_set_divisor;
116	}	188	}
117		189
118	reg = dw8250_readl_ext(p, DW_UART_CPR);	190	reg = dw8250_readl_ext(p, DW_UART_CPR);
		191	if (!reg) {
		192	reg = data->pdata->cpr_val;
		193	dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg);
		194	}
119	if (!reg)	195	if (!reg)
120	return;	196	return;
121		197
@@ -124,7 +200,7 @@ void dw8250_setup_port(struct uart_port *p) · 2 unmodified lines
124	p->type = PORT_16550A;	200	p->type = PORT_16550A;
125	p->flags \|= UPF_FIXED_TYPE;	201	p->flags \|= UPF_FIXED_TYPE;
126	p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);	202	p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
127	up->capabilities = UART_CAP_FIFO;	203	up->capabilities = UART_CAP_FIFO \| UART_CAP_NOTEMT;
128	}	204	}
129		205
130	if (reg & DW_UART_CPR_AFCE_MODE)	206	if (reg & DW_UART_CPR_AFCE_MODE)

drivers/tty/serial/8250/8250_dwlib.h+51−0

@@ -1,10 +1,16 @@
1	/* SPDX-License-Identifier: GPL-2.0+ */	1	/* SPDX-License-Identifier: GPL-2.0+ */
2	/* Synopsys DesignWare 8250 library header file. */	2	/* Synopsys DesignWare 8250 library header file. */
3		3
		4	#include <linux/io.h>
		5	#include <linux/notifier.h>
4	#include <linux/types.h>	6	#include <linux/types.h>
		7	#include <linux/workqueue.h>
5		8
6	#include "8250.h"	9	#include "8250.h"
7		10
		11	struct clk;
		12	struct reset_control;
		13
8	struct dw8250_port_data {	14	struct dw8250_port_data {
9	/* Port properties */	15	/* Port properties */
10	int line;	16	int line;
@@ -14,7 +20,52 @@ struct dw8250_port_data { · 3 unmodified lines
14		20
15	/* Hardware configuration */	21	/* Hardware configuration */
16	u8 dlf_size;	22	u8 dlf_size;
		23
		24	/* RS485 variables */
		25	bool hw_rs485_support;
		26	};
		27
		28	struct dw8250_platform_data {
		29	u8 usr_reg;
		30	u32 cpr_val;
		31	unsigned int quirks;
		32	};
		33
		34	struct dw8250_data {
		35	struct dw8250_port_data data;
		36	const struct dw8250_platform_data *pdata;
		37
		38	int msr_mask_on;
		39	int msr_mask_off;
		40	struct clk *clk;
		41	struct clk *pclk;
		42	struct notifier_block clk_notifier;
		43	struct work_struct clk_work;
		44	struct reset_control *rst;
		45
		46	unsigned int skip_autocfg:1;
		47	unsigned int uart_16550_compatible:1;
17	};	48	};
18		49
19	void dw8250_do_set_termios(struct uart_port p, struct ktermios termios, struct ktermios *old);	50	void dw8250_do_set_termios(struct uart_port p, struct ktermios termios, struct ktermios *old);
20	void dw8250_setup_port(struct uart_port *p);	51	void dw8250_setup_port(struct uart_port *p);
		52
		53	static inline struct dw8250_data to_dw8250_data(struct dw8250_port_data data)
		54	{
		55	return container_of(data, struct dw8250_data, data);
		56	}
		57
		58	static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
		59	{
		60	if (p->iotype == UPIO_MEM32BE)
		61	return ioread32be(p->membase + offset);
		62	return readl(p->membase + offset);
		63	}
		64
		65	static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
		66	{
		67	if (p->iotype == UPIO_MEM32BE)
		68	iowrite32be(reg, p->membase + offset);
		69	else
		70	writel(reg, p->membase + offset);
		71	}

drivers/tty/serial/8250/8250_fintek.c+4−4

 	if (!pdata)
 		return -EINVAL;
-	/* Hardware do not support same RTS level on send and receive */
-	if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
-			!(rs485->flags & SER_RS485_RTS_AFTER_SEND))
-		return -EINVAL;
 	if (rs485->flags & SER_RS485_ENABLED) {
+		/* Hardware do not support same RTS level on send and receive */
+		if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
+		    !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
+			return -EINVAL;
 		memset(rs485->padding, 0, sizeof(rs485->padding));
 		config |= RS485_URA;
 	} else {

drivers/tty/serial/8250/8250_mtk.c+0−7

 #define MTK_UART_TX_TRIGGER	1
 #define MTK_UART_RX_TRIGGER	MTK_UART_RX_SIZE
-#define MTK_UART_FEATURE_SEL	39	/* Feature Selection register */
-#define MTK_UART_FEAT_NEWRMAP	BIT(0)	/* Use new register map */
 #define MTK_UART_XON1		40	/* I/O: Xon character 1 */
 #define MTK_UART_XOFF1		42	/* I/O: Xoff character 1 */
 		uart.dma = data->dma;
 #endif
-	/* Set AP UART new register map */
-	writel(MTK_UART_FEAT_NEWRMAP, uart.port.membase +
-	       (MTK_UART_FEATURE_SEL << uart.port.regshift));
 	/* Disable Rate Fix function */
 	writel(0x0, uart.port.membase +
 			(MTK_UART_RATE_FIX << uart.port.regshift));

drivers/tty/serial/8250/8250_of.c+2−0

 		.data = (void *)PORT_ALTR_16550_F64, },
 	{ .compatible = "altr,16550-FIFO128",
 		.data = (void *)PORT_ALTR_16550_F128, },
+	{ .compatible = "fsl,16550-FIFO64",
+		.data = (void *)PORT_16550A_FSL64, },
 	{ .compatible = "mediatek,mtk-btif",
 		.data = (void *)PORT_MTK_BTIF, },
 	{ .compatible = "mrvl,mmp-uart",

drivers/tty/serial/8250/8250_pci.c+335−145

 #include <linux/pci.h>
 #include <linux/string.h>
 #include <linux/kernel.h>
+#include <linux/math.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/tty.h>
 }
 /*
- * EndRun Technologies.
+ * Oxford Semiconductor Inc.
- * Determine the number of ports available on the device.
+ * Check if an OxSemi device is part of the Tornado range of devices.
  */
 #define PCI_VENDOR_ID_ENDRUN			0x7401
 #define PCI_DEVICE_ID_ENDRUN_1588	0xe100
-static int pci_endrun_init(struct pci_dev *dev)
+static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
 {
-	u8 __iomem *p;
+	/* OxSemi Tornado devices are all 0xCxxx */
-	unsigned long deviceID;
+	if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
-	unsigned int  number_uarts = 0;
+	    (dev->device & 0xf000) != 0xc000)
+		return false;
-	/* EndRun device is all 0xexxx */
+	/* EndRun devices are all 0xExxx */
 	if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
-		(dev->device & 0xf000) != 0xe000)
+	    (dev->device & 0xf000) != 0xe000)
-		return 0;
+		return false;
-	p = pci_iomap(dev, 0, 5);
-	if (p == NULL)
-		return -ENOMEM;
-	deviceID = ioread32(p);
+	return true;
-	/* EndRun device */
-	if (deviceID == 0x07000200) {
-		number_uarts = ioread8(p + 4);
-		pci_dbg(dev, "%d ports detected on EndRun PCI Express device\n", number_uarts);
-	}
-	pci_iounmap(dev, p);
-	return number_uarts;
 }
 /*
- * Oxford Semiconductor Inc.
+ * Determine the number of ports available on a Tornado device.
- * Check that device is part of the Tornado range of devices, then determine
- * the number of ports available on the device.
  */
 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
 {
 	unsigned long deviceID;
 	unsigned int  number_uarts = 0;
-	/* OxSemi Tornado devices are all 0xCxxx */
+	if (!pci_oxsemi_tornado_p(dev))
-	if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
-	    (dev->device & 0xF000) != 0xC000)
 		return 0;
 	p = pci_iomap(dev, 0, 5);
 	/* Tornado device */
 	if (deviceID == 0x07000200) {
 		number_uarts = ioread8(p + 4);
-		pci_dbg(dev, "%d ports detected on Oxford PCI Express device\n", number_uarts);
+		pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
+			number_uarts,
+			dev->vendor == PCI_VENDOR_ID_ENDRUN ?
+			"EndRun" : "Oxford");
 	}
 	pci_iounmap(dev, p);
 	return number_uarts;
 }
+/* Tornado-specific constants for the TCR and CPR registers; see below.  */
+#define OXSEMI_TORNADO_TCR_MASK	0xf
+#define OXSEMI_TORNADO_CPR_MASK	0x1ff
+#define OXSEMI_TORNADO_CPR_MIN	0x008
+#define OXSEMI_TORNADO_CPR_DEF	0x10f
+/*
+ * Determine the oversampling rate, the clock prescaler, and the clock
+ * divisor for the requested baud rate.  The clock rate is 62.5 MHz,
+ * which is four times the baud base, and the prescaler increments in
+ * steps of 1/8.  Therefore to make calculations on integers we need
+ * to use a scaled clock rate, which is the baud base multiplied by 32
+ * (or our assumed UART clock rate multiplied by 2).
+ *
+ * The allowed oversampling rates are from 4 up to 16 inclusive (values
+ * from 0 to 3 inclusive map to 16).  Likewise the clock prescaler allows
+ * values between 1.000 and 63.875 inclusive (operation for values from
+ * 0.000 to 0.875 has not been specified).  The clock divisor is the usual
+ * unsigned 16-bit integer.
+ *
+ * For the most accurate baud rate we use a table of predetermined
+ * oversampling rates and clock prescalers that records all possible
+ * products of the two parameters in the range from 4 up to 255 inclusive,
+ * and additionally 335 for the 1500000bps rate, with the prescaler scaled
+ * by 8.  The table is sorted by the decreasing value of the oversampling
+ * rate and ties are resolved by sorting by the decreasing value of the
+ * product.  This way preference is given to higher oversampling rates.
+ *
+ * We iterate over the table and choose the product of an oversampling
+ * rate and a clock prescaler that gives the lowest integer division
+ * result deviation, or if an exact integer divider is found we stop
+ * looking for it right away.  We do some fixup if the resulting clock
+ * divisor required would be out of its unsigned 16-bit integer range.
+ *
+ * Finally we abuse the supposed fractional part returned to encode the
+ * 4-bit value of the oversampling rate and the 9-bit value of the clock
+ * prescaler which will end up in the TCR and CPR/CPR2 registers.
+ */
+static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
+						   unsigned int baud,
+						   unsigned int *frac)
+{
+	static u8 p[][2] = {
+		{ 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
+		{ 16, 10, }, { 16,  9, }, { 16,  8, }, { 15, 17, },
+		{ 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
+		{ 15, 12, }, { 15, 11, }, { 15, 10, }, { 15,  9, },
+		{ 15,  8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
+		{ 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
+		{ 14,  9, }, { 14,  8, }, { 13, 19, }, { 13, 18, },
+		{ 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
+		{ 13, 10, }, { 13,  9, }, { 13,  8, }, { 12, 19, },
+		{ 12, 18, }, { 12, 17, }, { 12, 11, }, { 12,  9, },
+		{ 12,  8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
+		{ 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
+		{ 11, 11, }, { 11, 10, }, { 11,  9, }, { 11,  8, },
+		{ 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
+		{ 10, 17, }, { 10, 10, }, { 10,  9, }, { 10,  8, },
+		{  9, 27, }, {  9, 23, }, {  9, 21, }, {  9, 19, },
+		{  9, 18, }, {  9, 17, }, {  9,  9, }, {  9,  8, },
+		{  8, 31, }, {  8, 29, }, {  8, 23, }, {  8, 19, },
+		{  8, 17, }, {  8,  8, }, {  7, 35, }, {  7, 31, },
+		{  7, 29, }, {  7, 25, }, {  7, 23, }, {  7, 21, },
+		{  7, 19, }, {  7, 17, }, {  7, 15, }, {  7, 14, },
+		{  7, 13, }, {  7, 12, }, {  7, 11, }, {  7, 10, },
+		{  7,  9, }, {  7,  8, }, {  6, 41, }, {  6, 37, },
+		{  6, 31, }, {  6, 29, }, {  6, 23, }, {  6, 19, },
+		{  6, 17, }, {  6, 13, }, {  6, 11, }, {  6, 10, },
+		{  6,  9, }, {  6,  8, }, {  5, 67, }, {  5, 47, },
+		{  5, 43, }, {  5, 41, }, {  5, 37, }, {  5, 31, },
+		{  5, 29, }, {  5, 25, }, {  5, 23, }, {  5, 19, },
+		{  5, 17, }, {  5, 15, }, {  5, 13, }, {  5, 11, },
+		{  5, 10, }, {  5,  9, }, {  5,  8, }, {  4, 61, },
+		{  4, 59, }, {  4, 53, }, {  4, 47, }, {  4, 43, },
+		{  4, 41, }, {  4, 37, }, {  4, 31, }, {  4, 29, },
+		{  4, 23, }, {  4, 19, }, {  4, 17, }, {  4, 13, },
+		{  4,  9, }, {  4,  8, },
+	};
+	/* Scale the quotient for comparison to get the fractional part.  */
+	const unsigned int quot_scale = 65536;
+	unsigned int sclk = port->uartclk * 2;
+	unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
+	unsigned int best_squot;
+	unsigned int squot;
+	unsigned int quot;
+	u16 cpr;
+	u8 tcr;
+	int i;
+	/* Old custom speed handling.  */
+	if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
+		unsigned int cust_div = port->custom_divisor;
+		quot = cust_div & UART_DIV_MAX;
+		tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
+		cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
+		if (cpr < OXSEMI_TORNADO_CPR_MIN)
+			cpr = OXSEMI_TORNADO_CPR_DEF;
+	} else {
+		best_squot = quot_scale;
+		for (i = 0; i < ARRAY_SIZE(p); i++) {
+			unsigned int spre;
+			unsigned int srem;
+			u8 cp;
+			u8 tc;
+			tc = p[i][0];
+			cp = p[i][1];
+			spre = tc * cp;
+			srem = sdiv % spre;
+			if (srem > spre / 2)
+				srem = spre - srem;
+			squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
+			if (srem == 0) {
+				tcr = tc;
+				cpr = cp;
+				quot = sdiv / spre;
+				break;
+			} else if (squot < best_squot) {
+				best_squot = squot;
+				tcr = tc;
+				cpr = cp;
+				quot = DIV_ROUND_CLOSEST(sdiv, spre);
+			}
+		}
+		while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
+		       quot % 2 == 0) {
+			quot >>= 1;
+			tcr <<= 1;
+		}
+		while (quot > UART_DIV_MAX) {
+			if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
+				quot >>= 1;
+				tcr <<= 1;
+			} else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
+				quot >>= 1;
+				cpr <<= 1;
+			} else {
+				quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
+				cpr = OXSEMI_TORNADO_CPR_MASK;
+			}
+		}
+	}
+	*frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
+	return quot;
+}
+/*
+ * Set the oversampling rate in the transmitter clock cycle register (TCR),
+ * the clock prescaler in the clock prescaler register (CPR and CPR2), and
+ * the clock divisor in the divisor latch (DLL and DLM).  Note that for
+ * backwards compatibility any write to CPR clears CPR2 and therefore CPR
+ * has to be written first, followed by CPR2, which occupies the location
+ * of CKS used with earlier UART designs.
+ */
+static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
+					   unsigned int baud,
+					   unsigned int quot,
+					   unsigned int quot_frac)
+{
+	struct uart_8250_port *up = up_to_u8250p(port);
+	u8 cpr2 = quot_frac >> 16;
+	u8 cpr = quot_frac >> 8;
+	u8 tcr = quot_frac;
+	serial_icr_write(up, UART_TCR, tcr);
+	serial_icr_write(up, UART_CPR, cpr);
+	serial_icr_write(up, UART_CKS, cpr2);
+	serial8250_do_set_divisor(port, baud, quot, 0);
+}
+/*
+ * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
+ * generator prescaler (CPR and CPR2).  Otherwise no prescaler would be used.
+ */
+static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
+					 unsigned int mctrl)
+{
+	struct uart_8250_port *up = up_to_u8250p(port);
+	up->mcr |= UART_MCR_CLKSEL;
+	serial8250_do_set_mctrl(port, mctrl);
+}
+static int pci_oxsemi_tornado_setup(struct serial_private *priv,
+				    const struct pciserial_board *board,
+				    struct uart_8250_port *up, int idx)
+{
+	struct pci_dev *dev = priv->dev;
+	if (pci_oxsemi_tornado_p(dev)) {
+		up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
+		up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
+		up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
+	}
+	return pci_default_setup(priv, board, up, idx);
+}
 static int pci_asix_setup(struct serial_private *priv,
 		  const struct pciserial_board *board,
 		  struct uart_8250_port *port, int idx)
 		.device		= PCI_ANY_ID,
 		.subvendor	= PCI_ANY_ID,
 		.subdevice	= PCI_ANY_ID,
-		.init		= pci_endrun_init,
+		.init		= pci_oxsemi_tornado_init,
 		.setup		= pci_default_setup,
 	},
 	/*
 		.subvendor	= PCI_ANY_ID,
 		.subdevice	= PCI_ANY_ID,
 		.init		= pci_oxsemi_tornado_init,
-		.setup		= pci_default_setup,
+		.setup		= pci_oxsemi_tornado_setup,
 	},
 	{
 		.vendor		= PCI_VENDOR_ID_MAINPINE,
 		.subvendor	= PCI_ANY_ID,
 		.subdevice	= PCI_ANY_ID,
 		.init		= pci_oxsemi_tornado_init,
-		.setup		= pci_default_setup,
+		.setup		= pci_oxsemi_tornado_setup,
 	},
 	{
 		.vendor		= PCI_VENDOR_ID_DIGI,
 		.subvendor		= PCI_SUBVENDOR_ID_IBM,
 		.subdevice		= PCI_ANY_ID,
 		.init			= pci_oxsemi_tornado_init,
-		.setup		= pci_default_setup,
+		.setup		= pci_oxsemi_tornado_setup,
 	},
 	{
 		.vendor         = PCI_VENDOR_ID_INTEL,
 	pbn_b0_2_1843200,
 	pbn_b0_4_1843200,
-	pbn_b0_1_3906250,
+	pbn_b0_1_15625000,
 	pbn_b0_bt_1_115200,
 	pbn_b0_bt_2_115200,
 	pbn_panacom2,
 	pbn_panacom4,
 	pbn_plx_romulus,
-	pbn_endrun_2_3906250,
 	pbn_oxsemi,
-	pbn_oxsemi_1_3906250,
+	pbn_oxsemi_1_15625000,
-	pbn_oxsemi_2_3906250,
+	pbn_oxsemi_2_15625000,
-	pbn_oxsemi_4_3906250,
+	pbn_oxsemi_4_15625000,
-	pbn_oxsemi_8_3906250,
+	pbn_oxsemi_8_15625000,
 	pbn_intel_i960,
 	pbn_sgi_ioc3,
 	pbn_computone_4,
 		.uart_offset	= 8,
 	},
-	[pbn_b0_1_3906250] = {
+	[pbn_b0_1_15625000] = {
 		.flags		= FL_BASE0,
 		.num_ports	= 1,
-		.base_baud	= 3906250,
+		.base_baud	= 15625000,
 		.uart_offset	= 8,
 	},
 		.first_offset	= 0x03,
 	},
-	/*
-	 * EndRun Technologies
-	* Uses the size of PCI Base region 0 to
-	* signal now many ports are available
-	* 2 port 952 Uart support
-	*/
-	[pbn_endrun_2_3906250] = {
-		.flags		= FL_BASE0,
-		.num_ports	= 2,
-		.base_baud	= 3906250,
-		.uart_offset	= 0x200,
-		.first_offset	= 0x1000,
-	},
 	/*
 	 * This board uses the size of PCI Base region 0 to
 	 * signal now many ports are available
 		.base_baud	= 115200,
 		.uart_offset	= 8,
 	},
-	[pbn_oxsemi_1_3906250] = {
+	[pbn_oxsemi_1_15625000] = {
 		.flags		= FL_BASE0,
 		.num_ports	= 1,
-		.base_baud	= 3906250,
+		.base_baud	= 15625000,
 		.uart_offset	= 0x200,
 		.first_offset	= 0x1000,
 	},
-	[pbn_oxsemi_2_3906250] = {
+	[pbn_oxsemi_2_15625000] = {
 		.flags		= FL_BASE0,
 		.num_ports	= 2,
-		.base_baud	= 3906250,
+		.base_baud	= 15625000,
 		.uart_offset	= 0x200,
 		.first_offset	= 0x1000,
 	},
-	[pbn_oxsemi_4_3906250] = {
+	[pbn_oxsemi_4_15625000] = {
 		.flags		= FL_BASE0,
 		.num_ports	= 4,
-		.base_baud	= 3906250,
+		.base_baud	= 15625000,
 		.uart_offset	= 0x200,
 		.first_offset	= 0x1000,
 	},
-	[pbn_oxsemi_8_3906250] = {
+	[pbn_oxsemi_8_15625000] = {
 		.flags		= FL_BASE0,
 		.num_ports	= 8,
-		.base_baud	= 3906250,
+		.base_baud	= 15625000,
 		.uart_offset	= 0x200,
 		.first_offset	= 0x1000,
 	},
 	},
 };
+#define REPORT_CONFIG(option) \
+	(IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
+#define REPORT_8250_CONFIG(option) \
+	(IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
+	 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
 static const struct pci_device_id blacklist[] = {
 	/* softmodems */
 	{ PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
 	{ PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
 	/* multi-io cards handled by parport_serial */
-	{ PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
+	/* WCH CH353 2S1P */
-	{ PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
+	{ PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
-	{ PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
+	/* WCH CH353 1S1P */
+	{ PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
+	/* WCH CH382 2S1P */
+	{ PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
 	/* Intel platforms with MID UART */
-	{ PCI_VDEVICE(INTEL, 0x081b), },
+	{ PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
-	{ PCI_VDEVICE(INTEL, 0x081c), },
+	{ PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
-	{ PCI_VDEVICE(INTEL, 0x081d), },
+	{ PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
-	{ PCI_VDEVICE(INTEL, 0x1191), },
+	{ PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
-	{ PCI_VDEVICE(INTEL, 0x18d8), },
+	{ PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
-	{ PCI_VDEVICE(INTEL, 0x19d8), },
+	{ PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
 	/* Intel platforms with DesignWare UART */
-	{ PCI_VDEVICE(INTEL, 0x0936), },
+	{ PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x0f0a), },
+	{ PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x0f0c), },
+	{ PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x228a), },
+	{ PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x228c), },
+	{ PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x4b96), },
+	{ PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x4b97), },
+	{ PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x4b98), },
+	{ PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x4b99), },
+	{ PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x4b9a), },
+	{ PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x4b9b), },
+	{ PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x9ce3), },
+	{ PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
-	{ PCI_VDEVICE(INTEL, 0x9ce4), },
+	{ PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
 	/* Exar devices */
-	{ PCI_VDEVICE(EXAR, PCI_ANY_ID), },
+	{ PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
-	{ PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
+	{ PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
 	/* Pericom devices */
-	{ PCI_VDEVICE(PERICOM, PCI_ANY_ID), },
+	{ PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
-	{ PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), },
+	{ PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
 	/* End of the black list */
 	{ }
 	board = &pci_boards[ent->driver_data];
 	exclude = pci_match_id(blacklist, dev);
-	if (exclude)
+	if (exclude) {
+		if (exclude->driver_data)
+			pci_warn(dev, "ignoring port, enable %s to handle\n",
+				 (const char *)exclude->driver_data);
 		return -ENODEV;
+	}
 	rc = pcim_enable_device(dev);
 	pci_save_state(dev);
 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
 		0x10b5, 0x106a, 0, 0,
 		pbn_plx_romulus },
-	/*
-	* EndRun Technologies. PCI express device range.
-	*    EndRun PTP/1588 has 2 Native UARTs.
-	*/
-	{	PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
-		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_endrun_2_3906250 },
 	/*
 	 * Quatech cards. These actually have configurable clocks but for
 	 * now we just use the default.
 	 */
 	{	PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_b0_1_3906250 },
+		pbn_b0_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_b0_1_3906250 },
+		pbn_b0_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_b0_1_3906250 },
+		pbn_b0_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_b0_1_3906250 },
+		pbn_b0_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_b0_1_3906250 },
+		pbn_b0_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_b0_1_3906250 },
+		pbn_b0_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_b0_1_3906250 },
+		pbn_b0_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_b0_1_3906250 },
+		pbn_b0_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_2_3906250 },
+		pbn_oxsemi_2_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_2_3906250 },
+		pbn_oxsemi_2_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_4_3906250 },
+		pbn_oxsemi_4_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_4_3906250 },
+		pbn_oxsemi_4_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_8_3906250 },
+		pbn_oxsemi_8_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_8_3906250 },
+		pbn_oxsemi_8_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	/*
 	 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
 	 */
 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 1 Port V.34 Super-G3 Fax */
 		PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
-		pbn_oxsemi_1_3906250 },
+		pbn_oxsemi_1_15625000 },
 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 2 Port V.34 Super-G3 Fax */
 		PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
-		pbn_oxsemi_2_3906250 },
+		pbn_oxsemi_2_15625000 },
 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 4 Port V.34 Super-G3 Fax */
 		PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
-		pbn_oxsemi_4_3906250 },
+		pbn_oxsemi_4_15625000 },
 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 8 Port V.34 Super-G3 Fax */
 		PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
-		pbn_oxsemi_8_3906250 },
+		pbn_oxsemi_8_15625000 },
 	/*
 	 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
 	 */
 	{	PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
 		PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
-		pbn_oxsemi_2_3906250 },
+		pbn_oxsemi_2_15625000 },
+	/*
+	 * EndRun Technologies. PCI express device range.
+	 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
+	 */
+	{	PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
+		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+		pbn_oxsemi_2_15625000 },
 	/*
 	 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,

drivers/tty/serial/8250/8250_port.c+98−42

 		.tx_loadsz	= 63,
 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
 				  UART_FCR7_64BYTE,
-		.flags		= UART_CAP_FIFO,
+		.flags		= UART_CAP_FIFO | UART_CAP_NOTEMT,
 	},
 	[PORT_RT2880] = {
 		.name		= "Palmchip BK-3103",
 	}
 }
-/*
- * For the 16C950
- */
-static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
-{
-	serial_out(up, UART_SCR, offset);
-	serial_out(up, UART_ICR, value);
-}
-static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
-{
-	unsigned int value;
-	serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
-	serial_out(up, UART_SCR, offset);
-	value = serial_in(up, UART_ICR);
-	serial_icr_write(up, UART_ACR, up->acr);
-	return value;
-}
 /*
  * FIFO support.
  */
 	hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
 }
-static void __stop_tx_rs485(struct uart_8250_port *p)
+static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
 {
 	struct uart_8250_em485 *em485 = p->em485;
+	stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
 	/*
 	 * rs485_stop_tx() is going to set RTS according to config
 	 * AND flush RX FIFO if required.
 	 */
-	if (p->port.rs485.delay_rts_after_send > 0) {
+	if (stop_delay > 0) {
 		em485->active_timer = &em485->stop_tx_timer;
-		start_hrtimer_ms(&em485->stop_tx_timer,
+		hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
-				   p->port.rs485.delay_rts_after_send);
 	} else {
 		p->rs485_stop_tx(p);
 		em485->active_timer = NULL;
 	if (em485) {
 		unsigned char lsr = serial_in(p, UART_LSR);
+		u64 stop_delay = 0;
+		if (!(lsr & UART_LSR_THRE))
+			return;
 		/*
 		 * To provide required timeing and allow FIFO transfer,
 		 * __stop_tx_rs485() must be called only when both FIFO and
-		 * shift register are empty. It is for device driver to enable
+		 * shift register are empty. The device driver should either
-		 * interrupt on TEMT.
+		 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
+		 * enlarge stop_tx_timer by the tx time of one frame to cover
+		 * for emptying of the shift register.
 		 */
-		if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
+		if (!(lsr & UART_LSR_TEMT)) {
-			return;
+			if (!(p->capabilities & UART_CAP_NOTEMT))
+				return;
+			/*
+			 * RTS might get deasserted too early with the normal
+			 * frame timing formula. It seems to suggest THRE might
+			 * get asserted already during tx of the stop bit
+			 * rather than after it is fully sent.
+			 * Roughly estimate 1 extra bit here with / 7.
+			 */
+			stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
+		}
-		__stop_tx_rs485(p);
+		__stop_tx_rs485(p, stop_delay);
 	}
 	__do_stop_tx(p);
 }
 			status = serial8250_rx_chars(up, status);
 	}
 	serial8250_modem_status(up);
-	if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
+	if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
-		(up->ier & UART_IER_THRI))
+		if (!up->dma || up->dma->tx_err)
-		serial8250_tx_chars(up);
+			serial8250_tx_chars(up);
+		else
+			__stop_tx(up);
+	}
 	uart_unlock_and_check_sysrq_irqrestore(port, flags);
 	serial8250_rpm_put(up);
 }
-/*
+static void wait_for_lsr(struct uart_8250_port *up, int bits)
- *	Wait for transmitter & holding register to empty
- */
-static void wait_for_xmitr(struct uart_8250_port *up, int bits)
 {
 	unsigned int status, tmout = 10000;
 		udelay(1);
 		touch_nmi_watchdog();
 	}
+}
+/*
+ *	Wait for transmitter & holding register to empty
+ */
+static void wait_for_xmitr(struct uart_8250_port *up, int bits)
+{
+	unsigned int tmout;
+	wait_for_lsr(up, bits);
 	/* Wait up to 1s for flow control if necessary */
 	if (up->port.flags & UPF_CONS_FLOW) {
 	}
 	if (!(c_cflag & PARODD))
 		cval |= UART_LCR_EPAR;
-#ifdef CMSPAR
 	if (c_cflag & CMSPAR)
 		cval |= UART_LCR_SPAR;
-#endif
 	return cval;
 }
 	serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
 }
+/*
+ * Print a string to the serial port using the device FIFO
+ *
+ * It sends fifosize bytes and then waits for the fifo
+ * to get empty.
+ */
+static void serial8250_console_fifo_write(struct uart_8250_port *up,
+					  const char *s, unsigned int count)
+{
+	int i;
+	const char *end = s + count;
+	unsigned int fifosize = up->tx_loadsz;
+	bool cr_sent = false;
+	while (s != end) {
+		wait_for_lsr(up, UART_LSR_THRE);
+		for (i = 0; i < fifosize && s != end; ++i) {
+			if (*s == '\n' && !cr_sent) {
+				serial_out(up, UART_TX, '\r');
+				cr_sent = true;
+			} else {
+				serial_out(up, UART_TX, *s++);
+				cr_sent = false;
+			}
+		}
+	}
+}
 /*
  *	Print a string to the serial port trying not to disturb
  *	any possible real use of the port...
 	struct uart_8250_em485 *em485 = up->em485;
 	struct uart_port *port = &up->port;
 	unsigned long flags;
-	unsigned int ier;
+	unsigned int ier, use_fifo;
 	int locked = 1;
 	touch_nmi_watchdog();
 		mdelay(port->rs485.delay_rts_before_send);
 	}
-	uart_console_write(port, s, count, serial8250_console_putchar);
+	use_fifo = (up->capabilities & UART_CAP_FIFO) &&
+		/*
+		 * BCM283x requires to check the fifo
+		 * after each byte.
+		 */
+		!(up->capabilities & UART_CAP_MINI) &&
+		/*
+		 * tx_loadsz contains the transmit fifo size
+		 */
+		up->tx_loadsz > 1 &&
+		(up->fcr & UART_FCR_ENABLE_FIFO) &&
+		port->state &&
+		test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
+		/*
+		 * After we put a data in the fifo, the controller will send
+		 * it regardless of the CTS state. Therefore, only use fifo
+		 * if we don't use control flow.
+		 */
+		!(up->port.flags & UPF_CONS_FLOW);
+	if (likely(use_fifo))
+		serial8250_console_fifo_write(up, s, count);
+	else
+		uart_console_write(port, s, count, serial8250_console_putchar);
 	/*
 	 *	Finally, wait for transmitter to become empty

drivers/tty/serial/8250/8250_pxa.c+0−1

@@ -22,7 +22,6 @@ · 21 unmodified lines
22	#include <linux/platform_device.h>	22	#include <linux/platform_device.h>
23	#include <linux/slab.h>	23	#include <linux/slab.h>
24	#include <linux/clk.h>	24	#include <linux/clk.h>
25	#include <linux/pm_runtime.h>
26		25
27	#include "8250.h"	26	#include "8250.h"
28		27

drivers/tty/serial/8250/Kconfig+1−1

@@ -380,7 +380,7 @@ config SERIAL_8250_DW · 379 unmodified lines
380	config SERIAL_8250_EM	380	config SERIAL_8250_EM
381	tristate "Support for Emma Mobile integrated serial port"	381	tristate "Support for Emma Mobile integrated serial port"
382	depends on SERIAL_8250 && HAVE_CLK	382	depends on SERIAL_8250 && HAVE_CLK
383	depends on (ARM && ARCH_RENESAS) \|\| COMPILE_TEST	383	depends on ARCH_RENESAS \|\| COMPILE_TEST
384	help	384	help
385	Selecting this option will add support for the integrated serial	385	Selecting this option will add support for the integrated serial
386	port hardware found on the Emma Mobile line of processors.	386	port hardware found on the Emma Mobile line of processors.

drivers/tty/serial/Kconfig+5−4

 config SERIAL_CPM
 	tristate "CPM SCC/SMC serial port support"
-	depends on CPM2 || CPM1
+	depends on CPM2 || CPM1 || (PPC32 && COMPILE_TEST)
 	select SERIAL_CORE
 	help
 	  This driver supports the SCC and SMC serial ports on Motorola
 config SERIAL_PIC32
 	tristate "Microchip PIC32 serial support"
-	depends on MACH_PIC32
+	depends on MACH_PIC32 || (MIPS && COMPILE_TEST)
 	select SERIAL_CORE
 	help
 	  If you have a PIC32, this driver supports the serial ports.
 config SERIAL_PIC32_CONSOLE
 	bool "PIC32 serial console support"
-	depends on SERIAL_PIC32
+	depends on SERIAL_PIC32=y
 	select SERIAL_CORE_CONSOLE
 	help
 	  If you have a PIC32, this driver supports the putting a console on one
 config SERIAL_AR933X
 	tristate "AR933X serial port support"
-	depends on HAVE_CLK && ATH79
+	depends on (HAVE_CLK && ATH79) || (MIPS && COMPILE_TEST)
 	select SERIAL_CORE
 	select SERIAL_MCTRL_GPIO if GPIOLIB
 	help
 	bool "Support for console on STM32"
 	depends on SERIAL_STM32=y
 	select SERIAL_CORE_CONSOLE
+	select SERIAL_EARLYCON
 config SERIAL_MVEBU_UART
 	bool "Marvell EBU serial port support"

drivers/tty/serial/altera_jtaguart.c+2−4

 		}
 	}
-	if (pending == 0) {
+	if (pending == 0)
-		pp->imr &= ~ALTERA_JTAGUART_CONTROL_WE_MSK;
+		altera_jtaguart_stop_tx(port);
-		writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG);
-	}
 }
 static irqreturn_t altera_jtaguart_interrupt(int irq, void *data)

drivers/tty/serial/amba-pl011.c+31−17

 #include <linux/io.h>
 #include <linux/acpi.h>
-#include "amba-pl011.h"
 #define UART_NR			14
 #define SERIAL_AMBA_MAJOR	204
 #define UART_DR_ERROR		(UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
 #define UART_DUMMY_DR_RX	(1 << 16)
+enum {
+	REG_DR,
+	REG_ST_DMAWM,
+	REG_ST_TIMEOUT,
+	REG_FR,
+	REG_LCRH_RX,
+	REG_LCRH_TX,
+	REG_IBRD,
+	REG_FBRD,
+	REG_CR,
+	REG_IFLS,
+	REG_IMSC,
+	REG_RIS,
+	REG_MIS,
+	REG_ICR,
+	REG_DMACR,
+	REG_ST_XFCR,
+	REG_ST_XON1,
+	REG_ST_XON2,
+	REG_ST_XOFF1,
+	REG_ST_XOFF2,
+	REG_ST_ITCR,
+	REG_ST_ITIP,
+	REG_ST_ABCR,
+	REG_ST_ABIMSC,
+	/* The size of the array - must be last */
+	REG_ARRAY_SIZE,
+};
 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
 	[REG_DR] = UART01x_DR,
 	[REG_FR] = UART01x_FR,
 	struct uart_amba_port *uap =
 		container_of(port, struct uart_amba_port, port);
-	/* pick sane settings if the user hasn't */
-	if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
-	    !(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
-		rs485->flags |= SER_RS485_RTS_ON_SEND;
-		rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
-	}
-	/* clamp the delays to [0, 100ms] */
-	rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
-	rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
-	memset(rs485->padding, 0, sizeof(rs485->padding));
 	if (port->rs485.flags & SER_RS485_ENABLED)
 		pl011_rs485_tx_stop(uap);
-	/* Set new configuration */
-	port->rs485 = *rs485;
 	/* Make sure auto RTS is disabled */
-	if (port->rs485.flags & SER_RS485_ENABLED) {
+	if (rs485->flags & SER_RS485_ENABLED) {
 		u32 cr = pl011_read(uap, REG_CR);
 		cr &= ~UART011_CR_RTSEN;

drivers/tty/serial/amba-pl011.h+0−35

@@ -1,35 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 */
2	#ifndef AMBA_PL011_H
3	#define AMBA_PL011_H
4
5	enum {
6	REG_DR,
7	REG_ST_DMAWM,
8	REG_ST_TIMEOUT,
9	REG_FR,
10	REG_LCRH_RX,
11	REG_LCRH_TX,
12	REG_IBRD,
13	REG_FBRD,
14	REG_CR,
15	REG_IFLS,
16	REG_IMSC,
17	REG_RIS,
18	REG_MIS,
19	REG_ICR,
20	REG_DMACR,
21	REG_ST_XFCR,
22	REG_ST_XON1,
23	REG_ST_XON2,
24	REG_ST_XOFF1,
25	REG_ST_XOFF2,
26	REG_ST_ITCR,
27	REG_ST_ITIP,
28	REG_ST_ABCR,
29	REG_ST_ABIMSC,
30
31	/* The size of the array - must be last */
32	REG_ARRAY_SIZE,
33	};
34
35	#endif

drivers/tty/serial/atmel_serial.c+1−3

 	/* Resetting serial mode to RS232 (0x0) */
 	mode &= ~ATMEL_US_USMODE;
-	port->rs485 = *rs485conf;
 	if (rs485conf->flags & SER_RS485_ENABLED) {
 		dev_dbg(port->dev, "Setting UART to RS485\n");
-		if (port->rs485.flags & SER_RS485_RX_DURING_TX)
+		if (rs485conf->flags & SER_RS485_RX_DURING_TX)
 			atmel_port->tx_done_mask = ATMEL_US_TXRDY;
 		else
 			atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;

drivers/tty/serial/cpm_uart/cpm_uart.h+2−0

@@ -19,6 +19,8 @@ struct gpio_desc; · 18 unmodified lines
19	#include "cpm_uart_cpm2.h"	19	#include "cpm_uart_cpm2.h"
20	#elif defined(CONFIG_CPM1)	20	#elif defined(CONFIG_CPM1)
21	#include "cpm_uart_cpm1.h"	21	#include "cpm_uart_cpm1.h"
		22	#elif defined(CONFIG_COMPILE_TEST)
		23	#include "cpm_uart_cpm2.h"
22	#endif	24	#endif
23		25
24	#define SERIAL_CPM_MAJOR 204	26	#define SERIAL_CPM_MAJOR 204

drivers/tty/serial/cpm_uart/cpm_uart_core.c+1−1

@@ -1247,7 +1247,7 @@ static int cpm_uart_init_port(struct device_node *np, · 1246 unmodified lines
1247	}	1247	}
1248		1248
1249	#ifdef CONFIG_PPC_EARLY_DEBUG_CPM	1249	#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1250	#ifdef CONFIG_CONSOLE_POLL	1250	#if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_CPM_CONSOLE)
1251	if (!udbg_port)	1251	if (!udbg_port)
1252	#endif	1252	#endif
1253	udbg_putc = NULL;	1253	udbg_putc = NULL;

drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c+0−1

@@ -25,7 +25,6 @@ · 24 unmodified lines
25	#include <asm/io.h>	25	#include <asm/io.h>
26	#include <asm/irq.h>	26	#include <asm/irq.h>
27	#include <asm/fs_pd.h>	27	#include <asm/fs_pd.h>
28	#include <asm/prom.h>
29		28
30	#include <linux/serial_core.h>	29	#include <linux/serial_core.h>
31	#include <linux/kernel.h>	30	#include <linux/kernel.h>

drivers/tty/serial/digicolor-usart.c+2−0

@@ -309,6 +309,8 @@ static void digicolor_uart_set_termios(struct uart_port *port, · 308 unmodified lines
309	case CS8:	309	case CS8:
310	default:	310	default:
311	config \|= UA_CONFIG_CHAR_LEN;	311	config \|= UA_CONFIG_CHAR_LEN;
		312	termios->c_cflag &= ~CSIZE;
		313	termios->c_cflag \|= CS8;
312	break;	314	break;
313	}	315	}
314		316

drivers/tty/serial/fsl_lpuart.c+8−58

 /* IMX lpuart has four extra unused regs located at the beginning */
 #define IMX_REG_OFF	0x10
-static DEFINE_IDA(fsl_lpuart_ida);
 enum lpuart_type {
 	VF610_LPUART,
 	LS1021A_LPUART,
 	int			rx_dma_rng_buf_len;
 	unsigned int		dma_tx_nents;
 	wait_queue_head_t	dma_wait;
-	bool			id_allocated;
 };
 struct lpuart_soc_data {
 	struct dma_chan *chan = sport->dma_rx_chan;
 	struct circ_buf *ring = &sport->rx_ring;
 	unsigned long flags;
-	int count = 0, copied;
+	int count, copied;
 	if (lpuart_is_32(sport)) {
 		unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
 		/* Enable auto RS-485 RTS mode */
 		modem |= UARTMODEM_TXRTSE;
-		/*
-		 * RTS needs to be logic HIGH either during transfer _or_ after
-		 * transfer, other variants are not supported by the hardware.
-		 */
-		if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
-				SER_RS485_RTS_AFTER_SEND)))
-			rs485->flags |= SER_RS485_RTS_ON_SEND;
-		if (rs485->flags & SER_RS485_RTS_ON_SEND &&
-				rs485->flags & SER_RS485_RTS_AFTER_SEND)
-			rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
 		/*
 		 * The hardware defaults to RTS logic HIGH while transfer.
 		 * Switch polarity in case RTS shall be logic HIGH
 			modem |= UARTMODEM_TXRTSPOL;
 	}
-	/* Store the new configuration */
-	sport->port.rs485 = *rs485;
 	writeb(modem, sport->port.membase + UARTMODEM);
 	return 0;
 }
 		/* Enable auto RS-485 RTS mode */
 		modem |= UARTMODEM_TXRTSE;
-		/*
-		 * RTS needs to be logic HIGH either during transfer _or_ after
-		 * transfer, other variants are not supported by the hardware.
-		 */
-		if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
-				SER_RS485_RTS_AFTER_SEND)))
-			rs485->flags |= SER_RS485_RTS_ON_SEND;
-		if (rs485->flags & SER_RS485_RTS_ON_SEND &&
-				rs485->flags & SER_RS485_RTS_AFTER_SEND)
-			rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
 		/*
 		 * The hardware defaults to RTS logic HIGH while transfer.
 		 * Switch polarity in case RTS shall be logic HIGH
 			modem |= UARTMODEM_TXRTSPOL;
 	}
-	/* Store the new configuration */
-	sport->port.rs485 = *rs485;
 	lpuart32_write(&sport->port, modem, UARTMODIR);
 	return 0;
 }
 	if (sport->port.rs485.flags & SER_RS485_ENABLED)
 		termios->c_cflag &= ~CRTSCTS;
-	if (termios->c_cflag & CRTSCTS) {
+	if (termios->c_cflag & CRTSCTS)
-		modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
+		modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE;
-	} else {
+	else
-		termios->c_cflag &= ~CRTSCTS;
 		modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
-	}
 	if (termios->c_cflag & CSTOPB)
 		bd |= UARTBAUD_SBNS;
 	ret = of_alias_get_id(np, "serial");
 	if (ret < 0) {
-		ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
+		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
-		if (ret < 0) {
+		return ret;
-			dev_err(&pdev->dev, "port line is full, add device failed\n");
-			return ret;
-		}
-		sport->id_allocated = true;
 	}
 	if (ret >= ARRAY_SIZE(lpuart_ports)) {
 		dev_err(&pdev->dev, "serial%d out of range\n", ret);
-		ret = -EINVAL;
+		return -EINVAL;
-		goto failed_out_of_range;
 	}
 	sport->port.line = ret;
 	ret = lpuart_enable_clks(sport);
 	if (ret)
-		goto failed_clock_enable;
+		return ret;
 	sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
 	lpuart_ports[sport->port.line] = sport;
 	uart_remove_one_port(&lpuart_reg, &sport->port);
 failed_attach_port:
 	lpuart_disable_clks(sport);
-failed_clock_enable:
-failed_out_of_range:
-	if (sport->id_allocated)
-		ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
 	return ret;
 }
 	uart_remove_one_port(&lpuart_reg, &sport->port);
-	if (sport->id_allocated)
-		ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
 	lpuart_disable_clks(sport);
 	if (sport->dma_tx_chan)
 static void __exit lpuart_serial_exit(void)
 {
-	ida_destroy(&fsl_lpuart_ida);
 	platform_driver_unregister(&lpuart_driver);
 	uart_unregister_driver(&lpuart_reg);
 }

drivers/tty/serial/icom.c+386−152

@@ -19,6 +19,7 @@ · 18 unmodified lines
19	#include <linux/fs.h>	19	#include <linux/fs.h>
20	#include <linux/tty_flip.h>	20	#include <linux/tty_flip.h>
21	#include <linux/serial.h>	21	#include <linux/serial.h>
		22	#include <linux/serial_core.h>
22	#include <linux/serial_reg.h>	23	#include <linux/serial_reg.h>
23	#include <linux/major.h>	24	#include <linux/major.h>
24	#include <linux/string.h>	25	#include <linux/string.h>
@@ -41,15 +42,273 @@ · 16 unmodified lines
41	#include <asm/irq.h>	42	#include <asm/irq.h>
42	#include <linux/uaccess.h>	43	#include <linux/uaccess.h>
43		44
44	#include "icom.h"
45
46	/#define ICOM_TRACE enable port trace capabilities /	45	/#define ICOM_TRACE enable port trace capabilities /
47		46
48	#define ICOM_DRIVER_NAME "icom"	47	#define ICOM_DRIVER_NAME "icom"
49	#define ICOM_VERSION_STR "1.3.1"
50	#define NR_PORTS 128	48	#define NR_PORTS 128
51	#define ICOM_PORT ((struct icom_port *)port)	49
52	#define to_icom_adapter(d) container_of(d, struct icom_adapter, kref)	50	static const unsigned int icom_acfg_baud[] = {
		51	300,
		52	600,
		53	900,
		54	1200,
		55	1800,
		56	2400,
		57	3600,
		58	4800,
		59	7200,
		60	9600,
		61	14400,
		62	19200,
		63	28800,
		64	38400,
		65	57600,
		66	76800,
		67	115200,
		68	153600,
		69	230400,
		70	307200,
		71	460800,
		72	};
		73	#define BAUD_TABLE_LIMIT (ARRAY_SIZE(icom_acfg_baud) - 1)
		74
		75	struct icom_regs {
		76	u32 control; /* Adapter Control Register */
		77	u32 interrupt; /* Adapter Interrupt Register */
		78	u32 int_mask; /* Adapter Interrupt Mask Reg */
		79	u32 int_pri; /* Adapter Interrupt Priority r */
		80	u32 int_reg_b; /* Adapter non-masked Interrupt */
		81	u32 resvd01;
		82	u32 resvd02;
		83	u32 resvd03;
		84	u32 control_2; /* Adapter Control Register 2 */
		85	u32 interrupt_2; /* Adapter Interrupt Register 2 */
		86	u32 int_mask_2; /* Adapter Interrupt Mask 2 */
		87	u32 int_pri_2; /* Adapter Interrupt Prior 2 */
		88	u32 int_reg_2b; /* Adapter non-masked 2 */
		89	};
		90
		91	struct func_dram {
		92	u32 reserved[108]; /* 0-1B0 reserved by personality code */
		93	u32 RcvStatusAddr; /* 1B0-1B3 Status Address for Next rcv */
		94	u8 RcvStnAddr; /* 1B4 Receive Station Addr */
		95	u8 IdleState; /* 1B5 Idle State */
		96	u8 IdleMonitor; /* 1B6 Idle Monitor */
		97	u8 FlagFillIdleTimer; /* 1B7 Flag Fill Idle Timer */
		98	u32 XmitStatusAddr; /* 1B8-1BB Transmit Status Address */
		99	u8 StartXmitCmd; /* 1BC Start Xmit Command */
		100	u8 HDLCConfigReg; /* 1BD Reserved */
		101	u8 CauseCode; /* 1BE Cause code for fatal error */
		102	u8 xchar; /* 1BF High priority send */
		103	u32 reserved3; /* 1C0-1C3 Reserved */
		104	u8 PrevCmdReg; /* 1C4 Reserved */
		105	u8 CmdReg; /* 1C5 Command Register */
		106	u8 async_config2; /* 1C6 Async Config Byte 2 */
		107	u8 async_config3; /* 1C7 Async Config Byte 3 */
		108	u8 dce_resvd[20]; /* 1C8-1DB DCE Rsvd */
		109	u8 dce_resvd21; /* 1DC DCE Rsvd (21st byte */
		110	u8 misc_flags; /* 1DD misc flags */
		111	#define V2_HARDWARE 0x40
		112	#define ICOM_HDW_ACTIVE 0x01
		113	u8 call_length; /* 1DE Phone #/CFI buff ln */
		114	u8 call_length2; /* 1DF Upper byte (unused) */
		115	u32 call_addr; /* 1E0-1E3 Phn #/CFI buff addr */
		116	u16 timer_value; /* 1E4-1E5 general timer value */
		117	u8 timer_command; /* 1E6 general timer cmd */
		118	u8 dce_command; /* 1E7 dce command reg */
		119	u8 dce_cmd_status; /* 1E8 dce command stat */
		120	u8 x21_r1_ioff; /* 1E9 dce ready counter */
		121	u8 x21_r0_ioff; /* 1EA dce not ready ctr */
		122	u8 x21_ralt_ioff; /* 1EB dce CNR counter */
		123	u8 x21_r1_ion; /* 1EC dce ready I on ctr */
		124	u8 rsvd_ier; /* 1ED Rsvd for IER (if ne */
		125	u8 ier; /* 1EE Interrupt Enable */
		126	u8 isr; /* 1EF Input Signal Reg */
		127	u8 osr; /* 1F0 Output Signal Reg */
		128	u8 reset; /* 1F1 Reset/Reload Reg */
		129	u8 disable; /* 1F2 Disable Reg */
		130	u8 sync; /* 1F3 Sync Reg */
		131	u8 error_stat; /* 1F4 Error Status */
		132	u8 cable_id; /* 1F5 Cable ID */
		133	u8 cs_length; /* 1F6 CS Load Length */
		134	u8 mac_length; /* 1F7 Mac Load Length */
		135	u32 cs_load_addr; /* 1F8-1FB Call Load PCI Addr */
		136	u32 mac_load_addr; /* 1FC-1FF Mac Load PCI Addr */
		137	};
		138
		139	/*
		140	* adapter defines and structures
		141	*/
		142	#define ICOM_CONTROL_START_A 0x00000008
		143	#define ICOM_CONTROL_STOP_A 0x00000004
		144	#define ICOM_CONTROL_START_B 0x00000002
		145	#define ICOM_CONTROL_STOP_B 0x00000001
		146	#define ICOM_CONTROL_START_C 0x00000008
		147	#define ICOM_CONTROL_STOP_C 0x00000004
		148	#define ICOM_CONTROL_START_D 0x00000002
		149	#define ICOM_CONTROL_STOP_D 0x00000001
		150	#define ICOM_IRAM_OFFSET 0x1000
		151	#define ICOM_IRAM_SIZE 0x0C00
		152	#define ICOM_DCE_IRAM_OFFSET 0x0A00
		153	#define ICOM_CABLE_ID_VALID 0x01
		154	#define ICOM_CABLE_ID_MASK 0xF0
		155	#define ICOM_DISABLE 0x80
		156	#define CMD_XMIT_RCV_ENABLE 0xC0
		157	#define CMD_XMIT_ENABLE 0x40
		158	#define CMD_RCV_DISABLE 0x00
		159	#define CMD_RCV_ENABLE 0x80
		160	#define CMD_RESTART 0x01
		161	#define CMD_HOLD_XMIT 0x02
		162	#define CMD_SND_BREAK 0x04
		163	#define RS232_CABLE 0x06
		164	#define V24_CABLE 0x0E
		165	#define V35_CABLE 0x0C
		166	#define V36_CABLE 0x02
		167	#define NO_CABLE 0x00
		168	#define START_DOWNLOAD 0x80
		169	#define ICOM_INT_MASK_PRC_A 0x00003FFF
		170	#define ICOM_INT_MASK_PRC_B 0x3FFF0000
		171	#define ICOM_INT_MASK_PRC_C 0x00003FFF
		172	#define ICOM_INT_MASK_PRC_D 0x3FFF0000
		173	#define INT_RCV_COMPLETED 0x1000
		174	#define INT_XMIT_COMPLETED 0x2000
		175	#define INT_IDLE_DETECT 0x0800
		176	#define INT_RCV_DISABLED 0x0400
		177	#define INT_XMIT_DISABLED 0x0200
		178	#define INT_RCV_XMIT_SHUTDOWN 0x0100
		179	#define INT_FATAL_ERROR 0x0080
		180	#define INT_CABLE_PULL 0x0020
		181	#define INT_SIGNAL_CHANGE 0x0010
		182	#define HDLC_PPP_PURE_ASYNC 0x02
		183	#define HDLC_FF_FILL 0x00
		184	#define HDLC_HDW_FLOW 0x01
		185	#define START_XMIT 0x80
		186	#define ICOM_ACFG_DRIVE1 0x20
		187	#define ICOM_ACFG_NO_PARITY 0x00
		188	#define ICOM_ACFG_PARITY_ENAB 0x02
		189	#define ICOM_ACFG_PARITY_ODD 0x01
		190	#define ICOM_ACFG_8BPC 0x00
		191	#define ICOM_ACFG_7BPC 0x04
		192	#define ICOM_ACFG_6BPC 0x08
		193	#define ICOM_ACFG_5BPC 0x0C
		194	#define ICOM_ACFG_1STOP_BIT 0x00
		195	#define ICOM_ACFG_2STOP_BIT 0x10
		196	#define ICOM_DTR 0x80
		197	#define ICOM_RTS 0x40
		198	#define ICOM_RI 0x08
		199	#define ICOM_DSR 0x80
		200	#define ICOM_DCD 0x20
		201	#define ICOM_CTS 0x40
		202
		203	#define NUM_XBUFFS 1
		204	#define NUM_RBUFFS 2
		205	#define RCV_BUFF_SZ 0x0200
		206	#define XMIT_BUFF_SZ 0x1000
		207	struct statusArea {
		208	/**********************************************/
		209	/* Transmit Status Area */
		210	/**********************************************/
		211	struct xmit_status_area{
		212	__le32 leNext; /* Next entry in Little Endian on Adapter */
		213	__le32 leNextASD;
		214	__le32 leBuffer; /* Buffer for entry in LE for Adapter */
		215	__le16 leLengthASD;
		216	__le16 leOffsetASD;
		217	__le16 leLength; /* Length of data in segment */
		218	__le16 flags;
		219	#define SA_FLAGS_DONE 0x0080 /* Done with Segment */
		220	#define SA_FLAGS_CONTINUED 0x8000 /* More Segments */
		221	#define SA_FLAGS_IDLE 0x4000 /* Mark IDLE after frm */
		222	#define SA_FLAGS_READY_TO_XMIT 0x0800
		223	#define SA_FLAGS_STAT_MASK 0x007F
		224	} xmit[NUM_XBUFFS];
		225
		226	/**********************************************/
		227	/* Receive Status Area */
		228	/**********************************************/
		229	struct {
		230	__le32 leNext; /* Next entry in Little Endian on Adapter */
		231	__le32 leNextASD;
		232	__le32 leBuffer; /* Buffer for entry in LE for Adapter */
		233	__le16 WorkingLength; /* size of segment */
		234	__le16 reserv01;
		235	__le16 leLength; /* Length of data in segment */
		236	__le16 flags;
		237	#define SA_FL_RCV_DONE 0x0010 /* Data ready */
		238	#define SA_FLAGS_OVERRUN 0x0040
		239	#define SA_FLAGS_PARITY_ERROR 0x0080
		240	#define SA_FLAGS_FRAME_ERROR 0x0001
		241	#define SA_FLAGS_FRAME_TRUNC 0x0002
		242	#define SA_FLAGS_BREAK_DET 0x0004 /* set conditionally by device driver, not hardware */
		243	#define SA_FLAGS_RCV_MASK 0xFFE6
		244	} rcv[NUM_RBUFFS];
		245	};
		246
		247	struct icom_adapter;
		248
		249
		250	#define ICOM_MAJOR 243
		251	#define ICOM_MINOR_START 0
		252
		253	struct icom_port {
		254	struct uart_port uart_port;
		255	unsigned char cable_id;
		256	unsigned char read_status_mask;
		257	unsigned char ignore_status_mask;
		258	void __iomem * int_reg;
		259	struct icom_regs __iomem *global_reg;
		260	struct func_dram __iomem *dram;
		261	int port;
		262	struct statusArea *statStg;
		263	dma_addr_t statStg_pci;
		264	__le32 *xmitRestart;
		265	dma_addr_t xmitRestart_pci;
		266	unsigned char *xmit_buf;
		267	dma_addr_t xmit_buf_pci;
		268	unsigned char *recv_buf;
		269	dma_addr_t recv_buf_pci;
		270	int next_rcv;
		271	int status;
		272	#define ICOM_PORT_ACTIVE 1 /* Port exists. */
		273	#define ICOM_PORT_OFF 0 /* Port does not exist. */
		274	struct icom_adapter *adapter;
		275	};
		276
		277	struct icom_adapter {
		278	void __iomem * base_addr;
		279	unsigned long base_addr_pci;
		280	struct pci_dev *pci_dev;
		281	struct icom_port port_info[4];
		282	int index;
		283	int version;
		284	#define ADAPTER_V1 0x0001
		285	#define ADAPTER_V2 0x0002
		286	u32 subsystem_id;
		287	#define FOUR_PORT_MODEL 0x0252
		288	#define V2_TWO_PORTS_RVX 0x021A
		289	#define V2_ONE_PORT_RVX_ONE_PORT_IMBED_MDM 0x0251
		290	int numb_ports;
		291	struct list_head icom_adapter_entry;
		292	struct kref kref;
		293	};
		294
		295	/* prototype */
		296	extern void iCom_sercons_init(void);
		297
		298	struct lookup_proc_table {
		299	u32 __iomem *global_control_reg;
		300	unsigned long processor_id;
		301	};
		302
		303	struct lookup_int_table {
		304	u32 __iomem *global_int_mask;
		305	unsigned long processor_id;
		306	};
		307
		308	static inline struct icom_port to_icom_port(struct uart_port port)
		309	{
		310	return container_of(port, struct icom_port, uart_port);
		311	}
53		312
54	static const struct pci_device_id icom_pci_table[] = {	313	static const struct pci_device_id icom_pci_table[] = {
55	{	314	{
@@ -222,7 +481,7 @@ static int get_port_memory(struct icom_port *icom_port) · 166 unmodified lines
222	if (index < (NUM_XBUFFS - 1)) {	481	if (index < (NUM_XBUFFS - 1)) {
223	memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));	482	memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
224	icom_port->statStg->xmit[index].leLengthASD =	483	icom_port->statStg->xmit[index].leLengthASD =
225	(unsigned short int) cpu_to_le16(XMIT_BUFF_SZ);	484	cpu_to_le16(XMIT_BUFF_SZ);
226	trace(icom_port, "FOD_ADDR", stgAddr);	485	trace(icom_port, "FOD_ADDR", stgAddr);
227	trace(icom_port, "FOD_XBUFF",	486	trace(icom_port, "FOD_XBUFF",
228	(unsigned long) icom_port->xmit_buf);	487	(unsigned long) icom_port->xmit_buf);
@@ -231,7 +490,7 @@ static int get_port_memory(struct icom_port *icom_port) · 2 unmodified lines
231	} else if (index == (NUM_XBUFFS - 1)) {	490	} else if (index == (NUM_XBUFFS - 1)) {
232	memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));	491	memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
233	icom_port->statStg->xmit[index].leLengthASD =	492	icom_port->statStg->xmit[index].leLengthASD =
234	(unsigned short int) cpu_to_le16(XMIT_BUFF_SZ);	493	cpu_to_le16(XMIT_BUFF_SZ);
235	trace(icom_port, "FOD_XBUFF",	494	trace(icom_port, "FOD_XBUFF",
236	(unsigned long) icom_port->xmit_buf);	495	(unsigned long) icom_port->xmit_buf);
237	icom_port->statStg->xmit[index].leBuffer =	496	icom_port->statStg->xmit[index].leBuffer =
@@ -249,7 +508,7 @@ static int get_port_memory(struct icom_port *icom_port) · 11 unmodified lines
249	stgAddr = stgAddr + sizeof(icom_port->statStg->rcv[0]);	508	stgAddr = stgAddr + sizeof(icom_port->statStg->rcv[0]);
250	icom_port->statStg->rcv[index].leLength = 0;	509	icom_port->statStg->rcv[index].leLength = 0;
251	icom_port->statStg->rcv[index].WorkingLength =	510	icom_port->statStg->rcv[index].WorkingLength =
252	(unsigned short int) cpu_to_le16(RCV_BUFF_SZ);	511	cpu_to_le16(RCV_BUFF_SZ);
253	if (index < (NUM_RBUFFS - 1) ) {	512	if (index < (NUM_RBUFFS - 1) ) {
254	offset = stgAddr - (unsigned long) icom_port->statStg;	513	offset = stgAddr - (unsigned long) icom_port->statStg;
255	icom_port->statStg->rcv[index].leNext =	514	icom_port->statStg->rcv[index].leNext =
@@ -617,16 +876,17 @@ unlock: · 361 unmodified lines
617		876
618	static int icom_write(struct uart_port *port)	877	static int icom_write(struct uart_port *port)
619	{	878	{
		879	struct icom_port *icom_port = to_icom_port(port);
620	unsigned long data_count;	880	unsigned long data_count;
621	unsigned char cmdReg;	881	unsigned char cmdReg;
622	unsigned long offset;	882	unsigned long offset;
623	int temp_tail = port->state->xmit.tail;	883	int temp_tail = port->state->xmit.tail;
624		884
625	trace(ICOM_PORT, "WRITE", 0);	885	trace(icom_port, "WRITE", 0);
626		886
627	if (cpu_to_le16(ICOM_PORT->statStg->xmit[0].flags) &	887	if (le16_to_cpu(icom_port->statStg->xmit[0].flags) &
628	SA_FLAGS_READY_TO_XMIT) {	888	SA_FLAGS_READY_TO_XMIT) {
629	trace(ICOM_PORT, "WRITE_FULL", 0);	889	trace(icom_port, "WRITE_FULL", 0);
630	return 0;	890	return 0;
631	}	891	}
632		892
@@ -634,7 +894,7 @@ static int icom_write(struct uart_port *port) · 1 unmodified line
634	while ((port->state->xmit.head != temp_tail) &&	894	while ((port->state->xmit.head != temp_tail) &&
635	(data_count <= XMIT_BUFF_SZ)) {	895	(data_count <= XMIT_BUFF_SZ)) {
636		896
637	ICOM_PORT->xmit_buf[data_count++] =	897	icom_port->xmit_buf[data_count++] =
638	port->state->xmit.buf[temp_tail];	898	port->state->xmit.buf[temp_tail];
639		899
640	temp_tail++;	900	temp_tail++;
@@ -642,22 +902,22 @@ static int icom_write(struct uart_port *port) · 1 unmodified line
642	}	902	}
643		903
644	if (data_count) {	904	if (data_count) {
645	ICOM_PORT->statStg->xmit[0].flags =	905	icom_port->statStg->xmit[0].flags =
646	cpu_to_le16(SA_FLAGS_READY_TO_XMIT);	906	cpu_to_le16(SA_FLAGS_READY_TO_XMIT);
647	ICOM_PORT->statStg->xmit[0].leLength =	907	icom_port->statStg->xmit[0].leLength =
648	cpu_to_le16(data_count);	908	cpu_to_le16(data_count);
649	offset =	909	offset =
650	(unsigned long) &ICOM_PORT->statStg->xmit[0] -	910	(unsigned long) &icom_port->statStg->xmit[0] -
651	(unsigned long) ICOM_PORT->statStg;	911	(unsigned long) icom_port->statStg;
652	*ICOM_PORT->xmitRestart =	912	*icom_port->xmitRestart =
653	cpu_to_le32(ICOM_PORT->statStg_pci + offset);	913	cpu_to_le32(icom_port->statStg_pci + offset);
654	cmdReg = readb(&ICOM_PORT->dram->CmdReg);	914	cmdReg = readb(&icom_port->dram->CmdReg);
655	writeb(cmdReg \| CMD_XMIT_RCV_ENABLE,	915	writeb(cmdReg \| CMD_XMIT_RCV_ENABLE,
656	&ICOM_PORT->dram->CmdReg);	916	&icom_port->dram->CmdReg);
657	writeb(START_XMIT, &ICOM_PORT->dram->StartXmitCmd);	917	writeb(START_XMIT, &icom_port->dram->StartXmitCmd);
658	trace(ICOM_PORT, "WRITE_START", data_count);	918	trace(icom_port, "WRITE_START", data_count);
659	/* write flush */	919	/* write flush */
660	readb(&ICOM_PORT->dram->StartXmitCmd);	920	readb(&icom_port->dram->StartXmitCmd);
661	}	921	}
662		922
663	return data_count;	923	return data_count;
@@ -696,8 +956,7 @@ static inline void check_modem_status(struct icom_port *icom_port) · 32 unmodified lines
696		956
697	static void xmit_interrupt(u16 port_int_reg, struct icom_port *icom_port)	957	static void xmit_interrupt(u16 port_int_reg, struct icom_port *icom_port)
698	{	958	{
699	unsigned short int count;	959	u16 count, i;
700	int i;
701		960
702	if (port_int_reg & (INT_XMIT_COMPLETED)) {	961	if (port_int_reg & (INT_XMIT_COMPLETED)) {
703	trace(icom_port, "XMIT_COMPLETE", 0);	962	trace(icom_port, "XMIT_COMPLETE", 0);
@@ -706,8 +965,7 @@ static void xmit_interrupt(u16 port_int_reg, struct icom_port *icom_port) · 2 unmodified lines
706	icom_port->statStg->xmit[0].flags &=	965	icom_port->statStg->xmit[0].flags &=
707	cpu_to_le16(~SA_FLAGS_READY_TO_XMIT);	966	cpu_to_le16(~SA_FLAGS_READY_TO_XMIT);
708		967
709	count = (unsigned short int)	968	count = le16_to_cpu(icom_port->statStg->xmit[0].leLength);
710	cpu_to_le16(icom_port->statStg->xmit[0].leLength);
711	icom_port->uart_port.icount.tx += count;	969	icom_port->uart_port.icount.tx += count;
712		970
713	for (i=0; i<count &&	971	for (i=0; i<count &&
@@ -729,7 +987,7 @@ static void recv_interrupt(u16 port_int_reg, struct icom_port *icom_port) · 15 unmodified lines
729	{	987	{
730	short int count, rcv_buff;	988	short int count, rcv_buff;
731	struct tty_port *port = &icom_port->uart_port.state->port;	989	struct tty_port *port = &icom_port->uart_port.state->port;
732	unsigned short int status;	990	u16 status;
733	struct uart_icount *icount;	991	struct uart_icount *icount;
734	unsigned long offset;	992	unsigned long offset;
735	unsigned char flag;	993	unsigned char flag;
@@ -737,19 +995,18 @@ static void recv_interrupt(u16 port_int_reg, struct icom_port *icom_port) · 1 unmodified line
737	trace(icom_port, "RCV_COMPLETE", 0);	995	trace(icom_port, "RCV_COMPLETE", 0);
738	rcv_buff = icom_port->next_rcv;	996	rcv_buff = icom_port->next_rcv;
739		997
740	status = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].flags);	998	status = le16_to_cpu(icom_port->statStg->rcv[rcv_buff].flags);
741	while (status & SA_FL_RCV_DONE) {	999	while (status & SA_FL_RCV_DONE) {
742	int first = -1;	1000	int first = -1;
743		1001
744	trace(icom_port, "FID_STATUS", status);	1002	trace(icom_port, "FID_STATUS", status);
745	count = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].leLength);	1003	count = le16_to_cpu(icom_port->statStg->rcv[rcv_buff].leLength);
746		1004
747	trace(icom_port, "RCV_COUNT", count);	1005	trace(icom_port, "RCV_COUNT", count);
748		1006
749	trace(icom_port, "REAL_COUNT", count);	1007	trace(icom_port, "REAL_COUNT", count);
750		1008
751	offset =	1009	offset = le32_to_cpu(icom_port->statStg->rcv[rcv_buff].leBuffer) -
752	cpu_to_le32(icom_port->statStg->rcv[rcv_buff].leBuffer) -
753	icom_port->recv_buf_pci;	1010	icom_port->recv_buf_pci;
754		1011
755	/* Block copy all but the last byte as this may have status */	1012	/* Block copy all but the last byte as this may have status */
@@ -819,13 +1076,13 @@ ignore_char: · 63 unmodified lines
819	icom_port->statStg->rcv[rcv_buff].flags = 0;	1076	icom_port->statStg->rcv[rcv_buff].flags = 0;
820	icom_port->statStg->rcv[rcv_buff].leLength = 0;	1077	icom_port->statStg->rcv[rcv_buff].leLength = 0;
821	icom_port->statStg->rcv[rcv_buff].WorkingLength =	1078	icom_port->statStg->rcv[rcv_buff].WorkingLength =
822	(unsigned short int) cpu_to_le16(RCV_BUFF_SZ);	1079	cpu_to_le16(RCV_BUFF_SZ);
823		1080
824	rcv_buff++;	1081	rcv_buff++;
825	if (rcv_buff == NUM_RBUFFS)	1082	if (rcv_buff == NUM_RBUFFS)
826	rcv_buff = 0;	1083	rcv_buff = 0;
827		1084
828	status = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].flags);	1085	status = le16_to_cpu(icom_port->statStg->rcv[rcv_buff].flags);
829	}	1086	}
830	icom_port->next_rcv = rcv_buff;	1087	icom_port->next_rcv = rcv_buff;
831		1088
@@ -925,11 +1182,12 @@ static irqreturn_t icom_interrupt(int irq, void *dev_id) · 93 unmodified lines
925	*/	1182	*/
926	static unsigned int icom_tx_empty(struct uart_port *port)	1183	static unsigned int icom_tx_empty(struct uart_port *port)
927	{	1184	{
		1185	struct icom_port *icom_port = to_icom_port(port);
928	int ret;	1186	int ret;
929	unsigned long flags;	1187	unsigned long flags;
930		1188
931	spin_lock_irqsave(&port->lock, flags);	1189	spin_lock_irqsave(&port->lock, flags);
932	if (cpu_to_le16(ICOM_PORT->statStg->xmit[0].flags) &	1190	if (le16_to_cpu(icom_port->statStg->xmit[0].flags) &
933	SA_FLAGS_READY_TO_XMIT)	1191	SA_FLAGS_READY_TO_XMIT)
934	ret = TIOCSER_TEMT;	1192	ret = TIOCSER_TEMT;
935	else	1193	else
@@ -941,38 +1199,40 @@ static unsigned int icom_tx_empty(struct uart_port *port) · 5 unmodified lines
941		1199
942	static void icom_set_mctrl(struct uart_port *port, unsigned int mctrl)	1200	static void icom_set_mctrl(struct uart_port *port, unsigned int mctrl)
943	{	1201	{
		1202	struct icom_port *icom_port = to_icom_port(port);
944	unsigned char local_osr;	1203	unsigned char local_osr;
945		1204
946	trace(ICOM_PORT, "SET_MODEM", 0);	1205	trace(icom_port, "SET_MODEM", 0);
947	local_osr = readb(&ICOM_PORT->dram->osr);	1206	local_osr = readb(&icom_port->dram->osr);
948		1207
949	if (mctrl & TIOCM_RTS) {	1208	if (mctrl & TIOCM_RTS) {
950	trace(ICOM_PORT, "RAISE_RTS", 0);	1209	trace(icom_port, "RAISE_RTS", 0);
951	local_osr \|= ICOM_RTS;	1210	local_osr \|= ICOM_RTS;
952	} else {	1211	} else {
953	trace(ICOM_PORT, "LOWER_RTS", 0);	1212	trace(icom_port, "LOWER_RTS", 0);
954	local_osr &= ~ICOM_RTS;	1213	local_osr &= ~ICOM_RTS;
955	}	1214	}
956		1215
957	if (mctrl & TIOCM_DTR) {	1216	if (mctrl & TIOCM_DTR) {
958	trace(ICOM_PORT, "RAISE_DTR", 0);	1217	trace(icom_port, "RAISE_DTR", 0);
959	local_osr \|= ICOM_DTR;	1218	local_osr \|= ICOM_DTR;
960	} else {	1219	} else {
961	trace(ICOM_PORT, "LOWER_DTR", 0);	1220	trace(icom_port, "LOWER_DTR", 0);
962	local_osr &= ~ICOM_DTR;	1221	local_osr &= ~ICOM_DTR;
963	}	1222	}
964		1223
965	writeb(local_osr, &ICOM_PORT->dram->osr);	1224	writeb(local_osr, &icom_port->dram->osr);
966	}	1225	}
967		1226
968	static unsigned int icom_get_mctrl(struct uart_port *port)	1227	static unsigned int icom_get_mctrl(struct uart_port *port)
969	{	1228	{
		1229	struct icom_port *icom_port = to_icom_port(port);
970	unsigned char status;	1230	unsigned char status;
971	unsigned int result;	1231	unsigned int result;
972		1232
973	trace(ICOM_PORT, "GET_MODEM", 0);	1233	trace(icom_port, "GET_MODEM", 0);
974		1234
975	status = readb(&ICOM_PORT->dram->isr);	1235	status = readb(&icom_port->dram->isr);
976		1236
977	result = ((status & ICOM_DCD) ? TIOCM_CAR : 0)	1237	result = ((status & ICOM_DCD) ? TIOCM_CAR : 0)
978	\| ((status & ICOM_RI) ? TIOCM_RNG : 0)	1238	\| ((status & ICOM_RI) ? TIOCM_RNG : 0)
@@ -983,44 +1243,47 @@ static unsigned int icom_get_mctrl(struct uart_port *port) · 4 unmodified lines
983		1243
984	static void icom_stop_tx(struct uart_port *port)	1244	static void icom_stop_tx(struct uart_port *port)
985	{	1245	{
		1246	struct icom_port *icom_port = to_icom_port(port);
986	unsigned char cmdReg;	1247	unsigned char cmdReg;
987		1248
988	trace(ICOM_PORT, "STOP", 0);	1249	trace(icom_port, "STOP", 0);
989	cmdReg = readb(&ICOM_PORT->dram->CmdReg);	1250	cmdReg = readb(&icom_port->dram->CmdReg);
990	writeb(cmdReg \| CMD_HOLD_XMIT, &ICOM_PORT->dram->CmdReg);	1251	writeb(cmdReg \| CMD_HOLD_XMIT, &icom_port->dram->CmdReg);
991	}	1252	}
992		1253
993	static void icom_start_tx(struct uart_port *port)	1254	static void icom_start_tx(struct uart_port *port)
994	{	1255	{
		1256	struct icom_port *icom_port = to_icom_port(port);
995	unsigned char cmdReg;	1257	unsigned char cmdReg;
996		1258
997	trace(ICOM_PORT, "START", 0);	1259	trace(icom_port, "START", 0);
998	cmdReg = readb(&ICOM_PORT->dram->CmdReg);	1260	cmdReg = readb(&icom_port->dram->CmdReg);
999	if ((cmdReg & CMD_HOLD_XMIT) == CMD_HOLD_XMIT)	1261	if ((cmdReg & CMD_HOLD_XMIT) == CMD_HOLD_XMIT)
1000	writeb(cmdReg & ~CMD_HOLD_XMIT,	1262	writeb(cmdReg & ~CMD_HOLD_XMIT,
1001	&ICOM_PORT->dram->CmdReg);	1263	&icom_port->dram->CmdReg);
1002		1264
1003	icom_write(port);	1265	icom_write(port);
1004	}	1266	}
1005		1267
1006	static void icom_send_xchar(struct uart_port *port, char ch)	1268	static void icom_send_xchar(struct uart_port *port, char ch)
1007	{	1269	{
		1270	struct icom_port *icom_port = to_icom_port(port);
1008	unsigned char xdata;	1271	unsigned char xdata;
1009	int index;	1272	int index;
1010	unsigned long flags;	1273	unsigned long flags;
1011		1274
1012	trace(ICOM_PORT, "SEND_XCHAR", ch);	1275	trace(icom_port, "SEND_XCHAR", ch);
1013		1276
1014	/* wait .1 sec to send char */	1277	/* wait .1 sec to send char */
1015	for (index = 0; index < 10; index++) {	1278	for (index = 0; index < 10; index++) {
1016	spin_lock_irqsave(&port->lock, flags);	1279	spin_lock_irqsave(&port->lock, flags);
1017	xdata = readb(&ICOM_PORT->dram->xchar);	1280	xdata = readb(&icom_port->dram->xchar);
1018	if (xdata == 0x00) {	1281	if (xdata == 0x00) {
1019	trace(ICOM_PORT, "QUICK_WRITE", 0);	1282	trace(icom_port, "QUICK_WRITE", 0);
1020	writeb(ch, &ICOM_PORT->dram->xchar);	1283	writeb(ch, &icom_port->dram->xchar);
1021		1284
1022	/* flush write operation */	1285	/* flush write operation */
1023	xdata = readb(&ICOM_PORT->dram->xchar);	1286	xdata = readb(&icom_port->dram->xchar);
1024	spin_unlock_irqrestore(&port->lock, flags);	1287	spin_unlock_irqrestore(&port->lock, flags);
1025	break;	1288	break;
1026	}	1289	}
@@ -1031,38 +1294,41 @@ static void icom_send_xchar(struct uart_port *port, char ch) · 4 unmodified lines
1031		1294
1032	static void icom_stop_rx(struct uart_port *port)	1295	static void icom_stop_rx(struct uart_port *port)
1033	{	1296	{
		1297	struct icom_port *icom_port = to_icom_port(port);
1034	unsigned char cmdReg;	1298	unsigned char cmdReg;
1035		1299
1036	cmdReg = readb(&ICOM_PORT->dram->CmdReg);	1300	cmdReg = readb(&icom_port->dram->CmdReg);
1037	writeb(cmdReg & ~CMD_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);	1301	writeb(cmdReg & ~CMD_RCV_ENABLE, &icom_port->dram->CmdReg);
1038	}	1302	}
1039		1303
1040	static void icom_break(struct uart_port *port, int break_state)	1304	static void icom_break(struct uart_port *port, int break_state)
1041	{	1305	{
		1306	struct icom_port *icom_port = to_icom_port(port);
1042	unsigned char cmdReg;	1307	unsigned char cmdReg;
1043	unsigned long flags;	1308	unsigned long flags;
1044		1309
1045	spin_lock_irqsave(&port->lock, flags);	1310	spin_lock_irqsave(&port->lock, flags);
1046	trace(ICOM_PORT, "BREAK", 0);	1311	trace(icom_port, "BREAK", 0);
1047	cmdReg = readb(&ICOM_PORT->dram->CmdReg);	1312	cmdReg = readb(&icom_port->dram->CmdReg);
1048	if (break_state == -1) {	1313	if (break_state == -1) {
1049	writeb(cmdReg \| CMD_SND_BREAK, &ICOM_PORT->dram->CmdReg);	1314	writeb(cmdReg \| CMD_SND_BREAK, &icom_port->dram->CmdReg);
1050	} else {	1315	} else {
1051	writeb(cmdReg & ~CMD_SND_BREAK, &ICOM_PORT->dram->CmdReg);	1316	writeb(cmdReg & ~CMD_SND_BREAK, &icom_port->dram->CmdReg);
1052	}	1317	}
1053	spin_unlock_irqrestore(&port->lock, flags);	1318	spin_unlock_irqrestore(&port->lock, flags);
1054	}	1319	}
1055		1320
1056	static int icom_open(struct uart_port *port)	1321	static int icom_open(struct uart_port *port)
1057	{	1322	{
		1323	struct icom_port *icom_port = to_icom_port(port);
1058	int retval;	1324	int retval;
1059		1325
1060	kref_get(&ICOM_PORT->adapter->kref);	1326	kref_get(&icom_port->adapter->kref);
1061	retval = startup(ICOM_PORT);	1327	retval = startup(icom_port);
1062		1328
1063	if (retval) {	1329	if (retval) {
1064	kref_put(&ICOM_PORT->adapter->kref, icom_kref_release);	1330	kref_put(&icom_port->adapter->kref, icom_kref_release);
1065	trace(ICOM_PORT, "STARTUP_ERROR", 0);	1331	trace(icom_port, "STARTUP_ERROR", 0);
1066	return retval;	1332	return retval;
1067	}	1333	}
1068		1334
@@ -1071,23 +1337,25 @@ static int icom_open(struct uart_port *port) · 2 unmodified lines
1071		1337
1072	static void icom_close(struct uart_port *port)	1338	static void icom_close(struct uart_port *port)
1073	{	1339	{
		1340	struct icom_port *icom_port = to_icom_port(port);
1074	unsigned char cmdReg;	1341	unsigned char cmdReg;
1075		1342
1076	trace(ICOM_PORT, "CLOSE", 0);	1343	trace(icom_port, "CLOSE", 0);
1077		1344
1078	/* stop receiver */	1345	/* stop receiver */
1079	cmdReg = readb(&ICOM_PORT->dram->CmdReg);	1346	cmdReg = readb(&icom_port->dram->CmdReg);
1080	writeb(cmdReg & ~CMD_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);	1347	writeb(cmdReg & ~CMD_RCV_ENABLE, &icom_port->dram->CmdReg);
1081		1348
1082	shutdown(ICOM_PORT);	1349	shutdown(icom_port);
1083		1350
1084	kref_put(&ICOM_PORT->adapter->kref, icom_kref_release);	1351	kref_put(&icom_port->adapter->kref, icom_kref_release);
1085	}	1352	}
1086		1353
1087	static void icom_set_termios(struct uart_port *port,	1354	static void icom_set_termios(struct uart_port *port,
1088	struct ktermios *termios,	1355	struct ktermios *termios,
1089	struct ktermios *old_termios)	1356	struct ktermios *old_termios)
1090	{	1357	{
		1358	struct icom_port *icom_port = to_icom_port(port);
1091	int baud;	1359	int baud;
1092	unsigned cflag, iflag;	1360	unsigned cflag, iflag;
1093	char new_config2;	1361	char new_config2;
@@ -1099,7 +1367,7 @@ static void icom_set_termios(struct uart_port *port, · 5 unmodified lines
1099	unsigned long flags;	1367	unsigned long flags;
1100		1368
1101	spin_lock_irqsave(&port->lock, flags);	1369	spin_lock_irqsave(&port->lock, flags);
1102	trace(ICOM_PORT, "CHANGE_SPEED", 0);	1370	trace(icom_port, "CHANGE_SPEED", 0);
1103		1371
1104	cflag = termios->c_cflag;	1372	cflag = termios->c_cflag;
1105	iflag = termios->c_iflag;	1373	iflag = termios->c_iflag;
@@ -1130,12 +1398,12 @@ static void icom_set_termios(struct uart_port *port, · 24 unmodified lines
1130	if (cflag & PARENB) {	1398	if (cflag & PARENB) {
1131	/* parity bit enabled */	1399	/* parity bit enabled */
1132	new_config2 \|= ICOM_ACFG_PARITY_ENAB;	1400	new_config2 \|= ICOM_ACFG_PARITY_ENAB;
1133	trace(ICOM_PORT, "PARENB", 0);	1401	trace(icom_port, "PARENB", 0);
1134	}	1402	}
1135	if (cflag & PARODD) {	1403	if (cflag & PARODD) {
1136	/* odd parity */	1404	/* odd parity */
1137	new_config2 \|= ICOM_ACFG_PARITY_ODD;	1405	new_config2 \|= ICOM_ACFG_PARITY_ODD;
1138	trace(ICOM_PORT, "PARODD", 0);	1406	trace(icom_port, "PARODD", 0);
1139	}	1407	}
1140		1408
1141	/* Determine divisor based on baud rate */	1409	/* Determine divisor based on baud rate */
@@ -1155,100 +1423,99 @@ static void icom_set_termios(struct uart_port *port, · 13 unmodified lines
1155	uart_update_timeout(port, cflag, baud);	1423	uart_update_timeout(port, cflag, baud);
1156		1424
1157	/* CTS flow control flag and modem status interrupts */	1425	/* CTS flow control flag and modem status interrupts */
1158	tmp_byte = readb(&(ICOM_PORT->dram->HDLCConfigReg));	1426	tmp_byte = readb(&(icom_port->dram->HDLCConfigReg));
1159	if (cflag & CRTSCTS)	1427	if (cflag & CRTSCTS)
1160	tmp_byte \|= HDLC_HDW_FLOW;	1428	tmp_byte \|= HDLC_HDW_FLOW;
1161	else	1429	else
1162	tmp_byte &= ~HDLC_HDW_FLOW;	1430	tmp_byte &= ~HDLC_HDW_FLOW;
1163	writeb(tmp_byte, &(ICOM_PORT->dram->HDLCConfigReg));	1431	writeb(tmp_byte, &(icom_port->dram->HDLCConfigReg));
1164		1432
1165	/*	1433	/*
1166	* Set up parity check flag	1434	* Set up parity check flag
1167	*/	1435	*/
1168	ICOM_PORT->read_status_mask = SA_FLAGS_OVERRUN \| SA_FL_RCV_DONE;	1436	icom_port->read_status_mask = SA_FLAGS_OVERRUN \| SA_FL_RCV_DONE;
1169	if (iflag & INPCK)	1437	if (iflag & INPCK)
1170	ICOM_PORT->read_status_mask \|=	1438	icom_port->read_status_mask \|=
1171	SA_FLAGS_FRAME_ERROR \| SA_FLAGS_PARITY_ERROR;	1439	SA_FLAGS_FRAME_ERROR \| SA_FLAGS_PARITY_ERROR;
1172		1440
1173	if ((iflag & BRKINT) \|\| (iflag & PARMRK))	1441	if ((iflag & BRKINT) \|\| (iflag & PARMRK))
1174	ICOM_PORT->read_status_mask \|= SA_FLAGS_BREAK_DET;	1442	icom_port->read_status_mask \|= SA_FLAGS_BREAK_DET;
1175		1443
1176	/*	1444	/*
1177	* Characters to ignore	1445	* Characters to ignore
1178	*/	1446	*/
1179	ICOM_PORT->ignore_status_mask = 0;	1447	icom_port->ignore_status_mask = 0;
1180	if (iflag & IGNPAR)	1448	if (iflag & IGNPAR)
1181	ICOM_PORT->ignore_status_mask \|=	1449	icom_port->ignore_status_mask \|=
1182	SA_FLAGS_PARITY_ERROR \| SA_FLAGS_FRAME_ERROR;	1450	SA_FLAGS_PARITY_ERROR \| SA_FLAGS_FRAME_ERROR;
1183	if (iflag & IGNBRK) {	1451	if (iflag & IGNBRK) {
1184	ICOM_PORT->ignore_status_mask \|= SA_FLAGS_BREAK_DET;	1452	icom_port->ignore_status_mask \|= SA_FLAGS_BREAK_DET;
1185	/*	1453	/*
1186	* If we're ignore parity and break indicators, ignore	1454	* If we're ignore parity and break indicators, ignore
1187	* overruns too. (For real raw support).	1455	* overruns too. (For real raw support).
1188	*/	1456	*/
1189	if (iflag & IGNPAR)	1457	if (iflag & IGNPAR)
1190	ICOM_PORT->ignore_status_mask \|= SA_FLAGS_OVERRUN;	1458	icom_port->ignore_status_mask \|= SA_FLAGS_OVERRUN;
1191	}	1459	}
1192		1460
1193	/*	1461	/*
1194	* !!! ignore all characters if CREAD is not set	1462	* !!! ignore all characters if CREAD is not set
1195	*/	1463	*/
1196	if ((cflag & CREAD) == 0)	1464	if ((cflag & CREAD) == 0)
1197	ICOM_PORT->ignore_status_mask \|= SA_FL_RCV_DONE;	1465	icom_port->ignore_status_mask \|= SA_FL_RCV_DONE;
1198		1466
1199	/* Turn off Receiver to prepare for reset */	1467	/* Turn off Receiver to prepare for reset */
1200	writeb(CMD_RCV_DISABLE, &ICOM_PORT->dram->CmdReg);	1468	writeb(CMD_RCV_DISABLE, &icom_port->dram->CmdReg);
1201		1469
1202	for (index = 0; index < 10; index++) {	1470	for (index = 0; index < 10; index++) {
1203	if (readb(&ICOM_PORT->dram->PrevCmdReg) == 0x00) {	1471	if (readb(&icom_port->dram->PrevCmdReg) == 0x00) {
1204	break;	1472	break;
1205	}	1473	}
1206	}	1474	}
1207		1475
1208	/* clear all current buffers of data */	1476	/* clear all current buffers of data */
1209	for (rcv_buff = 0; rcv_buff < NUM_RBUFFS; rcv_buff++) {	1477	for (rcv_buff = 0; rcv_buff < NUM_RBUFFS; rcv_buff++) {
1210	ICOM_PORT->statStg->rcv[rcv_buff].flags = 0;	1478	icom_port->statStg->rcv[rcv_buff].flags = 0;
1211	ICOM_PORT->statStg->rcv[rcv_buff].leLength = 0;	1479	icom_port->statStg->rcv[rcv_buff].leLength = 0;
1212	ICOM_PORT->statStg->rcv[rcv_buff].WorkingLength =	1480	icom_port->statStg->rcv[rcv_buff].WorkingLength =
1213	(unsigned short int) cpu_to_le16(RCV_BUFF_SZ);	1481	cpu_to_le16(RCV_BUFF_SZ);
1214	}	1482	}
1215		1483
1216	for (xmit_buff = 0; xmit_buff < NUM_XBUFFS; xmit_buff++) {	1484	for (xmit_buff = 0; xmit_buff < NUM_XBUFFS; xmit_buff++) {
1217	ICOM_PORT->statStg->xmit[xmit_buff].flags = 0;	1485	icom_port->statStg->xmit[xmit_buff].flags = 0;
1218	}	1486	}
1219		1487
1220	/* activate changes and start xmit and receiver here */	1488	/* activate changes and start xmit and receiver here */
1221	/* Enable the receiver */	1489	/* Enable the receiver */
1222	writeb(new_config3, &(ICOM_PORT->dram->async_config3));	1490	writeb(new_config3, &(icom_port->dram->async_config3));
1223	writeb(new_config2, &(ICOM_PORT->dram->async_config2));	1491	writeb(new_config2, &(icom_port->dram->async_config2));
1224	tmp_byte = readb(&(ICOM_PORT->dram->HDLCConfigReg));	1492	tmp_byte = readb(&(icom_port->dram->HDLCConfigReg));
1225	tmp_byte \|= HDLC_PPP_PURE_ASYNC \| HDLC_FF_FILL;	1493	tmp_byte \|= HDLC_PPP_PURE_ASYNC \| HDLC_FF_FILL;
1226	writeb(tmp_byte, &(ICOM_PORT->dram->HDLCConfigReg));	1494	writeb(tmp_byte, &(icom_port->dram->HDLCConfigReg));
1227	writeb(0x04, &(ICOM_PORT->dram->FlagFillIdleTimer)); /* 0.5 seconds */	1495	writeb(0x04, &(icom_port->dram->FlagFillIdleTimer)); /* 0.5 seconds */
1228	writeb(0xFF, &(ICOM_PORT->dram->ier)); /* enable modem signal interrupts */	1496	writeb(0xFF, &(icom_port->dram->ier)); /* enable modem signal interrupts */
1229		1497
1230	/* reset processor */	1498	/* reset processor */
1231	writeb(CMD_RESTART, &ICOM_PORT->dram->CmdReg);	1499	writeb(CMD_RESTART, &icom_port->dram->CmdReg);
1232		1500
1233	for (index = 0; index < 10; index++) {	1501	for (index = 0; index < 10; index++) {
1234	if (readb(&ICOM_PORT->dram->CmdReg) == 0x00) {	1502	if (readb(&icom_port->dram->CmdReg) == 0x00) {
1235	break;	1503	break;
1236	}	1504	}
1237	}	1505	}
1238		1506
1239	/* Enable Transmitter and Receiver */	1507	/* Enable Transmitter and Receiver */
1240	offset =	1508	offset =
1241	(unsigned long) &ICOM_PORT->statStg->rcv[0] -	1509	(unsigned long) &icom_port->statStg->rcv[0] -
1242	(unsigned long) ICOM_PORT->statStg;	1510	(unsigned long) icom_port->statStg;
1243	writel(ICOM_PORT->statStg_pci + offset,	1511	writel(icom_port->statStg_pci + offset,
1244	&ICOM_PORT->dram->RcvStatusAddr);	1512	&icom_port->dram->RcvStatusAddr);
1245	ICOM_PORT->next_rcv = 0;	1513	icom_port->next_rcv = 0;
1246	ICOM_PORT->put_length = 0;	1514	*icom_port->xmitRestart = 0;
1247	*ICOM_PORT->xmitRestart = 0;	1515	writel(icom_port->xmitRestart_pci,
1248	writel(ICOM_PORT->xmitRestart_pci,	1516	&icom_port->dram->XmitStatusAddr);
1249	&ICOM_PORT->dram->XmitStatusAddr);	1517	trace(icom_port, "XR_ENAB", 0);
1250	trace(ICOM_PORT, "XR_ENAB", 0);	1518	writeb(CMD_XMIT_RCV_ENABLE, &icom_port->dram->CmdReg);
1251	writeb(CMD_XMIT_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);
1252		1519
1253	spin_unlock_irqrestore(&port->lock, flags);	1520	spin_unlock_irqrestore(&port->lock, flags);
1254	}	1521	}
@@ -1258,15 +1525,6 @@ static const char icom_type(struct uart_port port) · 3 unmodified lines
1258	return "icom";	1525	return "icom";
1259	}	1526	}
1260		1527
1261	static void icom_release_port(struct uart_port *port)
1262	{
1263	}
1264
1265	static int icom_request_port(struct uart_port *port)
1266	{
1267	return 0;
1268	}
1269
1270	static void icom_config_port(struct uart_port *port, int flags)	1528	static void icom_config_port(struct uart_port *port, int flags)
1271	{	1529	{
1272	port->type = PORT_ICOM;	1530	port->type = PORT_ICOM;
@@ -1285,8 +1543,6 @@ static const struct uart_ops icom_ops = { · 12 unmodified lines
1285	.shutdown = icom_close,	1543	.shutdown = icom_close,
1286	.set_termios = icom_set_termios,	1544	.set_termios = icom_set_termios,
1287	.type = icom_type,	1545	.type = icom_type,
1288	.release_port = icom_release_port,
1289	.request_port = icom_request_port,
1290	.config_port = icom_config_port,	1546	.config_port = icom_config_port,
1291	};	1547	};
1292		1548
@@ -1315,7 +1571,6 @@ static int icom_init_ports(struct icom_adapter *icom_adapter) · 22 unmodified lines
1315	icom_port = &icom_adapter->port_info[i];	1571	icom_port = &icom_adapter->port_info[i];
1316	icom_port->port = i;	1572	icom_port->port = i;
1317	icom_port->status = ICOM_PORT_ACTIVE;	1573	icom_port->status = ICOM_PORT_ACTIVE;
1318	icom_port->imbed_modem = ICOM_UNKNOWN;
1319	}	1574	}
1320	} else {	1575	} else {
1321	if (subsystem_id == PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL) {	1576	if (subsystem_id == PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL) {
@@ -1326,26 +1581,15 @@ static int icom_init_ports(struct icom_adapter *icom_adapter) · 4 unmodified lines
1326		1581
1327	icom_port->port = i;	1582	icom_port->port = i;
1328	icom_port->status = ICOM_PORT_ACTIVE;	1583	icom_port->status = ICOM_PORT_ACTIVE;
1329	icom_port->imbed_modem = ICOM_IMBED_MODEM;
1330	}	1584	}
1331	} else {	1585	} else {
1332	icom_adapter->numb_ports = 4;	1586	icom_adapter->numb_ports = 4;
1333		1587
1334	icom_adapter->port_info[0].port = 0;	1588	icom_adapter->port_info[0].port = 0;
1335	icom_adapter->port_info[0].status = ICOM_PORT_ACTIVE;	1589	icom_adapter->port_info[0].status = ICOM_PORT_ACTIVE;
1336
1337	if (subsystem_id ==
1338	PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM) {
1339	icom_adapter->port_info[0].imbed_modem = ICOM_IMBED_MODEM;
1340	} else {
1341	icom_adapter->port_info[0].imbed_modem = ICOM_RVX;
1342	}
1343
1344	icom_adapter->port_info[1].status = ICOM_PORT_OFF;	1590	icom_adapter->port_info[1].status = ICOM_PORT_OFF;
1345
1346	icom_adapter->port_info[2].port = 2;	1591	icom_adapter->port_info[2].port = 2;
1347	icom_adapter->port_info[2].status = ICOM_PORT_ACTIVE;	1592	icom_adapter->port_info[2].status = ICOM_PORT_ACTIVE;
1348	icom_adapter->port_info[2].imbed_modem = ICOM_RVX;
1349	icom_adapter->port_info[3].status = ICOM_PORT_OFF;	1593	icom_adapter->port_info[3].status = ICOM_PORT_OFF;
1350	}	1594	}
1351	}	1595	}
@@ -1401,7 +1645,6 @@ static int icom_alloc_adapter(struct icom_adapter · 49 unmodified lines
1401	int adapter_count = 0;	1645	int adapter_count = 0;
1402	struct icom_adapter *icom_adapter;	1646	struct icom_adapter *icom_adapter;
1403	struct icom_adapter *cur_adapter_entry;	1647	struct icom_adapter *cur_adapter_entry;
1404	struct list_head *tmp;
1405		1648
1406	icom_adapter = kzalloc(sizeof(struct icom_adapter), GFP_KERNEL);	1649	icom_adapter = kzalloc(sizeof(struct icom_adapter), GFP_KERNEL);
1407		1650
@@ -1409,10 +1652,8 @@ static int icom_alloc_adapter(struct icom_adapter · 1 unmodified line
1409	return -ENOMEM;	1652	return -ENOMEM;
1410	}	1653	}
1411		1654
1412	list_for_each(tmp, &icom_adapter_head) {	1655	list_for_each_entry(cur_adapter_entry, &icom_adapter_head,
1413	cur_adapter_entry =	1656	icom_adapter_entry) {
1414	list_entry(tmp, struct icom_adapter,
1415	icom_adapter_entry);
1416	if (cur_adapter_entry->index != adapter_count) {	1657	if (cur_adapter_entry->index != adapter_count) {
1417	break;	1658	break;
1418	}	1659	}
@@ -1420,7 +1661,8 @@ static int icom_alloc_adapter(struct icom_adapter · 1 unmodified line
1420	}	1661	}
1421		1662
1422	icom_adapter->index = adapter_count;	1663	icom_adapter->index = adapter_count;
1423	list_add_tail(&icom_adapter->icom_adapter_entry, tmp);	1664	list_add_tail(&icom_adapter->icom_adapter_entry,
		1665	&cur_adapter_entry->icom_adapter_entry);
1424		1666
1425	*icom_adapter_ref = icom_adapter;	1667	*icom_adapter_ref = icom_adapter;
1426	return 0;	1668	return 0;
@@ -1432,8 +1674,10 @@ static void icom_free_adapter(struct icom_adapter *icom_adapter) · 5 unmodified lines
1432	kfree(icom_adapter);	1674	kfree(icom_adapter);
1433	}	1675	}
1434		1676
1435	static void icom_remove_adapter(struct icom_adapter *icom_adapter)	1677	static void icom_kref_release(struct kref *kref)
1436	{	1678	{
		1679	struct icom_adapter *icom_adapter = container_of(kref,
		1680	struct icom_adapter, kref);
1437	struct icom_port *icom_port;	1681	struct icom_port *icom_port;
1438	int index;	1682	int index;
1439		1683
@@ -1466,14 +1710,6 @@ static void icom_remove_adapter(struct icom_adapter *icom_adapter) · 26 unmodified lines
1466	icom_free_adapter(icom_adapter);	1710	icom_free_adapter(icom_adapter);
1467	}	1711	}
1468		1712
1469	static void icom_kref_release(struct kref *kref)
1470	{
1471	struct icom_adapter *icom_adapter;
1472
1473	icom_adapter = to_icom_adapter(kref);
1474	icom_remove_adapter(icom_adapter);
1475	}
1476
1477	static int icom_probe(struct pci_dev *dev,	1713	static int icom_probe(struct pci_dev *dev,
1478	const struct pci_device_id *ent)	1714	const struct pci_device_id *ent)
1479	{	1715	{
@@ -1501,7 +1737,7 @@ static int icom_probe(struct pci_dev *dev, · 21 unmodified lines
1501	retval = pci_read_config_dword(dev, PCI_COMMAND, &command_reg);	1737	retval = pci_read_config_dword(dev, PCI_COMMAND, &command_reg);
1502	if (retval) {	1738	if (retval) {
1503	dev_err(&dev->dev, "PCI Config read FAILED\n");	1739	dev_err(&dev->dev, "PCI Config read FAILED\n");
1504	return retval;	1740	goto probe_exit0;
1505	}	1741	}
1506		1742
1507	pci_write_config_dword(dev, PCI_COMMAND,	1743	pci_write_config_dword(dev, PCI_COMMAND,
@@ -1589,11 +1825,9 @@ probe_exit0: · 81 unmodified lines
1589	static void icom_remove(struct pci_dev *dev)	1825	static void icom_remove(struct pci_dev *dev)
1590	{	1826	{
1591	struct icom_adapter *icom_adapter;	1827	struct icom_adapter *icom_adapter;
1592	struct list_head *tmp;
1593		1828
1594	list_for_each(tmp, &icom_adapter_head) {	1829	list_for_each_entry(icom_adapter, &icom_adapter_head,
1595	icom_adapter = list_entry(tmp, struct icom_adapter,	1830	icom_adapter_entry) {
1596	icom_adapter_entry);
1597	if (icom_adapter->pci_dev == dev) {	1831	if (icom_adapter->pci_dev == dev) {
1598	kref_put(&icom_adapter->kref, icom_kref_release);	1832	kref_put(&icom_adapter->kref, icom_kref_release);
1599	return;	1833	return;

drivers/tty/serial/icom.h+0−274

@@ -1,274 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0+ */
2	/*
3	* icom.h
4	*
5	* Copyright (C) 2001 Michael Anderson, IBM Corporation
6	*
7	* Serial device driver include file.
8	*/
9
10	#include <linux/serial_core.h>
11
12	#define BAUD_TABLE_LIMIT ((sizeof(icom_acfg_baud)/sizeof(int)) - 1)
13	static int icom_acfg_baud[] = {
14	300,
15	600,
16	900,
17	1200,
18	1800,
19	2400,
20	3600,
21	4800,
22	7200,
23	9600,
24	14400,
25	19200,
26	28800,
27	38400,
28	57600,
29	76800,
30	115200,
31	153600,
32	230400,
33	307200,
34	460800,
35	};
36
37	struct icom_regs {
38	u32 control; /* Adapter Control Register */
39	u32 interrupt; /* Adapter Interrupt Register */
40	u32 int_mask; /* Adapter Interrupt Mask Reg */
41	u32 int_pri; /* Adapter Interrupt Priority r */
42	u32 int_reg_b; /* Adapter non-masked Interrupt */
43	u32 resvd01;
44	u32 resvd02;
45	u32 resvd03;
46	u32 control_2; /* Adapter Control Register 2 */
47	u32 interrupt_2; /* Adapter Interrupt Register 2 */
48	u32 int_mask_2; /* Adapter Interrupt Mask 2 */
49	u32 int_pri_2; /* Adapter Interrupt Prior 2 */
50	u32 int_reg_2b; /* Adapter non-masked 2 */
51	};
52
53	struct func_dram {
54	u32 reserved[108]; /* 0-1B0 reserved by personality code */
55	u32 RcvStatusAddr; /* 1B0-1B3 Status Address for Next rcv */
56	u8 RcvStnAddr; /* 1B4 Receive Station Addr */
57	u8 IdleState; /* 1B5 Idle State */
58	u8 IdleMonitor; /* 1B6 Idle Monitor */
59	u8 FlagFillIdleTimer; /* 1B7 Flag Fill Idle Timer */
60	u32 XmitStatusAddr; /* 1B8-1BB Transmit Status Address */
61	u8 StartXmitCmd; /* 1BC Start Xmit Command */
62	u8 HDLCConfigReg; /* 1BD Reserved */
63	u8 CauseCode; /* 1BE Cause code for fatal error */
64	u8 xchar; /* 1BF High priority send */
65	u32 reserved3; /* 1C0-1C3 Reserved */
66	u8 PrevCmdReg; /* 1C4 Reserved */
67	u8 CmdReg; /* 1C5 Command Register */
68	u8 async_config2; /* 1C6 Async Config Byte 2 */
69	u8 async_config3; /* 1C7 Async Config Byte 3 */
70	u8 dce_resvd[20]; /* 1C8-1DB DCE Rsvd */
71	u8 dce_resvd21; /* 1DC DCE Rsvd (21st byte */
72	u8 misc_flags; /* 1DD misc flags */
73	#define V2_HARDWARE 0x40
74	#define ICOM_HDW_ACTIVE 0x01
75	u8 call_length; /* 1DE Phone #/CFI buff ln */
76	u8 call_length2; /* 1DF Upper byte (unused) */
77	u32 call_addr; /* 1E0-1E3 Phn #/CFI buff addr */
78	u16 timer_value; /* 1E4-1E5 general timer value */
79	u8 timer_command; /* 1E6 general timer cmd */
80	u8 dce_command; /* 1E7 dce command reg */
81	u8 dce_cmd_status; /* 1E8 dce command stat */
82	u8 x21_r1_ioff; /* 1E9 dce ready counter */
83	u8 x21_r0_ioff; /* 1EA dce not ready ctr */
84	u8 x21_ralt_ioff; /* 1EB dce CNR counter */
85	u8 x21_r1_ion; /* 1EC dce ready I on ctr */
86	u8 rsvd_ier; /* 1ED Rsvd for IER (if ne */
87	u8 ier; /* 1EE Interrupt Enable */
88	u8 isr; /* 1EF Input Signal Reg */
89	u8 osr; /* 1F0 Output Signal Reg */
90	u8 reset; /* 1F1 Reset/Reload Reg */
91	u8 disable; /* 1F2 Disable Reg */
92	u8 sync; /* 1F3 Sync Reg */
93	u8 error_stat; /* 1F4 Error Status */
94	u8 cable_id; /* 1F5 Cable ID */
95	u8 cs_length; /* 1F6 CS Load Length */
96	u8 mac_length; /* 1F7 Mac Load Length */
97	u32 cs_load_addr; /* 1F8-1FB Call Load PCI Addr */
98	u32 mac_load_addr; /* 1FC-1FF Mac Load PCI Addr */
99	};
100
101	/*
102	* adapter defines and structures
103	*/
104	#define ICOM_CONTROL_START_A 0x00000008
105	#define ICOM_CONTROL_STOP_A 0x00000004
106	#define ICOM_CONTROL_START_B 0x00000002
107	#define ICOM_CONTROL_STOP_B 0x00000001
108	#define ICOM_CONTROL_START_C 0x00000008
109	#define ICOM_CONTROL_STOP_C 0x00000004
110	#define ICOM_CONTROL_START_D 0x00000002
111	#define ICOM_CONTROL_STOP_D 0x00000001
112	#define ICOM_IRAM_OFFSET 0x1000
113	#define ICOM_IRAM_SIZE 0x0C00
114	#define ICOM_DCE_IRAM_OFFSET 0x0A00
115	#define ICOM_CABLE_ID_VALID 0x01
116	#define ICOM_CABLE_ID_MASK 0xF0
117	#define ICOM_DISABLE 0x80
118	#define CMD_XMIT_RCV_ENABLE 0xC0
119	#define CMD_XMIT_ENABLE 0x40
120	#define CMD_RCV_DISABLE 0x00
121	#define CMD_RCV_ENABLE 0x80
122	#define CMD_RESTART 0x01
123	#define CMD_HOLD_XMIT 0x02
124	#define CMD_SND_BREAK 0x04
125	#define RS232_CABLE 0x06
126	#define V24_CABLE 0x0E
127	#define V35_CABLE 0x0C
128	#define V36_CABLE 0x02
129	#define NO_CABLE 0x00
130	#define START_DOWNLOAD 0x80
131	#define ICOM_INT_MASK_PRC_A 0x00003FFF
132	#define ICOM_INT_MASK_PRC_B 0x3FFF0000
133	#define ICOM_INT_MASK_PRC_C 0x00003FFF
134	#define ICOM_INT_MASK_PRC_D 0x3FFF0000
135	#define INT_RCV_COMPLETED 0x1000
136	#define INT_XMIT_COMPLETED 0x2000
137	#define INT_IDLE_DETECT 0x0800
138	#define INT_RCV_DISABLED 0x0400
139	#define INT_XMIT_DISABLED 0x0200
140	#define INT_RCV_XMIT_SHUTDOWN 0x0100
141	#define INT_FATAL_ERROR 0x0080
142	#define INT_CABLE_PULL 0x0020
143	#define INT_SIGNAL_CHANGE 0x0010
144	#define HDLC_PPP_PURE_ASYNC 0x02
145	#define HDLC_FF_FILL 0x00
146	#define HDLC_HDW_FLOW 0x01
147	#define START_XMIT 0x80
148	#define ICOM_ACFG_DRIVE1 0x20
149	#define ICOM_ACFG_NO_PARITY 0x00
150	#define ICOM_ACFG_PARITY_ENAB 0x02
151	#define ICOM_ACFG_PARITY_ODD 0x01
152	#define ICOM_ACFG_8BPC 0x00
153	#define ICOM_ACFG_7BPC 0x04
154	#define ICOM_ACFG_6BPC 0x08
155	#define ICOM_ACFG_5BPC 0x0C
156	#define ICOM_ACFG_1STOP_BIT 0x00
157	#define ICOM_ACFG_2STOP_BIT 0x10
158	#define ICOM_DTR 0x80
159	#define ICOM_RTS 0x40
160	#define ICOM_RI 0x08
161	#define ICOM_DSR 0x80
162	#define ICOM_DCD 0x20
163	#define ICOM_CTS 0x40
164
165	#define NUM_XBUFFS 1
166	#define NUM_RBUFFS 2
167	#define RCV_BUFF_SZ 0x0200
168	#define XMIT_BUFF_SZ 0x1000
169	struct statusArea {
170	/**********************************************/
171	/* Transmit Status Area */
172	/**********************************************/
173	struct xmit_status_area{
174	u32 leNext; /* Next entry in Little Endian on Adapter */
175	u32 leNextASD;
176	u32 leBuffer; /* Buffer for entry in LE for Adapter */
177	u16 leLengthASD;
178	u16 leOffsetASD;
179	u16 leLength; /* Length of data in segment */
180	u16 flags;
181	#define SA_FLAGS_DONE 0x0080 /* Done with Segment */
182	#define SA_FLAGS_CONTINUED 0x8000 /* More Segments */
183	#define SA_FLAGS_IDLE 0x4000 /* Mark IDLE after frm */
184	#define SA_FLAGS_READY_TO_XMIT 0x0800
185	#define SA_FLAGS_STAT_MASK 0x007F
186	} xmit[NUM_XBUFFS];
187
188	/**********************************************/
189	/* Receive Status Area */
190	/**********************************************/
191	struct {
192	u32 leNext; /* Next entry in Little Endian on Adapter */
193	u32 leNextASD;
194	u32 leBuffer; /* Buffer for entry in LE for Adapter */
195	u16 WorkingLength; /* size of segment */
196	u16 reserv01;
197	u16 leLength; /* Length of data in segment */
198	u16 flags;
199	#define SA_FL_RCV_DONE 0x0010 /* Data ready */
200	#define SA_FLAGS_OVERRUN 0x0040
201	#define SA_FLAGS_PARITY_ERROR 0x0080
202	#define SA_FLAGS_FRAME_ERROR 0x0001
203	#define SA_FLAGS_FRAME_TRUNC 0x0002
204	#define SA_FLAGS_BREAK_DET 0x0004 /* set conditionally by device driver, not hardware */
205	#define SA_FLAGS_RCV_MASK 0xFFE6
206	} rcv[NUM_RBUFFS];
207	};
208
209	struct icom_adapter;
210
211
212	#define ICOM_MAJOR 243
213	#define ICOM_MINOR_START 0
214
215	struct icom_port {
216	struct uart_port uart_port;
217	u8 imbed_modem;
218	#define ICOM_UNKNOWN 1
219	#define ICOM_RVX 2
220	#define ICOM_IMBED_MODEM 3
221	unsigned char cable_id;
222	unsigned char read_status_mask;
223	unsigned char ignore_status_mask;
224	void __iomem * int_reg;
225	struct icom_regs __iomem *global_reg;
226	struct func_dram __iomem *dram;
227	int port;
228	struct statusArea *statStg;
229	dma_addr_t statStg_pci;
230	u32 *xmitRestart;
231	dma_addr_t xmitRestart_pci;
232	unsigned char *xmit_buf;
233	dma_addr_t xmit_buf_pci;
234	unsigned char *recv_buf;
235	dma_addr_t recv_buf_pci;
236	int next_rcv;
237	int put_length;
238	int status;
239	#define ICOM_PORT_ACTIVE 1 /* Port exists. */
240	#define ICOM_PORT_OFF 0 /* Port does not exist. */
241	int load_in_progress;
242	struct icom_adapter *adapter;
243	};
244
245	struct icom_adapter {
246	void __iomem * base_addr;
247	unsigned long base_addr_pci;
248	struct pci_dev *pci_dev;
249	struct icom_port port_info[4];
250	int index;
251	int version;
252	#define ADAPTER_V1 0x0001
253	#define ADAPTER_V2 0x0002
254	u32 subsystem_id;
255	#define FOUR_PORT_MODEL 0x0252
256	#define V2_TWO_PORTS_RVX 0x021A
257	#define V2_ONE_PORT_RVX_ONE_PORT_IMBED_MDM 0x0251
258	int numb_ports;
259	struct list_head icom_adapter_entry;
260	struct kref kref;
261	};
262
263	/* prototype */
264	extern void iCom_sercons_init(void);
265
266	struct lookup_proc_table {
267	u32 __iomem *global_control_reg;
268	unsigned long processor_id;
269	};
270
271	struct lookup_int_table {
272	u32 __iomem *global_int_mask;
273	unsigned long processor_id;
274	};

drivers/tty/serial/imx.c+0−2

@@ -1937,8 +1937,6 @@ static int imx_uart_rs485_config(struct uart_port *port, · 1936 unmodified lines
1937	rs485conf->flags & SER_RS485_RX_DURING_TX)	1937	rs485conf->flags & SER_RS485_RX_DURING_TX)
1938	imx_uart_start_rx(port);	1938	imx_uart_start_rx(port);
1939		1939
1940	port->rs485 = *rs485conf;
1941
1942	return 0;	1940	return 0;
1943	}	1941	}
1944		1942

drivers/tty/serial/jsm/jsm_cls.c+1−7

 	/*
 	 * If baud rate is zero, flush queues, and set mval to drop DTR.
 	 */
-	if ((ch->ch_c_cflag & (CBAUD)) == 0) {
+	if ((ch->ch_c_cflag & CBAUD) == B0) {
 		ch->ch_r_head = 0;
 		ch->ch_r_tail = 0;
 		ch->ch_e_head = 0;
 	if (!(ch->ch_c_cflag & PARODD))
 		lcr |= UART_LCR_EPAR;
-	/*
-	 * Not all platforms support mark/space parity,
-	 * so this will hide behind an ifdef.
-	 */
-#ifdef CMSPAR
 	if (ch->ch_c_cflag & CMSPAR)
 		lcr |= UART_LCR_SPAR;
-#endif
 	if (ch->ch_c_cflag & CSTOPB)
 		lcr |= UART_LCR_STOP;

drivers/tty/serial/jsm/jsm_neo.c+1−7

 	/*
 	 * If baud rate is zero, flush queues, and set mval to drop DTR.
 	 */
-	if ((ch->ch_c_cflag & (CBAUD)) == 0) {
+	if ((ch->ch_c_cflag & CBAUD) == B0) {
 		ch->ch_r_head = ch->ch_r_tail = 0;
 		ch->ch_e_head = ch->ch_e_tail = 0;
 	if (!(ch->ch_c_cflag & PARODD))
 		lcr |= UART_LCR_EPAR;
-	/*
-	 * Not all platforms support mark/space parity,
-	 * so this will hide behind an ifdef.
-	 */
-#ifdef CMSPAR
 	if (ch->ch_c_cflag & CMSPAR)
 		lcr |= UART_LCR_SPAR;
-#endif
 	if (ch->ch_c_cflag & CSTOPB)
 		lcr |= UART_LCR_STOP;

drivers/tty/serial/max310x.c+0−1

@@ -1037,7 +1037,6 @@ static int max310x_rs485_config(struct uart_port *port, · 1036 unmodified lines
1037		1037
1038	rs485->flags &= SER_RS485_RTS_ON_SEND \| SER_RS485_RX_DURING_TX \|	1038	rs485->flags &= SER_RS485_RTS_ON_SEND \| SER_RS485_RX_DURING_TX \|
1039	SER_RS485_ENABLED;	1039	SER_RS485_ENABLED;
1040	memset(rs485->padding, 0, sizeof(rs485->padding));
1041	port->rs485 = *rs485;	1040	port->rs485 = *rs485;
1042		1041
1043	schedule_work(&one->rs_work);	1042	schedule_work(&one->rs_work);

drivers/tty/serial/men_z135_uart.c+0−1

@@ -833,7 +833,6 @@ static int men_z135_probe(struct mcb_device *mdev, · 832 unmodified lines
833	uart->port.iotype = UPIO_MEM;	833	uart->port.iotype = UPIO_MEM;
834	uart->port.ops = &men_z135_ops;	834	uart->port.ops = &men_z135_ops;
835	uart->port.irq = mcb_get_irq(mdev);	835	uart->port.irq = mcb_get_irq(mdev);
836	uart->port.iotype = UPIO_MEM;
837	uart->port.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP;	836	uart->port.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP;
838	uart->port.line = line++;	837	uart->port.line = line++;
839	uart->port.dev = dev;	838	uart->port.dev = dev;

drivers/tty/serial/meson_uart.c+37−3

 #define AML_UART_BAUD_MASK		0x7fffff
 #define AML_UART_BAUD_USE		BIT(23)
 #define AML_UART_BAUD_XTAL		BIT(24)
+#define AML_UART_BAUD_XTAL_DIV2		BIT(27)
 #define AML_UART_PORT_NUM		12
 #define AML_UART_PORT_OFFSET		6
 static struct uart_port *meson_ports[AML_UART_PORT_NUM];
+struct meson_uart_data {
+	bool has_xtal_div2;
+};
 static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 {
 }
 	return (port->type == PORT_MESON) ? "meson_uart" : NULL;
 }
+/*
+ * This function is called only from probe() using a temporary io mapping
+ * in order to perform a reset before setting up the device. Since the
+ * temporarily mapped region was successfully requested, there can be no
+ * console on this port at this time. Hence it is not necessary for this
+ * function to acquire the port->lock. (Since there is no console on this
+ * port at this time, the port->lock is not initialized yet.)
+ */
 static void meson_uart_reset(struct uart_port *port)
 {
 	u32 val;
 static int meson_uart_startup(struct uart_port *port)
 {
+	unsigned long flags;
 	u32 val;
 	int ret = 0;
+	spin_lock_irqsave(&port->lock, flags);
 	val = readl(port->membase + AML_UART_CONTROL);
 	val |= AML_UART_CLEAR_ERR;
 	writel(val, port->membase + AML_UART_CONTROL);
 	val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
 	writel(val, port->membase + AML_UART_MISC);
+	spin_unlock_irqrestore(&port->lock, flags);
 	ret = request_irq(port->irq, meson_uart_interrupt, 0,
 			  port->name, port);
 static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
 {
-	u32 val;
+	const struct meson_uart_data *private_data = port->private_data;
+	u32 val = 0;
 	while (!meson_uart_tx_empty(port))
 		cpu_relax();
 	if (port->uartclk == 24000000) {
-		val = ((port->uartclk / 3) / baud) - 1;
+		unsigned int xtal_div = 3;
+		if (private_data && private_data->has_xtal_div2) {
+			xtal_div = 2;
+			val |= AML_UART_BAUD_XTAL_DIV2;
+		}
+		val |= DIV_ROUND_CLOSEST(port->uartclk / xtal_div, baud) - 1;
 		val |= AML_UART_BAUD_XTAL;
 	} else {
-		val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;
+		val =  DIV_ROUND_CLOSEST(port->uartclk / 4, baud) - 1;
 	}
 	val |= AML_UART_BAUD_USE;
 	writel(val, port->membase + AML_UART_REG5);
 	port->x_char = 0;
 	port->ops = &meson_uart_ops;
 	port->fifosize = fifosize;
+	port->private_data = (void *)device_get_match_data(&pdev->dev);
 	meson_ports[pdev->id] = port;
 	platform_set_drvdata(pdev, port);
 	return 0;
 }
+static struct meson_uart_data s4_uart_data = {
+	.has_xtal_div2 = true,
+};
 static const struct of_device_id meson_uart_dt_match[] = {
 	{ .compatible = "amlogic,meson6-uart" },
 	{ .compatible = "amlogic,meson8-uart" },
 	{ .compatible = "amlogic,meson8b-uart" },
 	{ .compatible = "amlogic,meson-gx-uart" },
+	{
+		.compatible = "amlogic,meson-s4-uart",
+		.data = (void *)&s4_uart_data,
+	},
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, meson_uart_dt_match);

drivers/tty/serial/mpc52xx_uart.c+2−3

 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/clk.h>
 	port->irqflags = IRQF_SHARED;
 	port->irq = psc_fifoc_irq;
 }
-#endif
-#ifdef CONFIG_PPC_MPC512x
 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
 #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))

drivers/tty/serial/msm_serial.c+5−0

 static void __msm_console_write(struct uart_port *port, const char *s,
 				unsigned int count, bool is_uartdm)
 {
+	unsigned long flags;
 	int i;
 	int num_newlines = 0;
 	bool replaced = false;
 			num_newlines++;
 	count += num_newlines;
+	local_irq_save(flags);
 	if (port->sysrq)
 		locked = 0;
 	else if (oops_in_progress)
 	if (locked)
 		spin_unlock(&port->lock);
+	local_irq_restore(flags);
 }
 static void msm_console_write(struct console *co, const char *s,

drivers/tty/serial/omap-serial.c+3−10

 	up->ier = 0;
 	serial_out(up, UART_IER, 0);
-	/* Clamp the delays to [0, 100ms] */
-	rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
-	rs485->delay_rts_after_send  = min(rs485->delay_rts_after_send, 100U);
-	/* store new config */
-	port->rs485 = *rs485;
 	if (up->rts_gpiod) {
 		/* enable / disable rts */
-		val = (port->rs485.flags & SER_RS485_ENABLED) ?
+		val = (rs485->flags & SER_RS485_ENABLED) ?
 			SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
-		val = (port->rs485.flags & val) ? 1 : 0;
+		val = (rs485->flags & val) ? 1 : 0;
 		gpiod_set_value(up->rts_gpiod, val);
 	}
 	/* If RS-485 is disabled, make sure the THR interrupt is fired when
 	 * TX FIFO is below the trigger level.
 	 */
-	if (!(port->rs485.flags & SER_RS485_ENABLED) &&
+	if (!(rs485->flags & SER_RS485_ENABLED) &&
 	    (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
 		up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 		serial_out(up, UART_OMAP_SCR, up->scr);

drivers/tty/serial/owl-uart.c+4−3

 	struct circ_buf *xmit = &port->state->xmit;
 	unsigned int ch;
-	if (uart_tx_stopped(port))
-		return;
 	if (port->x_char) {
 		while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU))
 			cpu_relax();
 		port->x_char = 0;
 	}
+	if (uart_tx_stopped(port))
+		return;
 	while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) {
 		if (uart_circ_empty(xmit))
 			break;
 	owl_port->port.uartclk = clk_get_rate(owl_port->clk);
 	if (owl_port->port.uartclk == 0) {
 		dev_err(&pdev->dev, "clock rate is zero\n");
+		clk_disable_unprepare(owl_port->clk);
 		return -EINVAL;
 	}
 	owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;

drivers/tty/serial/pch_uart.c+12−65

@@ -550,18 +550,6 @@ static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) · 549 unmodified lines
550	return (u8)msr;	550	return (u8)msr;
551	}	551	}
552		552
553	static void pch_uart_hal_write(struct eg20t_port *priv,
554	const unsigned char *buf, int tx_size)
555	{
556	int i;
557	unsigned int thr;
558
559	for (i = 0; i < tx_size;) {
560	thr = buf[i++];
561	iowrite8(thr, priv->membase + PCH_UART_THR);
562	}
563	}
564
565	static int pch_uart_hal_read(struct eg20t_port priv, unsigned char buf,	553	static int pch_uart_hal_read(struct eg20t_port priv, unsigned char buf,
566	int rx_size)	554	int rx_size)
567	{	555	{
@@ -624,22 +612,6 @@ static int push_rx(struct eg20t_port priv, const unsigned char buf, · 56 unmodified lines
624	return 0;	612	return 0;
625	}	613	}
626		614
627	static int pop_tx_x(struct eg20t_port priv, unsigned char buf)
628	{
629	int ret = 0;
630	struct uart_port *port = &priv->port;
631
632	if (port->x_char) {
633	dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
634	__func__, port->x_char, jiffies);
635	buf[0] = port->x_char;
636	port->x_char = 0;
637	ret = 1;
638	}
639
640	return ret;
641	}
642
643	static int dma_push_rx(struct eg20t_port *priv, int size)	615	static int dma_push_rx(struct eg20t_port *priv, int size)
644	{	616	{
645	int room;	617	int room;
@@ -785,31 +757,6 @@ static void pch_dma_tx_complete(void *arg) · 139 unmodified lines
785	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);	757	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
786	}	758	}
787		759
788	static int pop_tx(struct eg20t_port *priv, int size)
789	{
790	int count = 0;
791	struct uart_port *port = &priv->port;
792	struct circ_buf *xmit = &port->state->xmit;
793
794	if (uart_tx_stopped(port) \|\| uart_circ_empty(xmit) \|\| count >= size)
795	goto pop_tx_end;
796
797	do {
798	int cnt_to_end =
799	CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
800	int sz = min(size - count, cnt_to_end);
801	pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
802	xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
803	count += sz;
804	} while (!uart_circ_empty(xmit) && count < size);
805
806	pop_tx_end:
807	dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
808	count, size - count, jiffies);
809
810	return count;
811	}
812
813	static int handle_rx_to(struct eg20t_port *priv)	760	static int handle_rx_to(struct eg20t_port *priv)
814	{	761	{
815	struct pch_uart_buffer *buf;	762	struct pch_uart_buffer *buf;
@@ -875,8 +822,6 @@ static unsigned int handle_tx(struct eg20t_port *priv) · 59 unmodified lines
875	struct uart_port *port = &priv->port;	822	struct uart_port *port = &priv->port;
876	struct circ_buf *xmit = &port->state->xmit;	823	struct circ_buf *xmit = &port->state->xmit;
877	int fifo_size;	824	int fifo_size;
878	int tx_size;
879	int size;
880	int tx_empty;	825	int tx_empty;
881		826
882	if (!priv->start_tx) {	827	if (!priv->start_tx) {
@@ -889,19 +834,19 @@ static unsigned int handle_tx(struct eg20t_port *priv) · 6 unmodified lines
889		834
890	fifo_size = max(priv->fifo_size, 1);	835	fifo_size = max(priv->fifo_size, 1);
891	tx_empty = 1;	836	tx_empty = 1;
892	if (pop_tx_x(priv, xmit->buf)) {	837	if (port->x_char) {
893	pch_uart_hal_write(priv, xmit->buf, 1);	838	iowrite8(port->x_char, priv->membase + PCH_UART_THR);
894	port->icount.tx++;	839	port->icount.tx++;
		840	port->x_char = 0;
895	tx_empty = 0;	841	tx_empty = 0;
896	fifo_size--;	842	fifo_size--;
897	}	843	}
898	size = min(xmit->head - xmit->tail, fifo_size);
899	if (size < 0)
900	size = fifo_size;
901		844
902	tx_size = pop_tx(priv, size);	845	while (!uart_tx_stopped(port) && !uart_circ_empty(xmit) && fifo_size) {
903	if (tx_size > 0) {	846	iowrite8(xmit->buf[xmit->tail], priv->membase + PCH_UART_THR);
904	port->icount.tx += tx_size;	847	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
		848	port->icount.tx++;
		849	fifo_size--;
905	tx_empty = 0;	850	tx_empty = 0;
906	}	851	}
907		852
@@ -946,9 +891,11 @@ static unsigned int dma_handle_tx(struct eg20t_port *priv) · 38 unmodified lines
946	}	891	}
947		892
948	fifo_size = max(priv->fifo_size, 1);	893	fifo_size = max(priv->fifo_size, 1);
949	if (pop_tx_x(priv, xmit->buf)) {	894
950	pch_uart_hal_write(priv, xmit->buf, 1);	895	if (port->x_char) {
		896	iowrite8(port->x_char, priv->membase + PCH_UART_THR);
951	port->icount.tx++;	897	port->icount.tx++;
		898	port->x_char = 0;
952	fifo_size--;	899	fifo_size--;
953	}	900	}
954		901

drivers/tty/serial/pic32_uart.c+116−43

@@ -25,38 +25,114 @@ · 24 unmodified lines
25	#include <linux/delay.h>	25	#include <linux/delay.h>
26		26
27	#include <asm/mach-pic32/pic32.h>	27	#include <asm/mach-pic32/pic32.h>
28	#include "pic32_uart.h"
29		28
30	/* UART name and device definitions */	29	/* UART name and device definitions */
31	#define PIC32_DEV_NAME "pic32-uart"	30	#define PIC32_DEV_NAME "pic32-uart"
32	#define PIC32_MAX_UARTS 6	31	#define PIC32_MAX_UARTS 6
33	#define PIC32_SDEV_NAME "ttyPIC"	32	#define PIC32_SDEV_NAME "ttyPIC"
34		33
35	/* pic32_sport pointer for console use */	34	#define PIC32_UART_DFLT_BRATE 9600
36	static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];	35	#define PIC32_UART_TX_FIFO_DEPTH 8
		36	#define PIC32_UART_RX_FIFO_DEPTH 8
		37
		38	#define PIC32_UART_MODE 0x00
		39	#define PIC32_UART_STA 0x10
		40	#define PIC32_UART_TX 0x20
		41	#define PIC32_UART_RX 0x30
		42	#define PIC32_UART_BRG 0x40
		43
		44	/* struct pic32_sport - pic32 serial port descriptor
		45	* @port: uart port descriptor
		46	* @idx: port index
		47	* @irq_fault: virtual fault interrupt number
		48	* @irq_fault_name: irq fault name
		49	* @irq_rx: virtual rx interrupt number
		50	* @irq_rx_name: irq rx name
		51	* @irq_tx: virtual tx interrupt number
		52	* @irq_tx_name: irq tx name
		53	* @cts_gpio: clear to send gpio
		54	* @dev: device descriptor
		55	**/
		56	struct pic32_sport {
		57	struct uart_port port;
		58	int idx;
		59
		60	int irq_fault;
		61	const char *irq_fault_name;
		62	int irq_rx;
		63	const char *irq_rx_name;
		64	int irq_tx;
		65	const char *irq_tx_name;
		66	bool enable_tx_irq;
		67
		68	bool hw_flow_ctrl;
		69	int cts_gpio;
		70
		71	struct clk *clk;
		72
		73	struct device *dev;
		74	};
37		75
38	static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)	76	static inline struct pic32_sport to_pic32_sport(struct uart_port port)
39	{	77	{
40	/* wait for tx empty, otherwise chars will be lost or corrupted */	78	return container_of(port, struct pic32_sport, port);
41	while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
42	udelay(1);
43	}	79	}
44		80
45	static inline int pic32_enable_clock(struct pic32_sport *sport)	81	static inline void pic32_uart_writel(struct pic32_sport *sport,
		82	u32 reg, u32 val)
46	{	83	{
47	int ret = clk_prepare_enable(sport->clk);	84	__raw_writel(val, sport->port.membase + reg);
48		85	}
49	if (ret)
50	return ret;
51		86
52	sport->ref_clk++;	87	static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
53	return 0;	88	{
		89	return __raw_readl(sport->port.membase + reg);
54	}	90	}
55		91
56	static inline void pic32_disable_clock(struct pic32_sport *sport)	92	/* pic32 uart mode register bits */
		93	#define PIC32_UART_MODE_ON BIT(15)
		94	#define PIC32_UART_MODE_FRZ BIT(14)
		95	#define PIC32_UART_MODE_SIDL BIT(13)
		96	#define PIC32_UART_MODE_IREN BIT(12)
		97	#define PIC32_UART_MODE_RTSMD BIT(11)
		98	#define PIC32_UART_MODE_RESV1 BIT(10)
		99	#define PIC32_UART_MODE_UEN1 BIT(9)
		100	#define PIC32_UART_MODE_UEN0 BIT(8)
		101	#define PIC32_UART_MODE_WAKE BIT(7)
		102	#define PIC32_UART_MODE_LPBK BIT(6)
		103	#define PIC32_UART_MODE_ABAUD BIT(5)
		104	#define PIC32_UART_MODE_RXINV BIT(4)
		105	#define PIC32_UART_MODE_BRGH BIT(3)
		106	#define PIC32_UART_MODE_PDSEL1 BIT(2)
		107	#define PIC32_UART_MODE_PDSEL0 BIT(1)
		108	#define PIC32_UART_MODE_STSEL BIT(0)
		109
		110	/* pic32 uart status register bits */
		111	#define PIC32_UART_STA_UTXISEL1 BIT(15)
		112	#define PIC32_UART_STA_UTXISEL0 BIT(14)
		113	#define PIC32_UART_STA_UTXINV BIT(13)
		114	#define PIC32_UART_STA_URXEN BIT(12)
		115	#define PIC32_UART_STA_UTXBRK BIT(11)
		116	#define PIC32_UART_STA_UTXEN BIT(10)
		117	#define PIC32_UART_STA_UTXBF BIT(9)
		118	#define PIC32_UART_STA_TRMT BIT(8)
		119	#define PIC32_UART_STA_URXISEL1 BIT(7)
		120	#define PIC32_UART_STA_URXISEL0 BIT(6)
		121	#define PIC32_UART_STA_ADDEN BIT(5)
		122	#define PIC32_UART_STA_RIDLE BIT(4)
		123	#define PIC32_UART_STA_PERR BIT(3)
		124	#define PIC32_UART_STA_FERR BIT(2)
		125	#define PIC32_UART_STA_OERR BIT(1)
		126	#define PIC32_UART_STA_URXDA BIT(0)
		127
		128	/* pic32_sport pointer for console use */
		129	static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
		130
		131	static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
57	{	132	{
58	sport->ref_clk--;	133	/* wait for tx empty, otherwise chars will be lost or corrupted */
59	clk_disable_unprepare(sport->clk);	134	while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
		135	udelay(1);
60	}	136	}
61		137
62	/* serial core request to check if uart tx buffer is empty */	138	/* serial core request to check if uart tx buffer is empty */
@@ -117,16 +193,16 @@ static unsigned int pic32_uart_get_mctrl(struct uart_port *port) · 54 unmodified lines
117	*/	193	*/
118	static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)	194	static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
119	{	195	{
120	if (en && !tx_irq_enabled(sport)) {	196	if (en && !sport->enable_tx_irq) {
121	enable_irq(sport->irq_tx);	197	enable_irq(sport->irq_tx);
122	tx_irq_enabled(sport) = 1;	198	sport->enable_tx_irq = true;
123	} else if (!en && tx_irq_enabled(sport)) {	199	} else if (!en && sport->enable_tx_irq) {
124	/* use disable_irq_nosync() and not disable_irq() to avoid self	200	/* use disable_irq_nosync() and not disable_irq() to avoid self
125	* imposed deadlock by not waiting for irq handler to end,	201	* imposed deadlock by not waiting for irq handler to end,
126	* since this callback is called from interrupt context.	202	* since this callback is called from interrupt context.
127	*/	203	*/
128	disable_irq_nosync(sport->irq_tx);	204	disable_irq_nosync(sport->irq_tx);
129	tx_irq_enabled(sport) = 0;	205	sport->enable_tx_irq = false;
130	}	206	}
131	}	207	}
132		208
@@ -395,7 +471,7 @@ static int pic32_uart_startup(struct uart_port *port) · 262 unmodified lines
395		471
396	local_irq_save(flags);	472	local_irq_save(flags);
397		473
398	ret = pic32_enable_clock(sport);	474	ret = clk_prepare_enable(sport->clk);
399	if (ret) {	475	if (ret) {
400	local_irq_restore(flags);	476	local_irq_restore(flags);
401	goto out_done;	477	goto out_done;
@@ -419,7 +495,7 @@ static int pic32_uart_startup(struct uart_port *port) · 17 unmodified lines
419	* For each irq request_irq() is called with interrupt disabled.	495	* For each irq request_irq() is called with interrupt disabled.
420	* And the irq is enabled as soon as we are ready to handle them.	496	* And the irq is enabled as soon as we are ready to handle them.
421	*/	497	*/
422	tx_irq_enabled(sport) = 0;	498	sport->enable_tx_irq = false;
423		499
424	sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",	500	sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
425	pic32_uart_type(port),	501	pic32_uart_type(port),
@@ -431,7 +507,7 @@ static int pic32_uart_startup(struct uart_port *port) · 5 unmodified lines
431	}	507	}
432	irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);	508	irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
433	ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,	509	ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
434	sport->irqflags_fault, sport->irq_fault_name, port);	510	IRQF_NO_THREAD, sport->irq_fault_name, port);
435	if (ret) {	511	if (ret) {
436	dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",	512	dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
437	__func__, sport->irq_fault, ret,	513	__func__, sport->irq_fault, ret,
@@ -449,7 +525,7 @@ static int pic32_uart_startup(struct uart_port *port) · 11 unmodified lines
449	}	525	}
450	irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);	526	irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
451	ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,	527	ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
452	sport->irqflags_rx, sport->irq_rx_name, port);	528	IRQF_NO_THREAD, sport->irq_rx_name, port);
453	if (ret) {	529	if (ret) {
454	dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",	530	dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
455	__func__, sport->irq_rx, ret,	531	__func__, sport->irq_rx, ret,
@@ -467,7 +543,7 @@ static int pic32_uart_startup(struct uart_port *port) · 11 unmodified lines
467	}	543	}
468	irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);	544	irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
469	ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,	545	ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
470	sport->irqflags_tx, sport->irq_tx_name, port);	546	IRQF_NO_THREAD, sport->irq_tx_name, port);
471	if (ret) {	547	if (ret) {
472	dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",	548	dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
473	__func__, sport->irq_tx, ret,	549	__func__, sport->irq_tx, ret,
@@ -488,19 +564,21 @@ static int pic32_uart_startup(struct uart_port *port) · 14 unmodified lines
488	/* enable all interrupts and eanable uart */	564	/* enable all interrupts and eanable uart */
489	pic32_uart_en_and_unmask(port);	565	pic32_uart_en_and_unmask(port);
490		566
		567	local_irq_restore(flags);
		568
491	enable_irq(sport->irq_rx);	569	enable_irq(sport->irq_rx);
492		570
493	return 0;	571	return 0;
494		572
495	out_t:	573	out_t:
496	kfree(sport->irq_tx_name);
497	free_irq(sport->irq_tx, port);	574	free_irq(sport->irq_tx, port);
		575	kfree(sport->irq_tx_name);
498	out_r:	576	out_r:
499	kfree(sport->irq_rx_name);
500	free_irq(sport->irq_rx, port);	577	free_irq(sport->irq_rx, port);
		578	kfree(sport->irq_rx_name);
501	out_f:	579	out_f:
502	kfree(sport->irq_fault_name);
503	free_irq(sport->irq_fault, port);	580	free_irq(sport->irq_fault, port);
		581	kfree(sport->irq_fault_name);
504	out_done:	582	out_done:
505	return ret;	583	return ret;
506	}	584	}
@@ -515,12 +593,15 @@ static void pic32_uart_shutdown(struct uart_port *port) · 8 unmodified lines
515	spin_lock_irqsave(&port->lock, flags);	593	spin_lock_irqsave(&port->lock, flags);
516	pic32_uart_dsbl_and_mask(port);	594	pic32_uart_dsbl_and_mask(port);
517	spin_unlock_irqrestore(&port->lock, flags);	595	spin_unlock_irqrestore(&port->lock, flags);
518	pic32_disable_clock(sport);	596	clk_disable_unprepare(sport->clk);
519		597
520	/* free all 3 interrupts for this UART */	598	/* free all 3 interrupts for this UART */
521	free_irq(sport->irq_fault, port);	599	free_irq(sport->irq_fault, port);
		600	kfree(sport->irq_fault_name);
522	free_irq(sport->irq_tx, port);	601	free_irq(sport->irq_tx, port);
		602	kfree(sport->irq_tx_name);
523	free_irq(sport->irq_rx, port);	603	free_irq(sport->irq_rx, port);
		604	kfree(sport->irq_rx_name);
524	}	605	}
525		606
526	/* serial core request to change current uart setting */	607	/* serial core request to change current uart setting */
@@ -712,10 +793,9 @@ static void pic32_console_write(struct console co, const char s, · 185 unmodified lines
712	unsigned int count)	793	unsigned int count)
713	{	794	{
714	struct pic32_sport *sport = pic32_sports[co->index];	795	struct pic32_sport *sport = pic32_sports[co->index];
715	struct uart_port *port = pic32_get_port(sport);
716		796
717	/* call uart helper to deal with \r\n */	797	/* call uart helper to deal with \r\n */
718	uart_console_write(port, s, count, pic32_console_putchar);	798	uart_console_write(&sport->port, s, count, pic32_console_putchar);
719	}	799	}
720		800
721	/* console core request to setup given console, find matching uart	801	/* console core request to setup given console, find matching uart
@@ -724,7 +804,6 @@ static void pic32_console_write(struct console co, const char s, · 2 unmodified lines
724	static int pic32_console_setup(struct console co, char options)	804	static int pic32_console_setup(struct console co, char options)
725	{	805	{
726	struct pic32_sport *sport;	806	struct pic32_sport *sport;
727	struct uart_port *port = NULL;
728	int baud = 115200;	807	int baud = 115200;
729	int bits = 8;	808	int bits = 8;
730	int parity = 'n';	809	int parity = 'n';
@@ -737,16 +816,15 @@ static int pic32_console_setup(struct console co, char options) · 6 unmodified lines
737	sport = pic32_sports[co->index];	816	sport = pic32_sports[co->index];
738	if (!sport)	817	if (!sport)
739	return -ENODEV;	818	return -ENODEV;
740	port = pic32_get_port(sport);
741		819
742	ret = pic32_enable_clock(sport);	820	ret = clk_prepare_enable(sport->clk);
743	if (ret)	821	if (ret)
744	return ret;	822	return ret;
745		823
746	if (options)	824	if (options)
747	uart_parse_options(options, &baud, &parity, &bits, &flow);	825	uart_parse_options(options, &baud, &parity, &bits, &flow);
748		826
749	return uart_set_options(port, co, baud, parity, bits, flow);	827	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
750	}	828	}
751		829
752	static struct uart_driver pic32_uart_driver;	830	static struct uart_driver pic32_uart_driver;
@@ -816,13 +894,9 @@ static int pic32_uart_probe(struct platform_device *pdev) · 63 unmodified lines
816		894
817	sport->idx = uart_idx;	895	sport->idx = uart_idx;
818	sport->irq_fault = irq_of_parse_and_map(np, 0);	896	sport->irq_fault = irq_of_parse_and_map(np, 0);
819	sport->irqflags_fault = IRQF_NO_THREAD;
820	sport->irq_rx = irq_of_parse_and_map(np, 1);	897	sport->irq_rx = irq_of_parse_and_map(np, 1);
821	sport->irqflags_rx = IRQF_NO_THREAD;
822	sport->irq_tx = irq_of_parse_and_map(np, 2);	898	sport->irq_tx = irq_of_parse_and_map(np, 2);
823	sport->irqflags_tx = IRQF_NO_THREAD;
824	sport->clk = devm_clk_get(&pdev->dev, NULL);	899	sport->clk = devm_clk_get(&pdev->dev, NULL);
825	sport->cts_gpio = -EINVAL;
826	sport->dev = &pdev->dev;	900	sport->dev = &pdev->dev;
827		901
828	/* Hardware flow control: gpios	902	/* Hardware flow control: gpios
@@ -850,7 +924,6 @@ static int pic32_uart_probe(struct platform_device *pdev) · 21 unmodified lines
850		924
851	pic32_sports[uart_idx] = sport;	925	pic32_sports[uart_idx] = sport;
852	port = &sport->port;	926	port = &sport->port;
853	memset(port, 0, sizeof(*port));
854	port->iotype = UPIO_MEM;	927	port->iotype = UPIO_MEM;
855	port->mapbase = res_mem->start;	928	port->mapbase = res_mem->start;
856	port->ops = &pic32_uart_ops;	929	port->ops = &pic32_uart_ops;
@@ -872,7 +945,7 @@ static int pic32_uart_probe(struct platform_device *pdev) · 15 unmodified lines
872	/* The peripheral clock has been enabled by console_setup,	945	/* The peripheral clock has been enabled by console_setup,
873	* so disable it till the port is used.	946	* so disable it till the port is used.
874	*/	947	*/
875	pic32_disable_clock(sport);	948	clk_disable_unprepare(sport->clk);
876	}	949	}
877	#endif	950	#endif
878		951
@@ -893,7 +966,7 @@ static int pic32_uart_remove(struct platform_device *pdev) · 14 unmodified lines
893	struct pic32_sport *sport = to_pic32_sport(port);	966	struct pic32_sport *sport = to_pic32_sport(port);
894		967
895	uart_remove_one_port(&pic32_uart_driver, port);	968	uart_remove_one_port(&pic32_uart_driver, port);
896	pic32_disable_clock(sport);	969	clk_disable_unprepare(sport->clk);
897	platform_set_drvdata(pdev, NULL);	970	platform_set_drvdata(pdev, NULL);
898	pic32_sports[sport->idx] = NULL;	971	pic32_sports[sport->idx] = NULL;
899		972

drivers/tty/serial/pic32_uart.h+0−125

@@ -1,125 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0+ */
2	/*
3	* PIC32 Integrated Serial Driver.
4	*
5	* Copyright (C) 2015 Microchip Technology, Inc.
6	*
7	* Authors:
8	* Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
9	*/
10	#ifndef __DT_PIC32_UART_H__
11	#define __DT_PIC32_UART_H__
12
13	#define PIC32_UART_DFLT_BRATE (9600)
14	#define PIC32_UART_TX_FIFO_DEPTH (8)
15	#define PIC32_UART_RX_FIFO_DEPTH (8)
16
17	#define PIC32_UART_MODE 0x00
18	#define PIC32_UART_STA 0x10
19	#define PIC32_UART_TX 0x20
20	#define PIC32_UART_RX 0x30
21	#define PIC32_UART_BRG 0x40
22
23	struct pic32_console_opt {
24	int baud;
25	int parity;
26	int bits;
27	int flow;
28	};
29
30	/* struct pic32_sport - pic32 serial port descriptor
31	* @port: uart port descriptor
32	* @idx: port index
33	* @irq_fault: virtual fault interrupt number
34	* @irqflags_fault: flags related to fault irq
35	* @irq_fault_name: irq fault name
36	* @irq_rx: virtual rx interrupt number
37	* @irqflags_rx: flags related to rx irq
38	* @irq_rx_name: irq rx name
39	* @irq_tx: virtual tx interrupt number
40	* @irqflags_tx: : flags related to tx irq
41	* @irq_tx_name: irq tx name
42	* @cts_gpio: clear to send gpio
43	* @dev: device descriptor
44	**/
45	struct pic32_sport {
46	struct uart_port port;
47	struct pic32_console_opt opt;
48	int idx;
49
50	int irq_fault;
51	int irqflags_fault;
52	const char *irq_fault_name;
53	int irq_rx;
54	int irqflags_rx;
55	const char *irq_rx_name;
56	int irq_tx;
57	int irqflags_tx;
58	const char *irq_tx_name;
59	u8 enable_tx_irq;
60
61	bool hw_flow_ctrl;
62	int cts_gpio;
63
64	int ref_clk;
65	struct clk *clk;
66
67	struct device *dev;
68	};
69	#define to_pic32_sport(c) container_of(c, struct pic32_sport, port)
70	#define pic32_get_port(sport) (&sport->port)
71	#define pic32_get_opt(sport) (&sport->opt)
72	#define tx_irq_enabled(sport) (sport->enable_tx_irq)
73
74	static inline void pic32_uart_writel(struct pic32_sport *sport,
75	u32 reg, u32 val)
76	{
77	struct uart_port *port = pic32_get_port(sport);
78
79	__raw_writel(val, port->membase + reg);
80	}
81
82	static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
83	{
84	struct uart_port *port = pic32_get_port(sport);
85
86	return __raw_readl(port->membase + reg);
87	}
88
89	/* pic32 uart mode register bits */
90	#define PIC32_UART_MODE_ON BIT(15)
91	#define PIC32_UART_MODE_FRZ BIT(14)
92	#define PIC32_UART_MODE_SIDL BIT(13)
93	#define PIC32_UART_MODE_IREN BIT(12)
94	#define PIC32_UART_MODE_RTSMD BIT(11)
95	#define PIC32_UART_MODE_RESV1 BIT(10)
96	#define PIC32_UART_MODE_UEN1 BIT(9)
97	#define PIC32_UART_MODE_UEN0 BIT(8)
98	#define PIC32_UART_MODE_WAKE BIT(7)
99	#define PIC32_UART_MODE_LPBK BIT(6)
100	#define PIC32_UART_MODE_ABAUD BIT(5)
101	#define PIC32_UART_MODE_RXINV BIT(4)
102	#define PIC32_UART_MODE_BRGH BIT(3)
103	#define PIC32_UART_MODE_PDSEL1 BIT(2)
104	#define PIC32_UART_MODE_PDSEL0 BIT(1)
105	#define PIC32_UART_MODE_STSEL BIT(0)
106
107	/* pic32 uart status register bits */
108	#define PIC32_UART_STA_UTXISEL1 BIT(15)
109	#define PIC32_UART_STA_UTXISEL0 BIT(14)
110	#define PIC32_UART_STA_UTXINV BIT(13)
111	#define PIC32_UART_STA_URXEN BIT(12)
112	#define PIC32_UART_STA_UTXBRK BIT(11)
113	#define PIC32_UART_STA_UTXEN BIT(10)
114	#define PIC32_UART_STA_UTXBF BIT(9)
115	#define PIC32_UART_STA_TRMT BIT(8)
116	#define PIC32_UART_STA_URXISEL1 BIT(7)
117	#define PIC32_UART_STA_URXISEL0 BIT(6)
118	#define PIC32_UART_STA_ADDEN BIT(5)
119	#define PIC32_UART_STA_RIDLE BIT(4)
120	#define PIC32_UART_STA_PERR BIT(3)
121	#define PIC32_UART_STA_FERR BIT(2)
122	#define PIC32_UART_STA_OERR BIT(1)
123	#define PIC32_UART_STA_URXDA BIT(0)
124
125	#endif /* __DT_PIC32_UART_H__ */

drivers/tty/serial/pmac_zilog.c+2−67

  */
 #undef DEBUG
-#undef DEBUG_HARD
 #undef USE_CTRL_O_SYSRQ
 #include <linux/module.h>
 #include <asm/irq.h>
 #ifdef CONFIG_PPC_PMAC
-#include <asm/prom.h>
 #include <asm/machdep.h>
 #include <asm/pmac_feature.h>
 #include <asm/dbdma.h>
 #include "pmac_zilog.h"
-/* Not yet implemented */
-#undef HAS_DBDMA
-static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
 MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
 MODULE_LICENSE("GPL");
 	spin_lock(&uap_a->port.lock);
 	r3 = read_zsreg(uap_a, R3);
-#ifdef DEBUG_HARD
-	pmz_debug("irq, r3: %x\n", r3);
-#endif
 	/* Channel A */
 	push = false;
 	if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
 	struct uart_pmac_port *uap = to_pmz(port);
 	unsigned char status;
-	pmz_debug("pmz: start_tx()\n");
 	uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
 	uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
 		struct circ_buf *xmit = &port->state->xmit;
 		if (uart_circ_empty(xmit))
-			goto out;
+			return;
 		write_zsdata(uap, xmit->buf[xmit->tail]);
 		zssync(uap);
 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 		if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 			uart_write_wakeup(&uap->port);
 	}
- out:
-	pmz_debug("pmz: start_tx() done.\n");
 }
 /*
 {
 	struct uart_pmac_port *uap = to_pmz(port);
-	pmz_debug("pmz: stop_rx()()\n");
 	/* Disable all RX interrupts.  */
 	uap->curregs[R1] &= ~RxINT_MASK;
 	pmz_maybe_update_regs(uap);
-	pmz_debug("pmz: stop_rx() done.\n");
 }
 /*
 	unsigned long flags;
 	int pwr_delay = 0;
-	pmz_debug("pmz: startup()\n");
 	uap->flags |= PMACZILOG_FLAG_IS_OPEN;
 	/* A console is never powered down. Else, power up and
 	pmz_interrupt_control(uap, 1);
 	spin_unlock_irqrestore(&port->lock, flags);
-	pmz_debug("pmz: startup() done.\n");
 	return 0;
 }
 	struct uart_pmac_port *uap = to_pmz(port);
 	unsigned long flags;
-	pmz_debug("pmz: shutdown()\n");
 	spin_lock_irqsave(&port->lock, flags);
 	/* Disable interrupt requests for the channel */
 		pmz_set_scc_power(uap, 0);	/* Shut the chip down */
 	spin_unlock_irqrestore(&port->lock, flags);
-	pmz_debug("pmz: shutdown() done.\n");
 }
 /* Shared by TTY driver and serial console setup.  The port lock is held
 	struct uart_pmac_port *uap = to_pmz(port);
 	unsigned long baud;
-	pmz_debug("pmz: set_termios()\n");
-	memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
 	/* XXX Check which revs of machines actually allow 1 and 4Mb speeds
 	 * on the IR dongle. Note that the IRTTY driver currently doesn't know
 	 * about the FIR mode and high speed modes. So these are unused. For
 		pmz_maybe_update_regs(uap);
 	}
 	uart_update_timeout(port, termios->c_cflag, baud);
-	pmz_debug("pmz: set_termios() done.\n");
 }
 /* The port lock is not held.  */
 		char	name[1];
 	} *slots;
 	int len;
-	struct resource r_ports, r_rxdma, r_txdma;
+	struct resource r_ports;
 	/*
 	 * Request & map chip registers
 	uap->control_reg = uap->port.membase;
 	uap->data_reg = uap->control_reg + 0x10;
-	/*
-	 * Request & map DBDMA registers
-	 */
-#ifdef HAS_DBDMA
-	if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
-	    of_address_to_resource(np, 2, &r_rxdma) == 0)
-		uap->flags |= PMACZILOG_FLAG_HAS_DMA;
-#else
-	memset(&r_txdma, 0, sizeof(struct resource));
-	memset(&r_rxdma, 0, sizeof(struct resource));
-#endif
-	if (ZS_HAS_DMA(uap)) {
-		uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
-		if (uap->tx_dma_regs == NULL) {
-			uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
-			goto no_dma;
-		}
-		uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
-		if (uap->rx_dma_regs == NULL) {
-			iounmap(uap->tx_dma_regs);
-			uap->tx_dma_regs = NULL;
-			uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
-			goto no_dma;
-		}
-		uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
-		uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
-	}
-no_dma:
 	/*
 	 * Detect port type
 	    of_device_is_compatible(np->parent->parent, "gatwick")) {
 		/* IRQs on gatwick are offset by 64 */
 		uap->port.irq = irq_create_mapping(NULL, 64 + 15);
-		uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
-		uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
 	}
 	/* Setup some valid baud rate information in the register
 	struct device_node *np;
 	np = uap->node;
-	iounmap(uap->rx_dma_regs);
-	iounmap(uap->tx_dma_regs);
 	iounmap(uap->control_reg);
 	uap->node = NULL;
 	of_node_put(np);
 static int __init init_pmz(void)
 {
 	int rc, i;
-	printk(KERN_INFO "%s\n", version);
 	/*
 	 * First, we need to do a direct OF-based probe pass. We

drivers/tty/serial/pmac_zilog.h+0−11

 #define PMACZILOG_FLAG_TX_ACTIVE	0x00000040
 #define PMACZILOG_FLAG_IS_IRDA		0x00000100
 #define PMACZILOG_FLAG_IS_INTMODEM	0x00000200
-#define PMACZILOG_FLAG_HAS_DMA		0x00000400
 #define PMACZILOG_FLAG_RSRC_REQUESTED	0x00000800
 #define PMACZILOG_FLAG_IS_OPEN		0x00002000
 #define PMACZILOG_FLAG_IS_EXTCLK	0x00008000
 	volatile u8			__iomem *control_reg;
 	volatile u8			__iomem *data_reg;
-#ifdef CONFIG_PPC_PMAC
-	unsigned int			tx_dma_irq;
-	unsigned int			rx_dma_irq;
-	volatile struct dbdma_regs	__iomem *tx_dma_regs;
-	volatile struct dbdma_regs	__iomem *rx_dma_regs;
-#endif
 	unsigned char			irq_name[8];
-	struct ktermios			termios_cache;
 };
 #define to_pmz(p) ((struct uart_pmac_port *)(p))
 #define ZS_WANTS_MODEM_STATUS(UP)	((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
 #define ZS_IS_IRDA(UP)			((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
 #define ZS_IS_INTMODEM(UP)		((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
-#define ZS_HAS_DMA(UP)			((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
 #define ZS_IS_OPEN(UP)			((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
 #define ZS_IS_EXTCLK(UP)		((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)

drivers/tty/serial/qcom_geni_serial.c+37−21

 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
-static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
-					32000000, 48000000, 51200000, 64000000,
-					80000000, 96000000, 100000000,
-					102400000, 112000000, 120000000,
-					128000000};
 #define to_dev_port(ptr, member) \
 		container_of(ptr, struct qcom_geni_serial_port, member)
 		 */
 		qcom_geni_serial_poll_tx_done(uport);
-		if (uart_circ_chars_pending(&uport->state->xmit)) {
+		if (!uart_circ_empty(&uport->state->xmit)) {
 			irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 			writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 					uport->membase + SE_GENI_M_IRQ_EN);
 	return 0;
 }
-static unsigned long get_clk_cfg(unsigned long clk_freq)
+static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
-		if (!(root_freq[i] % clk_freq))
-			return root_freq[i];
-	}
-	return 0;
-}
-static unsigned long get_clk_div_rate(unsigned int baud,
 			unsigned int sampling_rate, unsigned int *clk_div)
 {
 	unsigned long ser_clk;
 	unsigned long desired_clk;
+	unsigned long freq, prev;
+	unsigned long div, maxdiv;
+	int64_t mult;
 	desired_clk = baud * sampling_rate;
-	ser_clk = get_clk_cfg(desired_clk);
+	if (!desired_clk) {
+		pr_err("%s: Invalid frequency\n", __func__);
+		return 0;
+	}
+	maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
+	prev = 0;
+	for (div = 1; div <= maxdiv; div++) {
+		mult = div * desired_clk;
+		if (mult > ULONG_MAX)
+			break;
+		freq = clk_round_rate(clk, (unsigned long)mult);
+		if (!(freq % desired_clk)) {
+			ser_clk = freq;
+			break;
+		}
+		if (!prev)
+			ser_clk = freq;
+		else if (prev == freq)
+			break;
+		prev = freq;
+	}
 	if (!ser_clk) {
 		pr_err("%s: Can't find matching DFS entry for baud %d\n",
 								__func__, baud);
 	}
 	*clk_div = ser_clk / desired_clk;
+	if (!(*clk_div))
+		*clk_div = 1;
 	return ser_clk;
 }
 	if (ver >= QUP_SE_VERSION_2_5)
 		sampling_rate /= 2;
-	clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
+	clk_rate = get_clk_div_rate(port->se.clk, baud,
+		sampling_rate, &clk_div);
 	if (!clk_rate)
 		goto out_restart_rx;

drivers/tty/serial/rda-uart.c+2−0

 		fallthrough;
 	case CS7:
 		ctrl &= ~RDA_UART_DBITS_8;
+		termios->c_cflag &= ~CSIZE;
+		termios->c_cflag |= CS7;
 		break;
 	default:
 		ctrl |= RDA_UART_DBITS_8;

drivers/tty/serial/sa1100.c+2−2

 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
 	quot = uart_get_divisor(port, baud);
+	del_timer_sync(&sport->timer);
 	spin_lock_irqsave(&sport->port.lock, flags);
 	sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
 				UTSR1_TO_SM(UTSR1_ROR);
 	}
-	del_timer_sync(&sport->timer);
 	/*
 	 * Update the per-port timeout.
 	 */

drivers/tty/serial/samsung_tty.c+13−0

 			     unsigned int count)
 {
 	unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
+	unsigned long flags;
+	bool locked = true;
 	/* not possible to xmit on unconfigured port */
 	if (!s3c24xx_port_configured(ucon))
 		return;
+	if (cons_uart->sysrq)
+		locked = false;
+	else if (oops_in_progress)
+		locked = spin_trylock_irqsave(&cons_uart->lock, flags);
+	else
+		spin_lock_irqsave(&cons_uart->lock, flags);
 	uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
+	if (locked)
+		spin_unlock_irqrestore(&cons_uart->lock, flags);
 }
 /* Shouldn't be __init, as it can be instantiated from other module */
 		.num_clks	= 1,
 		.clksel_mask	= 0,
 		.clksel_shift	= 0,
+		.ucon_mask	= APPLE_S5L_UCON_MASK,
 	},
 	.def_cfg = {
 		.ucon		= APPLE_S5L_UCON_DEFAULT,

drivers/tty/serial/sc16is7xx.c+0−10

@@ -1134,16 +1134,6 @@ static int sc16is7xx_config_rs485(struct uart_port *port, · 1133 unmodified lines
1134	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);	1134	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1135		1135
1136	if (rs485->flags & SER_RS485_ENABLED) {	1136	if (rs485->flags & SER_RS485_ENABLED) {
1137	bool rts_during_rx, rts_during_tx;
1138
1139	rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
1140	rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
1141
1142	if (rts_during_rx == rts_during_tx)
1143	dev_err(port->dev,
1144	"unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
1145	rts_during_tx, rts_during_rx);
1146
1147	/*	1137	/*
1148	* RTS signal is handled by HW, it's timing can't be influenced.	1138	* RTS signal is handled by HW, it's timing can't be influenced.
1149	* However, it's sometimes useful to delay TX even without RTS	1139	* However, it's sometimes useful to delay TX even without RTS

drivers/tty/serial/serial_core.c+69−20

@@ -24,6 +24,7 @@ · 23 unmodified lines
24	#include <linux/sysrq.h>	24	#include <linux/sysrq.h>
25	#include <linux/delay.h>	25	#include <linux/delay.h>
26	#include <linux/mutex.h>	26	#include <linux/mutex.h>
		27	#include <linux/math64.h>
27	#include <linux/security.h>	28	#include <linux/security.h>
28		29
29	#include <linux/irq.h>	30	#include <linux/irq.h>
@@ -42,6 +43,11 @@ static struct lock_class_key port_lock_key; · 12 unmodified lines
42		43
43	#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)	44	#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
44		45
		46	/*
		47	* Max time with active RTS before/after data is sent.
		48	*/
		49	#define RS485_MAX_RTS_DELAY 100 /* msecs */
		50
45	static void uart_change_speed(struct tty_struct tty, struct uart_state state,	51	static void uart_change_speed(struct tty_struct tty, struct uart_state state,
46	struct ktermios *old_termios);	52	struct ktermios *old_termios);
47	static void uart_wait_until_sent(struct tty_struct *tty, int timeout);	53	static void uart_wait_until_sent(struct tty_struct *tty, int timeout);
@@ -333,15 +339,18 @@ void · 285 unmodified lines
333	uart_update_timeout(struct uart_port *port, unsigned int cflag,	339	uart_update_timeout(struct uart_port *port, unsigned int cflag,
334	unsigned int baud)	340	unsigned int baud)
335	{	341	{
336	unsigned int size;	342	unsigned int size = tty_get_frame_size(cflag);
		343	u64 frame_time;
337		344
338	size = tty_get_frame_size(cflag) * port->fifosize;	345	frame_time = (u64)size * NSEC_PER_SEC;
		346	size *= port->fifosize;
339		347
340	/*	348	/*
341	* Figure the timeout to send the above number of bits.	349	* Figure the timeout to send the above number of bits.
342	* Add .02 seconds of slop	350	* Add .02 seconds of slop
343	*/	351	*/
344	port->timeout = (HZ * size) / baud + HZ/50;	352	port->timeout = (HZ * size) / baud + HZ/50;
		353	port->frame_time = DIV64_U64_ROUND_UP(frame_time, baud);
345	}	354	}
346	EXPORT_SYMBOL(uart_update_timeout);	355	EXPORT_SYMBOL(uart_update_timeout);
347		356
@@ -1296,8 +1305,36 @@ static int uart_set_rs485_config(struct uart_port *port, · 948 unmodified lines
1296	if (copy_from_user(&rs485, rs485_user, sizeof(*rs485_user)))	1305	if (copy_from_user(&rs485, rs485_user, sizeof(*rs485_user)))
1297	return -EFAULT;	1306	return -EFAULT;
1298		1307
		1308	/* pick sane settings if the user hasn't */
		1309	if (!(rs485.flags & SER_RS485_RTS_ON_SEND) ==
		1310	!(rs485.flags & SER_RS485_RTS_AFTER_SEND)) {
		1311	dev_warn_ratelimited(port->dev,
		1312	"%s (%d): invalid RTS setting, using RTS_ON_SEND instead\n",
		1313	port->name, port->line);
		1314	rs485.flags \|= SER_RS485_RTS_ON_SEND;
		1315	rs485.flags &= ~SER_RS485_RTS_AFTER_SEND;
		1316	}
		1317
		1318	if (rs485.delay_rts_before_send > RS485_MAX_RTS_DELAY) {
		1319	rs485.delay_rts_before_send = RS485_MAX_RTS_DELAY;
		1320	dev_warn_ratelimited(port->dev,
		1321	"%s (%d): RTS delay before sending clamped to %u ms\n",
		1322	port->name, port->line, rs485.delay_rts_before_send);
		1323	}
		1324
		1325	if (rs485.delay_rts_after_send > RS485_MAX_RTS_DELAY) {
		1326	rs485.delay_rts_after_send = RS485_MAX_RTS_DELAY;
		1327	dev_warn_ratelimited(port->dev,
		1328	"%s (%d): RTS delay after sending clamped to %u ms\n",
		1329	port->name, port->line, rs485.delay_rts_after_send);
		1330	}
		1331	/* Return clean padding area to userspace */
		1332	memset(rs485.padding, 0, sizeof(rs485.padding));
		1333
1299	spin_lock_irqsave(&port->lock, flags);	1334	spin_lock_irqsave(&port->lock, flags);
1300	ret = port->rs485_config(port, &rs485);	1335	ret = port->rs485_config(port, &rs485);
		1336	if (!ret)
		1337	port->rs485 = rs485;
1301	spin_unlock_irqrestore(&port->lock, flags);	1338	spin_unlock_irqrestore(&port->lock, flags);
1302	if (ret)	1339	if (ret)
1303	return ret;	1340	return ret;
@@ -1610,24 +1647,24 @@ static void uart_wait_until_sent(struct tty_struct *tty, int timeout) · 306 unmodified lines
1610	* Note: we have to use pretty tight timings here to satisfy	1647	* Note: we have to use pretty tight timings here to satisfy
1611	* the NIST-PCTS.	1648	* the NIST-PCTS.
1612	*/	1649	*/
1613	char_time = (port->timeout - HZ/50) / port->fifosize;	1650	char_time = max(nsecs_to_jiffies(port->frame_time / 5), 1UL);
1614	char_time = char_time / 5;	1651
1615	if (char_time == 0)
1616	char_time = 1;
1617	if (timeout && timeout < char_time)	1652	if (timeout && timeout < char_time)
1618	char_time = timeout;	1653	char_time = timeout;
1619		1654
1620	/*	1655	if (!uart_cts_enabled(port)) {
1621	* If the transmitter hasn't cleared in twice the approximate	1656	/*
1622	* amount of time to send the entire FIFO, it probably won't	1657	* If the transmitter hasn't cleared in twice the approximate
1623	* ever clear. This assumes the UART isn't doing flow	1658	* amount of time to send the entire FIFO, it probably won't
1624	* control, which is currently the case. Hence, if it ever	1659	* ever clear. This assumes the UART isn't doing flow
1625	* takes longer than port->timeout, this is probably due to a	1660	* control, which is currently the case. Hence, if it ever
1626	* UART bug of some kind. So, we clamp the timeout parameter at	1661	* takes longer than port->timeout, this is probably due to a
1627	* 2*port->timeout.	1662	* UART bug of some kind. So, we clamp the timeout parameter at
1628	*/	1663	* 2*port->timeout.
1629	if (timeout == 0 \|\| timeout > 2 * port->timeout)	1664	*/
1630	timeout = 2 * port->timeout;	1665	if (timeout == 0 \|\| timeout > 2 * port->timeout)
		1666	timeout = 2 * port->timeout;
		1667	}
1631		1668
1632	expire = jiffies + timeout;	1669	expire = jiffies + timeout;
1633		1670
@@ -1643,7 +1680,7 @@ static void uart_wait_until_sent(struct tty_struct *tty, int timeout) · 9 unmodified lines
1643	msleep_interruptible(jiffies_to_msecs(char_time));	1680	msleep_interruptible(jiffies_to_msecs(char_time));
1644	if (signal_pending(current))	1681	if (signal_pending(current))
1645	break;	1682	break;
1646	if (time_after(jiffies, expire))	1683	if (timeout && time_after(jiffies, expire))
1647	break;	1684	break;
1648	}	1685	}
1649	uart_port_deref(port);	1686	uart_port_deref(port);
@@ -2174,15 +2211,23 @@ int uart_suspend_port(struct uart_driver drv, struct uart_port uport) · 524 unmodified lines
2174	}	2211	}
2175	put_device(tty_dev);	2212	put_device(tty_dev);
2176		2213
2177	/* Nothing to do if the console is not suspending */	2214	/*
2178	if (!console_suspend_enabled && uart_console(uport))	2215	* Nothing to do if the console is not suspending
		2216	* except stop_rx to prevent any asynchronous data
		2217	* over RX line. Re-start_rx, when required, is
		2218	* done by set_termios in resume sequence
		2219	*/
		2220	if (!console_suspend_enabled && uart_console(uport)) {
		2221	uport->ops->stop_rx(uport);
2179	goto unlock;	2222	goto unlock;
		2223	}
2180		2224
2181	uport->suspended = 1;	2225	uport->suspended = 1;
2182		2226
2183	if (tty_port_initialized(port)) {	2227	if (tty_port_initialized(port)) {
2184	const struct uart_ops *ops = uport->ops;	2228	const struct uart_ops *ops = uport->ops;
2185	int tries;	2229	int tries;
		2230	unsigned int mctrl;
2186		2231
2187	tty_port_set_suspended(port, 1);	2232	tty_port_set_suspended(port, 1);
2188	tty_port_set_initialized(port, 0);	2233	tty_port_set_initialized(port, 0);
@@ -2190,6 +2235,9 @@ int uart_suspend_port(struct uart_driver drv, struct uart_port uport) · 1 unmodified line
2190	spin_lock_irq(&uport->lock);	2235	spin_lock_irq(&uport->lock);
2191	ops->stop_tx(uport);	2236	ops->stop_tx(uport);
2192	ops->set_mctrl(uport, 0);	2237	ops->set_mctrl(uport, 0);
		2238	/* save mctrl so it can be restored on resume */
		2239	mctrl = uport->mctrl;
		2240	uport->mctrl = 0;
2193	ops->stop_rx(uport);	2241	ops->stop_rx(uport);
2194	spin_unlock_irq(&uport->lock);	2242	spin_unlock_irq(&uport->lock);
2195		2243
@@ -2203,6 +2251,7 @@ int uart_suspend_port(struct uart_driver drv, struct uart_port uport) · 7 unmodified lines
2203	uport->name);	2251	uport->name);
2204		2252
2205	ops->shutdown(uport);	2253	ops->shutdown(uport);
		2254	uport->mctrl = mctrl;
2206	}	2255	}
2207		2256
2208	/*	2257	/*

drivers/tty/serial/serial_txx9.c+2−0

@@ -618,6 +618,8 @@ serial_txx9_set_termios(struct uart_port up, struct ktermios termios, · 617 unmodified lines
618	case CS6: /* not supported */	618	case CS6: /* not supported */
619	case CS8:	619	case CS8:
620	cval \|= TXX9_SILCR_UMODE_8BIT;	620	cval \|= TXX9_SILCR_UMODE_8BIT;
		621	termios->c_cflag &= ~CSIZE;
		622	termios->c_cflag \|= CS8;
621	break;	623	break;
622	}	624	}
623		625

drivers/tty/serial/sh-sci.c+5−1

 	int best_clk = -1;
 	unsigned long flags;
-	if ((termios->c_cflag & CSIZE) == CS7)
+	if ((termios->c_cflag & CSIZE) == CS7) {
 		smr_val |= SCSMR_CHR;
+	} else {
+		termios->c_cflag &= ~CSIZE;
+		termios->c_cflag |= CS8;
+	}
 	if (termios->c_cflag & PARENB)
 		smr_val |= SCSMR_PE;
 	if (termios->c_cflag & PARODD)

drivers/tty/serial/sifive.c+11−9

  * @port: struct uart_port embedded in this struct
  * @dev: struct device *
  * @ier: shadowed copy of the interrupt enable register
- * @clkin_rate: input clock to the UART IP block.
  * @baud_rate: UART serial line rate (e.g., 115200 baud)
  * @clk: reference to this device's clock
  * @clk_notifier: clock rate change notifier for upstream clock changes
 	struct uart_port	port;
 	struct device		*dev;
 	unsigned char		ier;
-	unsigned long		clkin_rate;
 	unsigned long		baud_rate;
 	struct clk		*clk;
 	struct notifier_block	clk_notifier;
 {
 	u16 div;
-	div = DIV_ROUND_UP(ssp->clkin_rate, ssp->baud_rate) - 1;
+	div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1;
 	__ssp_writel(div, SIFIVE_SERIAL_DIV_OFFS, ssp);
 }
 		udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));
 	}
-	if (event == POST_RATE_CHANGE && ssp->clkin_rate != cnd->new_rate) {
+	if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) {
-		ssp->clkin_rate = cnd->new_rate;
+		ssp->port.uartclk = cnd->new_rate;
 		__ssp_update_div(ssp);
 	}
 	int rate;
 	char nstop;
-	if ((termios->c_cflag & CSIZE) != CS8)
+	if ((termios->c_cflag & CSIZE) != CS8) {
 		dev_err_once(ssp->port.dev, "only 8-bit words supported\n");
+		termios->c_cflag &= ~CSIZE;
+		termios->c_cflag |= CS8;
+	}
 	if (termios->c_iflag & (INPCK | PARMRK))
 		dev_err_once(ssp->port.dev, "parity checking not supported\n");
 	if (termios->c_iflag & BRKINT)
 		dev_err_once(ssp->port.dev, "BREAK detection not supported\n");
+	termios->c_iflag &= ~(INPCK|PARMRK|BRKINT);
 	/* Set number of stop bits */
 	nstop = (termios->c_cflag & CSTOPB) ? 2 : 1;
 	__ssp_set_stop_bits(ssp, nstop);
 	/* Set line rate */
-	rate = uart_get_baud_rate(port, termios, old, 0, ssp->clkin_rate / 16);
+	rate = uart_get_baud_rate(port, termios, old, 0,
+				  ssp->port.uartclk / 16);
 	__ssp_update_baud_rate(ssp, rate);
 	spin_lock_irqsave(&ssp->port.lock, flags);
 	}
 	/* Set up clock divider */
-	ssp->clkin_rate = clk_get_rate(ssp->clk);
+	ssp->port.uartclk = clk_get_rate(ssp->clk);
 	ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
-	ssp->port.uartclk = ssp->baud_rate * 16;
 	__ssp_update_div(ssp);
 	platform_set_drvdata(pdev, ssp);

drivers/tty/serial/st-asc.c+4−0

 	/* set character length */
 	if ((cflag & CSIZE) == CS7) {
 		ctrl_val |= ASC_CTL_MODE_7BIT_PAR;
+		cflag |= PARENB;
 	} else {
 		ctrl_val |= (cflag & PARENB) ?  ASC_CTL_MODE_8BIT_PAR :
 						ASC_CTL_MODE_8BIT;
+		cflag &= ~CSIZE;
+		cflag |= CS8;
 	}
+	termios->c_cflag = cflag;
 	/* set stop bit */
 	ctrl_val |= (cflag & CSTOPB) ? ASC_CTL_STOP_2BIT : ASC_CTL_STOP_1BIT;

drivers/tty/serial/stm32-usart.c+187−38

@@ -37,6 +37,7 @@ · 36 unmodified lines
37		37
38	static void stm32_usart_stop_tx(struct uart_port *port);	38	static void stm32_usart_stop_tx(struct uart_port *port);
39	static void stm32_usart_transmit_chars(struct uart_port *port);	39	static void stm32_usart_transmit_chars(struct uart_port *port);
		40	static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch);
40		41
41	static inline struct stm32_port to_stm32_port(struct uart_port port)	42	static inline struct stm32_port to_stm32_port(struct uart_port port)
42	{	43	{
@@ -107,8 +108,6 @@ static int stm32_usart_config_rs485(struct uart_port *port, · 64 unmodified lines
107		108
108	stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));	109	stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
109		110
110	port->rs485 = *rs485conf;
111
112	rs485conf->flags \|= SER_RS485_RX_DURING_TX;	111	rs485conf->flags \|= SER_RS485_RX_DURING_TX;
113		112
114	if (rs485conf->flags & SER_RS485_ENABLED) {	113	if (rs485conf->flags & SER_RS485_ENABLED) {
@@ -128,13 +127,10 @@ static int stm32_usart_config_rs485(struct uart_port *port, · 13 unmodified lines
128	rs485conf->delay_rts_after_send,	127	rs485conf->delay_rts_after_send,
129	baud);	128	baud);
130		129
131	if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {	130	if (rs485conf->flags & SER_RS485_RTS_ON_SEND)
132	cr3 &= ~USART_CR3_DEP;	131	cr3 &= ~USART_CR3_DEP;
133	rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;	132	else
134	} else {
135	cr3 \|= USART_CR3_DEP;	133	cr3 \|= USART_CR3_DEP;
136	rs485conf->flags \|= SER_RS485_RTS_AFTER_SEND;
137	}
138		134
139	writel_relaxed(cr3, port->membase + ofs->cr3);	135	writel_relaxed(cr3, port->membase + ofs->cr3);
140	writel_relaxed(cr1, port->membase + ofs->cr1);	136	writel_relaxed(cr1, port->membase + ofs->cr1);
@@ -421,6 +417,14 @@ static void stm32_usart_tx_interrupt_enable(struct uart_port *port) · 280 unmodified lines
421	stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);	417	stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
422	}	418	}
423		419
		420	static void stm32_usart_tc_interrupt_enable(struct uart_port *port)
		421	{
		422	struct stm32_port *stm32_port = to_stm32_port(port);
		423	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
		424
		425	stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE);
		426	}
		427
424	static void stm32_usart_rx_dma_complete(void *arg)	428	static void stm32_usart_rx_dma_complete(void *arg)
425	{	429	{
426	struct uart_port *port = arg;	430	struct uart_port *port = arg;
@@ -446,6 +450,50 @@ static void stm32_usart_tx_interrupt_disable(struct uart_port *port) · 19 unmodified lines
446	stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);	450	stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
447	}	451	}
448		452
		453	static void stm32_usart_tc_interrupt_disable(struct uart_port *port)
		454	{
		455	struct stm32_port *stm32_port = to_stm32_port(port);
		456	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
		457
		458	stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE);
		459	}
		460
		461	static void stm32_usart_rs485_rts_enable(struct uart_port *port)
		462	{
		463	struct stm32_port *stm32_port = to_stm32_port(port);
		464	struct serial_rs485 *rs485conf = &port->rs485;
		465
		466	if (stm32_port->hw_flow_control \|\|
		467	!(rs485conf->flags & SER_RS485_ENABLED))
		468	return;
		469
		470	if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
		471	mctrl_gpio_set(stm32_port->gpios,
		472	stm32_port->port.mctrl \| TIOCM_RTS);
		473	} else {
		474	mctrl_gpio_set(stm32_port->gpios,
		475	stm32_port->port.mctrl & ~TIOCM_RTS);
		476	}
		477	}
		478
		479	static void stm32_usart_rs485_rts_disable(struct uart_port *port)
		480	{
		481	struct stm32_port *stm32_port = to_stm32_port(port);
		482	struct serial_rs485 *rs485conf = &port->rs485;
		483
		484	if (stm32_port->hw_flow_control \|\|
		485	!(rs485conf->flags & SER_RS485_ENABLED))
		486	return;
		487
		488	if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
		489	mctrl_gpio_set(stm32_port->gpios,
		490	stm32_port->port.mctrl & ~TIOCM_RTS);
		491	} else {
		492	mctrl_gpio_set(stm32_port->gpios,
		493	stm32_port->port.mctrl \| TIOCM_RTS);
		494	}
		495	}
		496
449	static void stm32_usart_transmit_chars_pio(struct uart_port *port)	497	static void stm32_usart_transmit_chars_pio(struct uart_port *port)
450	{	498	{
451	struct stm32_port *stm32_port = to_stm32_port(port);	499	struct stm32_port *stm32_port = to_stm32_port(port);
@@ -553,6 +601,13 @@ static void stm32_usart_transmit_chars(struct uart_port *port) · 101 unmodified lines
553	u32 isr;	601	u32 isr;
554	int ret;	602	int ret;
555		603
		604	if (!stm32_port->hw_flow_control &&
		605	port->rs485.flags & SER_RS485_ENABLED) {
		606	stm32_port->txdone = false;
		607	stm32_usart_tc_interrupt_disable(port);
		608	stm32_usart_rs485_rts_enable(port);
		609	}
		610
556	if (port->x_char) {	611	if (port->x_char) {
557	if (stm32_usart_tx_dma_started(stm32_port) &&	612	if (stm32_usart_tx_dma_started(stm32_port) &&
558	stm32_usart_tx_dma_enabled(stm32_port))	613	stm32_usart_tx_dma_enabled(stm32_port))
@@ -593,8 +648,14 @@ static void stm32_usart_transmit_chars(struct uart_port *port) · 34 unmodified lines
593	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)	648	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
594	uart_write_wakeup(port);	649	uart_write_wakeup(port);
595		650
596	if (uart_circ_empty(xmit))	651	if (uart_circ_empty(xmit)) {
597	stm32_usart_tx_interrupt_disable(port);	652	stm32_usart_tx_interrupt_disable(port);
		653	if (!stm32_port->hw_flow_control &&
		654	port->rs485.flags & SER_RS485_ENABLED) {
		655	stm32_port->txdone = true;
		656	stm32_usart_tc_interrupt_enable(port);
		657	}
		658	}
598	}	659	}
599		660
600	static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)	661	static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
@@ -608,6 +669,13 @@ static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) · 7 unmodified lines
608		669
609	sr = readl_relaxed(port->membase + ofs->isr);	670	sr = readl_relaxed(port->membase + ofs->isr);
610		671
		672	if (!stm32_port->hw_flow_control &&
		673	port->rs485.flags & SER_RS485_ENABLED &&
		674	(sr & USART_SR_TC)) {
		675	stm32_usart_tc_interrupt_disable(port);
		676	stm32_usart_rs485_rts_disable(port);
		677	}
		678
611	if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)	679	if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
612	writel_relaxed(USART_ICR_RTOCF,	680	writel_relaxed(USART_ICR_RTOCF,
613	port->membase + ofs->icr);	681	port->membase + ofs->icr);
@@ -717,44 +785,27 @@ static void stm32_usart_disable_ms(struct uart_port *port) · 103 unmodified lines
717	static void stm32_usart_stop_tx(struct uart_port *port)	785	static void stm32_usart_stop_tx(struct uart_port *port)
718	{	786	{
719	struct stm32_port *stm32_port = to_stm32_port(port);	787	struct stm32_port *stm32_port = to_stm32_port(port);
720	struct serial_rs485 *rs485conf = &port->rs485;
721	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;	788	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
722		789
723	stm32_usart_tx_interrupt_disable(port);	790	stm32_usart_tx_interrupt_disable(port);
724	if (stm32_usart_tx_dma_started(stm32_port) && stm32_usart_tx_dma_enabled(stm32_port))	791	if (stm32_usart_tx_dma_started(stm32_port) && stm32_usart_tx_dma_enabled(stm32_port))
725	stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);	792	stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
726		793
727	if (rs485conf->flags & SER_RS485_ENABLED) {	794	stm32_usart_rs485_rts_disable(port);
728	if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
729	mctrl_gpio_set(stm32_port->gpios,
730	stm32_port->port.mctrl & ~TIOCM_RTS);
731	} else {
732	mctrl_gpio_set(stm32_port->gpios,
733	stm32_port->port.mctrl \| TIOCM_RTS);
734	}
735	}
736	}	795	}
737		796
738	/* There are probably characters waiting to be transmitted. */	797	/* There are probably characters waiting to be transmitted. */
739	static void stm32_usart_start_tx(struct uart_port *port)	798	static void stm32_usart_start_tx(struct uart_port *port)
740	{	799	{
741	struct stm32_port *stm32_port = to_stm32_port(port);
742	struct serial_rs485 *rs485conf = &port->rs485;
743	struct circ_buf *xmit = &port->state->xmit;	800	struct circ_buf *xmit = &port->state->xmit;
744		801
745	if (uart_circ_empty(xmit) && !port->x_char)	802	if (uart_circ_empty(xmit) && !port->x_char) {
		803	stm32_usart_rs485_rts_disable(port);
746	return;	804	return;
747
748	if (rs485conf->flags & SER_RS485_ENABLED) {
749	if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
750	mctrl_gpio_set(stm32_port->gpios,
751	stm32_port->port.mctrl \| TIOCM_RTS);
752	} else {
753	mctrl_gpio_set(stm32_port->gpios,
754	stm32_port->port.mctrl & ~TIOCM_RTS);
755	}
756	}	805	}
757		806
		807	stm32_usart_rs485_rts_enable(port);
		808
758	stm32_usart_transmit_chars(port);	809	stm32_usart_transmit_chars(port);
759	}	810	}
760		811
@@ -1037,13 +1088,22 @@ static void stm32_usart_set_termios(struct uart_port *port, · 276 unmodified lines
1037	* CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00	1088	* CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
1038	* M0 and M1 already cleared by cr1 initialization.	1089	* M0 and M1 already cleared by cr1 initialization.
1039	*/	1090	*/
1040	if (bits == 9)	1091	if (bits == 9) {
1041	cr1 \|= USART_CR1_M0;	1092	cr1 \|= USART_CR1_M0;
1042	else if ((bits == 7) && cfg->has_7bits_data)	1093	} else if ((bits == 7) && cfg->has_7bits_data) {
1043	cr1 \|= USART_CR1_M1;	1094	cr1 \|= USART_CR1_M1;
1044	else if (bits != 8)	1095	} else if (bits != 8) {
1045	dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"	1096	dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
1046	, bits);	1097	, bits);
		1098	cflag &= ~CSIZE;
		1099	cflag \|= CS8;
		1100	termios->c_cflag = cflag;
		1101	bits = 8;
		1102	if (cflag & PARENB) {
		1103	bits++;
		1104	cr1 \|= USART_CR1_M0;
		1105	}
		1106	}
1047		1107
1048	if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch \|\|	1108	if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch \|\|
1049	(stm32_port->fifoen &&	1109	(stm32_port->fifoen &&
@@ -1222,6 +1282,33 @@ static void stm32_usart_pm(struct uart_port *port, unsigned int state, · 172 unmodified lines
1222	}	1282	}
1223	}	1283	}
1224		1284
		1285	#if defined(CONFIG_CONSOLE_POLL)
		1286
		1287	/* Callbacks for characters polling in debug context (i.e. KGDB). */
		1288	static int stm32_usart_poll_init(struct uart_port *port)
		1289	{
		1290	struct stm32_port *stm32_port = to_stm32_port(port);
		1291
		1292	return clk_prepare_enable(stm32_port->clk);
		1293	}
		1294
		1295	static int stm32_usart_poll_get_char(struct uart_port *port)
		1296	{
		1297	struct stm32_port *stm32_port = to_stm32_port(port);
		1298	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
		1299
		1300	if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE))
		1301	return NO_POLL_CHAR;
		1302
		1303	return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask;
		1304	}
		1305
		1306	static void stm32_usart_poll_put_char(struct uart_port *port, unsigned char ch)
		1307	{
		1308	stm32_usart_console_putchar(port, ch);
		1309	}
		1310	#endif /* CONFIG_CONSOLE_POLL */
		1311
1225	static const struct uart_ops stm32_uart_ops = {	1312	static const struct uart_ops stm32_uart_ops = {
1226	.tx_empty = stm32_usart_tx_empty,	1313	.tx_empty = stm32_usart_tx_empty,
1227	.set_mctrl = stm32_usart_set_mctrl,	1314	.set_mctrl = stm32_usart_set_mctrl,
@@ -1243,6 +1330,11 @@ static const struct uart_ops stm32_uart_ops = { · 15 unmodified lines
1243	.request_port = stm32_usart_request_port,	1330	.request_port = stm32_usart_request_port,
1244	.config_port = stm32_usart_config_port,	1331	.config_port = stm32_usart_config_port,
1245	.verify_port = stm32_usart_verify_port,	1332	.verify_port = stm32_usart_verify_port,
		1333	#if defined(CONFIG_CONSOLE_POLL)
		1334	.poll_init = stm32_usart_poll_init,
		1335	.poll_get_char = stm32_usart_poll_get_char,
		1336	.poll_put_char = stm32_usart_poll_put_char,
		1337	#endif /* CONFIG_CONSOLE_POLL */
1246	};	1338	};
1247		1339
1248	/*	1340	/*
@@ -1640,18 +1732,24 @@ static int stm32_usart_serial_remove(struct platform_device *pdev) · 391 unmodified lines
1640	return 0;	1732	return 0;
1641	}	1733	}
1642		1734
1643	#ifdef CONFIG_SERIAL_STM32_CONSOLE	1735	static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1644	static void stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1645	{	1736	{
1646	struct stm32_port *stm32_port = to_stm32_port(port);	1737	struct stm32_port *stm32_port = to_stm32_port(port);
1647	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;	1738	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
		1739	u32 isr;
		1740	int ret;
1648		1741
1649	while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))	1742	ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr,
1650	cpu_relax();	1743	(isr & USART_SR_TXE), 100,
1651		1744	STM32_USART_TIMEOUT_USEC);
		1745	if (ret != 0) {
		1746	dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret);
		1747	return;
		1748	}
1652	writel_relaxed(ch, port->membase + ofs->tdr);	1749	writel_relaxed(ch, port->membase + ofs->tdr);
1653	}	1750	}
1654		1751
		1752	#ifdef CONFIG_SERIAL_STM32_CONSOLE
1655	static void stm32_usart_console_write(struct console co, const char s,	1753	static void stm32_usart_console_write(struct console co, const char s,
1656	unsigned int cnt)	1754	unsigned int cnt)
1657	{	1755	{
@@ -1727,6 +1825,57 @@ static struct console stm32_console = { · 69 unmodified lines
1727	#define STM32_SERIAL_CONSOLE NULL	1825	#define STM32_SERIAL_CONSOLE NULL
1728	#endif /* CONFIG_SERIAL_STM32_CONSOLE */	1826	#endif /* CONFIG_SERIAL_STM32_CONSOLE */
1729		1827
		1828	#ifdef CONFIG_SERIAL_EARLYCON
		1829	static void early_stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
		1830	{
		1831	struct stm32_usart_info *info = port->private_data;
		1832
		1833	while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE))
		1834	cpu_relax();
		1835
		1836	writel_relaxed(ch, port->membase + info->ofs.tdr);
		1837	}
		1838
		1839	static void early_stm32_serial_write(struct console console, const char s, unsigned int count)
		1840	{
		1841	struct earlycon_device *device = console->data;
		1842	struct uart_port *port = &device->port;
		1843
		1844	uart_console_write(port, s, count, early_stm32_usart_console_putchar);
		1845	}
		1846
		1847	static int __init early_stm32_h7_serial_setup(struct earlycon_device device, const char options)
		1848	{
		1849	if (!(device->port.membase \|\| device->port.iobase))
		1850	return -ENODEV;
		1851	device->port.private_data = &stm32h7_info;
		1852	device->con->write = early_stm32_serial_write;
		1853	return 0;
		1854	}
		1855
		1856	static int __init early_stm32_f7_serial_setup(struct earlycon_device device, const char options)
		1857	{
		1858	if (!(device->port.membase \|\| device->port.iobase))
		1859	return -ENODEV;
		1860	device->port.private_data = &stm32f7_info;
		1861	device->con->write = early_stm32_serial_write;
		1862	return 0;
		1863	}
		1864
		1865	static int __init early_stm32_f4_serial_setup(struct earlycon_device device, const char options)
		1866	{
		1867	if (!(device->port.membase \|\| device->port.iobase))
		1868	return -ENODEV;
		1869	device->port.private_data = &stm32f4_info;
		1870	device->con->write = early_stm32_serial_write;
		1871	return 0;
		1872	}
		1873
		1874	OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup);
		1875	OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup);
		1876	OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup);
		1877	#endif /* CONFIG_SERIAL_EARLYCON */
		1878
1730	static struct uart_driver stm32_usart_driver = {	1879	static struct uart_driver stm32_usart_driver = {
1731	.driver_name = DRIVER_NAME,	1880	.driver_name = DRIVER_NAME,
1732	.dev_name = STM32_SERIAL_NAME,	1881	.dev_name = STM32_SERIAL_NAME,

drivers/tty/serial/stm32-usart.h+3−0

 #define RX_BUF_P (RX_BUF_L / 2)	 /* dma rx buffer period     */
 #define TX_BUF_L RX_BUF_L	 /* dma tx buffer length     */
+#define STM32_USART_TIMEOUT_USEC USEC_PER_SEC /* 1s timeout in µs */
 struct stm32_port {
 	struct uart_port port;
 	struct clk *clk;
 	bool hw_flow_control;
 	bool swap;		 /* swap RX & TX pins */
 	bool fifoen;
+	bool txdone;
 	int rxftcfg;		/* RX FIFO threshold CFG      */
 	int txftcfg;		/* TX FIFO threshold CFG      */
 	bool wakeup_src;

drivers/tty/serial/sunplus-uart.c+1−1

@@ -498,7 +498,7 @@ static const struct uart_ops sunplus_uart_ops = { · 497 unmodified lines
498	};	498	};
499		499
500	#ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE	500	#ifdef CONFIG_SERIAL_SUNPLUS_CONSOLE
501	struct sunplus_uart_port *sunplus_console_ports[SUP_UART_NR];	501	static struct sunplus_uart_port *sunplus_console_ports[SUP_UART_NR];
502		502
503	static void sunplus_uart_console_putchar(struct uart_port *port,	503	static void sunplus_uart_console_putchar(struct uart_port *port,
504	unsigned char ch)	504	unsigned char ch)

drivers/tty/serial/sunsu.c+0−2

 		cval |= UART_LCR_PARITY;
 	if (!(cflag & PARODD))
 		cval |= UART_LCR_EPAR;
-#ifdef CMSPAR
 	if (cflag & CMSPAR)
 		cval |= UART_LCR_SPAR;
-#endif
 	/*
 	 * Work around a bug in the Oxford Semiconductor 952 rev B

drivers/tty/serial/uartlite.c+2−1

@@ -321,7 +321,8 @@ static void ulite_set_termios(struct uart_port port, struct ktermios termios, · 320 unmodified lines
321	struct uartlite_data *pdata = port->private_data;	321	struct uartlite_data *pdata = port->private_data;
322		322
323	/* Set termios to what the hardware supports */	323	/* Set termios to what the hardware supports */
324	termios->c_cflag &= ~(BRKINT \| CSTOPB \| PARENB \| PARODD \| CSIZE);	324	termios->c_iflag &= ~BRKINT;
		325	termios->c_cflag &= ~(CSTOPB \| PARENB \| PARODD \| CSIZE);
325	termios->c_cflag \|= pdata->cflags & (PARENB \| PARODD \| CSIZE);	326	termios->c_cflag \|= pdata->cflags & (PARENB \| PARODD \| CSIZE);
326	tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud);	327	tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud);
327		328

drivers/tty/serial/xilinx_uartps.c+16−30

 static void cdns_uart_handle_tx(void *dev_id)
 {
 	struct uart_port *port = (struct uart_port *)dev_id;
+	struct circ_buf *xmit = &port->state->xmit;
 	unsigned int numbytes;
-	if (uart_circ_empty(&port->state->xmit)) {
+	if (uart_circ_empty(xmit)) {
 		writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
-	} else {
+		return;
-		numbytes = port->fifosize;
+	}
-		while (numbytes && !uart_circ_empty(&port->state->xmit) &&
-		       !(readl(port->membase + CDNS_UART_SR) &
-						CDNS_UART_SR_TXFULL)) {
-			/*
-			 * Get the data from the UART circular buffer
-			 * and write it to the cdns_uart's TX_FIFO
-			 * register.
-			 */
-			writel(
-				port->state->xmit.buf[port->state->xmit.tail],
-					port->membase + CDNS_UART_FIFO);
-			port->icount.tx++;
-			/*
-			 * Adjust the tail of the UART buffer and wrap
-			 * the buffer if it reaches limit.
-			 */
-			port->state->xmit.tail =
-				(port->state->xmit.tail + 1) &
-					(UART_XMIT_SIZE - 1);
-			numbytes--;
-		}
-		if (uart_circ_chars_pending(
+	numbytes = port->fifosize;
-				&port->state->xmit) < WAKEUP_CHARS)
+	while (numbytes && !uart_circ_empty(xmit) &&
-			uart_write_wakeup(port);
+	       !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
+		writel(xmit->buf[xmit->tail], port->membase + CDNS_UART_FIFO);
+		port->icount.tx++;
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		numbytes--;
 	}
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
 }
 /**

drivers/tty/serial/zs.c+1−1

@@ -981,7 +981,7 @@ static const char zs_type(struct uart_port uport) · 980 unmodified lines
981	static void zs_release_port(struct uart_port *uport)	981	static void zs_release_port(struct uart_port *uport)
982	{	982	{
983	iounmap(uport->membase);	983	iounmap(uport->membase);
984	uport->membase = 0;	984	uport->membase = NULL;
985	release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);	985	release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
986	}	986	}
987		987

drivers/tty/synclink_gt.c+2−0

  */
 static void hdlcdev_exit(struct slgt_info *info)
 {
+	if (!info->netdev)
+		return;
 	unregister_hdlc_device(info->netdev);
 	free_netdev(info->netdev);
 	info->netdev = NULL;

drivers/tty/sysrq.c+15−12

@@ -232,8 +232,10 @@ static void showacpu(void *dummy) · 231 unmodified lines
232	unsigned long flags;	232	unsigned long flags;
233		233
234	/* Idle CPUs have no interesting backtrace. */	234	/* Idle CPUs have no interesting backtrace. */
235	if (idle_cpu(smp_processor_id()))	235	if (idle_cpu(smp_processor_id())) {
		236	pr_info("CPU%d: backtrace skipped as idling\n", smp_processor_id());
236	return;	237	return;
		238	}
237		239
238	raw_spin_lock_irqsave(&show_lock, flags);	240	raw_spin_lock_irqsave(&show_lock, flags);
239	pr_info("CPU%d:\n", smp_processor_id());	241	pr_info("CPU%d:\n", smp_processor_id());
@@ -260,10 +262,13 @@ static void sysrq_handle_showallcpus(int key) · 20 unmodified lines
260		262
261	if (in_hardirq())	263	if (in_hardirq())
262	regs = get_irq_regs();	264	regs = get_irq_regs();
263	if (regs) {	265
264	pr_info("CPU%d:\n", smp_processor_id());	266	pr_info("CPU%d:\n", smp_processor_id());
		267	if (regs)
265	show_regs(regs);	268	show_regs(regs);
266	}	269	else
		270	show_stack(NULL, NULL, KERN_INFO);
		271
267	schedule_work(&sysrq_showallcpus);	272	schedule_work(&sysrq_showallcpus);
268	}	273	}
269	}	274	}
@@ -274,6 +279,8 @@ static const struct sysrq_key_op sysrq_showallcpus_op = { · 4 unmodified lines
274	.action_msg = "Show backtrace of all active CPUs",	279	.action_msg = "Show backtrace of all active CPUs",
275	.enable_mask = SYSRQ_ENABLE_DUMP,	280	.enable_mask = SYSRQ_ENABLE_DUMP,
276	};	281	};
		282	#else
		283	#define sysrq_showallcpus_op ((const struct sysrq_key_op )NULL)
277	#endif	284	#endif
278		285
279	static void sysrq_handle_showregs(int key)	286	static void sysrq_handle_showregs(int key)
@@ -405,6 +412,7 @@ static const struct sysrq_key_op sysrq_moom_op = { · 125 unmodified lines
405	.enable_mask = SYSRQ_ENABLE_SIGNAL,	412	.enable_mask = SYSRQ_ENABLE_SIGNAL,
406	};	413	};
407		414
		415	#ifdef CONFIG_BLOCK
408	static void sysrq_handle_thaw(int key)	416	static void sysrq_handle_thaw(int key)
409	{	417	{
410	emergency_thaw_all();	418	emergency_thaw_all();
@@ -415,6 +423,9 @@ static const struct sysrq_key_op sysrq_thaw_op = { · 4 unmodified lines
415	.action_msg = "Emergency Thaw of all frozen filesystems",	423	.action_msg = "Emergency Thaw of all frozen filesystems",
416	.enable_mask = SYSRQ_ENABLE_SIGNAL,	424	.enable_mask = SYSRQ_ENABLE_SIGNAL,
417	};	425	};
		426	#else
		427	#define sysrq_thaw_op ((const struct sysrq_key_op )NULL)
		428	#endif
418		429
419	static void sysrq_handle_kill(int key)	430	static void sysrq_handle_kill(int key)
420	{	431	{
@@ -468,17 +479,9 @@ static const struct sysrq_key_op *sysrq_key_table[62] = { · 47 unmodified lines
468	NULL, /* g */	479	NULL, /* g */
469	NULL, /* h - reserved for help */	480	NULL, /* h - reserved for help */
470	&sysrq_kill_op, /* i */	481	&sysrq_kill_op, /* i */
471	#ifdef CONFIG_BLOCK
472	&sysrq_thaw_op, /* j */	482	&sysrq_thaw_op, /* j */
473	#else
474	NULL, /* j */
475	#endif
476	&sysrq_SAK_op, /* k */	483	&sysrq_SAK_op, /* k */
477	#ifdef CONFIG_SMP
478	&sysrq_showallcpus_op, /* l */	484	&sysrq_showallcpus_op, /* l */
479	#else
480	NULL, /* l */
481	#endif
482	&sysrq_showmem_op, /* m */	485	&sysrq_showmem_op, /* m */
483	&sysrq_unrt_op, /* n */	486	&sysrq_unrt_op, /* n */
484	/* o: This will often be registered as 'Off' at init time */	487	/* o: This will often be registered as 'Off' at init time */

drivers/tty/tty_baudrate.c+8−27

@@ -61,11 +61,10 @@ speed_t tty_termios_baud_rate(struct ktermios *termios) · 60 unmodified lines
61		61
62	cbaud = termios->c_cflag & CBAUD;	62	cbaud = termios->c_cflag & CBAUD;
63		63
64	#ifdef BOTHER
65	/* Magic token for arbitrary speed via c_ispeed/c_ospeed */	64	/* Magic token for arbitrary speed via c_ispeed/c_ospeed */
66	if (cbaud == BOTHER)	65	if (cbaud == BOTHER)
67	return termios->c_ospeed;	66	return termios->c_ospeed;
68	#endif	67
69	if (cbaud & CBAUDEX) {	68	if (cbaud & CBAUDEX) {
70	cbaud &= ~CBAUDEX;	69	cbaud &= ~CBAUDEX;
71		70
@@ -92,16 +91,15 @@ EXPORT_SYMBOL(tty_termios_baud_rate); · 20 unmodified lines
92		91
93	speed_t tty_termios_input_baud_rate(struct ktermios *termios)	92	speed_t tty_termios_input_baud_rate(struct ktermios *termios)
94	{	93	{
95	#ifdef IBSHIFT
96	unsigned int cbaud = (termios->c_cflag >> IBSHIFT) & CBAUD;	94	unsigned int cbaud = (termios->c_cflag >> IBSHIFT) & CBAUD;
97		95
98	if (cbaud == B0)	96	if (cbaud == B0)
99	return tty_termios_baud_rate(termios);	97	return tty_termios_baud_rate(termios);
100	#ifdef BOTHER	98
101	/* Magic token for arbitrary speed via c_ispeed*/	99	/* Magic token for arbitrary speed via c_ispeed*/
102	if (cbaud == BOTHER)	100	if (cbaud == BOTHER)
103	return termios->c_ispeed;	101	return termios->c_ispeed;
104	#endif	102
105	if (cbaud & CBAUDEX) {	103	if (cbaud & CBAUDEX) {
106	cbaud &= ~CBAUDEX;	104	cbaud &= ~CBAUDEX;
107		105
@@ -111,9 +109,6 @@ speed_t tty_termios_input_baud_rate(struct ktermios *termios) · 3 unmodified lines
111	cbaud += 15;	109	cbaud += 15;
112	}	110	}
113	return cbaud >= n_baud_table ? 0 : baud_table[cbaud];	111	return cbaud >= n_baud_table ? 0 : baud_table[cbaud];
114	#else /* IBSHIFT */
115	return tty_termios_baud_rate(termios);
116	#endif /* IBSHIFT */
117	}	112	}
118	EXPORT_SYMBOL(tty_termios_input_baud_rate);	113	EXPORT_SYMBOL(tty_termios_input_baud_rate);
119		114
@@ -153,11 +148,9 @@ void tty_termios_encode_baud_rate(struct ktermios *termios, · 33 unmodified lines
153	termios->c_ispeed = ibaud;	148	termios->c_ispeed = ibaud;
154	termios->c_ospeed = obaud;	149	termios->c_ospeed = obaud;
155		150
156	#ifdef IBSHIFT
157	if (((termios->c_cflag >> IBSHIFT) & CBAUD) != B0)	151	if (((termios->c_cflag >> IBSHIFT) & CBAUD) != B0)
158	ibinput = 1; /* An input speed was specified */	152	ibinput = 1; /* An input speed was specified */
159	#endif	153
160	#ifdef BOTHER
161	/* If the user asked for a precise weird speed give a precise weird	154	/* If the user asked for a precise weird speed give a precise weird
162	* answer. If they asked for a Bfoo speed they may have problems	155	* answer. If they asked for a Bfoo speed they may have problems
163	* digesting non-exact replies so fuzz a bit.	156	* digesting non-exact replies so fuzz a bit.
@@ -170,11 +163,9 @@ void tty_termios_encode_baud_rate(struct ktermios *termios, · 6 unmodified lines
170	}	163	}
171	if (((termios->c_cflag >> IBSHIFT) & CBAUD) == BOTHER)	164	if (((termios->c_cflag >> IBSHIFT) & CBAUD) == BOTHER)
172	iclose = 0;	165	iclose = 0;
173	#endif	166
174	termios->c_cflag &= ~CBAUD;	167	termios->c_cflag &= ~CBAUD;
175	#ifdef IBSHIFT
176	termios->c_cflag &= ~(CBAUD << IBSHIFT);	168	termios->c_cflag &= ~(CBAUD << IBSHIFT);
177	#endif
178		169
179	/*	170	/*
180	* Our goal is to find a close match to the standard baud rate	171	* Our goal is to find a close match to the standard baud rate
@@ -194,22 +185,16 @@ void tty_termios_encode_baud_rate(struct ktermios *termios, · 13 unmodified lines
194	/* For the case input == output don't set IBAUD bits	185	/* For the case input == output don't set IBAUD bits
195	* if the user didn't do so.	186	* if the user didn't do so.
196	*/	187	*/
197	if (ofound == i && !ibinput)	188	if (ofound == i && !ibinput) {
198	ifound = i;	189	ifound = i;
199	#ifdef IBSHIFT	190	} else {
200	else {
201	ifound = i;	191	ifound = i;
202	termios->c_cflag \|= (baud_bits[i] << IBSHIFT);	192	termios->c_cflag \|= (baud_bits[i] << IBSHIFT);
203	}	193	}
204	#endif
205	}	194	}
206	} while (++i < n_baud_table);	195	} while (++i < n_baud_table);
207		196
208	/*	197	/* If we found no match then use BOTHER. */
209	* If we found no match then use BOTHER if provided or warn
210	* the user their platform maintainer needs to wake up if not.
211	*/
212	#ifdef BOTHER
213	if (ofound == -1)	198	if (ofound == -1)
214	termios->c_cflag \|= BOTHER;	199	termios->c_cflag \|= BOTHER;
215	/* Set exact input bits only if the input and output differ or the	200	/* Set exact input bits only if the input and output differ or the
@@ -217,10 +202,6 @@ void tty_termios_encode_baud_rate(struct ktermios *termios, · 1 unmodified line
217	*/	202	*/
218	if (ifound == -1 && (ibaud != obaud \|\| ibinput))	203	if (ifound == -1 && (ibaud != obaud \|\| ibinput))
219	termios->c_cflag \|= (BOTHER << IBSHIFT);	204	termios->c_cflag \|= (BOTHER << IBSHIFT);
220	#else
221	if (ifound == -1 \|\| ofound == -1)
222	pr_warn_once("tty: Unable to return correct speed data as your architecture needs updating.\n");
223	#endif
224	}	205	}
225	EXPORT_SYMBOL_GPL(tty_termios_encode_baud_rate);	206	EXPORT_SYMBOL_GPL(tty_termios_encode_baud_rate);
226		207

drivers/tty/tty_ioctl.c+0−2

 	termios.c_cc[VKILL] = tmp.sg_kill;
 	set_sgflags(&termios, tmp.sg_flags);
 	/* Try and encode into Bfoo format */
-#ifdef BOTHER
 	tty_termios_encode_baud_rate(&termios, termios.c_ispeed,
 						termios.c_ospeed);
-#endif
 	up_write(&tty->termios_rwsem);
 	tty_set_termios(tty, &termios);
 	return 0;

drivers/usb/class/cdc-acm.h+0−8

@@ -7,14 +7,6 @@ · 6 unmodified lines
7	*	7	*
8	*/	8	*/
9		9
10	/*
11	* CMSPAR, some architectures can't have space and mark parity.
12	*/
13
14	#ifndef CMSPAR
15	#define CMSPAR 0
16	#endif
17
18	/*	10	/*
19	* Major and minor numbers.	11	* Major and minor numbers.
20	*/	12	*/

drivers/usb/serial/ark3116.c+1−2

@@ -208,10 +208,9 @@ static void ark3116_set_termios(struct tty_struct *tty, · 207 unmodified lines
208	lcr \|= UART_LCR_PARITY;	208	lcr \|= UART_LCR_PARITY;
209	if (!(cflag & PARODD))	209	if (!(cflag & PARODD))
210	lcr \|= UART_LCR_EPAR;	210	lcr \|= UART_LCR_EPAR;
211	#ifdef CMSPAR
212	if (cflag & CMSPAR)	211	if (cflag & CMSPAR)
213	lcr \|= UART_LCR_SPAR;	212	lcr \|= UART_LCR_SPAR;
214	#endif	213
215	/* handshake control */	214	/* handshake control */
216	hcr = (cflag & CRTSCTS) ? 0x03 : 0x00;	215	hcr = (cflag & CRTSCTS) ? 0x03 : 0x00;
217		216

drivers/usb/serial/whiteheat.c+0−4

 #include <linux/usb/ezusb.h>
 #include "whiteheat.h"			/* WhiteHEAT specific commands */
-#ifndef CMSPAR
-#define CMSPAR 0
-#endif
 /*
  * Version Information
  */

include/linux/serial_core.h+1−0

@@ -232,6 +232,7 @@ struct uart_port { · 231 unmodified lines
232	int hw_stopped; /* sw-assisted CTS flow state */	232	int hw_stopped; /* sw-assisted CTS flow state */
233	unsigned int mctrl; /* current modem ctrl settings */	233	unsigned int mctrl; /* current modem ctrl settings */
234	unsigned int timeout; /* character-based timeout */	234	unsigned int timeout; /* character-based timeout */
		235	unsigned int frame_time; /* frame timing in ns */
235	unsigned int type; /* port type */	236	unsigned int type; /* port type */
236	const struct uart_ops *ops;	237	const struct uart_ops *ops;
237	unsigned int custom_divisor;	238	unsigned int custom_divisor;

include/linux/serial_s3c.h+3−0

 #define APPLE_S5L_UCON_DEFAULT		(S3C2410_UCON_TXIRQMODE | \
 					 S3C2410_UCON_RXIRQMODE | \
 					 S3C2410_UCON_RXFIFO_TOI)
+#define APPLE_S5L_UCON_MASK		(APPLE_S5L_UCON_RXTO_ENA_MSK | \
+					 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \
+					 APPLE_S5L_UCON_TXTHRESH_ENA_MSK)
 #define APPLE_S5L_UTRSTAT_RXTHRESH	(1<<4)
 #define APPLE_S5L_UTRSTAT_TXTHRESH	(1<<5)

include/uapi/asm-generic/termbits-common.h+65−0

@@ -0,0 +1,65 @@
	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
	2	#ifndef __ASM_GENERIC_TERMBITS_COMMON_H
	3	#define __ASM_GENERIC_TERMBITS_COMMON_H
	4
	5	typedef unsigned char cc_t;
	6	typedef unsigned int speed_t;
	7
	8	/* c_iflag bits */
	9	#define IGNBRK 0x001 /* Ignore break condition */
	10	#define BRKINT 0x002 /* Signal interrupt on break */
	11	#define IGNPAR 0x004 /* Ignore characters with parity errors */
	12	#define PARMRK 0x008 /* Mark parity and framing errors */
	13	#define INPCK 0x010 /* Enable input parity check */
	14	#define ISTRIP 0x020 /* Strip 8th bit off characters */
	15	#define INLCR 0x040 /* Map NL to CR on input */
	16	#define IGNCR 0x080 /* Ignore CR */
	17	#define ICRNL 0x100 /* Map CR to NL on input */
	18	#define IXANY 0x800 /* Any character will restart after stop */
	19
	20	/* c_oflag bits */
	21	#define OPOST 0x01 /* Perform output processing */
	22	#define OCRNL 0x08
	23	#define ONOCR 0x10
	24	#define ONLRET 0x20
	25	#define OFILL 0x40
	26	#define OFDEL 0x80
	27
	28	/* c_cflag bit meaning */
	29	/* Common CBAUD rates */
	30	#define B0 0x00000000 /* hang up */
	31	#define B50 0x00000001
	32	#define B75 0x00000002
	33	#define B110 0x00000003
	34	#define B134 0x00000004
	35	#define B150 0x00000005
	36	#define B200 0x00000006
	37	#define B300 0x00000007
	38	#define B600 0x00000008
	39	#define B1200 0x00000009
	40	#define B1800 0x0000000a
	41	#define B2400 0x0000000b
	42	#define B4800 0x0000000c
	43	#define B9600 0x0000000d
	44	#define B19200 0x0000000e
	45	#define B38400 0x0000000f
	46	#define EXTA B19200
	47	#define EXTB B38400
	48
	49	#define CMSPAR 0x40000000 /* mark or space (stick) parity */
	50	#define CRTSCTS 0x80000000 /* flow control */
	51
	52	#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
	53
	54	/* tcflow() ACTION argument and TCXONC use these */
	55	#define TCOOFF 0 /* Suspend output */
	56	#define TCOON 1 /* Restart suspended output */
	57	#define TCIOFF 2 /* Send a STOP character */
	58	#define TCION 3 /* Send a START character */
	59
	60	/* tcflush() QUEUE_SELECTOR argument and TCFLSH use these */
	61	#define TCIFLUSH 0 /* Discard data received but not yet read */
	62	#define TCOFLUSH 1 /* Discard data written but not yet sent */
	63	#define TCIOFLUSH 2 /* Discard all pending data */
	64
	65	#endif /* __ASM_GENERIC_TERMBITS_COMMON_H */

include/uapi/asm-generic/termbits.h+94−145

@@ -2,10 +2,8 @@ · 1 unmodified line
2	#ifndef __ASM_GENERIC_TERMBITS_H	2	#ifndef __ASM_GENERIC_TERMBITS_H
3	#define __ASM_GENERIC_TERMBITS_H	3	#define __ASM_GENERIC_TERMBITS_H
4		4
5	#include <linux/posix_types.h>	5	#include <asm-generic/termbits-common.h>
6		6
7	typedef unsigned char cc_t;
8	typedef unsigned int speed_t;
9	typedef unsigned int tcflag_t;	7	typedef unsigned int tcflag_t;
10		8
11	#define NCCS 19	9	#define NCCS 19
@@ -41,156 +39,107 @@ struct ktermios { · 29 unmodified lines
41	};	39	};
42		40
43	/* c_cc characters */	41	/* c_cc characters */
44	#define VINTR 0	42	#define VINTR 0
45	#define VQUIT 1	43	#define VQUIT 1
46	#define VERASE 2	44	#define VERASE 2
47	#define VKILL 3	45	#define VKILL 3
48	#define VEOF 4	46	#define VEOF 4
49	#define VTIME 5	47	#define VTIME 5
50	#define VMIN 6	48	#define VMIN 6
51	#define VSWTC 7	49	#define VSWTC 7
52	#define VSTART 8	50	#define VSTART 8
53	#define VSTOP 9	51	#define VSTOP 9
54	#define VSUSP 10	52	#define VSUSP 10
55	#define VEOL 11	53	#define VEOL 11
56	#define VREPRINT 12	54	#define VREPRINT 12
57	#define VDISCARD 13	55	#define VDISCARD 13
58	#define VWERASE 14	56	#define VWERASE 14
59	#define VLNEXT 15	57	#define VLNEXT 15
60	#define VEOL2 16	58	#define VEOL2 16
61		59
62	/* c_iflag bits */	60	/* c_iflag bits */
63	#define IGNBRK 0000001	61	#define IUCLC 0x0200
64	#define BRKINT 0000002	62	#define IXON 0x0400
65	#define IGNPAR 0000004	63	#define IXOFF 0x1000
66	#define PARMRK 0000010	64	#define IMAXBEL 0x2000
67	#define INPCK 0000020	65	#define IUTF8 0x4000
68	#define ISTRIP 0000040
69	#define INLCR 0000100
70	#define IGNCR 0000200
71	#define ICRNL 0000400
72	#define IUCLC 0001000
73	#define IXON 0002000
74	#define IXANY 0004000
75	#define IXOFF 0010000
76	#define IMAXBEL 0020000
77	#define IUTF8 0040000
78		66
79	/* c_oflag bits */	67	/* c_oflag bits */
80	#define OPOST 0000001	68	#define OLCUC 0x00002
81	#define OLCUC 0000002	69	#define ONLCR 0x00004
82	#define ONLCR 0000004	70	#define NLDLY 0x00100
83	#define OCRNL 0000010	71	#define NL0 0x00000
84	#define ONOCR 0000020	72	#define NL1 0x00100
85	#define ONLRET 0000040	73	#define CRDLY 0x00600
86	#define OFILL 0000100	74	#define CR0 0x00000
87	#define OFDEL 0000200	75	#define CR1 0x00200
88	#define NLDLY 0000400	76	#define CR2 0x00400
89	#define NL0 0000000	77	#define CR3 0x00600
90	#define NL1 0000400	78	#define TABDLY 0x01800
91	#define CRDLY 0003000	79	#define TAB0 0x00000
92	#define CR0 0000000	80	#define TAB1 0x00800
93	#define CR1 0001000	81	#define TAB2 0x01000
94	#define CR2 0002000	82	#define TAB3 0x01800
95	#define CR3 0003000	83	#define XTABS 0x01800
96	#define TABDLY 0014000	84	#define BSDLY 0x02000
97	#define TAB0 0000000	85	#define BS0 0x00000
98	#define TAB1 0004000	86	#define BS1 0x02000
99	#define TAB2 0010000	87	#define VTDLY 0x04000
100	#define TAB3 0014000	88	#define VT0 0x00000
101	#define XTABS 0014000	89	#define VT1 0x04000
102	#define BSDLY 0020000	90	#define FFDLY 0x08000
103	#define BS0 0000000	91	#define FF0 0x00000
104	#define BS1 0020000	92	#define FF1 0x08000
105	#define VTDLY 0040000
106	#define VT0 0000000
107	#define VT1 0040000
108	#define FFDLY 0100000
109	#define FF0 0000000
110	#define FF1 0100000
111		93
112	/* c_cflag bit meaning */	94	/* c_cflag bit meaning */
113	#define CBAUD 0010017	95	#define CBAUD 0x0000100f
114	#define B0 0000000 /* hang up */	96	#define CSIZE 0x00000030
115	#define B50 0000001	97	#define CS5 0x00000000
116	#define B75 0000002	98	#define CS6 0x00000010
117	#define B110 0000003	99	#define CS7 0x00000020
118	#define B134 0000004	100	#define CS8 0x00000030
119	#define B150 0000005	101	#define CSTOPB 0x00000040
120	#define B200 0000006	102	#define CREAD 0x00000080
121	#define B300 0000007	103	#define PARENB 0x00000100
122	#define B600 0000010	104	#define PARODD 0x00000200
123	#define B1200 0000011	105	#define HUPCL 0x00000400
124	#define B1800 0000012	106	#define CLOCAL 0x00000800
125	#define B2400 0000013	107	#define CBAUDEX 0x00001000
126	#define B4800 0000014	108	#define BOTHER 0x00001000
127	#define B9600 0000015	109	#define B57600 0x00001001
128	#define B19200 0000016	110	#define B115200 0x00001002
129	#define B38400 0000017	111	#define B230400 0x00001003
130	#define EXTA B19200	112	#define B460800 0x00001004
131	#define EXTB B38400	113	#define B500000 0x00001005
132	#define CSIZE 0000060	114	#define B576000 0x00001006
133	#define CS5 0000000	115	#define B921600 0x00001007
134	#define CS6 0000020	116	#define B1000000 0x00001008
135	#define CS7 0000040	117	#define B1152000 0x00001009
136	#define CS8 0000060	118	#define B1500000 0x0000100a
137	#define CSTOPB 0000100	119	#define B2000000 0x0000100b
138	#define CREAD 0000200	120	#define B2500000 0x0000100c
139	#define PARENB 0000400	121	#define B3000000 0x0000100d
140	#define PARODD 0001000	122	#define B3500000 0x0000100e
141	#define HUPCL 0002000	123	#define B4000000 0x0000100f
142	#define CLOCAL 0004000	124	#define CIBAUD 0x100f0000 /* input baud rate */
143	#define CBAUDEX 0010000
144	#define BOTHER 0010000
145	#define B57600 0010001
146	#define B115200 0010002
147	#define B230400 0010003
148	#define B460800 0010004
149	#define B500000 0010005
150	#define B576000 0010006
151	#define B921600 0010007
152	#define B1000000 0010010
153	#define B1152000 0010011
154	#define B1500000 0010012
155	#define B2000000 0010013
156	#define B2500000 0010014
157	#define B3000000 0010015
158	#define B3500000 0010016
159	#define B4000000 0010017
160	#define CIBAUD 002003600000 /* input baud rate */
161	#define CMSPAR 010000000000 /* mark or space (stick) parity */
162	#define CRTSCTS 020000000000 /* flow control */
163
164	#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
165		125
166	/* c_lflag bits */	126	/* c_lflag bits */
167	#define ISIG 0000001	127	#define ISIG 0x00001
168	#define ICANON 0000002	128	#define ICANON 0x00002
169	#define XCASE 0000004	129	#define XCASE 0x00004
170	#define ECHO 0000010	130	#define ECHO 0x00008
171	#define ECHOE 0000020	131	#define ECHOE 0x00010
172	#define ECHOK 0000040	132	#define ECHOK 0x00020
173	#define ECHONL 0000100	133	#define ECHONL 0x00040
174	#define NOFLSH 0000200	134	#define NOFLSH 0x00080
175	#define TOSTOP 0000400	135	#define TOSTOP 0x00100
176	#define ECHOCTL 0001000	136	#define ECHOCTL 0x00200
177	#define ECHOPRT 0002000	137	#define ECHOPRT 0x00400
178	#define ECHOKE 0004000	138	#define ECHOKE 0x00800
179	#define FLUSHO 0010000	139	#define FLUSHO 0x01000
180	#define PENDIN 0040000	140	#define PENDIN 0x04000
181	#define IEXTEN 0100000	141	#define IEXTEN 0x08000
182	#define EXTPROC 0200000	142	#define EXTPROC 0x10000
183
184	/* tcflow() and TCXONC use these */
185	#define TCOOFF 0
186	#define TCOON 1
187	#define TCIOFF 2
188	#define TCION 3
189
190	/* tcflush() and TCFLSH use these */
191	#define TCIFLUSH 0
192	#define TCOFLUSH 1
193	#define TCIOFLUSH 2
194		143
195	/* tcsetattr uses these */	144	/* tcsetattr uses these */
196	#define TCSANOW 0	145	#define TCSANOW 0