lael-labs/linux

.mailmap+2−0

 James Bottomley <jejb@mulgrave.(none)>
 James Bottomley <jejb@titanic.il.steeleye.com>
 James E Wilson <wilson@specifix.com>
+James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
+James Hogan <jhogan@kernel.org> <james@albanarts.com>
 James Ketrenos <jketreno@io.(none)>
 Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
 <javier@osg.samsung.com> <javier.martinez@collabora.co.uk>

Documentation/ABI/testing/sysfs-power+1−1

@@ -127,7 +127,7 @@ Description: · 126 unmodified lines
127		127
128	What; /sys/power/pm_trace_dev_match	128	What; /sys/power/pm_trace_dev_match
129	Date: October 2010	129	Date: October 2010
130	Contact: James Hogan <james@albanarts.com>	130	Contact: James Hogan <jhogan@kernel.org>
131	Description:	131	Description:
132	The /sys/power/pm_trace_dev_match file contains the name of the	132	The /sys/power/pm_trace_dev_match file contains the name of the
133	device associated with the last PM event point saved in the RTC	133	device associated with the last PM event point saved in the RTC

Documentation/core-api/workqueue.rst+6−6

Documentation/cpu-freq/index.txt+0−2

@@ -32,8 +32,6 @@ cpufreq-stats.txt - General description of sysfs cpufreq stats. · 31 unmodified lines
32		32
33	index.txt - File index, Mailing list and Links (this document)	33	index.txt - File index, Mailing list and Links (this document)
34		34
35	intel-pstate.txt - Intel pstate cpufreq driver specific file.
36
37	pcc-cpufreq.txt - PCC cpufreq driver specific file.	35	pcc-cpufreq.txt - PCC cpufreq driver specific file.
38		36
39		37

Documentation/device-mapper/dm-raid.txt+1−0

@@ -344,3 +344,4 @@ Version History · 343 unmodified lines
344	(wrong raid10_copies/raid10_format sequence)	344	(wrong raid10_copies/raid10_format sequence)
345	1.11.1 Add raid4/5/6 journal write-back support via journal_mode option	345	1.11.1 Add raid4/5/6 journal write-back support via journal_mode option
346	1.12.1 fix for MD deadlock between mddev_suspend() and md_write_start() available	346	1.12.1 fix for MD deadlock between mddev_suspend() and md_write_start() available
		347	1.13.0 Fix dev_health status at end of "recover" (was 'a', now 'A')

Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt+1−1

@@ -32,7 +32,7 @@ Example: · 31 unmodified lines
32	compatible = "st,stm32h743-rcc", "st,stm32-rcc";	32	compatible = "st,stm32h743-rcc", "st,stm32-rcc";
33	reg = <0x58024400 0x400>;	33	reg = <0x58024400 0x400>;
34	#reset-cells = <1>;	34	#reset-cells = <1>;
35	#clock-cells = <2>;	35	#clock-cells = <1>;
36	clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;	36	clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
37		37
38	st,syscfg = <&pwrcfg>;	38	st,syscfg = <&pwrcfg>;

Documentation/devicetree/bindings/leds/ams,as3645a.txt+18−10

 compatible	: Must be "ams,as3645a".
 reg		: The I2C address of the device. Typically 0x30.
+#address-cells	: 1
+#size-cells	: 0
-Required properties of the "flash" child node
+Required properties of the flash child node (0)
-=============================================
+===============================================
+reg: 0
 flash-timeout-us: Flash timeout in microseconds. The value must be in
 		  the range [100000, 850000] and divisible by 50000.
 flash-max-microamp: Maximum flash current in microamperes. Has to be
 			and divisible by 50000.
-Optional properties of the "flash" child node
+Optional properties of the flash child node
-=============================================
+===========================================
 label		: The label of the flash LED.
-Required properties of the "indicator" child node
+Required properties of the indicator child node (1)
-=================================================
+===================================================
+reg: 1
 led-max-microamp: Maximum indicator current. The allowed values are
 		  2500, 5000, 7500 and 10000.
-Optional properties of the "indicator" child node
+Optional properties of the indicator child node
-=================================================
+===============================================
 label		: The label of the indicator LED.
 =======
 	as3645a@30 {
+		#address-cells: 1
+		#size-cells: 0
 		reg = <0x30>;
 		compatible = "ams,as3645a";
-		flash {
+		flash@0 {
+			reg = <0x0>;
 			flash-timeout-us = <150000>;
 			flash-max-microamp = <320000>;
 			led-max-microamp = <60000>;
 			ams,input-max-microamp = <1750000>;
 			label = "as3645a:flash";
 		};
-		indicator {
+		indicator@1 {
+			reg = <0x1>;
 			led-max-microamp = <10000>;
 			label = "as3645a:indicator";
 		};

Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt+7−5

 - clocks:
   Array of clocks required for SDHC.
-  Require at least input clock for Xenon IP core.
+  Require at least input clock for Xenon IP core. For Armada AP806 and
+  CP110, the AXI clock is also mandatory.
 - clock-names:
   Array of names corresponding to clocks property.
   The input clock for Xenon IP core should be named as "core".
+  The input clock for the AXI bus must be named as "axi".
 - reg:
   * For "marvell,armada-3700-sdhci", two register areas.
 		compatible = "marvell,armada-ap806-sdhci";
 		reg = <0xaa0000 0x1000>;
 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
-		clocks = <&emmc_clk>;
+		clocks = <&emmc_clk>,<&axi_clk>;
-		clock-names = "core";
+		clock-names = "core", "axi";
 		bus-width = <4>;
 		marvell,xenon-phy-slow-mode;
 		marvell,xenon-tun-count = <11>;
 		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
 		vqmmc-supply = <&sd_vqmmc_regulator>;
 		vmmc-supply = <&sd_vmmc_regulator>;
-		clocks = <&sdclk>;
+		clocks = <&sdclk>, <&axi_clk>;
-		clock-names = "core";
+		clock-names = "core", "axi";
 		bus-width = <4>;
 		marvell,xenon-tun-count = <9>;
 	};

Documentation/devicetree/bindings/net/marvell-pp2.txt+6−4

 	- main controller clock (for both armada-375-pp2 and armada-7k-pp2)
 	- GOP clock (for both armada-375-pp2 and armada-7k-pp2)
 	- MG clock (only for armada-7k-pp2)
-- clock-names: names of used clocks, must be "pp_clk", "gop_clk" and
+	- AXI clock (only for armada-7k-pp2)
-  "mg_clk" (the latter only for armada-7k-pp2).
+- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk"
+  and "axi_clk" (the 2 latter only for armada-7k-pp2).
 The ethernet ports are represented by subnodes. At least one port is
 required.
 cpm_ethernet: ethernet@0 {
 	compatible = "marvell,armada-7k-pp22";
 	reg = <0x0 0x100000>, <0x129000 0xb000>;
-	clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
+	clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
-	clock-names = "pp_clk", "gop_clk", "gp_clk";
+		 <&cpm_syscon0 1 5>, <&cpm_syscon0 1 18>;
+	clock-names = "pp_clk", "gop_clk", "gp_clk", "axi_clk";
 	eth0: eth0 {
 		interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,

Documentation/devicetree/bindings/net/rockchip-dwmac.txt+1−0

@@ -4,6 +4,7 @@ The device node has following properties. · 3 unmodified lines
4		4
5	Required properties:	5	Required properties:
6	- compatible: should be "rockchip,<name>-gamc"	6	- compatible: should be "rockchip,<name>-gamc"
		7	"rockchip,rk3128-gmac": found on RK312x SoCs
7	"rockchip,rk3228-gmac": found on RK322x SoCs	8	"rockchip,rk3228-gmac": found on RK322x SoCs
8	"rockchip,rk3288-gmac": found on RK3288 SoCs	9	"rockchip,rk3288-gmac": found on RK3288 SoCs
9	"rockchip,rk3328-gmac": found on RK3328 SoCs	10	"rockchip,rk3328-gmac": found on RK3328 SoCs

Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt+28−0

@@ -0,0 +1,28 @@
	1	Binding for the Synopsys HSDK reset controller
	2
	3	This binding uses the common reset binding[1].
	4
	5	[1] Documentation/devicetree/bindings/reset/reset.txt
	6
	7	Required properties:
	8	- compatible: should be "snps,hsdk-reset".
	9	- reg: should always contain 2 pairs address - length: first for reset
	10	configuration register and second for corresponding SW reset and status bits
	11	register.
	12	- #reset-cells: from common reset binding; Should always be set to 1.
	13
	14	Example:
	15	reset: reset@880 {
	16	compatible = "snps,hsdk-reset";
	17	#reset-cells = <1>;
	18	reg = <0x8A0 0x4>, <0xFF0 0x4>;
	19	};
	20
	21	Specifying reset lines connected to IP modules:
	22	ethernet@.... {
	23	....
	24	resets = <&reset HSDK_V1_ETH_RESET>;
	25	....
	26	};
	27
	28	The index could be found in <dt-bindings/reset/snps,hsdk-reset.h>

Documentation/devicetree/bindings/security/tpm/tpm-i2c.txt+6−0

                    the firmware event log
 - linux,sml-size : size of the memory allocated for the firmware event log
+Optional properties:
+- powered-while-suspended: present when the TPM is left powered on between
+                           suspend and resume (makes the suspend/resume
+                           callbacks do nothing).
 Example (for OpenPower Systems with Nuvoton TPM 2.0 on I2C)
 ----------------------------------------------------------

Documentation/devicetree/bindings/serial/renesas,sci-serial.txt+2−0

     - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
     - "renesas,scif-r8a7796" for R8A7796 (R-Car M3-W) SCIF compatible UART.
     - "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART.
+    - "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART.
+    - "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART.
     - "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART.
     - "renesas,hscif-r8a77995" for R8A77995 (R-Car D3) HSCIF compatible UART.
     - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.

Documentation/devicetree/bindings/vendor-prefixes.txt+1−1

@@ -3,8 +3,8 @@ Device tree binding vendor prefix registry. Keep list in alphabetical order. · 2 unmodified lines
3	This isn't an exhaustive list, but you should add new prefixes to it before	3	This isn't an exhaustive list, but you should add new prefixes to it before
4	using them to avoid name-space collisions.	4	using them to avoid name-space collisions.
5		5
6	abcn Abracon Corporation
7	abilis Abilis Systems	6	abilis Abilis Systems
		7	abracon Abracon Corporation
8	actions Actions Semiconductor Co., Ltd.	8	actions Actions Semiconductor Co., Ltd.
9	active-semi Active-Semi International Inc	9	active-semi Active-Semi International Inc
10	ad Avionic Design GmbH	10	ad Avionic Design GmbH

Documentation/driver-api/pm/devices.rst+1−1

@@ -675,7 +675,7 @@ sub-domain of the parent domain. · 674 unmodified lines
675		675
676	Support for power domains is provided through the :c:member:`pm_domain` field of	676	Support for power domains is provided through the :c:member:`pm_domain` field of
677	\|struct device\|. This field is a pointer to an object of type	677	\|struct device\|. This field is a pointer to an object of type
678	\|struct dev_pm_domain\|, defined in :file:`include/linux/pm.h``, providing a set	678	\|struct dev_pm_domain\|, defined in :file:`include/linux/pm.h`, providing a set
679	of power management callbacks analogous to the subsystem-level and device driver	679	of power management callbacks analogous to the subsystem-level and device driver
680	callbacks that are executed for the given device during all power transitions,	680	callbacks that are executed for the given device during all power transitions,
681	instead of the respective subsystem-level callbacks. Specifically, if a	681	instead of the respective subsystem-level callbacks. Specifically, if a

Documentation/driver-model/driver.txt+4−3

 };
 Device drivers can export attributes via their sysfs directories.
-Drivers can declare attributes using a DRIVER_ATTR macro that works
+Drivers can declare attributes using a DRIVER_ATTR_RW and DRIVER_ATTR_RO
-identically to the DEVICE_ATTR macro.
+macro that works identically to the DEVICE_ATTR_RW and DEVICE_ATTR_RO
+macros.
 Example:
-DRIVER_ATTR(debug,0644,show_debug,store_debug);
+DRIVER_ATTR_RW(debug);
 This is equivalent to declaring:

Documentation/filesystems/cifs/AUTHORS+5−0

 Jeff Layton (many, many fixes, as well as great work on the cifs Kerberos code)
 Scott Lovenberg
 Pavel Shilovsky (for great work adding SMB2 support, and various SMB3 features)
+Aurelien Aptel (for DFS SMB3 work and some key bug fixes)
+Ronnie Sahlberg (for SMB3 xattr work and bug fixes)
+Shirish Pargaonkar (for many ACL patches over the years)
+Sachin Prabhu (many bug fixes, including for reconnect, copy offload and security)
 Test case and Bug Report contributors
 -------------------------------------

Documentation/filesystems/cifs/README+38−43

@@ -1,10 +1,14 @@
1	The CIFS VFS support for Linux supports many advanced network filesystem	1	This module supports the SMB3 family of advanced network protocols (as well
2	features such as hierarchical dfs like namespace, hardlinks, locking and more.	2	as older dialects, originally called "CIFS" or SMB1).
		3
		4	The CIFS VFS module for Linux supports many advanced network filesystem
		5	features such as hierarchical DFS like namespace, hardlinks, locking and more.
3	It was designed to comply with the SNIA CIFS Technical Reference (which	6	It was designed to comply with the SNIA CIFS Technical Reference (which
4	supersedes the 1992 X/Open SMB Standard) as well as to perform best practice	7	supersedes the 1992 X/Open SMB Standard) as well as to perform best practice
5	practical interoperability with Windows 2000, Windows XP, Samba and equivalent	8	practical interoperability with Windows 2000, Windows XP, Samba and equivalent
6	servers. This code was developed in participation with the Protocol Freedom	9	servers. This code was developed in participation with the Protocol Freedom
7	Information Foundation.	10	Information Foundation. CIFS and now SMB3 has now become a defacto
		11	standard for interoperating between Macs and Windows and major NAS appliances.
8		12
9	Please see	13	Please see
10	http://protocolfreedom.org/ and	14	http://protocolfreedom.org/ and
@@ -15,30 +19,11 @@ for more details. · 4 unmodified lines
15	For questions or bug reports please contact:	19	For questions or bug reports please contact:
16	sfrench@samba.org (sfrench@us.ibm.com)	20	sfrench@samba.org (sfrench@us.ibm.com)
17		21
		22	See the project page at: https://wiki.samba.org/index.php/LinuxCIFS_utils
		23
18	Build instructions:	24	Build instructions:
19	==================	25	==================
20	For Linux 2.4:	26	For Linux:
21	1) Get the kernel source (e.g.from http://www.kernel.org)
22	and download the cifs vfs source (see the project page
23	at http://us1.samba.org/samba/Linux_CIFS_client.html)
24	and change directory into the top of the kernel directory
25	then patch the kernel (e.g. "patch -p1 < cifs_24.patch")
26	to add the cifs vfs to your kernel configure options if
27	it has not already been added (e.g. current SuSE and UL
28	users do not need to apply the cifs_24.patch since the cifs vfs is
29	already in the kernel configure menu) and then
30	mkdir linux/fs/cifs and then copy the current cifs vfs files from
31	the cifs download to your kernel build directory e.g.
32
33	cp <cifs_download_dir>/fs/cifs/* to <kernel_download_dir>/fs/cifs
34
35	2) make menuconfig (or make xconfig)
36	3) select cifs from within the network filesystem choices
37	4) save and exit
38	5) make dep
39	6) make modules (or "make" if CIFS VFS not to be built as a module)
40
41	For Linux 2.6:
42	1) Download the kernel (e.g. from http://www.kernel.org)	27	1) Download the kernel (e.g. from http://www.kernel.org)
43	and change directory into the top of the kernel directory tree	28	and change directory into the top of the kernel directory tree
44	(e.g. /usr/src/linux-2.5.73)	29	(e.g. /usr/src/linux-2.5.73)
@@ -61,16 +46,13 @@ would simply type "make install"). · 16 unmodified lines
61	If you do not have the utility mount.cifs (in the Samba 3.0 source tree and on	46	If you do not have the utility mount.cifs (in the Samba 3.0 source tree and on
62	the CIFS VFS web site) copy it to the same directory in which mount.smbfs and	47	the CIFS VFS web site) copy it to the same directory in which mount.smbfs and
63	similar files reside (usually /sbin). Although the helper software is not	48	similar files reside (usually /sbin). Although the helper software is not
64	required, mount.cifs is recommended. Eventually the Samba 3.0 utility program	49	required, mount.cifs is recommended. Most distros include a "cifs-utils"
65	"net" may also be helpful since it may someday provide easier mount syntax for	50	package that includes this utility so it is recommended to install this.
66	users who are used to Windows e.g.	51
67	net use <mount point> <UNC name or cifs URL>
68	Note that running the Winbind pam/nss module (logon service) on all of your	52	Note that running the Winbind pam/nss module (logon service) on all of your
69	Linux clients is useful in mapping Uids and Gids consistently across the	53	Linux clients is useful in mapping Uids and Gids consistently across the
70	domain to the proper network user. The mount.cifs mount helper can be	54	domain to the proper network user. The mount.cifs mount helper can be
71	trivially built from Samba 3.0 or later source e.g. by executing:	55	found at cifs-utils.git on git.samba.org
72
73	gcc samba/source/client/mount.cifs.c -o mount.cifs
74		56
75	If cifs is built as a module, then the size and number of network buffers	57	If cifs is built as a module, then the size and number of network buffers
76	and maximum number of simultaneous requests to one server can be configured.	58	and maximum number of simultaneous requests to one server can be configured.
@@ -79,6 +61,18 @@ Changing these from their defaults is not recommended. By executing modinfo · 2 unmodified lines
79	on kernel/fs/cifs/cifs.ko the list of configuration changes that can be made	61	on kernel/fs/cifs/cifs.ko the list of configuration changes that can be made
80	at module initialization time (by running insmod cifs.ko) can be seen.	62	at module initialization time (by running insmod cifs.ko) can be seen.
81		63
		64	Recommendations
		65	===============
		66	To improve security the SMB2.1 dialect or later (usually will get SMB3) is now
		67	the new default. To use old dialects (e.g. to mount Windows XP) use "vers=1.0"
		68	on mount (or vers=2.0 for Windows Vista). Note that the CIFS (vers=1.0) is
		69	much older and less secure than the default dialect SMB3 which includes
		70	many advanced security features such as downgrade attack detection
		71	and encrypted shares and stronger signing and authentication algorithms.
		72	There are additional mount options that may be helpful for SMB3 to get
		73	improved POSIX behavior (NB: can use vers=3.0 to force only SMB3, never 2.1):
		74	"mfsymlinks" and "cifsacl" and "idsfromsid"
		75
82	Allowing User Mounts	76	Allowing User Mounts
83	====================	77	====================
84	To permit users to mount and unmount over directories they own is possible	78	To permit users to mount and unmount over directories they own is possible
@@ -98,9 +92,7 @@ and execution of suid programs on the remote target would be enabled · 13 unmodified lines
98	by default. This can be changed, as with nfs and other filesystems,	92	by default. This can be changed, as with nfs and other filesystems,
99	by simply specifying "nosuid" among the mount options. For user mounts	93	by simply specifying "nosuid" among the mount options. For user mounts
100	though to be able to pass the suid flag to mount requires rebuilding	94	though to be able to pass the suid flag to mount requires rebuilding
101	mount.cifs with the following flag:	95	mount.cifs with the following flag: CIFS_ALLOW_USR_SUID
102
103	gcc samba/source/client/mount.cifs.c -DCIFS_ALLOW_USR_SUID -o mount.cifs
104		96
105	There is a corresponding manual page for cifs mounting in the Samba 3.0 and	97	There is a corresponding manual page for cifs mounting in the Samba 3.0 and
106	later source tree in docs/manpages/mount.cifs.8	98	later source tree in docs/manpages/mount.cifs.8
@@ -189,18 +181,18 @@ applications running on the same server as Samba. · 82 unmodified lines
189	Use instructions:	181	Use instructions:
190	================	182	================
191	Once the CIFS VFS support is built into the kernel or installed as a module	183	Once the CIFS VFS support is built into the kernel or installed as a module
192	(cifs.o), you can use mount syntax like the following to access Samba or Windows	184	(cifs.ko), you can use mount syntax like the following to access Samba or
193	servers:	185	Mac or Windows servers:
194		186
195	mount -t cifs //9.53.216.11/e$ /mnt -o user=myname,pass=mypassword	187	mount -t cifs //9.53.216.11/e$ /mnt -o username=myname,password=mypassword
196		188
197	Before -o the option -v may be specified to make the mount.cifs	189	Before -o the option -v may be specified to make the mount.cifs
198	mount helper display the mount steps more verbosely.	190	mount helper display the mount steps more verbosely.
199	After -o the following commonly used cifs vfs specific options	191	After -o the following commonly used cifs vfs specific options
200	are supported:	192	are supported:
201		193
202	user=<username>	194	username=<username>
203	pass=<password>	195	password=<password>
204	domain=<domain name>	196	domain=<domain name>
205		197
206	Other cifs mount options are described below. Use of TCP names (in addition to	198	Other cifs mount options are described below. Use of TCP names (in addition to
@@ -246,13 +238,16 @@ the Server's registry. Samba starting with version 3.10 will allow such · 39 unmodified lines
246	filenames (ie those which contain valid Linux characters, which normally	238	filenames (ie those which contain valid Linux characters, which normally
247	would be forbidden for Windows/CIFS semantics) as long as the server is	239	would be forbidden for Windows/CIFS semantics) as long as the server is
248	configured for Unix Extensions (and the client has not disabled	240	configured for Unix Extensions (and the client has not disabled
249	/proc/fs/cifs/LinuxExtensionsEnabled).	241	/proc/fs/cifs/LinuxExtensionsEnabled). In addition the mount option
250		242	"mapposix" can be used on CIFS (vers=1.0) to force the mapping of
		243	illegal Windows/NTFS/SMB characters to a remap range (this mount parm
		244	is the default for SMB3). This remap ("mapposix") range is also
		245	compatible with Mac (and "Services for Mac" on some older Windows).
251		246
252	CIFS VFS Mount Options	247	CIFS VFS Mount Options
253	======================	248	======================
254	A partial list of the supported mount options follows:	249	A partial list of the supported mount options follows:
255	user The user name to use when trying to establish	250	username The user name to use when trying to establish
256	the CIFS session.	251	the CIFS session.
257	password The user password. If the mount helper is	252	password The user password. If the mount helper is
258	installed, the user will be prompted for password	253	installed, the user will be prompted for password

Documentation/filesystems/cifs/TODO+34−38

@@ -1,4 +1,4 @@
1	Version 2.03 August 1, 2014	1	Version 2.04 September 13, 2017
2		2
3	A Partial List of Missing Features	3	A Partial List of Missing Features
4	==================================	4	==================================
@@ -8,73 +8,69 @@ for visible, important contributions to this module. Here · 3 unmodified lines
8	is a partial list of the known problems and missing features:	8	is a partial list of the known problems and missing features:
9		9
10	a) SMB3 (and SMB3.02) missing optional features:	10	a) SMB3 (and SMB3.02) missing optional features:
11	- RDMA	11	- RDMA (started)
12	- multichannel (started)	12	- multichannel (started)
13	- directory leases (improved metadata caching)	13	- directory leases (improved metadata caching)
14	- T10 copy offload (copy chunk is only mechanism supported)	14	- T10 copy offload (copy chunk is only mechanism supported)
15	- encrypted shares
16		15
17	b) improved sparse file support	16	b) improved sparse file support
18		17
19	c) Directory entry caching relies on a 1 second timer, rather than	18	c) Directory entry caching relies on a 1 second timer, rather than
20	using FindNotify or equivalent. - (started)	19	using Directory Leases
21		20
22	d) quota support (needs minor kernel change since quota calls	21	d) quota support (needs minor kernel change since quota calls
23	to make it to network filesystems or deviceless filesystems)	22	to make it to network filesystems or deviceless filesystems)
24		23
25	e) improve support for very old servers (OS/2 and Win9x for example)	24	e) Better optimize open to reduce redundant opens (using reference
26	Including support for changing the time remotely (utimes command).	25	counts more) and to improve use of compounding in SMB3 to reduce
		26	number of roundtrips.
27		27
28	f) hook lower into the sockets api (as NFS/SunRPC does) to avoid the	28	f) Finish inotify support so kde and gnome file list windows
29	extra copy in/out of the socket buffers in some cases.
30
31	g) Better optimize open (and pathbased setfilesize) to reduce the
32	oplock breaks coming from windows srv. Piggyback identical file
33	opens on top of each other by incrementing reference count rather
34	than resending (helps reduce server resource utilization and avoid
35	spurious oplock breaks).
36
37	h) Add support for storing symlink info to Windows servers
38	in the Extended Attribute format their SFU clients would recognize.
39
40	i) Finish inotify support so kde and gnome file list windows
41	will autorefresh (partially complete by Asser). Needs minor kernel	29	will autorefresh (partially complete by Asser). Needs minor kernel
42	vfs change to support removing D_NOTIFY on a file.	30	vfs change to support removing D_NOTIFY on a file.
43		31
44	j) Add GUI tool to configure /proc/fs/cifs settings and for display of	32	g) Add GUI tool to configure /proc/fs/cifs settings and for display of
45	the CIFS statistics (started)	33	the CIFS statistics (started)
46		34
47	k) implement support for security and trusted categories of xattrs	35	h) implement support for security and trusted categories of xattrs
48	(requires minor protocol extension) to enable better support for SELINUX	36	(requires minor protocol extension) to enable better support for SELINUX
49		37
50	l) Implement O_DIRECT flag on open (already supported on mount)	38	i) Implement O_DIRECT flag on open (already supported on mount)
51		39
52	m) Create UID mapping facility so server UIDs can be mapped on a per	40	j) Create UID mapping facility so server UIDs can be mapped on a per
53	mount or a per server basis to client UIDs or nobody if no mapping	41	mount or a per server basis to client UIDs or nobody if no mapping
54	exists. This is helpful when Unix extensions are negotiated to	42	exists. Also better integration with winbind for resolving SID owners
55	allow better permission checking when UIDs differ on the server	43
56	and client. Add new protocol request to the CIFS protocol	44	k) Add tools to take advantage of more smb3 specific ioctls and features
57	standard for asking the server for the corresponding name of a	45
58	particular uid.	46	l) encrypted file support
		47
		48	m) improved stats gathering, tools (perhaps integration with nfsometer?)
59		49
60	n) DOS attrs - returned as pseudo-xattr in Samba format (check VFAT and NTFS for this too)	50	n) allow setting more NTFS/SMB3 file attributes remotely (currently limited to compressed
		51	file attribute via chflags) and improve user space tools for managing and
		52	viewing them.
61		53
62	o) mount check for unmatched uids	54	o) mount helper GUI (to simplify the various configuration options on mount)
63		55
64	p) Add support for new vfs entry point for fallocate	56	p) autonegotiation of dialects (offering more than one dialect ie SMB3.02,
		57	SMB3, SMB2.1 not just SMB3).
65		58
66	q) Add tools to take advantage of cifs/smb3 specific ioctls and features	59	q) Allow mount.cifs to be more verbose in reporting errors with dialect
67	such as "CopyChunk" (fast server side file copy)	60	or unsupported feature errors.
68		61
69	r) encrypted file support	62	r) updating cifs documentation, and user guid.
70		63
71	s) improved stats gathering, tools (perhaps integration with nfsometer?)	64	s) Addressing bugs found by running a broader set of xfstests in standard
		65	file system xfstest suite.
72		66
73	t) allow setting more NTFS/SMB3 file attributes remotely (currently limited to compressed	67	t) split cifs and smb3 support into separate modules so legacy (and less
74	file attribute via chflags)	68	secure) CIFS dialect can be disabled in environments that don't need it
		69	and simplify the code.
75		70
76	u) mount helper GUI (to simplify the various configuration options on mount)	71	u) Finish up SMB3.1.1 dialect support
77		72
		73	v) POSIX Extensions for SMB3.1.1
78		74
79	KNOWN BUGS	75	KNOWN BUGS
80	====================================	76	====================================

Documentation/filesystems/cifs/cifs.txt+14−10

-  This is the client VFS module for the Common Internet File System
+  This is the client VFS module for the SMB3 NAS protocol as well
-  (CIFS) protocol which is the successor to the Server Message Block
+  older dialects such as the Common Internet File System (CIFS)
+  protocol which was the successor to the Server Message Block
   (SMB) protocol, the native file sharing mechanism for most early
   PC operating systems. New and improved versions of CIFS are now
   called SMB2 and SMB3. These dialects are also supported by the
   CIFS VFS module. CIFS is fully supported by network
-  file servers such as Windows 2000, 2003, 2008 and 2012
+  file servers such as Windows 2000, 2003, 2008, 2012 and 2016
   as well by Samba (which provides excellent CIFS
-  server support for Linux and many other operating systems), so
+  server support for Linux and many other operating systems), Apple
+  systems, as well as most Network Attached Storage vendors, so
   this network filesystem client can mount to a wide variety of
   servers.
   The intent of this module is to provide the most advanced network
-  file system function for CIFS compliant servers, including better
+  file system function for SMB3 compliant servers, including advanced
-  POSIX compliance, secure per-user session establishment, high
+  security features, excellent parallelized high performance i/o, better
-  performance safe distributed caching (oplock), optional packet
+  POSIX compliance, secure per-user session establishment, encryption,
+  high performance safe distributed caching (leases/oplocks), optional packet
   signing, large files, Unicode support and other internationalization
   improvements. Since both Samba server and this filesystem client support
-  the CIFS Unix extensions, the combination can provide a reasonable
+  the CIFS Unix extensions (and in the future SMB3 POSIX extensions),
-  alternative to NFSv4 for fileserving in some Linux to Linux environments,
+  the combination can provide a reasonable alternative to other network and
-  not just in Linux to Windows environments.
+  cluster file systems for fileserving in some Linux to Linux environments,
+  not just in Linux to Windows (or Linux to Mac) environments.
   This filesystem has an mount utility (mount.cifs) that can be obtained from

Documentation/filesystems/overlayfs.txt+4−1

@@ -210,8 +210,11 @@ path as another overlay mount and it may use a lower layer path that is · 209 unmodified lines
210	beneath or above the path of another overlay lower layer path.	210	beneath or above the path of another overlay lower layer path.
211		211
212	Using an upper layer path and/or a workdir path that are already used by	212	Using an upper layer path and/or a workdir path that are already used by
213	another overlay mount is not allowed and will fail with EBUSY. Using	213	another overlay mount is not allowed and may fail with EBUSY. Using
214	partially overlapping paths is not allowed but will not fail with EBUSY.	214	partially overlapping paths is not allowed but will not fail with EBUSY.
		215	If files are accessed from two overlayfs mounts which share or overlap the
		216	upper layer and/or workdir path the behavior of the overlay is undefined,
		217	though it will not result in a crash or deadlock.
215		218
216	Mounting an overlay using an upper layer path, where the upper layer path	219	Mounting an overlay using an upper layer path, where the upper layer path
217	was previously used by another mounted overlay in combination with a	220	was previously used by another mounted overlay in combination with a

Documentation/filesystems/sysfs.txt+2−1

@@ -366,7 +366,8 @@ struct driver_attribute { · 365 unmodified lines
366		366
367	Declaring:	367	Declaring:
368		368
369	DRIVER_ATTR(_name, _mode, _show, _store)	369	DRIVER_ATTR_RO(_name)
		370	DRIVER_ATTR_RW(_name)
370		371
371	Creation/Removal:	372	Creation/Removal:
372		373

Documentation/i2c/busses/i2c-i801+1−0

@@ -36,6 +36,7 @@ Supported adapters: · 35 unmodified lines
36	* Intel Gemini Lake (SOC)	36	* Intel Gemini Lake (SOC)
37	* Intel Cannon Lake-H (PCH)	37	* Intel Cannon Lake-H (PCH)
38	* Intel Cannon Lake-LP (PCH)	38	* Intel Cannon Lake-LP (PCH)
		39	* Intel Cedar Fork (PCH)
39	Datasheets: Publicly available at the Intel website	40	Datasheets: Publicly available at the Intel website
40		41
41	On Intel Patsburg and later chipsets, both the normal host SMBus controller	42	On Intel Patsburg and later chipsets, both the normal host SMBus controller

Documentation/networking/filter.txt+1−1

@@ -337,7 +337,7 @@ Examples for low-level BPF: · 336 unmodified lines
337	jeq #14, good /* __NR_rt_sigprocmask */	337	jeq #14, good /* __NR_rt_sigprocmask */
338	jeq #13, good /* __NR_rt_sigaction */	338	jeq #13, good /* __NR_rt_sigaction */
339	jeq #35, good /* __NR_nanosleep */	339	jeq #35, good /* __NR_nanosleep */
340	bad: ret #0 /* SECCOMP_RET_KILL */	340	bad: ret #0 /* SECCOMP_RET_KILL_THREAD */
341	good: ret #0x7fff0000 /* SECCOMP_RET_ALLOW */	341	good: ret #0x7fff0000 /* SECCOMP_RET_ALLOW */
342		342
343	The above example code can be placed into a file (here called "foo"), and	343	The above example code can be placed into a file (here called "foo"), and

Documentation/networking/ip-sysctl.txt+14−4

 	2: Enable DAD, and disable IPv6 operation if MAC-based duplicate
 	   link-local address has been found.
+	DAD operation and mode on a given interface will be selected according
+	to the maximum value of conf/{all,interface}/accept_dad.
 force_tllao - BOOLEAN
 	Enable sending the target link-layer address option even when
 	responding to a unicast neighbor solicitation.
 optimistic_dad - BOOLEAN
 	Whether to perform Optimistic Duplicate Address Detection (RFC 4429).
-		0: disabled (default)
+	0: disabled (default)
-		1: enabled
+	1: enabled
+	Optimistic Duplicate Address Detection for the interface will be enabled
+	if at least one of conf/{all,interface}/optimistic_dad is set to 1,
+	it will be disabled otherwise.
 use_optimistic - BOOLEAN
 	If enabled, do not classify optimistic addresses as deprecated during
 	source address selection.  Preferred addresses will still be chosen
 	before optimistic addresses, subject to other ranking in the source
 	address selection algorithm.
-		0: disabled (default)
+	0: disabled (default)
-		1: enabled
+	1: enabled
+	This will be enabled if at least one of
+	conf/{all,interface}/use_optimistic is set to 1, disabled otherwise.
 stable_secret - IPv6 address
 	This IPv6 address will be used as a secret to generate IPv6

Documentation/networking/switchdev.txt+34−34

@@ -13,42 +13,42 @@ an example setup using a data-center-class switch ASIC chip. Other setups · 12 unmodified lines
13	with SR-IOV or soft switches, such as OVS, are possible.	13	with SR-IOV or soft switches, such as OVS, are possible.
14		14
15		15
16	User-space tools	16	User-space tools
17		17
18	user space \|	18	user space \|
19	+-------------------------------------------------------------------+	19	+-------------------------------------------------------------------+
20	kernel \| Netlink	20	kernel \| Netlink
21	\|	21	\|
22	+--------------+-------------------------------+	22	+--------------+-------------------------------+
23	\| Network stack \|	23	\| Network stack \|
24	\| (Linux) \|	24	\| (Linux) \|
25	\| \|	25	\| \|
26	+----------------------------------------------+	26	+----------------------------------------------+
27		27
28	sw1p2 sw1p4 sw1p6	28	sw1p2 sw1p4 sw1p6
29	sw1p1 + sw1p3 + sw1p5 + eth1	29	sw1p1 + sw1p3 + sw1p5 + eth1
30	+ \| + \| + \| +	30	+ \| + \| + \| +
31	\| \| \| \| \| \| \|	31	\| \| \| \| \| \| \|
32	+--+----+----+----+-+--+----+---+ +-----+-----+	32	+--+----+----+----+----+----+---+ +-----+-----+
33	\| Switch driver \| \| mgmt \|	33	\| Switch driver \| \| mgmt \|
34	\| (this document) \| \| driver \|	34	\| (this document) \| \| driver \|
35	\| \| \| \|	35	\| \| \| \|
36	+--------------+----------------+ +-----------+	36	+--------------+----------------+ +-----------+
37	\|	37	\|
38	kernel \| HW bus (eg PCI)	38	kernel \| HW bus (eg PCI)
39	+-------------------------------------------------------------------+	39	+-------------------------------------------------------------------+
40	hardware \|	40	hardware \|
41	+--------------+---+------------+	41	+--------------+----------------+
42	\| Switch device (sw1) \|	42	\| Switch device (sw1) \|
43	\| +----+ +--------+	43	\| +----+ +--------+
44	\| \| v offloaded data path \| mgmt port	44	\| \| v offloaded data path \| mgmt port
45	\| \| \| \|	45	\| \| \| \|
46	+--\|----\|----+----+----+----+---+	46	+--\|----\|----+----+----+----+---+
47	\| \| \| \| \| \|	47	\| \| \| \| \| \|
48	+ + + + + +	48	+ + + + + +
49	p1 p2 p3 p4 p5 p6	49	p1 p2 p3 p4 p5 p6
50		50
51	front-panel ports	51	front-panel ports
52		52
53		53
54	Fig 1.	54	Fig 1.

Documentation/sysctl/kernel.txt+1−0

@@ -75,6 +75,7 @@ show up in /proc/sys/kernel: · 74 unmodified lines
75	- reboot-cmd [ SPARC only ]	75	- reboot-cmd [ SPARC only ]
76	- rtsig-max	76	- rtsig-max
77	- rtsig-nr	77	- rtsig-nr
		78	- seccomp/ ==> Documentation/userspace-api/seccomp_filter.rst
78	- sem	79	- sem
79	- sem_next_id [ sysv ipc ]	80	- sem_next_id [ sysv ipc ]
80	- sg-big-buff [ generic SCSI device (sg) ]	81	- sg-big-buff [ generic SCSI device (sg) ]

Documentation/userspace-api/seccomp_filter.rst+50−2

@@ -87,11 +87,16 @@ Return values · 86 unmodified lines
87	A seccomp filter may return any of the following values. If multiple	87	A seccomp filter may return any of the following values. If multiple
88	filters exist, the return value for the evaluation of a given system	88	filters exist, the return value for the evaluation of a given system
89	call will always use the highest precedent value. (For example,	89	call will always use the highest precedent value. (For example,
90	``SECCOMP_RET_KILL`` will always take precedence.)	90	``SECCOMP_RET_KILL_PROCESS`` will always take precedence.)
91		91
92	In precedence order, they are:	92	In precedence order, they are:
93		93
94	``SECCOMP_RET_KILL``:	94	``SECCOMP_RET_KILL_PROCESS``:
		95	Results in the entire process exiting immediately without executing
		96	the system call. The exit status of the task (``status & 0x7f``)
		97	will be ``SIGSYS``, not ``SIGKILL``.
		98
		99	``SECCOMP_RET_KILL_THREAD``:
95	Results in the task exiting immediately without executing the	100	Results in the task exiting immediately without executing the
96	system call. The exit status of the task (``status & 0x7f``) will	101	system call. The exit status of the task (``status & 0x7f``) will
97	be ``SIGSYS``, not ``SIGKILL``.	102	be ``SIGSYS``, not ``SIGKILL``.
@@ -141,6 +146,15 @@ In precedence order, they are: · 43 unmodified lines
141	allow use of ptrace, even of other sandboxed processes, without	146	allow use of ptrace, even of other sandboxed processes, without
142	extreme care; ptracers can use this mechanism to escape.)	147	extreme care; ptracers can use this mechanism to escape.)
143		148
		149	``SECCOMP_RET_LOG``:
		150	Results in the system call being executed after it is logged. This
		151	should be used by application developers to learn which syscalls their
		152	application needs without having to iterate through multiple test and
		153	development cycles to build the list.
		154
		155	This action will only be logged if "log" is present in the
		156	actions_logged sysctl string.
		157
144	``SECCOMP_RET_ALLOW``:	158	``SECCOMP_RET_ALLOW``:
145	Results in the system call being executed.	159	Results in the system call being executed.
146		160
@@ -169,7 +183,41 @@ The ``samples/seccomp/`` directory contains both an x86-specific example · 22 unmodified lines
169	and a more generic example of a higher level macro interface for BPF	183	and a more generic example of a higher level macro interface for BPF
170	program generation.	184	program generation.
171		185
		186	Sysctls
		187	=======
172		188
		189	Seccomp's sysctl files can be found in the ``/proc/sys/kernel/seccomp/``
		190	directory. Here's a description of each file in that directory:
		191
		192	``actions_avail``:
		193	A read-only ordered list of seccomp return values (refer to the
		194	``SECCOMP_RET_*`` macros above) in string form. The ordering, from
		195	left-to-right, is the least permissive return value to the most
		196	permissive return value.
		197
		198	The list represents the set of seccomp return values supported
		199	by the kernel. A userspace program may use this list to
		200	determine if the actions found in the ``seccomp.h``, when the
		201	program was built, differs from the set of actions actually
		202	supported in the current running kernel.
		203
		204	``actions_logged``:
		205	A read-write ordered list of seccomp return values (refer to the
		206	``SECCOMP_RET_*`` macros above) that are allowed to be logged. Writes
		207	to the file do not need to be in ordered form but reads from the file
		208	will be ordered in the same way as the actions_avail sysctl.
		209
		210	It is important to note that the value of ``actions_logged`` does not
		211	prevent certain actions from being logged when the audit subsystem is
		212	configured to audit a task. If the action is not found in
		213	``actions_logged`` list, the final decision on whether to audit the
		214	action for that task is ultimately left up to the audit subsystem to
		215	decide for all seccomp return values other than ``SECCOMP_RET_ALLOW``.
		216
		217	The ``allow`` string is not accepted in the ``actions_logged`` sysctl
		218	as it is not possible to log ``SECCOMP_RET_ALLOW`` actions. Attempting
		219	to write ``allow`` to the sysctl will result in an EINVAL being
		220	returned.
173		221
174	Adding architecture support	222	Adding architecture support
175	===========================	223	===========================

MAINTAINERS+35−12

@@ -352,6 +352,18 @@ L: linux-acpi@vger.kernel.org · 351 unmodified lines
352	S: Maintained	352	S: Maintained
353	F: drivers/acpi/arm64	353	F: drivers/acpi/arm64
354		354
		355	ACPI PMIC DRIVERS
		356	M: "Rafael J. Wysocki" <rjw@rjwysocki.net>
		357	M: Len Brown <lenb@kernel.org>
		358	R: Andy Shevchenko <andy@infradead.org>
		359	R: Mika Westerberg <mika.westerberg@linux.intel.com>
		360	L: linux-acpi@vger.kernel.org
		361	Q: https://patchwork.kernel.org/project/linux-acpi/list/
		362	T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
		363	B: https://bugzilla.kernel.org
		364	S: Supported
		365	F: drivers/acpi/pmic/
		366
355	ACPI THERMAL DRIVER	367	ACPI THERMAL DRIVER
356	M: Zhang Rui <rui.zhang@intel.com>	368	M: Zhang Rui <rui.zhang@intel.com>
357	L: linux-acpi@vger.kernel.org	369	L: linux-acpi@vger.kernel.org
@@ -2853,7 +2865,6 @@ S: Supported · 2495 unmodified lines
2853	F: drivers/scsi/bnx2i/	2865	F: drivers/scsi/bnx2i/
2854		2866
2855	BROADCOM BNX2X 10 GIGABIT ETHERNET DRIVER	2867	BROADCOM BNX2X 10 GIGABIT ETHERNET DRIVER
2856	M: Yuval Mintz <Yuval.Mintz@cavium.com>
2857	M: Ariel Elior <ariel.elior@cavium.com>	2868	M: Ariel Elior <ariel.elior@cavium.com>
2858	M: everest-linux-l2@cavium.com	2869	M: everest-linux-l2@cavium.com
2859	L: netdev@vger.kernel.org	2870	L: netdev@vger.kernel.org
@@ -5248,7 +5259,8 @@ S: Maintained · 2388 unmodified lines
5248	F: drivers/iommu/exynos-iommu.c	5259	F: drivers/iommu/exynos-iommu.c
5249		5260
5250	EZchip NPS platform support	5261	EZchip NPS platform support
5251	M: Noam Camus <noamc@ezchip.com>	5262	M: Elad Kanfi <eladkan@mellanox.com>
		5263	M: Vineet Gupta <vgupta@synopsys.com>
5252	S: Supported	5264	S: Supported
5253	F: arch/arc/plat-eznps	5265	F: arch/arc/plat-eznps
5254	F: arch/arc/boot/dts/eznps.dts	5266	F: arch/arc/boot/dts/eznps.dts
@@ -6643,8 +6655,8 @@ M: Alexander Aring <alex.aring@gmail.com> · 1388 unmodified lines
6643	M: Stefan Schmidt <stefan@osg.samsung.com>	6655	M: Stefan Schmidt <stefan@osg.samsung.com>
6644	L: linux-wpan@vger.kernel.org	6656	L: linux-wpan@vger.kernel.org
6645	W: http://wpan.cakelab.org/	6657	W: http://wpan.cakelab.org/
6646	T: git git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth.git	6658	T: git git://git.kernel.org/pub/scm/linux/kernel/git/sschmidt/wpan.git
6647	T: git git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.git	6659	T: git git://git.kernel.org/pub/scm/linux/kernel/git/sschmidt/wpan-next.git
6648	S: Maintained	6660	S: Maintained
6649	F: net/ieee802154/	6661	F: net/ieee802154/
6650	F: net/mac802154/	6662	F: net/mac802154/
@@ -6727,7 +6739,7 @@ F: Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt · 76 unmodified lines
6727	F: drivers/auxdisplay/img-ascii-lcd.c	6739	F: drivers/auxdisplay/img-ascii-lcd.c
6728		6740
6729	IMGTEC IR DECODER DRIVER	6741	IMGTEC IR DECODER DRIVER
6730	M: James Hogan <james.hogan@imgtec.com>	6742	M: James Hogan <jhogan@kernel.org>
6731	S: Maintained	6743	S: Maintained
6732	F: drivers/media/rc/img-ir/	6744	F: drivers/media/rc/img-ir/
6733		6745
@@ -7551,7 +7563,7 @@ F: arch/arm64/include/asm/kvm* · 817 unmodified lines
7551	F: arch/arm64/kvm/	7563	F: arch/arm64/kvm/
7552		7564
7553	KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips)	7565	KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips)
7554	M: James Hogan <james.hogan@imgtec.com>	7566	M: James Hogan <jhogan@kernel.org>
7555	L: linux-mips@linux-mips.org	7567	L: linux-mips@linux-mips.org
7556	S: Supported	7568	S: Supported
7557	F: arch/mips/include/uapi/asm/kvm*	7569	F: arch/mips/include/uapi/asm/kvm*
@@ -8253,6 +8265,12 @@ L: libertas-dev@lists.infradead.org · 695 unmodified lines
8253	S: Orphan	8265	S: Orphan
8254	F: drivers/net/wireless/marvell/libertas/	8266	F: drivers/net/wireless/marvell/libertas/
8255		8267
		8268	MARVELL MACCHIATOBIN SUPPORT
		8269	M: Russell King <rmk@armlinux.org.uk>
		8270	L: linux-arm-kernel@lists.infradead.org
		8271	S: Maintained
		8272	F: arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
		8273
8256	MARVELL MV643XX ETHERNET DRIVER	8274	MARVELL MV643XX ETHERNET DRIVER
8257	M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>	8275	M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8258	L: netdev@vger.kernel.org	8276	L: netdev@vger.kernel.org
@@ -8586,6 +8604,12 @@ M: Sean Wang <sean.wang@mediatek.com> · 327 unmodified lines
8586	S: Maintained	8604	S: Maintained
8587	F: drivers/media/rc/mtk-cir.c	8605	F: drivers/media/rc/mtk-cir.c
8588		8606
		8607	MEDIATEK PMIC LED DRIVER
		8608	M: Sean Wang <sean.wang@mediatek.com>
		8609	S: Maintained
		8610	F: drivers/leds/leds-mt6323.c
		8611	F: Documentation/devicetree/bindings/leds/leds-mt6323.txt
		8612
8589	MEDIATEK ETHERNET DRIVER	8613	MEDIATEK ETHERNET DRIVER
8590	M: Felix Fietkau <nbd@openwrt.org>	8614	M: Felix Fietkau <nbd@openwrt.org>
8591	M: John Crispin <john@phrozen.org>	8615	M: John Crispin <john@phrozen.org>
@@ -8868,7 +8892,7 @@ F: Documentation/devicetree/bindings/media/meson-ao-cec.txt · 276 unmodified lines
8868	T: git git://linuxtv.org/media_tree.git	8892	T: git git://linuxtv.org/media_tree.git
8869		8893
8870	METAG ARCHITECTURE	8894	METAG ARCHITECTURE
8871	M: James Hogan <james.hogan@imgtec.com>	8895	M: James Hogan <jhogan@kernel.org>
8872	L: linux-metag@vger.kernel.org	8896	L: linux-metag@vger.kernel.org
8873	T: git git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag.git	8897	T: git git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag.git
8874	S: Odd Fixes	8898	S: Odd Fixes
@@ -9337,7 +9361,7 @@ NETWORK BLOCK DEVICE (NBD) · 462 unmodified lines
9337	M: Josef Bacik <jbacik@fb.com>	9361	M: Josef Bacik <jbacik@fb.com>
9338	S: Maintained	9362	S: Maintained
9339	L: linux-block@vger.kernel.org	9363	L: linux-block@vger.kernel.org
9340	L: nbd-general@lists.sourceforge.net	9364	L: nbd@other.debian.org
9341	F: Documentation/blockdev/nbd.txt	9365	F: Documentation/blockdev/nbd.txt
9342	F: drivers/block/nbd.c	9366	F: drivers/block/nbd.c
9343	F: include/uapi/linux/nbd.h	9367	F: include/uapi/linux/nbd.h
@@ -11047,7 +11071,6 @@ S: Supported · 1703 unmodified lines
11047	F: drivers/scsi/qedi/	11071	F: drivers/scsi/qedi/
11048		11072
11049	QLOGIC QL4xxx ETHERNET DRIVER	11073	QLOGIC QL4xxx ETHERNET DRIVER
11050	M: Yuval Mintz <Yuval.Mintz@cavium.com>
11051	M: Ariel Elior <Ariel.Elior@cavium.com>	11074	M: Ariel Elior <Ariel.Elior@cavium.com>
11052	M: everest-linux-l2@cavium.com	11075	M: everest-linux-l2@cavium.com
11053	L: netdev@vger.kernel.org	11076	L: netdev@vger.kernel.org
@@ -12915,9 +12938,9 @@ F: drivers/mmc/host/dw_mmc* · 1861 unmodified lines
12915	SYNOPSYS HSDK RESET CONTROLLER DRIVER	12938	SYNOPSYS HSDK RESET CONTROLLER DRIVER
12916	M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>	12939	M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
12917	S: Supported	12940	S: Supported
12918	F: drivers/reset/reset-hsdk-v1.c	12941	F: drivers/reset/reset-hsdk.c
12919	F: include/dt-bindings/reset/snps,hsdk-v1-reset.h	12942	F: include/dt-bindings/reset/snps,hsdk-reset.h
12920	F: Documentation/devicetree/bindings/reset/snps,hsdk-v1-reset.txt	12943	F: Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt
12921		12944
12922	SYSTEM CONFIGURATION (SYSCON)	12945	SYSTEM CONFIGURATION (SYSCON)
12923	M: Lee Jones <lee.jones@linaro.org>	12946	M: Lee Jones <lee.jones@linaro.org>

Makefile+3−3

@@ -1,7 +1,7 @@
1	VERSION = 4	1	VERSION = 4
2	PATCHLEVEL = 14	2	PATCHLEVEL = 14
3	SUBLEVEL = 0	3	SUBLEVEL = 0
4	EXTRAVERSION = -rc1	4	EXTRAVERSION = -rc4
5	NAME = Fearless Coyote	5	NAME = Fearless Coyote
6		6
7	# DOCUMENTATION	7	# DOCUMENTATION
@@ -1172,11 +1172,11 @@ headers_check: headers_install · 1164 unmodified lines
1172		1172
1173	PHONY += kselftest	1173	PHONY += kselftest
1174	kselftest:	1174	kselftest:
1175	$(Q)$(MAKE) -C tools/testing/selftests run_tests	1175	$(Q)$(MAKE) -C $(srctree)/tools/testing/selftests run_tests
1176		1176
1177	PHONY += kselftest-clean	1177	PHONY += kselftest-clean
1178	kselftest-clean:	1178	kselftest-clean:
1179	$(Q)$(MAKE) -C tools/testing/selftests clean	1179	$(Q)$(MAKE) -C $(srctree)/tools/testing/selftests clean
1180		1180
1181	PHONY += kselftest-merge	1181	PHONY += kselftest-merge
1182	kselftest-merge:	1182	kselftest-merge:

arch/alpha/include/asm/mmu_context.h+1−0

@@ -8,6 +8,7 @@ · 7 unmodified lines
8	*/	8	*/
9		9
10	#include <linux/mm_types.h>	10	#include <linux/mm_types.h>
		11	#include <linux/sched.h>
11		12
12	#include <asm/machvec.h>	13	#include <asm/machvec.h>
13	#include <asm/compiler.h>	14	#include <asm/compiler.h>

arch/arc/Kconfig+1−1

@@ -24,7 +24,7 @@ config ARC · 23 unmodified lines
24	select GENERIC_SMP_IDLE_THREAD	24	select GENERIC_SMP_IDLE_THREAD
25	select HAVE_ARCH_KGDB	25	select HAVE_ARCH_KGDB
26	select HAVE_ARCH_TRACEHOOK	26	select HAVE_ARCH_TRACEHOOK
27	select HAVE_FUTEX_CMPXCHG	27	select HAVE_FUTEX_CMPXCHG if FUTEX
28	select HAVE_IOREMAP_PROT	28	select HAVE_IOREMAP_PROT
29	select HAVE_KPROBES	29	select HAVE_KPROBES
30	select HAVE_KRETPROBES	30	select HAVE_KRETPROBES

arch/arc/Makefile+0−2

@@ -6,8 +6,6 @@ · 5 unmodified lines
6	# published by the Free Software Foundation.	6	# published by the Free Software Foundation.
7	#	7	#
8		8
9	UTS_MACHINE := arc
10
11	ifeq ($(CROSS_COMPILE),)	9	ifeq ($(CROSS_COMPILE),)
12	ifndef CONFIG_CPU_BIG_ENDIAN	10	ifndef CONFIG_CPU_BIG_ENDIAN
13	CROSS_COMPILE := arc-linux-	11	CROSS_COMPILE := arc-linux-

arch/arc/boot/dts/axs10x_mb.dtsi+8−1

 			mmcclk: mmcclk {
 				compatible = "fixed-clock";
-				clock-frequency = <50000000>;
+				/*
+				 * DW sdio controller has external ciu clock divider
+				 * controlled via register in SDIO IP. It divides
+				 * sdio_ref_clk (which comes from CGU) by 16 for
+				 * default. So default mmcclk clock (which comes
+				 * to sdk_in) is 25000000 Hz.
+				 */
+				clock-frequency = <25000000>;
 				#clock-cells = <0>;
 			};

arch/arc/boot/dts/hsdk.dts+29−3

 /dts-v1/;
 #include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/reset/snps,hsdk-reset.h>
 / {
 	model = "snps,hsdk";
 		};
 	};
-	core_clk: core-clk {
+	input_clk: input-clk {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
-		clock-frequency = <500000000>;
+		clock-frequency = <33333333>;
 	};
 	cpu_intc: cpu-interrupt-controller {
 		ranges = <0x00000000 0xf0000000 0x10000000>;
+		cgu_rst: reset-controller@8a0 {
+			compatible = "snps,hsdk-reset";
+			#reset-cells = <1>;
+			reg = <0x8A0 0x4>, <0xFF0 0x4>;
+		};
+		core_clk: core-clk@0 {
+			compatible = "snps,hsdk-core-pll-clock";
+			reg = <0x00 0x10>, <0x14B8 0x4>;
+			#clock-cells = <0>;
+			clocks = <&input_clk>;
+		};
 		serial: serial@5000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x5000 0x100>;
 		mmcclk_ciu: mmcclk-ciu {
 			compatible = "fixed-clock";
-			clock-frequency = <100000000>;
+			/*
+			 * DW sdio controller has external ciu clock divider
+			 * controlled via register in SDIO IP. Due to its
+			 * unexpected default value (it should devide by 1
+			 * but it devides by 8) SDIO IP uses wrong clock and
+			 * works unstable (see STAR 9001204800)
+			 * So add temporary fix and change clock frequency
+			 * from 100000000 to 12500000 Hz until we fix dw sdio
+			 * driver itself.
+			 */
+			clock-frequency = <12500000>;
 			#clock-cells = <0>;
 		};
 			clocks = <&gmacclk>;
 			clock-names = "stmmaceth";
 			phy-handle = <&phy0>;
+			resets = <&cgu_rst HSDK_ETH_RESET>;
+			reset-names = "stmmaceth";
 			mdio {
 				#address-cells = <1>;

arch/arc/configs/axs101_defconfig+1−1

@@ -105,7 +105,7 @@ CONFIG_NLS_ISO8859_1=y · 104 unmodified lines
105	# CONFIG_ENABLE_WARN_DEPRECATED is not set	105	# CONFIG_ENABLE_WARN_DEPRECATED is not set
106	# CONFIG_ENABLE_MUST_CHECK is not set	106	# CONFIG_ENABLE_MUST_CHECK is not set
107	CONFIG_STRIP_ASM_SYMS=y	107	CONFIG_STRIP_ASM_SYMS=y
108	CONFIG_LOCKUP_DETECTOR=y	108	CONFIG_SOFTLOCKUP_DETECTOR=y
109	CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10	109	CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
110	# CONFIG_SCHED_DEBUG is not set	110	# CONFIG_SCHED_DEBUG is not set
111	# CONFIG_DEBUG_PREEMPT is not set	111	# CONFIG_DEBUG_PREEMPT is not set

arch/arc/configs/axs103_defconfig+1−1

@@ -104,7 +104,7 @@ CONFIG_NLS_ISO8859_1=y · 103 unmodified lines
104	# CONFIG_ENABLE_WARN_DEPRECATED is not set	104	# CONFIG_ENABLE_WARN_DEPRECATED is not set
105	# CONFIG_ENABLE_MUST_CHECK is not set	105	# CONFIG_ENABLE_MUST_CHECK is not set
106	CONFIG_STRIP_ASM_SYMS=y	106	CONFIG_STRIP_ASM_SYMS=y
107	CONFIG_LOCKUP_DETECTOR=y	107	CONFIG_SOFTLOCKUP_DETECTOR=y
108	CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10	108	CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
109	# CONFIG_SCHED_DEBUG is not set	109	# CONFIG_SCHED_DEBUG is not set
110	# CONFIG_DEBUG_PREEMPT is not set	110	# CONFIG_DEBUG_PREEMPT is not set

arch/arc/configs/axs103_smp_defconfig+1−1

@@ -107,7 +107,7 @@ CONFIG_NLS_ISO8859_1=y · 106 unmodified lines
107	# CONFIG_ENABLE_WARN_DEPRECATED is not set	107	# CONFIG_ENABLE_WARN_DEPRECATED is not set
108	# CONFIG_ENABLE_MUST_CHECK is not set	108	# CONFIG_ENABLE_MUST_CHECK is not set
109	CONFIG_STRIP_ASM_SYMS=y	109	CONFIG_STRIP_ASM_SYMS=y
110	CONFIG_LOCKUP_DETECTOR=y	110	CONFIG_SOFTLOCKUP_DETECTOR=y
111	CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10	111	CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
112	# CONFIG_SCHED_DEBUG is not set	112	# CONFIG_SCHED_DEBUG is not set
113	# CONFIG_DEBUG_PREEMPT is not set	113	# CONFIG_DEBUG_PREEMPT is not set

arch/arc/configs/haps_hs_smp_defconfig+1−1

@@ -84,5 +84,5 @@ CONFIG_TMPFS=y · 83 unmodified lines
84	CONFIG_NFS_FS=y	84	CONFIG_NFS_FS=y
85	# CONFIG_ENABLE_WARN_DEPRECATED is not set	85	# CONFIG_ENABLE_WARN_DEPRECATED is not set
86	# CONFIG_ENABLE_MUST_CHECK is not set	86	# CONFIG_ENABLE_MUST_CHECK is not set
87	CONFIG_LOCKUP_DETECTOR=y	87	CONFIG_SOFTLOCKUP_DETECTOR=y
88	# CONFIG_DEBUG_PREEMPT is not set	88	# CONFIG_DEBUG_PREEMPT is not set

arch/arc/configs/hsdk_defconfig+2−1

 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_HSDK=y
 CONFIG_EXT3_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set

arch/arc/configs/vdk_hs38_defconfig+1−1

@@ -94,7 +94,7 @@ CONFIG_NLS_ISO8859_1=y · 93 unmodified lines
94	# CONFIG_ENABLE_MUST_CHECK is not set	94	# CONFIG_ENABLE_MUST_CHECK is not set
95	CONFIG_STRIP_ASM_SYMS=y	95	CONFIG_STRIP_ASM_SYMS=y
96	CONFIG_DEBUG_SHIRQ=y	96	CONFIG_DEBUG_SHIRQ=y
97	CONFIG_LOCKUP_DETECTOR=y	97	CONFIG_SOFTLOCKUP_DETECTOR=y
98	CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10	98	CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
99	# CONFIG_SCHED_DEBUG is not set	99	# CONFIG_SCHED_DEBUG is not set
100	# CONFIG_DEBUG_PREEMPT is not set	100	# CONFIG_DEBUG_PREEMPT is not set

arch/arc/configs/vdk_hs38_smp_defconfig+1−1

@@ -98,7 +98,7 @@ CONFIG_NLS_ISO8859_1=y · 97 unmodified lines
98	# CONFIG_ENABLE_MUST_CHECK is not set	98	# CONFIG_ENABLE_MUST_CHECK is not set
99	CONFIG_STRIP_ASM_SYMS=y	99	CONFIG_STRIP_ASM_SYMS=y
100	CONFIG_DEBUG_SHIRQ=y	100	CONFIG_DEBUG_SHIRQ=y
101	CONFIG_LOCKUP_DETECTOR=y	101	CONFIG_SOFTLOCKUP_DETECTOR=y
102	CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10	102	CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
103	# CONFIG_SCHED_DEBUG is not set	103	# CONFIG_SCHED_DEBUG is not set
104	# CONFIG_DEBUG_PREEMPT is not set	104	# CONFIG_DEBUG_PREEMPT is not set

arch/arc/include/asm/arcregs.h+6−5

 /* Auxiliary registers */
 #define AUX_IDENTITY		4
+#define AUX_EXEC_CTRL		8
 #define AUX_INTR_VEC_BASE	0x25
 #define AUX_VOL			0x5e
 #endif
 };
-struct bcr_isa {
+struct bcr_isa_arcv2 {
 #ifdef CONFIG_CPU_BIG_ENDIAN
 	unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
-		     pad1:11, atomic1:1, ver:8;
+		     pad1:12, ver:8;
 #else
-	unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
+	unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
 		     ldd:1, pad2:4, div_rem:4;
 #endif
 };
 	struct cpuinfo_arc_mmu mmu;
 	struct cpuinfo_arc_bpu bpu;
 	struct bcr_identity core;
-	struct bcr_isa isa;
+	struct bcr_isa_arcv2 isa;
 	const char *details, *name;
 	unsigned int vec_base;
 	struct cpuinfo_arc_ccm iccm, dccm;
 	struct {
 		unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
-			     fpu_sp:1, fpu_dp:1, pad2:6,
+			     fpu_sp:1, fpu_dp:1, dual_iss_enb:1, dual_iss_exist:1, pad2:4,
 			     debug:1, ap:1, smart:1, rtt:1, pad3:4,
 			     timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
 	} extn;

arch/arc/include/asm/processor.h+0−3

@@ -78,9 +78,6 @@ struct task_struct; · 77 unmodified lines
78		78
79	#endif	79	#endif
80		80
81	#define copy_segments(tsk, mm) do { } while (0)
82	#define release_segments(mm) do { } while (0)
83
84	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->ret)	81	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->ret)
85	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp)	82	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp)
86		83

arch/arc/kernel/setup.c+25−7

 	{ 0x51, "R2.0" },
 	{ 0x52, "R2.1" },
 	{ 0x53, "R3.0" },
+	{ 0x54, "R4.0" },
 #endif
 	{ 0x00, NULL   }
 };
 #else
 	{ 0x40, "ARC EM"  },
 	{ 0x50, "ARC HS38"  },
+	{ 0x54, "ARC HS48"  },
 #endif
 	{ 0x00, "Unknown"   }
 };
 	struct bcr_generic bcr;
 	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
 	const struct id_to_str *tbl;
+	struct bcr_isa_arcv2 isa;
 	FIX_PTR(cpu);
 	READ_BCR(AUX_IDENTITY, cpu->core);
-	READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
 	for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
 		if (cpu->core.family == tbl->id) {
 	}
 	for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
-		if ((cpu->core.family & 0xF0) == tbl->id)
+		if ((cpu->core.family & 0xF4) == tbl->id)
 			break;
 	}
 	cpu->name = tbl->str;
 		cpu->bpu.full = bpu.ft;
 		cpu->bpu.num_cache = 256 << bpu.bce;
 		cpu->bpu.num_pred = 2048 << bpu.pte;
+		if (cpu->core.family >= 0x54) {
+			unsigned int exec_ctrl;
+			READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
+			cpu->extn.dual_iss_exist = 1;
+			cpu->extn.dual_iss_enb = exec_ctrl & 1;
+		}
 	}
 	READ_BCR(ARC_REG_AP_BCR, bcr);
 	cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
+	READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
 	/* some hacks for lack of feature BCR info in old ARC700 cores */
 	if (is_isa_arcompact()) {
-		if (!cpu->isa.ver)	/* ISA BCR absent, use Kconfig info */
+		if (!isa.ver)	/* ISA BCR absent, use Kconfig info */
 			cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
-		else
+		else {
-			cpu->isa.atomic = cpu->isa.atomic1;
+			/* ARC700_BUILD only has 2 bits of isa info */
+			struct bcr_generic bcr = *(struct bcr_generic *)&isa;
+			cpu->isa.atomic = bcr.info & 1;
+		}
 		cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
 		 /* there's no direct way to distinguish 750 vs. 770 */
 		if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
 			cpu->name = "ARC750";
+	} else {
+		cpu->isa = isa;
 	}
 }
 		       "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
 		       core->family, core->cpu_id, core->chip_id);
-	n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s\n",
+	n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
 		       cpu_id, cpu->name, cpu->details,
 		       is_isa_arcompact() ? "ARCompact" : "ARCv2",
-		       IS_AVAIL1(cpu->isa.be, "[Big-Endian]"));
+		       IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
+		       IS_AVAIL3(cpu->extn.dual_iss_exist, cpu->extn.dual_iss_enb, " Dual-Issue"));
 	n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
 		       IS_AVAIL1(cpu->extn.timer0, "Timer0 "),

arch/arc/plat-axs10x/axs10x.c+7−0

@@ -111,6 +111,13 @@ static void __init axs10x_early_init(void) · 110 unmodified lines
111		111
112	axs10x_enable_gpio_intc_wire();	112	axs10x_enable_gpio_intc_wire();
113		113
		114	/*
		115	* Reset ethernet IP core.
		116	* TODO: get rid of this quirk after axs10x reset driver (or simple
		117	* reset driver) will be available in upstream.
		118	*/
		119	iowrite32((1 << 5), (void __iomem *) CREG_MB_SW_RESET);
		120
114	scnprintf(mb, 32, "MainBoard v%d", mb_rev);	121	scnprintf(mb, 32, "MainBoard v%d", mb_rev);
115	axs10x_print_board_ver(CREG_MB_VER, mb);	122	axs10x_print_board_ver(CREG_MB_VER, mb);
116	}	123	}

arch/arc/plat-hsdk/Kconfig+2−1

@@ -6,4 +6,5 @@ · 5 unmodified lines
6	#	6	#
7		7
8	menuconfig ARC_SOC_HSDK	8	menuconfig ARC_SOC_HSDK
9	bool "ARC HS Development Kit SOC"	9	bool "ARC HS Development Kit SOC"
		10	select CLK_HSDK

arch/arc/plat-hsdk/platform.c+42−0

@@ -38,6 +38,42 @@ static void __init hsdk_init_per_cpu(unsigned int cpu) · 37 unmodified lines
38	#define CREG_PAE (CREG_BASE + 0x180)	38	#define CREG_PAE (CREG_BASE + 0x180)
39	#define CREG_PAE_UPDATE (CREG_BASE + 0x194)	39	#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
40		40
		41	#define CREG_CORE_IF_CLK_DIV (CREG_BASE + 0x4B8)
		42	#define CREG_CORE_IF_CLK_DIV_2 0x1
		43	#define CGU_BASE ARC_PERIPHERAL_BASE
		44	#define CGU_PLL_STATUS (ARC_PERIPHERAL_BASE + 0x4)
		45	#define CGU_PLL_CTRL (ARC_PERIPHERAL_BASE + 0x0)
		46	#define CGU_PLL_STATUS_LOCK BIT(0)
		47	#define CGU_PLL_STATUS_ERR BIT(1)
		48	#define CGU_PLL_CTRL_1GHZ 0x3A10
		49	#define HSDK_PLL_LOCK_TIMEOUT 500
		50
		51	#define HSDK_PLL_LOCKED() \
		52	!!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK)
		53
		54	#define HSDK_PLL_ERR() \
		55	!!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR)
		56
		57	static void __init hsdk_set_cpu_freq_1ghz(void)
		58	{
		59	u32 timeout = HSDK_PLL_LOCK_TIMEOUT;
		60
		61	/*
		62	* As we set cpu clock which exceeds 500MHz, the divider for the interface
		63	* clock must be programmed to div-by-2.
		64	*/
		65	iowrite32(CREG_CORE_IF_CLK_DIV_2, (void __iomem *) CREG_CORE_IF_CLK_DIV);
		66
		67	/* Set cpu clock to 1GHz */
		68	iowrite32(CGU_PLL_CTRL_1GHZ, (void __iomem *) CGU_PLL_CTRL);
		69
		70	while (!HSDK_PLL_LOCKED() && timeout--)
		71	cpu_relax();
		72
		73	if (!HSDK_PLL_LOCKED() \|\| HSDK_PLL_ERR())
		74	pr_err("Failed to setup CPU frequency to 1GHz!");
		75	}
		76
41	static void __init hsdk_init_early(void)	77	static void __init hsdk_init_early(void)
42	{	78	{
43	/*	79	/*
@@ -52,6 +88,12 @@ static void __init hsdk_init_early(void) · 8 unmodified lines
52		88
53	/* Really apply settings made above */	89	/* Really apply settings made above */
54	writel(1, (void __iomem *) CREG_PAE_UPDATE);	90	writel(1, (void __iomem *) CREG_PAE_UPDATE);
		91
		92	/*
		93	* Setup CPU frequency to 1GHz.
		94	* TODO: remove it after smart hsdk pll driver will be introduced.
		95	*/
		96	hsdk_set_cpu_freq_1ghz();
55	}	97	}
56		98
57	static const char *hsdk_compat[] __initconst = {	99	static const char *hsdk_compat[] __initconst = {

arch/arm/boot/dts/am33xx.dtsi+2−0

@@ -36,6 +36,8 @@ · 35 unmodified lines
36	phy1 = &usb1_phy;	36	phy1 = &usb1_phy;
37	ethernet0 = &cpsw_emac0;	37	ethernet0 = &cpsw_emac0;
38	ethernet1 = &cpsw_emac1;	38	ethernet1 = &cpsw_emac1;
		39	spi0 = &spi0;
		40	spi1 = &spi1;
39	};	41	};
40		42
41	cpus {	43	cpus {

arch/arm/boot/dts/am43x-epos-evm.dts+1−5

 	pinctrl-0 = <&cpsw_default>;
 	pinctrl-1 = <&cpsw_sleep>;
 	status = "okay";
+	slaves = <1>;
 };
 &davinci_mdio {
 	phy-mode = "rmii";
 };
-&cpsw_emac1 {
-	phy_id = <&davinci_mdio>, <1>;
-	phy-mode = "rmii";
-};
 &phy_sel {
 	rmii-clock-ext;
 };

arch/arm/boot/dts/at91-sama5d27_som1_ek.dts+11−8

 		usb1: ohci@00400000 {
 			num-ports = <3>;
-			atmel,vbus-gpio = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>;
+			atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */
+					   &pioA PIN_PA27 GPIO_ACTIVE_HIGH
+					   0
+					  >;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usb_default>;
 			status = "okay";
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_mikrobus2_uart>;
 				atmel,use-dma-rx;
-				atmel-use-dma-tx;
+				atmel,use-dma-tx;
 				status = "okay";
 			};
 			uart4: serial@fc00c000 {
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
-				pinctrl-name = "default";
+				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_mikrobus1_uart>;
 				status = "okay";
 			};
 				};
 				pinctrl_led_gpio_default: led_gpio_default {
-					pinmux = <PIN_PA27__GPIO>,
+					pinmux = <PIN_PA10__GPIO>,
 						 <PIN_PB1__GPIO>,
 						 <PIN_PA31__GPIO>;
 					bias-pull-up;
 				};
 				pinctrl_usb_default: usb_default {
-					pinmux = <PIN_PA10__GPIO>,
+					pinmux = <PIN_PA27__GPIO>,
 						 <PIN_PD19__GPIO>;
 					bias-disable;
 				};
 		red {
 			label = "red";
-			gpios = <&pioA PIN_PA27 GPIO_ACTIVE_LOW>;
+			gpios = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>;
 		};
 		green {
 			label = "green";
-			gpios = <&pioA PIN_PB1 GPIO_ACTIVE_LOW>;
+			gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>;
 		};
 		blue {
 			label = "blue";
-			gpios = <&pioA PIN_PA31 GPIO_ACTIVE_LOW>;
+			gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 	};

arch/arm/boot/dts/da850-evm.dts+7−0

@@ -15,6 +15,13 @@ · 14 unmodified lines
15	compatible = "ti,da850-evm", "ti,da850";	15	compatible = "ti,da850-evm", "ti,da850";
16	model = "DA850/AM1808/OMAP-L138 EVM";	16	model = "DA850/AM1808/OMAP-L138 EVM";
17		17
		18	aliases {
		19	serial0 = &serial0;
		20	serial1 = &serial1;
		21	serial2 = &serial2;
		22	ethernet0 = &eth0;
		23	};
		24
18	soc@1c00000 {	25	soc@1c00000 {
19	pmx_core: pinmux@14120 {	26	pmx_core: pinmux@14120 {
20	status = "okay";	27	status = "okay";

arch/arm/boot/dts/dra7xx-clocks.dtsi+2−0

@@ -1817,6 +1817,8 @@ · 1816 unmodified lines
1817	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;	1817	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1818	ti,bit-shift = <24>;	1818	ti,bit-shift = <24>;
1819	reg = <0x1868>;	1819	reg = <0x1868>;
		1820	assigned-clocks = <&mcasp3_ahclkx_mux>;
		1821	assigned-clock-parents = <&abe_24m_fclk>;
1820	};	1822	};
1821		1823
1822	mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {	1824	mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {

arch/arm/boot/dts/omap3-n900.dts+0−11

 		io-channel-names = "temp", "bsi", "vbat";
 	};
-	rear_camera: camera@0 {
-		compatible = "linux,camera";
-		module {
-			model = "TCM8341MD";
-			sensor = <&cam1>;
-		};
-	};
 	pwm9: dmtimer-pwm {
 		compatible = "ti,omap-dmtimer-pwm";
 		#pwm-cells = <3>;
 				clock-lanes = <1>;
 				data-lanes = <0>;
 				lane-polarity = <0 0>;
-				clock-inv = <0>;
 				/* Select strobe = <1> for back camera, <0> for front camera */
 				strobe = <1>;
-				crc = <0>;
 			};
 		};
 	};

arch/arm/boot/dts/omap3-n950-n9.dtsi+7−3

 	clock-frequency = <400000>;
 	as3645a@30 {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		reg = <0x30>;
 		compatible = "ams,as3645a";
-		flash {
+		flash@0 {
+			reg = <0x0>;
 			flash-timeout-us = <150000>;
 			flash-max-microamp = <320000>;
 			led-max-microamp = <60000>;
-			peak-current-limit = <1750000>;
+			ams,input-max-microamp = <1750000>;
 		};
-		indicator {
+		indicator@1 {
+			reg = <0x1>;
 			led-max-microamp = <10000>;
 		};
 	};

arch/arm/boot/dts/stm32429i-eval.dts+2−3

 /dts-v1/;
 #include "stm32f429.dtsi"
+#include "stm32f429-pinctrl.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 	stmpe1600: stmpe1600@42 {
 		compatible = "st,stmpe1600";
 		reg = <0x42>;
-		irq-gpio = <&gpioi 8 0>;
-		irq-trigger = <3>;
 		interrupts = <8 3>;
-		interrupt-parent = <&exti>;
+		interrupt-parent = <&gpioi>;
 		interrupt-controller;
 		wakeup-source;

arch/arm/boot/dts/stm32f4-pinctrl.dtsi+343−0

@@ -0,0 +1,343 @@
	1	/*
	2	* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
	44	#include <dt-bindings/mfd/stm32f4-rcc.h>
	45
	46	/ {
	47	soc {
	48	pinctrl: pin-controller {
	49	#address-cells = <1>;
	50	#size-cells = <1>;
	51	ranges = <0 0x40020000 0x3000>;
	52	interrupt-parent = <&exti>;
	53	st,syscfg = <&syscfg 0x8>;
	54	pins-are-numbered;
	55
	56	gpioa: gpio@40020000 {
	57	gpio-controller;
	58	#gpio-cells = <2>;
	59	interrupt-controller;
	60	#interrupt-cells = <2>;
	61	reg = <0x0 0x400>;
	62	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
	63	st,bank-name = "GPIOA";
	64	};
	65
	66	gpiob: gpio@40020400 {
	67	gpio-controller;
	68	#gpio-cells = <2>;
	69	interrupt-controller;
	70	#interrupt-cells = <2>;
	71	reg = <0x400 0x400>;
	72	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
	73	st,bank-name = "GPIOB";
	74	};
	75
	76	gpioc: gpio@40020800 {
	77	gpio-controller;
	78	#gpio-cells = <2>;
	79	interrupt-controller;
	80	#interrupt-cells = <2>;
	81	reg = <0x800 0x400>;
	82	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
	83	st,bank-name = "GPIOC";
	84	};
	85
	86	gpiod: gpio@40020c00 {
	87	gpio-controller;
	88	#gpio-cells = <2>;
	89	interrupt-controller;
	90	#interrupt-cells = <2>;
	91	reg = <0xc00 0x400>;
	92	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
	93	st,bank-name = "GPIOD";
	94	};
	95
	96	gpioe: gpio@40021000 {
	97	gpio-controller;
	98	#gpio-cells = <2>;
	99	interrupt-controller;
	100	#interrupt-cells = <2>;
	101	reg = <0x1000 0x400>;
	102	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
	103	st,bank-name = "GPIOE";
	104	};
	105
	106	gpiof: gpio@40021400 {
	107	gpio-controller;
	108	#gpio-cells = <2>;
	109	interrupt-controller;
	110	#interrupt-cells = <2>;
	111	reg = <0x1400 0x400>;
	112	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
	113	st,bank-name = "GPIOF";
	114	};
	115
	116	gpiog: gpio@40021800 {
	117	gpio-controller;
	118	#gpio-cells = <2>;
	119	interrupt-controller;
	120	#interrupt-cells = <2>;
	121	reg = <0x1800 0x400>;
	122	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
	123	st,bank-name = "GPIOG";
	124	};
	125
	126	gpioh: gpio@40021c00 {
	127	gpio-controller;
	128	#gpio-cells = <2>;
	129	interrupt-controller;
	130	#interrupt-cells = <2>;
	131	reg = <0x1c00 0x400>;
	132	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
	133	st,bank-name = "GPIOH";
	134	};
	135
	136	gpioi: gpio@40022000 {
	137	gpio-controller;
	138	#gpio-cells = <2>;
	139	interrupt-controller;
	140	#interrupt-cells = <2>;
	141	reg = <0x2000 0x400>;
	142	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
	143	st,bank-name = "GPIOI";
	144	};
	145
	146	gpioj: gpio@40022400 {
	147	gpio-controller;
	148	#gpio-cells = <2>;
	149	interrupt-controller;
	150	#interrupt-cells = <2>;
	151	reg = <0x2400 0x400>;
	152	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
	153	st,bank-name = "GPIOJ";
	154	};
	155
	156	gpiok: gpio@40022800 {
	157	gpio-controller;
	158	#gpio-cells = <2>;
	159	interrupt-controller;
	160	#interrupt-cells = <2>;
	161	reg = <0x2800 0x400>;
	162	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
	163	st,bank-name = "GPIOK";
	164	};
	165
	166	usart1_pins_a: usart1@0 {
	167	pins1 {
	168	pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
	169	bias-disable;
	170	drive-push-pull;
	171	slew-rate = <0>;
	172	};
	173	pins2 {
	174	pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
	175	bias-disable;
	176	};
	177	};
	178
	179	usart3_pins_a: usart3@0 {
	180	pins1 {
	181	pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
	182	bias-disable;
	183	drive-push-pull;
	184	slew-rate = <0>;
	185	};
	186	pins2 {
	187	pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
	188	bias-disable;
	189	};
	190	};
	191
	192	usbotg_fs_pins_a: usbotg_fs@0 {
	193	pins {
	194	pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
	195	<STM32F429_PA11_FUNC_OTG_FS_DM>,
	196	<STM32F429_PA12_FUNC_OTG_FS_DP>;
	197	bias-disable;
	198	drive-push-pull;
	199	slew-rate = <2>;
	200	};
	201	};
	202
	203	usbotg_fs_pins_b: usbotg_fs@1 {
	204	pins {
	205	pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
	206	<STM32F429_PB14_FUNC_OTG_HS_DM>,
	207	<STM32F429_PB15_FUNC_OTG_HS_DP>;
	208	bias-disable;
	209	drive-push-pull;
	210	slew-rate = <2>;
	211	};
	212	};
	213
	214	usbotg_hs_pins_a: usbotg_hs@0 {
	215	pins {
	216	pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
	217	<STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
	218	<STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
	219	<STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
	220	<STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
	221	<STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
	222	<STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
	223	<STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
	224	<STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
	225	<STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
	226	<STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
	227	<STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
	228	bias-disable;
	229	drive-push-pull;
	230	slew-rate = <2>;
	231	};
	232	};
	233
	234	ethernet_mii: mii@0 {
	235	pins {
	236	pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
	237	<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
	238	<STM32F429_PC2_FUNC_ETH_MII_TXD2>,
	239	<STM32F429_PB8_FUNC_ETH_MII_TXD3>,
	240	<STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
	241	<STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
	242	<STM32F429_PA2_FUNC_ETH_MDIO>,
	243	<STM32F429_PC1_FUNC_ETH_MDC>,
	244	<STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
	245	<STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
	246	<STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
	247	<STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
	248	<STM32F429_PH6_FUNC_ETH_MII_RXD2>,
	249	<STM32F429_PH7_FUNC_ETH_MII_RXD3>;
	250	slew-rate = <2>;
	251	};
	252	};
	253
	254	adc3_in8_pin: adc@200 {
	255	pins {
	256	pinmux = <STM32F429_PF10_FUNC_ANALOG>;
	257	};
	258	};
	259
	260	pwm1_pins: pwm@1 {
	261	pins {
	262	pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
	263	<STM32F429_PB13_FUNC_TIM1_CH1N>,
	264	<STM32F429_PB12_FUNC_TIM1_BKIN>;
	265	};
	266	};
	267
	268	pwm3_pins: pwm@3 {
	269	pins {
	270	pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
	271	<STM32F429_PB5_FUNC_TIM3_CH2>;
	272	};
	273	};
	274
	275	i2c1_pins: i2c1@0 {
	276	pins {
	277	pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
	278	<STM32F429_PB6_FUNC_I2C1_SCL>;
	279	bias-disable;
	280	drive-open-drain;
	281	slew-rate = <3>;
	282	};
	283	};
	284
	285	ltdc_pins: ltdc@0 {
	286	pins {
	287	pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
	288	<STM32F429_PI13_FUNC_LCD_VSYNC>,
	289	<STM32F429_PI14_FUNC_LCD_CLK>,
	290	<STM32F429_PI15_FUNC_LCD_R0>,
	291	<STM32F429_PJ0_FUNC_LCD_R1>,
	292	<STM32F429_PJ1_FUNC_LCD_R2>,
	293	<STM32F429_PJ2_FUNC_LCD_R3>,
	294	<STM32F429_PJ3_FUNC_LCD_R4>,
	295	<STM32F429_PJ4_FUNC_LCD_R5>,
	296	<STM32F429_PJ5_FUNC_LCD_R6>,
	297	<STM32F429_PJ6_FUNC_LCD_R7>,
	298	<STM32F429_PJ7_FUNC_LCD_G0>,
	299	<STM32F429_PJ8_FUNC_LCD_G1>,
	300	<STM32F429_PJ9_FUNC_LCD_G2>,
	301	<STM32F429_PJ10_FUNC_LCD_G3>,
	302	<STM32F429_PJ11_FUNC_LCD_G4>,
	303	<STM32F429_PJ12_FUNC_LCD_B0>,
	304	<STM32F429_PJ13_FUNC_LCD_B1>,
	305	<STM32F429_PJ14_FUNC_LCD_B2>,
	306	<STM32F429_PJ15_FUNC_LCD_B3>,
	307	<STM32F429_PK0_FUNC_LCD_G5>,
	308	<STM32F429_PK1_FUNC_LCD_G6>,
	309	<STM32F429_PK2_FUNC_LCD_G7>,
	310	<STM32F429_PK3_FUNC_LCD_B4>,
	311	<STM32F429_PK4_FUNC_LCD_B5>,
	312	<STM32F429_PK5_FUNC_LCD_B6>,
	313	<STM32F429_PK6_FUNC_LCD_B7>,
	314	<STM32F429_PK7_FUNC_LCD_DE>;
	315	slew-rate = <2>;
	316	};
	317	};
	318
	319	dcmi_pins: dcmi@0 {
	320	pins {
	321	pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
	322	<STM32F429_PB7_FUNC_DCMI_VSYNC>,
	323	<STM32F429_PA6_FUNC_DCMI_PIXCLK>,
	324	<STM32F429_PC6_FUNC_DCMI_D0>,
	325	<STM32F429_PC7_FUNC_DCMI_D1>,
	326	<STM32F429_PC8_FUNC_DCMI_D2>,
	327	<STM32F429_PC9_FUNC_DCMI_D3>,
	328	<STM32F429_PC11_FUNC_DCMI_D4>,
	329	<STM32F429_PD3_FUNC_DCMI_D5>,
	330	<STM32F429_PB8_FUNC_DCMI_D6>,
	331	<STM32F429_PE6_FUNC_DCMI_D7>,
	332	<STM32F429_PC10_FUNC_DCMI_D8>,
	333	<STM32F429_PC12_FUNC_DCMI_D9>,
	334	<STM32F429_PD6_FUNC_DCMI_D10>,
	335	<STM32F429_PD2_FUNC_DCMI_D11>;
	336	bias-disable;
	337	drive-push-pull;
	338	slew-rate = <3>;
	339	};
	340	};
	341	};
	342	};
	343	};

arch/arm/boot/dts/stm32f429-disco.dts+1−0

@@ -47,6 +47,7 @@ · 46 unmodified lines
47		47
48	/dts-v1/;	48	/dts-v1/;
49	#include "stm32f429.dtsi"	49	#include "stm32f429.dtsi"
		50	#include "stm32f429-pinctrl.dtsi"
50	#include <dt-bindings/input/input.h>	51	#include <dt-bindings/input/input.h>
51		52
52	/ {	53	/ {

arch/arm/boot/dts/stm32f429-pinctrl.dtsi+95−0

@@ -0,0 +1,95 @@
	1	/*
	2	* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	#include "stm32f4-pinctrl.dtsi"
	44
	45	/ {
	46	soc {
	47	pinctrl: pin-controller {
	48	compatible = "st,stm32f429-pinctrl";
	49
	50	gpioa: gpio@40020000 {
	51	gpio-ranges = <&pinctrl 0 0 16>;
	52	};
	53
	54	gpiob: gpio@40020400 {
	55	gpio-ranges = <&pinctrl 0 16 16>;
	56	};
	57
	58	gpioc: gpio@40020800 {
	59	gpio-ranges = <&pinctrl 0 32 16>;
	60	};
	61
	62	gpiod: gpio@40020c00 {
	63	gpio-ranges = <&pinctrl 0 48 16>;
	64	};
	65
	66	gpioe: gpio@40021000 {
	67	gpio-ranges = <&pinctrl 0 64 16>;
	68	};
	69
	70	gpiof: gpio@40021400 {
	71	gpio-ranges = <&pinctrl 0 80 16>;
	72	};
	73
	74	gpiog: gpio@40021800 {
	75	gpio-ranges = <&pinctrl 0 96 16>;
	76	};
	77
	78	gpioh: gpio@40021c00 {
	79	gpio-ranges = <&pinctrl 0 112 16>;
	80	};
	81
	82	gpioi: gpio@40022000 {
	83	gpio-ranges = <&pinctrl 0 128 16>;
	84	};
	85
	86	gpioj: gpio@40022400 {
	87	gpio-ranges = <&pinctrl 0 144 16>;
	88	};
	89
	90	gpiok: gpio@40022800 {
	91	gpio-ranges = <&pinctrl 0 160 8>;
	92	};
	93	};
	94	};
	95	};

arch/arm/boot/dts/stm32f429.dtsi+0−297

@@ -47,7 +47,6 @@ · 46 unmodified lines
47		47
48	#include "skeleton.dtsi"	48	#include "skeleton.dtsi"
49	#include "armv7-m.dtsi"	49	#include "armv7-m.dtsi"
50	#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
51	#include <dt-bindings/clock/stm32fx-clock.h>	50	#include <dt-bindings/clock/stm32fx-clock.h>
52	#include <dt-bindings/mfd/stm32f4-rcc.h>	51	#include <dt-bindings/mfd/stm32f4-rcc.h>
53		52
@@ -591,302 +590,6 @@ · 537 unmodified lines
591	status = "disabled";	590	status = "disabled";
592	};	591	};
593		592
594	pinctrl: pin-controller {
595	#address-cells = <1>;
596	#size-cells = <1>;
597	compatible = "st,stm32f429-pinctrl";
598	ranges = <0 0x40020000 0x3000>;
599	interrupt-parent = <&exti>;
600	st,syscfg = <&syscfg 0x8>;
601	pins-are-numbered;
602
603	gpioa: gpio@40020000 {
604	gpio-controller;
605	#gpio-cells = <2>;
606	interrupt-controller;
607	#interrupt-cells = <2>;
608	reg = <0x0 0x400>;
609	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
610	st,bank-name = "GPIOA";
611	};
612
613	gpiob: gpio@40020400 {
614	gpio-controller;
615	#gpio-cells = <2>;
616	interrupt-controller;
617	#interrupt-cells = <2>;
618	reg = <0x400 0x400>;
619	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
620	st,bank-name = "GPIOB";
621	};
622
623	gpioc: gpio@40020800 {
624	gpio-controller;
625	#gpio-cells = <2>;
626	interrupt-controller;
627	#interrupt-cells = <2>;
628	reg = <0x800 0x400>;
629	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
630	st,bank-name = "GPIOC";
631	};
632
633	gpiod: gpio@40020c00 {
634	gpio-controller;
635	#gpio-cells = <2>;
636	interrupt-controller;
637	#interrupt-cells = <2>;
638	reg = <0xc00 0x400>;
639	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
640	st,bank-name = "GPIOD";
641	};
642
643	gpioe: gpio@40021000 {
644	gpio-controller;
645	#gpio-cells = <2>;
646	interrupt-controller;
647	#interrupt-cells = <2>;
648	reg = <0x1000 0x400>;
649	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
650	st,bank-name = "GPIOE";
651	};
652
653	gpiof: gpio@40021400 {
654	gpio-controller;
655	#gpio-cells = <2>;
656	interrupt-controller;
657	#interrupt-cells = <2>;
658	reg = <0x1400 0x400>;
659	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
660	st,bank-name = "GPIOF";
661	};
662
663	gpiog: gpio@40021800 {
664	gpio-controller;
665	#gpio-cells = <2>;
666	interrupt-controller;
667	#interrupt-cells = <2>;
668	reg = <0x1800 0x400>;
669	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
670	st,bank-name = "GPIOG";
671	};
672
673	gpioh: gpio@40021c00 {
674	gpio-controller;
675	#gpio-cells = <2>;
676	interrupt-controller;
677	#interrupt-cells = <2>;
678	reg = <0x1c00 0x400>;
679	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
680	st,bank-name = "GPIOH";
681	};
682
683	gpioi: gpio@40022000 {
684	gpio-controller;
685	#gpio-cells = <2>;
686	interrupt-controller;
687	#interrupt-cells = <2>;
688	reg = <0x2000 0x400>;
689	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
690	st,bank-name = "GPIOI";
691	};
692
693	gpioj: gpio@40022400 {
694	gpio-controller;
695	#gpio-cells = <2>;
696	interrupt-controller;
697	#interrupt-cells = <2>;
698	reg = <0x2400 0x400>;
699	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
700	st,bank-name = "GPIOJ";
701	};
702
703	gpiok: gpio@40022800 {
704	gpio-controller;
705	#gpio-cells = <2>;
706	interrupt-controller;
707	#interrupt-cells = <2>;
708	reg = <0x2800 0x400>;
709	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
710	st,bank-name = "GPIOK";
711	};
712
713	usart1_pins_a: usart1@0 {
714	pins1 {
715	pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
716	bias-disable;
717	drive-push-pull;
718	slew-rate = <0>;
719	};
720	pins2 {
721	pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
722	bias-disable;
723	};
724	};
725
726	usart3_pins_a: usart3@0 {
727	pins1 {
728	pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
729	bias-disable;
730	drive-push-pull;
731	slew-rate = <0>;
732	};
733	pins2 {
734	pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
735	bias-disable;
736	};
737	};
738
739	usbotg_fs_pins_a: usbotg_fs@0 {
740	pins {
741	pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
742	<STM32F429_PA11_FUNC_OTG_FS_DM>,
743	<STM32F429_PA12_FUNC_OTG_FS_DP>;
744	bias-disable;
745	drive-push-pull;
746	slew-rate = <2>;
747	};
748	};
749
750	usbotg_fs_pins_b: usbotg_fs@1 {
751	pins {
752	pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
753	<STM32F429_PB14_FUNC_OTG_HS_DM>,
754	<STM32F429_PB15_FUNC_OTG_HS_DP>;
755	bias-disable;
756	drive-push-pull;
757	slew-rate = <2>;
758	};
759	};
760
761	usbotg_hs_pins_a: usbotg_hs@0 {
762	pins {
763	pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
764	<STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
765	<STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
766	<STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
767	<STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
768	<STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
769	<STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
770	<STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
771	<STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
772	<STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
773	<STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
774	<STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
775	bias-disable;
776	drive-push-pull;
777	slew-rate = <2>;
778	};
779	};
780
781	ethernet_mii: mii@0 {
782	pins {
783	pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
784	<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
785	<STM32F429_PC2_FUNC_ETH_MII_TXD2>,
786	<STM32F429_PB8_FUNC_ETH_MII_TXD3>,
787	<STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
788	<STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
789	<STM32F429_PA2_FUNC_ETH_MDIO>,
790	<STM32F429_PC1_FUNC_ETH_MDC>,
791	<STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
792	<STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
793	<STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
794	<STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
795	<STM32F429_PH6_FUNC_ETH_MII_RXD2>,
796	<STM32F429_PH7_FUNC_ETH_MII_RXD3>;
797	slew-rate = <2>;
798	};
799	};
800
801	adc3_in8_pin: adc@200 {
802	pins {
803	pinmux = <STM32F429_PF10_FUNC_ANALOG>;
804	};
805	};
806
807	pwm1_pins: pwm@1 {
808	pins {
809	pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
810	<STM32F429_PB13_FUNC_TIM1_CH1N>,
811	<STM32F429_PB12_FUNC_TIM1_BKIN>;
812	};
813	};
814
815	pwm3_pins: pwm@3 {
816	pins {
817	pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
818	<STM32F429_PB5_FUNC_TIM3_CH2>;
819	};
820	};
821
822	i2c1_pins: i2c1@0 {
823	pins {
824	pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
825	<STM32F429_PB6_FUNC_I2C1_SCL>;
826	bias-disable;
827	drive-open-drain;
828	slew-rate = <3>;
829	};
830	};
831
832	ltdc_pins: ltdc@0 {
833	pins {
834	pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
835	<STM32F429_PI13_FUNC_LCD_VSYNC>,
836	<STM32F429_PI14_FUNC_LCD_CLK>,
837	<STM32F429_PI15_FUNC_LCD_R0>,
838	<STM32F429_PJ0_FUNC_LCD_R1>,
839	<STM32F429_PJ1_FUNC_LCD_R2>,
840	<STM32F429_PJ2_FUNC_LCD_R3>,
841	<STM32F429_PJ3_FUNC_LCD_R4>,
842	<STM32F429_PJ4_FUNC_LCD_R5>,
843	<STM32F429_PJ5_FUNC_LCD_R6>,
844	<STM32F429_PJ6_FUNC_LCD_R7>,
845	<STM32F429_PJ7_FUNC_LCD_G0>,
846	<STM32F429_PJ8_FUNC_LCD_G1>,
847	<STM32F429_PJ9_FUNC_LCD_G2>,
848	<STM32F429_PJ10_FUNC_LCD_G3>,
849	<STM32F429_PJ11_FUNC_LCD_G4>,
850	<STM32F429_PJ12_FUNC_LCD_B0>,
851	<STM32F429_PJ13_FUNC_LCD_B1>,
852	<STM32F429_PJ14_FUNC_LCD_B2>,
853	<STM32F429_PJ15_FUNC_LCD_B3>,
854	<STM32F429_PK0_FUNC_LCD_G5>,
855	<STM32F429_PK1_FUNC_LCD_G6>,
856	<STM32F429_PK2_FUNC_LCD_G7>,
857	<STM32F429_PK3_FUNC_LCD_B4>,
858	<STM32F429_PK4_FUNC_LCD_B5>,
859	<STM32F429_PK5_FUNC_LCD_B6>,
860	<STM32F429_PK6_FUNC_LCD_B7>,
861	<STM32F429_PK7_FUNC_LCD_DE>;
862	slew-rate = <2>;
863	};
864	};
865
866	dcmi_pins: dcmi@0 {
867	pins {
868	pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
869	<STM32F429_PB7_FUNC_DCMI_VSYNC>,
870	<STM32F429_PA6_FUNC_DCMI_PIXCLK>,
871	<STM32F429_PC6_FUNC_DCMI_D0>,
872	<STM32F429_PC7_FUNC_DCMI_D1>,
873	<STM32F429_PC8_FUNC_DCMI_D2>,
874	<STM32F429_PC9_FUNC_DCMI_D3>,
875	<STM32F429_PC11_FUNC_DCMI_D4>,
876	<STM32F429_PD3_FUNC_DCMI_D5>,
877	<STM32F429_PB8_FUNC_DCMI_D6>,
878	<STM32F429_PE6_FUNC_DCMI_D7>,
879	<STM32F429_PC10_FUNC_DCMI_D8>,
880	<STM32F429_PC12_FUNC_DCMI_D9>,
881	<STM32F429_PD6_FUNC_DCMI_D10>,
882	<STM32F429_PD2_FUNC_DCMI_D11>;
883	bias-disable;
884	drive-push-pull;
885	slew-rate = <3>;
886	};
887	};
888	};
889
890	crc: crc@40023000 {	593	crc: crc@40023000 {
891	compatible = "st,stm32f4-crc";	594	compatible = "st,stm32f4-crc";
892	reg = <0x40023000 0x400>;	595	reg = <0x40023000 0x400>;

arch/arm/boot/dts/stm32f469-disco.dts+1−0

@@ -47,6 +47,7 @@ · 46 unmodified lines
47		47
48	/dts-v1/;	48	/dts-v1/;
49	#include "stm32f429.dtsi"	49	#include "stm32f429.dtsi"
		50	#include "stm32f469-pinctrl.dtsi"
50		51
51	/ {	52	/ {
52	model = "STMicroelectronics STM32F469i-DISCO board";	53	model = "STMicroelectronics STM32F469i-DISCO board";

arch/arm/boot/dts/stm32f469-pinctrl.dtsi+96−0

@@ -0,0 +1,96 @@
	1	/*
	2	* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	#include "stm32f4-pinctrl.dtsi"
	44
	45	/ {
	46	soc {
	47	pinctrl: pin-controller {
	48	compatible = "st,stm32f469-pinctrl";
	49
	50	gpioa: gpio@40020000 {
	51	gpio-ranges = <&pinctrl 0 0 16>;
	52	};
	53
	54	gpiob: gpio@40020400 {
	55	gpio-ranges = <&pinctrl 0 16 16>;
	56	};
	57
	58	gpioc: gpio@40020800 {
	59	gpio-ranges = <&pinctrl 0 32 16>;
	60	};
	61
	62	gpiod: gpio@40020c00 {
	63	gpio-ranges = <&pinctrl 0 48 16>;
	64	};
	65
	66	gpioe: gpio@40021000 {
	67	gpio-ranges = <&pinctrl 0 64 16>;
	68	};
	69
	70	gpiof: gpio@40021400 {
	71	gpio-ranges = <&pinctrl 0 80 16>;
	72	};
	73
	74	gpiog: gpio@40021800 {
	75	gpio-ranges = <&pinctrl 0 96 16>;
	76	};
	77
	78	gpioh: gpio@40021c00 {
	79	gpio-ranges = <&pinctrl 0 112 16>;
	80	};
	81
	82	gpioi: gpio@40022000 {
	83	gpio-ranges = <&pinctrl 0 128 16>;
	84	};
	85
	86	gpioj: gpio@40022400 {
	87	gpio-ranges = <&pinctrl 0 144 6>,
	88	<&pinctrl 12 156 4>;
	89	};
	90
	91	gpiok: gpio@40022800 {
	92	gpio-ranges = <&pinctrl 3 163 5>;
	93	};
	94	};
	95	};
	96	};

arch/arm/configs/gemini_defconfig+2−1

 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_ATA=y
+CONFIG_PATA_FTIDE010=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_GEMINI=y
 CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
 # CONFIG_DNOTIFY is not set
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y

arch/arm/configs/pxa_defconfig+1−1

@@ -471,7 +471,7 @@ CONFIG_LCD_PLATFORM=m · 470 unmodified lines
471	CONFIG_LCD_TOSA=m	471	CONFIG_LCD_TOSA=m
472	CONFIG_BACKLIGHT_PWM=m	472	CONFIG_BACKLIGHT_PWM=m
473	CONFIG_BACKLIGHT_TOSA=m	473	CONFIG_BACKLIGHT_TOSA=m
474	CONFIG_FRAMEBUFFER_CONSOLE=m	474	CONFIG_FRAMEBUFFER_CONSOLE=y
475	CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y	475	CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
476	CONFIG_LOGO=y	476	CONFIG_LOGO=y
477	CONFIG_SOUND=m	477	CONFIG_SOUND=m

arch/arm/configs/viper_defconfig+1−1

@@ -113,7 +113,7 @@ CONFIG_FB_PXA_PARAMETERS=y · 112 unmodified lines
113	CONFIG_BACKLIGHT_LCD_SUPPORT=y	113	CONFIG_BACKLIGHT_LCD_SUPPORT=y
114	CONFIG_BACKLIGHT_PWM=m	114	CONFIG_BACKLIGHT_PWM=m
115	# CONFIG_VGA_CONSOLE is not set	115	# CONFIG_VGA_CONSOLE is not set
116	CONFIG_FRAMEBUFFER_CONSOLE=m	116	CONFIG_FRAMEBUFFER_CONSOLE=y
117	CONFIG_LOGO=y	117	CONFIG_LOGO=y
118	CONFIG_SOUND=m	118	CONFIG_SOUND=m
119	CONFIG_SND=m	119	CONFIG_SND=m

arch/arm/configs/zeus_defconfig+1−1

@@ -112,7 +112,7 @@ CONFIG_FB_PXA=m · 111 unmodified lines
112	CONFIG_FB_PXA_PARAMETERS=y	112	CONFIG_FB_PXA_PARAMETERS=y
113	CONFIG_BACKLIGHT_LCD_SUPPORT=y	113	CONFIG_BACKLIGHT_LCD_SUPPORT=y
114	# CONFIG_VGA_CONSOLE is not set	114	# CONFIG_VGA_CONSOLE is not set
115	CONFIG_FRAMEBUFFER_CONSOLE=m	115	CONFIG_FRAMEBUFFER_CONSOLE=y
116	CONFIG_LOGO=y	116	CONFIG_LOGO=y
117	CONFIG_SOUND=m	117	CONFIG_SOUND=m
118	CONFIG_SND=m	118	CONFIG_SND=m

arch/arm/include/asm/thread_info.h+6−9

 #define TIF_NEED_RESCHED	1	/* rescheduling necessary */
 #define TIF_NOTIFY_RESUME	2	/* callback before returning to user */
 #define TIF_UPROBE		3	/* breakpointed or singlestepping */
-#define TIF_FSCHECK		4	/* Check FS is USER_DS on return */
+#define TIF_SYSCALL_TRACE	4	/* syscall trace active */
-#define TIF_SYSCALL_TRACE	5	/* syscall trace active */
+#define TIF_SYSCALL_AUDIT	5	/* syscall auditing active */
-#define TIF_SYSCALL_AUDIT	6	/* syscall auditing active */
+#define TIF_SYSCALL_TRACEPOINT	6	/* syscall tracepoint instrumentation */
-#define TIF_SYSCALL_TRACEPOINT	7	/* syscall tracepoint instrumentation */
+#define TIF_SECCOMP		7	/* seccomp syscall filtering active */
-#define TIF_SECCOMP		8	/* seccomp syscall filtering active */
 #define TIF_NOHZ		12	/* in adaptive nohz mode */
 #define TIF_USING_IWMMXT	17
 #define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
 #define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)
 #define _TIF_UPROBE		(1 << TIF_UPROBE)
-#define _TIF_FSCHECK		(1 << TIF_FSCHECK)
 #define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
 #define _TIF_SYSCALL_AUDIT	(1 << TIF_SYSCALL_AUDIT)
 #define _TIF_SYSCALL_TRACEPOINT	(1 << TIF_SYSCALL_TRACEPOINT)
 /*
  * Change these and you break ASM code in entry-common.S
  */
-#define _TIF_WORK_MASK		(_TIF_NEED_RESCHED | _TIF_SIGPENDING |	\
+#define _TIF_WORK_MASK		(_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
-				 _TIF_NOTIFY_RESUME | _TIF_UPROBE |	\
+				 _TIF_NOTIFY_RESUME | _TIF_UPROBE)
-				 _TIF_FSCHECK)
 #endif /* __KERNEL__ */
 #endif /* __ASM_ARM_THREAD_INFO_H */

arch/arm/include/asm/uaccess.h+0−2

@@ -70,8 +70,6 @@ static inline void set_fs(mm_segment_t fs) · 69 unmodified lines
70	{	70	{
71	current_thread_info()->addr_limit = fs;	71	current_thread_info()->addr_limit = fs;
72	modify_domain(DOMAIN_KERNEL, fs ? DOMAIN_CLIENT : DOMAIN_MANAGER);	72	modify_domain(DOMAIN_KERNEL, fs ? DOMAIN_CLIENT : DOMAIN_MANAGER);
73	/* On user-mode return, check fs is correct */
74	set_thread_flag(TIF_FSCHECK);
75	}	73	}
76		74
77	#define segment_eq(a, b) ((a) == (b))	75	#define segment_eq(a, b) ((a) == (b))

arch/arm/kernel/entry-common.S+13−7

 #include <asm/unistd.h>
 #include <asm/ftrace.h>
 #include <asm/unwind.h>
+#include <asm/memory.h>
 #ifdef CONFIG_AEABI
 #include <asm/unistd-oabi.h>
 #endif
  UNWIND(.fnstart	)
  UNWIND(.cantunwind	)
 	disable_irq_notrace			@ disable interrupts
+	ldr	r2, [tsk, #TI_ADDR_LIMIT]
+	cmp	r2, #TASK_SIZE
+	blne	addr_limit_check_failed
 	ldr	r1, [tsk, #TI_FLAGS]		@ re-check for syscall tracing
-	tst	r1, #_TIF_SYSCALL_WORK
+	tst	r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
-	bne	fast_work_pending
-	tst	r1, #_TIF_WORK_MASK
 	bne	fast_work_pending
 	/* perform architecture specific actions before user return */
 	arch_ret_to_user r1, lr
  UNWIND(.cantunwind	)
 	str	r0, [sp, #S_R0 + S_OFF]!	@ save returned r0
 	disable_irq_notrace			@ disable interrupts
+	ldr	r2, [tsk, #TI_ADDR_LIMIT]
+	cmp	r2, #TASK_SIZE
+	blne	addr_limit_check_failed
 	ldr	r1, [tsk, #TI_FLAGS]		@ re-check for syscall tracing
-	tst	r1, #_TIF_SYSCALL_WORK
+	tst	r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
-	bne	fast_work_pending
-	tst	r1, #_TIF_WORK_MASK
 	beq	no_work_pending
  UNWIND(.fnend		)
 ENDPROC(ret_fast_syscall)
 	/* Slower path - fall through to work_pending */
-fast_work_pending:
 #endif
 	tst	r1, #_TIF_SYSCALL_WORK
 ret_slow_syscall:
 	disable_irq_notrace			@ disable interrupts
 ENTRY(ret_to_user_from_irq)
+	ldr	r2, [tsk, #TI_ADDR_LIMIT]
+	cmp	r2, #TASK_SIZE
+	blne	addr_limit_check_failed
 	ldr	r1, [tsk, #TI_FLAGS]
 	tst	r1, #_TIF_WORK_MASK
 	bne	slow_work_pending

arch/arm/kernel/signal.c+6−4

 	 * Update the trace code with the current status.
 	 */
 	trace_hardirqs_off();
-	/* Check valid user FS if needed */
-	addr_limit_user_check();
 	do {
 		if (likely(thread_flags & _TIF_NEED_RESCHED)) {
 			schedule();
 	return page;
 }
+/* Defer to generic check */
+asmlinkage void addr_limit_check_failed(void)
+{
+	addr_limit_user_check();
+}

arch/arm/mach-at91/pm.c+2−2

@@ -533,8 +533,8 @@ static void __init at91_pm_backup_init(void) · 532 unmodified lines
533	}	533	}
534		534
535	pm_bu->suspended = 0;	535	pm_bu->suspended = 0;
536	pm_bu->canary = virt_to_phys(&canary);	536	pm_bu->canary = __pa_symbol(&canary);
537	pm_bu->resume = virt_to_phys(cpu_resume);	537	pm_bu->resume = __pa_symbol(cpu_resume);
538		538
539	return;	539	return;
540		540

arch/arm/mach-omap2/hsmmc.c+2−2

@@ -58,10 +58,10 @@ void omap_hsmmc_late_init(struct omap2_hsmmc_info *c) · 57 unmodified lines
58	struct platform_device *pdev;	58	struct platform_device *pdev;
59	int res;	59	int res;
60		60
61	if (omap_hsmmc_done != 1)	61	if (omap_hsmmc_done)
62	return;	62	return;
63		63
64	omap_hsmmc_done++;	64	omap_hsmmc_done = 1;
65		65
66	for (; c->mmc; c++) {	66	for (; c->mmc; c++) {
67	pdev = c->pdev;	67	pdev = c->pdev;

arch/arm/mach-omap2/omap_hwmod_7xx_data.c+1−0

@@ -839,6 +839,7 @@ static struct omap_hwmod dra7xx_gpio1_hwmod = { · 838 unmodified lines
839	.name = "gpio1",	839	.name = "gpio1",
840	.class = &dra7xx_gpio_hwmod_class,	840	.class = &dra7xx_gpio_hwmod_class,
841	.clkdm_name = "wkupaon_clkdm",	841	.clkdm_name = "wkupaon_clkdm",
		842	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
842	.main_clk = "wkupaon_iclk_mux",	843	.main_clk = "wkupaon_iclk_mux",
843	.prcm = {	844	.prcm = {
844	.omap4 = {	845	.omap4 = {

arch/arm64/Makefile+5−0

 KBUILD_CFLAGS	+= $(call cc-option, -mpc-relative-literal-loads)
 KBUILD_AFLAGS	+= $(lseinstr) $(brokengasinst)
+KBUILD_CFLAGS	+= $(call cc-option,-mabi=lp64)
+KBUILD_AFLAGS	+= $(call cc-option,-mabi=lp64)
 ifeq ($(CONFIG_CPU_BIG_ENDIAN), y)
 KBUILD_CPPFLAGS	+= -mbig-endian
 CHECKFLAGS	+= -D__AARCH64EB__
 AS		+= -EB
 LD		+= -EB
+LDFLAGS		+= -maarch64linuxb
 UTS_MACHINE	:= aarch64_be
 else
 KBUILD_CPPFLAGS	+= -mlittle-endian
 CHECKFLAGS	+= -D__AARCH64EL__
 AS		+= -EL
 LD		+= -EL
+LDFLAGS		+= -maarch64linux
 UTS_MACHINE	:= aarch64
 endif

arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi+6−4

 &sd_emmc_a {
 	status = "okay";
 	pinctrl-0 = <&sdio_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	#address-cells = <1>;
 	#size-cells = <0>;
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <4>;
 	cap-sd-highspeed;
 &sd_emmc_c {
 	status = "okay";
 	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <8>;
-	cap-sd-highspeed;
 	cap-mmc-highspeed;
 	max-frequency = <200000000>;
 	non-removable;

arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts+14−5

 		states = <3300000 0>,
 		         <1800000 1>;
+		regulator-settling-time-up-us = <100>;
+		regulator-settling-time-down-us = <5000>;
 	};
 	wifi_32k: wifi-32k {
 &sd_emmc_a {
 	status = "okay";
 	pinctrl-0 = <&sdio_pins>, <&sdio_irq_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	#address-cells = <1>;
 	#size-cells = <0>;
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <4>;
 	cap-sd-highspeed;
-	max-frequency = <100000000>;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	max-frequency = <200000000>;
 	disable-wp;
 	cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
 &sd_emmc_c {
 	status = "disabled";
 	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <8>;
-	cap-sd-highspeed;
 	max-frequency = <200000000>;
 	non-removable;
 	disable-wp;

arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts+7−5

 / {
 	compatible = "nexbox,a95x", "amlogic,meson-gxbb";
 	model = "NEXBOX A95X";
 	aliases {
 		serial0 = &uart_AO;
 	};
 &sd_emmc_a {
 	status = "okay";
 	pinctrl-0 = <&sdio_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	#address-cells = <1>;
 	#size-cells = <0>;
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <4>;
 	cap-sd-highspeed;
 &sd_emmc_c {
 	status = "okay";
 	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <8>;
-	cap-sd-highspeed;
 	cap-mmc-highspeed;
 	max-frequency = <200000000>;
 	non-removable;

arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts+5−4

 / {
 	compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
 	model = "Hardkernel ODROID-C2";
 	aliases {
 		serial0 = &uart_AO;
 	};
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <4>;
 	cap-sd-highspeed;
 &sd_emmc_c {
 	status = "okay";
 	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <8>;
-	cap-sd-highspeed;
 	max-frequency = <200000000>;
 	non-removable;
 	disable-wp;

arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi+9−4

 &sd_emmc_a {
 	status = "okay";
 	pinctrl-0 = <&sdio_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	#address-cells = <1>;
 	#size-cells = <0>;
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <4>;
 	cap-sd-highspeed;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
 	max-frequency = <100000000>;
 	disable-wp;
 &sd_emmc_c {
 	status = "okay";
 	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <8>;
-	cap-sd-highspeed;
 	cap-mmc-highspeed;
 	max-frequency = <200000000>;
 	non-removable;

arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi+6−4

 &sd_emmc_a {
 	status = "okay";
 	pinctrl-0 = <&sdio_pins &sdio_irq_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	#address-cells = <1>;
 	#size-cells = <0>;
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <4>;
 	cap-sd-highspeed;
 &sd_emmc_c {
 	status = "okay";
 	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <8>;
-	cap-sd-highspeed;
 	cap-mmc-highspeed;
 	max-frequency = <200000000>;
 	non-removable;

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi+36−3

 			};
 		};
+		emmc_clk_gate_pins: emmc_clk_gate {
+			mux {
+				groups = "BOOT_8";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "BOOT_8";
+				bias-pull-down;
+			};
+		};
 		nor_pins: nor {
 			mux {
 				groups = "nor_d",
 			};
 		};
+		sdcard_clk_gate_pins: sdcard_clk_gate {
+			mux {
+				groups = "CARD_2";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "CARD_2";
+				bias-pull-down;
+			};
+		};
 		sdio_pins: sdio {
 			mux {
 				groups = "sdio_d0",
 			};
 		};
+		sdio_clk_gate_pins: sdio_clk_gate {
+			mux {
+				groups = "GPIOX_4";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "GPIOX_4";
+				bias-pull-down;
+			};
+		};
 		sdio_irq_pins: sdio_irq {
 			mux {
 				groups = "sdio_irq";
 &sd_emmc_a {
 	clocks = <&clkc CLKID_SD_EMMC_A>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_A_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };
 &sd_emmc_b {
 	clocks = <&clkc CLKID_SD_EMMC_B>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_B_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };
 &sd_emmc_c {
 	clocks = <&clkc CLKID_SD_EMMC_C>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_C_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };

arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts+4−3

 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <4>;
 	cap-sd-highspeed;
 &sd_emmc_c {
 	status = "okay";
 	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <8>;
-	cap-sd-highspeed;
 	cap-mmc-highspeed;
 	max-frequency = <100000000>;
 	non-removable;

arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts+11−2

 		states = <3300000 0>,
 			 <1800000 1>;
+		regulator-settling-time-up-us = <200>;
+		regulator-settling-time-down-us = <50000>;
 	};
 	vddio_boot: regulator-vddio_boot {
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <4>;
 	cap-sd-highspeed;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
 	max-frequency = <100000000>;
 	disable-wp;
 &sd_emmc_c {
 	status = "okay";
 	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	mmc-ddr-3_3v;
 	max-frequency = <50000000>;
 	non-removable;
 	disable-wp;

arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts+6−4

 &sd_emmc_a {
 	status = "okay";
 	pinctrl-0 = <&sdio_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	#address-cells = <1>;
 	#size-cells = <0>;
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <4>;
 	cap-sd-highspeed;
 &sd_emmc_c {
 	status = "okay";
 	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <8>;
-	cap-sd-highspeed;
 	cap-mmc-highspeed;
 	max-frequency = <200000000>;
 	non-removable;

arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi+6−4

 &sd_emmc_a {
 	status = "okay";
 	pinctrl-0 = <&sdio_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	#address-cells = <1>;
 	#size-cells = <0>;
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <4>;
 	cap-sd-highspeed;
 &sd_emmc_c {
 	status = "okay";
 	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <8>;
-	cap-sd-highspeed;
 	cap-mmc-highspeed;
 	max-frequency = <200000000>;
 	non-removable;

arch/arm64/boot/dts/amlogic/meson-gxl.dtsi+36−3

 			};
 		};
+		emmc_clk_gate_pins: emmc_clk_gate {
+			mux {
+				groups = "BOOT_8";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "BOOT_8";
+				bias-pull-down;
+			};
+		};
 		nor_pins: nor {
 			mux {
 				groups = "nor_d",
 			};
 		};
+		sdcard_clk_gate_pins: sdcard_clk_gate {
+			mux {
+				groups = "CARD_2";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "CARD_2";
+				bias-pull-down;
+			};
+		};
 		sdio_pins: sdio {
 			mux {
 				groups = "sdio_d0",
 			};
 		};
+		sdio_clk_gate_pins: sdio_clk_gate {
+			mux {
+				groups = "GPIOX_4";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "GPIOX_4";
+				bias-pull-down;
+			};
+		};
 		sdio_irq_pins: sdio_irq {
 			mux {
 				groups = "sdio_irq";
 &sd_emmc_a {
 	clocks = <&clkc CLKID_SD_EMMC_A>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_A_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };
 &sd_emmc_b {
 	clocks = <&clkc CLKID_SD_EMMC_B>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_B_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
 };
 &sd_emmc_c {
 	clocks = <&clkc CLKID_SD_EMMC_C>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_C_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };

arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts+4−3

 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <4>;
 	cap-sd-highspeed;
 &sd_emmc_c {
 	status = "okay";
 	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	bus-width = <8>;
-	cap-sd-highspeed;
 	cap-mmc-highspeed;
 	max-frequency = <200000000>;
 	non-removable;

arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts+0−1

@@ -220,7 +220,6 @@ · 219 unmodified lines
220	pinctrl-names = "default";	220	pinctrl-names = "default";
221		221
222	bus-width = <8>;	222	bus-width = <8>;
223	cap-sd-highspeed;
224	cap-mmc-highspeed;	223	cap-mmc-highspeed;
225	max-frequency = <200000000>;	224	max-frequency = <200000000>;
226	non-removable;	225	non-removable;

arch/arm64/boot/dts/marvell/armada-ap806.dtsi+2−2

@@ -254,7 +254,7 @@ · 253 unmodified lines
254		254
255	ap_syscon: system-controller@6f4000 {	255	ap_syscon: system-controller@6f4000 {
256	compatible = "syscon", "simple-mfd";	256	compatible = "syscon", "simple-mfd";
257	reg = <0x6f4000 0x1000>;	257	reg = <0x6f4000 0x2000>;
258		258
259	ap_clk: clock {	259	ap_clk: clock {
260	compatible = "marvell,ap806-clock";	260	compatible = "marvell,ap806-clock";
@@ -265,7 +265,7 @@ · 4 unmodified lines
265	compatible = "marvell,ap806-pinctrl";	265	compatible = "marvell,ap806-pinctrl";
266	};	266	};
267		267
268	ap_gpio: gpio {	268	ap_gpio: gpio@1040 {
269	compatible = "marvell,armada-8k-gpio";	269	compatible = "marvell,armada-8k-gpio";
270	offset = <0x1040>;	270	offset = <0x1040>;
271	ngpios = <20>;	271	ngpios = <20>;

arch/arm64/boot/dts/rockchip/rk3368.dtsi+2−70

@@ -113,8 +113,7 @@ · 112 unmodified lines
113	compatible = "arm,cortex-a53", "arm,armv8";	113	compatible = "arm,cortex-a53", "arm,armv8";
114	reg = <0x0 0x0>;	114	reg = <0x0 0x0>;
115	enable-method = "psci";	115	enable-method = "psci";
116	clocks = <&cru ARMCLKL>;	116
117	operating-points-v2 = <&cluster0_opp>;
118	#cooling-cells = <2>; /* min followed by max */	117	#cooling-cells = <2>; /* min followed by max */
119	};	118	};
120		119
@@ -123,8 +122,6 @@ · 2 unmodified lines
123	compatible = "arm,cortex-a53", "arm,armv8";	122	compatible = "arm,cortex-a53", "arm,armv8";
124	reg = <0x0 0x1>;	123	reg = <0x0 0x1>;
125	enable-method = "psci";	124	enable-method = "psci";
126	clocks = <&cru ARMCLKL>;
127	operating-points-v2 = <&cluster0_opp>;
128	};	125	};
129		126
130	cpu_l2: cpu@2 {	127	cpu_l2: cpu@2 {
@@ -132,8 +129,6 @@ · 1 unmodified line
132	compatible = "arm,cortex-a53", "arm,armv8";	129	compatible = "arm,cortex-a53", "arm,armv8";
133	reg = <0x0 0x2>;	130	reg = <0x0 0x2>;
134	enable-method = "psci";	131	enable-method = "psci";
135	clocks = <&cru ARMCLKL>;
136	operating-points-v2 = <&cluster0_opp>;
137	};	132	};
138		133
139	cpu_l3: cpu@3 {	134	cpu_l3: cpu@3 {
@@ -141,8 +136,6 @@ · 1 unmodified line
141	compatible = "arm,cortex-a53", "arm,armv8";	136	compatible = "arm,cortex-a53", "arm,armv8";
142	reg = <0x0 0x3>;	137	reg = <0x0 0x3>;
143	enable-method = "psci";	138	enable-method = "psci";
144	clocks = <&cru ARMCLKL>;
145	operating-points-v2 = <&cluster0_opp>;
146	};	139	};
147		140
148	cpu_b0: cpu@100 {	141	cpu_b0: cpu@100 {
@@ -150,8 +143,7 @@ · 1 unmodified line
150	compatible = "arm,cortex-a53", "arm,armv8";	143	compatible = "arm,cortex-a53", "arm,armv8";
151	reg = <0x0 0x100>;	144	reg = <0x0 0x100>;
152	enable-method = "psci";	145	enable-method = "psci";
153	clocks = <&cru ARMCLKB>;	146
154	operating-points-v2 = <&cluster1_opp>;
155	#cooling-cells = <2>; /* min followed by max */	147	#cooling-cells = <2>; /* min followed by max */
156	};	148	};
157		149
@@ -160,8 +152,6 @@ · 2 unmodified lines
160	compatible = "arm,cortex-a53", "arm,armv8";	152	compatible = "arm,cortex-a53", "arm,armv8";
161	reg = <0x0 0x101>;	153	reg = <0x0 0x101>;
162	enable-method = "psci";	154	enable-method = "psci";
163	clocks = <&cru ARMCLKB>;
164	operating-points-v2 = <&cluster1_opp>;
165	};	155	};
166		156
167	cpu_b2: cpu@102 {	157	cpu_b2: cpu@102 {
@@ -169,8 +159,6 @@ · 1 unmodified line
169	compatible = "arm,cortex-a53", "arm,armv8";	159	compatible = "arm,cortex-a53", "arm,armv8";
170	reg = <0x0 0x102>;	160	reg = <0x0 0x102>;
171	enable-method = "psci";	161	enable-method = "psci";
172	clocks = <&cru ARMCLKB>;
173	operating-points-v2 = <&cluster1_opp>;
174	};	162	};
175		163
176	cpu_b3: cpu@103 {	164	cpu_b3: cpu@103 {
@@ -178,62 +166,6 @@ · 1 unmodified line
178	compatible = "arm,cortex-a53", "arm,armv8";	166	compatible = "arm,cortex-a53", "arm,armv8";
179	reg = <0x0 0x103>;	167	reg = <0x0 0x103>;
180	enable-method = "psci";	168	enable-method = "psci";
181	clocks = <&cru ARMCLKB>;
182	operating-points-v2 = <&cluster1_opp>;
183	};
184	};
185
186	cluster0_opp: opp-table0 {
187	compatible = "operating-points-v2";
188	opp-shared;
189
190	opp00 {
191	opp-hz = /bits/ 64 <312000000>;
192	opp-microvolt = <950000>;
193	clock-latency-ns = <40000>;
194	};
195	opp01 {
196	opp-hz = /bits/ 64 <408000000>;
197	opp-microvolt = <950000>;
198	};
199	opp02 {
200	opp-hz = /bits/ 64 <600000000>;
201	opp-microvolt = <950000>;
202	};
203	opp03 {
204	opp-hz = /bits/ 64 <816000000>;
205	opp-microvolt = <1025000>;
206	};
207	opp04 {
208	opp-hz = /bits/ 64 <1008000000>;
209	opp-microvolt = <1125000>;
210	};
211	};
212
213	cluster1_opp: opp-table1 {
214	compatible = "operating-points-v2";
215	opp-shared;
216
217	opp00 {
218	opp-hz = /bits/ 64 <312000000>;
219	opp-microvolt = <950000>;
220	clock-latency-ns = <40000>;
221	};
222	opp01 {
223	opp-hz = /bits/ 64 <408000000>;
224	opp-microvolt = <950000>;
225	};
226	opp02 {
227	opp-hz = /bits/ 64 <600000000>;
228	opp-microvolt = <950000>;
229	};
230	opp03 {
231	opp-hz = /bits/ 64 <816000000>;
232	opp-microvolt = <975000>;
233	};
234	opp04 {
235	opp-hz = /bits/ 64 <1008000000>;
236	opp-microvolt = <1050000>;
237	};	169	};
238	};	170	};
239		171

arch/arm64/boot/dts/rockchip/rk3399.dtsi+3−3

@@ -1629,9 +1629,9 @@ · 1628 unmodified lines
1629	compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";	1629	compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1630	reg = <0x0 0xff960000 0x0 0x8000>;	1630	reg = <0x0 0xff960000 0x0 0x8000>;
1631	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;	1631	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1632	clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,	1632	clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1633	<&cru SCLK_DPHY_TX0_CFG>;	1633	<&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1634	clock-names = "ref", "pclk", "phy_cfg";	1634	clock-names = "ref", "pclk", "phy_cfg", "grf";
1635	power-domains = <&power RK3399_PD_VIO>;	1635	power-domains = <&power RK3399_PD_VIO>;
1636	rockchip,grf = <&grf>;	1636	rockchip,grf = <&grf>;
1637	status = "disabled";	1637	status = "disabled";

arch/arm64/include/asm/linkage.h+2−2

@@ -1,7 +1,7 @@
1	#ifndef __ASM_LINKAGE_H	1	#ifndef __ASM_LINKAGE_H
2	#define __ASM_LINKAGE_H	2	#define __ASM_LINKAGE_H
3		3
4	#define __ALIGN .align 4	4	#define __ALIGN .align 2
5	#define __ALIGN_STR ".align 4"	5	#define __ALIGN_STR ".align 2"
6		6
7	#endif	7	#endif

arch/arm64/include/asm/memory.h+6−3

 #define KERNEL_END        _end
 /*
- * The size of the KASAN shadow region. This should be 1/8th of the
+ * KASAN requires 1/8th of the kernel virtual address space for the shadow
- * size of the entire kernel virtual address space.
+ * region. KASAN can bloat the stack significantly, so double the (minimum)
+ * stack size when KASAN is in use.
  */
 #ifdef CONFIG_KASAN
 #define KASAN_SHADOW_SIZE	(UL(1) << (VA_BITS - 3))
+#define KASAN_THREAD_SHIFT	1
 #else
 #define KASAN_SHADOW_SIZE	(0)
+#define KASAN_THREAD_SHIFT	0
 #endif
-#define MIN_THREAD_SHIFT	14
+#define MIN_THREAD_SHIFT	(14 + KASAN_THREAD_SHIFT)
 /*
  * VMAP'd stacks are allocated at page granularity, so we must ensure that such

arch/arm64/include/asm/pgtable.h+1−1

@@ -401,7 +401,7 @@ static inline phys_addr_t pmd_page_paddr(pmd_t pmd) · 400 unmodified lines
401	/* Find an entry in the third-level page table. */	401	/* Find an entry in the third-level page table. */
402	#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))	402	#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
403		403
404	#define pte_offset_phys(dir,addr) (pmd_page_paddr((dir)) + pte_index(addr) sizeof(pte_t))	404	#define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE((dir))) + pte_index(addr) sizeof(pte_t))
405	#define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr))))	405	#define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr))))
406		406
407	#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))	407	#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))

arch/arm64/kernel/armv8_deprecated.c+1−1

@@ -649,4 +649,4 @@ static int __init armv8_deprecated_init(void) · 648 unmodified lines
649	return 0;	649	return 0;
650	}	650	}
651		651
652	late_initcall(armv8_deprecated_init);	652	core_initcall(armv8_deprecated_init);

arch/arm64/kernel/cpufeature.c+1−1

@@ -1307,4 +1307,4 @@ static int __init enable_mrs_emulation(void) · 1306 unmodified lines
1307	return 0;	1307	return 0;
1308	}	1308	}
1309		1309
1310	late_initcall(enable_mrs_emulation);	1310	core_initcall(enable_mrs_emulation);

arch/arm64/kernel/fpsimd.c+5−1

 }
 EXPORT_SYMBOL(kernel_neon_end);
+#ifdef CONFIG_EFI
 static DEFINE_PER_CPU(struct fpsimd_state, efi_fpsimd_state);
 static DEFINE_PER_CPU(bool, efi_fpsimd_state_used);
 		kernel_neon_end();
 }
+#endif /* CONFIG_EFI */
 #endif /* CONFIG_KERNEL_MODE_NEON */
 #ifdef CONFIG_CPU_PM
 	return 0;
 }
-late_initcall(fpsimd_init);
+core_initcall(fpsimd_init);

arch/arm64/kernel/head.S+1−0

@@ -384,6 +384,7 @@ ENTRY(kimage_vaddr) · 383 unmodified lines
384	* booted in EL1 or EL2 respectively.	384	* booted in EL1 or EL2 respectively.
385	*/	385	*/
386	ENTRY(el2_setup)	386	ENTRY(el2_setup)
		387	msr SPsel, #1 // We want to use SP_EL{1,2}
387	mrs x0, CurrentEL	388	mrs x0, CurrentEL
388	cmp x0, #CurrentEL_EL2	389	cmp x0, #CurrentEL_EL2
389	b.eq 1f	390	b.eq 1f

arch/arm64/kernel/signal.c+3−3

 	 */
 	trace_hardirqs_off();
-	/* Check valid user FS if needed */
-	addr_limit_user_check();
 	do {
+		/* Check valid user FS if needed */
+		addr_limit_user_check();
 		if (thread_flags & _TIF_NEED_RESCHED) {
 			schedule();
 		} else {

arch/arm64/mm/fault.c+2−2

@@ -97,7 +97,7 @@ static void data_abort_decode(unsigned int esr) · 96 unmodified lines
97	(esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,	97	(esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,
98	(esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);	98	(esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);
99	} else {	99	} else {
100	pr_alert(" ISV = 0, ISS = 0x%08lu\n", esr & ESR_ELx_ISS_MASK);	100	pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK);
101	}	101	}
102		102
103	pr_alert(" CM = %lu, WnR = %lu\n",	103	pr_alert(" CM = %lu, WnR = %lu\n",
@@ -651,7 +651,7 @@ static const struct fault_info fault_info[] = { · 547 unmodified lines
651	{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" },	651	{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" },
652	{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },	652	{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
653	{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },	653	{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
654	{ do_page_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },	654	{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
655	{ do_bad, SIGBUS, 0, "unknown 8" },	655	{ do_bad, SIGBUS, 0, "unknown 8" },
656	{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },	656	{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },
657	{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },	657	{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },

arch/c6x/include/asm/processor.h+0−3

@@ -92,9 +92,6 @@ static inline void release_thread(struct task_struct *dead_task) · 91 unmodified lines
92	{	92	{
93	}	93	}
94		94
95	#define copy_segments(tsk, mm) do { } while (0)
96	#define release_segments(mm) do { } while (0)
97
98	/*	95	/*
99	* saved kernel SP and DP of a blocked thread.	96	* saved kernel SP and DP of a blocked thread.
100	*/	97	*/

arch/frv/include/asm/processor.h+0−4

@@ -92,10 +92,6 @@ static inline void release_thread(struct task_struct *dead_task) · 91 unmodified lines
92	extern asmlinkage void save_user_regs(struct user_context *target);	92	extern asmlinkage void save_user_regs(struct user_context *target);
93	extern asmlinkage void restore_user_regs(const struct user_context target, ...);	93	extern asmlinkage void restore_user_regs(const struct user_context target, ...);
94		94
95	#define copy_segments(tsk, mm) do { } while (0)
96	#define release_segments(mm) do { } while (0)
97	#define forget_segments() do { } while (0)
98
99	unsigned long get_wchan(struct task_struct *p);	95	unsigned long get_wchan(struct task_struct *p);
100		96
101	#define KSTK_EIP(tsk) ((tsk)->thread.frame0->pc)	97	#define KSTK_EIP(tsk) ((tsk)->thread.frame0->pc)

arch/m32r/Kconfig+4−0

 	int "Timer divider (integer)"
 	default "128"
+config CPU_BIG_ENDIAN
+        bool "Generate big endian code"
+	default n
 config CPU_LITTLE_ENDIAN
         bool "Generate little endian code"
 	default n

arch/m32r/include/asm/processor.h+0−8

@@ -118,14 +118,6 @@ struct mm_struct; · 117 unmodified lines
118	/* Free all resources held by a thread. */	118	/* Free all resources held by a thread. */
119	extern void release_thread(struct task_struct *);	119	extern void release_thread(struct task_struct *);
120		120
121	/* Copy and release all segment info associated with a VM */
122	extern void copy_segments(struct task_struct p, struct mm_struct mm);
123	extern void release_segments(struct mm_struct * mm);
124
125	/* Copy and release all segment info associated with a VM */
126	#define copy_segments(p, mm) do { } while (0)
127	#define release_segments(mm) do { } while (0)
128
129	unsigned long get_wchan(struct task_struct *p);	121	unsigned long get_wchan(struct task_struct *p);
130	#define KSTK_EIP(tsk) ((tsk)->thread.lr)	122	#define KSTK_EIP(tsk) ((tsk)->thread.lr)
131	#define KSTK_ESP(tsk) ((tsk)->thread.sp)	123	#define KSTK_ESP(tsk) ((tsk)->thread.sp)

arch/m32r/kernel/traps.c+9−0

@@ -114,6 +114,15 @@ static void set_eit_vector_entries(void) · 113 unmodified lines
114	_flush_cache_copyback_all();	114	_flush_cache_copyback_all();
115	}	115	}
116		116
		117	void abort(void)
		118	{
		119	BUG();
		120
		121	/* if that doesn't kill us, halt */
		122	panic("Oops failed to kill thread");
		123	}
		124	EXPORT_SYMBOL(abort);
		125
117	void __init trap_init(void)	126	void __init trap_init(void)
118	{	127	{
119	set_eit_vector_entries();	128	set_eit_vector_entries();

arch/metag/include/asm/processor.h+0−3

@@ -131,9 +131,6 @@ static inline void release_thread(struct task_struct *dead_task) · 130 unmodified lines
131	{	131	{
132	}	132	}
133		133
134	#define copy_segments(tsk, mm) do { } while (0)
135	#define release_segments(mm) do { } while (0)
136
137	/*	134	/*
138	* Return saved PC of a blocked thread.	135	* Return saved PC of a blocked thread.
139	*/	136	*/

arch/microblaze/Kconfig+1−1

@@ -39,7 +39,7 @@ config MICROBLAZE · 38 unmodified lines
39	# Endianness selection	39	# Endianness selection
40	choice	40	choice
41	prompt "Endianness selection"	41	prompt "Endianness selection"
42	default CPU_BIG_ENDIAN	42	default CPU_LITTLE_ENDIAN
43	help	43	help
44	microblaze architectures can be configured for either little or	44	microblaze architectures can be configured for either little or
45	big endian formats. Be sure to select the appropriate mode.	45	big endian formats. Be sure to select the appropriate mode.

arch/microblaze/include/uapi/asm/Kbuild+1−0

@@ -7,6 +7,7 @@ generic-y += fcntl.h · 6 unmodified lines
7	generic-y += ioctl.h	7	generic-y += ioctl.h
8	generic-y += ioctls.h	8	generic-y += ioctls.h
9	generic-y += ipcbuf.h	9	generic-y += ipcbuf.h
		10	generic-y += kvm_para.h
10	generic-y += mman.h	11	generic-y += mman.h
11	generic-y += msgbuf.h	12	generic-y += msgbuf.h
12	generic-y += param.h	13	generic-y += param.h

arch/microblaze/kernel/dma.c+1−1

@@ -165,7 +165,7 @@ int dma_direct_mmap_coherent(struct device dev, struct vm_area_struct vma, · 164 unmodified lines
165	unsigned long attrs)	165	unsigned long attrs)
166	{	166	{
167	#ifdef CONFIG_MMU	167	#ifdef CONFIG_MMU
168	unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;	168	unsigned long user_count = vma_pages(vma);
169	unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;	169	unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
170	unsigned long off = vma->vm_pgoff;	170	unsigned long off = vma->vm_pgoff;
171	unsigned long pfn;	171	unsigned long pfn;

arch/mips/ath79/pci.c+6−6

@@ -22,10 +22,10 @@ · 21 unmodified lines
22	#include "pci.h"	22	#include "pci.h"
23		23
24	static int (ath79_pci_plat_dev_init)(struct pci_dev dev);	24	static int (ath79_pci_plat_dev_init)(struct pci_dev dev);
25	static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;	25	static const struct ath79_pci_irq *ath79_pci_irq_map;
26	static unsigned ath79_pci_nr_irqs __initdata;	26	static unsigned ath79_pci_nr_irqs;
27		27
28	static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {	28	static const struct ath79_pci_irq ar71xx_pci_irq_map[] = {
29	{	29	{
30	.slot = 17,	30	.slot = 17,
31	.pin = 1,	31	.pin = 1,
@@ -41,7 +41,7 @@ static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { · 9 unmodified lines
41	}	41	}
42	};	42	};
43		43
44	static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = {	44	static const struct ath79_pci_irq ar724x_pci_irq_map[] = {
45	{	45	{
46	.slot = 0,	46	.slot = 0,
47	.pin = 1,	47	.pin = 1,
@@ -49,7 +49,7 @@ static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = { · 1 unmodified line
49	}	49	}
50	};	50	};
51		51
52	static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {	52	static const struct ath79_pci_irq qca955x_pci_irq_map[] = {
53	{	53	{
54	.bus = 0,	54	.bus = 0,
55	.slot = 0,	55	.slot = 0,
@@ -64,7 +64,7 @@ static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = { · 8 unmodified lines
64	},	64	},
65	};	65	};
66		66
67	int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)	67	int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
68	{	68	{
69	int irq = -1;	69	int irq = -1;
70	int i;	70	int i;

arch/mips/include/asm/mipsregs.h+9−6

 #define __write_64bit_c0_split(source, sel, val)			\
 do {									\
+	unsigned long long __tmp;					\
 	unsigned long __flags;						\
 									\
 	local_irq_save(__flags);					\
 	if (sel == 0)							\
 		__asm__ __volatile__(					\
 			".set\tmips64\n\t"				\
-			"dsll\t%L0, %L0, 32\n\t"			\
+			"dsll\t%L0, %L1, 32\n\t"			\
 			"dsrl\t%L0, %L0, 32\n\t"			\
-			"dsll\t%M0, %M0, 32\n\t"			\
+			"dsll\t%M0, %M1, 32\n\t"			\
 			"or\t%L0, %L0, %M0\n\t"				\
 			"dmtc0\t%L0, " #source "\n\t"			\
 			".set\tmips0"					\
-			: : "r" (val));					\
+			: "=&r,r" (__tmp)				\
+			: "r,0" (val));					\
 	else								\
 		__asm__ __volatile__(					\
 			".set\tmips64\n\t"				\
-			"dsll\t%L0, %L0, 32\n\t"			\
+			"dsll\t%L0, %L1, 32\n\t"			\
 			"dsrl\t%L0, %L0, 32\n\t"			\
-			"dsll\t%M0, %M0, 32\n\t"			\
+			"dsll\t%M0, %M1, 32\n\t"			\
 			"or\t%L0, %L0, %M0\n\t"				\
 			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
 			".set\tmips0"					\
-			: : "r" (val));					\
+			: "=&r,r" (__tmp)				\
+			: "r,0" (val));					\
 	local_irq_restore(__flags);					\
 } while (0)

arch/mips/kernel/perf_event_mipsxx.c+1−2

@@ -618,8 +618,7 @@ static int mipspmu_event_init(struct perf_event *event) · 617 unmodified lines
618	return -ENOENT;	618	return -ENOENT;
619	}	619	}
620		620
621	if ((unsigned int)event->cpu >= nr_cpumask_bits \|\|	621	if (event->cpu >= 0 && !cpu_online(event->cpu))
622	(event->cpu >= 0 && !cpu_online(event->cpu)))
623	return -ENODEV;	622	return -ENODEV;
624		623
625	if (!atomic_inc_not_zero(&active_events)) {	624	if (!atomic_inc_not_zero(&active_events)) {

arch/mips/pci/fixup-capcella.c+2−2

@@ -32,13 +32,13 @@ · 31 unmodified lines
32	#define INTC PC104PLUS_INTC_IRQ	32	#define INTC PC104PLUS_INTC_IRQ
33	#define INTD PC104PLUS_INTD_IRQ	33	#define INTD PC104PLUS_INTD_IRQ
34		34
35	static char irq_tab_capcella[][5] __initdata = {	35	static char irq_tab_capcella[][5] = {
36	[11] = { -1, INT1, INT1, INT1, INT1 },	36	[11] = { -1, INT1, INT1, INT1, INT1 },
37	[12] = { -1, INT2, INT2, INT2, INT2 },	37	[12] = { -1, INT2, INT2, INT2, INT2 },
38	[14] = { -1, INTA, INTB, INTC, INTD }	38	[14] = { -1, INTA, INTB, INTC, INTD }
39	};	39	};
40		40
41	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	41	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
42	{	42	{
43	return irq_tab_capcella[slot][pin];	43	return irq_tab_capcella[slot][pin];
44	}	44	}

arch/mips/pci/fixup-cobalt.c+4−4

@@ -147,7 +147,7 @@ static void qube_raq_via_board_id_fixup(struct pci_dev *dev) · 146 unmodified lines
147	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,	147	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
148	qube_raq_via_board_id_fixup);	148	qube_raq_via_board_id_fixup);
149		149
150	static char irq_tab_qube1[] __initdata = {	150	static char irq_tab_qube1[] = {
151	[COBALT_PCICONF_CPU] = 0,	151	[COBALT_PCICONF_CPU] = 0,
152	[COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,	152	[COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
153	[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,	153	[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
@@ -156,7 +156,7 @@ static char irq_tab_qube1[] __initdata = { · 2 unmodified lines
156	[COBALT_PCICONF_ETH1] = 0	156	[COBALT_PCICONF_ETH1] = 0
157	};	157	};
158		158
159	static char irq_tab_cobalt[] __initdata = {	159	static char irq_tab_cobalt[] = {
160	[COBALT_PCICONF_CPU] = 0,	160	[COBALT_PCICONF_CPU] = 0,
161	[COBALT_PCICONF_ETH0] = ETH0_IRQ,	161	[COBALT_PCICONF_ETH0] = ETH0_IRQ,
162	[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,	162	[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
@@ -165,7 +165,7 @@ static char irq_tab_cobalt[] __initdata = { · 2 unmodified lines
165	[COBALT_PCICONF_ETH1] = ETH1_IRQ	165	[COBALT_PCICONF_ETH1] = ETH1_IRQ
166	};	166	};
167		167
168	static char irq_tab_raq2[] __initdata = {	168	static char irq_tab_raq2[] = {
169	[COBALT_PCICONF_CPU] = 0,	169	[COBALT_PCICONF_CPU] = 0,
170	[COBALT_PCICONF_ETH0] = ETH0_IRQ,	170	[COBALT_PCICONF_ETH0] = ETH0_IRQ,
171	[COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,	171	[COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
@@ -174,7 +174,7 @@ static char irq_tab_raq2[] __initdata = { · 2 unmodified lines
174	[COBALT_PCICONF_ETH1] = ETH1_IRQ	174	[COBALT_PCICONF_ETH1] = ETH1_IRQ
175	};	175	};
176		176
177	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	177	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
178	{	178	{
179	if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)	179	if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
180	return irq_tab_qube1[slot];	180	return irq_tab_qube1[slot];

arch/mips/pci/fixup-emma2rh.c+2−2

@@ -43,7 +43,7 @@ · 42 unmodified lines
43	*/	43	*/
44		44
45	#define MAX_SLOT_NUM 10	45	#define MAX_SLOT_NUM 10
46	static unsigned char irq_map[][5] __initdata = {	46	static unsigned char irq_map[][5] = {
47	[3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC,	47	[3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC,
48	MARKEINS_PCI_IRQ_INTD, 0,},	48	MARKEINS_PCI_IRQ_INTD, 0,},
49	[4] = {0, MARKEINS_PCI_IRQ_INTA, 0, 0, 0,},	49	[4] = {0, MARKEINS_PCI_IRQ_INTA, 0, 0, 0,},
@@ -85,7 +85,7 @@ static void emma2rh_pci_host_fixup(struct pci_dev *dev) · 35 unmodified lines
85	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH,	85	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH,
86	emma2rh_pci_host_fixup);	86	emma2rh_pci_host_fixup);
87		87
88	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	88	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
89	{	89	{
90	return irq_map[slot][pin];	90	return irq_map[slot][pin];
91	}	91	}

arch/mips/pci/fixup-fuloong2e.c+1−1

@@ -19,7 +19,7 @@ · 18 unmodified lines
19	/* South bridge slot number is set by the pci probe process */	19	/* South bridge slot number is set by the pci probe process */
20	static u8 sb_slot = 5;	20	static u8 sb_slot = 5;
21		21
22	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	22	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
23	{	23	{
24	int irq = 0;	24	int irq = 0;
25		25

arch/mips/pci/fixup-ip32.c+2−2

@@ -21,7 +21,7 @@ · 20 unmodified lines
21	#define INTB MACEPCI_SHARED0_IRQ	21	#define INTB MACEPCI_SHARED0_IRQ
22	#define INTC MACEPCI_SHARED1_IRQ	22	#define INTC MACEPCI_SHARED1_IRQ
23	#define INTD MACEPCI_SHARED2_IRQ	23	#define INTD MACEPCI_SHARED2_IRQ
24	static char irq_tab_mace[][5] __initdata = {	24	static char irq_tab_mace[][5] = {
25	/* Dummy INT#A INT#B INT#C INT#D */	25	/* Dummy INT#A INT#B INT#C INT#D */
26	{0, 0, 0, 0, 0}, /* This is placeholder row - never used */	26	{0, 0, 0, 0, 0}, /* This is placeholder row - never used */
27	{0, SCSI0, SCSI0, SCSI0, SCSI0},	27	{0, SCSI0, SCSI0, SCSI0, SCSI0},
@@ -39,7 +39,7 @@ static char irq_tab_mace[][5] __initdata = { · 11 unmodified lines
39	* irqs. I suppose a device without a pin A will thank us for doing it	39	* irqs. I suppose a device without a pin A will thank us for doing it
40	* right if there exists such a broken piece of crap.	40	* right if there exists such a broken piece of crap.
41	*/	41	*/
42	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	42	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
43	{	43	{
44	return irq_tab_mace[slot][pin];	44	return irq_tab_mace[slot][pin];
45	}	45	}

arch/mips/pci/fixup-jmr3927.c+1−1

@@ -31,7 +31,7 @@ · 30 unmodified lines
31	#include <asm/txx9/pci.h>	31	#include <asm/txx9/pci.h>
32	#include <asm/txx9/jmr3927.h>	32	#include <asm/txx9/jmr3927.h>
33		33
34	int __init jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	34	int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
35	{	35	{
36	unsigned char irq = pin;	36	unsigned char irq = pin;
37		37

arch/mips/pci/fixup-lantiq.c+1−1

@@ -23,7 +23,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) · 22 unmodified lines
23	return 0;	23	return 0;
24	}	24	}
25		25
26	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	26	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
27	{	27	{
28	return of_irq_parse_and_map_pci(dev, slot, pin);	28	return of_irq_parse_and_map_pci(dev, slot, pin);
29	}	29	}

arch/mips/pci/fixup-lemote2f.c+2−2

@@ -30,7 +30,7 @@ · 29 unmodified lines
30	#define PCID 7	30	#define PCID 7
31		31
32	/* all the pci device has the PCIA pin, check the datasheet. */	32	/* all the pci device has the PCIA pin, check the datasheet. */
33	static char irq_tab[][5] __initdata = {	33	static char irq_tab[][5] = {
34	/* INTA INTB INTC INTD */	34	/* INTA INTB INTC INTD */
35	{0, 0, 0, 0, 0}, /* 11: Unused */	35	{0, 0, 0, 0, 0}, /* 11: Unused */
36	{0, 0, 0, 0, 0}, /* 12: Unused */	36	{0, 0, 0, 0, 0}, /* 12: Unused */
@@ -51,7 +51,7 @@ static char irq_tab[][5] __initdata = { · 14 unmodified lines
51	{0, 0, 0, 0, 0}, /* 27: Unused */	51	{0, 0, 0, 0, 0}, /* 27: Unused */
52	};	52	};
53		53
54	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	54	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
55	{	55	{
56	int virq;	56	int virq;
57		57

arch/mips/pci/fixup-loongson3.c+1−1

@@ -32,7 +32,7 @@ static void print_fixup_info(const struct pci_dev *pdev) · 31 unmodified lines
32	pdev->vendor, pdev->device, pdev->irq);	32	pdev->vendor, pdev->device, pdev->irq);
33	}	33	}
34		34
35	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	35	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
36	{	36	{
37	print_fixup_info(dev);	37	print_fixup_info(dev);
38	return dev->irq;	38	return dev->irq;

arch/mips/pci/fixup-malta.c+2−2

@@ -12,7 +12,7 @@ · 11 unmodified lines
12	static char pci_irq[5] = {	12	static char pci_irq[5] = {
13	};	13	};
14		14
15	static char irq_tab[][5] __initdata = {	15	static char irq_tab[][5] = {
16	/* INTA INTB INTC INTD */	16	/* INTA INTB INTC INTD */
17	{0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */	17	{0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */
18	{0, 0, 0, 0, 0 }, /* 1: Unused */	18	{0, 0, 0, 0, 0 }, /* 1: Unused */
@@ -38,7 +38,7 @@ static char irq_tab[][5] __initdata = { · 19 unmodified lines
38	{0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */	38	{0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */
39	};	39	};
40		40
41	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	41	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
42	{	42	{
43	int virq;	43	int virq;
44	virq = irq_tab[slot][pin];	44	virq = irq_tab[slot][pin];

arch/mips/pci/fixup-mpc30x.c+3−3

@@ -22,19 +22,19 @@ · 21 unmodified lines
22		22
23	#include <asm/vr41xx/mpc30x.h>	23	#include <asm/vr41xx/mpc30x.h>
24		24
25	static const int internal_func_irqs[] __initconst = {	25	static const int internal_func_irqs[] = {
26	VRC4173_CASCADE_IRQ,	26	VRC4173_CASCADE_IRQ,
27	VRC4173_AC97_IRQ,	27	VRC4173_AC97_IRQ,
28	VRC4173_USB_IRQ,	28	VRC4173_USB_IRQ,
29	};	29	};
30		30
31	static const int irq_tab_mpc30x[] __initconst = {	31	static const int irq_tab_mpc30x[] = {
32	[12] = VRC4173_PCMCIA1_IRQ,	32	[12] = VRC4173_PCMCIA1_IRQ,
33	[13] = VRC4173_PCMCIA2_IRQ,	33	[13] = VRC4173_PCMCIA2_IRQ,
34	[29] = MQ200_IRQ,	34	[29] = MQ200_IRQ,
35	};	35	};
36		36
37	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	37	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
38	{	38	{
39	if (slot == 30)	39	if (slot == 30)
40	return internal_func_irqs[PCI_FUNC(dev->devfn)];	40	return internal_func_irqs[PCI_FUNC(dev->devfn)];

arch/mips/pci/fixup-pmcmsp.c+4−4

@@ -47,7 +47,7 @@ · 46 unmodified lines
47		47
48	#if defined(CONFIG_PMC_MSP7120_GW)	48	#if defined(CONFIG_PMC_MSP7120_GW)
49	/* Garibaldi Board IRQ wiring to PCI slots */	49	/* Garibaldi Board IRQ wiring to PCI slots */
50	static char irq_tab[][5] __initdata = {	50	static char irq_tab[][5] = {
51	/* INTA INTB INTC INTD */	51	/* INTA INTB INTC INTD */
52	{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */	52	{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
53	{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */	53	{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
@@ -86,7 +86,7 @@ static char irq_tab[][5] __initdata = { · 32 unmodified lines
86	#elif defined(CONFIG_PMC_MSP7120_EVAL)	86	#elif defined(CONFIG_PMC_MSP7120_EVAL)
87		87
88	/* MSP7120 Eval Board IRQ wiring to PCI slots */	88	/* MSP7120 Eval Board IRQ wiring to PCI slots */
89	static char irq_tab[][5] __initdata = {	89	static char irq_tab[][5] = {
90	/* INTA INTB INTC INTD */	90	/* INTA INTB INTC INTD */
91	{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */	91	{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
92	{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */	92	{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
@@ -125,7 +125,7 @@ static char irq_tab[][5] __initdata = { · 32 unmodified lines
125	#else	125	#else
126		126
127	/* Unknown board -- don't assign any IRQs */	127	/* Unknown board -- don't assign any IRQs */
128	static char irq_tab[][5] __initdata = {	128	static char irq_tab[][5] = {
129	/* INTA INTB INTC INTD */	129	/* INTA INTB INTC INTD */
130	{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */	130	{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
131	{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */	131	{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
@@ -202,7 +202,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) · 70 unmodified lines
202	* RETURNS: IRQ number	202	* RETURNS: IRQ number
203	*	203	*
204	****************************************************************************/	204	****************************************************************************/
205	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	205	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
206	{	206	{
207	#if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL)	207	#if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL)
208	printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n");	208	printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n");

arch/mips/pci/fixup-rbtx4927.c+1−1

@@ -36,7 +36,7 @@ · 35 unmodified lines
36	#include <asm/txx9/pci.h>	36	#include <asm/txx9/pci.h>
37	#include <asm/txx9/rbtx4927.h>	37	#include <asm/txx9/rbtx4927.h>
38		38
39	int __init rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	39	int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
40	{	40	{
41	unsigned char irq = pin;	41	unsigned char irq = pin;
42		42

arch/mips/pci/fixup-rbtx4938.c+1−1

@@ -13,7 +13,7 @@ · 12 unmodified lines
13	#include <asm/txx9/pci.h>	13	#include <asm/txx9/pci.h>
14	#include <asm/txx9/rbtx4938.h>	14	#include <asm/txx9/rbtx4938.h>
15		15
16	int __init rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	16	int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
17	{	17	{
18	int irq = tx4938_pcic1_map_irq(dev, slot);	18	int irq = tx4938_pcic1_map_irq(dev, slot);
19		19

arch/mips/pci/fixup-sni.c+6−6

@@ -40,7 +40,7 @@ · 39 unmodified lines
40	* seem to be a documentation error. At least on my RM200C the Cirrus	40	* seem to be a documentation error. At least on my RM200C the Cirrus
41	* Logic CL-GD5434 VGA is device 3.	41	* Logic CL-GD5434 VGA is device 3.
42	*/	42	*/
43	static char irq_tab_rm200[8][5] __initdata = {	43	static char irq_tab_rm200[8][5] = {
44	/* INTA INTB INTC INTD */	44	/* INTA INTB INTC INTD */
45	{ 0, 0, 0, 0, 0 }, /* EISA bridge */	45	{ 0, 0, 0, 0, 0 }, /* EISA bridge */
46	{ SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */	46	{ SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
@@ -57,7 +57,7 @@ static char irq_tab_rm200[8][5] __initdata = { · 10 unmodified lines
57	*	57	*
58	* The VGA card is optional for RM300 systems.	58	* The VGA card is optional for RM300 systems.
59	*/	59	*/
60	static char irq_tab_rm300d[8][5] __initdata = {	60	static char irq_tab_rm300d[8][5] = {
61	/* INTA INTB INTC INTD */	61	/* INTA INTB INTC INTD */
62	{ 0, 0, 0, 0, 0 }, /* EISA bridge */	62	{ 0, 0, 0, 0, 0 }, /* EISA bridge */
63	{ SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */	63	{ SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
@@ -69,7 +69,7 @@ static char irq_tab_rm300d[8][5] __initdata = { · 5 unmodified lines
69	{ 0, INTD, INTA, INTB, INTC }, /* Slot 4 */	69	{ 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
70	};	70	};
71		71
72	static char irq_tab_rm300e[5][5] __initdata = {	72	static char irq_tab_rm300e[5][5] = {
73	/* INTA INTB INTC INTD */	73	/* INTA INTB INTC INTD */
74	{ 0, 0, 0, 0, 0 }, /* HOST bridge */	74	{ 0, 0, 0, 0, 0 }, /* HOST bridge */
75	{ SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */	75	{ SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
@@ -96,7 +96,7 @@ static char irq_tab_rm300e[5][5] __initdata = { · 20 unmodified lines
96	#define INTC PCIT_IRQ_INTC	96	#define INTC PCIT_IRQ_INTC
97	#define INTD PCIT_IRQ_INTD	97	#define INTD PCIT_IRQ_INTD
98		98
99	static char irq_tab_pcit[13][5] __initdata = {	99	static char irq_tab_pcit[13][5] = {
100	/* INTA INTB INTC INTD */	100	/* INTA INTB INTC INTD */
101	{ 0, 0, 0, 0, 0 }, /* HOST bridge */	101	{ 0, 0, 0, 0, 0 }, /* HOST bridge */
102	{ SCSI0, SCSI0, SCSI0, SCSI0, SCSI0 }, /* SCSI */	102	{ SCSI0, SCSI0, SCSI0, SCSI0, SCSI0 }, /* SCSI */
@@ -113,7 +113,7 @@ static char irq_tab_pcit[13][5] __initdata = { · 10 unmodified lines
113	{ 0, INTA, INTB, INTC, INTD }, /* Slot 5 */	113	{ 0, INTA, INTB, INTC, INTD }, /* Slot 5 */
114	};	114	};
115		115
116	static char irq_tab_pcit_cplus[13][5] __initdata = {	116	static char irq_tab_pcit_cplus[13][5] = {
117	/* INTA INTB INTC INTD */	117	/* INTA INTB INTC INTD */
118	{ 0, 0, 0, 0, 0 }, /* HOST bridge */	118	{ 0, 0, 0, 0, 0 }, /* HOST bridge */
119	{ 0, INTB, INTC, INTD, INTA }, /* PCI Slot 9 */	119	{ 0, INTB, INTC, INTD, INTA }, /* PCI Slot 9 */
@@ -130,7 +130,7 @@ static inline int is_rm300_revd(void) · 10 unmodified lines
130	return (csmsr & 0xa0) == 0x20;	130	return (csmsr & 0xa0) == 0x20;
131	}	131	}
132		132
133	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	133	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
134	{	134	{
135	switch (sni_brd_type) {	135	switch (sni_brd_type) {
136	case SNI_BRD_PCI_TOWER_CPLUS:	136	case SNI_BRD_PCI_TOWER_CPLUS:

arch/mips/pci/fixup-tb0219.c+1−1

@@ -23,7 +23,7 @@ · 22 unmodified lines
23		23
24	#include <asm/vr41xx/tb0219.h>	24	#include <asm/vr41xx/tb0219.h>
25		25
26	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	26	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
27	{	27	{
28	int irq = -1;	28	int irq = -1;
29		29

arch/mips/pci/fixup-tb0226.c+1−1

@@ -23,7 +23,7 @@ · 22 unmodified lines
23	#include <asm/vr41xx/giu.h>	23	#include <asm/vr41xx/giu.h>
24	#include <asm/vr41xx/tb0226.h>	24	#include <asm/vr41xx/tb0226.h>
25		25
26	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	26	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
27	{	27	{
28	int irq = -1;	28	int irq = -1;
29		29

arch/mips/pci/fixup-tb0287.c+1−1

@@ -22,7 +22,7 @@ · 21 unmodified lines
22		22
23	#include <asm/vr41xx/tb0287.h>	23	#include <asm/vr41xx/tb0287.h>
24		24
25	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	25	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
26	{	26	{
27	unsigned char bus;	27	unsigned char bus;
28	int irq = -1;	28	int irq = -1;

arch/mips/pci/pci-alchemy.c+1−1

@@ -522,7 +522,7 @@ static int __init alchemy_pci_init(void) · 521 unmodified lines
522	arch_initcall(alchemy_pci_init);	522	arch_initcall(alchemy_pci_init);
523		523
524		524
525	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	525	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
526	{	526	{
527	struct alchemy_pci_context *ctx = dev->sysdata;	527	struct alchemy_pci_context *ctx = dev->sysdata;
528	if (ctx && ctx->board_map_irq)	528	if (ctx && ctx->board_map_irq)

arch/mips/pci/pci-bcm47xx.c+1−1

@@ -28,7 +28,7 @@ · 27 unmodified lines
28	#include <linux/bcma/bcma.h>	28	#include <linux/bcma/bcma.h>
29	#include <bcm47xx.h>	29	#include <bcm47xx.h>
30		30
31	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	31	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
32	{	32	{
33	return 0;	33	return 0;
34	}	34	}

arch/mips/pci/pci-lasat.c+1−1

@@ -61,7 +61,7 @@ arch_initcall(lasat_pci_setup); · 60 unmodified lines
61	#define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7)	61	#define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7)
62	#define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8)	62	#define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8)
63		63
64	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	64	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
65	{	65	{
66	switch (slot) {	66	switch (slot) {
67	case 1:	67	case 1:

arch/mips/pci/pci-mt7620.c+1−1

@@ -361,7 +361,7 @@ static int mt7620_pci_probe(struct platform_device *pdev) · 360 unmodified lines
361	return 0;	361	return 0;
362	}	362	}
363		363
364	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	364	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
365	{	365	{
366	u16 cmd;	366	u16 cmd;
367	u32 val;	367	u32 val;

arch/mips/pci/pci-octeon.c+2−3

 	} s;
 };
-int __initconst (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
+int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
-					 u8 slot, u8 pin);
 enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
 /**
  *		 as it goes through each bridge.
  * Returns Interrupt number for the device
  */
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
 	if (octeon_pcibios_map_irq)
 		return octeon_pcibios_map_irq(dev, slot, pin);

arch/mips/pci/pci-rt2880.c+1−1

@@ -181,7 +181,7 @@ static inline void rt2880_pci_write_u32(unsigned long reg, u32 val) · 180 unmodified lines
181	spin_unlock_irqrestore(&rt2880_pci_lock, flags);	181	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
182	}	182	}
183		183
184	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	184	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
185	{	185	{
186	u16 cmd;	186	u16 cmd;
187	int irq = -1;	187	int irq = -1;

arch/mips/pci/pci-rt3883.c+1−1

@@ -564,7 +564,7 @@ err_put_intc_node: · 563 unmodified lines
564	return err;	564	return err;
565	}	565	}
566		566
567	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	567	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
568	{	568	{
569	return of_irq_parse_and_map_pci(dev, slot, pin);	569	return of_irq_parse_and_map_pci(dev, slot, pin);
570	}	570	}

arch/mips/pci/pci-tx4938.c+1−1

@@ -112,7 +112,7 @@ int __init tx4938_pciclk66_setup(void) · 111 unmodified lines
112	return pciclk;	112	return pciclk;
113	}	113	}
114		114
115	int __init tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)	115	int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
116	{	116	{
117	if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) {	117	if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) {
118	switch (slot) {	118	switch (slot) {

arch/mips/pci/pci-tx4939.c+2−2

@@ -48,7 +48,7 @@ void __init tx4939_report_pci1clk(void) · 47 unmodified lines
48	((pciclk + 50000) / 100000) % 10);	48	((pciclk + 50000) / 100000) % 10);
49	}	49	}
50		50
51	int __init tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot)	51	int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
52	{	52	{
53	if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) {	53	if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) {
54	switch (slot) {	54	switch (slot) {
@@ -68,7 +68,7 @@ int __init tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot) · 13 unmodified lines
68	return -1;	68	return -1;
69	}	69	}
70		70
71	int __init tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	71	int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
72	{	72	{
73	int irq = tx4939_pcic1_map_irq(dev, slot);	73	int irq = tx4939_pcic1_map_irq(dev, slot);
74		74

arch/mips/pci/pci-xlp.c+1−1

@@ -205,7 +205,7 @@ int xlp_socdev_to_node(const struct pci_dev *lnkdev) · 204 unmodified lines
205	return PCI_SLOT(lnkdev->devfn) / 8;	205	return PCI_SLOT(lnkdev->devfn) / 8;
206	}	206	}
207		207
208	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	208	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
209	{	209	{
210	struct pci_dev *lnkdev;	210	struct pci_dev *lnkdev;
211	int lnkfunc, node;	211	int lnkfunc, node;

arch/mips/pci/pci-xlr.c+1−1

@@ -315,7 +315,7 @@ static void xls_pcie_ack_b(struct irq_data *d) · 314 unmodified lines
315	}	315	}
316	}	316	}
317		317
318	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	318	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
319	{	319	{
320	return get_irq_vector(dev);	320	return get_irq_vector(dev);
321	}	321	}

arch/mips/pci/pcie-octeon.c+1−2

  *		 as it goes through each bridge.
  * Returns Interrupt number for the device
  */
-int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
+int octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-				       u8 slot, u8 pin)
 {
 	/*
 	 * The EBH5600 board with the PCI to PCIe bridge mistakenly

arch/mips/pmcs-msp71xx/msp_smp.c+2−0

@@ -22,6 +22,8 @@ · 21 unmodified lines
22	#include <linux/smp.h>	22	#include <linux/smp.h>
23	#include <linux/interrupt.h>	23	#include <linux/interrupt.h>
24		24
		25	#include <asm/setup.h>
		26
25	#ifdef CONFIG_MIPS_MT_SMP	27	#ifdef CONFIG_MIPS_MT_SMP
26	#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */	28	#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
27	#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for call */	29	#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for call */

arch/mips/txx9/generic/pci.c+6−2

 	return 0;
 }
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+static int (*txx9_pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
-	return txx9_board_vec->pci_map_irq(dev, slot, pin);
+	return txx9_pci_map_irq(dev, slot, pin);
 }
 char * (*txx9_board_pcibios_setup)(char *str) __initdata;
 			txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
 		return NULL;
 	}
+	txx9_pci_map_irq = txx9_board_vec->pci_map_irq;
 	return str;
 }

arch/mn10300/kernel/process.c+0−12

 }
 #endif
-void release_segments(struct mm_struct *mm)
-{
-}
 void machine_restart(char *cmd)
 {
 #ifdef CONFIG_KERNEL_DEBUGGER
 {
 }
-/*
- * we do not have to muck with descriptors here, that is
- * done in switch_mm() as needed.
- */
-void copy_segments(struct task_struct *p, struct mm_struct *new_mm)
-{
-}
 /*
  * this gets called so that we can store lazy state into memory and copy the
  * current task into the new thread.

arch/parisc/Kconfig+12−0

@@ -257,6 +257,18 @@ config PARISC_PAGE_SIZE_64KB · 256 unmodified lines
257		257
258	endchoice	258	endchoice
259		259
		260	config PARISC_SELF_EXTRACT
		261	bool "Build kernel as self-extracting executable"
		262	default y
		263	help
		264	Say Y if you want to build the parisc kernel as a kind of
		265	self-extracting executable.
		266
		267	If you say N here, the kernel will be compressed with gzip
		268	which can be loaded by the palo bootloader directly too.
		269
		270	If you don't know what to do here, say Y.
		271
260	config SMP	272	config SMP
261	bool "Symmetric multi-processing support"	273	bool "Symmetric multi-processing support"
262	---help---	274	---help---

arch/parisc/Makefile+5−0

 bzImage: vmlinux
 	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
+ifdef CONFIG_PARISC_SELF_EXTRACT
 vmlinuz: bzImage
 	$(OBJCOPY) $(boot)/bzImage $@
+else
+vmlinuz: vmlinux
+	@gzip -cf -9 $< > $@
+endif
 install:
 	$(CONFIG_SHELL) $(src)/arch/parisc/install.sh \

arch/parisc/boot/compressed/Makefile+1−1

@@ -15,7 +15,7 @@ targets += misc.o piggy.o sizes.h head.o real2.o firmware.o · 14 unmodified lines
15	KBUILD_CFLAGS := -D__KERNEL__ -O2 -DBOOTLOADER	15	KBUILD_CFLAGS := -D__KERNEL__ -O2 -DBOOTLOADER
16	KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING	16	KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING
17	KBUILD_CFLAGS += $(cflags-y) -fno-delete-null-pointer-checks	17	KBUILD_CFLAGS += $(cflags-y) -fno-delete-null-pointer-checks
18	KBUILD_CFLAGS += -fno-PIE -mno-space-regs -mdisable-fpregs	18	KBUILD_CFLAGS += -fno-PIE -mno-space-regs -mdisable-fpregs -Os
19	ifndef CONFIG_64BIT	19	ifndef CONFIG_64BIT
20	KBUILD_CFLAGS += -mfast-indirect-calls	20	KBUILD_CFLAGS += -mfast-indirect-calls
21	endif	21	endif

arch/parisc/boot/compressed/misc.c+2−1

 /* Symbols defined by linker scripts */
 extern char input_data[];
 extern int input_len;
-extern __le32 output_len;	/* at unaligned address, little-endian */
+/* output_len is inserted by the linker possibly at an unaligned address */
+extern __le32 output_len __aligned(1);
 extern char _text, _end;
 extern char _bss, _ebss;
 extern char _startcode_end;

arch/parisc/include/asm/pdc.h+1−0

@@ -280,6 +280,7 @@ void setup_pdc(void); /* in inventory.c */ · 279 unmodified lines
280	/* wrapper-functions from pdc.c */	280	/* wrapper-functions from pdc.c */
281		281
282	int pdc_add_valid(unsigned long address);	282	int pdc_add_valid(unsigned long address);
		283	int pdc_instr(unsigned int *instr);
283	int pdc_chassis_info(struct pdc_chassis_info chassis_info, void led_info, unsigned long len);	284	int pdc_chassis_info(struct pdc_chassis_info chassis_info, void led_info, unsigned long len);
284	int pdc_chassis_disp(unsigned long disp);	285	int pdc_chassis_disp(unsigned long disp);
285	int pdc_chassis_warn(unsigned long *warn);	286	int pdc_chassis_warn(unsigned long *warn);

arch/parisc/include/asm/smp.h+1−0

@@ -1,6 +1,7 @@
1	#ifndef __ASM_SMP_H	1	#ifndef __ASM_SMP_H
2	#define __ASM_SMP_H	2	#define __ASM_SMP_H
3		3
		4	extern int init_per_cpu(int cpuid);
4		5
5	#if defined(CONFIG_SMP)	6	#if defined(CONFIG_SMP)
6		7

arch/parisc/kernel/firmware.c+20−0

@@ -232,6 +232,26 @@ int pdc_add_valid(unsigned long address) · 231 unmodified lines
232	}	232	}
233	EXPORT_SYMBOL(pdc_add_valid);	233	EXPORT_SYMBOL(pdc_add_valid);
234		234
		235	/**
		236	* pdc_instr - Get instruction that invokes PDCE_CHECK in HPMC handler.
		237	* @instr: Pointer to variable which will get instruction opcode.
		238	*
		239	* The return value is PDC_OK (0) in case call succeeded.
		240	*/
		241	int __init pdc_instr(unsigned int *instr)
		242	{
		243	int retval;
		244	unsigned long flags;
		245
		246	spin_lock_irqsave(&pdc_lock, flags);
		247	retval = mem_pdc_call(PDC_INSTR, 0UL, __pa(pdc_result));
		248	convert_to_wide(pdc_result);
		249	*instr = pdc_result[0];
		250	spin_unlock_irqrestore(&pdc_lock, flags);
		251
		252	return retval;
		253	}
		254
235	/**	255	/**
236	* pdc_chassis_info - Return chassis information.	256	* pdc_chassis_info - Return chassis information.
237	* @result: The return buffer.	257	* @result: The return buffer.

arch/parisc/kernel/pdt.c+9−0

 #include <linux/memblock.h>
 #include <linux/seq_file.h>
 #include <linux/kthread.h>
+#include <linux/initrd.h>
 #include <asm/pdc.h>
 #include <asm/pdcpat.h>
 	}
 	for (i = 0; i < pdt_status.pdt_entries; i++) {
+		unsigned long addr;
 		report_mem_err(pdt_entry[i]);
+		addr = pdt_entry[i] & PDT_ADDR_PHYS_MASK;
+		if (IS_ENABLED(CONFIG_BLK_DEV_INITRD) &&
+			addr >= initrd_start && addr < initrd_end)
+			pr_crit("CRITICAL: initrd possibly broken "
+				"due to bad memory!\n");
 		/* mark memory page bad */
 		memblock_reserve(pdt_entry[i] & PAGE_MASK, PAGE_SIZE);
 	}

arch/parisc/kernel/process.c+1−1

@@ -146,7 +146,7 @@ void machine_power_off(void) · 145 unmodified lines
146		146
147	/* prevent soft lockup/stalled CPU messages for endless loop. */	147	/* prevent soft lockup/stalled CPU messages for endless loop. */
148	rcu_sysrq_start();	148	rcu_sysrq_start();
149	lockup_detector_suspend();	149	lockup_detector_soft_poweroff();
150	for (;;);	150	for (;;);
151	}	151	}
152		152

arch/parisc/kernel/processor.c+1−1

@@ -317,7 +317,7 @@ void __init collect_boot_cpu_data(void) · 316 unmodified lines
317	*	317	*
318	* o Enable CPU profiling hooks.	318	* o Enable CPU profiling hooks.
319	*/	319	*/
320	int init_per_cpu(int cpunum)	320	int __init init_per_cpu(int cpunum)
321	{	321	{
322	int ret;	322	int ret;
323	struct pdc_coproc_cfg coproc_cfg;	323	struct pdc_coproc_cfg coproc_cfg;

arch/parisc/kernel/setup.c+3−3

 #include <linux/export.h>
 #include <linux/sched.h>
 #include <linux/sched/clock.h>
+#include <linux/start_kernel.h>
 #include <asm/processor.h>
 #include <asm/sections.h>
 #include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/unwind.h>
+#include <asm/smp.h>
 static char __initdata command_line[COMMAND_LINE_SIZE];
 }
 #endif
-extern int init_per_cpu(int cpuid);
 extern void collect_boot_cpu_data(void);
 void __init setup_arch(char **cmdline_p)
 }
 arch_initcall(parisc_init);
-void start_parisc(void)
+void __init start_parisc(void)
 {
-	extern void start_kernel(void);
 	extern void early_trap_init(void);
 	int ret, cpunum;

arch/parisc/kernel/smp.c+1−2

 static void __init
 smp_cpu_init(int cpunum)
 {
-	extern int init_per_cpu(int);  /* arch/parisc/kernel/processor.c */
 	extern void init_IRQ(void);    /* arch/parisc/kernel/irq.c */
 	extern void start_cpu_itimer(void); /* arch/parisc/kernel/time.c */
 	/* Set modes and Enable floating point coprocessor */
-	(void) init_per_cpu(cpunum);
+	init_per_cpu(cpunum);
 	disable_sr_hashing();

arch/parisc/kernel/traps.c+9−1

 	u32 check = 0;
 	u32 *ivap;
 	u32 *hpmcp;
-	u32 length;
+	u32 length, instr;
 	if (strcmp((const char *)iva, "cows can fly"))
 		panic("IVT invalid");
 	for (i = 0; i < 8; i++)
 	    *ivap++ = 0;
+	/*
+	 * Use PDC_INSTR firmware function to get instruction that invokes
+	 * PDCE_CHECK in HPMC handler.  See programming note at page 1-31 of
+	 * the PA 1.1 Firmware Architecture document.
+	 */
+	if (pdc_instr(&instr) == PDC_OK)
+		ivap[0] = instr;
 	/* Compute Checksum for HPMC handler */
 	length = os_hpmc_size;
 	ivap[7] = length;

arch/parisc/kernel/unwind.c+12−0

 #include <linux/slab.h>
 #include <linux/kallsyms.h>
 #include <linux/sort.h>
+#include <linux/sched.h>
 #include <linux/uaccess.h>
 #include <asm/assembly.h>
 			info->prev_sp = sp - 64;
 			info->prev_ip = 0;
+			/* The stack is at the end inside the thread_union
+			 * struct. If we reach data, we have reached the
+			 * beginning of the stack and should stop unwinding. */
+			if (info->prev_sp >= (unsigned long) task_thread_info(info->t) &&
+			    info->prev_sp < ((unsigned long) task_thread_info(info->t)
+						+ THREAD_SZ_ALGN)) {
+				info->prev_sp = 0;
+				break;
+			}
 			if (get_user(tmp, (unsigned long *)(info->prev_sp - RP_OFFSET)))
 				break;
 			info->prev_ip = tmp;

arch/parisc/mm/fault.c+29−4

@@ -17,6 +17,7 @@ · 16 unmodified lines
17	#include <linux/interrupt.h>	17	#include <linux/interrupt.h>
18	#include <linux/extable.h>	18	#include <linux/extable.h>
19	#include <linux/uaccess.h>	19	#include <linux/uaccess.h>
		20	#include <linux/hugetlb.h>
20		21
21	#include <asm/traps.h>	22	#include <asm/traps.h>
22		23
@@ -261,7 +262,7 @@ void do_page_fault(struct pt_regs *regs, unsigned long code, · 238 unmodified lines
261	struct task_struct *tsk;	262	struct task_struct *tsk;
262	struct mm_struct *mm;	263	struct mm_struct *mm;
263	unsigned long acc_type;	264	unsigned long acc_type;
264	int fault;	265	int fault = 0;
265	unsigned int flags;	266	unsigned int flags;
266		267
267	if (faulthandler_disabled())	268	if (faulthandler_disabled())
@@ -315,7 +316,8 @@ good_area: · 47 unmodified lines
315	goto out_of_memory;	316	goto out_of_memory;
316	else if (fault & VM_FAULT_SIGSEGV)	317	else if (fault & VM_FAULT_SIGSEGV)
317	goto bad_area;	318	goto bad_area;
318	else if (fault & VM_FAULT_SIGBUS)	319	else if (fault & (VM_FAULT_SIGBUS\|VM_FAULT_HWPOISON\|
		320	VM_FAULT_HWPOISON_LARGE))
319	goto bad_area;	321	goto bad_area;
320	BUG();	322	BUG();
321	}	323	}
@@ -352,8 +354,7 @@ bad_area: · 30 unmodified lines
352		354
353	if (user_mode(regs)) {	355	if (user_mode(regs)) {
354	struct siginfo si;	356	struct siginfo si;
355		357	unsigned int lsb = 0;
356	show_signal_msg(regs, code, address, tsk, vma);
357		358
358	switch (code) {	359	switch (code) {
359	case 15: /* Data TLB miss fault/Data page fault */	360	case 15: /* Data TLB miss fault/Data page fault */
@@ -386,6 +387,30 @@ bad_area: · 26 unmodified lines
386	si.si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;	387	si.si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
387	break;	388	break;
388	}	389	}
		390
		391	#ifdef CONFIG_MEMORY_FAILURE
		392	if (fault & (VM_FAULT_HWPOISON\|VM_FAULT_HWPOISON_LARGE)) {
		393	printk(KERN_ERR
		394	"MCE: Killing %s:%d due to hardware memory corruption fault at %08lx\n",
		395	tsk->comm, tsk->pid, address);
		396	si.si_signo = SIGBUS;
		397	si.si_code = BUS_MCEERR_AR;
		398	}
		399	#endif
		400
		401	/*
		402	* Either small page or large page may be poisoned.
		403	* In other words, VM_FAULT_HWPOISON_LARGE and
		404	* VM_FAULT_HWPOISON are mutually exclusive.
		405	*/
		406	if (fault & VM_FAULT_HWPOISON_LARGE)
		407	lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
		408	else if (fault & VM_FAULT_HWPOISON)
		409	lsb = PAGE_SHIFT;
		410	else
		411	show_signal_msg(regs, code, address, tsk, vma);
		412	si.si_addr_lsb = lsb;
		413
389	si.si_errno = 0;	414	si.si_errno = 0;
390	si.si_addr = (void __user *) address;	415	si.si_addr = (void __user *) address;
391	force_sig_info(si.si_signo, &si, current);	416	force_sig_info(si.si_signo, &si, current);

arch/powerpc/configs/g5_defconfig+3−2

 CONFIG_LOGO=y
 CONFIG_SOUND=m
 CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
+CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=m
 CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=m
 CONFIG_SND_POWERMAC=m
 CONFIG_SND_AOA=m
 CONFIG_SND_AOA_FABRIC_LAYOUT=m

arch/powerpc/configs/gamecube_defconfig+3−2

 # CONFIG_LOGO_LINUX_CLUT224 is not set
 CONFIG_SOUND=y
 CONFIG_SND=y
-CONFIG_SND_SEQUENCER=y
+CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SEQUENCER_OSS=y
 # CONFIG_SND_VERBOSE_PROCFS is not set
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQUENCER_OSS=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_GENERIC=y

arch/powerpc/configs/pasemi_defconfig+2−1

 CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
-CONFIG_SND_SEQUENCER=y
+CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
+CONFIG_SND_SEQUENCER=y
 CONFIG_SND_SEQUENCER_OSS=y
 CONFIG_SND_USB_AUDIO=y
 CONFIG_SND_USB_USX2Y=y

arch/powerpc/configs/pmac32_defconfig+4−3

 CONFIG_LOGO=y
 CONFIG_SOUND=m
 CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
+CONFIG_SND_OSSEMUL=y
-CONFIG_SND_SEQ_DUMMY=m
 CONFIG_SND_MIXER_OSS=m
 CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQUENCER_OSS=m
 CONFIG_SND_DUMMY=m
 CONFIG_SND_POWERMAC=m
 CONFIG_SND_AOA=m

arch/powerpc/configs/ppc64_defconfig+4−3

 CONFIG_LOGO=y
 CONFIG_SOUND=m
 CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
+CONFIG_SND_OSSEMUL=y
-CONFIG_SND_SEQ_DUMMY=m
 CONFIG_SND_MIXER_OSS=m
 CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQUENCER_OSS=m
 CONFIG_SND_POWERMAC=m
 CONFIG_SND_AOA=m
 CONFIG_SND_AOA_FABRIC_LAYOUT=m

arch/powerpc/configs/ppc64e_defconfig+4−3

 CONFIG_LOGO=y
 CONFIG_SOUND=m
 CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
+CONFIG_SND_OSSEMUL=y
-CONFIG_SND_SEQ_DUMMY=m
 CONFIG_SND_MIXER_OSS=m
 CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQUENCER_OSS=m
 CONFIG_HID_DRAGONRISE=y
 CONFIG_HID_GYRATION=y
 CONFIG_HID_TWINHAN=y

arch/powerpc/configs/ppc6xx_defconfig+4−3

 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_SOUND=m
 CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
+CONFIG_SND_OSSEMUL=y
-CONFIG_SND_SEQ_DUMMY=m
 CONFIG_SND_MIXER_OSS=m
 CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
 CONFIG_SND_DYNAMIC_MINORS=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
 CONFIG_SND_VERBOSE_PRINTK=y
 CONFIG_SND_DEBUG=y
 CONFIG_SND_DEBUG_VERBOSE=y
 CONFIG_SND_PCM_XRUN_DEBUG=y
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQUENCER_OSS=m
 CONFIG_SND_DUMMY=m
 CONFIG_SND_VIRMIDI=m
 CONFIG_SND_MTPAV=m

arch/powerpc/configs/wii_defconfig+3−2

 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_SOUND=y
 CONFIG_SND=y
-CONFIG_SND_SEQUENCER=y
+CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SEQUENCER_OSS=y
 # CONFIG_SND_VERBOSE_PROCFS is not set
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQUENCER_OSS=y
 CONFIG_HID_APPLE=m
 CONFIG_HID_WACOM=m
 CONFIG_MMC=y

arch/powerpc/kernel/dt_cpu_ftrs.c+2−2

@@ -102,10 +102,10 @@ static void cpufeatures_flush_tlb(void) · 101 unmodified lines
102	case PVR_POWER8:	102	case PVR_POWER8:
103	case PVR_POWER8E:	103	case PVR_POWER8E:
104	case PVR_POWER8NVL:	104	case PVR_POWER8NVL:
105	__flush_tlb_power8(POWER8_TLB_SETS);	105	__flush_tlb_power8(TLB_INVAL_SCOPE_GLOBAL);
106	break;	106	break;
107	case PVR_POWER9:	107	case PVR_POWER9:
108	__flush_tlb_power9(POWER9_TLB_SETS_HASH);	108	__flush_tlb_power9(TLB_INVAL_SCOPE_GLOBAL);
109	break;	109	break;
110	default:	110	default:
111	pr_err("unknown CPU version for boot TLB flush\n");	111	pr_err("unknown CPU version for boot TLB flush\n");

arch/powerpc/kernel/eeh.c+4−0

 	} else if ((ret = eeh_ops->init()))
 		return ret;
+	/* Initialize PHB PEs */
+	list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
+		eeh_dev_phb_init_dynamic(hose);
 	/* Initialize EEH event */
 	ret = eeh_event_init();
 	if (ret)

arch/powerpc/kernel/eeh_dev.c+0−18

@@ -78,21 +78,3 @@ void eeh_dev_phb_init_dynamic(struct pci_controller *phb) · 77 unmodified lines
78	/* EEH PE for PHB */	78	/* EEH PE for PHB */
79	eeh_phb_pe_create(phb);	79	eeh_phb_pe_create(phb);
80	}	80	}
81
82	/**
83	* eeh_dev_phb_init - Create EEH devices for devices included in existing PHBs
84	*
85	* Scan all the existing PHBs and create EEH devices for their OF
86	* nodes and their children OF nodes
87	*/
88	static int __init eeh_dev_phb_init(void)
89	{
90	struct pci_controller phb, tmp;
91
92	list_for_each_entry_safe(phb, tmp, &hose_list, list_node)
93	eeh_dev_phb_init_dynamic(phb);
94
95	return 0;
96	}
97
98	core_initcall(eeh_dev_phb_init);

arch/powerpc/kernel/mce_power.c+13−0

@@ -624,5 +624,18 @@ long __machine_check_early_realmode_p8(struct pt_regs *regs) · 623 unmodified lines
624		624
625	long __machine_check_early_realmode_p9(struct pt_regs *regs)	625	long __machine_check_early_realmode_p9(struct pt_regs *regs)
626	{	626	{
		627	/*
		628	* On POWER9 DD2.1 and below, it's possible to get a machine check
		629	* caused by a paste instruction where only DSISR bit 25 is set. This
		630	* will result in the MCE handler seeing an unknown event and the kernel
		631	* crashing. An MCE that occurs like this is spurious, so we don't need
		632	* to do anything in terms of servicing it. If there is something that
		633	* needs to be serviced, the CPU will raise the MCE again with the
		634	* correct DSISR so that it can be serviced properly. So detect this
		635	* case and mark it as handled.
		636	*/
		637	if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000)
		638	return 1;
		639
627	return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table);	640	return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table);
628	}	641	}

arch/powerpc/kernel/optprobes.c+3−1

 	 * and that can be emulated.
 	 */
 	if (!is_conditional_branch(*p->ainsn.insn) &&
-			analyse_instr(&op, &regs, *p->ainsn.insn))
+			analyse_instr(&op, &regs, *p->ainsn.insn) == 1) {
+		emulate_update_regs(&regs, &op);
 		nip = regs.nip;
+	}
 	return nip;
 }

arch/powerpc/kernel/ptrace.c+1−1

@@ -131,7 +131,7 @@ static void flush_tmregs_to_thread(struct task_struct *tsk) · 130 unmodified lines
131	* in the appropriate thread structures from live.	131	* in the appropriate thread structures from live.
132	*/	132	*/
133		133
134	if (tsk != current)	134	if ((!cpu_has_feature(CPU_FTR_TM)) \|\| (tsk != current))
135	return;	135	return;
136		136
137	if (MSR_TM_SUSPENDED(mfmsr())) {	137	if (MSR_TM_SUSPENDED(mfmsr())) {

arch/powerpc/kernel/setup-common.c+0−3

 #endif
 #endif
-#ifdef CONFIG_PPC_64K_PAGES
-	init_mm.context.pte_frag = NULL;
-#endif
 #ifdef CONFIG_SPAPR_TCE_IOMMU
 	mm_iommu_init(&init_mm);
 #endif

arch/powerpc/kernel/traps.c+10−2

 int machine_check_e500mc(struct pt_regs *regs)
 {
 	unsigned long mcsr = mfspr(SPRN_MCSR);
+	unsigned long pvr = mfspr(SPRN_PVR);
 	unsigned long reason = mcsr;
 	int recoverable = 1;
 		 * may still get logged and cause a machine check.  We should
 		 * only treat the non-write shadow case as non-recoverable.
 		 */
-		if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
+		/* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
-			recoverable = 0;
+		 * is not implemented but L1 data cache always runs in write
+		 * shadow mode. Hence on data cache parity errors HW will
+		 * automatically invalidate the L1 Data Cache.
+		 */
+		if (PVR_VER(pvr) != PVR_VER_E6500) {
+			if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
+				recoverable = 0;
+		}
 	}
 	if (reason & MCSR_L2MMU_MHIT) {

arch/powerpc/kernel/watchdog.c+15−15

@@ -310,9 +310,6 @@ static int start_wd_on_cpu(unsigned int cpu) · 309 unmodified lines
310	if (!(watchdog_enabled & NMI_WATCHDOG_ENABLED))	310	if (!(watchdog_enabled & NMI_WATCHDOG_ENABLED))
311	return 0;	311	return 0;
312		312
313	if (watchdog_suspended)
314	return 0;
315
316	if (!cpumask_test_cpu(cpu, &watchdog_cpumask))	313	if (!cpumask_test_cpu(cpu, &watchdog_cpumask))
317	return 0;	314	return 0;
318		315
@@ -358,36 +355,39 @@ static void watchdog_calc_timeouts(void) · 39 unmodified lines
358	wd_timer_period_ms = watchdog_thresh * 1000 * 2 / 5;	355	wd_timer_period_ms = watchdog_thresh * 1000 * 2 / 5;
359	}	356	}
360		357
361	void watchdog_nmi_reconfigure(void)	358	void watchdog_nmi_stop(void)
362	{	359	{
363	int cpu;	360	int cpu;
364		361
365	watchdog_calc_timeouts();
366
367	for_each_cpu(cpu, &wd_cpus_enabled)	362	for_each_cpu(cpu, &wd_cpus_enabled)
368	stop_wd_on_cpu(cpu);	363	stop_wd_on_cpu(cpu);
		364	}
369		365
		366	void watchdog_nmi_start(void)
		367	{
		368	int cpu;
		369
		370	watchdog_calc_timeouts();
370	for_each_cpu_and(cpu, cpu_online_mask, &watchdog_cpumask)	371	for_each_cpu_and(cpu, cpu_online_mask, &watchdog_cpumask)
371	start_wd_on_cpu(cpu);	372	start_wd_on_cpu(cpu);
372	}	373	}
373		374
374	/*	375	/*
375	* This runs after lockup_detector_init() which sets up watchdog_cpumask.	376	* Invoked from core watchdog init.
376	*/	377	*/
377	static int __init powerpc_watchdog_init(void)	378	int __init watchdog_nmi_probe(void)
378	{	379	{
379	int err;	380	int err;
380		381
381	watchdog_calc_timeouts();	382	err = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
382		383	"powerpc/watchdog:online",
383	err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/watchdog:online",	384	start_wd_on_cpu, stop_wd_on_cpu);
384	start_wd_on_cpu, stop_wd_on_cpu);	385	if (err < 0) {
385	if (err < 0)
386	pr_warn("Watchdog could not be initialized");	386	pr_warn("Watchdog could not be initialized");
387		387	return err;
		388	}
388	return 0;	389	return 0;
389	}	390	}
390	arch_initcall(powerpc_watchdog_init);
391		391
392	static void handle_backtrace_ipi(struct pt_regs *regs)	392	static void handle_backtrace_ipi(struct pt_regs *regs)
393	{	393	{

arch/powerpc/kvm/book3s_hv_rmhandlers.S+13−1

 BEGIN_FTR_SECTION
 	mtspr	SPRN_PPR, r0
 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
+/* Move canary into DSISR to check for later */
+BEGIN_FTR_SECTION
+	li	r0, 0x7fff
+	mtspr	SPRN_HDSISR, r0
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
 	ld	r0, VCPU_GPR(R0)(r4)
 	ld	r4, VCPU_GPR(R4)(r4)
 kvmppc_hdsi:
 	ld	r3, VCPU_KVM(r9)
 	lbz	r0, KVM_RADIX(r3)
-	cmpwi	r0, 0
 	mfspr	r4, SPRN_HDAR
 	mfspr	r6, SPRN_HDSISR
+BEGIN_FTR_SECTION
+	/* Look for DSISR canary. If we find it, retry instruction */
+	cmpdi	r6, 0x7fff
+	beq	6f
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
+	cmpwi	r0, 0
 	bne	.Lradix_hdsi		/* on radix, just save DAR/DSISR/ASDR */
 	/* HPTE not found fault or protection fault? */
 	andis.	r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h

arch/powerpc/kvm/book3s_xive.c+2−3

 		return -EINVAL;
 	state = &sb->irq_state[idx];
 	arch_spin_lock(&sb->lock);
-	*server = state->guest_server;
+	*server = state->act_server;
 	*priority = state->guest_priority;
 	arch_spin_unlock(&sb->lock);
 	xive->saved_src_count++;
 	/* Convert saved state into something compatible with xics */
-	val = state->guest_server;
+	val = state->act_server;
 	prio = state->saved_scan_prio;
 	if (prio == MASKED) {
 	/* First convert prio and mark interrupt as untargetted */
 	act_prio = xive_prio_from_guest(guest_prio);
 	state->act_priority = MASKED;
-	state->guest_server = server;
 	/*
 	 * We need to drop the lock due to the mutex below. Hopefully

arch/powerpc/kvm/book3s_xive.h+0−1

@@ -35,7 +35,6 @@ struct kvmppc_xive_irq_state { · 34 unmodified lines
35	struct xive_irq_data pt_data; / XIVE Pass-through associated data */	35	struct xive_irq_data pt_data; / XIVE Pass-through associated data */
36		36
37	/* Targetting as set by guest */	37	/* Targetting as set by guest */
38	u32 guest_server; /* Current guest selected target */
39	u8 guest_priority; /* Guest set priority */	38	u8 guest_priority; /* Guest set priority */
40	u8 saved_priority; /* Saved priority when masking */	39	u8 saved_priority; /* Saved priority when masking */
41		40

arch/powerpc/lib/sstep.c+12−11

@@ -944,9 +944,9 @@ NOKPROBE_SYMBOL(emulate_dcbz); · 943 unmodified lines
944	: "r" (addr), "i" (-EFAULT), "0" (err))	944	: "r" (addr), "i" (-EFAULT), "0" (err))
945		945
946	static nokprobe_inline void set_cr0(const struct pt_regs *regs,	946	static nokprobe_inline void set_cr0(const struct pt_regs *regs,
947	struct instruction_op *op, int rd)	947	struct instruction_op *op)
948	{	948	{
949	long val = regs->gpr[rd];	949	long val = op->val;
950		950
951	op->type \|= SETCC;	951	op->type \|= SETCC;
952	op->ccval = (regs->ccr & 0x0fffffff) \| ((regs->xer >> 3) & 0x10000000);	952	op->ccval = (regs->ccr & 0x0fffffff) \| ((regs->xer >> 3) & 0x10000000);
@@ -1326,7 +1326,7 @@ int analyse_instr(struct instruction_op op, const struct pt_regs regs, · 373 unmodified lines
1326	case 13: /* addic. */	1326	case 13: /* addic. */
1327	imm = (short) instr;	1327	imm = (short) instr;
1328	add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);	1328	add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1329	set_cr0(regs, op, rd);	1329	set_cr0(regs, op);
1330	return 1;	1330	return 1;
1331		1331
1332	case 14: /* addi */	1332	case 14: /* addi */
@@ -1397,13 +1397,13 @@ int analyse_instr(struct instruction_op op, const struct pt_regs regs, · 64 unmodified lines
1397		1397
1398	case 28: /* andi. */	1398	case 28: /* andi. */
1399	op->val = regs->gpr[rd] & (unsigned short) instr;	1399	op->val = regs->gpr[rd] & (unsigned short) instr;
1400	set_cr0(regs, op, ra);	1400	set_cr0(regs, op);
1401	goto logical_done_nocc;	1401	goto logical_done_nocc;
1402		1402
1403	case 29: /* andis. */	1403	case 29: /* andis. */
1404	imm = (unsigned short) instr;	1404	imm = (unsigned short) instr;
1405	op->val = regs->gpr[rd] & (imm << 16);	1405	op->val = regs->gpr[rd] & (imm << 16);
1406	set_cr0(regs, op, ra);	1406	set_cr0(regs, op);
1407	goto logical_done_nocc;	1407	goto logical_done_nocc;
1408		1408
1409	#ifdef __powerpc64__	1409	#ifdef __powerpc64__
@@ -1513,10 +1513,10 @@ int analyse_instr(struct instruction_op op, const struct pt_regs regs, · 103 unmodified lines
1513	op->type = COMPUTE + SETCC;	1513	op->type = COMPUTE + SETCC;
1514	imm = 0xf0000000UL;	1514	imm = 0xf0000000UL;
1515	val = regs->gpr[rd];	1515	val = regs->gpr[rd];
1516	op->val = regs->ccr;	1516	op->ccval = regs->ccr;
1517	for (sh = 0; sh < 8; ++sh) {	1517	for (sh = 0; sh < 8; ++sh) {
1518	if (instr & (0x80000 >> sh))	1518	if (instr & (0x80000 >> sh))
1519	op->val = (op->val & ~imm) \|	1519	op->ccval = (op->ccval & ~imm) \|
1520	(val & imm);	1520	(val & imm);
1521	imm >>= 4;	1521	imm >>= 4;
1522	}	1522	}
@@ -1651,8 +1651,9 @@ int analyse_instr(struct instruction_op op, const struct pt_regs regs, · 128 unmodified lines
1651	goto arith_done;	1651	goto arith_done;
1652		1652
1653	case 235: /* mullw */	1653	case 235: /* mullw */
1654	op->val = (unsigned int) regs->gpr[ra] *	1654	op->val = (long)(int) regs->gpr[ra] *
1655	(unsigned int) regs->gpr[rb];	1655	(int) regs->gpr[rb];
		1656
1656	goto arith_done;	1657	goto arith_done;
1657		1658
1658	case 266: /* add */	1659	case 266: /* add */
@@ -2526,7 +2527,7 @@ int analyse_instr(struct instruction_op op, const struct pt_regs regs, · 867 unmodified lines
2526		2527
2527	logical_done:	2528	logical_done:
2528	if (instr & 1)	2529	if (instr & 1)
2529	set_cr0(regs, op, ra);	2530	set_cr0(regs, op);
2530	logical_done_nocc:	2531	logical_done_nocc:
2531	op->reg = ra;	2532	op->reg = ra;
2532	op->type \|= SETREG;	2533	op->type \|= SETREG;
@@ -2534,7 +2535,7 @@ int analyse_instr(struct instruction_op op, const struct pt_regs regs, · 1 unmodified line
2534		2535
2535	arith_done:	2536	arith_done:
2536	if (instr & 1)	2537	if (instr & 1)
2537	set_cr0(regs, op, rd);	2538	set_cr0(regs, op);
2538	compute_done:	2539	compute_done:
2539	op->reg = rd;	2540	op->reg = rd;
2540	op->type \|= SETREG;	2541	op->type \|= SETREG;

arch/powerpc/mm/pgtable_32.c+1−1

 			break;
 	}
 	wmb();
+	local_irq_restore(flags);
 	flush_tlb_kernel_range((unsigned long)page_address(start),
 			       (unsigned long)page_address(page));
-	local_irq_restore(flags);
 	return err;
 }

arch/powerpc/perf/core-book3s.c+5−0

 	u32 pmcs[MAX_HWEVENTS];
 	int i;
+	if (!ppmu) {
+		pr_info("Performance monitor hardware not registered.\n");
+		return;
+	}
 	if (!ppmu->n_counter)
 		return;

arch/powerpc/platforms/powernv/idle.c+7−1

@@ -393,7 +393,13 @@ static void pnv_program_cpu_hotplug_lpcr(unsigned int cpu, u64 lpcr_val) · 392 unmodified lines
393	u64 pir = get_hard_smp_processor_id(cpu);	393	u64 pir = get_hard_smp_processor_id(cpu);
394		394
395	mtspr(SPRN_LPCR, lpcr_val);	395	mtspr(SPRN_LPCR, lpcr_val);
396	opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val);	396
		397	/*
		398	* Program the LPCR via stop-api only if the deepest stop state
		399	* can lose hypervisor context.
		400	*/
		401	if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT)
		402	opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val);
397	}	403	}
398		404
399	/*	405	/*

arch/powerpc/platforms/powernv/setup.c+9−1

@@ -272,7 +272,15 @@ static void pnv_kexec_cpu_down(int crash_shutdown, int secondary) · 271 unmodified lines
272	#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE	272	#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
273	static unsigned long pnv_memory_block_size(void)	273	static unsigned long pnv_memory_block_size(void)
274	{	274	{
275	return 256UL * 1024 * 1024;	275	/*
		276	* We map the kernel linear region with 1GB large pages on radix. For
		277	* memory hot unplug to work our memory block size must be at least
		278	* this size.
		279	*/
		280	if (radix_enabled())
		281	return 1UL * 1024 * 1024 * 1024;
		282	else
		283	return 256UL * 1024 * 1024;
276	}	284	}
277	#endif	285	#endif
278		286

arch/powerpc/platforms/pseries/dlpar.c+0−1

@@ -266,7 +266,6 @@ int dlpar_attach_node(struct device_node dn, struct device_node parent) · 265 unmodified lines
266	return rc;	266	return rc;
267	}	267	}
268		268
269	of_node_put(dn->parent);
270	return 0;	269	return 0;
271	}	270	}
272		271

arch/powerpc/platforms/pseries/hotplug-cpu.c+5−1

 	}
 	dn = dlpar_configure_connector(cpu_to_be32(drc_index), parent);
-	of_node_put(parent);
 	if (!dn) {
 		pr_warn("Failed call to configure-connector, drc index: %x\n",
 			drc_index);
 		dlpar_release_drc(drc_index);
+		of_node_put(parent);
 		return -EINVAL;
 	}
 	rc = dlpar_attach_node(dn, parent);
+	/* Regardless we are done with parent now */
+	of_node_put(parent);
 	if (rc) {
 		saved_rc = rc;
 		pr_warn("Failed to attach node %s, rc: %d, drc index: %x\n",

arch/powerpc/platforms/pseries/mobility.c+3−1

 		return -ENOENT;
 	dn = dlpar_configure_connector(drc_index, parent_dn);
-	if (!dn)
+	if (!dn) {
+		of_node_put(parent_dn);
 		return -ENOENT;
+	}
 	rc = dlpar_attach_node(dn, parent_dn);
 	if (rc)

arch/powerpc/sysdev/fsl_rio.c+15−2

 #define RIWAR_WRTYP_ALLOC	0x00006000
 #define RIWAR_SIZE_MASK		0x0000003F
+static DEFINE_SPINLOCK(fsl_rio_config_lock);
 #define __fsl_read_rio_config(x, addr, err, op)		\
 	__asm__ __volatile__(				\
 		"1:	"op" %1,0(%2)\n"		\
 			u8 hopcount, u32 offset, int len, u32 *val)
 {
 	struct rio_priv *priv = mport->priv;
+	unsigned long flags;
 	u8 *data;
 	u32 rval, err = 0;
 	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
 		return -EINVAL;
+	spin_lock_irqsave(&fsl_rio_config_lock, flags);
 	out_be32(&priv->maint_atmu_regs->rowtar,
 		 (destid << 22) | (hopcount << 12) | (offset >> 12));
 	out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
 		__fsl_read_rio_config(rval, data, err, "lwz");
 		break;
 	default:
+		spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
 		return -EINVAL;
 	}
 			 err, destid, hopcount, offset);
 	}
+	spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
 	*val = rval;
 	return err;
 			u8 hopcount, u32 offset, int len, u32 val)
 {
 	struct rio_priv *priv = mport->priv;
+	unsigned long flags;
 	u8 *data;
+	int ret = 0;
 	pr_debug
 		("fsl_rio_config_write:"
 		" index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
 	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
 		return -EINVAL;
+	spin_lock_irqsave(&fsl_rio_config_lock, flags);
 	out_be32(&priv->maint_atmu_regs->rowtar,
 		 (destid << 22) | (hopcount << 12) | (offset >> 12));
 	out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
 		out_be32((u32 *) data, val);
 		break;
 	default:
-		return -EINVAL;
+		ret = -EINVAL;
 	}
+	spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
-	return 0;
+	return ret;
 }
 static void fsl_rio_inbound_mem_init(struct rio_priv *priv)

arch/powerpc/sysdev/fsl_rmu.c+8−0

 #define DOORBELL_MESSAGE_SIZE	0x08
+static DEFINE_SPINLOCK(fsl_rio_doorbell_lock);
 struct rio_msg_regs {
 	u32 omr;
 	u32 osr;
 int fsl_rio_doorbell_send(struct rio_mport *mport,
 				int index, u16 destid, u16 data)
 {
+	unsigned long flags;
 	pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
 		 index, destid, data);
+	spin_lock_irqsave(&fsl_rio_doorbell_lock, flags);
 	/* In the serial version silicons, such as MPC8548, MPC8641,
 	 * below operations is must be.
 	 */
 	out_be32(&dbell->dbell_regs->oddatr, (index << 20) | data);
 	out_be32(&dbell->dbell_regs->odmr, 0x00000001);
+	spin_unlock_irqrestore(&fsl_rio_doorbell_lock, flags);
 	return 0;
 }

arch/powerpc/sysdev/xive/common.c+8−0

@@ -1402,6 +1402,14 @@ void xive_teardown_cpu(void) · 1401 unmodified lines
1402		1402
1403	if (xive_ops->teardown_cpu)	1403	if (xive_ops->teardown_cpu)
1404	xive_ops->teardown_cpu(cpu, xc);	1404	xive_ops->teardown_cpu(cpu, xc);
		1405
		1406	#ifdef CONFIG_SMP
		1407	/* Get rid of IPI */
		1408	xive_cleanup_cpu_ipi(cpu, xc);
		1409	#endif
		1410
		1411	/* Disable and free the queues */
		1412	xive_cleanup_cpu_queues(cpu, xc);
1405	}	1413	}
1406		1414
1407	void xive_kexec_teardown_cpu(int secondary)	1415	void xive_kexec_teardown_cpu(int secondary)

arch/powerpc/sysdev/xive/spapr.c+4−0

 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
 {
+	if (!xc->hw_ipi)
+		return;
 	xive_irq_bitmap_free(xc->hw_ipi);
+	xc->hw_ipi = 0;
 }
 #endif /* CONFIG_SMP */

arch/s390/include/asm/pgtable.h+3−1

@@ -1507,7 +1507,9 @@ static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, · 1506 unmodified lines
1507	static inline void pmdp_invalidate(struct vm_area_struct *vma,	1507	static inline void pmdp_invalidate(struct vm_area_struct *vma,
1508	unsigned long addr, pmd_t *pmdp)	1508	unsigned long addr, pmd_t *pmdp)
1509	{	1509	{
1510	pmdp_xchg_direct(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));	1510	pmd_t pmd = __pmd(pmd_val(*pmdp) \| _SEGMENT_ENTRY_INVALID);
		1511
		1512	pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd);
1511	}	1513	}
1512		1514
1513	#define __HAVE_ARCH_PMDP_SET_WRPROTECT	1515	#define __HAVE_ARCH_PMDP_SET_WRPROTECT

arch/s390/kernel/early.c+0−12

@@ -404,18 +404,6 @@ static inline void save_vector_registers(void) · 403 unmodified lines
404	#endif	404	#endif
405	}	405	}
406		406
407	static int __init topology_setup(char *str)
408	{
409	bool enabled;
410	int rc;
411
412	rc = kstrtobool(str, &enabled);
413	if (!rc && !enabled)
414	S390_lowcore.machine_flags &= ~MACHINE_FLAG_TOPOLOGY;
415	return rc;
416	}
417	early_param("topology", topology_setup);
418
419	static int __init disable_vector_extension(char *str)	407	static int __init disable_vector_extension(char *str)
420	{	408	{
421	S390_lowcore.machine_flags &= ~MACHINE_FLAG_VX;	409	S390_lowcore.machine_flags &= ~MACHINE_FLAG_VX;

arch/s390/kernel/perf_cpum_sf.c+6−3

 	}
 	/* Check online status of the CPU to which the event is pinned */
-	if ((unsigned int)event->cpu >= nr_cpumask_bits ||
+	if (event->cpu >= 0) {
-	    (event->cpu >= 0 && !cpu_online(event->cpu)))
+		if ((unsigned int)event->cpu >= nr_cpumask_bits)
-		return -ENODEV;
+			return -ENODEV;
+		if (!cpu_online(event->cpu))
+			return -ENODEV;
+	}
 	/* Force reset of idle/hv excludes regardless of what the
 	 * user requested.

arch/s390/kernel/topology.c+135−13

@@ -8,6 +8,8 @@ · 7 unmodified lines
8		8
9	#include <linux/workqueue.h>	9	#include <linux/workqueue.h>
10	#include <linux/bootmem.h>	10	#include <linux/bootmem.h>
		11	#include <linux/uaccess.h>
		12	#include <linux/sysctl.h>
11	#include <linux/cpuset.h>	13	#include <linux/cpuset.h>
12	#include <linux/device.h>	14	#include <linux/device.h>
13	#include <linux/export.h>	15	#include <linux/export.h>
@@ -29,12 +31,20 @@ · 15 unmodified lines
29	#define PTF_VERTICAL (1UL)	31	#define PTF_VERTICAL (1UL)
30	#define PTF_CHECK (2UL)	32	#define PTF_CHECK (2UL)
31		33
		34	enum {
		35	TOPOLOGY_MODE_HW,
		36	TOPOLOGY_MODE_SINGLE,
		37	TOPOLOGY_MODE_PACKAGE,
		38	TOPOLOGY_MODE_UNINITIALIZED
		39	};
		40
32	struct mask_info {	41	struct mask_info {
33	struct mask_info *next;	42	struct mask_info *next;
34	unsigned char id;	43	unsigned char id;
35	cpumask_t mask;	44	cpumask_t mask;
36	};	45	};
37		46
		47	static int topology_mode = TOPOLOGY_MODE_UNINITIALIZED;
38	static void set_topology_timer(void);	48	static void set_topology_timer(void);
39	static void topology_work_fn(struct work_struct *work);	49	static void topology_work_fn(struct work_struct *work);
40	static struct sysinfo_15_1_x *tl_info;	50	static struct sysinfo_15_1_x *tl_info;
@@ -59,11 +69,26 @@ static cpumask_t cpu_group_map(struct mask_info *info, unsigned int cpu) · 18 unmodified lines
59	cpumask_t mask;	69	cpumask_t mask;
60		70
61	cpumask_copy(&mask, cpumask_of(cpu));	71	cpumask_copy(&mask, cpumask_of(cpu));
62	if (!MACHINE_HAS_TOPOLOGY)	72	switch (topology_mode) {
63	return mask;	73	case TOPOLOGY_MODE_HW:
64	for (; info; info = info->next) {	74	while (info) {
65	if (cpumask_test_cpu(cpu, &info->mask))	75	if (cpumask_test_cpu(cpu, &info->mask)) {
66	return info->mask;	76	mask = info->mask;
		77	break;
		78	}
		79	info = info->next;
		80	}
		81	if (cpumask_empty(&mask))
		82	cpumask_copy(&mask, cpumask_of(cpu));
		83	break;
		84	case TOPOLOGY_MODE_PACKAGE:
		85	cpumask_copy(&mask, cpu_present_mask);
		86	break;
		87	default:
		88	/* fallthrough */
		89	case TOPOLOGY_MODE_SINGLE:
		90	cpumask_copy(&mask, cpumask_of(cpu));
		91	break;
67	}	92	}
68	return mask;	93	return mask;
69	}	94	}
@@ -74,7 +99,7 @@ static cpumask_t cpu_thread_map(unsigned int cpu) · 4 unmodified lines
74	int i;	99	int i;
75		100
76	cpumask_copy(&mask, cpumask_of(cpu));	101	cpumask_copy(&mask, cpumask_of(cpu));
77	if (!MACHINE_HAS_TOPOLOGY)	102	if (topology_mode != TOPOLOGY_MODE_HW)
78	return mask;	103	return mask;
79	cpu -= cpu % (smp_cpu_mtid + 1);	104	cpu -= cpu % (smp_cpu_mtid + 1);
80	for (i = 0; i <= smp_cpu_mtid; i++)	105	for (i = 0; i <= smp_cpu_mtid; i++)
@@ -184,10 +209,8 @@ static void topology_update_polarization_simple(void) · 103 unmodified lines
184	{	209	{
185	int cpu;	210	int cpu;
186		211
187	mutex_lock(&smp_cpu_state_mutex);
188	for_each_possible_cpu(cpu)	212	for_each_possible_cpu(cpu)
189	smp_cpu_set_polarization(cpu, POLARIZATION_HRZ);	213	smp_cpu_set_polarization(cpu, POLARIZATION_HRZ);
190	mutex_unlock(&smp_cpu_state_mutex);
191	}	214	}
192		215
193	static int ptf(unsigned long fc)	216	static int ptf(unsigned long fc)
@@ -223,7 +246,7 @@ int topology_set_cpu_management(int fc) · 29 unmodified lines
223	static void update_cpu_masks(void)	246	static void update_cpu_masks(void)
224	{	247	{
225	struct cpu_topology_s390 *topo;	248	struct cpu_topology_s390 *topo;
226	int cpu;	249	int cpu, id;
227		250
228	for_each_possible_cpu(cpu) {	251	for_each_possible_cpu(cpu) {
229	topo = &cpu_topology[cpu];	252	topo = &cpu_topology[cpu];
@@ -231,12 +254,13 @@ static void update_cpu_masks(void) · 1 unmodified line
231	topo->core_mask = cpu_group_map(&socket_info, cpu);	254	topo->core_mask = cpu_group_map(&socket_info, cpu);
232	topo->book_mask = cpu_group_map(&book_info, cpu);	255	topo->book_mask = cpu_group_map(&book_info, cpu);
233	topo->drawer_mask = cpu_group_map(&drawer_info, cpu);	256	topo->drawer_mask = cpu_group_map(&drawer_info, cpu);
234	if (!MACHINE_HAS_TOPOLOGY) {	257	if (topology_mode != TOPOLOGY_MODE_HW) {
		258	id = topology_mode == TOPOLOGY_MODE_PACKAGE ? 0 : cpu;
235	topo->thread_id = cpu;	259	topo->thread_id = cpu;
236	topo->core_id = cpu;	260	topo->core_id = cpu;
237	topo->socket_id = cpu;	261	topo->socket_id = id;
238	topo->book_id = cpu;	262	topo->book_id = id;
239	topo->drawer_id = cpu;	263	topo->drawer_id = id;
240	if (cpu_present(cpu))	264	if (cpu_present(cpu))
241	cpumask_set_cpu(cpu, &cpus_with_topology);	265	cpumask_set_cpu(cpu, &cpus_with_topology);
242	}	266	}
@@ -254,6 +278,7 @@ static int __arch_update_cpu_topology(void) · 11 unmodified lines
254	struct sysinfo_15_1_x *info = tl_info;	278	struct sysinfo_15_1_x *info = tl_info;
255	int rc = 0;	279	int rc = 0;
256		280
		281	mutex_lock(&smp_cpu_state_mutex);
257	cpumask_clear(&cpus_with_topology);	282	cpumask_clear(&cpus_with_topology);
258	if (MACHINE_HAS_TOPOLOGY) {	283	if (MACHINE_HAS_TOPOLOGY) {
259	rc = 1;	284	rc = 1;
@@ -263,6 +288,7 @@ static int __arch_update_cpu_topology(void) · 3 unmodified lines
263	update_cpu_masks();	288	update_cpu_masks();
264	if (!MACHINE_HAS_TOPOLOGY)	289	if (!MACHINE_HAS_TOPOLOGY)
265	topology_update_polarization_simple();	290	topology_update_polarization_simple();
		291	mutex_unlock(&smp_cpu_state_mutex);
266	return rc;	292	return rc;
267	}	293	}
268		294
@@ -289,6 +315,11 @@ void topology_schedule_update(void) · 20 unmodified lines
289	schedule_work(&topology_work);	315	schedule_work(&topology_work);
290	}	316	}
291		317
		318	static void topology_flush_work(void)
		319	{
		320	flush_work(&topology_work);
		321	}
		322
292	static void topology_timer_fn(unsigned long ignored)	323	static void topology_timer_fn(unsigned long ignored)
293	{	324	{
294	if (ptf(PTF_CHECK))	325	if (ptf(PTF_CHECK))
@@ -459,6 +490,12 @@ void __init topology_init_early(void) · 164 unmodified lines
459	struct sysinfo_15_1_x *info;	490	struct sysinfo_15_1_x *info;
460		491
461	set_sched_topology(s390_topology);	492	set_sched_topology(s390_topology);
		493	if (topology_mode == TOPOLOGY_MODE_UNINITIALIZED) {
		494	if (MACHINE_HAS_TOPOLOGY)
		495	topology_mode = TOPOLOGY_MODE_HW;
		496	else
		497	topology_mode = TOPOLOGY_MODE_SINGLE;
		498	}
462	if (!MACHINE_HAS_TOPOLOGY)	499	if (!MACHINE_HAS_TOPOLOGY)
463	goto out;	500	goto out;
464	tl_info = memblock_virt_alloc(PAGE_SIZE, PAGE_SIZE);	501	tl_info = memblock_virt_alloc(PAGE_SIZE, PAGE_SIZE);
@@ -474,12 +511,97 @@ out: · 9 unmodified lines
474	__arch_update_cpu_topology();	511	__arch_update_cpu_topology();
475	}	512	}
476		513
		514	static inline int topology_get_mode(int enabled)
		515	{
		516	if (!enabled)
		517	return TOPOLOGY_MODE_SINGLE;
		518	return MACHINE_HAS_TOPOLOGY ? TOPOLOGY_MODE_HW : TOPOLOGY_MODE_PACKAGE;
		519	}
		520
		521	static inline int topology_is_enabled(void)
		522	{
		523	return topology_mode != TOPOLOGY_MODE_SINGLE;
		524	}
		525
		526	static int __init topology_setup(char *str)
		527	{
		528	bool enabled;
		529	int rc;
		530
		531	rc = kstrtobool(str, &enabled);
		532	if (rc)
		533	return rc;
		534	topology_mode = topology_get_mode(enabled);
		535	return 0;
		536	}
		537	early_param("topology", topology_setup);
		538
		539	static int topology_ctl_handler(struct ctl_table *ctl, int write,
		540	void __user buffer, size_t lenp, loff_t *ppos)
		541	{
		542	unsigned int len;
		543	int new_mode;
		544	char buf[2];
		545
		546	if (!lenp \|\| ppos) {
		547	*lenp = 0;
		548	return 0;
		549	}
		550	if (!write) {
		551	strncpy(buf, topology_is_enabled() ? "1\n" : "0\n",
		552	ARRAY_SIZE(buf));
		553	len = strnlen(buf, ARRAY_SIZE(buf));
		554	if (len > *lenp)
		555	len = *lenp;
		556	if (copy_to_user(buffer, buf, len))
		557	return -EFAULT;
		558	goto out;
		559	}
		560	len = *lenp;
		561	if (copy_from_user(buf, buffer, len > sizeof(buf) ? sizeof(buf) : len))
		562	return -EFAULT;
		563	if (buf[0] != '0' && buf[0] != '1')
		564	return -EINVAL;
		565	mutex_lock(&smp_cpu_state_mutex);
		566	new_mode = topology_get_mode(buf[0] == '1');
		567	if (topology_mode != new_mode) {
		568	topology_mode = new_mode;
		569	topology_schedule_update();
		570	}
		571	mutex_unlock(&smp_cpu_state_mutex);
		572	topology_flush_work();
		573	out:
		574	*lenp = len;
		575	*ppos += len;
		576	return 0;
		577	}
		578
		579	static struct ctl_table topology_ctl_table[] = {
		580	{
		581	.procname = "topology",
		582	.mode = 0644,
		583	.proc_handler = topology_ctl_handler,
		584	},
		585	{ },
		586	};
		587
		588	static struct ctl_table topology_dir_table[] = {
		589	{
		590	.procname = "s390",
		591	.maxlen = 0,
		592	.mode = 0555,
		593	.child = topology_ctl_table,
		594	},
		595	{ },
		596	};
		597
477	static int __init topology_init(void)	598	static int __init topology_init(void)
478	{	599	{
479	if (MACHINE_HAS_TOPOLOGY)	600	if (MACHINE_HAS_TOPOLOGY)
480	set_topology_timer();	601	set_topology_timer();
481	else	602	else
482	topology_update_polarization_simple();	603	topology_update_polarization_simple();
		604	register_sysctl_table(topology_dir_table);
483	return device_create_file(cpu_subsys.dev_root, &dev_attr_dispatching);	605	return device_create_file(cpu_subsys.dev_root, &dev_attr_dispatching);
484	}	606	}
485	device_initcall(topology_init);	607	device_initcall(topology_init);

arch/s390/mm/gup.c+3−4

 static inline int gup_huge_pmd(pmd_t *pmdp, pmd_t pmd, unsigned long addr,
 		unsigned long end, int write, struct page **pages, int *nr)
 {
-	unsigned long mask, result;
 	struct page *head, *page;
+	unsigned long mask;
 	int refs;
-	result = write ? 0 : _SEGMENT_ENTRY_PROTECT;
+	mask = (write ? _SEGMENT_ENTRY_PROTECT : 0) | _SEGMENT_ENTRY_INVALID;
-	mask = result | _SEGMENT_ENTRY_INVALID;
+	if ((pmd_val(pmd) & mask) != 0)
-	if ((pmd_val(pmd) & mask) != result)
 		return 0;
 	VM_BUG_ON(!pfn_valid(pmd_val(pmd) >> PAGE_SHIFT));

arch/sh/include/asm/processor_32.h+0−4

 /* Free all resources held by a thread. */
 extern void release_thread(struct task_struct *);
-/* Copy and release all segment info associated with a VM */
-#define copy_segments(p, mm)	do { } while(0)
-#define release_segments(mm)	do { } while(0)
 /*
  * FPU lazy state save handling.
  */

arch/sh/include/asm/processor_64.h+0−4

 /* Free all resources held by a thread. */
 extern void release_thread(struct task_struct *);
-/* Copy and release all segment info associated with a VM */
-#define copy_segments(p, mm)	do { } while (0)
-#define release_segments(mm)	do { } while (0)
-#define forget_segments()	do { } while (0)
 /*
  * FPU lazy state save handling.
  */

arch/sh/include/cpu-sh2a/cpu/sh7264.h+1−3

@@ -43,9 +43,7 @@ enum { · 42 unmodified lines
43	GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,	43	GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
44	GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,	44	GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
45		45
46	/* Port H */	46	/* Port H - Port H does not have a Data Register */
47	GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
48	GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
49		47
50	/* Port I - not on device */	48	/* Port I - not on device */
51		49

arch/sh/include/cpu-sh2a/cpu/sh7269.h+1−3

@@ -45,9 +45,7 @@ enum { · 44 unmodified lines
45	GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,	45	GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
46	GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,	46	GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
47		47
48	/* Port H */	48	/* Port H - Port H does not have a Data Register */
49	GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
50	GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
51		49
52	/* Port I - not on device */	50	/* Port I - not on device */
53		51

arch/sh/include/cpu-sh4/cpu/sh7722.h+1−1

@@ -67,7 +67,7 @@ enum { · 66 unmodified lines
67	GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,	67	GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
68		68
69	/* PTQ */	69	/* PTQ */
70	GPIO_PTQ7, GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,	70	GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
71	GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,	71	GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
72		72
73	/* PTR */	73	/* PTR */

arch/sh/include/cpu-sh4/cpu/sh7757.h+4−4

@@ -40,7 +40,7 @@ enum { · 39 unmodified lines
40		40
41	/* PTJ */	41	/* PTJ */
42	GPIO_PTJ0, GPIO_PTJ1, GPIO_PTJ2, GPIO_PTJ3,	42	GPIO_PTJ0, GPIO_PTJ1, GPIO_PTJ2, GPIO_PTJ3,
43	GPIO_PTJ4, GPIO_PTJ5, GPIO_PTJ6, GPIO_PTJ7_RESV,	43	GPIO_PTJ4, GPIO_PTJ5, GPIO_PTJ6,
44		44
45	/* PTK */	45	/* PTK */
46	GPIO_PTK0, GPIO_PTK1, GPIO_PTK2, GPIO_PTK3,	46	GPIO_PTK0, GPIO_PTK1, GPIO_PTK2, GPIO_PTK3,
@@ -48,7 +48,7 @@ enum { · 1 unmodified line
48		48
49	/* PTL */	49	/* PTL */
50	GPIO_PTL0, GPIO_PTL1, GPIO_PTL2, GPIO_PTL3,	50	GPIO_PTL0, GPIO_PTL1, GPIO_PTL2, GPIO_PTL3,
51	GPIO_PTL4, GPIO_PTL5, GPIO_PTL6, GPIO_PTL7_RESV,	51	GPIO_PTL4, GPIO_PTL5, GPIO_PTL6,
52		52
53	/* PTM */	53	/* PTM */
54	GPIO_PTM0, GPIO_PTM1, GPIO_PTM2, GPIO_PTM3,	54	GPIO_PTM0, GPIO_PTM1, GPIO_PTM2, GPIO_PTM3,
@@ -56,7 +56,7 @@ enum { · 1 unmodified line
56		56
57	/* PTN */	57	/* PTN */
58	GPIO_PTN0, GPIO_PTN1, GPIO_PTN2, GPIO_PTN3,	58	GPIO_PTN0, GPIO_PTN1, GPIO_PTN2, GPIO_PTN3,
59	GPIO_PTN4, GPIO_PTN5, GPIO_PTN6, GPIO_PTN7_RESV,	59	GPIO_PTN4, GPIO_PTN5, GPIO_PTN6,
60		60
61	/* PTO */	61	/* PTO */
62	GPIO_PTO0, GPIO_PTO1, GPIO_PTO2, GPIO_PTO3,	62	GPIO_PTO0, GPIO_PTO1, GPIO_PTO2, GPIO_PTO3,
@@ -68,7 +68,7 @@ enum { · 5 unmodified lines
68		68
69	/* PTQ */	69	/* PTQ */
70	GPIO_PTQ0, GPIO_PTQ1, GPIO_PTQ2, GPIO_PTQ3,	70	GPIO_PTQ0, GPIO_PTQ1, GPIO_PTQ2, GPIO_PTQ3,
71	GPIO_PTQ4, GPIO_PTQ5, GPIO_PTQ6, GPIO_PTQ7_RESV,	71	GPIO_PTQ4, GPIO_PTQ5, GPIO_PTQ6,
72		72
73	/* PTR */	73	/* PTR */
74	GPIO_PTR0, GPIO_PTR1, GPIO_PTR2, GPIO_PTR3,	74	GPIO_PTR0, GPIO_PTR1, GPIO_PTR2, GPIO_PTR3,

arch/tile/configs/tilegx_defconfig+0−1

@@ -409,5 +409,4 @@ CONFIG_CRYPTO_SEED=m · 408 unmodified lines
409	CONFIG_CRYPTO_SERPENT=m	409	CONFIG_CRYPTO_SERPENT=m
410	CONFIG_CRYPTO_TEA=m	410	CONFIG_CRYPTO_TEA=m
411	CONFIG_CRYPTO_TWOFISH=m	411	CONFIG_CRYPTO_TWOFISH=m
412	CONFIG_CRYPTO_ZLIB=m
413	CONFIG_CRYPTO_LZO=m	412	CONFIG_CRYPTO_LZO=m

arch/tile/configs/tilepro_defconfig+0−2

 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=y
 CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_ECN=m
 CONFIG_IP_NF_TARGET_TTL=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 CONFIG_CRC_CCITT=m
 CONFIG_CRC7=m

arch/tile/kernel/setup.c+1−1

@@ -140,7 +140,7 @@ static int __init setup_maxnodemem(char *str) · 139 unmodified lines
140	{	140	{
141	char *endp;	141	char *endp;
142	unsigned long long maxnodemem;	142	unsigned long long maxnodemem;
143	long node;	143	unsigned long node;
144		144
145	node = str ? simple_strtoul(str, &endp, 0) : INT_MAX;	145	node = str ? simple_strtoul(str, &endp, 0) : INT_MAX;
146	if (node >= MAX_NUMNODES \|\| *endp != ':')	146	if (node >= MAX_NUMNODES \|\| *endp != ':')

arch/um/include/asm/processor-generic.h+0−5

 {
 }
-static inline void mm_copy_segments(struct mm_struct *from_mm,
-				    struct mm_struct *new_mm)
-{
-}
 #define init_stack	(init_thread_union.stack)
 /*

arch/um/kernel/time.c+2−2

@@ -98,7 +98,7 @@ static struct clocksource timer_clocksource = { · 97 unmodified lines
98	.flags = CLOCK_SOURCE_IS_CONTINUOUS,	98	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
99	};	99	};
100		100
101	static void __init timer_setup(void)	101	static void __init um_timer_setup(void)
102	{	102	{
103	int err;	103	int err;
104		104
@@ -132,5 +132,5 @@ void read_persistent_clock(struct timespec *ts) · 27 unmodified lines
132	void __init time_init(void)	132	void __init time_init(void)
133	{	133	{
134	timer_set_signal_handler();	134	timer_set_signal_handler();
135	late_time_init = timer_setup;	135	late_time_init = um_timer_setup;
136	}	136	}

arch/x86/crypto/blowfish-x86_64-asm_64.S+26−22

 #define s3	((16 + 2 + (3 * 256)) * 4)
 /* register macros */
-#define CTX %rdi
+#define CTX %r12
 #define RIO %rsi
 #define RX0 %rax
 #define RX2bh %ch
 #define RX3bh %dh
-#define RT0 %rbp
+#define RT0 %rdi
 #define RT1 %rsi
 #define RT2 %r8
 #define RT3 %r9
-#define RT0d %ebp
+#define RT0d %edi
 #define RT1d %esi
 #define RT2d %r8d
 #define RT3d %r9d
 ENTRY(__blowfish_enc_blk)
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 *	%rcx: bool, if true: xor output
 	 */
-	movq %rbp, %r11;
+	movq %r12, %r11;
+	movq %rdi, CTX;
 	movq %rsi, %r10;
 	movq %rdx, RIO;
 	round_enc(14);
 	add_roundkey_enc(16);
-	movq %r11, %rbp;
+	movq %r11, %r12;
 	movq %r10, RIO;
 	test %cl, %cl;
 ENTRY(blowfish_dec_blk)
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 */
-	movq %rbp, %r11;
+	movq %r12, %r11;
+	movq %rdi, CTX;
 	movq %rsi, %r10;
 	movq %rdx, RIO;
 	movq %r10, RIO;
 	write_block();
-	movq %r11, %rbp;
+	movq %r11, %r12;
 	ret;
 ENDPROC(blowfish_dec_blk)
 ENTRY(__blowfish_enc_blk_4way)
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 *	%rcx: bool, if true: xor output
 	 */
-	pushq %rbp;
+	pushq %r12;
 	pushq %rbx;
 	pushq %rcx;
-	preload_roundkey_enc(0);
+	movq %rdi, CTX
 	movq %rsi, %r11;
 	movq %rdx, RIO;
+	preload_roundkey_enc(0);
 	read_block4();
 	round_enc4(0);
 	round_enc4(14);
 	add_preloaded_roundkey4();
-	popq %rbp;
+	popq %r12;
 	movq %r11, RIO;
-	test %bpl, %bpl;
+	test %r12b, %r12b;
 	jnz .L__enc_xor4;
 	write_block4();
 	popq %rbx;
-	popq %rbp;
+	popq %r12;
 	ret;
 .L__enc_xor4:
 	xor_block4();
 	popq %rbx;
-	popq %rbp;
+	popq %r12;
 	ret;
 ENDPROC(__blowfish_enc_blk_4way)
 ENTRY(blowfish_dec_blk_4way)
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 */
-	pushq %rbp;
+	pushq %r12;
 	pushq %rbx;
-	preload_roundkey_dec(17);
-	movq %rsi, %r11;
+	movq %rdi, CTX;
+	movq %rsi, %r11
 	movq %rdx, RIO;
+	preload_roundkey_dec(17);
 	read_block4();
 	round_dec4(17);
 	write_block4();
 	popq %rbx;
-	popq %rbp;
+	popq %r12;
 	ret;
 ENDPROC(blowfish_dec_blk_4way)

arch/x86/crypto/camellia-x86_64-asm_64.S+13−13

@@ -75,17 +75,17 @@ · 74 unmodified lines
75	#define RCD1bh %dh	75	#define RCD1bh %dh
76		76
77	#define RT0 %rsi	77	#define RT0 %rsi
78	#define RT1 %rbp	78	#define RT1 %r12
79	#define RT2 %r8	79	#define RT2 %r8
80		80
81	#define RT0d %esi	81	#define RT0d %esi
82	#define RT1d %ebp	82	#define RT1d %r12d
83	#define RT2d %r8d	83	#define RT2d %r8d
84		84
85	#define RT2bl %r8b	85	#define RT2bl %r8b
86		86
87	#define RXOR %r9	87	#define RXOR %r9
88	#define RRBP %r10	88	#define RR12 %r10
89	#define RDST %r11	89	#define RDST %r11
90		90
91	#define RXORd %r9d	91	#define RXORd %r9d
@@ -197,7 +197,7 @@ ENTRY(__camellia_enc_blk) · 105 unmodified lines
197	* %rdx: src	197	* %rdx: src
198	* %rcx: bool xor	198	* %rcx: bool xor
199	*/	199	*/
200	movq %rbp, RRBP;	200	movq %r12, RR12;
201		201
202	movq %rcx, RXOR;	202	movq %rcx, RXOR;
203	movq %rsi, RDST;	203	movq %rsi, RDST;
@@ -227,13 +227,13 @@ ENTRY(__camellia_enc_blk) · 23 unmodified lines
227		227
228	enc_outunpack(mov, RT1);	228	enc_outunpack(mov, RT1);
229		229
230	movq RRBP, %rbp;	230	movq RR12, %r12;
231	ret;	231	ret;
232		232
233	.L__enc_xor:	233	.L__enc_xor:
234	enc_outunpack(xor, RT1);	234	enc_outunpack(xor, RT1);
235		235
236	movq RRBP, %rbp;	236	movq RR12, %r12;
237	ret;	237	ret;
238	ENDPROC(__camellia_enc_blk)	238	ENDPROC(__camellia_enc_blk)
239		239
@@ -248,7 +248,7 @@ ENTRY(camellia_dec_blk) · 8 unmodified lines
248	movl $24, RXORd;	248	movl $24, RXORd;
249	cmovel RXORd, RT2d; /* max */	249	cmovel RXORd, RT2d; /* max */
250		250
251	movq %rbp, RRBP;	251	movq %r12, RR12;
252	movq %rsi, RDST;	252	movq %rsi, RDST;
253	movq %rdx, RIO;	253	movq %rdx, RIO;
254		254
@@ -271,7 +271,7 @@ ENTRY(camellia_dec_blk) · 16 unmodified lines
271		271
272	dec_outunpack();	272	dec_outunpack();
273		273
274	movq RRBP, %rbp;	274	movq RR12, %r12;
275	ret;	275	ret;
276	ENDPROC(camellia_dec_blk)	276	ENDPROC(camellia_dec_blk)
277		277
@@ -433,7 +433,7 @@ ENTRY(__camellia_enc_blk_2way) · 155 unmodified lines
433	*/	433	*/
434	pushq %rbx;	434	pushq %rbx;
435		435
436	movq %rbp, RRBP;	436	movq %r12, RR12;
437	movq %rcx, RXOR;	437	movq %rcx, RXOR;
438	movq %rsi, RDST;	438	movq %rsi, RDST;
439	movq %rdx, RIO;	439	movq %rdx, RIO;
@@ -461,14 +461,14 @@ ENTRY(__camellia_enc_blk_2way) · 21 unmodified lines
461		461
462	enc_outunpack2(mov, RT2);	462	enc_outunpack2(mov, RT2);
463		463
464	movq RRBP, %rbp;	464	movq RR12, %r12;
465	popq %rbx;	465	popq %rbx;
466	ret;	466	ret;
467		467
468	.L__enc2_xor:	468	.L__enc2_xor:
469	enc_outunpack2(xor, RT2);	469	enc_outunpack2(xor, RT2);
470		470
471	movq RRBP, %rbp;	471	movq RR12, %r12;
472	popq %rbx;	472	popq %rbx;
473	ret;	473	ret;
474	ENDPROC(__camellia_enc_blk_2way)	474	ENDPROC(__camellia_enc_blk_2way)
@@ -485,7 +485,7 @@ ENTRY(camellia_dec_blk_2way) · 10 unmodified lines
485	cmovel RXORd, RT2d; /* max */	485	cmovel RXORd, RT2d; /* max */
486		486
487	movq %rbx, RXOR;	487	movq %rbx, RXOR;
488	movq %rbp, RRBP;	488	movq %r12, RR12;
489	movq %rsi, RDST;	489	movq %rsi, RDST;
490	movq %rdx, RIO;	490	movq %rdx, RIO;
491		491
@@ -508,7 +508,7 @@ ENTRY(camellia_dec_blk_2way) · 16 unmodified lines
508		508
509	dec_outunpack2();	509	dec_outunpack2();
510		510
511	movq RRBP, %rbp;	511	movq RR12, %r12;
512	movq RXOR, %rbx;	512	movq RXOR, %rbx;
513	ret;	513	ret;
514	ENDPROC(camellia_dec_blk_2way)	514	ENDPROC(camellia_dec_blk_2way)

arch/x86/crypto/cast5-avx-x86_64-asm_64.S+30−17

 /**********************************************************************
   16-way AVX cast5
  **********************************************************************/
-#define CTX %rdi
+#define CTX %r15
 #define RL1 %xmm0
 #define RR1 %xmm1
 #define RTMP %xmm15
-#define RID1  %rbp
+#define RID1  %rdi
-#define RID1d %ebp
+#define RID1d %edi
 #define RID2  %rsi
 #define RID2d %esi
 .align 16
 __cast5_enc_blk16:
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	RL1: blocks 1 and 2
 	 *	RR1: blocks 3 and 4
 	 *	RL2: blocks 5 and 6
 	 *	RR4: encrypted blocks 15 and 16
 	 */
-	pushq %rbp;
+	pushq %r15;
 	pushq %rbx;
+	movq %rdi, CTX;
 	vmovdqa .Lbswap_mask, RKM;
 	vmovd .Lfirst_mask, R1ST;
 	vmovd .L32_mask, R32;
 .L__skip_enc:
 	popq %rbx;
-	popq %rbp;
+	popq %r15;
 	vmovdqa .Lbswap_mask, RKM;
 .align 16
 __cast5_dec_blk16:
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	RL1: encrypted blocks 1 and 2
 	 *	RR1: encrypted blocks 3 and 4
 	 *	RL2: encrypted blocks 5 and 6
 	 *	RR4: decrypted blocks 15 and 16
 	 */
-	pushq %rbp;
+	pushq %r15;
 	pushq %rbx;
+	movq %rdi, CTX;
 	vmovdqa .Lbswap_mask, RKM;
 	vmovd .Lfirst_mask, R1ST;
 	vmovd .L32_mask, R32;
 	vmovdqa .Lbswap_mask, RKM;
 	popq %rbx;
-	popq %rbp;
+	popq %r15;
 	outunpack_blocks(RR1, RL1, RTMP, RX, RKM);
 	outunpack_blocks(RR2, RL2, RTMP, RX, RKM);
 ENTRY(cast5_ecb_enc_16way)
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 */
 	FRAME_BEGIN
+	pushq %r15;
+	movq %rdi, CTX;
 	movq %rsi, %r11;
 	vmovdqu (0*4*4)(%rdx), RL1;
 	vmovdqu RR4, (6*4*4)(%r11);
 	vmovdqu RL4, (7*4*4)(%r11);
+	popq %r15;
 	FRAME_END
 	ret;
 ENDPROC(cast5_ecb_enc_16way)
 ENTRY(cast5_ecb_dec_16way)
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 */
 	FRAME_BEGIN
+	pushq %r15;
+	movq %rdi, CTX;
 	movq %rsi, %r11;
 	vmovdqu (0*4*4)(%rdx), RL1;
 	vmovdqu RR4, (6*4*4)(%r11);
 	vmovdqu RL4, (7*4*4)(%r11);
+	popq %r15;
 	FRAME_END
 	ret;
 ENDPROC(cast5_ecb_dec_16way)
 ENTRY(cast5_cbc_dec_16way)
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 */
 	FRAME_BEGIN
 	pushq %r12;
+	pushq %r15;
+	movq %rdi, CTX;
 	movq %rsi, %r11;
 	movq %rdx, %r12;
 	vmovdqu RR4, (6*16)(%r11);
 	vmovdqu RL4, (7*16)(%r11);
+	popq %r15;
 	popq %r12;
 	FRAME_END
 	ret;
 ENDPROC(cast5_cbc_dec_16way)
 ENTRY(cast5_ctr_16way)
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 *	%rcx: iv (big endian, 64bit)
 	 */
 	FRAME_BEGIN
 	pushq %r12;
+	pushq %r15;
+	movq %rdi, CTX;
 	movq %rsi, %r11;
 	movq %rdx, %r12;
 	vmovdqu RR4, (6*16)(%r11);
 	vmovdqu RL4, (7*16)(%r11);
+	popq %r15;
 	popq %r12;
 	FRAME_END
 	ret;
 ENDPROC(cast5_ctr_16way)

arch/x86/crypto/cast6-avx-x86_64-asm_64.S+34−16

 /**********************************************************************
   8-way AVX cast6
  **********************************************************************/
-#define CTX %rdi
+#define CTX %r15
 #define RA1 %xmm0
 #define RB1 %xmm1
 #define RTMP %xmm15
-#define RID1  %rbp
+#define RID1  %rdi
-#define RID1d %ebp
+#define RID1d %edi
 #define RID2  %rsi
 #define RID2d %esi
 .align 8
 __cast6_enc_blk8:
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2: blocks
 	 * output:
 	 *	RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2: encrypted blocks
 	 */
-	pushq %rbp;
+	pushq %r15;
 	pushq %rbx;
+	movq %rdi, CTX;
 	vmovdqa .Lbswap_mask, RKM;
 	vmovd .Lfirst_mask, R1ST;
 	vmovd .L32_mask, R32;
 	QBAR(11);
 	popq %rbx;
-	popq %rbp;
+	popq %r15;
 	vmovdqa .Lbswap_mask, RKM;
 .align 8
 __cast6_dec_blk8:
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2: encrypted blocks
 	 * output:
 	 *	RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2: decrypted blocks
 	 */
-	pushq %rbp;
+	pushq %r15;
 	pushq %rbx;
+	movq %rdi, CTX;
 	vmovdqa .Lbswap_mask, RKM;
 	vmovd .Lfirst_mask, R1ST;
 	vmovd .L32_mask, R32;
 	QBAR(0);
 	popq %rbx;
-	popq %rbp;
+	popq %r15;
 	vmovdqa .Lbswap_mask, RKM;
 	outunpack_blocks(RA1, RB1, RC1, RD1, RTMP, RX, RKRF, RKM);
 ENTRY(cast6_ecb_enc_8way)
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 */
 	FRAME_BEGIN
+	pushq %r15;
+	movq %rdi, CTX;
 	movq %rsi, %r11;
 	load_8way(%rdx, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
 	store_8way(%r11, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+	popq %r15;
 	FRAME_END
 	ret;
 ENDPROC(cast6_ecb_enc_8way)
 ENTRY(cast6_ecb_dec_8way)
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 */
 	FRAME_BEGIN
+	pushq %r15;
+	movq %rdi, CTX;
 	movq %rsi, %r11;
 	load_8way(%rdx, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
 	store_8way(%r11, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+	popq %r15;
 	FRAME_END
 	ret;
 ENDPROC(cast6_ecb_dec_8way)
 ENTRY(cast6_cbc_dec_8way)
 	/* input:
-	 *	%rdi: ctx, CTX
+	 *	%rdi: ctx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 */
 	FRAME_BEGIN
 	pushq %r12;
+	pushq %r15;
+	movq %rdi, CTX;
 	movq %rsi, %r11;
 	movq %rdx, %r12;
 	store_cbc_8way(%r12, %r11, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+	popq %r15;
 	popq %r12;
 	FRAME_END
 	ret;
 ENDPROC(cast6_cbc_dec_8way)
 	 *	%rcx: iv (little endian, 128bit)
 	 */
 	FRAME_BEGIN
 	pushq %r12;
+	pushq %r15
+	movq %rdi, CTX;
 	movq %rsi, %r11;
 	movq %rdx, %r12;
 	store_ctr_8way(%r12, %r11, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+	popq %r15;
 	popq %r12;
 	FRAME_END
 	ret;
 ENDPROC(cast6_ctr_8way)
 	 *	%rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
 	 */
 	FRAME_BEGIN
+	pushq %r15;
+	movq %rdi, CTX
 	movq %rsi, %r11;
 	/* regs <= src, dst <= IVs, regs <= regs xor IVs */
 	/* dst <= regs xor IVs(in dst) */
 	store_xts_8way(%r11, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+	popq %r15;
 	FRAME_END
 	ret;
 ENDPROC(cast6_xts_enc_8way)
 	 *	%rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
 	 */
 	FRAME_BEGIN
+	pushq %r15;
+	movq %rdi, CTX
 	movq %rsi, %r11;
 	/* regs <= src, dst <= IVs, regs <= regs xor IVs */
 	/* dst <= regs xor IVs(in dst) */
 	store_xts_8way(%r11, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+	popq %r15;
 	FRAME_END
 	ret;
 ENDPROC(cast6_xts_dec_8way)

arch/x86/crypto/des3_ede-asm_64.S+9−6

 #define RW2bh %ch
 #define RT0 %r15
-#define RT1 %rbp
+#define RT1 %rsi
 #define RT2 %r14
 #define RT3 %rdx
 #define RT0d %r15d
-#define RT1d %ebp
+#define RT1d %esi
 #define RT2d %r14d
 #define RT3d %edx
 	 *	%rsi: dst
 	 *	%rdx: src
 	 */
-	pushq %rbp;
 	pushq %rbx;
 	pushq %r12;
 	pushq %r13;
 	pushq %r14;
 	pushq %r15;
+	pushq %rsi; /* dst */
 	read_block(%rdx, RL0, RR0);
 	initial_permutation(RL0, RR0);
 	round1(32+15, RL0, RR0, dummy2);
 	final_permutation(RR0, RL0);
+	popq %rsi /* dst */
 	write_block(%rsi, RR0, RL0);
 	popq %r15;
 	popq %r13;
 	popq %r12;
 	popq %rbx;
-	popq %rbp;
 	ret;
 ENDPROC(des3_ede_x86_64_crypt_blk)
 	 *	%rdx: src (3 blocks)
 	 */
-	pushq %rbp;
 	pushq %rbx;
 	pushq %r12;
 	pushq %r13;
 	pushq %r14;
 	pushq %r15;
+	pushq %rsi /* dst */
 	/* load input */
 	movl 0 * 4(%rdx), RL0d;
 	movl 1 * 4(%rdx), RR0d;
 	bswapl RR2d;
 	bswapl RL2d;
+	popq %rsi /* dst */
 	movl RR0d, 0 * 4(%rsi);
 	movl RL0d, 1 * 4(%rsi);
 	movl RR1d, 2 * 4(%rsi);
 	popq %r13;
 	popq %r12;
 	popq %rbx;
-	popq %rbp;
 	ret;
 ENDPROC(des3_ede_x86_64_crypt_blk_3way)

arch/x86/crypto/sha1_avx2_x86_64_asm.S+1−3

 #define	REG_RE	%rdx
 #define	REG_RTA	%r12
 #define	REG_RTB	%rbx
-#define	REG_T1	%ebp
+#define	REG_T1	%r11d
 #define	xmm_mov	vmovups
 #define	avx2_zeroupper	vzeroupper
 #define	RND_F1	1
 	ENTRY(\name)
 	push	%rbx
-	push	%rbp
 	push	%r12
 	push	%r13
 	push	%r14
 	pop	%r14
 	pop	%r13
 	pop	%r12
-	pop	%rbp
 	pop	%rbx
 	ret

arch/x86/crypto/sha1_ssse3_asm.S+5−6

 #define REG_A	%ecx
 #define REG_B	%esi
 #define REG_C	%edi
-#define REG_D	%ebp
+#define REG_D	%r12d
 #define REG_E	%edx
 #define REG_T1	%eax
 	ENTRY(\name)
 	push	%rbx
-	push	%rbp
 	push	%r12
+	push	%rbp
+	mov	%rsp, %rbp
-	mov	%rsp, %r12
 	sub	$64, %rsp		# allocate workspace
 	and	$~15, %rsp		# align stack
 	xor	%rax, %rax
 	rep stosq
-	mov	%r12, %rsp		# deallocate workspace
+	mov	%rbp, %rsp		# deallocate workspace
-	pop	%r12
 	pop	%rbp
+	pop	%r12
 	pop	%rbx
 	ret

arch/x86/crypto/sha256-avx-asm.S+7−8

@@ -103,7 +103,7 @@ SRND = %rsi # clobbers INP · 102 unmodified lines
103	c = %ecx	103	c = %ecx
104	d = %r8d	104	d = %r8d
105	e = %edx	105	e = %edx
106	TBL = %rbp	106	TBL = %r12
107	a = %eax	107	a = %eax
108	b = %ebx	108	b = %ebx
109		109
@@ -350,13 +350,13 @@ a = TMP_ · 240 unmodified lines
350	ENTRY(sha256_transform_avx)	350	ENTRY(sha256_transform_avx)
351	.align 32	351	.align 32
352	pushq %rbx	352	pushq %rbx
353	pushq %rbp	353	pushq %r12
354	pushq %r13	354	pushq %r13
355	pushq %r14	355	pushq %r14
356	pushq %r15	356	pushq %r15
357	pushq %r12	357	pushq %rbp
		358	movq %rsp, %rbp
358		359
359	mov %rsp, %r12
360	subq $STACK_SIZE, %rsp # allocate stack space	360	subq $STACK_SIZE, %rsp # allocate stack space
361	and $~15, %rsp # align stack pointer	361	and $~15, %rsp # align stack pointer
362		362
@@ -452,13 +452,12 @@ loop2: · 89 unmodified lines
452		452
453	done_hash:	453	done_hash:
454		454
455	mov %r12, %rsp	455	mov %rbp, %rsp
456		456	popq %rbp
457	popq %r12
458	popq %r15	457	popq %r15
459	popq %r14	458	popq %r14
460	popq %r13	459	popq %r13
461	popq %rbp	460	popq %r12
462	popq %rbx	461	popq %rbx
463	ret	462	ret
464	ENDPROC(sha256_transform_avx)	463	ENDPROC(sha256_transform_avx)

arch/x86/crypto/sha256-avx2-asm.S+7−15

@@ -98,8 +98,6 @@ d = %r8d · 97 unmodified lines
98	e = %edx # clobbers NUM_BLKS	98	e = %edx # clobbers NUM_BLKS
99	y3 = %esi # clobbers INP	99	y3 = %esi # clobbers INP
100		100
101
102	TBL = %rbp
103	SRND = CTX # SRND is same register as CTX	101	SRND = CTX # SRND is same register as CTX
104		102
105	a = %eax	103	a = %eax
@@ -531,7 +529,6 @@ STACK_SIZE = _RSP + _RSP_SIZE · 425 unmodified lines
531	ENTRY(sha256_transform_rorx)	529	ENTRY(sha256_transform_rorx)
532	.align 32	530	.align 32
533	pushq %rbx	531	pushq %rbx
534	pushq %rbp
535	pushq %r12	532	pushq %r12
536	pushq %r13	533	pushq %r13
537	pushq %r14	534	pushq %r14
@@ -568,8 +565,6 @@ ENTRY(sha256_transform_rorx) · 30 unmodified lines
568	mov CTX, _CTX(%rsp)	565	mov CTX, _CTX(%rsp)
569		566
570	loop0:	567	loop0:
571	lea K256(%rip), TBL
572
573	## Load first 16 dwords from two blocks	568	## Load first 16 dwords from two blocks
574	VMOVDQ 0*32(INP),XTMP0	569	VMOVDQ 0*32(INP),XTMP0
575	VMOVDQ 1*32(INP),XTMP1	570	VMOVDQ 1*32(INP),XTMP1
@@ -597,19 +592,19 @@ last_block_enter: · 21 unmodified lines
597		592
598	.align 16	593	.align 16
599	loop1:	594	loop1:
600	vpaddd 0*32(TBL, SRND), X0, XFER	595	vpaddd K256+0*32(SRND), X0, XFER
601	vmovdqa XFER, 0*32+_XFER(%rsp, SRND)	596	vmovdqa XFER, 0*32+_XFER(%rsp, SRND)
602	FOUR_ROUNDS_AND_SCHED _XFER + 0*32	597	FOUR_ROUNDS_AND_SCHED _XFER + 0*32
603		598
604	vpaddd 1*32(TBL, SRND), X0, XFER	599	vpaddd K256+1*32(SRND), X0, XFER
605	vmovdqa XFER, 1*32+_XFER(%rsp, SRND)	600	vmovdqa XFER, 1*32+_XFER(%rsp, SRND)
606	FOUR_ROUNDS_AND_SCHED _XFER + 1*32	601	FOUR_ROUNDS_AND_SCHED _XFER + 1*32
607		602
608	vpaddd 2*32(TBL, SRND), X0, XFER	603	vpaddd K256+2*32(SRND), X0, XFER
609	vmovdqa XFER, 2*32+_XFER(%rsp, SRND)	604	vmovdqa XFER, 2*32+_XFER(%rsp, SRND)
610	FOUR_ROUNDS_AND_SCHED _XFER + 2*32	605	FOUR_ROUNDS_AND_SCHED _XFER + 2*32
611		606
612	vpaddd 3*32(TBL, SRND), X0, XFER	607	vpaddd K256+3*32(SRND), X0, XFER
613	vmovdqa XFER, 3*32+_XFER(%rsp, SRND)	608	vmovdqa XFER, 3*32+_XFER(%rsp, SRND)
614	FOUR_ROUNDS_AND_SCHED _XFER + 3*32	609	FOUR_ROUNDS_AND_SCHED _XFER + 3*32
615		610
@@ -619,10 +614,11 @@ loop1: · 3 unmodified lines
619		614
620	loop2:	615	loop2:
621	## Do last 16 rounds with no scheduling	616	## Do last 16 rounds with no scheduling
622	vpaddd 0*32(TBL, SRND), X0, XFER	617	vpaddd K256+0*32(SRND), X0, XFER
623	vmovdqa XFER, 0*32+_XFER(%rsp, SRND)	618	vmovdqa XFER, 0*32+_XFER(%rsp, SRND)
624	DO_4ROUNDS _XFER + 0*32	619	DO_4ROUNDS _XFER + 0*32
625	vpaddd 1*32(TBL, SRND), X1, XFER	620
		621	vpaddd K256+1*32(SRND), X1, XFER
626	vmovdqa XFER, 1*32+_XFER(%rsp, SRND)	622	vmovdqa XFER, 1*32+_XFER(%rsp, SRND)
627	DO_4ROUNDS _XFER + 1*32	623	DO_4ROUNDS _XFER + 1*32
628	add $2*32, SRND	624	add $2*32, SRND
@@ -676,9 +672,6 @@ loop3: · 47 unmodified lines
676	ja done_hash	672	ja done_hash
677		673
678	do_last_block:	674	do_last_block:
679	#### do last block
680	lea K256(%rip), TBL
681
682	VMOVDQ 0*16(INP),XWORD0	675	VMOVDQ 0*16(INP),XWORD0
683	VMOVDQ 1*16(INP),XWORD1	676	VMOVDQ 1*16(INP),XWORD1
684	VMOVDQ 2*16(INP),XWORD2	677	VMOVDQ 2*16(INP),XWORD2
@@ -718,7 +711,6 @@ done_hash: · 33 unmodified lines
718	popq %r14	711	popq %r14
719	popq %r13	712	popq %r13
720	popq %r12	713	popq %r12
721	popq %rbp
722	popq %rbx	714	popq %rbx
723	ret	715	ret
724	ENDPROC(sha256_transform_rorx)	716	ENDPROC(sha256_transform_rorx)

arch/x86/crypto/sha256-ssse3-asm.S+7−8

@@ -95,7 +95,7 @@ SRND = %rsi # clobbers INP · 94 unmodified lines
95	c = %ecx	95	c = %ecx
96	d = %r8d	96	d = %r8d
97	e = %edx	97	e = %edx
98	TBL = %rbp	98	TBL = %r12
99	a = %eax	99	a = %eax
100	b = %ebx	100	b = %ebx
101		101
@@ -356,13 +356,13 @@ a = TMP_ · 254 unmodified lines
356	ENTRY(sha256_transform_ssse3)	356	ENTRY(sha256_transform_ssse3)
357	.align 32	357	.align 32
358	pushq %rbx	358	pushq %rbx
359	pushq %rbp	359	pushq %r12
360	pushq %r13	360	pushq %r13
361	pushq %r14	361	pushq %r14
362	pushq %r15	362	pushq %r15
363	pushq %r12	363	pushq %rbp
		364	mov %rsp, %rbp
364		365
365	mov %rsp, %r12
366	subq $STACK_SIZE, %rsp	366	subq $STACK_SIZE, %rsp
367	and $~15, %rsp	367	and $~15, %rsp
368		368
@@ -462,13 +462,12 @@ loop2: · 93 unmodified lines
462		462
463	done_hash:	463	done_hash:
464		464
465	mov %r12, %rsp	465	mov %rbp, %rsp
466		466	popq %rbp
467	popq %r12
468	popq %r15	467	popq %r15
469	popq %r14	468	popq %r14
470	popq %r13	469	popq %r13
471	popq %rbp	470	popq %r12
472	popq %rbx	471	popq %rbx
473		472
474	ret	473	ret

arch/x86/crypto/sha512-avx2-asm.S+39−36

 BYTE_FLIP_MASK  = %ymm9
-# 1st arg
+# 1st arg is %rdi, which is saved to the stack and accessed later via %r12
-CTX         = %rdi
+CTX1        = %rdi
+CTX2        = %r12
 # 2nd arg
 INP         = %rsi
 # 3rd arg
 e           = %rdx
 y3          = %rsi
-TBL   = %rbp
+TBL   = %rdi # clobbers CTX1
 a     = %rax
 b     = %rbx
 h     = %r11
 old_h = %r11
-T1    = %r12
+T1    = %r12 # clobbers CTX2
 y0    = %r13
 y1    = %r14
 y2    = %r15
-y4    = %r12
 # Local variables (stack frame)
 XFER_SIZE = 4*8
 SRND_SIZE = 1*8
 INP_SIZE = 1*8
 INPEND_SIZE = 1*8
+CTX_SIZE = 1*8
 RSPSAVE_SIZE = 1*8
-GPRSAVE_SIZE = 6*8
+GPRSAVE_SIZE = 5*8
 frame_XFER = 0
 frame_SRND = frame_XFER + XFER_SIZE
 frame_INP = frame_SRND + SRND_SIZE
 frame_INPEND = frame_INP + INP_SIZE
-frame_RSPSAVE = frame_INPEND + INPEND_SIZE
+frame_CTX = frame_INPEND + INPEND_SIZE
+frame_RSPSAVE = frame_CTX + CTX_SIZE
 frame_GPRSAVE = frame_RSPSAVE + RSPSAVE_SIZE
 frame_size = frame_GPRSAVE + GPRSAVE_SIZE
 	mov	%rax, frame_RSPSAVE(%rsp)
 	# Save GPRs
-	mov	%rbp, frame_GPRSAVE(%rsp)
+	mov	%rbx, 8*0+frame_GPRSAVE(%rsp)
-	mov	%rbx, 8*1+frame_GPRSAVE(%rsp)
+	mov	%r12, 8*1+frame_GPRSAVE(%rsp)
-	mov	%r12, 8*2+frame_GPRSAVE(%rsp)
+	mov	%r13, 8*2+frame_GPRSAVE(%rsp)
-	mov	%r13, 8*3+frame_GPRSAVE(%rsp)
+	mov	%r14, 8*3+frame_GPRSAVE(%rsp)
-	mov	%r14, 8*4+frame_GPRSAVE(%rsp)
+	mov	%r15, 8*4+frame_GPRSAVE(%rsp)
-	mov	%r15, 8*5+frame_GPRSAVE(%rsp)
 	shl	$7, NUM_BLKS	# convert to bytes
 	jz	done_hash
 	mov	NUM_BLKS, frame_INPEND(%rsp)
 	## load initial digest
-	mov	8*0(CTX),a
+	mov	8*0(CTX1), a
-	mov	8*1(CTX),b
+	mov	8*1(CTX1), b
-	mov	8*2(CTX),c
+	mov	8*2(CTX1), c
-	mov	8*3(CTX),d
+	mov	8*3(CTX1), d
-	mov	8*4(CTX),e
+	mov	8*4(CTX1), e
-	mov	8*5(CTX),f
+	mov	8*5(CTX1), f
-	mov	8*6(CTX),g
+	mov	8*6(CTX1), g
-	mov	8*7(CTX),h
+	mov	8*7(CTX1), h
+	# save %rdi (CTX) before it gets clobbered
+	mov	%rdi, frame_CTX(%rsp)
 	vmovdqa	PSHUFFLE_BYTE_FLIP_MASK(%rip), BYTE_FLIP_MASK
 	subq	$1, frame_SRND(%rsp)
 	jne	loop2
-	addm	8*0(CTX),a
+	mov	frame_CTX(%rsp), CTX2
-	addm	8*1(CTX),b
+	addm	8*0(CTX2), a
-	addm	8*2(CTX),c
+	addm	8*1(CTX2), b
-	addm	8*3(CTX),d
+	addm	8*2(CTX2), c
-	addm	8*4(CTX),e
+	addm	8*3(CTX2), d
-	addm	8*5(CTX),f
+	addm	8*4(CTX2), e
-	addm	8*6(CTX),g
+	addm	8*5(CTX2), f
-	addm	8*7(CTX),h
+	addm	8*6(CTX2), g
+	addm	8*7(CTX2), h
 	mov	frame_INP(%rsp), INP
 	add	$128, INP
 done_hash:
 # Restore GPRs
-	mov	frame_GPRSAVE(%rsp)     ,%rbp
+	mov	8*0+frame_GPRSAVE(%rsp), %rbx
-	mov	8*1+frame_GPRSAVE(%rsp) ,%rbx
+	mov	8*1+frame_GPRSAVE(%rsp), %r12
-	mov	8*2+frame_GPRSAVE(%rsp) ,%r12
+	mov	8*2+frame_GPRSAVE(%rsp), %r13
-	mov	8*3+frame_GPRSAVE(%rsp) ,%r13
+	mov	8*3+frame_GPRSAVE(%rsp), %r14
-	mov	8*4+frame_GPRSAVE(%rsp) ,%r14
+	mov	8*4+frame_GPRSAVE(%rsp), %r15
-	mov	8*5+frame_GPRSAVE(%rsp) ,%r15
 	# Restore Stack Pointer
 	mov	frame_RSPSAVE(%rsp), %rsp

arch/x86/crypto/twofish-avx-x86_64-asm_64.S+6−6

@@ -76,8 +76,8 @@ · 75 unmodified lines
76	#define RT %xmm14	76	#define RT %xmm14
77	#define RR %xmm15	77	#define RR %xmm15
78		78
79	#define RID1 %rbp	79	#define RID1 %r13
80	#define RID1d %ebp	80	#define RID1d %r13d
81	#define RID2 %rsi	81	#define RID2 %rsi
82	#define RID2d %esi	82	#define RID2d %esi
83		83
@@ -259,7 +259,7 @@ __twofish_enc_blk8: · 175 unmodified lines
259		259
260	vmovdqu w(CTX), RK1;	260	vmovdqu w(CTX), RK1;
261		261
262	pushq %rbp;	262	pushq %r13;
263	pushq %rbx;	263	pushq %rbx;
264	pushq %rcx;	264	pushq %rcx;
265		265
@@ -282,7 +282,7 @@ __twofish_enc_blk8: · 16 unmodified lines
282		282
283	popq %rcx;	283	popq %rcx;
284	popq %rbx;	284	popq %rbx;
285	popq %rbp;	285	popq %r13;
286		286
287	outunpack_blocks(RC1, RD1, RA1, RB1, RK1, RX0, RY0, RK2);	287	outunpack_blocks(RC1, RD1, RA1, RB1, RK1, RX0, RY0, RK2);
288	outunpack_blocks(RC2, RD2, RA2, RB2, RK1, RX0, RY0, RK2);	288	outunpack_blocks(RC2, RD2, RA2, RB2, RK1, RX0, RY0, RK2);
@@ -301,7 +301,7 @@ __twofish_dec_blk8: · 12 unmodified lines
301		301
302	vmovdqu (w+4*4)(CTX), RK1;	302	vmovdqu (w+4*4)(CTX), RK1;
303		303
304	pushq %rbp;	304	pushq %r13;
305	pushq %rbx;	305	pushq %rbx;
306		306
307	inpack_blocks(RC1, RD1, RA1, RB1, RK1, RX0, RY0, RK2);	307	inpack_blocks(RC1, RD1, RA1, RB1, RK1, RX0, RY0, RK2);
@@ -322,7 +322,7 @@ __twofish_dec_blk8: · 14 unmodified lines
322	vmovdqu (w)(CTX), RK1;	322	vmovdqu (w)(CTX), RK1;
323		323
324	popq %rbx;	324	popq %rbx;
325	popq %rbp;	325	popq %r13;
326		326
327	outunpack_blocks(RA1, RB1, RC1, RD1, RK1, RX0, RY0, RK2);	327	outunpack_blocks(RA1, RB1, RC1, RD1, RK1, RX0, RY0, RK2);
328	outunpack_blocks(RA2, RB2, RC2, RD2, RK1, RX0, RY0, RK2);	328	outunpack_blocks(RA2, RB2, RC2, RD2, RK1, RX0, RY0, RK2);

arch/x86/events/intel/core.c+4−7

@@ -4409,10 +4409,9 @@ static __init int fixup_ht_bug(void) · 4408 unmodified lines
4409	return 0;	4409	return 0;
4410	}	4410	}
4411		4411
4412	if (lockup_detector_suspend() != 0) {	4412	cpus_read_lock();
4413	pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");	4413
4414	return 0;	4414	hardlockup_detector_perf_stop();
4415	}
4416		4415
4417	x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS \| PMU_FL_EXCL_ENABLED);	4416	x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS \| PMU_FL_EXCL_ENABLED);
4418		4417
@@ -4420,9 +4419,7 @@ static __init int fixup_ht_bug(void) · 1 unmodified line
4420	x86_pmu.commit_scheduling = NULL;	4419	x86_pmu.commit_scheduling = NULL;
4421	x86_pmu.stop_scheduling = NULL;	4420	x86_pmu.stop_scheduling = NULL;
4422		4421
4423	lockup_detector_resume();	4422	hardlockup_detector_perf_restart();
4424
4425	cpus_read_lock();
4426		4423
4427	for_each_online_cpu(c)	4424	for_each_online_cpu(c)
4428	free_excl_cntrs(c);	4425	free_excl_cntrs(c);

arch/x86/events/intel/cstate.c+4−0

 	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_MOBILE,  snb_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_DESKTOP, snb_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_X, snb_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE,  snb_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_DENVERTON, glm_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GEMINI_LAKE, glm_cstates),
 	{ },
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);

arch/x86/events/intel/rapl.c+3−0

@@ -775,6 +775,9 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { · 774 unmodified lines
775	X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),	775	X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),
776		776
777	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),	777	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
		778	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),
		779
		780	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GEMINI_LAKE, hsw_rapl_init),
778	{},	781	{},
779	};	782	};
780		783

arch/x86/events/intel/uncore_snbep.c+2−2

@@ -3462,7 +3462,7 @@ static struct intel_uncore_ops skx_uncore_iio_ops = { · 3461 unmodified lines
3462	static struct intel_uncore_type skx_uncore_iio = {	3462	static struct intel_uncore_type skx_uncore_iio = {
3463	.name = "iio",	3463	.name = "iio",
3464	.num_counters = 4,	3464	.num_counters = 4,
3465	.num_boxes = 5,	3465	.num_boxes = 6,
3466	.perf_ctr_bits = 48,	3466	.perf_ctr_bits = 48,
3467	.event_ctl = SKX_IIO0_MSR_PMON_CTL0,	3467	.event_ctl = SKX_IIO0_MSR_PMON_CTL0,
3468	.perf_ctr = SKX_IIO0_MSR_PMON_CTR0,	3468	.perf_ctr = SKX_IIO0_MSR_PMON_CTR0,
@@ -3492,7 +3492,7 @@ static const struct attribute_group skx_uncore_format_group = { · 23 unmodified lines
3492	static struct intel_uncore_type skx_uncore_irp = {	3492	static struct intel_uncore_type skx_uncore_irp = {
3493	.name = "irp",	3493	.name = "irp",
3494	.num_counters = 2,	3494	.num_counters = 2,
3495	.num_boxes = 5,	3495	.num_boxes = 6,
3496	.perf_ctr_bits = 48,	3496	.perf_ctr_bits = 48,
3497	.event_ctl = SKX_IRP0_MSR_PMON_CTL0,	3497	.event_ctl = SKX_IRP0_MSR_PMON_CTL0,
3498	.perf_ctr = SKX_IRP0_MSR_PMON_CTR0,	3498	.perf_ctr = SKX_IRP0_MSR_PMON_CTR0,

arch/x86/events/msr.c+8−0

@@ -63,6 +63,14 @@ static bool test_intel(int idx) · 62 unmodified lines
63	case INTEL_FAM6_ATOM_SILVERMONT1:	63	case INTEL_FAM6_ATOM_SILVERMONT1:
64	case INTEL_FAM6_ATOM_SILVERMONT2:	64	case INTEL_FAM6_ATOM_SILVERMONT2:
65	case INTEL_FAM6_ATOM_AIRMONT:	65	case INTEL_FAM6_ATOM_AIRMONT:
		66
		67	case INTEL_FAM6_ATOM_GOLDMONT:
		68	case INTEL_FAM6_ATOM_DENVERTON:
		69
		70	case INTEL_FAM6_ATOM_GEMINI_LAKE:
		71
		72	case INTEL_FAM6_XEON_PHI_KNL:
		73	case INTEL_FAM6_XEON_PHI_KNM:
66	if (idx == PERF_MSR_SMI)	74	if (idx == PERF_MSR_SMI)
67	return true;	75	return true;
68	break;	76	break;

arch/x86/ia32/ia32_signal.c+1−1

@@ -231,7 +231,7 @@ static void __user get_sigframe(struct ksignal ksig, struct pt_regs *regs, · 230 unmodified lines
231	ksig->ka.sa.sa_restorer)	231	ksig->ka.sa.sa_restorer)
232	sp = (unsigned long) ksig->ka.sa.sa_restorer;	232	sp = (unsigned long) ksig->ka.sa.sa_restorer;
233		233
234	if (fpu->fpstate_active) {	234	if (fpu->initialized) {
235	unsigned long fx_aligned, math_size;	235	unsigned long fx_aligned, math_size;
236		236
237	sp = fpu__alloc_mathframe(sp, 1, &fx_aligned, &math_size);	237	sp = fpu__alloc_mathframe(sp, 1, &fx_aligned, &math_size);

arch/x86/include/asm/alternative.h+1−2

 #define alternative_call_2(oldfunc, newfunc1, feature1, newfunc2, feature2,   \
 			   output, input...)				      \
 {									      \
-	register void *__sp asm(_ASM_SP);				      \
 	asm volatile (ALTERNATIVE_2("call %P[old]", "call %P[new1]", feature1,\
 		"call %P[new2]", feature2)				      \
-		: output, "+r" (__sp)					      \
+		: output, ASM_CALL_CONSTRAINT				      \
 		: [old] "i" (oldfunc), [new1] "i" (newfunc1),		      \
 		  [new2] "i" (newfunc2), ## input);			      \
 }

arch/x86/include/asm/asm.h+14−1

 # define __ASM_FORM_COMMA(x) " " #x ","
 #endif
-#ifdef CONFIG_X86_32
+#ifndef __x86_64__
+/* 32 bit */
 # define __ASM_SEL(a,b) __ASM_FORM(a)
 # define __ASM_SEL_RAW(a,b) __ASM_FORM_RAW(a)
 #else
+/* 64 bit */
 # define __ASM_SEL(a,b) __ASM_FORM(b)
 # define __ASM_SEL_RAW(a,b) __ASM_FORM_RAW(b)
 #endif
 /* For C file, we already have NOKPROBE_SYMBOL macro */
 #endif
+#ifndef __ASSEMBLY__
+/*
+ * This output constraint should be used for any inline asm which has a "call"
+ * instruction.  Otherwise the asm may be inserted before the frame pointer
+ * gets set up by the containing function.  If you forget to do this, objtool
+ * may print a "call without frame pointer save/setup" warning.
+ */
+register unsigned long current_stack_pointer asm(_ASM_SP);
+#define ASM_CALL_CONSTRAINT "+r" (current_stack_pointer)
+#endif
 #endif /* _ASM_X86_ASM_H */

arch/x86/include/asm/fpu/internal.h+22−68

 /*
  * High level FPU state handling functions:
  */
-extern void fpu__activate_curr(struct fpu *fpu);
+extern void fpu__initialize(struct fpu *fpu);
-extern void fpu__activate_fpstate_read(struct fpu *fpu);
+extern void fpu__prepare_read(struct fpu *fpu);
-extern void fpu__activate_fpstate_write(struct fpu *fpu);
+extern void fpu__prepare_write(struct fpu *fpu);
-extern void fpu__current_fpstate_write_begin(void);
-extern void fpu__current_fpstate_write_end(void);
 extern void fpu__save(struct fpu *fpu);
 extern void fpu__restore(struct fpu *fpu);
 extern int  fpu__restore_sig(void __user *buf, int ia32_frame);
 	err;								\
 })
-#define check_insn(insn, output, input...)				\
+#define kernel_insn(insn, output, input...)				\
-({									\
-	int err;							\
 	asm volatile("1:" #insn "\n\t"					\
 		     "2:\n"						\
-		     ".section .fixup,\"ax\"\n"				\
+		     _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_fprestore)	\
-		     "3:  movl $-1,%[err]\n"				\
+		     : output : input)
-		     "    jmp  2b\n"					\
-		     ".previous\n"					\
-		     _ASM_EXTABLE(1b, 3b)				\
-		     : [err] "=r" (err), output				\
-		     : "0"(0), input);					\
-	err;								\
-})
 static inline int copy_fregs_to_user(struct fregs_state __user *fx)
 {
 static inline void copy_kernel_to_fxregs(struct fxregs_state *fx)
 {
-	int err;
 	if (IS_ENABLED(CONFIG_X86_32)) {
-		err = check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
+		kernel_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
 	} else {
 		if (IS_ENABLED(CONFIG_AS_FXSAVEQ)) {
-			err = check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
+			kernel_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
 		} else {
 			/* See comment in copy_fxregs_to_kernel() below. */
-			err = check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), "m" (*fx));
+			kernel_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), "m" (*fx));
 		}
 	}
-	/* Copying from a kernel buffer to FPU registers should never fail: */
-	WARN_ON_FPU(err);
 }
 static inline int copy_user_to_fxregs(struct fxregs_state __user *fx)
 static inline void copy_kernel_to_fregs(struct fregs_state *fx)
 {
-	int err = check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
+	kernel_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
-	WARN_ON_FPU(err);
 }
 static inline int copy_user_to_fregs(struct fregs_state __user *fx)
  * Use XRSTORS to restore context if it is enabled. XRSTORS supports compact
  * XSAVE area format.
  */
-#define XSTATE_XRESTORE(st, lmask, hmask, err)				\
+#define XSTATE_XRESTORE(st, lmask, hmask)				\
 	asm volatile(ALTERNATIVE(XRSTOR,				\
 				 XRSTORS, X86_FEATURE_XSAVES)		\
 		     "\n"						\
-		     "xor %[err], %[err]\n"				\
 		     "3:\n"						\
-		     ".pushsection .fixup,\"ax\"\n"			\
+		     _ASM_EXTABLE_HANDLE(661b, 3b, ex_handler_fprestore)\
-		     "4: movl $-2, %[err]\n"				\
+		     :							\
-		     "jmp 3b\n"						\
-		     ".popsection\n"					\
-		     _ASM_EXTABLE(661b, 4b)				\
-		     : [err] "=r" (err)					\
 		     : "D" (st), "m" (*st), "a" (lmask), "d" (hmask)	\
 		     : "memory")
 	else
 		XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
-	/* We should never fault when copying from a kernel buffer: */
+	/*
+	 * We should never fault when copying from a kernel buffer, and the FPU
+	 * state we set at boot time should be valid.
+	 */
 	WARN_ON_FPU(err);
 }
 	u32 hmask = mask >> 32;
 	int err;
-	WARN_ON(!alternatives_patched);
+	WARN_ON_FPU(!alternatives_patched);
 	XSTATE_XSAVE(xstate, lmask, hmask, err);
 {
 	u32 lmask = mask;
 	u32 hmask = mask >> 32;
-	int err;
-	XSTATE_XRESTORE(xstate, lmask, hmask, err);
-	/* We should never fault when copying from a kernel buffer: */
+	XSTATE_XRESTORE(xstate, lmask, hmask);
-	WARN_ON_FPU(err);
 }
 /*
  */
 static inline void fpregs_deactivate(struct fpu *fpu)
 {
-	WARN_ON_FPU(!fpu->fpregs_active);
-	fpu->fpregs_active = 0;
 	this_cpu_write(fpu_fpregs_owner_ctx, NULL);
 	trace_x86_fpu_regs_deactivated(fpu);
 }
 static inline void fpregs_activate(struct fpu *fpu)
 {
-	WARN_ON_FPU(fpu->fpregs_active);
-	fpu->fpregs_active = 1;
 	this_cpu_write(fpu_fpregs_owner_ctx, fpu);
 	trace_x86_fpu_regs_activated(fpu);
 }
-/*
- * The question "does this thread have fpu access?"
- * is slightly racy, since preemption could come in
- * and revoke it immediately after the test.
- *
- * However, even in that very unlikely scenario,
- * we can just assume we have FPU access - typically
- * to save the FP state - we'll just take a #NM
- * fault and get the FPU access back.
- */
-static inline int fpregs_active(void)
-{
-	return current->thread.fpu.fpregs_active;
-}
 /*
  * FPU state switching for scheduling.
  *
 static inline void
 switch_fpu_prepare(struct fpu *old_fpu, int cpu)
 {
-	if (old_fpu->fpregs_active) {
+	if (old_fpu->initialized) {
 		if (!copy_fpregs_to_fpstate(old_fpu))
 			old_fpu->last_cpu = -1;
 		else
 			old_fpu->last_cpu = cpu;
 		/* But leave fpu_fpregs_owner_ctx! */
-		old_fpu->fpregs_active = 0;
 		trace_x86_fpu_regs_deactivated(old_fpu);
 	} else
 		old_fpu->last_cpu = -1;
 static inline void switch_fpu_finish(struct fpu *new_fpu, int cpu)
 {
 	bool preload = static_cpu_has(X86_FEATURE_FPU) &&
-		       new_fpu->fpstate_active;
+		       new_fpu->initialized;
 	if (preload) {
 		if (!fpregs_state_valid(new_fpu, cpu))
 	struct fpu *fpu = &current->thread.fpu;
 	preempt_disable();
-	if (!fpregs_active())
+	fpregs_activate(fpu);
-		fpregs_activate(fpu);
 	preempt_enable();
 }

arch/x86/include/asm/fpu/types.h+6−26

@@ -68,6 +68,9 @@ struct fxregs_state { · 67 unmodified lines
68	/* Default value for fxregs_state.mxcsr: */	68	/* Default value for fxregs_state.mxcsr: */
69	#define MXCSR_DEFAULT 0x1f80	69	#define MXCSR_DEFAULT 0x1f80
70		70
		71	/* Copy both mxcsr & mxcsr_flags with a single u64 memcpy: */
		72	#define MXCSR_AND_FLAGS_SIZE sizeof(u64)
		73
71	/*	74	/*
72	* Software based FPU emulation state. This is arbitrary really,	75	* Software based FPU emulation state. This is arbitrary really,
73	* it matches the x87 format to make it easier to understand:	76	* it matches the x87 format to make it easier to understand:
@@ -290,36 +293,13 @@ struct fpu { · 216 unmodified lines
290	unsigned int last_cpu;	293	unsigned int last_cpu;
291		294
292	/*	295	/*
293	* @fpstate_active:	296	* @initialized:
294	*	297	*
295	* This flag indicates whether this context is active: if the task	298	* This flag indicates whether this context is initialized: if the task
296	* is not running then we can restore from this context, if the task	299	* is not running then we can restore from this context, if the task
297	* is running then we should save into this context.	300	* is running then we should save into this context.
298	*/	301	*/
299	unsigned char fpstate_active;	302	unsigned char initialized;
300
301	/*
302	* @fpregs_active:
303	*
304	* This flag determines whether a given context is actively
305	* loaded into the FPU's registers and that those registers
306	* represent the task's current FPU state.
307	*
308	* Note the interaction with fpstate_active:
309	*
310	* # task does not use the FPU:
311	* fpstate_active == 0
312	*
313	* # task uses the FPU and regs are active:
314	* fpstate_active == 1 && fpregs_active == 1
315	*
316	* # the regs are inactive but still match fpstate:
317	* fpstate_active == 1 && fpregs_active == 0 && fpregs_owner == fpu
318	*
319	* The third state is what we use for the lazy restore optimization
320	* on lazy-switching CPUs.
321	*/
322	unsigned char fpregs_active;
323		303
324	/*	304	/*
325	* @state:	305	* @state:

arch/x86/include/asm/fpu/xstate.h+8−4

 void *get_xsave_addr(struct xregs_state *xsave, int xstate);
 const void *get_xsave_field_ptr(int xstate_field);
 int using_compacted_format(void);
-int copyout_from_xsaves(unsigned int pos, unsigned int count, void *kbuf,
+int copy_xstate_to_kernel(void *kbuf, struct xregs_state *xsave, unsigned int offset, unsigned int size);
-			void __user *ubuf, struct xregs_state *xsave);
+int copy_xstate_to_user(void __user *ubuf, struct xregs_state *xsave, unsigned int offset, unsigned int size);
-int copyin_to_xsaves(const void *kbuf, const void __user *ubuf,
+int copy_kernel_to_xstate(struct xregs_state *xsave, const void *kbuf);
-		     struct xregs_state *xsave);
+int copy_user_to_xstate(struct xregs_state *xsave, const void __user *ubuf);
+/* Validate an xstate header supplied by userspace (ptrace or sigreturn) */
+extern int validate_xstate_header(const struct xstate_header *hdr);
 #endif

arch/x86/include/asm/kvm_para.h+2−2

@@ -88,7 +88,7 @@ static inline long kvm_hypercall4(unsigned int nr, unsigned long p1, · 87 unmodified lines
88	bool kvm_para_available(void);	88	bool kvm_para_available(void);
89	unsigned int kvm_arch_para_features(void);	89	unsigned int kvm_arch_para_features(void);
90	void __init kvm_guest_init(void);	90	void __init kvm_guest_init(void);
91	void kvm_async_pf_task_wait(u32 token);	91	void kvm_async_pf_task_wait(u32 token, int interrupt_kernel);
92	void kvm_async_pf_task_wake(u32 token);	92	void kvm_async_pf_task_wake(u32 token);
93	u32 kvm_read_and_reset_pf_reason(void);	93	u32 kvm_read_and_reset_pf_reason(void);
94	extern void kvm_disable_steal_time(void);	94	extern void kvm_disable_steal_time(void);
@@ -103,7 +103,7 @@ static inline void kvm_spinlock_init(void) · 8 unmodified lines
103		103
104	#else /* CONFIG_KVM_GUEST */	104	#else /* CONFIG_KVM_GUEST */
105	#define kvm_guest_init() do {} while (0)	105	#define kvm_guest_init() do {} while (0)
106	#define kvm_async_pf_task_wait(T) do {} while(0)	106	#define kvm_async_pf_task_wait(T, I) do {} while(0)
107	#define kvm_async_pf_task_wake(T) do {} while(0)	107	#define kvm_async_pf_task_wake(T) do {} while(0)
108		108
109	static inline bool kvm_para_available(void)	109	static inline bool kvm_para_available(void)

arch/x86/include/asm/mmu_context.h+28−4

@@ -286,6 +286,32 @@ static inline bool arch_vma_access_permitted(struct vm_area_struct *vma, · 285 unmodified lines
286	return __pkru_allows_pkey(vma_pkey(vma), write);	286	return __pkru_allows_pkey(vma_pkey(vma), write);
287	}	287	}
288		288
		289	/*
		290	* If PCID is on, ASID-aware code paths put the ASID+1 into the PCID
		291	* bits. This serves two purposes. It prevents a nasty situation in
		292	* which PCID-unaware code saves CR3, loads some other value (with PCID
		293	* == 0), and then restores CR3, thus corrupting the TLB for ASID 0 if
		294	* the saved ASID was nonzero. It also means that any bugs involving
		295	* loading a PCID-enabled CR3 with CR4.PCIDE off will trigger
		296	* deterministically.
		297	*/
		298
		299	static inline unsigned long build_cr3(struct mm_struct *mm, u16 asid)
		300	{
		301	if (static_cpu_has(X86_FEATURE_PCID)) {
		302	VM_WARN_ON_ONCE(asid > 4094);
		303	return __sme_pa(mm->pgd) \| (asid + 1);
		304	} else {
		305	VM_WARN_ON_ONCE(asid != 0);
		306	return __sme_pa(mm->pgd);
		307	}
		308	}
		309
		310	static inline unsigned long build_cr3_noflush(struct mm_struct *mm, u16 asid)
		311	{
		312	VM_WARN_ON_ONCE(asid > 4094);
		313	return __sme_pa(mm->pgd) \| (asid + 1) \| CR3_NOFLUSH;
		314	}
289		315
290	/*	316	/*
291	* This can be used from process context to figure out what the value of	317	* This can be used from process context to figure out what the value of
@@ -296,10 +322,8 @@ static inline bool arch_vma_access_permitted(struct vm_area_struct *vma, · 4 unmodified lines
296	*/	322	*/
297	static inline unsigned long __get_current_cr3_fast(void)	323	static inline unsigned long __get_current_cr3_fast(void)
298	{	324	{
299	unsigned long cr3 = __pa(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd);	325	unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm),
300		326	this_cpu_read(cpu_tlbstate.loaded_mm_asid));
301	if (static_cpu_has(X86_FEATURE_PCID))
302	cr3 \|= this_cpu_read(cpu_tlbstate.loaded_mm_asid);
303		327
304	/* For now, be very restrictive about when this can be called. */	328	/* For now, be very restrictive about when this can be called. */
305	VM_WARN_ON(in_nmi() \|\| preemptible());	329	VM_WARN_ON(in_nmi() \|\| preemptible());

arch/x86/include/asm/mshyperv.h+4−6

 	u64 input_address = input ? virt_to_phys(input) : 0;
 	u64 output_address = output ? virt_to_phys(output) : 0;
 	u64 hv_status;
-	register void *__sp asm(_ASM_SP);
 #ifdef CONFIG_X86_64
 	if (!hv_hypercall_pg)
 	__asm__ __volatile__("mov %4, %%r8\n"
 			     "call *%5"
-			     : "=a" (hv_status), "+r" (__sp),
+			     : "=a" (hv_status), ASM_CALL_CONSTRAINT,
 			       "+c" (control), "+d" (input_address)
 			     :  "r" (output_address), "m" (hv_hypercall_pg)
 			     : "cc", "memory", "r8", "r9", "r10", "r11");
 	__asm__ __volatile__("call *%7"
 			     : "=A" (hv_status),
-			       "+c" (input_address_lo), "+r" (__sp)
+			       "+c" (input_address_lo), ASM_CALL_CONSTRAINT
 			     : "A" (control),
 			       "b" (input_address_hi),
 			       "D"(output_address_hi), "S"(output_address_lo),
 static inline u64 hv_do_fast_hypercall8(u16 code, u64 input1)
 {
 	u64 hv_status, control = (u64)code | HV_HYPERCALL_FAST_BIT;
-	register void *__sp asm(_ASM_SP);
 #ifdef CONFIG_X86_64
 	{
 		__asm__ __volatile__("call *%4"
-				     : "=a" (hv_status), "+r" (__sp),
+				     : "=a" (hv_status), ASM_CALL_CONSTRAINT,
 				       "+c" (control), "+d" (input1)
 				     : "m" (hv_hypercall_pg)
 				     : "cc", "r8", "r9", "r10", "r11");
 		__asm__ __volatile__ ("call *%5"
 				      : "=A"(hv_status),
 					"+c"(input1_lo),
-					"+r"(__sp)
+					ASM_CALL_CONSTRAINT
 				      :	"A" (control),
 					"b" (input1_hi),
 					"m" (hv_hypercall_pg)

arch/x86/include/asm/paravirt_types.h+7−7

@@ -459,8 +459,8 @@ int paravirt_disable_iospace(void); · 458 unmodified lines
459	*/	459	*/
460	#ifdef CONFIG_X86_32	460	#ifdef CONFIG_X86_32
461	#define PVOP_VCALL_ARGS \	461	#define PVOP_VCALL_ARGS \
462	unsigned long __eax = __eax, __edx = __edx, __ecx = __ecx; \	462	unsigned long __eax = __eax, __edx = __edx, __ecx = __ecx;
463	register void *__sp asm("esp")	463
464	#define PVOP_CALL_ARGS PVOP_VCALL_ARGS	464	#define PVOP_CALL_ARGS PVOP_VCALL_ARGS
465		465
466	#define PVOP_CALL_ARG1(x) "a" ((unsigned long)(x))	466	#define PVOP_CALL_ARG1(x) "a" ((unsigned long)(x))
@@ -480,8 +480,8 @@ int paravirt_disable_iospace(void); · 13 unmodified lines
480	/* [re]ax isn't an arg, but the return val */	480	/* [re]ax isn't an arg, but the return val */
481	#define PVOP_VCALL_ARGS \	481	#define PVOP_VCALL_ARGS \
482	unsigned long __edi = __edi, __esi = __esi, \	482	unsigned long __edi = __edi, __esi = __esi, \
483	__edx = __edx, __ecx = __ecx, __eax = __eax; \	483	__edx = __edx, __ecx = __ecx, __eax = __eax;
484	register void *__sp asm("rsp")	484
485	#define PVOP_CALL_ARGS PVOP_VCALL_ARGS	485	#define PVOP_CALL_ARGS PVOP_VCALL_ARGS
486		486
487	#define PVOP_CALL_ARG1(x) "D" ((unsigned long)(x))	487	#define PVOP_CALL_ARG1(x) "D" ((unsigned long)(x))
@@ -532,7 +532,7 @@ int paravirt_disable_iospace(void); · 44 unmodified lines
532	asm volatile(pre \	532	asm volatile(pre \
533	paravirt_alt(PARAVIRT_CALL) \	533	paravirt_alt(PARAVIRT_CALL) \
534	post \	534	post \
535	: call_clbr, "+r" (__sp) \	535	: call_clbr, ASM_CALL_CONSTRAINT \
536	: paravirt_type(op), \	536	: paravirt_type(op), \
537	paravirt_clobber(clbr), \	537	paravirt_clobber(clbr), \
538	##__VA_ARGS__ \	538	##__VA_ARGS__ \
@@ -542,7 +542,7 @@ int paravirt_disable_iospace(void); · 3 unmodified lines
542	asm volatile(pre \	542	asm volatile(pre \
543	paravirt_alt(PARAVIRT_CALL) \	543	paravirt_alt(PARAVIRT_CALL) \
544	post \	544	post \
545	: call_clbr, "+r" (__sp) \	545	: call_clbr, ASM_CALL_CONSTRAINT \
546	: paravirt_type(op), \	546	: paravirt_type(op), \
547	paravirt_clobber(clbr), \	547	paravirt_clobber(clbr), \
548	##__VA_ARGS__ \	548	##__VA_ARGS__ \
@@ -569,7 +569,7 @@ int paravirt_disable_iospace(void); · 20 unmodified lines
569	asm volatile(pre \	569	asm volatile(pre \
570	paravirt_alt(PARAVIRT_CALL) \	570	paravirt_alt(PARAVIRT_CALL) \
571	post \	571	post \
572	: call_clbr, "+r" (__sp) \	572	: call_clbr, ASM_CALL_CONSTRAINT \
573	: paravirt_type(op), \	573	: paravirt_type(op), \
574	paravirt_clobber(clbr), \	574	paravirt_clobber(clbr), \
575	##__VA_ARGS__ \	575	##__VA_ARGS__ \

arch/x86/include/asm/preempt.h+5−10

@@ -100,19 +100,14 @@ static __always_inline bool should_resched(int preempt_offset) · 99 unmodified lines
100		100
101	#ifdef CONFIG_PREEMPT	101	#ifdef CONFIG_PREEMPT
102	extern asmlinkage void ___preempt_schedule(void);	102	extern asmlinkage void ___preempt_schedule(void);
103	# define __preempt_schedule() \	103	# define __preempt_schedule() \
104	({ \	104	asm volatile ("call ___preempt_schedule" : ASM_CALL_CONSTRAINT)
105	register void *__sp asm(_ASM_SP); \
106	asm volatile ("call ___preempt_schedule" : "+r"(__sp)); \
107	})
108		105
109	extern asmlinkage void preempt_schedule(void);	106	extern asmlinkage void preempt_schedule(void);
110	extern asmlinkage void ___preempt_schedule_notrace(void);	107	extern asmlinkage void ___preempt_schedule_notrace(void);
111	# define __preempt_schedule_notrace() \	108	# define __preempt_schedule_notrace() \
112	({ \	109	asm volatile ("call ___preempt_schedule_notrace" : ASM_CALL_CONSTRAINT)
113	register void *__sp asm(_ASM_SP); \	110
114	asm volatile ("call ___preempt_schedule_notrace" : "+r"(__sp)); \
115	})
116	extern asmlinkage void preempt_schedule_notrace(void);	111	extern asmlinkage void preempt_schedule_notrace(void);
117	#endif	112	#endif
118		113

arch/x86/include/asm/processor.h+2−4

 	 * Like all of Linux's memory ordering operations, this is a
 	 * compiler barrier as well.
 	 */
-	register void *__sp asm(_ASM_SP);
 #ifdef CONFIG_X86_32
 	asm volatile (
 		"pushfl\n\t"
 		"pushl $1f\n\t"
 		"iret\n\t"
 		"1:"
-		: "+r" (__sp) : : "memory");
+		: ASM_CALL_CONSTRAINT : : "memory");
 #else
 	unsigned int tmp;
 		"iretq\n\t"
 		UNWIND_HINT_RESTORE
 		"1:"
-		: "=&r" (tmp), "+r" (__sp) : : "cc", "memory");
+		: "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
 #endif
 }

arch/x86/include/asm/rwsem.h+2−2

 ({							\
 	long tmp;					\
 	struct rw_semaphore* ret;			\
-	register void *__sp asm(_ASM_SP);		\
 							\
 	asm volatile("# beginning down_write\n\t"	\
 		     LOCK_PREFIX "  xadd      %1,(%4)\n\t"	\
 		     "  call " slow_path "\n"		\
 		     "1:\n"				\
 		     "# ending down_write"		\
-		     : "+m" (sem->count), "=d" (tmp), "=a" (ret), "+r" (__sp) \
+		     : "+m" (sem->count), "=d" (tmp),	\
+		       "=a" (ret), ASM_CALL_CONSTRAINT	\
 		     : "a" (sem), "1" (RWSEM_ACTIVE_WRITE_BIAS) \
 		     : "memory", "cc");			\
 	ret;						\

arch/x86/include/asm/thread_info.h+0−11

@@ -158,17 +158,6 @@ struct thread_info { · 157 unmodified lines
158	*/	158	*/
159	#ifndef __ASSEMBLY__	159	#ifndef __ASSEMBLY__
160		160
161	static inline unsigned long current_stack_pointer(void)
162	{
163	unsigned long sp;
164	#ifdef CONFIG_X86_64
165	asm("mov %%rsp,%0" : "=g" (sp));
166	#else
167	asm("mov %%esp,%0" : "=g" (sp));
168	#endif
169	return sp;
170	}
171
172	/*	161	/*
173	* Walks up the stack frames to make sure that the specified object is	162	* Walks up the stack frames to make sure that the specified object is
174	* entirely contained by a single stack frame.	163	* entirely contained by a single stack frame.

arch/x86/include/asm/trace/fpu.h+4−7

 	TP_STRUCT__entry(
 		__field(struct fpu *, fpu)
-		__field(bool, fpregs_active)
+		__field(bool, initialized)
-		__field(bool, fpstate_active)
 		__field(u64, xfeatures)
 		__field(u64, xcomp_bv)
 		),
 	TP_fast_assign(
 		__entry->fpu		= fpu;
-		__entry->fpregs_active	= fpu->fpregs_active;
+		__entry->initialized	= fpu->initialized;
-		__entry->fpstate_active	= fpu->fpstate_active;
 		if (boot_cpu_has(X86_FEATURE_OSXSAVE)) {
 			__entry->xfeatures = fpu->state.xsave.header.xfeatures;
 			__entry->xcomp_bv  = fpu->state.xsave.header.xcomp_bv;
 		}
 	),
-	TP_printk("x86/fpu: %p fpregs_active: %d fpstate_active: %d xfeatures: %llx xcomp_bv: %llx",
+	TP_printk("x86/fpu: %p initialized: %d xfeatures: %llx xcomp_bv: %llx",
 			__entry->fpu,
-			__entry->fpregs_active,
+			__entry->initialized,
-			__entry->fpstate_active,
 			__entry->xfeatures,
 			__entry->xcomp_bv
 	)

arch/x86/include/asm/uaccess.h+3−3

 ({									\
 	int __ret_gu;							\
 	register __inttype(*(ptr)) __val_gu asm("%"_ASM_DX);		\
-	register void *__sp asm(_ASM_SP);				\
 	__chk_user_ptr(ptr);						\
 	might_fault();							\
 	asm volatile("call __get_user_%P4"				\
-		     : "=a" (__ret_gu), "=r" (__val_gu), "+r" (__sp)	\
+		     : "=a" (__ret_gu), "=r" (__val_gu),		\
+			ASM_CALL_CONSTRAINT				\
 		     : "0" (ptr), "i" (sizeof(*(ptr))));		\
 	(x) = (__force __typeof__(*(ptr))) __val_gu;			\
 	__builtin_expect(__ret_gu, 0);					\
 		     _ASM_EXTABLE(1b, 4b)				\
 		     _ASM_EXTABLE(2b, 4b)				\
 		     : "=r" (retval), "=&A"(x)				\
-		     : "m" (__m(__ptr)), "m" __m(((u32 *)(__ptr)) + 1),	\
+		     : "m" (__m(__ptr)), "m" __m(((u32 __user *)(__ptr)) + 1),	\
 		       "i" (errret), "0" (retval));			\
 })

arch/x86/include/asm/xen/hypercall.h+4−5

 	register unsigned long __arg2 asm(__HYPERCALL_ARG2REG) = __arg2; \
 	register unsigned long __arg3 asm(__HYPERCALL_ARG3REG) = __arg3; \
 	register unsigned long __arg4 asm(__HYPERCALL_ARG4REG) = __arg4; \
-	register unsigned long __arg5 asm(__HYPERCALL_ARG5REG) = __arg5; \
+	register unsigned long __arg5 asm(__HYPERCALL_ARG5REG) = __arg5;
-	register void *__sp asm(_ASM_SP);
-#define __HYPERCALL_0PARAM	"=r" (__res), "+r" (__sp)
+#define __HYPERCALL_0PARAM	"=r" (__res), ASM_CALL_CONSTRAINT
 #define __HYPERCALL_1PARAM	__HYPERCALL_0PARAM, "+r" (__arg1)
 #define __HYPERCALL_2PARAM	__HYPERCALL_1PARAM, "+r" (__arg2)
 #define __HYPERCALL_3PARAM	__HYPERCALL_2PARAM, "+r" (__arg3)
 MULTI_update_descriptor(struct multicall_entry *mcl, u64 maddr,
 			struct desc_struct desc)
 {
-	u32 *p = (u32 *) &desc;
 	mcl->op = __HYPERVISOR_update_descriptor;
 	if (sizeof(maddr) == sizeof(long)) {
 		mcl->args[0] = maddr;
 		mcl->args[1] = *(unsigned long *)&desc;
 	} else {
+		u32 *p = (u32 *)&desc;
 		mcl->args[0] = maddr;
 		mcl->args[1] = maddr >> 32;
 		mcl->args[2] = *p++;

arch/x86/kernel/cpu/amd.c+11−0

 	}
 }
+static void init_amd_zn(struct cpuinfo_x86 *c)
+{
+	/*
+	 * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
+	 * all up to and including B1.
+	 */
+	if (c->x86_model <= 1 && c->x86_mask <= 1)
+		set_cpu_cap(c, X86_FEATURE_CPB);
+}
 static void init_amd(struct cpuinfo_x86 *c)
 {
 	early_init_amd(c);
 	case 0x10: init_amd_gh(c); break;
 	case 0x12: init_amd_ln(c); break;
 	case 0x15: init_amd_bd(c); break;
+	case 0x17: init_amd_zn(c); break;
 	}
 	/* Enable workaround for FXSAVE leak */

arch/x86/kernel/cpu/bugs.c+0−8

@@ -21,14 +21,6 @@ · 20 unmodified lines
21		21
22	void __init check_bugs(void)	22	void __init check_bugs(void)
23	{	23	{
24	#ifdef CONFIG_X86_32
25	/*
26	* Regardless of whether PCID is enumerated, the SDM says
27	* that it can't be enabled in 32-bit mode.
28	*/
29	setup_clear_cpu_cap(X86_FEATURE_PCID);
30	#endif
31
32	identify_boot_cpu();	24	identify_boot_cpu();
33		25
34	if (!IS_ENABLED(CONFIG_SMP)) {	26	if (!IS_ENABLED(CONFIG_SMP)) {

arch/x86/kernel/cpu/common.c+8−0

@@ -904,6 +904,14 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) · 903 unmodified lines
904		904
905	setup_force_cpu_cap(X86_FEATURE_ALWAYS);	905	setup_force_cpu_cap(X86_FEATURE_ALWAYS);
906	fpu__init_system(c);	906	fpu__init_system(c);
		907
		908	#ifdef CONFIG_X86_32
		909	/*
		910	* Regardless of whether PCID is enumerated, the SDM says
		911	* that it can't be enabled in 32-bit mode.
		912	*/
		913	setup_clear_cpu_cap(X86_FEATURE_PCID);
		914	#endif
907	}	915	}
908		916
909	void __init early_cpu_init(void)	917	void __init early_cpu_init(void)

arch/x86/kernel/fpu/core.c+43−112

 	kernel_fpu_disable();
-	if (fpu->fpregs_active) {
+	if (fpu->initialized) {
 		/*
 		 * Ignore return value -- we don't care if reg state
 		 * is clobbered.
 {
 	struct fpu *fpu = &current->thread.fpu;
-	if (fpu->fpregs_active)
+	if (fpu->initialized)
 		copy_kernel_to_fpregs(&fpu->state);
 	kernel_fpu_enable();
 	preempt_disable();
 	trace_x86_fpu_before_save(fpu);
-	if (fpu->fpregs_active) {
+	if (fpu->initialized) {
 		if (!copy_fpregs_to_fpstate(fpu)) {
 			copy_kernel_to_fpregs(&fpu->state);
 		}
 int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu)
 {
-	dst_fpu->fpregs_active = 0;
 	dst_fpu->last_cpu = -1;
-	if (!src_fpu->fpstate_active || !static_cpu_has(X86_FEATURE_FPU))
+	if (!src_fpu->initialized || !static_cpu_has(X86_FEATURE_FPU))
 		return 0;
 	WARN_ON_FPU(src_fpu != &current->thread.fpu);
 	/*
 	 * Save current FPU registers directly into the child
 	 * FPU context, without any memory-to-memory copying.
-	 * In lazy mode, if the FPU context isn't loaded into
-	 * fpregs, CR0.TS will be set and do_device_not_available
-	 * will load the FPU context.
 	 *
-	 * We have to do all this with preemption disabled,
+	 * ( The function 'fails' in the FNSAVE case, which destroys
-	 * mostly because of the FNSAVE case, because in that
+	 *   register contents so we have to copy them back. )
-	 * case we must not allow preemption in the window
-	 * between the FNSAVE and us marking the context lazy.
-	 *
-	 * It shouldn't be an issue as even FNSAVE is plenty
-	 * fast in terms of critical section length.
 	 */
-	preempt_disable();
 	if (!copy_fpregs_to_fpstate(dst_fpu)) {
-		memcpy(&src_fpu->state, &dst_fpu->state,
+		memcpy(&src_fpu->state, &dst_fpu->state, fpu_kernel_xstate_size);
-		       fpu_kernel_xstate_size);
 		copy_kernel_to_fpregs(&src_fpu->state);
 	}
-	preempt_enable();
 	trace_x86_fpu_copy_src(src_fpu);
 	trace_x86_fpu_copy_dst(dst_fpu);
  * Activate the current task's in-memory FPU context,
  * if it has not been used before:
  */
-void fpu__activate_curr(struct fpu *fpu)
+void fpu__initialize(struct fpu *fpu)
 {
 	WARN_ON_FPU(fpu != &current->thread.fpu);
-	if (!fpu->fpstate_active) {
+	if (!fpu->initialized) {
 		fpstate_init(&fpu->state);
 		trace_x86_fpu_init_state(fpu);
 		trace_x86_fpu_activate_state(fpu);
 		/* Safe to do for the current task: */
-		fpu->fpstate_active = 1;
+		fpu->initialized = 1;
 	}
 }
-EXPORT_SYMBOL_GPL(fpu__activate_curr);
+EXPORT_SYMBOL_GPL(fpu__initialize);
 /*
  * This function must be called before we read a task's fpstate.
  *
- * If the task has not used the FPU before then initialize its
+ * There's two cases where this gets called:
- * fpstate.
+ *
+ * - for the current task (when coredumping), in which case we have
+ *   to save the latest FPU registers into the fpstate,
+ *
+ * - or it's called for stopped tasks (ptrace), in which case the
+ *   registers were already saved by the context-switch code when
+ *   the task scheduled out - we only have to initialize the registers
+ *   if they've never been initialized.
  *
  * If the task has used the FPU before then save it.
  */
-void fpu__activate_fpstate_read(struct fpu *fpu)
+void fpu__prepare_read(struct fpu *fpu)
 {
-	/*
+	if (fpu == &current->thread.fpu) {
-	 * If fpregs are active (in the current CPU), then
-	 * copy them to the fpstate:
-	 */
-	if (fpu->fpregs_active) {
 		fpu__save(fpu);
 	} else {
-		if (!fpu->fpstate_active) {
+		if (!fpu->initialized) {
 			fpstate_init(&fpu->state);
 			trace_x86_fpu_init_state(fpu);
 			trace_x86_fpu_activate_state(fpu);
 			/* Safe to do for current and for stopped child tasks: */
-			fpu->fpstate_active = 1;
+			fpu->initialized = 1;
 		}
 	}
 }
 /*
  * This function must be called before we write a task's fpstate.
  *
- * If the task has used the FPU before then unlazy it.
+ * If the task has used the FPU before then invalidate any cached FPU registers.
  * If the task has not used the FPU before then initialize its fpstate.
  *
  * After this function call, after registers in the fpstate are
  * modified and the child task has woken up, the child task will
  * restore the modified FPU state from the modified context. If we
- * didn't clear its lazy status here then the lazy in-registers
+ * didn't clear its cached status here then the cached in-registers
  * state pending on its former CPU could be restored, corrupting
  * the modifications.
  */
-void fpu__activate_fpstate_write(struct fpu *fpu)
+void fpu__prepare_write(struct fpu *fpu)
 {
 	/*
 	 * Only stopped child tasks can be used to modify the FPU
 	 */
 	WARN_ON_FPU(fpu == &current->thread.fpu);
-	if (fpu->fpstate_active) {
+	if (fpu->initialized) {
-		/* Invalidate any lazy state: */
+		/* Invalidate any cached state: */
 		__fpu_invalidate_fpregs_state(fpu);
 	} else {
 		fpstate_init(&fpu->state);
 		trace_x86_fpu_activate_state(fpu);
 		/* Safe to do for stopped child tasks: */
-		fpu->fpstate_active = 1;
+		fpu->initialized = 1;
 	}
 }
-/*
- * This function must be called before we write the current
- * task's fpstate.
- *
- * This call gets the current FPU register state and moves
- * it in to the 'fpstate'.  Preemption is disabled so that
- * no writes to the 'fpstate' can occur from context
- * swiches.
- *
- * Must be followed by a fpu__current_fpstate_write_end().
- */
-void fpu__current_fpstate_write_begin(void)
-{
-	struct fpu *fpu = &current->thread.fpu;
-	/*
-	 * Ensure that the context-switching code does not write
-	 * over the fpstate while we are doing our update.
-	 */
-	preempt_disable();
-	/*
-	 * Move the fpregs in to the fpu's 'fpstate'.
-	 */
-	fpu__activate_fpstate_read(fpu);
-	/*
-	 * The caller is about to write to 'fpu'.  Ensure that no
-	 * CPU thinks that its fpregs match the fpstate.  This
-	 * ensures we will not be lazy and skip a XRSTOR in the
-	 * future.
-	 */
-	__fpu_invalidate_fpregs_state(fpu);
-}
-/*
- * This function must be paired with fpu__current_fpstate_write_begin()
- *
- * This will ensure that the modified fpstate gets placed back in
- * the fpregs if necessary.
- *
- * Note: This function may be called whether or not an _actual_
- * write to the fpstate occurred.
- */
-void fpu__current_fpstate_write_end(void)
-{
-	struct fpu *fpu = &current->thread.fpu;
-	/*
-	 * 'fpu' now has an updated copy of the state, but the
-	 * registers may still be out of date.  Update them with
-	 * an XRSTOR if they are active.
-	 */
-	if (fpregs_active())
-		copy_kernel_to_fpregs(&fpu->state);
-	/*
-	 * Our update is done and the fpregs/fpstate are in sync
-	 * if necessary.  Context switches can happen again.
-	 */
-	preempt_enable();
-}
 /*
  * 'fpu__restore()' is called to copy FPU registers from
  * the FPU fpstate to the live hw registers and to activate
  */
 void fpu__restore(struct fpu *fpu)
 {
-	fpu__activate_curr(fpu);
+	fpu__initialize(fpu);
 	/* Avoid __kernel_fpu_begin() right after fpregs_activate() */
 	kernel_fpu_disable();
 {
 	preempt_disable();
-	if (fpu->fpregs_active) {
+	if (fpu == &current->thread.fpu) {
-		/* Ignore delayed exceptions from user space */
+		if (fpu->initialized) {
-		asm volatile("1: fwait\n"
+			/* Ignore delayed exceptions from user space */
-			     "2:\n"
+			asm volatile("1: fwait\n"
-			     _ASM_EXTABLE(1b, 2b));
+				     "2:\n"
-		fpregs_deactivate(fpu);
+				     _ASM_EXTABLE(1b, 2b));
+			fpregs_deactivate(fpu);
+		}
 	}
-	fpu->fpstate_active = 0;
+	fpu->initialized = 0;
 	trace_x86_fpu_dropped(fpu);
 	 * Make sure fpstate is cleared and initialized.
 	 */
 	if (static_cpu_has(X86_FEATURE_FPU)) {
-		fpu__activate_curr(fpu);
+		preempt_disable();
+		fpu__initialize(fpu);
 		user_fpu_begin();
 		copy_init_fpstate_to_fpregs();
+		preempt_enable();
 	}
 }

arch/x86/kernel/fpu/init.c+1−1

@@ -240,7 +240,7 @@ static void __init fpu__init_system_ctx_switch(void) · 239 unmodified lines
240	WARN_ON_FPU(!on_boot_cpu);	240	WARN_ON_FPU(!on_boot_cpu);
241	on_boot_cpu = 0;	241	on_boot_cpu = 0;
242		242
243	WARN_ON_FPU(current->thread.fpu.fpstate_active);	243	WARN_ON_FPU(current->thread.fpu.initialized);
244	}	244	}
245		245
246	/*	246	/*

arch/x86/kernel/fpu/regset.c+26−22

@@ -16,14 +16,14 @@ int regset_fpregs_active(struct task_struct target, const struct user_regset r · 15 unmodified lines
16	{	16	{
17	struct fpu *target_fpu = &target->thread.fpu;	17	struct fpu *target_fpu = &target->thread.fpu;
18		18
19	return target_fpu->fpstate_active ? regset->n : 0;	19	return target_fpu->initialized ? regset->n : 0;
20	}	20	}
21		21
22	int regset_xregset_fpregs_active(struct task_struct target, const struct user_regset regset)	22	int regset_xregset_fpregs_active(struct task_struct target, const struct user_regset regset)
23	{	23	{
24	struct fpu *target_fpu = &target->thread.fpu;	24	struct fpu *target_fpu = &target->thread.fpu;
25		25
26	if (boot_cpu_has(X86_FEATURE_FXSR) && target_fpu->fpstate_active)	26	if (boot_cpu_has(X86_FEATURE_FXSR) && target_fpu->initialized)
27	return regset->n;	27	return regset->n;
28	else	28	else
29	return 0;	29	return 0;
@@ -38,7 +38,7 @@ int xfpregs_get(struct task_struct target, const struct user_regset regset, · 8 unmodified lines
38	if (!boot_cpu_has(X86_FEATURE_FXSR))	38	if (!boot_cpu_has(X86_FEATURE_FXSR))
39	return -ENODEV;	39	return -ENODEV;
40		40
41	fpu__activate_fpstate_read(fpu);	41	fpu__prepare_read(fpu);
42	fpstate_sanitize_xstate(fpu);	42	fpstate_sanitize_xstate(fpu);
43		43
44	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,	44	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
@@ -55,7 +55,7 @@ int xfpregs_set(struct task_struct target, const struct user_regset regset, · 10 unmodified lines
55	if (!boot_cpu_has(X86_FEATURE_FXSR))	55	if (!boot_cpu_has(X86_FEATURE_FXSR))
56	return -ENODEV;	56	return -ENODEV;
57		57
58	fpu__activate_fpstate_write(fpu);	58	fpu__prepare_write(fpu);
59	fpstate_sanitize_xstate(fpu);	59	fpstate_sanitize_xstate(fpu);
60		60
61	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,	61	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
@@ -89,10 +89,13 @@ int xstateregs_get(struct task_struct target, const struct user_regset regset, · 27 unmodified lines
89		89
90	xsave = &fpu->state.xsave;	90	xsave = &fpu->state.xsave;
91		91
92	fpu__activate_fpstate_read(fpu);	92	fpu__prepare_read(fpu);
93		93
94	if (using_compacted_format()) {	94	if (using_compacted_format()) {
95	ret = copyout_from_xsaves(pos, count, kbuf, ubuf, xsave);	95	if (kbuf)
		96	ret = copy_xstate_to_kernel(kbuf, xsave, pos, count);
		97	else
		98	ret = copy_xstate_to_user(ubuf, xsave, pos, count);
96	} else {	99	} else {
97	fpstate_sanitize_xstate(fpu);	100	fpstate_sanitize_xstate(fpu);
98	/*	101	/*
@@ -129,28 +132,29 @@ int xstateregs_set(struct task_struct target, const struct user_regset regset, · 30 unmodified lines
129		132
130	xsave = &fpu->state.xsave;	133	xsave = &fpu->state.xsave;
131		134
132	fpu__activate_fpstate_write(fpu);	135	fpu__prepare_write(fpu);
133		136
134	if (boot_cpu_has(X86_FEATURE_XSAVES))	137	if (using_compacted_format()) {
135	ret = copyin_to_xsaves(kbuf, ubuf, xsave);	138	if (kbuf)
136	else	139	ret = copy_kernel_to_xstate(xsave, kbuf);
		140	else
		141	ret = copy_user_to_xstate(xsave, ubuf);
		142	} else {
137	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);	143	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
138		144	if (!ret)
139	/*	145	ret = validate_xstate_header(&xsave->header);
140	* In case of failure, mark all states as init:	146	}
141	*/
142	if (ret)
143	fpstate_init(&fpu->state);
144		147
145	/*	148	/*
146	* mxcsr reserved bits must be masked to zero for security reasons.	149	* mxcsr reserved bits must be masked to zero for security reasons.
147	*/	150	*/
148	xsave->i387.mxcsr &= mxcsr_feature_mask;	151	xsave->i387.mxcsr &= mxcsr_feature_mask;
149	xsave->header.xfeatures &= xfeatures_mask;	152
150	/*	153	/*
151	* These bits must be zero.	154	* In case of failure, mark all states as init:
152	*/	155	*/
153	memset(&xsave->header.reserved, 0, 48);	156	if (ret)
		157	fpstate_init(&fpu->state);
154		158
155	return ret;	159	return ret;
156	}	160	}
@@ -299,7 +303,7 @@ int fpregs_get(struct task_struct target, const struct user_regset regset, · 142 unmodified lines
299	struct fpu *fpu = &target->thread.fpu;	303	struct fpu *fpu = &target->thread.fpu;
300	struct user_i387_ia32_struct env;	304	struct user_i387_ia32_struct env;
301		305
302	fpu__activate_fpstate_read(fpu);	306	fpu__prepare_read(fpu);
303		307
304	if (!boot_cpu_has(X86_FEATURE_FPU))	308	if (!boot_cpu_has(X86_FEATURE_FPU))
305	return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);	309	return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
@@ -329,7 +333,7 @@ int fpregs_set(struct task_struct target, const struct user_regset regset, · 23 unmodified lines
329	struct user_i387_ia32_struct env;	333	struct user_i387_ia32_struct env;
330	int ret;	334	int ret;
331		335
332	fpu__activate_fpstate_write(fpu);	336	fpu__prepare_write(fpu);
333	fpstate_sanitize_xstate(fpu);	337	fpstate_sanitize_xstate(fpu);
334		338
335	if (!boot_cpu_has(X86_FEATURE_FPU))	339	if (!boot_cpu_has(X86_FEATURE_FPU))
@@ -369,7 +373,7 @@ int dump_fpu(struct pt_regs regs, struct user_i387_struct ufpu) · 33 unmodified lines
369	struct fpu *fpu = &tsk->thread.fpu;	373	struct fpu *fpu = &tsk->thread.fpu;
370	int fpvalid;	374	int fpvalid;
371		375
372	fpvalid = fpu->fpstate_active;	376	fpvalid = fpu->initialized;
373	if (fpvalid)	377	if (fpvalid)
374	fpvalid = !fpregs_get(tsk, NULL,	378	fpvalid = !fpregs_get(tsk, NULL,
375	0, sizeof(struct user_i387_ia32_struct),	379	0, sizeof(struct user_i387_ia32_struct),

arch/x86/kernel/fpu/signal.c+21−16

@@ -155,7 +155,8 @@ static inline int copy_fpregs_to_sigframe(struct xregs_state __user *buf) · 154 unmodified lines
155	*/	155	*/
156	int copy_fpstate_to_sigframe(void __user buf, void __user buf_fx, int size)	156	int copy_fpstate_to_sigframe(void __user buf, void __user buf_fx, int size)
157	{	157	{
158	struct xregs_state *xsave = &current->thread.fpu.state.xsave;	158	struct fpu *fpu = &current->thread.fpu;
		159	struct xregs_state *xsave = &fpu->state.xsave;
159	struct task_struct *tsk = current;	160	struct task_struct *tsk = current;
160	int ia32_fxstate = (buf != buf_fx);	161	int ia32_fxstate = (buf != buf_fx);
161		162
@@ -170,13 +171,13 @@ int copy_fpstate_to_sigframe(void __user buf, void __user buf_fx, int size) · 8 unmodified lines
170	sizeof(struct user_i387_ia32_struct), NULL,	171	sizeof(struct user_i387_ia32_struct), NULL,
171	(struct _fpstate_32 __user *) buf) ? -1 : 1;	172	(struct _fpstate_32 __user *) buf) ? -1 : 1;
172		173
173	if (fpregs_active() \|\| using_compacted_format()) {	174	if (fpu->initialized \|\| using_compacted_format()) {
174	/* Save the live register state to the user directly. */	175	/* Save the live register state to the user directly. */
175	if (copy_fpregs_to_sigframe(buf_fx))	176	if (copy_fpregs_to_sigframe(buf_fx))
176	return -1;	177	return -1;
177	/* Update the thread's fxstate to save the fsave header. */	178	/* Update the thread's fxstate to save the fsave header. */
178	if (ia32_fxstate)	179	if (ia32_fxstate)
179	copy_fxregs_to_kernel(&tsk->thread.fpu);	180	copy_fxregs_to_kernel(fpu);
180	} else {	181	} else {
181	/*	182	/*
182	* It is a bug if kernel uses compacted-format for xsave	183	* It is a bug if kernel uses compacted-format for xsave
@@ -189,7 +190,7 @@ int copy_fpstate_to_sigframe(void __user buf, void __user buf_fx, int size) · 6 unmodified lines
189	return -1;	190	return -1;
190	}	191	}
191		192
192	fpstate_sanitize_xstate(&tsk->thread.fpu);	193	fpstate_sanitize_xstate(fpu);
193	if (__copy_to_user(buf_fx, xsave, fpu_user_xstate_size))	194	if (__copy_to_user(buf_fx, xsave, fpu_user_xstate_size))
194	return -1;	195	return -1;
195	}	196	}
@@ -213,8 +214,11 @@ sanitize_restored_xstate(struct task_struct *tsk, · 17 unmodified lines
213	struct xstate_header *header = &xsave->header;	214	struct xstate_header *header = &xsave->header;
214		215
215	if (use_xsave()) {	216	if (use_xsave()) {
216	/* These bits must be zero. */	217	/*
217	memset(header->reserved, 0, 48);	218	* Note: we don't need to zero the reserved bits in the
		219	* xstate_header here because we either didn't copy them at all,
		220	* or we checked earlier that they aren't set.
		221	*/
218		222
219	/*	223	/*
220	* Init the state that is not present in the memory	224	* Init the state that is not present in the memory
@@ -223,7 +227,7 @@ sanitize_restored_xstate(struct task_struct *tsk, · 2 unmodified lines
223	if (fx_only)	227	if (fx_only)
224	header->xfeatures = XFEATURE_MASK_FPSSE;	228	header->xfeatures = XFEATURE_MASK_FPSSE;
225	else	229	else
226	header->xfeatures &= (xfeatures_mask & xfeatures);	230	header->xfeatures &= xfeatures;
227	}	231	}
228		232
229	if (use_fxsr()) {	233	if (use_fxsr()) {
@@ -279,7 +283,7 @@ static int __fpu__restore_sig(void __user buf, void __user buf_fx, int size) · 49 unmodified lines
279	if (!access_ok(VERIFY_READ, buf, size))	283	if (!access_ok(VERIFY_READ, buf, size))
280	return -EACCES;	284	return -EACCES;
281		285
282	fpu__activate_curr(fpu);	286	fpu__initialize(fpu);
283		287
284	if (!static_cpu_has(X86_FEATURE_FPU))	288	if (!static_cpu_has(X86_FEATURE_FPU))
285	return fpregs_soft_set(current, NULL,	289	return fpregs_soft_set(current, NULL,
@@ -307,28 +311,29 @@ static int __fpu__restore_sig(void __user buf, void __user buf_fx, int size) · 21 unmodified lines
307	/*	311	/*
308	* For 32-bit frames with fxstate, copy the user state to the	312	* For 32-bit frames with fxstate, copy the user state to the
309	* thread's fpu state, reconstruct fxstate from the fsave	313	* thread's fpu state, reconstruct fxstate from the fsave
310	* header. Sanitize the copied state etc.	314	* header. Validate and sanitize the copied state.
311	*/	315	*/
312	struct fpu *fpu = &tsk->thread.fpu;	316	struct fpu *fpu = &tsk->thread.fpu;
313	struct user_i387_ia32_struct env;	317	struct user_i387_ia32_struct env;
314	int err = 0;	318	int err = 0;
315		319
316	/*	320	/*
317	* Drop the current fpu which clears fpu->fpstate_active. This ensures	321	* Drop the current fpu which clears fpu->initialized. This ensures
318	* that any context-switch during the copy of the new state,	322	* that any context-switch during the copy of the new state,
319	* avoids the intermediate state from getting restored/saved.	323	* avoids the intermediate state from getting restored/saved.
320	* Thus avoiding the new restored state from getting corrupted.	324	* Thus avoiding the new restored state from getting corrupted.
321	* We will be ready to restore/save the state only after	325	* We will be ready to restore/save the state only after
322	* fpu->fpstate_active is again set.	326	* fpu->initialized is again set.
323	*/	327	*/
324	fpu__drop(fpu);	328	fpu__drop(fpu);
325		329
326	if (using_compacted_format()) {	330	if (using_compacted_format()) {
327	err = copyin_to_xsaves(NULL, buf_fx,	331	err = copy_user_to_xstate(&fpu->state.xsave, buf_fx);
328	&fpu->state.xsave);
329	} else {	332	} else {
330	err = __copy_from_user(&fpu->state.xsave,	333	err = __copy_from_user(&fpu->state.xsave, buf_fx, state_size);
331	buf_fx, state_size);	334
		335	if (!err && state_size > offsetof(struct xregs_state, header))
		336	err = validate_xstate_header(&fpu->state.xsave.header);
332	}	337	}
333		338
334	if (err \|\| __copy_from_user(&env, buf, sizeof(env))) {	339	if (err \|\| __copy_from_user(&env, buf, sizeof(env))) {
@@ -339,7 +344,7 @@ static int __fpu__restore_sig(void __user buf, void __user buf_fx, int size) · 4 unmodified lines
339	sanitize_restored_xstate(tsk, &env, xfeatures, fx_only);	344	sanitize_restored_xstate(tsk, &env, xfeatures, fx_only);
340	}	345	}
341		346
342	fpu->fpstate_active = 1;	347	fpu->initialized = 1;
343	preempt_disable();	348	preempt_disable();
344	fpu__restore(fpu);	349	fpu__restore(fpu);
345	preempt_enable();	350	preempt_enable();

arch/x86/kernel/fpu/xstate.c+213−51

@@ -483,6 +483,30 @@ int using_compacted_format(void) · 482 unmodified lines
483	return boot_cpu_has(X86_FEATURE_XSAVES);	483	return boot_cpu_has(X86_FEATURE_XSAVES);
484	}	484	}
485		485
		486	/* Validate an xstate header supplied by userspace (ptrace or sigreturn) */
		487	int validate_xstate_header(const struct xstate_header *hdr)
		488	{
		489	/* No unknown or supervisor features may be set */
		490	if (hdr->xfeatures & (~xfeatures_mask \| XFEATURE_MASK_SUPERVISOR))
		491	return -EINVAL;
		492
		493	/* Userspace must use the uncompacted format */
		494	if (hdr->xcomp_bv)
		495	return -EINVAL;
		496
		497	/*
		498	* If 'reserved' is shrunken to add a new field, make sure to validate
		499	* that new field here!
		500	*/
		501	BUILD_BUG_ON(sizeof(hdr->reserved) != 48);
		502
		503	/* No reserved bits may be set */
		504	if (memchr_inv(hdr->reserved, 0, sizeof(hdr->reserved)))
		505	return -EINVAL;
		506
		507	return 0;
		508	}
		509
486	static void __xstate_dump_leaves(void)	510	static void __xstate_dump_leaves(void)
487	{	511	{
488	int i;	512	int i;
@@ -867,7 +891,7 @@ const void *get_xsave_field_ptr(int xsave_state) · 378 unmodified lines
867	{	891	{
868	struct fpu *fpu = &current->thread.fpu;	892	struct fpu *fpu = &current->thread.fpu;
869		893
870	if (!fpu->fpstate_active)	894	if (!fpu->initialized)
871	return NULL;	895	return NULL;
872	/*	896	/*
873	* fpu__save() takes the CPU's xstate registers	897	* fpu__save() takes the CPU's xstate registers
@@ -920,39 +944,130 @@ int arch_set_user_pkey_access(struct task_struct *tsk, int pkey, · 46 unmodified lines
920	}	944	}
921	#endif /* ! CONFIG_ARCH_HAS_PKEYS */	945	#endif /* ! CONFIG_ARCH_HAS_PKEYS */
922		946
		947	/*
		948	* Weird legacy quirk: SSE and YMM states store information in the
		949	* MXCSR and MXCSR_FLAGS fields of the FP area. That means if the FP
		950	* area is marked as unused in the xfeatures header, we need to copy
		951	* MXCSR and MXCSR_FLAGS if either SSE or YMM are in use.
		952	*/
		953	static inline bool xfeatures_mxcsr_quirk(u64 xfeatures)
		954	{
		955	if (!(xfeatures & (XFEATURE_MASK_SSE\|XFEATURE_MASK_YMM)))
		956	return false;
		957
		958	if (xfeatures & XFEATURE_MASK_FP)
		959	return false;
		960
		961	return true;
		962	}
		963
923	/*	964	/*
924	* This is similar to user_regset_copyout(), but will not add offset to	965	* This is similar to user_regset_copyout(), but will not add offset to
925	* the source data pointer or increment pos, count, kbuf, and ubuf.	966	* the source data pointer or increment pos, count, kbuf, and ubuf.
926	*/	967	*/
927	static inline int xstate_copyout(unsigned int pos, unsigned int count,	968	static inline void
928	void kbuf, void __user ubuf,	969	__copy_xstate_to_kernel(void kbuf, const void data,
929	const void *data, const int start_pos,	970	unsigned int offset, unsigned int size, unsigned int size_total)
930	const int end_pos)
931	{	971	{
932	if ((count == 0) \|\| (pos < start_pos))	972	if (offset < size_total) {
933	return 0;	973	unsigned int copy = min(size, size_total - offset);
934		974
935	if (end_pos < 0 \|\| pos < end_pos) {	975	memcpy(kbuf + offset, data, copy);
936	unsigned int copy = (end_pos < 0 ? count : min(count, end_pos - pos));	976	}
		977	}
937		978
938	if (kbuf) {	979	/*
939	memcpy(kbuf + pos, data, copy);	980	* Convert from kernel XSAVES compacted format to standard format and copy
940	} else {	981	* to a kernel-space ptrace buffer.
941	if (__copy_to_user(ubuf + pos, data, copy))	982	*
942	return -EFAULT;	983	* It supports partial copy but pos always starts from zero. This is called
		984	* from xstateregs_get() and there we check the CPU has XSAVES.
		985	*/
		986	int copy_xstate_to_kernel(void kbuf, struct xregs_state xsave, unsigned int offset_start, unsigned int size_total)
		987	{
		988	unsigned int offset, size;
		989	struct xstate_header header;
		990	int i;
		991
		992	/*
		993	* Currently copy_regset_to_user() starts from pos 0:
		994	*/
		995	if (unlikely(offset_start != 0))
		996	return -EFAULT;
		997
		998	/*
		999	* The destination is a ptrace buffer; we put in only user xstates:
		1000	*/
		1001	memset(&header, 0, sizeof(header));
		1002	header.xfeatures = xsave->header.xfeatures;
		1003	header.xfeatures &= ~XFEATURE_MASK_SUPERVISOR;
		1004
		1005	/*
		1006	* Copy xregs_state->header:
		1007	*/
		1008	offset = offsetof(struct xregs_state, header);
		1009	size = sizeof(header);
		1010
		1011	__copy_xstate_to_kernel(kbuf, &header, offset, size, size_total);
		1012
		1013	for (i = 0; i < XFEATURE_MAX; i++) {
		1014	/*
		1015	* Copy only in-use xstates:
		1016	*/
		1017	if ((header.xfeatures >> i) & 1) {
		1018	void *src = __raw_xsave_addr(xsave, 1 << i);
		1019
		1020	offset = xstate_offsets[i];
		1021	size = xstate_sizes[i];
		1022
		1023	/* The next component has to fit fully into the output buffer: */
		1024	if (offset + size > size_total)
		1025	break;
		1026
		1027	__copy_xstate_to_kernel(kbuf, src, offset, size, size_total);
943	}	1028	}
		1029
		1030	}
		1031
		1032	if (xfeatures_mxcsr_quirk(header.xfeatures)) {
		1033	offset = offsetof(struct fxregs_state, mxcsr);
		1034	size = MXCSR_AND_FLAGS_SIZE;
		1035	__copy_xstate_to_kernel(kbuf, &xsave->i387.mxcsr, offset, size, size_total);
		1036	}
		1037
		1038	/*
		1039	* Fill xsave->i387.sw_reserved value for ptrace frame:
		1040	*/
		1041	offset = offsetof(struct fxregs_state, sw_reserved);
		1042	size = sizeof(xstate_fx_sw_bytes);
		1043
		1044	__copy_xstate_to_kernel(kbuf, xstate_fx_sw_bytes, offset, size, size_total);
		1045
		1046	return 0;
		1047	}
		1048
		1049	static inline int
		1050	__copy_xstate_to_user(void __user ubuf, const void data, unsigned int offset, unsigned int size, unsigned int size_total)
		1051	{
		1052	if (!size)
		1053	return 0;
		1054
		1055	if (offset < size_total) {
		1056	unsigned int copy = min(size, size_total - offset);
		1057
		1058	if (__copy_to_user(ubuf + offset, data, copy))
		1059	return -EFAULT;
944	}	1060	}
945	return 0;	1061	return 0;
946	}	1062	}
947		1063
948	/*	1064	/*
949	* Convert from kernel XSAVES compacted format to standard format and copy	1065	* Convert from kernel XSAVES compacted format to standard format and copy
950	* to a ptrace buffer. It supports partial copy but pos always starts from	1066	* to a user-space buffer. It supports partial copy but pos always starts from
951	* zero. This is called from xstateregs_get() and there we check the CPU	1067	* zero. This is called from xstateregs_get() and there we check the CPU
952	* has XSAVES.	1068	* has XSAVES.
953	*/	1069	*/
954	int copyout_from_xsaves(unsigned int pos, unsigned int count, void *kbuf,	1070	int copy_xstate_to_user(void __user ubuf, struct xregs_state xsave, unsigned int offset_start, unsigned int size_total)
955	void __user ubuf, struct xregs_state xsave)
956	{	1071	{
957	unsigned int offset, size;	1072	unsigned int offset, size;
958	int ret, i;	1073	int ret, i;
@@ -961,7 +1076,7 @@ int copyout_from_xsaves(unsigned int pos, unsigned int count, void *kbuf, · 2 unmodified lines
961	/*	1076	/*
962	* Currently copy_regset_to_user() starts from pos 0:	1077	* Currently copy_regset_to_user() starts from pos 0:
963	*/	1078	*/
964	if (unlikely(pos != 0))	1079	if (unlikely(offset_start != 0))
965	return -EFAULT;	1080	return -EFAULT;
966		1081
967	/*	1082	/*
@@ -977,8 +1092,7 @@ int copyout_from_xsaves(unsigned int pos, unsigned int count, void *kbuf, · 9 unmodified lines
977	offset = offsetof(struct xregs_state, header);	1092	offset = offsetof(struct xregs_state, header);
978	size = sizeof(header);	1093	size = sizeof(header);
979		1094
980	ret = xstate_copyout(offset, size, kbuf, ubuf, &header, 0, count);	1095	ret = __copy_xstate_to_user(ubuf, &header, offset, size, size_total);
981
982	if (ret)	1096	if (ret)
983	return ret;	1097	return ret;
984		1098
@@ -992,25 +1106,30 @@ int copyout_from_xsaves(unsigned int pos, unsigned int count, void *kbuf, · 7 unmodified lines
992	offset = xstate_offsets[i];	1106	offset = xstate_offsets[i];
993	size = xstate_sizes[i];	1107	size = xstate_sizes[i];
994		1108
995	ret = xstate_copyout(offset, size, kbuf, ubuf, src, 0, count);	1109	/* The next component has to fit fully into the output buffer: */
		1110	if (offset + size > size_total)
		1111	break;
996		1112
		1113	ret = __copy_xstate_to_user(ubuf, src, offset, size, size_total);
997	if (ret)	1114	if (ret)
998	return ret;	1115	return ret;
999
1000	if (offset + size >= count)
1001	break;
1002	}	1116	}
1003		1117
1004	}	1118	}
1005		1119
		1120	if (xfeatures_mxcsr_quirk(header.xfeatures)) {
		1121	offset = offsetof(struct fxregs_state, mxcsr);
		1122	size = MXCSR_AND_FLAGS_SIZE;
		1123	__copy_xstate_to_user(ubuf, &xsave->i387.mxcsr, offset, size, size_total);
		1124	}
		1125
1006	/*	1126	/*
1007	* Fill xsave->i387.sw_reserved value for ptrace frame:	1127	* Fill xsave->i387.sw_reserved value for ptrace frame:
1008	*/	1128	*/
1009	offset = offsetof(struct fxregs_state, sw_reserved);	1129	offset = offsetof(struct fxregs_state, sw_reserved);
1010	size = sizeof(xstate_fx_sw_bytes);	1130	size = sizeof(xstate_fx_sw_bytes);
1011		1131
1012	ret = xstate_copyout(offset, size, kbuf, ubuf, xstate_fx_sw_bytes, 0, count);	1132	ret = __copy_xstate_to_user(ubuf, xstate_fx_sw_bytes, offset, size, size_total);
1013
1014	if (ret)	1133	if (ret)
1015	return ret;	1134	return ret;
1016		1135
@@ -1018,55 +1137,98 @@ int copyout_from_xsaves(unsigned int pos, unsigned int count, void *kbuf, · 1 unmodified line
1018	}	1137	}
1019		1138
1020	/*	1139	/*
1021	* Convert from a ptrace standard-format buffer to kernel XSAVES format	1140	* Convert from a ptrace standard-format kernel buffer to kernel XSAVES format
1022	* and copy to the target thread. This is called from xstateregs_set() and	1141	* and copy to the target thread. This is called from xstateregs_set().
1023	* there we check the CPU has XSAVES and a whole standard-sized buffer
1024	* exists.
1025	*/	1142	*/
1026	int copyin_to_xsaves(const void kbuf, const void __user ubuf,	1143	int copy_kernel_to_xstate(struct xregs_state xsave, const void kbuf)
1027	struct xregs_state *xsave)
1028	{	1144	{
1029	unsigned int offset, size;	1145	unsigned int offset, size;
1030	int i;	1146	int i;
1031	u64 xfeatures;	1147	struct xstate_header hdr;
1032	u64 allowed_features;
1033		1148
1034	offset = offsetof(struct xregs_state, header);	1149	offset = offsetof(struct xregs_state, header);
1035	size = sizeof(xfeatures);	1150	size = sizeof(hdr);
1036		1151
1037	if (kbuf) {	1152	memcpy(&hdr, kbuf + offset, size);
1038	memcpy(&xfeatures, kbuf + offset, size);	1153
1039	} else {	1154	if (validate_xstate_header(&hdr))
1040	if (__copy_from_user(&xfeatures, ubuf + offset, size))	1155	return -EINVAL;
1041	return -EFAULT;	1156
		1157	for (i = 0; i < XFEATURE_MAX; i++) {
		1158	u64 mask = ((u64)1 << i);
		1159
		1160	if (hdr.xfeatures & mask) {
		1161	void *dst = __raw_xsave_addr(xsave, 1 << i);
		1162
		1163	offset = xstate_offsets[i];
		1164	size = xstate_sizes[i];
		1165
		1166	memcpy(dst, kbuf + offset, size);
		1167	}
		1168	}
		1169
		1170	if (xfeatures_mxcsr_quirk(hdr.xfeatures)) {
		1171	offset = offsetof(struct fxregs_state, mxcsr);
		1172	size = MXCSR_AND_FLAGS_SIZE;
		1173	memcpy(&xsave->i387.mxcsr, kbuf + offset, size);
1042	}	1174	}
1043		1175
1044	/*	1176	/*
1045	* Reject if the user sets any disabled or supervisor features:	1177	* The state that came in from userspace was user-state only.
		1178	* Mask all the user states out of 'xfeatures':
		1179	*/
		1180	xsave->header.xfeatures &= XFEATURE_MASK_SUPERVISOR;
		1181
		1182	/*
		1183	* Add back in the features that came in from userspace:
1046	*/	1184	*/
1047	allowed_features = xfeatures_mask & ~XFEATURE_MASK_SUPERVISOR;	1185	xsave->header.xfeatures \|= hdr.xfeatures;
1048		1186
1049	if (xfeatures & ~allowed_features)	1187	return 0;
		1188	}
		1189
		1190	/*
		1191	* Convert from a ptrace or sigreturn standard-format user-space buffer to
		1192	* kernel XSAVES format and copy to the target thread. This is called from
		1193	* xstateregs_set(), as well as potentially from the sigreturn() and
		1194	* rt_sigreturn() system calls.
		1195	*/
		1196	int copy_user_to_xstate(struct xregs_state xsave, const void __user ubuf)
		1197	{
		1198	unsigned int offset, size;
		1199	int i;
		1200	struct xstate_header hdr;
		1201
		1202	offset = offsetof(struct xregs_state, header);
		1203	size = sizeof(hdr);
		1204
		1205	if (__copy_from_user(&hdr, ubuf + offset, size))
		1206	return -EFAULT;
		1207
		1208	if (validate_xstate_header(&hdr))
1050	return -EINVAL;	1209	return -EINVAL;
1051		1210
1052	for (i = 0; i < XFEATURE_MAX; i++) {	1211	for (i = 0; i < XFEATURE_MAX; i++) {
1053	u64 mask = ((u64)1 << i);	1212	u64 mask = ((u64)1 << i);
1054		1213
1055	if (xfeatures & mask) {	1214	if (hdr.xfeatures & mask) {
1056	void *dst = __raw_xsave_addr(xsave, 1 << i);	1215	void *dst = __raw_xsave_addr(xsave, 1 << i);
1057		1216
1058	offset = xstate_offsets[i];	1217	offset = xstate_offsets[i];
1059	size = xstate_sizes[i];	1218	size = xstate_sizes[i];
1060		1219
1061	if (kbuf) {	1220	if (__copy_from_user(dst, ubuf + offset, size))
1062	memcpy(dst, kbuf + offset, size);	1221	return -EFAULT;
1063	} else {
1064	if (__copy_from_user(dst, ubuf + offset, size))
1065	return -EFAULT;
1066	}
1067	}	1222	}
1068	}	1223	}
1069		1224
		1225	if (xfeatures_mxcsr_quirk(hdr.xfeatures)) {
		1226	offset = offsetof(struct fxregs_state, mxcsr);
		1227	size = MXCSR_AND_FLAGS_SIZE;
		1228	if (__copy_from_user(&xsave->i387.mxcsr, ubuf + offset, size))
		1229	return -EFAULT;
		1230	}
		1231
1070	/*	1232	/*
1071	* The state that came in from userspace was user-state only.	1233	* The state that came in from userspace was user-state only.
1072	* Mask all the user states out of 'xfeatures':	1234	* Mask all the user states out of 'xfeatures':
@@ -1076,7 +1238,7 @@ int copyin_to_xsaves(const void kbuf, const void __user ubuf, · 3 unmodified lines
1076	/*	1238	/*
1077	* Add back in the features that came in from userspace:	1239	* Add back in the features that came in from userspace:
1078	*/	1240	*/
1079	xsave->header.xfeatures \|= xfeatures;	1241	xsave->header.xfeatures \|= hdr.xfeatures;
1080		1242
1081	return 0;	1243	return 0;
1082	}	1244	}

arch/x86/kernel/irq_32.c+3−3

@@ -64,7 +64,7 @@ static void call_on_stack(void func, void stack) · 63 unmodified lines
64		64
65	static inline void *current_stack(void)	65	static inline void *current_stack(void)
66	{	66	{
67	return (void *)(current_stack_pointer() & ~(THREAD_SIZE - 1));	67	return (void *)(current_stack_pointer & ~(THREAD_SIZE - 1));
68	}	68	}
69		69
70	static inline int execute_on_irq_stack(int overflow, struct irq_desc *desc)	70	static inline int execute_on_irq_stack(int overflow, struct irq_desc *desc)
@@ -88,7 +88,7 @@ static inline int execute_on_irq_stack(int overflow, struct irq_desc *desc) · 17 unmodified lines
88		88
89	/* Save the next esp at the bottom of the stack */	89	/* Save the next esp at the bottom of the stack */
90	prev_esp = (u32 *)irqstk;	90	prev_esp = (u32 *)irqstk;
91	*prev_esp = current_stack_pointer();	91	*prev_esp = current_stack_pointer;
92		92
93	if (unlikely(overflow))	93	if (unlikely(overflow))
94	call_on_stack(print_stack_overflow, isp);	94	call_on_stack(print_stack_overflow, isp);
@@ -139,7 +139,7 @@ void do_softirq_own_stack(void) · 44 unmodified lines
139		139
140	/* Push the previous esp onto the stack */	140	/* Push the previous esp onto the stack */
141	prev_esp = (u32 *)irqstk;	141	prev_esp = (u32 *)irqstk;
142	*prev_esp = current_stack_pointer();	142	*prev_esp = current_stack_pointer;
143		143
144	call_on_stack(__do_softirq, isp);	144	call_on_stack(__do_softirq, isp);
145	}	145	}

arch/x86/kernel/ksysfs.c+1−1

@@ -299,7 +299,7 @@ static int __init create_setup_data_nodes(struct kobject *parent) · 298 unmodified lines
299	return 0;	299	return 0;
300		300
301	out_clean_nodes:	301	out_clean_nodes:
302	for (j = i - 1; j > 0; j--)	302	for (j = i - 1; j >= 0; j--)
303	cleanup_setup_data_node(*(kobjp + j));	303	cleanup_setup_data_node(*(kobjp + j));
304	kfree(kobjp);	304	kfree(kobjp);
305	out_setup_data_kobj:	305	out_setup_data_kobj:

arch/x86/kernel/kvm.c+10−3

 	return NULL;
 }
-void kvm_async_pf_task_wait(u32 token)
+/*
+ * @interrupt_kernel: Is this called from a routine which interrupts the kernel
+ * 		      (other than user space)?
+ */
+void kvm_async_pf_task_wait(u32 token, int interrupt_kernel)
 {
 	u32 key = hash_32(token, KVM_TASK_SLEEP_HASHBITS);
 	struct kvm_task_sleep_head *b = &async_pf_sleepers[key];
 	n.token = token;
 	n.cpu = smp_processor_id();
-	n.halted = is_idle_task(current) || preempt_count() > 1;
+	n.halted = is_idle_task(current) ||
+		   (IS_ENABLED(CONFIG_PREEMPT_COUNT)
+		    ? preempt_count() > 1 || rcu_preempt_depth()
+		    : interrupt_kernel);
 	init_swait_queue_head(&n.wq);
 	hlist_add_head(&n.link, &b->list);
 	raw_spin_unlock(&b->lock);
 	case KVM_PV_REASON_PAGE_NOT_PRESENT:
 		/* page is swapped out by the host. */
 		prev_state = exception_enter();
-		kvm_async_pf_task_wait((u32)read_cr2());
+		kvm_async_pf_task_wait((u32)read_cr2(), !user_mode(regs));
 		exception_exit(prev_state);
 		break;
 	case KVM_PV_REASON_PAGE_READY:

arch/x86/kernel/signal.c+3−3

@@ -263,7 +263,7 @@ get_sigframe(struct k_sigaction ka, struct pt_regs regs, size_t frame_size, · 262 unmodified lines
263	sp = (unsigned long) ka->sa.sa_restorer;	263	sp = (unsigned long) ka->sa.sa_restorer;
264	}	264	}
265		265
266	if (fpu->fpstate_active) {	266	if (fpu->initialized) {
267	sp = fpu__alloc_mathframe(sp, IS_ENABLED(CONFIG_X86_32),	267	sp = fpu__alloc_mathframe(sp, IS_ENABLED(CONFIG_X86_32),
268	&buf_fx, &math_size);	268	&buf_fx, &math_size);
269	fpstate = (void __user )sp;	269	fpstate = (void __user )sp;
@@ -279,7 +279,7 @@ get_sigframe(struct k_sigaction ka, struct pt_regs regs, size_t frame_size, · 9 unmodified lines
279	return (void __user *)-1L;	279	return (void __user *)-1L;
280		280
281	/* save i387 and extended state */	281	/* save i387 and extended state */
282	if (fpu->fpstate_active &&	282	if (fpu->initialized &&
283	copy_fpstate_to_sigframe(fpstate, (void __user )buf_fx, math_size) < 0)	283	copy_fpstate_to_sigframe(fpstate, (void __user )buf_fx, math_size) < 0)
284	return (void __user *)-1L;	284	return (void __user *)-1L;
285		285
@@ -755,7 +755,7 @@ handle_signal(struct ksignal ksig, struct pt_regs regs) · 469 unmodified lines
755	/*	755	/*
756	* Ensure the signal handler starts with the new fpu state.	756	* Ensure the signal handler starts with the new fpu state.
757	*/	757	*/
758	if (fpu->fpstate_active)	758	if (fpu->initialized)
759	fpu__clear(fpu);	759	fpu__clear(fpu);
760	}	760	}
761	signal_setup_done(failed, ksig, stepping);	761	signal_setup_done(failed, ksig, stepping);

arch/x86/kernel/smpboot.c+7−6

 	 */
 	if (boot_cpu_has(X86_FEATURE_PCID))
 		__write_cr4(__read_cr4() | X86_CR4_PCIDE);
-	cpu_init();
-	x86_cpuinit.early_percpu_clock_init();
-	preempt_disable();
-	smp_callin();
-	enable_start_cpu0 = 0;
 #ifdef CONFIG_X86_32
 	/* switch away from the initial page table */
 	__flush_tlb_all();
 #endif
+	cpu_init();
+	x86_cpuinit.early_percpu_clock_init();
+	preempt_disable();
+	smp_callin();
+	enable_start_cpu0 = 0;
 	/* otherwise gcc will move up smp_processor_id before the cpu_init */
 	barrier();
 	/*

arch/x86/kernel/traps.c+1−1

@@ -142,7 +142,7 @@ void ist_begin_non_atomic(struct pt_regs *regs) · 141 unmodified lines
142	* from double_fault.	142	* from double_fault.
143	*/	143	*/
144	BUG_ON((unsigned long)(current_top_of_stack() -	144	BUG_ON((unsigned long)(current_top_of_stack() -
145	current_stack_pointer()) >= THREAD_SIZE);	145	current_stack_pointer) >= THREAD_SIZE);
146		146
147	preempt_enable_no_resched();	147	preempt_enable_no_resched();
148	}	148	}

arch/x86/kvm/Kconfig+1−0

@@ -23,6 +23,7 @@ config KVM · 22 unmodified lines
23	depends on HIGH_RES_TIMERS	23	depends on HIGH_RES_TIMERS
24	# for TASKSTATS/TASK_DELAY_ACCT:	24	# for TASKSTATS/TASK_DELAY_ACCT:
25	depends on NET && MULTIUSER	25	depends on NET && MULTIUSER
		26	depends on X86_LOCAL_APIC
26	select PREEMPT_NOTIFIERS	27	select PREEMPT_NOTIFIERS
27	select MMU_NOTIFIER	28	select MMU_NOTIFIER
28	select ANON_INODES	29	select ANON_INODES

arch/x86/kvm/emulate.c+10−7

 	#op " %al \n\t" \
 	FOP_RET
-asm(".global kvm_fastop_exception \n"
+asm(".pushsection .fixup, \"ax\"\n"
-    "kvm_fastop_exception: xor %esi, %esi; ret");
+    ".global kvm_fastop_exception \n"
+    "kvm_fastop_exception: xor %esi, %esi; ret\n"
+    ".popsection");
 FOP_START(setcc)
 FOP_SETCC(seto)
 		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
 		if (efer & EFER_LMA) {
 			u64 maxphyaddr;
-			u32 eax = 0x80000008;
+			u32 eax, ebx, ecx, edx;
-			if (ctxt->ops->get_cpuid(ctxt, &eax, NULL, NULL,
+			eax = 0x80000008;
-						 NULL, false))
+			ecx = 0;
+			if (ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx,
+						 &edx, false))
 				maxphyaddr = eax & 0xff;
 			else
 				maxphyaddr = 36;
 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
 {
-	register void *__sp asm(_ASM_SP);
 	ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
 	if (!(ctxt->d & ByteOp))
 	asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
 	    : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
-	      [fastop]"+S"(fop), "+r"(__sp)
+	      [fastop]"+S"(fop), ASM_CALL_CONSTRAINT
 	    : "c"(ctxt->src2.val));
 	ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);

arch/x86/kvm/mmu.c+1−1

@@ -3837,7 +3837,7 @@ int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, · 3836 unmodified lines
3837	case KVM_PV_REASON_PAGE_NOT_PRESENT:	3837	case KVM_PV_REASON_PAGE_NOT_PRESENT:
3838	vcpu->arch.apf.host_apf_reason = 0;	3838	vcpu->arch.apf.host_apf_reason = 0;
3839	local_irq_disable();	3839	local_irq_disable();
3840	kvm_async_pf_task_wait(fault_address);	3840	kvm_async_pf_task_wait(fault_address, 0);
3841	local_irq_enable();	3841	local_irq_enable();
3842	break;	3842	break;
3843	case KVM_PV_REASON_PAGE_READY:	3843	case KVM_PV_REASON_PAGE_READY:

arch/x86/kvm/vmx.c+124−124

@@ -200,6 +200,8 @@ struct loaded_vmcs { · 199 unmodified lines
200	int cpu;	200	int cpu;
201	bool launched;	201	bool launched;
202	bool nmi_known_unmasked;	202	bool nmi_known_unmasked;
		203	unsigned long vmcs_host_cr3; /* May not match real cr3 */
		204	unsigned long vmcs_host_cr4; /* May not match real cr4 */
203	struct list_head loaded_vmcss_on_cpu_link;	205	struct list_head loaded_vmcss_on_cpu_link;
204	};	206	};
205		207
@@ -600,8 +602,6 @@ struct vcpu_vmx { · 394 unmodified lines
600	int gs_ldt_reload_needed;	602	int gs_ldt_reload_needed;
601	int fs_reload_needed;	603	int fs_reload_needed;
602	u64 msr_host_bndcfgs;	604	u64 msr_host_bndcfgs;
603	unsigned long vmcs_host_cr3; /* May not match real cr3 */
604	unsigned long vmcs_host_cr4; /* May not match real cr4 */
605	} host_state;	605	} host_state;
606	struct {	606	struct {
607	int vm86_active;	607	int vm86_active;
@@ -2202,46 +2202,44 @@ static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) · 1594 unmodified lines
2202	struct pi_desc old, new;	2202	struct pi_desc old, new;
2203	unsigned int dest;	2203	unsigned int dest;
2204		2204
2205	if (!kvm_arch_has_assigned_device(vcpu->kvm) \|\|	2205	/*
2206	!irq_remapping_cap(IRQ_POSTING_CAP) \|\|	2206	* In case of hot-plug or hot-unplug, we may have to undo
2207	!kvm_vcpu_apicv_active(vcpu))	2207	* vmx_vcpu_pi_put even if there is no assigned device. And we
		2208	* always keep PI.NDST up to date for simplicity: it makes the
		2209	* code easier, and CPU migration is not a fast path.
		2210	*/
		2211	if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
		2212	return;
		2213
		2214	/*
		2215	* First handle the simple case where no cmpxchg is necessary; just
		2216	* allow posting non-urgent interrupts.
		2217	*
		2218	* If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
		2219	* PI.NDST: pi_post_block will do it for us and the wakeup_handler
		2220	* expects the VCPU to be on the blocked_vcpu_list that matches
		2221	* PI.NDST.
		2222	*/
		2223	if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR \|\|
		2224	vcpu->cpu == cpu) {
		2225	pi_clear_sn(pi_desc);
2208	return;	2226	return;
		2227	}
2209		2228
		2229	/* The full case. */
2210	do {	2230	do {
2211	old.control = new.control = pi_desc->control;	2231	old.control = new.control = pi_desc->control;
2212		2232
2213	/*	2233	dest = cpu_physical_id(cpu);
2214	* If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2215	* are two possible cases:
2216	* 1. After running 'pre_block', context switch
2217	* happened. For this case, 'sn' was set in
2218	* vmx_vcpu_put(), so we need to clear it here.
2219	* 2. After running 'pre_block', we were blocked,
2220	* and woken up by some other guy. For this case,
2221	* we don't need to do anything, 'pi_post_block'
2222	* will do everything for us. However, we cannot
2223	* check whether it is case #1 or case #2 here
2224	* (maybe, not needed), so we also clear sn here,
2225	* I think it is not a big deal.
2226	*/
2227	if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2228	if (vcpu->cpu != cpu) {
2229	dest = cpu_physical_id(cpu);
2230
2231	if (x2apic_enabled())
2232	new.ndst = dest;
2233	else
2234	new.ndst = (dest << 8) & 0xFF00;
2235	}
2236		2234
2237	/* set 'NV' to 'notification vector' */	2235	if (x2apic_enabled())
2238	new.nv = POSTED_INTR_VECTOR;	2236	new.ndst = dest;
2239	}	2237	else
		2238	new.ndst = (dest << 8) & 0xFF00;
2240		2239
2241	/* Allow posting non-urgent interrupts */
2242	new.sn = 0;	2240	new.sn = 0;
2243	} while (cmpxchg(&pi_desc->control, old.control,	2241	} while (cmpxchg64(&pi_desc->control, old.control,
2244	new.control) != old.control);	2242	new.control) != old.control);
2245	}	2243	}
2246		2244
2247	static void decache_tsc_multiplier(struct vcpu_vmx *vmx)	2245	static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
@@ -5077,21 +5075,30 @@ static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, · 2829 unmodified lines
5077	int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;	5075	int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5078		5076
5079	if (vcpu->mode == IN_GUEST_MODE) {	5077	if (vcpu->mode == IN_GUEST_MODE) {
5080	struct vcpu_vmx *vmx = to_vmx(vcpu);
5081
5082	/*	5078	/*
5083	* Currently, we don't support urgent interrupt,	5079	* The vector of interrupt to be delivered to vcpu had
5084	* all interrupts are recognized as non-urgent	5080	* been set in PIR before this function.
5085	* interrupt, so we cannot post interrupts when	5081	*
5086	* 'SN' is set.	5082	* Following cases will be reached in this block, and
		5083	* we always send a notification event in all cases as
		5084	* explained below.
		5085	*
		5086	* Case 1: vcpu keeps in non-root mode. Sending a
		5087	* notification event posts the interrupt to vcpu.
5087	*	5088	*
5088	* If the vcpu is in guest mode, it means it is	5089	* Case 2: vcpu exits to root mode and is still
5089	* running instead of being scheduled out and	5090	* runnable. PIR will be synced to vIRR before the
5090	* waiting in the run queue, and that's the only	5091	* next vcpu entry. Sending a notification event in
5091	* case when 'SN' is set currently, warning if	5092	* this case has no effect, as vcpu is not in root
5092	* 'SN' is set.	5093	* mode.
		5094	*
		5095	* Case 3: vcpu exits to root mode and is blocked.
		5096	* vcpu_block() has already synced PIR to vIRR and
		5097	* never blocks vcpu if vIRR is not cleared. Therefore,
		5098	* a blocked vcpu here does not wait for any requested
		5099	* interrupts in PIR, and sending a notification event
		5100	* which has no effect is safe here.
5093	*/	5101	*/
5094	WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5095		5102
5096	apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);	5103	apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5097	return true;	5104	return true;
@@ -5169,12 +5176,12 @@ static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) · 71 unmodified lines
5169	*/	5176	*/
5170	cr3 = __read_cr3();	5177	cr3 = __read_cr3();
5171	vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */	5178	vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5172	vmx->host_state.vmcs_host_cr3 = cr3;	5179	vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5173		5180
5174	/* Save the most likely value for this task's CR4 in the VMCS. */	5181	/* Save the most likely value for this task's CR4 in the VMCS. */
5175	cr4 = cr4_read_shadow();	5182	cr4 = cr4_read_shadow();
5176	vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */	5183	vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5177	vmx->host_state.vmcs_host_cr4 = cr4;	5184	vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5178		5185
5179	vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */	5186	vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5180	#ifdef CONFIG_X86_64	5187	#ifdef CONFIG_X86_64
@@ -9036,7 +9043,6 @@ static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) · 3855 unmodified lines
9036	static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)	9043	static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9037	{	9044	{
9038	u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);	9045	u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9039	register void *__sp asm(_ASM_SP);
9040		9046
9041	if ((exit_intr_info & (INTR_INFO_VALID_MASK \| INTR_INFO_INTR_TYPE_MASK))	9047	if ((exit_intr_info & (INTR_INFO_VALID_MASK \| INTR_INFO_INTR_TYPE_MASK))
9042	== (INTR_INFO_VALID_MASK \| INTR_TYPE_EXT_INTR)) {	9048	== (INTR_INFO_VALID_MASK \| INTR_TYPE_EXT_INTR)) {
@@ -9065,7 +9071,7 @@ static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) · 22 unmodified lines
9065	#ifdef CONFIG_X86_64	9071	#ifdef CONFIG_X86_64
9066	[sp]"=&r"(tmp),	9072	[sp]"=&r"(tmp),
9067	#endif	9073	#endif
9068	"+r"(__sp)	9074	ASM_CALL_CONSTRAINT
9069	:	9075	:
9070	[entry]"r"(entry),	9076	[entry]"r"(entry),
9071	[ss]"i"(__KERNEL_DS),	9077	[ss]"i"(__KERNEL_DS),
@@ -9265,15 +9271,15 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) · 193 unmodified lines
9265	vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);	9271	vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9266		9272
9267	cr3 = __get_current_cr3_fast();	9273	cr3 = __get_current_cr3_fast();
9268	if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {	9274	if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9269	vmcs_writel(HOST_CR3, cr3);	9275	vmcs_writel(HOST_CR3, cr3);
9270	vmx->host_state.vmcs_host_cr3 = cr3;	9276	vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9271	}	9277	}
9272		9278
9273	cr4 = cr4_read_shadow();	9279	cr4 = cr4_read_shadow();
9274	if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {	9280	if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9275	vmcs_writel(HOST_CR4, cr4);	9281	vmcs_writel(HOST_CR4, cr4);
9276	vmx->host_state.vmcs_host_cr4 = cr4;	9282	vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9277	}	9283	}
9278		9284
9279	/* When single-stepping over STI and MOV SS, we must clear the	9285	/* When single-stepping over STI and MOV SS, we must clear the
@@ -9583,6 +9589,13 @@ static struct kvm_vcpu vmx_create_vcpu(struct kvm kvm, unsigned int id) · 303 unmodified lines
9583		9589
9584	vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;	9590	vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9585		9591
		9592	/*
		9593	* Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
		9594	* or POSTED_INTR_WAKEUP_VECTOR.
		9595	*/
		9596	vmx->pi_desc.nv = POSTED_INTR_VECTOR;
		9597	vmx->pi_desc.sn = 1;
		9598
9586	return &vmx->vcpu;	9599	return &vmx->vcpu;
9587		9600
9588	free_vmcs:	9601	free_vmcs:
@@ -9831,7 +9844,8 @@ static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, · 242 unmodified lines
9831		9844
9832	WARN_ON(!is_guest_mode(vcpu));	9845	WARN_ON(!is_guest_mode(vcpu));
9833		9846
9834	if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) {	9847	if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
		9848	!to_vmx(vcpu)->nested.nested_run_pending) {
9835	vmcs12->vm_exit_intr_error_code = fault->error_code;	9849	vmcs12->vm_exit_intr_error_code = fault->error_code;
9836	nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,	9850	nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9837	PF_VECTOR \| INTR_TYPE_HARD_EXCEPTION \|	9851	PF_VECTOR \| INTR_TYPE_HARD_EXCEPTION \|
@@ -11696,6 +11710,37 @@ static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, · 1858 unmodified lines
11696	kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);	11710	kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11697	}	11711	}
11698		11712
		11713	static void __pi_post_block(struct kvm_vcpu *vcpu)
		11714	{
		11715	struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
		11716	struct pi_desc old, new;
		11717	unsigned int dest;
		11718
		11719	do {
		11720	old.control = new.control = pi_desc->control;
		11721	WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
		11722	"Wakeup handler not enabled while the VCPU is blocked\n");
		11723
		11724	dest = cpu_physical_id(vcpu->cpu);
		11725
		11726	if (x2apic_enabled())
		11727	new.ndst = dest;
		11728	else
		11729	new.ndst = (dest << 8) & 0xFF00;
		11730
		11731	/* set 'NV' to 'notification vector' */
		11732	new.nv = POSTED_INTR_VECTOR;
		11733	} while (cmpxchg64(&pi_desc->control, old.control,
		11734	new.control) != old.control);
		11735
		11736	if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
		11737	spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
		11738	list_del(&vcpu->blocked_vcpu_list);
		11739	spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
		11740	vcpu->pre_pcpu = -1;
		11741	}
		11742	}
		11743
11699	/*	11744	/*
11700	* This routine does the following things for vCPU which is going	11745	* This routine does the following things for vCPU which is going
11701	* to be blocked if VT-d PI is enabled.	11746	* to be blocked if VT-d PI is enabled.
@@ -11711,7 +11756,6 @@ static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, · 9 unmodified lines
11711	*/	11756	*/
11712	static int pi_pre_block(struct kvm_vcpu *vcpu)	11757	static int pi_pre_block(struct kvm_vcpu *vcpu)
11713	{	11758	{
11714	unsigned long flags;
11715	unsigned int dest;	11759	unsigned int dest;
11716	struct pi_desc old, new;	11760	struct pi_desc old, new;
11717	struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);	11761	struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
@@ -11721,34 +11765,20 @@ static int pi_pre_block(struct kvm_vcpu *vcpu) · 3 unmodified lines
11721	!kvm_vcpu_apicv_active(vcpu))	11765	!kvm_vcpu_apicv_active(vcpu))
11722	return 0;	11766	return 0;
11723		11767
11724	vcpu->pre_pcpu = vcpu->cpu;	11768	WARN_ON(irqs_disabled());
11725	spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,	11769	local_irq_disable();
11726	vcpu->pre_pcpu), flags);	11770	if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
11727	list_add_tail(&vcpu->blocked_vcpu_list,	11771	vcpu->pre_pcpu = vcpu->cpu;
11728	&per_cpu(blocked_vcpu_on_cpu,	11772	spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11729	vcpu->pre_pcpu));	11773	list_add_tail(&vcpu->blocked_vcpu_list,
11730	spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,	11774	&per_cpu(blocked_vcpu_on_cpu,
11731	vcpu->pre_pcpu), flags);	11775	vcpu->pre_pcpu));
		11776	spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
		11777	}
11732		11778
11733	do {	11779	do {
11734	old.control = new.control = pi_desc->control;	11780	old.control = new.control = pi_desc->control;
11735		11781
11736	/*
11737	* We should not block the vCPU if
11738	* an interrupt is posted for it.
11739	*/
11740	if (pi_test_on(pi_desc) == 1) {
11741	spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11742	vcpu->pre_pcpu), flags);
11743	list_del(&vcpu->blocked_vcpu_list);
11744	spin_unlock_irqrestore(
11745	&per_cpu(blocked_vcpu_on_cpu_lock,
11746	vcpu->pre_pcpu), flags);
11747	vcpu->pre_pcpu = -1;
11748
11749	return 1;
11750	}
11751
11752	WARN((pi_desc->sn == 1),	11782	WARN((pi_desc->sn == 1),
11753	"Warning: SN field of posted-interrupts "	11783	"Warning: SN field of posted-interrupts "
11754	"is set before blocking\n");	11784	"is set before blocking\n");
@@ -11770,10 +11800,15 @@ static int pi_pre_block(struct kvm_vcpu *vcpu) · 15 unmodified lines
11770		11800
11771	/* set 'NV' to 'wakeup vector' */	11801	/* set 'NV' to 'wakeup vector' */
11772	new.nv = POSTED_INTR_WAKEUP_VECTOR;	11802	new.nv = POSTED_INTR_WAKEUP_VECTOR;
11773	} while (cmpxchg(&pi_desc->control, old.control,	11803	} while (cmpxchg64(&pi_desc->control, old.control,
11774	new.control) != old.control);	11804	new.control) != old.control);
11775		11805
11776	return 0;	11806	/* We should not block the vCPU if an interrupt is posted for it. */
		11807	if (pi_test_on(pi_desc) == 1)
		11808	__pi_post_block(vcpu);
		11809
		11810	local_irq_enable();
		11811	return (vcpu->pre_pcpu == -1);
11777	}	11812	}
11778		11813
11779	static int vmx_pre_block(struct kvm_vcpu *vcpu)	11814	static int vmx_pre_block(struct kvm_vcpu *vcpu)
@@ -11789,44 +11824,13 @@ static int vmx_pre_block(struct kvm_vcpu *vcpu) · 9 unmodified lines
11789		11824
11790	static void pi_post_block(struct kvm_vcpu *vcpu)	11825	static void pi_post_block(struct kvm_vcpu *vcpu)
11791	{	11826	{
11792	struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);	11827	if (vcpu->pre_pcpu == -1)
11793	struct pi_desc old, new;
11794	unsigned int dest;
11795	unsigned long flags;
11796
11797	if (!kvm_arch_has_assigned_device(vcpu->kvm) \|\|
11798	!irq_remapping_cap(IRQ_POSTING_CAP) \|\|
11799	!kvm_vcpu_apicv_active(vcpu))
11800	return;	11828	return;
11801		11829
11802	do {	11830	WARN_ON(irqs_disabled());
11803	old.control = new.control = pi_desc->control;	11831	local_irq_disable();
11804		11832	__pi_post_block(vcpu);
11805	dest = cpu_physical_id(vcpu->cpu);	11833	local_irq_enable();
11806
11807	if (x2apic_enabled())
11808	new.ndst = dest;
11809	else
11810	new.ndst = (dest << 8) & 0xFF00;
11811
11812	/* Allow posting non-urgent interrupts */
11813	new.sn = 0;
11814
11815	/* set 'NV' to 'notification vector' */
11816	new.nv = POSTED_INTR_VECTOR;
11817	} while (cmpxchg(&pi_desc->control, old.control,
11818	new.control) != old.control);
11819
11820	if(vcpu->pre_pcpu != -1) {
11821	spin_lock_irqsave(
11822	&per_cpu(blocked_vcpu_on_cpu_lock,
11823	vcpu->pre_pcpu), flags);
11824	list_del(&vcpu->blocked_vcpu_list);
11825	spin_unlock_irqrestore(
11826	&per_cpu(blocked_vcpu_on_cpu_lock,
11827	vcpu->pre_pcpu), flags);
11828	vcpu->pre_pcpu = -1;
11829	}
11830	}	11834	}
11831		11835
11832	static void vmx_post_block(struct kvm_vcpu *vcpu)	11836	static void vmx_post_block(struct kvm_vcpu *vcpu)
@@ -11911,12 +11915,8 @@ static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, · 78 unmodified lines
11911		11915
11912	if (set)	11916	if (set)
11913	ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);	11917	ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11914	else {	11918	else
11915	/* suppress notification event before unposting */
11916	pi_set_sn(vcpu_to_pi_desc(vcpu));
11917	ret = irq_set_vcpu_affinity(host_irq, NULL);	11919	ret = irq_set_vcpu_affinity(host_irq, NULL);
11918	pi_clear_sn(vcpu_to_pi_desc(vcpu));
11919	}
11920		11920
11921	if (ret < 0) {	11921	if (ret < 0) {
11922	printk(KERN_INFO "%s: failed to update PI IRTE\n",	11922	printk(KERN_INFO "%s: failed to update PI IRTE\n",

arch/x86/kvm/x86.c+1−1

@@ -7225,7 +7225,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu vcpu, struct kvm_run kvm_run) · 7224 unmodified lines
7225	int r;	7225	int r;
7226	sigset_t sigsaved;	7226	sigset_t sigsaved;
7227		7227
7228	fpu__activate_curr(fpu);	7228	fpu__initialize(fpu);
7229		7229
7230	if (vcpu->sigset_active)	7230	if (vcpu->sigset_active)
7231	sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);	7231	sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);

arch/x86/math-emu/fpu_entry.c+1−1

@@ -114,7 +114,7 @@ void math_emulate(struct math_emu_info *info) · 113 unmodified lines
114	struct desc_struct code_descriptor;	114	struct desc_struct code_descriptor;
115	struct fpu *fpu = &current->thread.fpu;	115	struct fpu *fpu = &current->thread.fpu;
116		116
117	fpu__activate_curr(fpu);	117	fpu__initialize(fpu);
118		118
119	#ifdef RE_ENTRANT_CHECKING	119	#ifdef RE_ENTRANT_CHECKING
120	if (emulating) {	120	if (emulating) {

arch/x86/mm/extable.c+24−0

@@ -2,6 +2,7 @@ · 1 unmodified line
2	#include <linux/uaccess.h>	2	#include <linux/uaccess.h>
3	#include <linux/sched/debug.h>	3	#include <linux/sched/debug.h>
4		4
		5	#include <asm/fpu/internal.h>
5	#include <asm/traps.h>	6	#include <asm/traps.h>
6	#include <asm/kdebug.h>	7	#include <asm/kdebug.h>
7		8
@@ -78,6 +79,29 @@ bool ex_handler_refcount(const struct exception_table_entry *fixup, · 70 unmodified lines
78	}	79	}
79	EXPORT_SYMBOL_GPL(ex_handler_refcount);	80	EXPORT_SYMBOL_GPL(ex_handler_refcount);
80		81
		82	/*
		83	* Handler for when we fail to restore a task's FPU state. We should never get
		84	* here because the FPU state of a task using the FPU (task->thread.fpu.state)
		85	* should always be valid. However, past bugs have allowed userspace to set
		86	* reserved bits in the XSAVE area using PTRACE_SETREGSET or sys_rt_sigreturn().
		87	* These caused XRSTOR to fail when switching to the task, leaking the FPU
		88	* registers of the task previously executing on the CPU. Mitigate this class
		89	* of vulnerability by restoring from the initial state (essentially, zeroing
		90	* out all the FPU registers) if we can't restore from the task's FPU state.
		91	*/
		92	bool ex_handler_fprestore(const struct exception_table_entry *fixup,
		93	struct pt_regs *regs, int trapnr)
		94	{
		95	regs->ip = ex_fixup_addr(fixup);
		96
		97	WARN_ONCE(1, "Bad FPU state detected at %pB, reinitializing FPU registers.",
		98	(void *)instruction_pointer(regs));
		99
		100	__copy_kernel_to_fpregs(&init_fpstate, -1);
		101	return true;
		102	}
		103	EXPORT_SYMBOL_GPL(ex_handler_fprestore);
		104
81	bool ex_handler_ext(const struct exception_table_entry *fixup,	105	bool ex_handler_ext(const struct exception_table_entry *fixup,
82	struct pt_regs *regs, int trapnr)	106	struct pt_regs *regs, int trapnr)
83	{	107	{

arch/x86/mm/fault.c+25−25

  * 6. T1   : reaches here, sees vma_pkey(vma)=5, when we really
  *	     faulted on a pte with its pkey=4.
  */
-static void fill_sig_info_pkey(int si_code, siginfo_t *info,
+static void fill_sig_info_pkey(int si_code, siginfo_t *info, u32 *pkey)
-		struct vm_area_struct *vma)
 {
 	/* This is effectively an #ifdef */
 	if (!boot_cpu_has(X86_FEATURE_OSPKE))
 	 * valid VMA, so we should never reach this without a
 	 * valid VMA.
 	 */
-	if (!vma) {
+	if (!pkey) {
 		WARN_ONCE(1, "PKU fault with no VMA passed in");
 		info->si_pkey = 0;
 		return;
 	 * absolutely guranteed to be 100% accurate because of
 	 * the race explained above.
 	 */
-	info->si_pkey = vma_pkey(vma);
+	info->si_pkey = *pkey;
 }
 static void
 force_sig_info_fault(int si_signo, int si_code, unsigned long address,
-		     struct task_struct *tsk, struct vm_area_struct *vma,
+		     struct task_struct *tsk, u32 *pkey, int fault)
-		     int fault)
 {
 	unsigned lsb = 0;
 	siginfo_t info;
 		lsb = PAGE_SHIFT;
 	info.si_addr_lsb = lsb;
-	fill_sig_info_pkey(si_code, &info, vma);
+	fill_sig_info_pkey(si_code, &info, pkey);
 	force_sig_info(si_signo, &info, tsk);
 }
 	struct task_struct *tsk = current;
 	unsigned long flags;
 	int sig;
-	/* No context means no VMA to pass down */
-	struct vm_area_struct *vma = NULL;
 	/* Are we prepared to handle this kernel fault? */
 	if (fixup_exception(regs, X86_TRAP_PF)) {
 			/* XXX: hwpoison faults will set the wrong code. */
 			force_sig_info_fault(signal, si_code, address,
-					     tsk, vma, 0);
+					     tsk, NULL, 0);
 		}
 		/*
 	if (is_vmalloc_addr((void *)address) &&
 	    (((unsigned long)tsk->stack - 1 - address < PAGE_SIZE) ||
 	     address - ((unsigned long)tsk->stack + THREAD_SIZE) < PAGE_SIZE)) {
-		register void *__sp asm("rsp");
 		unsigned long stack = this_cpu_read(orig_ist.ist[DOUBLEFAULT_STACK]) - sizeof(void *);
 		/*
 		 * We're likely to be running with very little stack space
 		asm volatile ("movq %[stack], %%rsp\n\t"
 			      "call handle_stack_overflow\n\t"
 			      "1: jmp 1b"
-			      : "+r" (__sp)
+			      : ASM_CALL_CONSTRAINT
 			      : "D" ("kernel stack overflow (page fault)"),
 				"S" (regs), "d" (address),
 				[stack] "rm" (stack));
 static void
 __bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code,
-		       unsigned long address, struct vm_area_struct *vma,
+		       unsigned long address, u32 *pkey, int si_code)
-		       int si_code)
 {
 	struct task_struct *tsk = current;
 		tsk->thread.error_code	= error_code;
 		tsk->thread.trap_nr	= X86_TRAP_PF;
-		force_sig_info_fault(SIGSEGV, si_code, address, tsk, vma, 0);
+		force_sig_info_fault(SIGSEGV, si_code, address, tsk, pkey, 0);
 		return;
 	}
 static noinline void
 bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code,
-		     unsigned long address, struct vm_area_struct *vma)
+		     unsigned long address, u32 *pkey)
 {
-	__bad_area_nosemaphore(regs, error_code, address, vma, SEGV_MAPERR);
+	__bad_area_nosemaphore(regs, error_code, address, pkey, SEGV_MAPERR);
 }
 static void
 	   unsigned long address,  struct vm_area_struct *vma, int si_code)
 {
 	struct mm_struct *mm = current->mm;
+	u32 pkey;
+	if (vma)
+		pkey = vma_pkey(vma);
 	/*
 	 * Something tried to access memory that isn't in our memory map..
 	 */
 	up_read(&mm->mmap_sem);
-	__bad_area_nosemaphore(regs, error_code, address, vma, si_code);
+	__bad_area_nosemaphore(regs, error_code, address,
+			       (vma) ? &pkey : NULL, si_code);
 }
 static noinline void
 static void
 do_sigbus(struct pt_regs *regs, unsigned long error_code, unsigned long address,
-	  struct vm_area_struct *vma, unsigned int fault)
+	  u32 *pkey, unsigned int fault)
 {
 	struct task_struct *tsk = current;
 	int code = BUS_ADRERR;
 		code = BUS_MCEERR_AR;
 	}
 #endif
-	force_sig_info_fault(SIGBUS, code, address, tsk, vma, fault);
+	force_sig_info_fault(SIGBUS, code, address, tsk, pkey, fault);
 }
 static noinline void
 mm_fault_error(struct pt_regs *regs, unsigned long error_code,
-	       unsigned long address, struct vm_area_struct *vma,
+	       unsigned long address, u32 *pkey, unsigned int fault)
-	       unsigned int fault)
 {
 	if (fatal_signal_pending(current) && !(error_code & PF_USER)) {
 		no_context(regs, error_code, address, 0, 0);
 	} else {
 		if (fault & (VM_FAULT_SIGBUS|VM_FAULT_HWPOISON|
 			     VM_FAULT_HWPOISON_LARGE))
-			do_sigbus(regs, error_code, address, vma, fault);
+			do_sigbus(regs, error_code, address, pkey, fault);
 		else if (fault & VM_FAULT_SIGSEGV)
-			bad_area_nosemaphore(regs, error_code, address, vma);
+			bad_area_nosemaphore(regs, error_code, address, pkey);
 		else
 			BUG();
 	}
 	struct mm_struct *mm;
 	int fault, major = 0;
 	unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
+	u32 pkey;
 	tsk = current;
 	mm = tsk->mm;
 		return;
 	}
+	pkey = vma_pkey(vma);
 	up_read(&mm->mmap_sem);
 	if (unlikely(fault & VM_FAULT_ERROR)) {
-		mm_fault_error(regs, error_code, address, vma, fault);
+		mm_fault_error(regs, error_code, address, &pkey, fault);
 		return;
 	}

arch/x86/mm/mem_encrypt.c+2−0

@@ -10,6 +10,8 @@ · 9 unmodified lines
10	* published by the Free Software Foundation.	10	* published by the Free Software Foundation.
11	*/	11	*/
12		12
		13	#define DISABLE_BRANCH_PROFILING
		14
13	#include <linux/linkage.h>	15	#include <linux/linkage.h>
14	#include <linux/init.h>	16	#include <linux/init.h>
15	#include <linux/mm.h>	17	#include <linux/mm.h>

arch/x86/mm/pkeys.c+1−2

 #include <asm/cpufeature.h>             /* boot_cpu_has, ...            */
 #include <asm/mmu_context.h>            /* vma_pkey()                   */
-#include <asm/fpu/internal.h>           /* fpregs_active()              */
 int __execute_only_pkey(struct mm_struct *mm)
 {
 	 */
 	preempt_disable();
 	if (!need_to_set_mm_pkey &&
-	    fpregs_active() &&
+	    current->thread.fpu.initialized &&
 	    !__pkru_allows_read(read_pkru(), execute_only_pkey)) {
 		preempt_enable();
 		return execute_only_pkey;

arch/x86/mm/tlb.c+6−7

 	 * isn't free.
 	 */
 #ifdef CONFIG_DEBUG_VM
-	if (WARN_ON_ONCE(__read_cr3() !=
+	if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev, prev_asid))) {
-			 (__sme_pa(real_prev->pgd) | prev_asid))) {
 		/*
 		 * If we were to BUG here, we'd be very likely to kill
 		 * the system so hard that we don't see the call trace.
 			 */
 			this_cpu_write(cpu_tlbstate.ctxs[prev_asid].tlb_gen,
 				       next_tlb_gen);
-			write_cr3(__sme_pa(next->pgd) | prev_asid);
+			write_cr3(build_cr3(next, prev_asid));
 			trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH,
 					TLB_FLUSH_ALL);
 		}
 			 * mapped in the new pgd, we'll double-fault.  Forcibly
 			 * map it.
 			 */
-			unsigned int index = pgd_index(current_stack_pointer());
+			unsigned int index = pgd_index(current_stack_pointer);
 			pgd_t *pgd = next->pgd + index;
 			if (unlikely(pgd_none(*pgd)))
 		if (need_flush) {
 			this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
 			this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
-			write_cr3(__sme_pa(next->pgd) | new_asid);
+			write_cr3(build_cr3(next, new_asid));
 			trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH,
 					TLB_FLUSH_ALL);
 		} else {
 			/* The new ASID is already up to date. */
-			write_cr3(__sme_pa(next->pgd) | new_asid | CR3_NOFLUSH);
+			write_cr3(build_cr3_noflush(next, new_asid));
 			trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0);
 		}
 		!(cr4_read_shadow() & X86_CR4_PCIDE));
 	/* Force ASID 0 and force a TLB flush. */
-	write_cr3(cr3 & ~CR3_PCID_MASK);
+	write_cr3(build_cr3(mm, 0));
 	/* Reinitialize tlbstate. */
 	this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);

arch/x86/net/bpf_jit_comp.c+2−2

 	/* if (index >= array->map.max_entries)
 	 *   goto out;
 	 */
-	EMIT4(0x48, 0x8B, 0x46,                   /* mov rax, qword ptr [rsi + 16] */
+	EMIT2(0x89, 0xD2);                        /* mov edx, edx */
+	EMIT3(0x39, 0x56,                         /* cmp dword ptr [rsi + 16], edx */
 	      offsetof(struct bpf_array, map.max_entries));
-	EMIT3(0x48, 0x39, 0xD0);                  /* cmp rax, rdx */
 #define OFFSET1 43 /* number of bytes to jump */
 	EMIT2(X86_JBE, OFFSET1);                  /* jbe out */
 	label1 = cnt;

arch/x86/xen/mmu_pv.c+5−10

 	 * from _brk_limit way up to the max_pfn_mapped (which is the end of
 	 * the ramdisk). We continue on, erasing PMD entries that point to page
 	 * tables - do note that they are accessible at this stage via __va.
-	 * For good measure we also round up to the PMD - which means that if
+	 * As Xen is aligning the memory end to a 4MB boundary, for good
+	 * measure we also round up to PMD_SIZE * 2 - which means that if
 	 * anybody is using __ka address to the initial boot-stack - and try
 	 * to use it - they are going to crash. The xen_start_info has been
 	 * taken care of already in xen_setup_kernel_pagetable. */
 	addr = xen_start_info->pt_base;
-	size = roundup(xen_start_info->nr_pt_frames * PAGE_SIZE, PMD_SIZE);
+	size = xen_start_info->nr_pt_frames * PAGE_SIZE;
-	xen_cleanhighmap(addr, addr + size);
+	xen_cleanhighmap(addr, roundup(addr + size, PMD_SIZE * 2));
 	xen_start_info->pt_base = (unsigned long)__va(__pa(xen_start_info->pt_base));
-#ifdef DEBUG
-	/* This is superfluous and is not necessary, but you know what
-	 * lets do it. The MODULES_VADDR -> MODULES_END should be clear of
-	 * anything at this stage. */
-	xen_cleanhighmap(MODULES_VADDR, roundup(MODULES_VADDR, PUD_SIZE) - 1);
-#endif
 }
 #endif
  * not the first page table in the page table pool.
  * Iterate through the initial page tables to find the real page table base.
  */
-static phys_addr_t xen_find_pt_base(pmd_t *pmd)
+static phys_addr_t __init xen_find_pt_base(pmd_t *pmd)
 {
 	phys_addr_t pt_base, paddr;
 	unsigned pmdidx;

arch/xtensa/include/asm/processor.h+0−5

 /* Free all resources held by a thread. */
 #define release_thread(thread) do { } while(0)
-/* Copy and release all segment info associated with a VM */
-#define copy_segments(p, mm)	do { } while(0)
-#define release_segments(mm)	do { } while(0)
-#define forget_segments()	do { } while (0)
 extern unsigned long get_wchan(struct task_struct *p);
 #define KSTK_EIP(tsk)		(task_pt_regs(tsk)->pc)

block/blk-core.c+3−0

@@ -854,6 +854,9 @@ struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) · 853 unmodified lines
854		854
855	kobject_init(&q->kobj, &blk_queue_ktype);	855	kobject_init(&q->kobj, &blk_queue_ktype);
856		856
		857	#ifdef CONFIG_BLK_DEV_IO_TRACE
		858	mutex_init(&q->blk_trace_mutex);
		859	#endif
857	mutex_init(&q->sysfs_lock);	860	mutex_init(&q->sysfs_lock);
858	spin_lock_init(&q->__queue_lock);	861	spin_lock_init(&q->__queue_lock);
859		862

block/blk-mq-debugfs.c+5−1

 		goto err;
 	/*
-	 * blk_mq_init_hctx() attempted to do this already, but q->debugfs_dir
+	 * blk_mq_init_sched() attempted to do this already, but q->debugfs_dir
 	 * didn't exist yet (because we don't know what to name the directory
 	 * until the queue is registered to a gendisk).
 	 */
+	if (q->elevator && !q->sched_debugfs_dir)
+		blk_mq_debugfs_register_sched(q);
+	/* Similarly, blk_mq_init_hctx() couldn't do this previously. */
 	queue_for_each_hw_ctx(q, hctx, i) {
 		if (!hctx->debugfs_dir && blk_mq_debugfs_register_hctx(q, hctx))
 			goto err;

block/blk-throttle.c+2−2

@@ -1911,11 +1911,11 @@ static void throtl_upgrade_state(struct throtl_data *td) · 1910 unmodified lines
1911		1911
1912	tg->disptime = jiffies - 1;	1912	tg->disptime = jiffies - 1;
1913	throtl_select_dispatch(sq);	1913	throtl_select_dispatch(sq);
1914	throtl_schedule_next_dispatch(sq, false);	1914	throtl_schedule_next_dispatch(sq, true);
1915	}	1915	}
1916	rcu_read_unlock();	1916	rcu_read_unlock();
1917	throtl_select_dispatch(&td->service_queue);	1917	throtl_select_dispatch(&td->service_queue);
1918	throtl_schedule_next_dispatch(&td->service_queue, false);	1918	throtl_schedule_next_dispatch(&td->service_queue, true);
1919	queue_work(kthrotld_workqueue, &td->dispatch_work);	1919	queue_work(kthrotld_workqueue, &td->dispatch_work);
1920	}	1920	}
1921		1921

block/bsg-lib.c+21−7

 failjob_rls_rqst_payload:
 	kfree(job->request_payload.sg_list);
 failjob_rls_job:
-	kfree(job);
 	return -ENOMEM;
 }
 	struct bsg_job *job = blk_mq_rq_to_pdu(req);
 	struct scsi_request *sreq = &job->sreq;
+	/* called right after the request is allocated for the request_queue */
+	sreq->sense = kzalloc(SCSI_SENSE_BUFFERSIZE, gfp);
+	if (!sreq->sense)
+		return -ENOMEM;
+	return 0;
+}
+static void bsg_initialize_rq(struct request *req)
+{
+	struct bsg_job *job = blk_mq_rq_to_pdu(req);
+	struct scsi_request *sreq = &job->sreq;
+	void *sense = sreq->sense;
+	/* called right before the request is given to the request_queue user */
 	memset(job, 0, sizeof(*job));
 	scsi_req_init(sreq);
+	sreq->sense = sense;
 	sreq->sense_len = SCSI_SENSE_BUFFERSIZE;
-	sreq->sense = kzalloc(sreq->sense_len, gfp);
-	if (!sreq->sense)
-		return -ENOMEM;
 	job->req = req;
-	job->reply = sreq->sense;
+	job->reply = sense;
 	job->reply_len = sreq->sense_len;
 	job->dd_data = job + 1;
-	return 0;
 }
 static void bsg_exit_rq(struct request_queue *q, struct request *req)
 	q->cmd_size = sizeof(struct bsg_job) + dd_job_size;
 	q->init_rq_fn = bsg_init_rq;
 	q->exit_rq_fn = bsg_exit_rq;
+	q->initialize_rq_fn = bsg_initialize_rq;
 	q->request_fn = bsg_request_fn;
 	ret = blk_init_allocated_queue(q);

block/partition-generic.c+1−1

@@ -112,7 +112,7 @@ ssize_t part_stat_show(struct device *dev, · 111 unmodified lines
112	struct device_attribute attr, char buf)	112	struct device_attribute attr, char buf)
113	{	113	{
114	struct hd_struct *p = dev_to_part(dev);	114	struct hd_struct *p = dev_to_part(dev);
115	struct request_queue *q = dev_to_disk(dev)->queue;	115	struct request_queue *q = part_to_disk(p)->queue;
116	unsigned int inflight[2];	116	unsigned int inflight[2];
117	int cpu;	117	int cpu;
118		118

crypto/af_alg.c+2−2

@@ -619,14 +619,14 @@ void af_alg_pull_tsgl(struct sock sk, size_t used, struct scatterlist dst, · 618 unmodified lines
619	struct af_alg_ctx *ctx = ask->private;	619	struct af_alg_ctx *ctx = ask->private;
620	struct af_alg_tsgl *sgl;	620	struct af_alg_tsgl *sgl;
621	struct scatterlist *sg;	621	struct scatterlist *sg;
622	unsigned int i, j;	622	unsigned int i, j = 0;
623		623
624	while (!list_empty(&ctx->tsgl_list)) {	624	while (!list_empty(&ctx->tsgl_list)) {
625	sgl = list_first_entry(&ctx->tsgl_list, struct af_alg_tsgl,	625	sgl = list_first_entry(&ctx->tsgl_list, struct af_alg_tsgl,
626	list);	626	list);
627	sg = sgl->sg;	627	sg = sgl->sg;
628		628
629	for (i = 0, j = 0; i < sgl->cur; i++) {	629	for (i = 0; i < sgl->cur; i++) {
630	size_t plen = min_t(size_t, used, sg[i].length);	630	size_t plen = min_t(size_t, used, sg[i].length);
631	struct page *page = sg_page(sg + i);	631	struct page *page = sg_page(sg + i);
632		632

crypto/drbg.c+4−4

@@ -1133,10 +1133,10 @@ static inline void drbg_dealloc_state(struct drbg_state *drbg) · 1132 unmodified lines
1133	{	1133	{
1134	if (!drbg)	1134	if (!drbg)
1135	return;	1135	return;
1136	kzfree(drbg->V);	1136	kzfree(drbg->Vbuf);
1137	drbg->Vbuf = NULL;	1137	drbg->V = NULL;
1138	kzfree(drbg->C);	1138	kzfree(drbg->Cbuf);
1139	drbg->Cbuf = NULL;	1139	drbg->C = NULL;
1140	kzfree(drbg->scratchpadbuf);	1140	kzfree(drbg->scratchpadbuf);
1141	drbg->scratchpadbuf = NULL;	1141	drbg->scratchpadbuf = NULL;
1142	drbg->reseed_ctr = 0;	1142	drbg->reseed_ctr = 0;

drivers/acpi/acpi_watchdog.c+1−1

@@ -66,7 +66,7 @@ void __init acpi_watchdog_init(void) · 65 unmodified lines
66	for (i = 0; i < wdat->entries; i++) {	66	for (i = 0; i < wdat->entries; i++) {
67	const struct acpi_generic_address *gas;	67	const struct acpi_generic_address *gas;
68	struct resource_entry *rentry;	68	struct resource_entry *rentry;
69	struct resource res;	69	struct resource res = {};
70	bool found;	70	bool found;
71		71
72	gas = &entries[i].register_region;	72	gas = &entries[i].register_region;

drivers/acpi/apei/ghes.c+9−7

@@ -743,17 +743,19 @@ static int ghes_proc(struct ghes *ghes) · 742 unmodified lines
743	}	743	}
744	ghes_do_proc(ghes, ghes->estatus);	744	ghes_do_proc(ghes, ghes->estatus);
745		745
		746	out:
		747	ghes_clear_estatus(ghes);
		748
		749	if (rc == -ENOENT)
		750	return rc;
		751
746	/*	752	/*
747	* GHESv2 type HEST entries introduce support for error acknowledgment,	753	* GHESv2 type HEST entries introduce support for error acknowledgment,
748	* so only acknowledge the error if this support is present.	754	* so only acknowledge the error if this support is present.
749	*/	755	*/
750	if (is_hest_type_generic_v2(ghes)) {	756	if (is_hest_type_generic_v2(ghes))
751	rc = ghes_ack_error(ghes->generic_v2);	757	return ghes_ack_error(ghes->generic_v2);
752	if (rc)	758
753	return rc;
754	}
755	out:
756	ghes_clear_estatus(ghes);
757	return rc;	759	return rc;
758	}	760	}
759		761

drivers/acpi/arm64/iort.c+35−0

@@ -1178,12 +1178,44 @@ dev_put: · 1177 unmodified lines
1178	return ret;	1178	return ret;
1179	}	1179	}
1180		1180
		1181	static bool __init iort_enable_acs(struct acpi_iort_node *iort_node)
		1182	{
		1183	if (iort_node->type == ACPI_IORT_NODE_PCI_ROOT_COMPLEX) {
		1184	struct acpi_iort_node *parent;
		1185	struct acpi_iort_id_mapping *map;
		1186	int i;
		1187
		1188	map = ACPI_ADD_PTR(struct acpi_iort_id_mapping, iort_node,
		1189	iort_node->mapping_offset);
		1190
		1191	for (i = 0; i < iort_node->mapping_count; i++, map++) {
		1192	if (!map->output_reference)
		1193	continue;
		1194
		1195	parent = ACPI_ADD_PTR(struct acpi_iort_node,
		1196	iort_table, map->output_reference);
		1197	/*
		1198	* If we detect a RC->SMMU mapping, make sure
		1199	* we enable ACS on the system.
		1200	*/
		1201	if ((parent->type == ACPI_IORT_NODE_SMMU) \|\|
		1202	(parent->type == ACPI_IORT_NODE_SMMU_V3)) {
		1203	pci_request_acs();
		1204	return true;
		1205	}
		1206	}
		1207	}
		1208
		1209	return false;
		1210	}
		1211
1181	static void __init iort_init_platform_devices(void)	1212	static void __init iort_init_platform_devices(void)
1182	{	1213	{
1183	struct acpi_iort_node iort_node, iort_end;	1214	struct acpi_iort_node iort_node, iort_end;
1184	struct acpi_table_iort *iort;	1215	struct acpi_table_iort *iort;
1185	struct fwnode_handle *fwnode;	1216	struct fwnode_handle *fwnode;
1186	int i, ret;	1217	int i, ret;
		1218	bool acs_enabled = false;
1187		1219
1188	/*	1220	/*
1189	* iort_table and iort both point to the start of IORT table, but	1221	* iort_table and iort both point to the start of IORT table, but
@@ -1203,6 +1235,9 @@ static void __init iort_init_platform_devices(void) · 13 unmodified lines
1203	return;	1235	return;
1204	}	1236	}
1205		1237
		1238	if (!acs_enabled)
		1239	acs_enabled = iort_enable_acs(iort_node);
		1240
1206	if ((iort_node->type == ACPI_IORT_NODE_SMMU) \|\|	1241	if ((iort_node->type == ACPI_IORT_NODE_SMMU) \|\|
1207	(iort_node->type == ACPI_IORT_NODE_SMMU_V3)) {	1242	(iort_node->type == ACPI_IORT_NODE_SMMU_V3)) {
1208		1243

drivers/acpi/property.c+19−5

 					    struct fwnode_handle *child)
 {
 	const struct acpi_device *adev = to_acpi_device_node(fwnode);
-	struct acpi_device *child_adev = NULL;
 	const struct list_head *head;
 	struct list_head *next;
 	if (!child || is_acpi_device_node(child)) {
+		struct acpi_device *child_adev;
 		if (adev)
 			head = &adev->children;
 		else
 			goto nondev;
 		if (child) {
-			child_adev = to_acpi_device_node(child);
+			adev = to_acpi_device_node(child);
-			next = child_adev->node.next;
+			next = adev->node.next;
 			if (next == head) {
 				child = NULL;
 				goto nondev;
 		const struct acpi_data_node *data = to_acpi_data_node(fwnode);
 		struct acpi_data_node *dn;
-		if (child_adev)
+		if (adev)
-			head = &child_adev->data.subnodes;
+			head = &adev->data.subnodes;
 		else if (data)
 			head = &data->data.subnodes;
 		else
 DECLARE_ACPI_FWNODE_OPS(acpi_device_fwnode_ops);
 DECLARE_ACPI_FWNODE_OPS(acpi_data_fwnode_ops);
 const struct fwnode_operations acpi_static_fwnode_ops;
+bool is_acpi_device_node(const struct fwnode_handle *fwnode)
+{
+	return !IS_ERR_OR_NULL(fwnode) &&
+		fwnode->ops == &acpi_device_fwnode_ops;
+}
+EXPORT_SYMBOL(is_acpi_device_node);
+bool is_acpi_data_node(const struct fwnode_handle *fwnode)
+{
+	return !IS_ERR_OR_NULL(fwnode) && fwnode->ops == &acpi_data_fwnode_ops;
+}
+EXPORT_SYMBOL(is_acpi_data_node);

drivers/android/binder.c+4−4

 				       debug_id, (u64)fda->num_fds);
 				continue;
 			}
-			fd_array = (u32 *)(parent_buffer + fda->parent_offset);
+			fd_array = (u32 *)(parent_buffer + (uintptr_t)fda->parent_offset);
 			for (fd_index = 0; fd_index < fda->num_fds; fd_index++)
 				task_close_fd(proc, fd_array[fd_index]);
 		} break;
 			     (u64)node->ptr);
 		binder_node_unlock(node);
 	} else {
-		int ret;
 		struct binder_ref_data dest_rdata;
 		binder_node_unlock(node);
 	 */
 	parent_buffer = parent->buffer -
 		binder_alloc_get_user_buffer_offset(&target_proc->alloc);
-	fd_array = (u32 *)(parent_buffer + fda->parent_offset);
+	fd_array = (u32 *)(parent_buffer + (uintptr_t)fda->parent_offset);
 	if (!IS_ALIGNED((unsigned long)fd_array, sizeof(u32))) {
 		binder_user_error("%d:%d parent offset not aligned correctly.\n",
 				  proc->pid, thread->pid);
 				  proc->pid, thread->pid);
 		return -EINVAL;
 	}
-	parent_buffer = (u8 *)(parent->buffer -
+	parent_buffer = (u8 *)((uintptr_t)parent->buffer -
 			binder_alloc_get_user_buffer_offset(
 				&target_proc->alloc));
 	*(binder_uintptr_t *)(parent_buffer + bp->parent_offset) = bp->buffer;
 err_dead_proc_or_thread:
 	return_error = BR_DEAD_REPLY;
 	return_error_line = __LINE__;
+	binder_dequeue_work(proc, tcomplete);
 err_translate_failed:
 err_bad_object_type:
 err_bad_offset:

drivers/android/binder_alloc.c+12−6

 	struct binder_alloc *alloc;
 	uintptr_t page_addr;
 	size_t index;
+	struct vm_area_struct *vma;
 	alloc = page->alloc;
 	if (!mutex_trylock(&alloc->mutex))
 	index = page - alloc->pages;
 	page_addr = (uintptr_t)alloc->buffer + index * PAGE_SIZE;
-	if (alloc->vma) {
+	vma = alloc->vma;
+	if (vma) {
 		mm = get_task_mm(alloc->tsk);
 		if (!mm)
 			goto err_get_task_mm_failed;
 		if (!down_write_trylock(&mm->mmap_sem))
 			goto err_down_write_mmap_sem_failed;
+	}
+	list_lru_isolate(lru, item);
+	spin_unlock(lock);
+	if (vma) {
 		trace_binder_unmap_user_start(alloc, index);
-		zap_page_range(alloc->vma,
+		zap_page_range(vma,
 			       page_addr + alloc->user_buffer_offset,
 			       PAGE_SIZE);
 	trace_binder_unmap_kernel_end(alloc, index);
-	list_lru_isolate(lru, item);
+	spin_lock(lock);
 	mutex_unlock(&alloc->mutex);
-	return LRU_REMOVED;
+	return LRU_REMOVED_RETRY;
 err_down_write_mmap_sem_failed:
-	mmput(mm);
+	mmput_async(mm);
 err_get_task_mm_failed:
 err_page_already_freed:
 	mutex_unlock(&alloc->mutex);

drivers/ata/ahci.c+4−1

 static int ahci_pci_reset_controller(struct ata_host *host)
 {
 	struct pci_dev *pdev = to_pci_dev(host->dev);
+	int rc;
-	ahci_reset_controller(host);
+	rc = ahci_reset_controller(host);
+	if (rc)
+		return rc;
 	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 		struct ahci_host_priv *hpriv = host->private_data;

drivers/ata/ata_piix.c+1−0

@@ -492,6 +492,7 @@ static const struct ich_laptop ich_laptop[] = { · 491 unmodified lines
492	{ 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */	492	{ 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
493	{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */	493	{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
494	{ 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */	494	{ 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
		495	{ 0x24CA, 0x10CF, 0x11AB }, /* ICH4M on Fujitsu-Siemens Lifebook S6120 */
495	{ 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */	496	{ 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
496	{ 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */	497	{ 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
497	{ 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */	498	{ 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */

drivers/ata/libata-core.c+10−10

@@ -3234,19 +3234,19 @@ static const struct ata_timing ata_timing[] = { · 3233 unmodified lines
3234	};	3234	};
3235		3235
3236	#define ENOUGH(v, unit) (((v)-1)/(unit)+1)	3236	#define ENOUGH(v, unit) (((v)-1)/(unit)+1)
3237	#define EZ(v, unit) ((v)?ENOUGH(v, unit):0)	3237	#define EZ(v, unit) ((v)?ENOUGH(((v) * 1000), unit):0)
3238		3238
3239	static void ata_timing_quantize(const struct ata_timing t, struct ata_timing q, int T, int UT)	3239	static void ata_timing_quantize(const struct ata_timing t, struct ata_timing q, int T, int UT)
3240	{	3240	{
3241	q->setup = EZ(t->setup * 1000, T);	3241	q->setup = EZ(t->setup, T);
3242	q->act8b = EZ(t->act8b * 1000, T);	3242	q->act8b = EZ(t->act8b, T);
3243	q->rec8b = EZ(t->rec8b * 1000, T);	3243	q->rec8b = EZ(t->rec8b, T);
3244	q->cyc8b = EZ(t->cyc8b * 1000, T);	3244	q->cyc8b = EZ(t->cyc8b, T);
3245	q->active = EZ(t->active * 1000, T);	3245	q->active = EZ(t->active, T);
3246	q->recover = EZ(t->recover * 1000, T);	3246	q->recover = EZ(t->recover, T);
3247	q->dmack_hold = EZ(t->dmack_hold * 1000, T);	3247	q->dmack_hold = EZ(t->dmack_hold, T);
3248	q->cycle = EZ(t->cycle * 1000, T);	3248	q->cycle = EZ(t->cycle, T);
3249	q->udma = EZ(t->udma * 1000, UT);	3249	q->udma = EZ(t->udma, UT);
3250	}	3250	}
3251		3251
3252	void ata_timing_merge(const struct ata_timing a, const struct ata_timing b,	3252	void ata_timing_merge(const struct ata_timing a, const struct ata_timing b,

drivers/auxdisplay/charlcd.c+9−2

 static int charlcd_open(struct inode *inode, struct file *file)
 {
 	struct charlcd_priv *priv = to_priv(the_charlcd);
+	int ret;
+	ret = -EBUSY;
 	if (!atomic_dec_and_test(&charlcd_available))
-		return -EBUSY;	/* open only once at a time */
+		goto fail;	/* open only once at a time */
+	ret = -EPERM;
 	if (file->f_mode & FMODE_READ)	/* device is write-only */
-		return -EPERM;
+		goto fail;
 	if (priv->must_clear) {
 		charlcd_clear_display(&priv->lcd);
 		priv->must_clear = false;
 	}
 	return nonseekable_open(inode, file);
+ fail:
+	atomic_inc(&charlcd_available);
+	return ret;
 }
 static int charlcd_release(struct inode *inode, struct file *file)

drivers/auxdisplay/panel.c+9−2

 static int keypad_open(struct inode *inode, struct file *file)
 {
+	int ret;
+	ret = -EBUSY;
 	if (!atomic_dec_and_test(&keypad_available))
-		return -EBUSY;	/* open only once at a time */
+		goto fail;	/* open only once at a time */
+	ret = -EPERM;
 	if (file->f_mode & FMODE_WRITE)	/* device is read-only */
-		return -EPERM;
+		goto fail;
 	keypad_buflen = 0;	/* flush the buffer on opening */
 	return 0;
+ fail:
+	atomic_inc(&keypad_available);
+	return ret;
 }
 static int keypad_release(struct inode *inode, struct file *file)

drivers/base/arch_topology.c+6−6

@@ -166,11 +166,11 @@ bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu) · 165 unmodified lines
166	}	166	}
167		167
168	#ifdef CONFIG_CPU_FREQ	168	#ifdef CONFIG_CPU_FREQ
169	static cpumask_var_t cpus_to_visit;	169	static cpumask_var_t cpus_to_visit __initdata;
170	static void parsing_done_workfn(struct work_struct *work);	170	static void __init parsing_done_workfn(struct work_struct *work);
171	static DECLARE_WORK(parsing_done_work, parsing_done_workfn);	171	static __initdata DECLARE_WORK(parsing_done_work, parsing_done_workfn);
172		172
173	static int	173	static int __init
174	init_cpu_capacity_callback(struct notifier_block *nb,	174	init_cpu_capacity_callback(struct notifier_block *nb,
175	unsigned long val,	175	unsigned long val,
176	void *data)	176	void *data)
@@ -206,7 +206,7 @@ init_cpu_capacity_callback(struct notifier_block *nb, · 29 unmodified lines
206	return 0;	206	return 0;
207	}	207	}
208		208
209	static struct notifier_block init_cpu_capacity_notifier = {	209	static struct notifier_block init_cpu_capacity_notifier __initdata = {
210	.notifier_call = init_cpu_capacity_callback,	210	.notifier_call = init_cpu_capacity_callback,
211	};	211	};
212		212
@@ -232,7 +232,7 @@ static int __init register_cpufreq_notifier(void) · 19 unmodified lines
232	}	232	}
233	core_initcall(register_cpufreq_notifier);	233	core_initcall(register_cpufreq_notifier);
234		234
235	static void parsing_done_workfn(struct work_struct *work)	235	static void __init parsing_done_workfn(struct work_struct *work)
236	{	236	{
237	cpufreq_unregister_notifier(&init_cpu_capacity_notifier,	237	cpufreq_unregister_notifier(&init_cpu_capacity_notifier,
238	CPUFREQ_POLICY_NOTIFIER);	238	CPUFREQ_POLICY_NOTIFIER);

drivers/base/dma-coherent.c+9−10

@@ -348,16 +348,15 @@ static int rmem_dma_device_init(struct reserved_mem rmem, struct device dev) · 347 unmodified lines
348	struct dma_coherent_mem *mem = rmem->priv;	348	struct dma_coherent_mem *mem = rmem->priv;
349	int ret;	349	int ret;
350		350
351	if (!mem)	351	if (!mem) {
352	return -ENODEV;	352	ret = dma_init_coherent_memory(rmem->base, rmem->base,
353		353	rmem->size,
354	ret = dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,	354	DMA_MEMORY_EXCLUSIVE, &mem);
355	DMA_MEMORY_EXCLUSIVE, &mem);	355	if (ret) {
356		356	pr_err("Reserved memory: failed to init DMA memory pool at %pa, size %ld MiB\n",
357	if (ret) {	357	&rmem->base, (unsigned long)rmem->size / SZ_1M);
358	pr_err("Reserved memory: failed to init DMA memory pool at %pa, size %ld MiB\n",	358	return ret;
359	&rmem->base, (unsigned long)rmem->size / SZ_1M);	359	}
360	return ret;
361	}	360	}
362	mem->use_dev_dma_pfn_offset = true;	361	mem->use_dev_dma_pfn_offset = true;
363	rmem->priv = mem;	362	rmem->priv = mem;

drivers/base/platform.c+2−1

@@ -868,7 +868,8 @@ static ssize_t driver_override_store(struct device *dev, · 867 unmodified lines
868	struct platform_device *pdev = to_platform_device(dev);	868	struct platform_device *pdev = to_platform_device(dev);
869	char driver_override, old, *cp;	869	char driver_override, old, *cp;
870		870
871	if (count > PATH_MAX)	871	/* We need to keep extra room for a newline */
		872	if (count >= (PAGE_SIZE - 1))
872	return -EINVAL;	873	return -EINVAL;
873		874
874	driver_override = kstrndup(buf, count, GFP_KERNEL);	875	driver_override = kstrndup(buf, count, GFP_KERNEL);

drivers/base/power/main.c+6−3

 {
 	spin_lock_irq(&dev->power.lock);
 	dev->power.no_pm_callbacks =
-		(!dev->bus || pm_ops_is_empty(dev->bus->pm)) &&
+		(!dev->bus || (pm_ops_is_empty(dev->bus->pm) &&
-		(!dev->class || pm_ops_is_empty(dev->class->pm)) &&
+		 !dev->bus->suspend && !dev->bus->resume)) &&
+		(!dev->class || (pm_ops_is_empty(dev->class->pm) &&
+		 !dev->class->suspend && !dev->class->resume)) &&
 		(!dev->type || pm_ops_is_empty(dev->type->pm)) &&
 		(!dev->pm_domain || pm_ops_is_empty(&dev->pm_domain->ops)) &&
-		(!dev->driver || pm_ops_is_empty(dev->driver->pm));
+		(!dev->driver || (pm_ops_is_empty(dev->driver->pm) &&
+		 !dev->driver->suspend && !dev->driver->resume));
 	spin_unlock_irq(&dev->power.lock);
 }

drivers/base/power/opp/core.c+7−0

 	opp->available = availability_req;
+	dev_pm_opp_get(opp);
+	mutex_unlock(&opp_table->lock);
 	/* Notify the change of the OPP availability */
 	if (availability_req)
 		blocking_notifier_call_chain(&opp_table->head, OPP_EVENT_ENABLE,
 		blocking_notifier_call_chain(&opp_table->head,
 					     OPP_EVENT_DISABLE, opp);
+	dev_pm_opp_put(opp);
+	goto put_table;
 unlock:
 	mutex_unlock(&opp_table->lock);
+put_table:
 	dev_pm_opp_put_opp_table(opp_table);
 	return r;
 }

drivers/base/power/qos.c+5−5

@@ -277,11 +277,11 @@ void dev_pm_qos_constraints_destroy(struct device *dev) · 276 unmodified lines
277	mutex_unlock(&dev_pm_qos_sysfs_mtx);	277	mutex_unlock(&dev_pm_qos_sysfs_mtx);
278	}	278	}
279		279
280	static bool dev_pm_qos_invalid_request(struct device *dev,	280	static bool dev_pm_qos_invalid_req_type(struct device *dev,
281	struct dev_pm_qos_request *req)	281	enum dev_pm_qos_req_type type)
282	{	282	{
283	return !req \|\| (req->type == DEV_PM_QOS_LATENCY_TOLERANCE	283	return type == DEV_PM_QOS_LATENCY_TOLERANCE &&
284	&& !dev->power.set_latency_tolerance);	284	!dev->power.set_latency_tolerance;
285	}	285	}
286		286
287	static int __dev_pm_qos_add_request(struct device *dev,	287	static int __dev_pm_qos_add_request(struct device *dev,
@@ -290,7 +290,7 @@ static int __dev_pm_qos_add_request(struct device *dev, · 2 unmodified lines
290	{	290	{
291	int ret = 0;	291	int ret = 0;
292		292
293	if (!dev \|\| dev_pm_qos_invalid_request(dev, req))	293	if (!dev \|\| !req \|\| dev_pm_qos_invalid_req_type(dev, type))
294	return -EINVAL;	294	return -EINVAL;
295		295
296	if (WARN(dev_pm_qos_request_active(req),	296	if (WARN(dev_pm_qos_request_active(req),

drivers/block/Kconfig+1−1

@@ -17,7 +17,7 @@ if BLK_DEV · 16 unmodified lines
17		17
18	config BLK_DEV_NULL_BLK	18	config BLK_DEV_NULL_BLK
19	tristate "Null test block driver"	19	tristate "Null test block driver"
20	depends on CONFIGFS_FS	20	select CONFIGFS_FS
21		21
22	config BLK_DEV_FD	22	config BLK_DEV_FD
23	tristate "Normal floppy disk support"	23	tristate "Normal floppy disk support"

drivers/block/brd.c+1−1

@@ -342,7 +342,7 @@ static long __brd_direct_access(struct brd_device *brd, pgoff_t pgoff, · 341 unmodified lines
342		342
343	if (!brd)	343	if (!brd)
344	return -ENODEV;	344	return -ENODEV;
345	page = brd_insert_page(brd, PFN_PHYS(pgoff) / 512);	345	page = brd_insert_page(brd, (sector_t)pgoff << PAGE_SECTORS_SHIFT);
346	if (!page)	346	if (!page)
347	return -ENOSPC;	347	return -ENOSPC;
348	*kaddr = page_address(page);	348	*kaddr = page_address(page);

drivers/block/loop.h+2−4

 struct loop_cmd {
 	struct kthread_work work;
 	struct request *rq;
-	union {
+	bool use_aio; /* use AIO interface to handle I/O */
-		bool use_aio; /* use AIO interface to handle I/O */
+	atomic_t ref; /* only for aio */
-		atomic_t ref; /* only for aio */
-	};
 	long ret;
 	struct kiocb iocb;
 	struct bio_vec *bvec;

drivers/block/nbd.c+11−1

 	 * appropriate.
 	 */
 	ret = nbd_handle_cmd(cmd, hctx->queue_num);
+	if (ret < 0)
+		ret = BLK_STS_IOERR;
+	else if (!ret)
+		ret = BLK_STS_OK;
 	complete(&cmd->send_complete);
-	return ret < 0 ? BLK_STS_IOERR : BLK_STS_OK;
+	return ret;
 }
 static int nbd_add_socket(struct nbd_device *nbd, unsigned long arg,
 	if (!capable(CAP_SYS_ADMIN))
 		return -EPERM;
+	/* The block layer will pass back some non-nbd ioctls in case we have
+	 * special handling for them, but we don't so just return an error.
+	 */
+	if (_IOC_TYPE(cmd) != 0xab)
+		return -EINVAL;
 	mutex_lock(&nbd->config_lock);
 	/* Don't allow ioctl operations on a nbd device that was created with

drivers/block/zram/zram_drv.c+12−24

 	bit_spin_unlock(ZRAM_ACCESS, &zram->table[index].value);
 }
-static bool zram_same_page_read(struct zram *zram, u32 index,
-				struct page *page,
-				unsigned int offset, unsigned int len)
-{
-	zram_slot_lock(zram, index);
-	if (unlikely(!zram_get_handle(zram, index) ||
-			zram_test_flag(zram, index, ZRAM_SAME))) {
-		void *mem;
-		zram_slot_unlock(zram, index);
-		mem = kmap_atomic(page);
-		zram_fill_page(mem + offset, len,
-					zram_get_element(zram, index));
-		kunmap_atomic(mem);
-		return true;
-	}
-	zram_slot_unlock(zram, index);
-	return false;
-}
 static void zram_meta_free(struct zram *zram, u64 disksize)
 {
 	size_t num_pages = disksize >> PAGE_SHIFT;
 		zram_slot_unlock(zram, index);
 	}
-	if (zram_same_page_read(zram, index, page, 0, PAGE_SIZE))
-		return 0;
 	zram_slot_lock(zram, index);
 	handle = zram_get_handle(zram, index);
+	if (!handle || zram_test_flag(zram, index, ZRAM_SAME)) {
+		unsigned long value;
+		void *mem;
+		value = handle ? zram_get_element(zram, index) : 0;
+		mem = kmap_atomic(page);
+		zram_fill_page(mem, PAGE_SIZE, value);
+		kunmap_atomic(mem);
+		zram_slot_unlock(zram, index);
+		return 0;
+	}
 	size = zram_get_obj_size(zram, index);
 	src = zs_map_object(zram->mem_pool, handle, ZS_MM_RO);

drivers/char/tpm/tpm-interface.c+5−5

@@ -455,7 +455,7 @@ ssize_t tpm_transmit(struct tpm_chip chip, struct tpm_space space, · 454 unmodified lines
455	goto out;	455	goto out;
456	}	456	}
457		457
458	msleep(TPM_TIMEOUT); /* CHECK */	458	tpm_msleep(TPM_TIMEOUT);
459	rmb();	459	rmb();
460	} while (time_before(jiffies, stop));	460	} while (time_before(jiffies, stop));
461		461
@@ -970,7 +970,7 @@ int tpm_do_selftest(struct tpm_chip *chip) · 508 unmodified lines
970	dev_info(	970	dev_info(
971	&chip->dev, HW_ERR	971	&chip->dev, HW_ERR
972	"TPM command timed out during continue self test");	972	"TPM command timed out during continue self test");
973	msleep(delay_msec);	973	tpm_msleep(delay_msec);
974	continue;	974	continue;
975	}	975	}
976		976
@@ -985,7 +985,7 @@ int tpm_do_selftest(struct tpm_chip *chip) · 8 unmodified lines
985	}	985	}
986	if (rc != TPM_WARN_DOING_SELFTEST)	986	if (rc != TPM_WARN_DOING_SELFTEST)
987	return rc;	987	return rc;
988	msleep(delay_msec);	988	tpm_msleep(delay_msec);
989	} while (--loops > 0);	989	} while (--loops > 0);
990		990
991	return rc;	991	return rc;
@@ -1085,7 +1085,7 @@ again: · 93 unmodified lines
1085	}	1085	}
1086	} else {	1086	} else {
1087	do {	1087	do {
1088	msleep(TPM_TIMEOUT);	1088	tpm_msleep(TPM_TIMEOUT);
1089	status = chip->ops->status(chip);	1089	status = chip->ops->status(chip);
1090	if ((status & mask) == mask)	1090	if ((status & mask) == mask)
1091	return 0;	1091	return 0;
@@ -1150,7 +1150,7 @@ int tpm_pm_suspend(struct device *dev) · 58 unmodified lines
1150	*/	1150	*/
1151	if (rc != TPM_WARN_RETRY)	1151	if (rc != TPM_WARN_RETRY)
1152	break;	1152	break;
1153	msleep(TPM_TIMEOUT_RETRY);	1153	tpm_msleep(TPM_TIMEOUT_RETRY);
1154	}	1154	}
1155		1155
1156	if (rc)	1156	if (rc)

drivers/char/tpm/tpm.h+8−1

 enum tpm_timeout {
 	TPM_TIMEOUT = 5,	/* msecs */
-	TPM_TIMEOUT_RETRY = 100 /* msecs */
+	TPM_TIMEOUT_RETRY = 100, /* msecs */
+	TPM_TIMEOUT_RANGE_US = 300	/* usecs */
 };
 /* TPM addresses */
 int wait_for_tpm_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout,
 		      wait_queue_head_t *queue, bool check_cancel);
+static inline void tpm_msleep(unsigned int delay_msec)
+{
+	usleep_range(delay_msec * 1000,
+		     (delay_msec * 1000) + TPM_TIMEOUT_RANGE_US);
+};
 struct tpm_chip *tpm_chip_find_get(int chip_num);
 __must_check int tpm_try_get_ops(struct tpm_chip *chip);
 void tpm_put_ops(struct tpm_chip *chip);

drivers/char/tpm/tpm2-cmd.c+1−1

@@ -899,7 +899,7 @@ static int tpm2_do_selftest(struct tpm_chip *chip) · 898 unmodified lines
899	if (rc != TPM2_RC_TESTING)	899	if (rc != TPM2_RC_TESTING)
900	break;	900	break;
901		901
902	msleep(delay_msec);	902	tpm_msleep(delay_msec);
903	}	903	}
904		904
905	return rc;	905	return rc;

drivers/char/tpm/tpm_crb.c+1−1

@@ -665,7 +665,7 @@ static const struct dev_pm_ops crb_pm = { · 664 unmodified lines
665	SET_RUNTIME_PM_OPS(crb_pm_runtime_suspend, crb_pm_runtime_resume, NULL)	665	SET_RUNTIME_PM_OPS(crb_pm_runtime_suspend, crb_pm_runtime_resume, NULL)
666	};	666	};
667		667
668	static struct acpi_device_id crb_device_ids[] = {	668	static const struct acpi_device_id crb_device_ids[] = {
669	{"MSFT0101", 0},	669	{"MSFT0101", 0},
670	{"", 0},	670	{"", 0},
671	};	671	};

drivers/char/tpm/tpm_ibmvtpm.c+61−37

 static const char tpm_ibmvtpm_driver_name[] = "tpm_ibmvtpm";
-static struct vio_device_id tpm_ibmvtpm_device_table[] = {
+static const struct vio_device_id tpm_ibmvtpm_device_table[] = {
 	{ "IBM,vtpm", "IBM,vtpm"},
 	{ "", "" }
 };
 MODULE_DEVICE_TABLE(vio, tpm_ibmvtpm_device_table);
 /**
+ *
+ * ibmvtpm_send_crq_word - Send a CRQ request
+ * @vdev:	vio device struct
+ * @w1:		pre-constructed first word of tpm crq (second word is reserved)
+ *
+ * Return:
+ *	0 - Success
+ *	Non-zero - Failure
+ */
+static int ibmvtpm_send_crq_word(struct vio_dev *vdev, u64 w1)
+{
+	return plpar_hcall_norets(H_SEND_CRQ, vdev->unit_address, w1, 0);
+}
+/**
+ *
  * ibmvtpm_send_crq - Send a CRQ request
  *
  * @vdev:	vio device struct
- * @w1:		first word
+ * @valid:	Valid field
- * @w2:		second word
+ * @msg:	Type field
+ * @len:	Length field
+ * @data:	Data field
+ *
+ * The ibmvtpm crq is defined as follows:
+ *
+ * Byte  |   0   |   1   |   2   |   3   |   4   |   5   |   6   |   7
+ * -----------------------------------------------------------------------
+ * Word0 | Valid | Type  |     Length    |              Data
+ * -----------------------------------------------------------------------
+ * Word1 |                Reserved
+ * -----------------------------------------------------------------------
+ *
+ * Which matches the following structure (on bigendian host):
+ *
+ * struct ibmvtpm_crq {
+ *         u8 valid;
+ *         u8 msg;
+ *         __be16 len;
+ *         __be32 data;
+ *         __be64 reserved;
+ * } __attribute__((packed, aligned(8)));
+ *
+ * However, the value is passed in a register so just compute the numeric value
+ * to load into the register avoiding byteswap altogether. Endian only affects
+ * memory loads and stores - registers are internally represented the same.
  *
  * Return:
- *	0 -Sucess
+ *	0 (H_SUCCESS) - Success
  *	Non-zero - Failure
  */
-static int ibmvtpm_send_crq(struct vio_dev *vdev, u64 w1, u64 w2)
+static int ibmvtpm_send_crq(struct vio_dev *vdev,
+		u8 valid, u8 msg, u16 len, u32 data)
 {
-	return plpar_hcall_norets(H_SEND_CRQ, vdev->unit_address, w1, w2);
+	u64 w1 = ((u64)valid << 56) | ((u64)msg << 48) | ((u64)len << 32) |
+		(u64)data;
+	return ibmvtpm_send_crq_word(vdev, w1);
 }
 /**
 static int tpm_ibmvtpm_send(struct tpm_chip *chip, u8 *buf, size_t count)
 {
 	struct ibmvtpm_dev *ibmvtpm = dev_get_drvdata(&chip->dev);
-	struct ibmvtpm_crq crq;
-	__be64 *word = (__be64 *)&crq;
 	int rc, sig;
 	if (!ibmvtpm->rtce_buf) {
 	spin_lock(&ibmvtpm->rtce_lock);
 	ibmvtpm->res_len = 0;
 	memcpy((void *)ibmvtpm->rtce_buf, (void *)buf, count);
-	crq.valid = (u8)IBMVTPM_VALID_CMD;
-	crq.msg = (u8)VTPM_TPM_COMMAND;
-	crq.len = cpu_to_be16(count);
-	crq.data = cpu_to_be32(ibmvtpm->rtce_dma_handle);
 	/*
 	 * set the processing flag before the Hcall, since we may get the
 	 */
 	ibmvtpm->tpm_processing_cmd = true;
-	rc = ibmvtpm_send_crq(ibmvtpm->vdev, be64_to_cpu(word[0]),
+	rc = ibmvtpm_send_crq(ibmvtpm->vdev,
-			      be64_to_cpu(word[1]));
+			IBMVTPM_VALID_CMD, VTPM_TPM_COMMAND,
+			count, ibmvtpm->rtce_dma_handle);
 	if (rc != H_SUCCESS) {
 		dev_err(ibmvtpm->dev, "tpm_ibmvtpm_send failed rc=%d\n", rc);
 		rc = 0;
  */
 static int ibmvtpm_crq_get_rtce_size(struct ibmvtpm_dev *ibmvtpm)
 {
-	struct ibmvtpm_crq crq;
-	u64 *buf = (u64 *) &crq;
 	int rc;
-	crq.valid = (u8)IBMVTPM_VALID_CMD;
+	rc = ibmvtpm_send_crq(ibmvtpm->vdev,
-	crq.msg = (u8)VTPM_GET_RTCE_BUFFER_SIZE;
+			IBMVTPM_VALID_CMD, VTPM_GET_RTCE_BUFFER_SIZE, 0, 0);
-	rc = ibmvtpm_send_crq(ibmvtpm->vdev, cpu_to_be64(buf[0]),
-			      cpu_to_be64(buf[1]));
 	if (rc != H_SUCCESS)
 		dev_err(ibmvtpm->dev,
 			"ibmvtpm_crq_get_rtce_size failed rc=%d\n", rc);
  */
 static int ibmvtpm_crq_get_version(struct ibmvtpm_dev *ibmvtpm)
 {
-	struct ibmvtpm_crq crq;
-	u64 *buf = (u64 *) &crq;
 	int rc;
-	crq.valid = (u8)IBMVTPM_VALID_CMD;
+	rc = ibmvtpm_send_crq(ibmvtpm->vdev,
-	crq.msg = (u8)VTPM_GET_VERSION;
+			IBMVTPM_VALID_CMD, VTPM_GET_VERSION, 0, 0);
-	rc = ibmvtpm_send_crq(ibmvtpm->vdev, cpu_to_be64(buf[0]),
-			      cpu_to_be64(buf[1]));
 	if (rc != H_SUCCESS)
 		dev_err(ibmvtpm->dev,
 			"ibmvtpm_crq_get_version failed rc=%d\n", rc);
 {
 	int rc;
-	rc = ibmvtpm_send_crq(ibmvtpm->vdev, INIT_CRQ_COMP_CMD, 0);
+	rc = ibmvtpm_send_crq_word(ibmvtpm->vdev, INIT_CRQ_COMP_CMD);
 	if (rc != H_SUCCESS)
 		dev_err(ibmvtpm->dev,
 			"ibmvtpm_crq_send_init_complete failed rc=%d\n", rc);
 {
 	int rc;
-	rc = ibmvtpm_send_crq(ibmvtpm->vdev, INIT_CRQ_CMD, 0);
+	rc = ibmvtpm_send_crq_word(ibmvtpm->vdev, INIT_CRQ_CMD);
 	if (rc != H_SUCCESS)
 		dev_err(ibmvtpm->dev,
 			"ibmvtpm_crq_send_init failed rc=%d\n", rc);
 {
 	struct tpm_chip *chip = dev_get_drvdata(dev);
 	struct ibmvtpm_dev *ibmvtpm = dev_get_drvdata(&chip->dev);
-	struct ibmvtpm_crq crq;
-	u64 *buf = (u64 *) &crq;
 	int rc = 0;
-	crq.valid = (u8)IBMVTPM_VALID_CMD;
+	rc = ibmvtpm_send_crq(ibmvtpm->vdev,
-	crq.msg = (u8)VTPM_PREPARE_TO_SUSPEND;
+			IBMVTPM_VALID_CMD, VTPM_PREPARE_TO_SUSPEND, 0, 0);
-	rc = ibmvtpm_send_crq(ibmvtpm->vdev, cpu_to_be64(buf[0]),
-			      cpu_to_be64(buf[1]));
 	if (rc != H_SUCCESS)
 		dev_err(ibmvtpm->dev,
 			"tpm_ibmvtpm_suspend failed rc=%d\n", rc);

drivers/char/tpm/tpm_infineon.c+3−3

@@ -191,7 +191,7 @@ static int wait(struct tpm_chip *chip, int wait_for_bit) · 190 unmodified lines
191	/* check the status-register if wait_for_bit is set */	191	/* check the status-register if wait_for_bit is set */
192	if (status & 1 << wait_for_bit)	192	if (status & 1 << wait_for_bit)
193	break;	193	break;
194	msleep(TPM_MSLEEP_TIME);	194	tpm_msleep(TPM_MSLEEP_TIME);
195	}	195	}
196	if (i == TPM_MAX_TRIES) { /* timeout occurs */	196	if (i == TPM_MAX_TRIES) { /* timeout occurs */
197	if (wait_for_bit == STAT_XFE)	197	if (wait_for_bit == STAT_XFE)
@@ -226,7 +226,7 @@ static void tpm_wtx(struct tpm_chip *chip) · 28 unmodified lines
226	wait_and_send(chip, TPM_CTRL_WTX);	226	wait_and_send(chip, TPM_CTRL_WTX);
227	wait_and_send(chip, 0x00);	227	wait_and_send(chip, 0x00);
228	wait_and_send(chip, 0x00);	228	wait_and_send(chip, 0x00);
229	msleep(TPM_WTX_MSLEEP_TIME);	229	tpm_msleep(TPM_WTX_MSLEEP_TIME);
230	}	230	}
231		231
232	static void tpm_wtx_abort(struct tpm_chip *chip)	232	static void tpm_wtx_abort(struct tpm_chip *chip)
@@ -237,7 +237,7 @@ static void tpm_wtx_abort(struct tpm_chip *chip) · 4 unmodified lines
237	wait_and_send(chip, 0x00);	237	wait_and_send(chip, 0x00);
238	wait_and_send(chip, 0x00);	238	wait_and_send(chip, 0x00);
239	number_of_wtx = 0;	239	number_of_wtx = 0;
240	msleep(TPM_WTX_MSLEEP_TIME);	240	tpm_msleep(TPM_WTX_MSLEEP_TIME);
241	}	241	}
242		242
243	static int tpm_inf_recv(struct tpm_chip chip, u8 buf, size_t count)	243	static int tpm_inf_recv(struct tpm_chip chip, u8 buf, size_t count)

drivers/char/tpm/tpm_tis_core.c+4−4

@@ -51,7 +51,7 @@ static int wait_startup(struct tpm_chip *chip, int l) · 50 unmodified lines
51		51
52	if (access & TPM_ACCESS_VALID)	52	if (access & TPM_ACCESS_VALID)
53	return 0;	53	return 0;
54	msleep(TPM_TIMEOUT);	54	tpm_msleep(TPM_TIMEOUT);
55	} while (time_before(jiffies, stop));	55	} while (time_before(jiffies, stop));
56	return -1;	56	return -1;
57	}	57	}
@@ -117,7 +117,7 @@ again: · 59 unmodified lines
117	do {	117	do {
118	if (check_locality(chip, l))	118	if (check_locality(chip, l))
119	return l;	119	return l;
120	msleep(TPM_TIMEOUT);	120	tpm_msleep(TPM_TIMEOUT);
121	} while (time_before(jiffies, stop));	121	} while (time_before(jiffies, stop));
122	}	122	}
123	return -1;	123	return -1;
@@ -164,7 +164,7 @@ static int get_burstcount(struct tpm_chip *chip) · 40 unmodified lines
164	burstcnt = (value >> 8) & 0xFFFF;	164	burstcnt = (value >> 8) & 0xFFFF;
165	if (burstcnt)	165	if (burstcnt)
166	return burstcnt;	166	return burstcnt;
167	msleep(TPM_TIMEOUT);	167	tpm_msleep(TPM_TIMEOUT);
168	} while (time_before(jiffies, stop));	168	} while (time_before(jiffies, stop));
169	return -EBUSY;	169	return -EBUSY;
170	}	170	}
@@ -396,7 +396,7 @@ static int tpm_tis_send(struct tpm_chip chip, u8 buf, size_t len) · 225 unmodified lines
396	priv->irq = irq;	396	priv->irq = irq;
397	chip->flags \|= TPM_CHIP_FLAG_IRQ;	397	chip->flags \|= TPM_CHIP_FLAG_IRQ;
398	if (!priv->irq_tested)	398	if (!priv->irq_tested)
399	msleep(1);	399	tpm_msleep(1);
400	if (!priv->irq_tested)	400	if (!priv->irq_tested)
401	disable_interrupts(chip);	401	disable_interrupts(chip);
402	priv->irq_tested = true;	402	priv->irq_tested = true;

drivers/clk/clk-bulk.c+1−0

@@ -105,6 +105,7 @@ err: · 104 unmodified lines
105		105
106	return ret;	106	return ret;
107	}	107	}
		108	EXPORT_SYMBOL_GPL(clk_bulk_prepare);
108		109
109	#endif /* CONFIG_HAVE_CLK_PREPARE */	110	#endif /* CONFIG_HAVE_CLK_PREPARE */
110		111

drivers/clk/rockchip/clk-rk3128.c+7−5

 			RK2928_CLKGATE_CON(10), 8, GFLAGS),
 	GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
-			RK2928_CLKGATE_CON(10), 8, GFLAGS),
+			RK2928_CLKGATE_CON(10), 0, GFLAGS),
 	GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0,
-			RK2928_CLKGATE_CON(10), 8, GFLAGS),
+			RK2928_CLKGATE_CON(10), 1, GFLAGS),
 	GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0,
-			RK2928_CLKGATE_CON(10), 8, GFLAGS),
+			RK2928_CLKGATE_CON(10), 2, GFLAGS),
 	GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,
-			RK2928_CLKGATE_CON(10), 8, GFLAGS),
+			RK2928_CLKGATE_CON(2), 15, GFLAGS),
 	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
 			RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
 	GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
 	GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS),
-	GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 2, GFLAGS),
+	GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
 	GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS),
 	/* PD_MMC */
 	"aclk_peri",
 	"hclk_peri",
 	"pclk_peri",
+	"pclk_pmu",
+	"sclk_timer5",
 };
 static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)

drivers/clk/samsung/clk-exynos4.c+15−0

@@ -294,6 +294,18 @@ static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { · 293 unmodified lines
294	#define PLL_ENABLED (1 << 31)	294	#define PLL_ENABLED (1 << 31)
295	#define PLL_LOCKED (1 << 29)	295	#define PLL_LOCKED (1 << 29)
296		296
		297	static void exynos4_clk_enable_pll(u32 reg)
		298	{
		299	u32 pll_con = readl(reg_base + reg);
		300	pll_con \|= PLL_ENABLED;
		301	writel(pll_con, reg_base + reg);
		302
		303	while (!(pll_con & PLL_LOCKED)) {
		304	cpu_relax();
		305	pll_con = readl(reg_base + reg);
		306	}
		307	}
		308
297	static void exynos4_clk_wait_for_pll(u32 reg)	309	static void exynos4_clk_wait_for_pll(u32 reg)
298	{	310	{
299	u32 pll_con;	311	u32 pll_con;
@@ -315,6 +327,9 @@ static int exynos4_clk_suspend(void) · 15 unmodified lines
315	samsung_clk_save(reg_base, exynos4_save_pll,	327	samsung_clk_save(reg_base, exynos4_save_pll,
316	ARRAY_SIZE(exynos4_clk_pll_regs));	328	ARRAY_SIZE(exynos4_clk_pll_regs));
317		329
		330	exynos4_clk_enable_pll(EPLL_CON0);
		331	exynos4_clk_enable_pll(VPLL_CON0);
		332
318	if (exynos4_soc == EXYNOS4210) {	333	if (exynos4_soc == EXYNOS4210) {
319	samsung_clk_save(reg_base, exynos4_save_soc,	334	samsung_clk_save(reg_base, exynos4_save_soc,
320	ARRAY_SIZE(exynos4210_clk_save));	335	ARRAY_SIZE(exynos4210_clk_save));

drivers/clocksource/numachip.c+1−1

@@ -43,7 +43,7 @@ static int numachip2_set_next_event(unsigned long delta, struct clock_event_devi · 42 unmodified lines
43	return 0;	43	return 0;
44	}	44	}
45		45
46	static struct clock_event_device numachip2_clockevent = {	46	static const struct clock_event_device numachip2_clockevent __initconst = {
47	.name = "numachip2",	47	.name = "numachip2",
48	.rating = 400,	48	.rating = 400,
49	.set_next_event = numachip2_set_next_event,	49	.set_next_event = numachip2_set_next_event,

drivers/clocksource/timer-integrator-ap.c+2−2

@@ -36,8 +36,8 @@ static u64 notrace integrator_read_sched_clock(void) · 35 unmodified lines
36	return -readl(sched_clk_base + TIMER_VALUE);	36	return -readl(sched_clk_base + TIMER_VALUE);
37	}	37	}
38		38
39	static int integrator_clocksource_init(unsigned long inrate,	39	static int __init integrator_clocksource_init(unsigned long inrate,
40	void __iomem *base)	40	void __iomem *base)
41	{	41	{
42	u32 ctrl = TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC;	42	u32 ctrl = TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC;
43	unsigned long rate = inrate;	43	unsigned long rate = inrate;

drivers/cpufreq/cpufreq-dt-platdev.c+16−0

@@ -106,6 +106,22 @@ static const struct of_device_id whitelist[] __initconst = { · 105 unmodified lines
106	* platforms using "operating-points-v2" property.	106	* platforms using "operating-points-v2" property.
107	*/	107	*/
108	static const struct of_device_id blacklist[] __initconst = {	108	static const struct of_device_id blacklist[] __initconst = {
		109	{ .compatible = "calxeda,highbank", },
		110	{ .compatible = "calxeda,ecx-2000", },
		111
		112	{ .compatible = "marvell,armadaxp", },
		113
		114	{ .compatible = "nvidia,tegra124", },
		115
		116	{ .compatible = "st,stih407", },
		117	{ .compatible = "st,stih410", },
		118
		119	{ .compatible = "sigma,tango4", },
		120
		121	{ .compatible = "ti,am33xx", },
		122	{ .compatible = "ti,am43", },
		123	{ .compatible = "ti,dra7", },
		124
109	{ }	125	{ }
110	};	126	};
111		127

drivers/cpufreq/ti-cpufreq.c+1−1

@@ -190,7 +190,7 @@ static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data) · 189 unmodified lines
190		190
191	static const struct of_device_id ti_cpufreq_of_match[] = {	191	static const struct of_device_id ti_cpufreq_of_match[] = {
192	{ .compatible = "ti,am33xx", .data = &am3x_soc_data, },	192	{ .compatible = "ti,am33xx", .data = &am3x_soc_data, },
193	{ .compatible = "ti,am4372", .data = &am4x_soc_data, },	193	{ .compatible = "ti,am43", .data = &am4x_soc_data, },
194	{ .compatible = "ti,dra7", .data = &dra7_soc_data },	194	{ .compatible = "ti,dra7", .data = &dra7_soc_data },
195	{},	195	{},
196	};	196	};

drivers/cpuidle/cpuidle-arm.c+4−2

 		ret = dt_init_idle_driver(drv, arm_idle_state_match, 1);
 		if (ret <= 0) {
 			ret = ret ? : -ENODEV;
-			goto out_fail;
+			goto init_fail;
 		}
 		ret = cpuidle_register_driver(drv);
 		if (ret) {
 			pr_err("Failed to register cpuidle driver\n");
-			goto out_fail;
+			goto init_fail;
 		}
 		/*
 	}
 	return 0;
+init_fail:
+	kfree(drv);
 out_fail:
 	while (--cpu >= 0) {
 		dev = per_cpu(cpuidle_devices, cpu);

drivers/crypto/caam/Kconfig+1−4

 config CRYPTO_DEV_FSL_CAAM
 	tristate "Freescale CAAM-Multicore driver backend"
 	depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE
+	select SOC_BUS
 	help
 	  Enables the driver module for Freescale's Cryptographic Accelerator
 	  and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
 	  To compile this as a module, choose M here: the module
 	  will be called caamrng.
-config CRYPTO_DEV_FSL_CAAM_IMX
-	def_bool SOC_IMX6 || SOC_IMX7D
-	depends on CRYPTO_DEV_FSL_CAAM
 config CRYPTO_DEV_FSL_CAAM_DEBUG
 	bool "Enable debug output in CAAM driver"
 	depends on CRYPTO_DEV_FSL_CAAM

drivers/crypto/caam/ctrl.c+10−9

 #include <linux/device.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/sys_soc.h>
 #include "compat.h"
 #include "regs.h"
 EXPORT_SYMBOL(caam_little_end);
 bool caam_dpaa2;
 EXPORT_SYMBOL(caam_dpaa2);
+bool caam_imx;
+EXPORT_SYMBOL(caam_imx);
 #ifdef CONFIG_CAAM_QI
 #include "qi.h"
  * i.MX targets tend to have clock control subsystems that can
  * enable/disable clocking to our device.
  */
-#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
 static inline struct clk *caam_drv_identify_clk(struct device *dev,
 						char *clk_name)
 {
-	return devm_clk_get(dev, clk_name);
+	return caam_imx ? devm_clk_get(dev, clk_name) : NULL;
 }
-#else
-static inline struct clk *caam_drv_identify_clk(struct device *dev,
-						char *clk_name)
-{
-	return NULL;
-}
-#endif
 /*
  * Descriptor to instantiate RNG State Handle 0 in normal mode and
 {
 	int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
 	u64 caam_id;
+	static const struct soc_device_attribute imx_soc[] = {
+		{.family = "Freescale i.MX"},
+		{},
+	};
 	struct device *dev;
 	struct device_node *nprop, *np;
 	struct caam_ctrl __iomem *ctrl;
 	dev_set_drvdata(dev, ctrlpriv);
 	nprop = pdev->dev.of_node;
+	caam_imx = (bool)soc_device_match(imx_soc);
 	/* Enable clocking */
 	clk = caam_drv_identify_clk(&pdev->dev, "ipg");
 	if (IS_ERR(clk)) {

drivers/crypto/caam/regs.h+28−31

@@ -67,6 +67,7 @@ · 66 unmodified lines
67	*/	67	*/
68		68
69	extern bool caam_little_end;	69	extern bool caam_little_end;
		70	extern bool caam_imx;
70		71
71	#define caam_to_cpu(len) \	72	#define caam_to_cpu(len) \
72	static inline u##len caam##len ## _to_cpu(u##len val) \	73	static inline u##len caam##len ## _to_cpu(u##len val) \
@@ -154,13 +155,10 @@ static inline u64 rd_reg64(void __iomem *reg) · 81 unmodified lines
154	#else /* CONFIG_64BIT */	155	#else /* CONFIG_64BIT */
155	static inline void wr_reg64(void __iomem *reg, u64 data)	156	static inline void wr_reg64(void __iomem *reg, u64 data)
156	{	157	{
157	#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX	158	if (!caam_imx && caam_little_end) {
158	if (caam_little_end) {
159	wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);	159	wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
160	wr_reg32((u32 __iomem *)(reg), data);	160	wr_reg32((u32 __iomem *)(reg), data);
161	} else	161	} else {
162	#endif
163	{
164	wr_reg32((u32 __iomem *)(reg), data >> 32);	162	wr_reg32((u32 __iomem *)(reg), data >> 32);
165	wr_reg32((u32 __iomem *)(reg) + 1, data);	163	wr_reg32((u32 __iomem *)(reg) + 1, data);
166	}	164	}
@@ -168,41 +166,40 @@ static inline void wr_reg64(void __iomem *reg, u64 data) · 1 unmodified line
168		166
169	static inline u64 rd_reg64(void __iomem *reg)	167	static inline u64 rd_reg64(void __iomem *reg)
170	{	168	{
171	#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX	169	if (!caam_imx && caam_little_end)
172	if (caam_little_end)
173	return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 \|	170	return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 \|
174	(u64)rd_reg32((u32 __iomem *)(reg)));	171	(u64)rd_reg32((u32 __iomem *)(reg)));
175	else	172
176	#endif	173	return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 \|
177	return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 \|	174	(u64)rd_reg32((u32 __iomem *)(reg) + 1));
178	(u64)rd_reg32((u32 __iomem *)(reg) + 1));
179	}	175	}
180	#endif /* CONFIG_64BIT */	176	#endif /* CONFIG_64BIT */
181		177
		178	static inline u64 cpu_to_caam_dma64(dma_addr_t value)
		179	{
		180	if (caam_imx)
		181	return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) \|
		182	(u64)cpu_to_caam32(upper_32_bits(value)));
		183
		184	return cpu_to_caam64(value);
		185	}
		186
		187	static inline u64 caam_dma64_to_cpu(u64 value)
		188	{
		189	if (caam_imx)
		190	return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) \|
		191	(u64)caam32_to_cpu(upper_32_bits(value)));
		192
		193	return caam64_to_cpu(value);
		194	}
		195
182	#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT	196	#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
183	#ifdef CONFIG_SOC_IMX7D	197	#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
184	#define cpu_to_caam_dma(value) \	198	#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
185	(((u64)cpu_to_caam32(lower_32_bits(value)) << 32) \| \
186	(u64)cpu_to_caam32(upper_32_bits(value)))
187	#define caam_dma_to_cpu(value) \
188	(((u64)caam32_to_cpu(lower_32_bits(value)) << 32) \| \
189	(u64)caam32_to_cpu(upper_32_bits(value)))
190	#else
191	#define cpu_to_caam_dma(value) cpu_to_caam64(value)
192	#define caam_dma_to_cpu(value) caam64_to_cpu(value)
193	#endif /* CONFIG_SOC_IMX7D */
194	#else	199	#else
195	#define cpu_to_caam_dma(value) cpu_to_caam32(value)	200	#define cpu_to_caam_dma(value) cpu_to_caam32(value)
196	#define caam_dma_to_cpu(value) caam32_to_cpu(value)	201	#define caam_dma_to_cpu(value) caam32_to_cpu(value)
197	#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */	202	#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
198
199	#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
200	#define cpu_to_caam_dma64(value) \
201	(((u64)cpu_to_caam32(lower_32_bits(value)) << 32) \| \
202	(u64)cpu_to_caam32(upper_32_bits(value)))
203	#else
204	#define cpu_to_caam_dma64(value) cpu_to_caam64(value)
205	#endif
206		203
207	/*	204	/*
208	* jr_outentry	205	* jr_outentry

drivers/crypto/inside-secure/safexcel_cipher.c+1−1

@@ -386,7 +386,7 @@ static int safexcel_cipher_exit_inv(struct crypto_tfm *tfm) · 385 unmodified lines
386	struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);	386	struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
387	struct safexcel_crypto_priv *priv = ctx->priv;	387	struct safexcel_crypto_priv *priv = ctx->priv;
388	struct skcipher_request req;	388	struct skcipher_request req;
389	struct safexcel_inv_result result = { 0 };	389	struct safexcel_inv_result result = {};
390	int ring = ctx->base.ring;	390	int ring = ctx->base.ring;
391		391
392	memset(&req, 0, sizeof(struct skcipher_request));	392	memset(&req, 0, sizeof(struct skcipher_request));

drivers/crypto/inside-secure/safexcel_hash.c+1−1

@@ -419,7 +419,7 @@ static int safexcel_ahash_exit_inv(struct crypto_tfm *tfm) · 418 unmodified lines
419	struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);	419	struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
420	struct safexcel_crypto_priv *priv = ctx->priv;	420	struct safexcel_crypto_priv *priv = ctx->priv;
421	struct ahash_request req;	421	struct ahash_request req;
422	struct safexcel_inv_result result = { 0 };	422	struct safexcel_inv_result result = {};
423	int ring = ctx->base.ring;	423	int ring = ctx->base.ring;
424		424
425	memset(&req, 0, sizeof(struct ahash_request));	425	memset(&req, 0, sizeof(struct ahash_request));

drivers/crypto/talitos.c+5−4

 		req_ctx->swinit = 0;
 	} else {
 		desc->ptr[1] = zero_entry;
-		/* Indicate next op is not the first. */
-		req_ctx->first = 0;
 	}
+	/* Indicate next op is not the first. */
+	req_ctx->first = 0;
 	/* HMAC key */
 	if (ctx->keylen)
 	sg_count = edesc->src_nents ?: 1;
 	if (is_sec1 && sg_count > 1)
-		sg_copy_to_buffer(areq->src, sg_count, edesc->buf, length);
+		sg_copy_to_buffer(req_ctx->psrc, sg_count, edesc->buf, length);
 	else
 		sg_count = dma_map_sg(dev, req_ctx->psrc, sg_count,
 				      DMA_TO_DEVICE);
 		t_alg->algt.alg.hash.final = ahash_final;
 		t_alg->algt.alg.hash.finup = ahash_finup;
 		t_alg->algt.alg.hash.digest = ahash_digest;
-		t_alg->algt.alg.hash.setkey = ahash_setkey;
+		if (!strncmp(alg->cra_name, "hmac", 4))
+			t_alg->algt.alg.hash.setkey = ahash_setkey;
 		t_alg->algt.alg.hash.import = ahash_import;
 		t_alg->algt.alg.hash.export = ahash_export;

drivers/fpga/altera-cvp.c+3−3

@@ -361,12 +361,12 @@ static const struct fpga_manager_ops altera_cvp_ops = { · 360 unmodified lines
361	.write_complete = altera_cvp_write_complete,	361	.write_complete = altera_cvp_write_complete,
362	};	362	};
363		363
364	static ssize_t show_chkcfg(struct device_driver dev, char buf)	364	static ssize_t chkcfg_show(struct device_driver dev, char buf)
365	{	365	{
366	return snprintf(buf, 3, "%d\n", altera_cvp_chkcfg);	366	return snprintf(buf, 3, "%d\n", altera_cvp_chkcfg);
367	}	367	}
368		368
369	static ssize_t store_chkcfg(struct device_driver drv, const char buf,	369	static ssize_t chkcfg_store(struct device_driver drv, const char buf,
370	size_t count)	370	size_t count)
371	{	371	{
372	int ret;	372	int ret;
@@ -378,7 +378,7 @@ static ssize_t store_chkcfg(struct device_driver drv, const char buf, · 5 unmodified lines
378	return count;	378	return count;
379	}	379	}
380		380
381	static DRIVER_ATTR(chkcfg, 0600, show_chkcfg, store_chkcfg);	381	static DRIVER_ATTR_RW(chkcfg);
382		382
383	static int altera_cvp_probe(struct pci_dev *pdev,	383	static int altera_cvp_probe(struct pci_dev *pdev,
384	const struct pci_device_id *dev_id);	384	const struct pci_device_id *dev_id);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c+188−1

@@ -636,7 +636,194 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) · 635 unmodified lines
636	NUM_BANKS(ADDR_SURF_2_BANK);	636	NUM_BANKS(ADDR_SURF_2_BANK);
637	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)	637	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
638	WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);	638	WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
639	} else if (adev->asic_type == CHIP_OLAND \|\| adev->asic_type == CHIP_HAINAN) {	639	} else if (adev->asic_type == CHIP_OLAND) {
		640	tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
		641	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		642	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		643	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) \|
		644	NUM_BANKS(ADDR_SURF_16_BANK) \|
		645	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		646	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
		647	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
		648	tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
		649	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		650	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		651	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) \|
		652	NUM_BANKS(ADDR_SURF_16_BANK) \|
		653	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		654	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
		655	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
		656	tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
		657	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		658	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		659	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
		660	NUM_BANKS(ADDR_SURF_16_BANK) \|
		661	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		662	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
		663	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
		664	tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
		665	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		666	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		667	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) \|
		668	NUM_BANKS(ADDR_SURF_16_BANK) \|
		669	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		670	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
		671	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
		672	tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
		673	ARRAY_MODE(ARRAY_1D_TILED_THIN1) \|
		674	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		675	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) \|
		676	NUM_BANKS(ADDR_SURF_16_BANK) \|
		677	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		678	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
		679	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		680	tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
		681	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		682	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		683	TILE_SPLIT(split_equal_to_row_size) \|
		684	NUM_BANKS(ADDR_SURF_16_BANK) \|
		685	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		686	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
		687	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		688	tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
		689	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		690	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		691	TILE_SPLIT(split_equal_to_row_size) \|
		692	NUM_BANKS(ADDR_SURF_16_BANK) \|
		693	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		694	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|
		695	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		696	tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
		697	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		698	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		699	TILE_SPLIT(split_equal_to_row_size) \|
		700	NUM_BANKS(ADDR_SURF_16_BANK) \|
		701	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		702	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
		703	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
		704	tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|
		705	ARRAY_MODE(ARRAY_LINEAR_ALIGNED) \|
		706	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		707	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) \|
		708	NUM_BANKS(ADDR_SURF_16_BANK) \|
		709	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		710	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
		711	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		712	tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|
		713	ARRAY_MODE(ARRAY_1D_TILED_THIN1) \|
		714	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		715	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) \|
		716	NUM_BANKS(ADDR_SURF_16_BANK) \|
		717	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		718	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
		719	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		720	tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|
		721	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		722	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		723	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
		724	NUM_BANKS(ADDR_SURF_16_BANK) \|
		725	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		726	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
		727	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
		728	tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|
		729	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		730	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		731	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
		732	NUM_BANKS(ADDR_SURF_16_BANK) \|
		733	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		734	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
		735	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		736	tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|
		737	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		738	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		739	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) \|
		740	NUM_BANKS(ADDR_SURF_16_BANK) \|
		741	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		742	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|
		743	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		744	tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
		745	ARRAY_MODE(ARRAY_1D_TILED_THIN1) \|
		746	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		747	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) \|
		748	NUM_BANKS(ADDR_SURF_16_BANK) \|
		749	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		750	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
		751	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		752	tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
		753	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		754	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		755	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
		756	NUM_BANKS(ADDR_SURF_16_BANK) \|
		757	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		758	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
		759	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		760	tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
		761	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		762	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		763	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
		764	NUM_BANKS(ADDR_SURF_16_BANK) \|
		765	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		766	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
		767	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		768	tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
		769	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		770	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		771	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) \|
		772	NUM_BANKS(ADDR_SURF_16_BANK) \|
		773	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		774	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|
		775	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		776	tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
		777	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		778	PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
		779	TILE_SPLIT(split_equal_to_row_size) \|
		780	NUM_BANKS(ADDR_SURF_16_BANK) \|
		781	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		782	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|
		783	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		784	tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
		785	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		786	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
		787	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
		788	NUM_BANKS(ADDR_SURF_16_BANK) \|
		789	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) \|
		790	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
		791	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		792	tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
		793	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		794	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
		795	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
		796	NUM_BANKS(ADDR_SURF_16_BANK) \|
		797	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		798	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
		799	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
		800	tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
		801	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		802	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
		803	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
		804	NUM_BANKS(ADDR_SURF_16_BANK) \|
		805	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		806	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
		807	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		808	tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
		809	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		810	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
		811	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) \|
		812	NUM_BANKS(ADDR_SURF_16_BANK) \|
		813	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		814	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|
		815	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
		816	tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
		817	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
		818	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
		819	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) \|
		820	NUM_BANKS(ADDR_SURF_8_BANK) \|
		821	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
		822	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|
		823	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
		824	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
		825	WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
		826	} else if (adev->asic_type == CHIP_HAINAN) {
640	tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|	827	tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
641	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|	828	ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
642	PIPE_CONFIG(ADDR_SURF_P2) \|	829	PIPE_CONFIG(ADDR_SURF_P2) \|

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c+2−0

@@ -892,6 +892,8 @@ static int kfd_ioctl_get_tile_config(struct file *filep, · 891 unmodified lines
892	int err = 0;	892	int err = 0;
893		893
894	dev = kfd_device_by_id(args->gpu_id);	894	dev = kfd_device_by_id(args->gpu_id);
		895	if (!dev)
		896	return -EINVAL;
895		897
896	dev->kfd2kgd->get_tile_config(dev->kgd, &config);	898	dev->kfd2kgd->get_tile_config(dev->kgd, &config);
897		899

drivers/gpu/drm/amd/amdkfd/kfd_events.c+4−1

 				struct kfd_event *ev)
 {
 	if (p->signal_event_count == KFD_SIGNAL_EVENT_LIMIT) {
-		pr_warn("Signal event wasn't created because limit was reached\n");
+		if (!p->signal_event_limit_reached) {
+			pr_warn("Signal event wasn't created because limit was reached\n");
+			p->signal_event_limit_reached = true;
+		}
 		return -ENOMEM;
 	}

drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c+17−5

 {
 	if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
 		kq->mqd->destroy_mqd(kq->mqd,
-					NULL,
+					kq->queue->mqd,
-					false,
+					KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
 					QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS,
 					kq->queue->pipe,
 					kq->queue->queue);
 	uint32_t wptr, rptr;
 	unsigned int *queue_address;
+	/* When rptr == wptr, the buffer is empty.
+	 * When rptr == wptr + 1, the buffer is full.
+	 * It is always rptr that advances to the position of wptr, rather than
+	 * the opposite. So we can only use up to queue_size_dwords - 1 dwords.
+	 */
 	rptr = *kq->rptr_kernel;
 	wptr = *kq->wptr_kernel;
 	queue_address = (unsigned int *)kq->pq_kernel_addr;
 	pr_debug("wptr: %d\n", wptr);
 	pr_debug("queue_address 0x%p\n", queue_address);
-	available_size = (rptr - 1 - wptr + queue_size_dwords) %
+	available_size = (rptr + queue_size_dwords - 1 - wptr) %
 							queue_size_dwords;
-	if (packet_size_in_dwords >= queue_size_dwords ||
+	if (packet_size_in_dwords > available_size) {
-			packet_size_in_dwords >= available_size) {
 		/*
 		 * make sure calling functions know
 		 * acquire_packet_buffer() failed
 	}
 	if (wptr + packet_size_in_dwords >= queue_size_dwords) {
+		/* make sure after rolling back to position 0, there is
+		 * still enough space.
+		 */
+		if (packet_size_in_dwords >= rptr) {
+			*buffer_ptr = NULL;
+			return -ENOMEM;
+		}
+		/* fill nops, roll back and start at position 0 */
 		while (wptr > 0) {
 			queue_address[wptr] = kq->nop_packet;
 			wptr = (wptr + 1) % queue_size_dwords;

drivers/gpu/drm/amd/amdkfd/kfd_priv.h+1−0

@@ -521,6 +521,7 @@ struct kfd_process { · 520 unmodified lines
521	struct list_head signal_event_pages;	521	struct list_head signal_event_pages;
522	u32 next_nonsignal_event_id;	522	u32 next_nonsignal_event_id;
523	size_t signal_event_count;	523	size_t signal_event_count;
		524	bool signal_event_limit_reached;
524	};	525	};
525		526
526	/**	527	/**

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c+0−1

@@ -143,7 +143,6 @@ int pqm_create_queue(struct process_queue_manager *pqm, · 142 unmodified lines
143	int num_queues = 0;	143	int num_queues = 0;
144	struct queue *cur;	144	struct queue *cur;
145		145
146	memset(&q_properties, 0, sizeof(struct queue_properties));
147	memcpy(&q_properties, properties, sizeof(struct queue_properties));	146	memcpy(&q_properties, properties, sizeof(struct queue_properties));
148	q = NULL;	147	q = NULL;
149	kq = NULL;	148	kq = NULL;

drivers/gpu/drm/etnaviv/etnaviv_gem.c+3−0

 void etnaviv_gem_free_object(struct drm_gem_object *obj)
 {
 	struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj);
+	struct etnaviv_drm_private *priv = obj->dev->dev_private;
 	struct etnaviv_vram_mapping *mapping, *tmp;
 	/* object should not be active */
 	WARN_ON(is_active(etnaviv_obj));
+	mutex_lock(&priv->gem_lock);
 	list_del(&etnaviv_obj->gem_node);
+	mutex_unlock(&priv->gem_lock);
 	list_for_each_entry_safe(mapping, tmp, &etnaviv_obj->vram_list,
 				 obj_node) {

drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c+4−2

@@ -445,8 +445,10 @@ int etnaviv_ioctl_gem_submit(struct drm_device dev, void data, · 444 unmodified lines
445	cmdbuf->user_size = ALIGN(args->stream_size, 8);	445	cmdbuf->user_size = ALIGN(args->stream_size, 8);
446		446
447	ret = etnaviv_gpu_submit(gpu, submit, cmdbuf);	447	ret = etnaviv_gpu_submit(gpu, submit, cmdbuf);
448	if (ret == 0)	448	if (ret)
449	cmdbuf = NULL;	449	goto out;
		450
		451	cmdbuf = NULL;
450		452
451	if (args->flags & ETNA_SUBMIT_FENCE_FD_OUT) {	453	if (args->flags & ETNA_SUBMIT_FENCE_FD_OUT) {
452	/*	454	/*

drivers/gpu/drm/exynos/exynos5433_drm_decon.c+1−0

@@ -14,6 +14,7 @@ · 13 unmodified lines
14	#include <linux/clk.h>	14	#include <linux/clk.h>
15	#include <linux/component.h>	15	#include <linux/component.h>
16	#include <linux/iopoll.h>	16	#include <linux/iopoll.h>
		17	#include <linux/irq.h>
17	#include <linux/mfd/syscon.h>	18	#include <linux/mfd/syscon.h>
18	#include <linux/of_device.h>	19	#include <linux/of_device.h>
19	#include <linux/of_gpio.h>	20	#include <linux/of_gpio.h>

drivers/gpu/drm/exynos/exynos_drm_drv.c+12−24

@@ -168,23 +168,19 @@ static struct drm_driver exynos_drm_driver = { · 167 unmodified lines
168	static int exynos_drm_suspend(struct device *dev)	168	static int exynos_drm_suspend(struct device *dev)
169	{	169	{
170	struct drm_device *drm_dev = dev_get_drvdata(dev);	170	struct drm_device *drm_dev = dev_get_drvdata(dev);
171	struct drm_connector *connector;	171	struct exynos_drm_private *private = drm_dev->dev_private;
172	struct drm_connector_list_iter conn_iter;
173		172
174	if (pm_runtime_suspended(dev) \|\| !drm_dev)	173	if (pm_runtime_suspended(dev) \|\| !drm_dev)
175	return 0;	174	return 0;
176		175
177	drm_connector_list_iter_begin(drm_dev, &conn_iter);	176	drm_kms_helper_poll_disable(drm_dev);
178	drm_for_each_connector_iter(connector, &conn_iter) {	177	exynos_drm_fbdev_suspend(drm_dev);
179	int old_dpms = connector->dpms;	178	private->suspend_state = drm_atomic_helper_suspend(drm_dev);
180		179	if (IS_ERR(private->suspend_state)) {
181	if (connector->funcs->dpms)	180	exynos_drm_fbdev_resume(drm_dev);
182	connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);	181	drm_kms_helper_poll_enable(drm_dev);
183		182	return PTR_ERR(private->suspend_state);
184	/* Set the old mode back to the connector for resume */
185	connector->dpms = old_dpms;
186	}	183	}
187	drm_connector_list_iter_end(&conn_iter);
188		184
189	return 0;	185	return 0;
190	}	186	}
@@ -192,22 +188,14 @@ static int exynos_drm_suspend(struct device *dev) · 1 unmodified line
192	static int exynos_drm_resume(struct device *dev)	188	static int exynos_drm_resume(struct device *dev)
193	{	189	{
194	struct drm_device *drm_dev = dev_get_drvdata(dev);	190	struct drm_device *drm_dev = dev_get_drvdata(dev);
195	struct drm_connector *connector;	191	struct exynos_drm_private *private = drm_dev->dev_private;
196	struct drm_connector_list_iter conn_iter;
197		192
198	if (pm_runtime_suspended(dev) \|\| !drm_dev)	193	if (pm_runtime_suspended(dev) \|\| !drm_dev)
199	return 0;	194	return 0;
200		195
201	drm_connector_list_iter_begin(drm_dev, &conn_iter);	196	drm_atomic_helper_resume(drm_dev, private->suspend_state);
202	drm_for_each_connector_iter(connector, &conn_iter) {	197	exynos_drm_fbdev_resume(drm_dev);
203	if (connector->funcs->dpms) {	198	drm_kms_helper_poll_enable(drm_dev);
204	int dpms = connector->dpms;
205
206	connector->dpms = DRM_MODE_DPMS_OFF;
207	connector->funcs->dpms(connector, dpms);
208	}
209	}
210	drm_connector_list_iter_end(&conn_iter);
211		199
212	return 0;	200	return 0;
213	}	201	}

drivers/gpu/drm/exynos/exynos_drm_drv.h+1−0

@@ -202,6 +202,7 @@ struct drm_exynos_file_private { · 201 unmodified lines
202	*/	202	*/
203	struct exynos_drm_private {	203	struct exynos_drm_private {
204	struct drm_fb_helper *fb_helper;	204	struct drm_fb_helper *fb_helper;
		205	struct drm_atomic_state *suspend_state;
205		206
206	struct device *dma_dev;	207	struct device *dma_dev;
207	void *mapping;	208	void *mapping;

drivers/gpu/drm/exynos/exynos_drm_fbdev.c+20−0

@@ -18,6 +18,8 @@ · 17 unmodified lines
18	#include <drm/drm_crtc_helper.h>	18	#include <drm/drm_crtc_helper.h>
19	#include <drm/exynos_drm.h>	19	#include <drm/exynos_drm.h>
20		20
		21	#include <linux/console.h>
		22
21	#include "exynos_drm_drv.h"	23	#include "exynos_drm_drv.h"
22	#include "exynos_drm_fb.h"	24	#include "exynos_drm_fb.h"
23	#include "exynos_drm_fbdev.h"	25	#include "exynos_drm_fbdev.h"
@@ -285,3 +287,21 @@ void exynos_drm_output_poll_changed(struct drm_device *dev) · 261 unmodified lines
285		287
286	drm_fb_helper_hotplug_event(fb_helper);	288	drm_fb_helper_hotplug_event(fb_helper);
287	}	289	}
		290
		291	void exynos_drm_fbdev_suspend(struct drm_device *dev)
		292	{
		293	struct exynos_drm_private *private = dev->dev_private;
		294
		295	console_lock();
		296	drm_fb_helper_set_suspend(private->fb_helper, 1);
		297	console_unlock();
		298	}
		299
		300	void exynos_drm_fbdev_resume(struct drm_device *dev)
		301	{
		302	struct exynos_drm_private *private = dev->dev_private;
		303
		304	console_lock();
		305	drm_fb_helper_set_suspend(private->fb_helper, 0);
		306	console_unlock();
		307	}

drivers/gpu/drm/exynos/exynos_drm_fbdev.h+10−0

 void exynos_drm_fbdev_fini(struct drm_device *dev);
 void exynos_drm_fbdev_restore_mode(struct drm_device *dev);
 void exynos_drm_output_poll_changed(struct drm_device *dev);
+void exynos_drm_fbdev_suspend(struct drm_device *drm);
+void exynos_drm_fbdev_resume(struct drm_device *drm);
 #else
 #define exynos_drm_output_poll_changed (NULL)
+static inline void exynos_drm_fbdev_suspend(struct drm_device *drm)
+{
+}
+static inline void exynos_drm_fbdev_resume(struct drm_device *drm)
+{
+}
 #endif
 #endif

drivers/gpu/drm/exynos/exynos_hdmi.c+11−3

 	struct drm_device *dev = encoder->dev;
 	struct drm_connector *connector;
 	struct drm_display_mode *m;
+	struct drm_connector_list_iter conn_iter;
 	int mode_ok;
 	drm_mode_set_crtcinfo(adjusted_mode, 0);
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+	drm_connector_list_iter_begin(dev, &conn_iter);
+	drm_for_each_connector_iter(connector, &conn_iter) {
 		if (connector->encoder == encoder)
 			break;
 	}
+	if (connector)
+		drm_connector_get(connector);
+	drm_connector_list_iter_end(&conn_iter);
-	if (connector->encoder != encoder)
+	if (!connector)
 		return true;
 	mode_ok = hdmi_mode_valid(connector, adjusted_mode);
 	if (mode_ok == MODE_OK)
-		return true;
+		goto cleanup;
 	/*
 	 * Find the most suitable mode and copy it to adjusted_mode.
 		}
 	}
+cleanup:
+	drm_connector_put(connector);
 	return true;
 }

drivers/gpu/drm/i915/gvt/cfg_space.c+48−65

@@ -197,78 +197,65 @@ static int emulate_pci_command_write(struct intel_vgpu *vgpu, · 196 unmodified lines
197	static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,	197	static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
198	void *p_data, unsigned int bytes)	198	void *p_data, unsigned int bytes)
199	{	199	{
200	unsigned int bar_index =
201	(rounddown(offset, 8) % PCI_BASE_ADDRESS_0) / 8;
202	u32 new = (u32 )(p_data);	200	u32 new = (u32 )(p_data);
203	bool lo = IS_ALIGNED(offset, 8);	201	bool lo = IS_ALIGNED(offset, 8);
204	u64 size;	202	u64 size;
205	int ret = 0;	203	int ret = 0;
206	bool mmio_enabled =	204	bool mmio_enabled =
207	vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;	205	vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
		206	struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar;
208		207
209	if (WARN_ON(bar_index >= INTEL_GVT_PCI_BAR_MAX))	208	/*
210	return -EINVAL;	209	* Power-up software can determine how much address
211		210	* space the device requires by writing a value of
		211	* all 1's to the register and then reading the value
		212	* back. The device will return 0's in all don't-care
		213	* address bits.
		214	*/
212	if (new == 0xffffffff) {	215	if (new == 0xffffffff) {
213	/*	216	switch (offset) {
214	* Power-up software can determine how much address	217	case PCI_BASE_ADDRESS_0:
215	* space the device requires by writing a value of	218	case PCI_BASE_ADDRESS_1:
216	* all 1's to the register and then reading the value	219	size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1);
217	* back. The device will return 0's in all don't-care	220	intel_vgpu_write_pci_bar(vgpu, offset,
218	* address bits.	221	size >> (lo ? 0 : 32), lo);
219	*/	222	/*
220	size = vgpu->cfg_space.bar[bar_index].size;	223	* Untrap the BAR, since guest hasn't configured a
221	if (lo) {	224	* valid GPA
222	new = rounddown(new, size);
223	} else {
224	u32 val = vgpu_cfg_space(vgpu)[rounddown(offset, 8)];
225	/* for 32bit mode bar it returns all-0 in upper 32
226	* bit, for 64bit mode bar it will calculate the
227	* size with lower 32bit and return the corresponding
228	* value
229	*/	225	*/
230	if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
231	new &= (~(size-1)) >> 32;
232	else
233	new = 0;
234	}
235	/*
236	* Unmapp & untrap the BAR, since guest hasn't configured a
237	* valid GPA
238	*/
239	switch (bar_index) {
240	case INTEL_GVT_PCI_BAR_GTTMMIO:
241	ret = trap_gttmmio(vgpu, false);	226	ret = trap_gttmmio(vgpu, false);
242	break;	227	break;
243	case INTEL_GVT_PCI_BAR_APERTURE:	228	case PCI_BASE_ADDRESS_2:
		229	case PCI_BASE_ADDRESS_3:
		230	size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1);
		231	intel_vgpu_write_pci_bar(vgpu, offset,
		232	size >> (lo ? 0 : 32), lo);
244	ret = map_aperture(vgpu, false);	233	ret = map_aperture(vgpu, false);
245	break;	234	break;
		235	default:
		236	/* Unimplemented BARs */
		237	intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false);
246	}	238	}
247	intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
248	} else {	239	} else {
249	/*	240	switch (offset) {
250	* Unmapp & untrap the old BAR first, since guest has	241	case PCI_BASE_ADDRESS_0:
251	* re-configured the BAR	242	case PCI_BASE_ADDRESS_1:
252	*/	243	/*
253	switch (bar_index) {	244	* Untrap the old BAR first, since guest has
254	case INTEL_GVT_PCI_BAR_GTTMMIO:	245	* re-configured the BAR
255	ret = trap_gttmmio(vgpu, false);	246	*/
		247	trap_gttmmio(vgpu, false);
		248	intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
		249	ret = trap_gttmmio(vgpu, mmio_enabled);
256	break;	250	break;
257	case INTEL_GVT_PCI_BAR_APERTURE:	251	case PCI_BASE_ADDRESS_2:
258	ret = map_aperture(vgpu, false);	252	case PCI_BASE_ADDRESS_3:
		253	map_aperture(vgpu, false);
		254	intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
		255	ret = map_aperture(vgpu, mmio_enabled);
259	break;	256	break;
260	}	257	default:
261	intel_vgpu_write_pci_bar(vgpu, offset, new, lo);	258	intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
262	/* Track the new BAR */
263	if (mmio_enabled) {
264	switch (bar_index) {
265	case INTEL_GVT_PCI_BAR_GTTMMIO:
266	ret = trap_gttmmio(vgpu, true);
267	break;
268	case INTEL_GVT_PCI_BAR_APERTURE:
269	ret = map_aperture(vgpu, true);
270	break;
271	}
272	}	259	}
273	}	260	}
274	return ret;	261	return ret;
@@ -299,10 +286,7 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, · 24 unmodified lines
299	}	286	}
300		287
301	switch (rounddown(offset, 4)) {	288	switch (rounddown(offset, 4)) {
302	case PCI_BASE_ADDRESS_0:	289	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
303	case PCI_BASE_ADDRESS_1:
304	case PCI_BASE_ADDRESS_2:
305	case PCI_BASE_ADDRESS_3:
306	if (WARN_ON(!IS_ALIGNED(offset, 4)))	290	if (WARN_ON(!IS_ALIGNED(offset, 4)))
307	return -EINVAL;	291	return -EINVAL;
308	return emulate_pci_bar_write(vgpu, offset, p_data, bytes);	292	return emulate_pci_bar_write(vgpu, offset, p_data, bytes);
@@ -344,7 +328,6 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, · 35 unmodified lines
344	struct intel_gvt *gvt = vgpu->gvt;	328	struct intel_gvt *gvt = vgpu->gvt;
345	const struct intel_gvt_device_info *info = &gvt->device_info;	329	const struct intel_gvt_device_info *info = &gvt->device_info;
346	u16 *gmch_ctl;	330	u16 *gmch_ctl;
347	int i;
348		331
349	memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,	332	memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
350	info->cfg_space_size);	333	info->cfg_space_size);
@@ -371,13 +354,13 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, · 20 unmodified lines
371	*/	354	*/
372	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);	355	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);
373	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);	356	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);
		357	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8);
374	memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);	358	memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
375		359
376	for (i = 0; i < INTEL_GVT_MAX_BAR_NUM; i++) {	360	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =
377	vgpu->cfg_space.bar[i].size = pci_resource_len(	361	pci_resource_len(gvt->dev_priv->drm.pdev, 0);
378	gvt->dev_priv->drm.pdev, i * 2);	362	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =
379	vgpu->cfg_space.bar[i].tracked = false;	363	pci_resource_len(gvt->dev_priv->drm.pdev, 2);
380	}
381	}	364	}
382		365
383	/**	366	/**

drivers/gpu/drm/i915/i915_irq.c+0−3

 								pipe);
 	int position;
 	int vbl_start, vbl_end, hsync_start, htotal, vtotal;
-	bool in_vbl = true;
 	unsigned long irqflags;
 	if (WARN_ON(!mode->crtc_clock)) {
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-	in_vbl = position >= vbl_start && position < vbl_end;
 	/*
 	 * While in vblank, position will be negative
 	 * counting up towards 0 at vbl_end. And outside

drivers/gpu/drm/i915/intel_audio.c+0−5

 			 connector->encoder->base.id,
 			 connector->encoder->name);
-	/* ELD Conn_Type */
-	connector->eld[5] &= ~(3 << 2);
-	if (intel_crtc_has_dp_encoder(crtc_state))
-		connector->eld[5] |= (1 << 2);
 	connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 	if (dev_priv->display.audio_codec_enable)

drivers/gpu/drm/i915/intel_bios.c+7−0

@@ -1163,6 +1163,13 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, · 1162 unmodified lines
1163	is_hdmi = is_dvi && (child->common.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;	1163	is_hdmi = is_dvi && (child->common.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
1164	is_edp = is_dp && (child->common.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);	1164	is_edp = is_dp && (child->common.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
1165		1165
		1166	if (port == PORT_A && is_dvi) {
		1167	DRM_DEBUG_KMS("VBT claims port A supports DVI%s, ignoring\n",
		1168	is_hdmi ? "/HDMI" : "");
		1169	is_dvi = false;
		1170	is_hdmi = false;
		1171	}
		1172
1166	info->supports_dvi = is_dvi;	1173	info->supports_dvi = is_dvi;
1167	info->supports_hdmi = is_hdmi;	1174	info->supports_hdmi = is_hdmi;
1168	info->supports_dp = is_dp;	1175	info->supports_dp = is_dp;

drivers/gpu/drm/i915/intel_csr.c+1−1

@@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) · 215 unmodified lines
216		216
217	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;	217	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
218		218
219	if (IS_BROXTON(dev_priv))	219	if (IS_GEN9_LP(dev_priv))
220	mask \|= DC_STATE_DEBUG_MASK_CORES;	220	mask \|= DC_STATE_DEBUG_MASK_CORES;
221		221
222	/* The below bit doesn't need to be cleared ever afterwards */	222	/* The below bit doesn't need to be cleared ever afterwards */

drivers/gpu/drm/i915/intel_ddi.c+2−1

 out:
 	if (ret && IS_GEN9_LP(dev_priv)) {
 		tmp = I915_READ(BXT_PHY_CTL(port));
-		if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
+		if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
+			    BXT_PHY_LANE_POWERDOWN_ACK |
 			    BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
 			DRM_ERROR("Port %c enabled but PHY powered down? "
 				  "(PHY_CTL %08x)\n", port_name(port), tmp);

drivers/gpu/drm/i915/intel_display.c+1−3

 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 	struct drm_crtc *crtc;
 	struct intel_crtc_state *intel_cstate;
-	bool hw_check = intel_state->modeset;
 	u64 put_domains[I915_MAX_PIPES] = {};
 	unsigned crtc_vblank_mask = 0;
 	int i;
 		if (needs_modeset(new_crtc_state) ||
 		    to_intel_crtc_state(new_crtc_state)->update_pipe) {
-			hw_check = true;
 			put_domains[to_intel_crtc(crtc)->pipe] =
 				modeset_get_crtc_power_domains(crtc,
 		if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
 			DRM_DEBUG_KMS("bad plane %d handle\n", i);
-			return -EINVAL;
+			goto err;
 		}
 		stride_alignment = intel_fb_stride_alignment(fb, i);

drivers/gpu/drm/i915/intel_dpio_phy.c+0−20

@@ -208,12 +208,6 @@ static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = { · 207 unmodified lines
208	},	208	},
209	};	209	};
210		210
211	static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
212	{
213	return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) \|
214	BIT(phy_info->channel[DPIO_CH0].port);
215	}
216
217	static const struct bxt_ddi_phy_info *	211	static const struct bxt_ddi_phy_info *
218	bxt_get_phy_list(struct drm_i915_private dev_priv, int count)	212	bxt_get_phy_list(struct drm_i915_private dev_priv, int count)
219	{	213	{
@@ -313,7 +307,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, · 93 unmodified lines
313	enum dpio_phy phy)	307	enum dpio_phy phy)
314	{	308	{
315	const struct bxt_ddi_phy_info *phy_info;	309	const struct bxt_ddi_phy_info *phy_info;
316	enum port port;
317		310
318	phy_info = bxt_get_phy_info(dev_priv, phy);	311	phy_info = bxt_get_phy_info(dev_priv, phy);
319		312
@@ -335,19 +328,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, · 15 unmodified lines
335	return false;	328	return false;
336	}	329	}
337		330
338	for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
339	u32 tmp = I915_READ(BXT_PHY_CTL(port));
340
341	if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
342	DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
343	"for port %c powered down "
344	"(PHY_CTL %08x)\n",
345	phy, port_name(port), tmp);
346
347	return false;
348	}
349	}
350
351	return true;	331	return true;
352	}	332	}
353		333

drivers/gpu/drm/i915/intel_dsi.c+0−11

 			      struct intel_crtc_state *old_crtc_state,
 			      struct drm_connector_state *old_conn_state)
 {
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 	intel_panel_disable_backlight(old_conn_state);
-	/*
-	 * Disable Device ready before the port shutdown in order
-	 * to avoid split screen
-	 */
-	if (IS_BROXTON(dev_priv)) {
-		for_each_dsi_port(port, intel_dsi->ports)
-			I915_WRITE(MIPI_DEVICE_READY(port), 0);
-	}
 	/*
 	 * According to the spec we should send SHUTDOWN before
 	 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing

drivers/gpu/drm/i915/intel_modes.c+17−0

@@ -30,6 +30,21 @@ · 29 unmodified lines
30	#include "intel_drv.h"	30	#include "intel_drv.h"
31	#include "i915_drv.h"	31	#include "i915_drv.h"
32		32
		33	static void intel_connector_update_eld_conn_type(struct drm_connector *connector)
		34	{
		35	u8 conn_type;
		36
		37	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort \|\|
		38	connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
		39	conn_type = DRM_ELD_CONN_TYPE_DP;
		40	} else {
		41	conn_type = DRM_ELD_CONN_TYPE_HDMI;
		42	}
		43
		44	connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] &= ~DRM_ELD_CONN_TYPE_MASK;
		45	connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] \|= conn_type;
		46	}
		47
33	/**	48	/**
34	* intel_connector_update_modes - update connector from edid	49	* intel_connector_update_modes - update connector from edid
35	* @connector: DRM connector device to use	50	* @connector: DRM connector device to use
@@ -44,6 +59,8 @@ int intel_connector_update_modes(struct drm_connector *connector, · 8 unmodified lines
44	ret = drm_add_edid_modes(connector, edid);	59	ret = drm_add_edid_modes(connector, edid);
45	drm_edid_to_eld(connector, edid);	60	drm_edid_to_eld(connector, edid);
46		61
		62	intel_connector_update_eld_conn_type(connector);
		63
47	return ret;	64	return ret;
48	}	65	}
49		66

drivers/gpu/drm/i915/intel_panel.c+4−0

 	if (!panel->backlight.max)
 		return -ENODEV;
+	panel->backlight.min = get_backlight_min_vbt(connector);
 	val = bxt_get_backlight(connector);
 	val = intel_panel_compute_brightness(connector, val);
 	panel->backlight.level = clamp(val, panel->backlight.min,
 	if (!panel->backlight.max)
 		return -ENODEV;
+	panel->backlight.min = get_backlight_min_vbt(connector);
 	val = bxt_get_backlight(connector);
 	val = intel_panel_compute_brightness(connector, val);
 	panel->backlight.level = clamp(val, panel->backlight.min,

drivers/gpu/drm/i915/intel_runtime_pm.c+3−0

@@ -2782,6 +2782,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume · 2781 unmodified lines
2782		2782
2783	/* 6. Enable DBUF */	2783	/* 6. Enable DBUF */
2784	gen9_dbuf_enable(dev_priv);	2784	gen9_dbuf_enable(dev_priv);
		2785
		2786	if (resume && dev_priv->csr.dmc_payload)
		2787	intel_csr_load_program(dev_priv);
2785	}	2788	}
2786		2789
2787	#undef CNL_PROCMON_IDX	2790	#undef CNL_PROCMON_IDX

drivers/gpu/drm/qxl/qxl_display.c+23−18

 	    .y2 = qfb->base.height
 	};
-	if (!old_state->fb) {
+	if (old_state->fb) {
-		qxl_io_log(qdev,
+		qfb_old = to_qxl_framebuffer(old_state->fb);
-			   "create primary fb: %dx%d,%d,%d\n",
+		bo_old = gem_to_qxl_bo(qfb_old->obj);
-			   bo->surf.width, bo->surf.height,
+	} else {
-			   bo->surf.stride, bo->surf.format);
+		bo_old = NULL;
+	}
-		qxl_io_create_primary(qdev, 0, bo);
+	if (bo == bo_old)
-		bo->is_primary = true;
 		return;
-	} else {
+	if (bo_old && bo_old->is_primary) {
-		qfb_old = to_qxl_framebuffer(old_state->fb);
+		qxl_io_destroy_primary(qdev);
-		bo_old = gem_to_qxl_bo(qfb_old->obj);
 		bo_old->is_primary = false;
 	}
-	bo->is_primary = true;
+	if (!bo->is_primary) {
+		qxl_io_create_primary(qdev, 0, bo);
+		bo->is_primary = true;
+	}
 	qxl_draw_dirty_fb(qdev, qfb, bo, 0, 0, &norect, 1, 1);
 }
 {
 	struct qxl_device *qdev = plane->dev->dev_private;
-	if (old_state->fb)
+	if (old_state->fb) {
-	{	struct qxl_framebuffer *qfb =
+		struct qxl_framebuffer *qfb =
 			to_qxl_framebuffer(old_state->fb);
 		struct qxl_bo *bo = gem_to_qxl_bo(qfb->obj);
-		qxl_io_destroy_primary(qdev);
+		if (bo->is_primary) {
-		bo->is_primary = false;
+			qxl_io_destroy_primary(qdev);
+			bo->is_primary = false;
+		}
 	}
 }
 	struct drm_gem_object *obj;
 	struct qxl_bo *user_bo;
-	if (!plane->state->fb) {
+	if (!old_state->fb) {
-		/* we never executed prepare_fb, so there's nothing to
+		/*
+		 * we never executed prepare_fb, so there's nothing to
 		 * unpin.
 		 */
 		return;
 	}
-	obj = to_qxl_framebuffer(plane->state->fb)->obj;
+	obj = to_qxl_framebuffer(old_state->fb)->obj;
 	user_bo = gem_to_qxl_bo(obj);
 	qxl_bo_unpin(user_bo);
 }

drivers/gpu/drm/radeon/radeon_device.c+1−1

@@ -1663,7 +1663,7 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, · 1662 unmodified lines
1663	radeon_agp_suspend(rdev);	1663	radeon_agp_suspend(rdev);
1664		1664
1665	pci_save_state(dev->pdev);	1665	pci_save_state(dev->pdev);
1666	if (freeze && rdev->family >= CHIP_CEDAR) {	1666	if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
1667	rdev->asic->asic_reset(rdev, true);	1667	rdev->asic->asic_reset(rdev, true);
1668	pci_restore_state(dev->pdev);	1668	pci_restore_state(dev->pdev);
1669	} else if (suspend) {	1669	} else if (suspend) {

drivers/gpu/drm/sun4i/Kconfig+1−1

@@ -26,7 +26,7 @@ config DRM_SUN4I_HDMI_CEC · 25 unmodified lines
26	bool "Allwinner A10 HDMI CEC Support"	26	bool "Allwinner A10 HDMI CEC Support"
27	depends on DRM_SUN4I_HDMI	27	depends on DRM_SUN4I_HDMI
28	select CEC_CORE	28	select CEC_CORE
29	depends on CEC_PIN	29	select CEC_PIN
30	help	30	help
31	Choose this option if you have an Allwinner SoC with an HDMI	31	Choose this option if you have an Allwinner SoC with an HDMI
32	controller and want to use CEC.	32	controller and want to use CEC.

drivers/gpu/drm/sun4i/sun4i_hdmi.h+1−1

@@ -15,7 +15,7 @@ · 14 unmodified lines
15	#include <drm/drm_connector.h>	15	#include <drm/drm_connector.h>
16	#include <drm/drm_encoder.h>	16	#include <drm/drm_encoder.h>
17		17
18	#include <media/cec.h>	18	#include <media/cec-pin.h>
19		19
20	#define SUN4I_HDMI_CTRL_REG 0x004	20	#define SUN4I_HDMI_CTRL_REG 0x004
21	#define SUN4I_HDMI_CTRL_ENABLE BIT(31)	21	#define SUN4I_HDMI_CTRL_ENABLE BIT(31)

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c+14−5

 	hdmi->mod_clk = devm_clk_get(dev, "mod");
 	if (IS_ERR(hdmi->mod_clk)) {
 		dev_err(dev, "Couldn't get the HDMI mod clock\n");
-		return PTR_ERR(hdmi->mod_clk);
+		ret = PTR_ERR(hdmi->mod_clk);
+		goto err_disable_bus_clk;
 	}
 	clk_prepare_enable(hdmi->mod_clk);
 	hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
 	if (IS_ERR(hdmi->pll0_clk)) {
 		dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
-		return PTR_ERR(hdmi->pll0_clk);
+		ret = PTR_ERR(hdmi->pll0_clk);
+		goto err_disable_mod_clk;
 	}
 	hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
 	if (IS_ERR(hdmi->pll1_clk)) {
 		dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
-		return PTR_ERR(hdmi->pll1_clk);
+		ret = PTR_ERR(hdmi->pll1_clk);
+		goto err_disable_mod_clk;
 	}
 	ret = sun4i_tmds_create(hdmi);
 	if (ret) {
 		dev_err(dev, "Couldn't create the TMDS clock\n");
-		return ret;
+		goto err_disable_mod_clk;
 	}
 	writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
 	ret = sun4i_hdmi_i2c_create(dev, hdmi);
 	if (ret) {
 		dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
-		return ret;
+		goto err_disable_mod_clk;
 	}
 	drm_encoder_helper_add(&hdmi->encoder,
 	drm_encoder_cleanup(&hdmi->encoder);
 err_del_i2c_adapter:
 	i2c_del_adapter(hdmi->i2c);
+err_disable_mod_clk:
+	clk_disable_unprepare(hdmi->mod_clk);
+err_disable_bus_clk:
+	clk_disable_unprepare(hdmi->bus_clk);
 	return ret;
 }
 	drm_connector_cleanup(&hdmi->connector);
 	drm_encoder_cleanup(&hdmi->encoder);
 	i2c_del_adapter(hdmi->i2c);
+	clk_disable_unprepare(hdmi->mod_clk);
+	clk_disable_unprepare(hdmi->bus_clk);
 }
 static const struct component_ops sun4i_hdmi_ops = {

drivers/gpu/drm/tegra/trace.h+1−1

@@ -63,6 +63,6 @@ DEFINE_EVENT(register_access, sor_readl, · 62 unmodified lines
63		63
64	/* This part must be outside protection */	64	/* This part must be outside protection */
65	#undef TRACE_INCLUDE_PATH	65	#undef TRACE_INCLUDE_PATH
66	#define TRACE_INCLUDE_PATH .	66	#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/tegra
67	#define TRACE_INCLUDE_FILE trace	67	#define TRACE_INCLUDE_FILE trace
68	#include <trace/define_trace.h>	68	#include <trace/define_trace.h>

drivers/hid/hid-ids.h+2−0

 #define USB_VENDOR_ID_IDEACOM		0x1cb6
 #define USB_DEVICE_ID_IDEACOM_IDC6650	0x6650
 #define USB_DEVICE_ID_IDEACOM_IDC6651	0x6651
+#define USB_DEVICE_ID_IDEACOM_IDC6680	0x6680
 #define USB_VENDOR_ID_ILITEK		0x222a
 #define USB_DEVICE_ID_ILITEK_MULTITOUCH	0x0001
 #define USB_DEVICE_ID_LENOVO_CBTKBD	0x6048
 #define USB_DEVICE_ID_LENOVO_TPPRODOCK	0x6067
 #define USB_DEVICE_ID_LENOVO_X1_COVER	0x6085
+#define USB_DEVICE_ID_LENOVO_X1_TAB	0x60a3
 #define USB_VENDOR_ID_LG		0x1fd2
 #define USB_DEVICE_ID_LG_MULTITOUCH	0x0064

drivers/hid/hid-multitouch.c+7−0

 	    field->application != HID_DG_PEN &&
 	    field->application != HID_DG_TOUCHPAD &&
 	    field->application != HID_GD_KEYBOARD &&
+	    field->application != HID_GD_SYSTEM_CONTROL &&
 	    field->application != HID_CP_CONSUMER_CONTROL &&
 	    field->application != HID_GD_WIRELESS_RADIO_CTLS &&
 	    !(field->application == HID_VD_ASUS_CUSTOM_MEDIA_KEYS &&
 			USB_VENDOR_ID_ALPS_JP,
 			HID_DEVICE_ID_ALPS_U1_DUAL_3BTN_PTP) },
+	/* Lenovo X1 TAB Gen 2 */
+	{ .driver_data = MT_CLS_WIN_8_DUAL,
+		HID_DEVICE(BUS_USB, HID_GROUP_MULTITOUCH_WIN_8,
+			   USB_VENDOR_ID_LENOVO,
+			   USB_DEVICE_ID_LENOVO_X1_TAB) },
 	/* Anton devices */
 	{ .driver_data = MT_CLS_EXPORT_ALL_INPUTS,
 		MT_USB_DEVICE(USB_VENDOR_ID_ANTON,

drivers/hid/hid-rmi.c+10−3

 	if (!(data->device_flags & RMI_DEVICE))
 		return 0;
-	ret = rmi_reset_attn_mode(hdev);
+	/* Make sure the HID device is ready to receive events */
+	ret = hid_hw_open(hdev);
 	if (ret)
 		return ret;
+	ret = rmi_reset_attn_mode(hdev);
+	if (ret)
+		goto out;
 	ret = rmi_driver_resume(rmi_dev, false);
 	if (ret) {
 		hid_warn(hdev, "Failed to resume device: %d\n", ret);
-		return ret;
+		goto out;
 	}
-	return 0;
+out:
+	hid_hw_close(hdev);
+	return ret;
 }
 #endif /* CONFIG_PM */

drivers/hid/hidraw.c+1−1

 			kfree(hidraw);
 		} else {
 			/* close device for last reader */
-			hid_hw_power(hidraw->hid, PM_HINT_NORMAL);
 			hid_hw_close(hidraw->hid);
+			hid_hw_power(hidraw->hid, PM_HINT_NORMAL);
 		}
 	}
 }

drivers/hid/i2c-hid/i2c-hid.c+2−1

 {
 	/* the worst case is computed from the set_report command with a
 	 * reportID > 15 and the maximum report length */
-	int args_len = sizeof(__u8) + /* optional ReportID byte */
+	int args_len = sizeof(__u8) + /* ReportID */
+		       sizeof(__u8) + /* optional ReportID byte */
 		       sizeof(__u16) + /* data register */
 		       sizeof(__u16) + /* size of the report */
 		       report_size; /* report */

drivers/hid/usbhid/hid-quirks.c+1−0

@@ -99,6 +99,7 @@ static const struct hid_blacklist { · 98 unmodified lines
99	{ USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A, HID_QUIRK_ALWAYS_POLL },	99	{ USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A, HID_QUIRK_ALWAYS_POLL },
100	{ USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A, HID_QUIRK_ALWAYS_POLL },	100	{ USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A, HID_QUIRK_ALWAYS_POLL },
101	{ USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE, HID_QUIRK_ALWAYS_POLL },	101	{ USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE, HID_QUIRK_ALWAYS_POLL },
		102	{ USB_VENDOR_ID_IDEACOM, USB_DEVICE_ID_IDEACOM_IDC6680, HID_QUIRK_MULTI_INPUT },
102	{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C007, HID_QUIRK_ALWAYS_POLL },	103	{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C007, HID_QUIRK_ALWAYS_POLL },
103	{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C077, HID_QUIRK_ALWAYS_POLL },	104	{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C077, HID_QUIRK_ALWAYS_POLL },
104	{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_KEYBOARD_G710_PLUS, HID_QUIRK_NOGET },	105	{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_KEYBOARD_G710_PLUS, HID_QUIRK_NOGET },

drivers/hid/wacom_sys.c+6−1

 	/* Try to find an already-probed interface from the same device */
 	list_for_each_entry(data, &wacom_udev_list, list) {
-		if (compare_device_paths(hdev, data->dev, '/'))
+		if (compare_device_paths(hdev, data->dev, '/')) {
+			kref_get(&data->kref);
 			return data;
+		}
 	}
 	/* Fallback to finding devices that appear to be "siblings" */
 	if (!wacom->led.groups)
 		return -ENOTSUPP;
+	if (wacom->wacom_wac.features.type == REMOTE)
+		return -ENOTSUPP;
 	if (wacom->wacom_wac.pid) { /* wireless connected */
 		report_id = WAC_CMD_WL_LED_CONTROL;
 		buf_size = 13;

drivers/hid/wacom_wac.c+89−21

 				keys = data[9] & 0x07;
 			}
 		} else {
-			buttons = ((data[6] & 0x10) << 10) |
+			buttons = ((data[6] & 0x10) << 5)  |
-			          ((data[5] & 0x10) << 9)  |
+			          ((data[5] & 0x10) << 4)  |
 			          ((data[6] & 0x0F) << 4)  |
 			          (data[5] & 0x0F);
 		}
 			continue;
 		if (range) {
+			/* Fix rotation alignment: userspace expects zero at left */
+			int16_t rotation = (int16_t)get_unaligned_le16(&frame[9]);
+			rotation += 1800/4;
+			if (rotation > 899)
+				rotation -= 1800;
 			input_report_abs(pen_input, ABS_X, get_unaligned_le16(&frame[1]));
 			input_report_abs(pen_input, ABS_Y, get_unaligned_le16(&frame[3]));
-			input_report_abs(pen_input, ABS_TILT_X, frame[7]);
+			input_report_abs(pen_input, ABS_TILT_X, (char)frame[7]);
-			input_report_abs(pen_input, ABS_TILT_Y, frame[8]);
+			input_report_abs(pen_input, ABS_TILT_Y, (char)frame[8]);
-			input_report_abs(pen_input, ABS_Z, get_unaligned_le16(&frame[9]));
+			input_report_abs(pen_input, ABS_Z, rotation);
 			input_report_abs(pen_input, ABS_WHEEL, get_unaligned_le16(&frame[11]));
 		}
 		input_report_abs(pen_input, ABS_PRESSURE, get_unaligned_le16(&frame[5]));
 	unsigned char *data = wacom->data;
 	int buttons = (data[282] << 1) | ((data[281] >> 6) & 0x01);
-	int ring = data[285];
+	int ring = data[285] & 0x7F;
-	int prox = buttons | (ring & 0x80);
+	bool ringstatus = data[285] & 0x80;
+	bool prox = buttons || ringstatus;
+	/* Fix touchring data: userspace expects 0 at left and increasing clockwise */
+	ring = 71 - ring;
+	ring += 3*72/16;
+	if (ring > 71)
+		ring -= 72;
 	wacom_report_numbered_buttons(pad_input, 9, buttons);
-	input_report_abs(pad_input, ABS_WHEEL, (ring & 0x80) ? (ring & 0x7f) : 0);
+	input_report_abs(pad_input, ABS_WHEEL, ringstatus ? ring : 0);
 	input_report_key(pad_input, wacom->tool[1], prox ? 1 : 0);
 	input_report_abs(pad_input, ABS_MISC, prox ? PAD_DEVICE_ID : 0);
 	return 0;
 }
+static int wacom_offset_rotation(struct input_dev *input, struct hid_usage *usage,
+				 int value, int num, int denom)
+{
+	struct input_absinfo *abs = &input->absinfo[usage->code];
+	int range = (abs->maximum - abs->minimum + 1);
+	value += num*range/denom;
+	if (value > abs->maximum)
+		value -= range;
+	else if (value < abs->minimum)
+		value += range;
+	return value;
+}
 int wacom_equivalent_usage(int usage)
 {
 	if ((usage & HID_USAGE_PAGE) == WACOM_HID_UP_WACOMDIGITIZER) {
 	unsigned equivalent_usage = wacom_equivalent_usage(usage->hid);
 	int i;
 	bool is_touch_on = value;
+	bool do_report = false;
 	/*
 	 * Avoid reporting this event and setting inrange_state if this usage
 	}
 	switch (equivalent_usage) {
+	case WACOM_HID_WD_TOUCHRING:
+		/*
+		 * Userspace expects touchrings to increase in value with
+		 * clockwise gestures and have their zero point at the
+		 * tablet's left. HID events "should" be clockwise-
+		 * increasing and zero at top, though the MobileStudio
+		 * Pro and 2nd-gen Intuos Pro don't do this...
+		 */
+		if (hdev->vendor == 0x56a &&
+		    (hdev->product == 0x34d || hdev->product == 0x34e ||  /* MobileStudio Pro */
+		     hdev->product == 0x357 || hdev->product == 0x358)) { /* Intuos Pro 2 */
+			value = (field->logical_maximum - value);
+			if (hdev->product == 0x357 || hdev->product == 0x358)
+				value = wacom_offset_rotation(input, usage, value, 3, 16);
+			else if (hdev->product == 0x34d || hdev->product == 0x34e)
+				value = wacom_offset_rotation(input, usage, value, 1, 2);
+		}
+		else {
+			value = wacom_offset_rotation(input, usage, value, 1, 4);
+		}
+		do_report = true;
+		break;
 	case WACOM_HID_WD_TOUCHRINGSTATUS:
 		if (!value)
 			input_event(input, usage->type, usage->code, 0);
 					 value, i);
 		 /* fall through*/
 	default:
+		do_report = true;
+		break;
+	}
+	if (do_report) {
 		input_event(input, usage->type, usage->code, value);
 		if (value)
 			wacom_wac->hid_data.pad_input_event_flag = true;
-		break;
 	}
 }
 		wacom_wac->hid_data.tipswitch |= value;
 		return;
 	case HID_DG_TOOLSERIALNUMBER:
-		wacom_wac->serial[0] = (wacom_wac->serial[0] & ~0xFFFFFFFFULL);
+		if (value) {
-		wacom_wac->serial[0] |= (__u32)value;
+			wacom_wac->serial[0] = (wacom_wac->serial[0] & ~0xFFFFFFFFULL);
+			wacom_wac->serial[0] |= (__u32)value;
+		}
 		return;
+	case HID_DG_TWIST:
+		/*
+		 * Userspace expects pen twist to have its zero point when
+		 * the buttons/finger is on the tablet's left. HID values
+		 * are zero when buttons are toward the top.
+		 */
+		value = wacom_offset_rotation(input, usage, value, 1, 4);
+		break;
 	case WACOM_HID_WD_SENSE:
 		wacom_wac->hid_data.sense_state = value;
 		return;
 	case WACOM_HID_WD_SERIALHI:
-		wacom_wac->serial[0] = (wacom_wac->serial[0] & 0xFFFFFFFF);
+		if (value) {
-		wacom_wac->serial[0] |= ((__u64)value) << 32;
+			wacom_wac->serial[0] = (wacom_wac->serial[0] & 0xFFFFFFFF);
-		/*
+			wacom_wac->serial[0] |= ((__u64)value) << 32;
-		 * Non-USI EMR devices may contain additional tool type
+			/*
-		 * information here. See WACOM_HID_WD_TOOLTYPE case for
+			 * Non-USI EMR devices may contain additional tool type
-		 * more details.
+			 * information here. See WACOM_HID_WD_TOOLTYPE case for
-		 */
+			 * more details.
-		if (value >> 20 == 1) {
+			 */
-			wacom_wac->id[0] |= value & 0xFFFFF;
+			if (value >> 20 == 1) {
+				wacom_wac->id[0] |= value & 0xFFFFF;
+			}
 		}
 		return;
 	case WACOM_HID_WD_TOOLTYPE:
 		input_report_key(input, wacom_wac->tool[0], prox);
 		if (wacom_wac->serial[0]) {
 			input_event(input, EV_MSC, MSC_SERIAL, wacom_wac->serial[0]);
-			input_report_abs(input, ABS_MISC, id);
+			input_report_abs(input, ABS_MISC, prox ? id : 0);
 		}
 		wacom_wac->hid_data.tipswitch = false;
 	if (!prox) {
 		wacom_wac->tool[0] = 0;
 		wacom_wac->id[0] = 0;
+		wacom_wac->serial[0] = 0;
 	}
 }

drivers/hv/channel_mgmt.c+0−4

 void vmbus_hvsock_device_unregister(struct vmbus_channel *channel)
 {
-	mutex_lock(&vmbus_connection.channel_mutex);
 	BUG_ON(!is_hvsock_channel(channel));
 	channel->rescind = true;
 	vmbus_device_unregister(channel->device_obj);
-	mutex_unlock(&vmbus_connection.channel_mutex);
 }
 EXPORT_SYMBOL_GPL(vmbus_hvsock_device_unregister);

drivers/hv/hv_fcopy.c+4−0

 		out_src = smsg_out;
 		break;
+	case WRITE_TO_FILE:
+		out_src = fcopy_transaction.fcopy_msg;
+		out_len = sizeof(struct hv_do_fcopy);
+		break;
 	default:
 		out_src = fcopy_transaction.fcopy_msg;
 		out_len = fcopy_transaction.recv_len;

drivers/hwmon/xgene-hwmon.c+11−8

 			 sizeof(struct slimpro_resp_msg) * ASYNC_MSG_FIFO_SIZE,
 			 GFP_KERNEL);
 	if (rc)
-		goto out_mbox_free;
+		return -ENOMEM;
 	INIT_WORK(&ctx->workq, xgene_hwmon_evt_work);
 		if (IS_ERR(ctx->mbox_chan)) {
 			dev_err(&pdev->dev,
 				"SLIMpro mailbox channel request failed\n");
-			return -ENODEV;
+			rc = -ENODEV;
+			goto out_mbox_free;
 		}
 	} else {
 		struct acpi_pcct_hw_reduced *cppc_ss;
 		if (device_property_read_u32(&pdev->dev, "pcc-channel",
 					     &ctx->mbox_idx)) {
 			dev_err(&pdev->dev, "no pcc-channel property\n");
-			return -ENODEV;
+			rc = -ENODEV;
+			goto out_mbox_free;
 		}
 		cl->rx_callback = xgene_hwmon_pcc_rx_cb;
 		if (IS_ERR(ctx->mbox_chan)) {
 			dev_err(&pdev->dev,
 				"PPC channel request failed\n");
-			return -ENODEV;
+			rc = -ENODEV;
+			goto out_mbox_free;
 		}
 		/*
 		if (!cppc_ss) {
 			dev_err(&pdev->dev, "PPC subspace not found\n");
 			rc = -ENODEV;
-			goto out_mbox_free;
+			goto out;
 		}
 		if (!ctx->mbox_chan->mbox->txdone_irq) {
 			dev_err(&pdev->dev, "PCC IRQ not supported\n");
 			rc = -ENODEV;
-			goto out_mbox_free;
+			goto out;
 		}
 		/*
 		} else {
 			dev_err(&pdev->dev, "Failed to get PCC comm region\n");
 			rc = -ENODEV;
-			goto out_mbox_free;
+			goto out;
 		}
 		if (!ctx->pcc_comm_addr) {
 			dev_err(&pdev->dev,
 				"Failed to ioremap PCC comm region\n");
 			rc = -ENOMEM;
-			goto out_mbox_free;
+			goto out;
 		}
 		/*

drivers/hwtracing/intel_th/pci.c+10−0

 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x19e1),
 		.driver_data = (kernel_ulong_t)0,
 	},
+	{
+		/* Lewisburg PCH */
+		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa1a6),
+		.driver_data = (kernel_ulong_t)0,
+	},
 	{
 		/* Gemini Lake */
 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x318e),
 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9da6),
 		.driver_data = (kernel_ulong_t)&intel_th_2x,
 	},
+	{
+		/* Cedar Fork PCH */
+		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x18e1),
+		.driver_data = (kernel_ulong_t)&intel_th_2x,
+	},
 	{ 0 },
 };

drivers/hwtracing/stm/core.c+1−1

@@ -1119,7 +1119,7 @@ void stm_source_unregister_device(struct stm_source_data *data) · 1118 unmodified lines
1119		1119
1120	stm_source_link_drop(src);	1120	stm_source_link_drop(src);
1121		1121
1122	device_destroy(&stm_source_class, src->dev.devt);	1122	device_unregister(&src->dev);
1123	}	1123	}
1124	EXPORT_SYMBOL_GPL(stm_source_unregister_device);	1124	EXPORT_SYMBOL_GPL(stm_source_unregister_device);
1125		1125

drivers/i2c/busses/Kconfig+1−0

@@ -131,6 +131,7 @@ config I2C_I801 · 130 unmodified lines
131	Gemini Lake (SOC)	131	Gemini Lake (SOC)
132	Cannon Lake-H (PCH)	132	Cannon Lake-H (PCH)
133	Cannon Lake-LP (PCH)	133	Cannon Lake-LP (PCH)
		134	Cedar Fork (PCH)
134		135
135	This driver can also be built as a module. If so, the module	136	This driver can also be built as a module. If so, the module
136	will be called i2c-i801.	137	will be called i2c-i801.

drivers/i2c/busses/i2c-i801.c+4−0

  * Gemini Lake (SOC)		0x31d4	32	hard	yes	yes	yes
  * Cannon Lake-H (PCH)		0xa323	32	hard	yes	yes	yes
  * Cannon Lake-LP (PCH)		0x9da3	32	hard	yes	yes	yes
+ * Cedar Fork (PCH)		0x18df	32	hard	yes	yes	yes
  *
  * Features supported by this driver:
  * Software PEC				no
 /* Older devices have their ID defined in <linux/pci_ids.h> */
 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS		0x0f12
+#define PCI_DEVICE_ID_INTEL_CDF_SMBUS			0x18df
 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS			0x19df
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS		0x1c22
 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS		0x1d22
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
 	case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
 	case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
 	case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
+	case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
 	case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
 	case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
 		priv->features |= FEATURE_I2C_BLOCK_READ;

drivers/i2c/busses/i2c-img-scb.c+1−1

@@ -1459,6 +1459,6 @@ static struct platform_driver img_scb_i2c_driver = { · 1458 unmodified lines
1459	};	1459	};
1460	module_platform_driver(img_scb_i2c_driver);	1460	module_platform_driver(img_scb_i2c_driver);
1461		1461
1462	MODULE_AUTHOR("James Hogan <james.hogan@imgtec.com>");	1462	MODULE_AUTHOR("James Hogan <jhogan@kernel.org>");
1463	MODULE_DESCRIPTION("IMG host I2C driver");	1463	MODULE_DESCRIPTION("IMG host I2C driver");
1464	MODULE_LICENSE("GPL v2");	1464	MODULE_LICENSE("GPL v2");

drivers/i2c/busses/i2c-sprd.c+1−0

@@ -627,6 +627,7 @@ static const struct dev_pm_ops sprd_i2c_pm_ops = { · 626 unmodified lines
627		627
628	static const struct of_device_id sprd_i2c_of_match[] = {	628	static const struct of_device_id sprd_i2c_of_match[] = {
629	{ .compatible = "sprd,sc9860-i2c", },	629	{ .compatible = "sprd,sc9860-i2c", },
		630	{},
630	};	631	};
631		632
632	static struct platform_driver sprd_i2c_driver = {	633	static struct platform_driver sprd_i2c_driver = {

drivers/i2c/busses/i2c-stm32f7.c+7−10

 	unsigned int msg_num;
 	unsigned int msg_id;
 	struct stm32f7_i2c_msg f7_msg;
-	struct stm32f7_i2c_setup *setup;
+	struct stm32f7_i2c_setup setup;
 	struct stm32f7_i2c_timings timing;
 };
 	},
 };
-struct stm32f7_i2c_setup stm32f7_setup = {
+static const struct stm32f7_i2c_setup stm32f7_setup = {
 	.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 	.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 	.dnf = STM32F7_I2C_DNF_DEFAULT,
 	writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
 	/* Enable I2C */
-	if (i2c_dev->setup->analog_filter)
+	if (i2c_dev->setup.analog_filter)
 		stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 				     STM32F7_I2C_CR1_ANFOFF);
 	else
 	}
 	setup = of_device_get_match_data(&pdev->dev);
-	i2c_dev->setup->rise_time = setup->rise_time;
+	i2c_dev->setup = *setup;
-	i2c_dev->setup->fall_time = setup->fall_time;
-	i2c_dev->setup->dnf = setup->dnf;
-	i2c_dev->setup->analog_filter = setup->analog_filter;
 	ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
 				       &rise_time);
 	if (!ret)
-		i2c_dev->setup->rise_time = rise_time;
+		i2c_dev->setup.rise_time = rise_time;
 	ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
 				       &fall_time);
 	if (!ret)
-		i2c_dev->setup->fall_time = fall_time;
+		i2c_dev->setup.fall_time = fall_time;
-	ret = stm32f7_i2c_setup_timing(i2c_dev, i2c_dev->setup);
+	ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
 	if (ret)
 		goto clk_free;

drivers/ide/ide-probe.c+1−0

@@ -1451,6 +1451,7 @@ int ide_host_register(struct ide_host host, const struct ide_port_info d, · 1450 unmodified lines
1451	if (hwif_init(hwif) == 0) {	1451	if (hwif_init(hwif) == 0) {
1452	printk(KERN_INFO "%s: failed to initialize IDE "	1452	printk(KERN_INFO "%s: failed to initialize IDE "
1453	"interface\n", hwif->name);	1453	"interface\n", hwif->name);
		1454	device_unregister(hwif->portdev);
1454	device_unregister(&hwif->gendev);	1455	device_unregister(&hwif->gendev);
1455	ide_disable_port(hwif);	1456	ide_disable_port(hwif);
1456	continue;	1457	continue;

drivers/ide/ide-scan-pci.c+9−4

 {
 	struct list_head *l;
 	struct pci_driver *d;
+	int ret;
 	list_for_each(l, &ide_pci_drivers) {
 		d = list_entry(l, struct pci_driver, node);
 			const struct pci_device_id *id =
 				pci_match_id(d->id_table, dev);
-			if (id != NULL && d->probe(dev, id) >= 0) {
+			if (id != NULL) {
-				dev->driver = d;
+				pci_assign_irq(dev);
-				pci_dev_get(dev);
+				ret = d->probe(dev, id);
-				return 1;
+				if (ret >= 0) {
+					dev->driver = d;
+					pci_dev_get(dev);
+					return 1;
+				}
 			}
 		}
 	}

drivers/ide/setup-pci.c+40−23

 /**
  *	ide_pci_enable	-	do PCI enables
  *	@dev: PCI device
+ *	@bars: PCI BARs mask
  *	@d: IDE port info
  *
  *	Enable the IDE PCI device. We attempt to enable the device in full
  *	Returns zero on success or an error code
  */
-static int ide_pci_enable(struct pci_dev *dev, const struct ide_port_info *d)
+static int ide_pci_enable(struct pci_dev *dev, int bars,
+			  const struct ide_port_info *d)
 {
-	int ret, bars;
+	int ret;
 	if (pci_enable_device(dev)) {
 		ret = pci_enable_device_io(dev);
 		goto out;
 	}
-	if (d->host_flags & IDE_HFLAG_SINGLE)
-		bars = (1 << 2) - 1;
-	else
-		bars = (1 << 4) - 1;
-	if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) {
-		if (d->host_flags & IDE_HFLAG_CS5520)
-			bars |= (1 << 2);
-		else
-			bars |= (1 << 4);
-	}
 	ret = pci_request_selected_regions(dev, bars, d->name);
 	if (ret < 0)
 		printk(KERN_ERR "%s %s: can't reserve resources\n",
 /**
  *	ide_setup_pci_controller	-	set up IDE PCI
  *	@dev: PCI device
+ *	@bars: PCI BARs mask
  *	@d: IDE port info
  *	@noisy: verbose flag
  *
  *	and enables it if need be
  */
-static int ide_setup_pci_controller(struct pci_dev *dev,
+static int ide_setup_pci_controller(struct pci_dev *dev, int bars,
 				    const struct ide_port_info *d, int noisy)
 {
 	int ret;
 	if (noisy)
 		ide_setup_pci_noise(dev, d);
-	ret = ide_pci_enable(dev, d);
+	ret = ide_pci_enable(dev, bars, d);
 	if (ret < 0)
 		goto out;
 	if (ret < 0) {
 		printk(KERN_ERR "%s %s: error accessing PCI regs\n",
 			d->name, pci_name(dev));
-		goto out;
+		goto out_free_bars;
 	}
 	if (!(pcicmd & PCI_COMMAND_IO)) {	/* is device disabled? */
 		ret = ide_pci_configure(dev, d);
 		if (ret < 0)
-			goto out;
+			goto out_free_bars;
 		printk(KERN_INFO "%s %s: device enabled (Linux)\n",
 			d->name, pci_name(dev));
 	}
+	goto out;
+out_free_bars:
+	pci_release_selected_regions(dev, bars);
 out:
 	return ret;
 }
 {
 	struct pci_dev *pdev[] = { dev1, dev2 };
 	struct ide_host *host;
-	int ret, i, n_ports = dev2 ? 4 : 2;
+	int ret, i, n_ports = dev2 ? 4 : 2, bars;
 	struct ide_hw hw[4], *hws[] = { NULL, NULL, NULL, NULL };
+	if (d->host_flags & IDE_HFLAG_SINGLE)
+		bars = (1 << 2) - 1;
+	else
+		bars = (1 << 4) - 1;
+	if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) {
+		if (d->host_flags & IDE_HFLAG_CS5520)
+			bars |= (1 << 2);
+		else
+			bars |= (1 << 4);
+	}
 	for (i = 0; i < n_ports / 2; i++) {
-		ret = ide_setup_pci_controller(pdev[i], d, !i);
+		ret = ide_setup_pci_controller(pdev[i], bars, d, !i);
-		if (ret < 0)
+		if (ret < 0) {
+			if (i == 1)
+				pci_release_selected_regions(pdev[0], bars);
 			goto out;
+		}
 		ide_pci_setup_ports(pdev[i], d, &hw[i*2], &hws[i*2]);
 	}
 	host = ide_host_alloc(d, hws, n_ports);
 	if (host == NULL) {
 		ret = -ENOMEM;
-		goto out;
+		goto out_free_bars;
 	}
 	host->dev[0] = &dev1->dev;
 		 * do_ide_setup_pci_device() on the first device!
 		 */
 		if (ret < 0)
-			goto out;
+			goto out_free_bars;
 		/* fixup IRQ */
 		if (ide_pci_is_in_compatibility_mode(pdev[i])) {
 	ret = ide_host_register(host, d, hws);
 	if (ret)
 		ide_host_free(host);
+	else
+		goto out;
+out_free_bars:
+	i = n_ports / 2;
+	while (i--)
+		pci_release_selected_regions(pdev[i], bars);
 out:
 	return ret;
 }

drivers/iio/adc/ad7793.c+2−2

@@ -257,7 +257,7 @@ static int ad7793_setup(struct iio_dev *indio_dev, · 256 unmodified lines
257	unsigned int vref_mv)	257	unsigned int vref_mv)
258	{	258	{
259	struct ad7793_state *st = iio_priv(indio_dev);	259	struct ad7793_state *st = iio_priv(indio_dev);
260	int i, ret = -1;	260	int i, ret;
261	unsigned long long scale_uv;	261	unsigned long long scale_uv;
262	u32 id;	262	u32 id;
263		263
@@ -266,7 +266,7 @@ static int ad7793_setup(struct iio_dev *indio_dev, · 2 unmodified lines
266	return ret;	266	return ret;
267		267
268	/* reset the serial interface */	268	/* reset the serial interface */
269	ret = spi_write(st->sd.spi, (u8 *)&ret, sizeof(ret));	269	ret = ad_sd_reset(&st->sd, 32);
270	if (ret < 0)	270	if (ret < 0)
271	goto out;	271	goto out;
272	usleep_range(500, 2000); /* Wait for at least 500us */	272	usleep_range(500, 2000); /* Wait for at least 500us */

drivers/iio/adc/ad_sigma_delta.c+28−0

@@ -177,6 +177,34 @@ out: · 176 unmodified lines
177	}	177	}
178	EXPORT_SYMBOL_GPL(ad_sd_read_reg);	178	EXPORT_SYMBOL_GPL(ad_sd_read_reg);
179		179
		180	/**
		181	* ad_sd_reset() - Reset the serial interface
		182	*
		183	* @sigma_delta: The sigma delta device
		184	* @reset_length: Number of SCLKs with DIN = 1
		185	*
		186	* Returns 0 on success, an error code otherwise.
		187	**/
		188	int ad_sd_reset(struct ad_sigma_delta *sigma_delta,
		189	unsigned int reset_length)
		190	{
		191	uint8_t *buf;
		192	unsigned int size;
		193	int ret;
		194
		195	size = DIV_ROUND_UP(reset_length, 8);
		196	buf = kcalloc(size, sizeof(*buf), GFP_KERNEL);
		197	if (!buf)
		198	return -ENOMEM;
		199
		200	memset(buf, 0xff, size);
		201	ret = spi_write(sigma_delta->spi, buf, size);
		202	kfree(buf);
		203
		204	return ret;
		205	}
		206	EXPORT_SYMBOL_GPL(ad_sd_reset);
		207
180	static int ad_sd_calibrate(struct ad_sigma_delta *sigma_delta,	208	static int ad_sd_calibrate(struct ad_sigma_delta *sigma_delta,
181	unsigned int mode, unsigned int channel)	209	unsigned int mode, unsigned int channel)
182	{	210	{

drivers/iio/adc/mcp320x.c+16−9

  * MCP3204
  * MCP3208
  * ------------
+ * 13 bit converter
+ * MCP3301
  *
  * Datasheet can be found here:
  * http://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf  mcp3001
 }
 static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel,
-				  bool differential, int device_index)
+				  bool differential, int device_index, int *val)
 {
 	int ret;
 	switch (device_index) {
 	case mcp3001:
-		return (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3);
+		*val = (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3);
+		return 0;
 	case mcp3002:
 	case mcp3004:
 	case mcp3008:
-		return (adc->rx_buf[0] << 2 | adc->rx_buf[1] >> 6);
+		*val = (adc->rx_buf[0] << 2 | adc->rx_buf[1] >> 6);
+		return 0;
 	case mcp3201:
-		return (adc->rx_buf[0] << 7 | adc->rx_buf[1] >> 1);
+		*val = (adc->rx_buf[0] << 7 | adc->rx_buf[1] >> 1);
+		return 0;
 	case mcp3202:
 	case mcp3204:
 	case mcp3208:
-		return (adc->rx_buf[0] << 4 | adc->rx_buf[1] >> 4);
+		*val = (adc->rx_buf[0] << 4 | adc->rx_buf[1] >> 4);
+		return 0;
 	case mcp3301:
-		return sign_extend32((adc->rx_buf[0] & 0x1f) << 8 | adc->rx_buf[1], 12);
+		*val = sign_extend32((adc->rx_buf[0] & 0x1f) << 8
+				    | adc->rx_buf[1], 12);
+		return 0;
 	default:
 		return -EINVAL;
 	}
 	switch (mask) {
 	case IIO_CHAN_INFO_RAW:
 		ret = mcp320x_adc_conversion(adc, channel->address,
-			channel->differential, device_index);
+			channel->differential, device_index, val);
 		if (ret < 0)
 			goto out;
-		*val = ret;
 		ret = IIO_VAL_INT;
 		break;
 	indio_dev->name = spi_get_device_id(spi)->name;
 	indio_dev->modes = INDIO_DIRECT_MODE;
 	indio_dev->info = &mcp320x_info;
+	spi_set_drvdata(spi, indio_dev);
 	chip_info = &mcp320x_chip_infos[spi_get_device_id(spi)->driver_data];
 	indio_dev->channels = chip_info->channels;

drivers/iio/adc/stm32-adc.c+1−1

@@ -1666,7 +1666,7 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev) · 1665 unmodified lines
1666		1666
1667	num_channels = of_property_count_u32_elems(node, "st,adc-channels");	1667	num_channels = of_property_count_u32_elems(node, "st,adc-channels");
1668	if (num_channels < 0 \|\|	1668	if (num_channels < 0 \|\|
1669	num_channels >= adc_info->max_channels) {	1669	num_channels > adc_info->max_channels) {
1670	dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");	1670	dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
1671	return num_channels < 0 ? num_channels : -EINVAL;	1671	return num_channels < 0 ? num_channels : -EINVAL;
1672	}	1672	}

drivers/iio/adc/ti-ads1015.c+5−3

 #define ADS1015_CFG_COMP_QUE_MASK	GENMASK(1, 0)
 #define ADS1015_CFG_COMP_LAT_MASK	BIT(2)
-#define ADS1015_CFG_COMP_POL_MASK	BIT(2)
+#define ADS1015_CFG_COMP_POL_MASK	BIT(3)
 #define ADS1015_CFG_COMP_MODE_MASK	BIT(4)
 #define ADS1015_CFG_DR_MASK	GENMASK(7, 5)
 #define ADS1015_CFG_MOD_MASK	BIT(8)
 		switch (irq_trig) {
 		case IRQF_TRIGGER_LOW:
-			cfg_comp |= ADS1015_CFG_COMP_POL_LOW;
+			cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
+					ADS1015_CFG_COMP_POL_SHIFT;
 			break;
 		case IRQF_TRIGGER_HIGH:
-			cfg_comp |= ADS1015_CFG_COMP_POL_HIGH;
+			cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
+					ADS1015_CFG_COMP_POL_SHIFT;
 			break;
 		default:
 			return -EINVAL;

drivers/iio/adc/twl4030-madc.c+10−4

 	/* Enable 3v1 bias regulator for MADC[3:6] */
 	madc->usb3v1 = devm_regulator_get(madc->dev, "vusb3v1");
-	if (IS_ERR(madc->usb3v1))
+	if (IS_ERR(madc->usb3v1)) {
-		return -ENODEV;
+		ret = -ENODEV;
+		goto err_i2c;
+	}
 	ret = regulator_enable(madc->usb3v1);
-	if (ret)
+	if (ret) {
 		dev_err(madc->dev, "could not enable 3v1 bias regulator\n");
+		goto err_i2c;
+	}
 	ret = iio_device_register(iio_dev);
 	if (ret) {
 		dev_err(&pdev->dev, "could not register iio device\n");
-		goto err_i2c;
+		goto err_usb3v1;
 	}
 	return 0;
+err_usb3v1:
+	regulator_disable(madc->usb3v1);
 err_i2c:
 	twl4030_madc_set_current_generator(madc, 0, 0);
 err_current_generator:

drivers/iio/common/st_sensors/st_sensors_core.c+10−1

@@ -463,8 +463,17 @@ int st_sensors_set_dataready_irq(struct iio_dev *indio_dev, bool enable) · 462 unmodified lines
463	u8 drdy_mask;	463	u8 drdy_mask;
464	struct st_sensor_data *sdata = iio_priv(indio_dev);	464	struct st_sensor_data *sdata = iio_priv(indio_dev);
465		465
466	if (!sdata->sensor_settings->drdy_irq.addr)	466	if (!sdata->sensor_settings->drdy_irq.addr) {
		467	/*
		468	* there are some devices (e.g. LIS3MDL) where drdy line is
		469	* routed to a given pin and it is not possible to select a
		470	* different one. Take into account irq status register
		471	* to understand if irq trigger can be properly supported
		472	*/
		473	if (sdata->sensor_settings->drdy_irq.addr_stat_drdy)
		474	sdata->hw_irq_trigger = enable;
467	return 0;	475	return 0;
		476	}
468		477
469	/* Enable/Disable the interrupt generator 1. */	478	/* Enable/Disable the interrupt generator 1. */
470	if (sdata->sensor_settings->drdy_irq.ig1.en_addr > 0) {	479	if (sdata->sensor_settings->drdy_irq.ig1.en_addr > 0) {

drivers/iio/industrialio-core.c+3−1

 	ret = indio_dev->info->debugfs_reg_access(indio_dev,
 						  indio_dev->cached_reg_addr,
 						  0, &val);
-	if (ret)
+	if (ret) {
 		dev_err(indio_dev->dev.parent, "%s: read failed\n", __func__);
+		return ret;
+	}
 	len = snprintf(buf, sizeof(buf), "0x%X\n", val);

drivers/iio/magnetometer/st_magn_core.c+4−0

 				},
 			},
 		},
+		.drdy_irq = {
+			/* drdy line is routed drdy pin */
+			.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
+		},
 		.multi_read_bit = true,
 		.bootime = 2,
 	},

drivers/iio/pressure/bmp280-core.c+1−1

@@ -573,7 +573,7 @@ static int bmp280_chip_config(struct bmp280_data *data) · 572 unmodified lines
573	u8 osrs = BMP280_OSRS_TEMP_X(data->oversampling_temp + 1) \|	573	u8 osrs = BMP280_OSRS_TEMP_X(data->oversampling_temp + 1) \|
574	BMP280_OSRS_PRESS_X(data->oversampling_press + 1);	574	BMP280_OSRS_PRESS_X(data->oversampling_press + 1);
575		575
576	ret = regmap_update_bits(data->regmap, BMP280_REG_CTRL_MEAS,	576	ret = regmap_write_bits(data->regmap, BMP280_REG_CTRL_MEAS,
577	BMP280_OSRS_TEMP_MASK \|	577	BMP280_OSRS_TEMP_MASK \|
578	BMP280_OSRS_PRESS_MASK \|	578	BMP280_OSRS_PRESS_MASK \|
579	BMP280_MODE_MASK,	579	BMP280_MODE_MASK,

drivers/iio/trigger/stm32-timer-trigger.c+3−1

 		clk_disable(priv->clk);
 	/* Stop timer */
+	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 	regmap_write(priv->regmap, TIM_PSC, 0);
 	regmap_write(priv->regmap, TIM_ARR, 0);
 	if (ret)
 		return ret;
+	/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
+	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 	regmap_write(priv->regmap, TIM_ARR, preset);
-	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
 	return len;
 }

drivers/infiniband/core/iwpm_msg.c+8−0

 	if (ret)
 		goto pid_query_error;
+	nlmsg_end(skb, nlh);
 	pr_debug("%s: Multicasting a nlmsg (dev = %s ifname = %s iwpm = %s)\n",
 		__func__, pm_msg->dev_name, pm_msg->if_name, iwpm_ulib_name);
 				&pm_msg->loc_addr, IWPM_NLA_MANAGE_ADDR);
 	if (ret)
 		goto add_mapping_error;
+	nlmsg_end(skb, nlh);
 	nlmsg_request->req_buffer = pm_msg;
 	ret = rdma_nl_unicast_wait(skb, iwpm_user_pid);
 				&pm_msg->rem_addr, IWPM_NLA_QUERY_REMOTE_ADDR);
 	if (ret)
 		goto query_mapping_error;
+	nlmsg_end(skb, nlh);
 	nlmsg_request->req_buffer = pm_msg;
 	ret = rdma_nl_unicast_wait(skb, iwpm_user_pid);
 	if (ret)
 		goto remove_mapping_error;
+	nlmsg_end(skb, nlh);
 	ret = rdma_nl_unicast_wait(skb, iwpm_user_pid);
 	if (ret) {
 		skb = NULL; /* skb is freed in the netlink send-op handling */

drivers/infiniband/core/iwpm_util.c+5−0

 				&mapping_num, IWPM_NLA_MAPINFO_SEND_NUM);
 	if (ret)
 		goto mapinfo_num_error;
+	nlmsg_end(skb, nlh);
 	ret = rdma_nl_unicast(skb, iwpm_pid);
 	if (ret) {
 		skb = NULL;
 			if (ret)
 				goto send_mapping_info_unlock;
+			nlmsg_end(skb, nlh);
 			iwpm_print_sockaddr(&map_info->local_sockaddr,
 				"send_mapping_info: Local sockaddr:");
 			iwpm_print_sockaddr(&map_info->mapped_sockaddr,

drivers/infiniband/core/security.c+3−1

 	atomic_set(&qp->qp_sec->error_list_count, 0);
 	init_completion(&qp->qp_sec->error_complete);
 	ret = security_ib_alloc_security(&qp->qp_sec->security);
-	if (ret)
+	if (ret) {
 		kfree(qp->qp_sec);
+		qp->qp_sec = NULL;
+	}
 	return ret;
 }

drivers/infiniband/core/uverbs_cmd.c+7−7

@@ -3869,15 +3869,15 @@ int ib_uverbs_ex_query_device(struct ib_uverbs_file *file, · 3868 unmodified lines
3869	resp.raw_packet_caps = attr.raw_packet_caps;	3869	resp.raw_packet_caps = attr.raw_packet_caps;
3870	resp.response_length += sizeof(resp.raw_packet_caps);	3870	resp.response_length += sizeof(resp.raw_packet_caps);
3871		3871
3872	if (ucore->outlen < resp.response_length + sizeof(resp.xrq_caps))	3872	if (ucore->outlen < resp.response_length + sizeof(resp.tm_caps))
3873	goto end;	3873	goto end;
3874		3874
3875	resp.xrq_caps.max_rndv_hdr_size = attr.xrq_caps.max_rndv_hdr_size;	3875	resp.tm_caps.max_rndv_hdr_size = attr.tm_caps.max_rndv_hdr_size;
3876	resp.xrq_caps.max_num_tags = attr.xrq_caps.max_num_tags;	3876	resp.tm_caps.max_num_tags = attr.tm_caps.max_num_tags;
3877	resp.xrq_caps.max_ops = attr.xrq_caps.max_ops;	3877	resp.tm_caps.max_ops = attr.tm_caps.max_ops;
3878	resp.xrq_caps.max_sge = attr.xrq_caps.max_sge;	3878	resp.tm_caps.max_sge = attr.tm_caps.max_sge;
3879	resp.xrq_caps.flags = attr.xrq_caps.flags;	3879	resp.tm_caps.flags = attr.tm_caps.flags;
3880	resp.response_length += sizeof(resp.xrq_caps);	3880	resp.response_length += sizeof(resp.tm_caps);
3881	end:	3881	end:
3882	err = ib_copy_to_udata(ucore, &resp, resp.response_length);	3882	err = ib_copy_to_udata(ucore, &resp, resp.response_length);
3883	return err;	3883	return err;

drivers/infiniband/core/verbs.c+2−2

@@ -1646,7 +1646,7 @@ static bool is_valid_mcast_lid(struct ib_qp *qp, u16 lid) · 1645 unmodified lines
1646	*/	1646	*/
1647	if (!ib_query_qp(qp, &attr, IB_QP_STATE \| IB_QP_PORT, &init_attr)) {	1647	if (!ib_query_qp(qp, &attr, IB_QP_STATE \| IB_QP_PORT, &init_attr)) {
1648	if (attr.qp_state >= IB_QPS_INIT) {	1648	if (attr.qp_state >= IB_QPS_INIT) {
1649	if (qp->device->get_link_layer(qp->device, attr.port_num) !=	1649	if (rdma_port_get_link_layer(qp->device, attr.port_num) !=
1650	IB_LINK_LAYER_INFINIBAND)	1650	IB_LINK_LAYER_INFINIBAND)
1651	return true;	1651	return true;
1652	goto lid_check;	1652	goto lid_check;
@@ -1655,7 +1655,7 @@ static bool is_valid_mcast_lid(struct ib_qp *qp, u16 lid) · 2 unmodified lines
1655		1655
1656	/* Can't get a quick answer, iterate over all ports */	1656	/* Can't get a quick answer, iterate over all ports */
1657	for (port = 0; port < qp->device->phys_port_cnt; port++)	1657	for (port = 0; port < qp->device->phys_port_cnt; port++)
1658	if (qp->device->get_link_layer(qp->device, port) !=	1658	if (rdma_port_get_link_layer(qp->device, port) !=
1659	IB_LINK_LAYER_INFINIBAND)	1659	IB_LINK_LAYER_INFINIBAND)
1660	num_eth_ports++;	1660	num_eth_ports++;
1661		1661

drivers/infiniband/hw/bnxt_re/bnxt_re.h+9−5

 	struct ib_device		ibdev;
 	struct list_head		list;
 	unsigned long			flags;
-#define BNXT_RE_FLAG_NETDEV_REGISTERED	0
+#define BNXT_RE_FLAG_NETDEV_REGISTERED		0
-#define BNXT_RE_FLAG_IBDEV_REGISTERED	1
+#define BNXT_RE_FLAG_IBDEV_REGISTERED		1
-#define BNXT_RE_FLAG_GOT_MSIX		2
+#define BNXT_RE_FLAG_GOT_MSIX			2
-#define BNXT_RE_FLAG_RCFW_CHANNEL_EN	8
+#define BNXT_RE_FLAG_HAVE_L2_REF		3
-#define BNXT_RE_FLAG_QOS_WORK_REG	16
+#define BNXT_RE_FLAG_RCFW_CHANNEL_EN		4
+#define BNXT_RE_FLAG_QOS_WORK_REG		5
+#define BNXT_RE_FLAG_TASK_IN_PROG		6
 	struct net_device		*netdev;
 	unsigned int			version, major, minor;
 	struct bnxt_en_dev		*en_dev;
 	struct delayed_work		worker;
 	u8				cur_prio_map;
+	u8				active_speed;
+	u8				active_width;
 	/* FP Notification Queue (CQ & SRQ) */
 	struct tasklet_struct		nq_task;

drivers/infiniband/hw/bnxt_re/ib_verbs.c+64−43

@@ -259,14 +259,9 @@ int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num, · 258 unmodified lines
259	port_attr->sm_sl = 0;	259	port_attr->sm_sl = 0;
260	port_attr->subnet_timeout = 0;	260	port_attr->subnet_timeout = 0;
261	port_attr->init_type_reply = 0;	261	port_attr->init_type_reply = 0;
262	/* call the underlying netdev's ethtool hooks to query speed settings	262	port_attr->active_speed = rdev->active_speed;
263	* for which we acquire rtnl_lock _only_ if it's registered with	263	port_attr->active_width = rdev->active_width;
264	* IB stack to avoid race in the NETDEV_UNREG path	264
265	*/
266	if (test_bit(BNXT_RE_FLAG_IBDEV_REGISTERED, &rdev->flags))
267	if (ib_get_eth_speed(ibdev, port_num, &port_attr->active_speed,
268	&port_attr->active_width))
269	return -EINVAL;
270	return 0;	265	return 0;
271	}	266	}
272		267
@@ -319,6 +314,7 @@ int bnxt_re_del_gid(struct ib_device *ibdev, u8 port_num, · 46 unmodified lines
319	struct bnxt_re_gid_ctx ctx, *ctx_tbl;	314	struct bnxt_re_gid_ctx ctx, *ctx_tbl;
320	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);	315	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
321	struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;	316	struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
		317	struct bnxt_qplib_gid *gid_to_del;
322		318
323	/* Delete the entry from the hardware */	319	/* Delete the entry from the hardware */
324	ctx = *context;	320	ctx = *context;
@@ -328,11 +324,25 @@ int bnxt_re_del_gid(struct ib_device *ibdev, u8 port_num, · 3 unmodified lines
328	if (sgid_tbl && sgid_tbl->active) {	324	if (sgid_tbl && sgid_tbl->active) {
329	if (ctx->idx >= sgid_tbl->max)	325	if (ctx->idx >= sgid_tbl->max)
330	return -EINVAL;	326	return -EINVAL;
		327	gid_to_del = &sgid_tbl->tbl[ctx->idx];
		328	/* DEL_GID is called in WQ context(netdevice_event_work_handler)
		329	* or via the ib_unregister_device path. In the former case QP1
		330	* may not be destroyed yet, in which case just return as FW
		331	* needs that entry to be present and will fail it's deletion.
		332	* We could get invoked again after QP1 is destroyed OR get an
		333	* ADD_GID call with a different GID value for the same index
		334	* where we issue MODIFY_GID cmd to update the GID entry -- TBD
		335	*/
		336	if (ctx->idx == 0 &&
		337	rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
		338	ctx->refcnt == 1 && rdev->qp1_sqp) {
		339	dev_dbg(rdev_to_dev(rdev),
		340	"Trying to delete GID0 while QP1 is alive\n");
		341	return -EFAULT;
		342	}
331	ctx->refcnt--;	343	ctx->refcnt--;
332	if (!ctx->refcnt) {	344	if (!ctx->refcnt) {
333	rc = bnxt_qplib_del_sgid(sgid_tbl,	345	rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, true);
334	&sgid_tbl->tbl[ctx->idx],
335	true);
336	if (rc) {	346	if (rc) {
337	dev_err(rdev_to_dev(rdev),	347	dev_err(rdev_to_dev(rdev),
338	"Failed to remove GID: %#x", rc);	348	"Failed to remove GID: %#x", rc);
@@ -816,6 +826,8 @@ int bnxt_re_destroy_qp(struct ib_qp *ib_qp) · 477 unmodified lines
816		826
817	kfree(rdev->sqp_ah);	827	kfree(rdev->sqp_ah);
818	kfree(rdev->qp1_sqp);	828	kfree(rdev->qp1_sqp);
		829	rdev->qp1_sqp = NULL;
		830	rdev->sqp_ah = NULL;
819	}	831	}
820		832
821	if (!IS_ERR_OR_NULL(qp->rumem))	833	if (!IS_ERR_OR_NULL(qp->rumem))
@@ -1436,11 +1448,14 @@ int bnxt_re_modify_qp(struct ib_qp ib_qp, struct ib_qp_attr qp_attr, · 614 unmodified lines
1436	qp->qplib_qp.modify_flags \|=	1448	qp->qplib_qp.modify_flags \|=
1437	CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;	1449	CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1438	qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);	1450	qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
		1451	qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
1439	} else if (qp_attr->qp_state == IB_QPS_RTR) {	1452	} else if (qp_attr->qp_state == IB_QPS_RTR) {
1440	qp->qplib_qp.modify_flags \|=	1453	qp->qplib_qp.modify_flags \|=
1441	CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;	1454	CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1442	qp->qplib_qp.path_mtu =	1455	qp->qplib_qp.path_mtu =
1443	__from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));	1456	__from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
		1457	qp->qplib_qp.mtu =
		1458	ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1444	}	1459	}
1445		1460
1446	if (qp_attr_mask & IB_QP_TIMEOUT) {	1461	if (qp_attr_mask & IB_QP_TIMEOUT) {
@@ -1551,43 +1566,46 @@ int bnxt_re_query_qp(struct ib_qp ib_qp, struct ib_qp_attr qp_attr, · 104 unmodified lines
1551	{	1566	{
1552	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);	1567	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1553	struct bnxt_re_dev *rdev = qp->rdev;	1568	struct bnxt_re_dev *rdev = qp->rdev;
1554	struct bnxt_qplib_qp qplib_qp;	1569	struct bnxt_qplib_qp *qplib_qp;
1555	int rc;	1570	int rc;
1556		1571
1557	memset(&qplib_qp, 0, sizeof(struct bnxt_qplib_qp));	1572	qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
1558	qplib_qp.id = qp->qplib_qp.id;	1573	if (!qplib_qp)
1559	qplib_qp.ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;	1574	return -ENOMEM;
		1575
		1576	qplib_qp->id = qp->qplib_qp.id;
		1577	qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
1560		1578
1561	rc = bnxt_qplib_query_qp(&rdev->qplib_res, &qplib_qp);	1579	rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
1562	if (rc) {	1580	if (rc) {
1563	dev_err(rdev_to_dev(rdev), "Failed to query HW QP");	1581	dev_err(rdev_to_dev(rdev), "Failed to query HW QP");
1564	return rc;	1582	goto out;
1565	}	1583	}
1566	qp_attr->qp_state = __to_ib_qp_state(qplib_qp.state);	1584	qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
1567	qp_attr->en_sqd_async_notify = qplib_qp.en_sqd_async_notify ? 1 : 0;	1585	qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
1568	qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp.access);	1586	qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
1569	qp_attr->pkey_index = qplib_qp.pkey_index;	1587	qp_attr->pkey_index = qplib_qp->pkey_index;
1570	qp_attr->qkey = qplib_qp.qkey;	1588	qp_attr->qkey = qplib_qp->qkey;
1571	qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;	1589	qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
1572	rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp.ah.flow_label,	1590	rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
1573	qplib_qp.ah.host_sgid_index,	1591	qplib_qp->ah.host_sgid_index,
1574	qplib_qp.ah.hop_limit,	1592	qplib_qp->ah.hop_limit,
1575	qplib_qp.ah.traffic_class);	1593	qplib_qp->ah.traffic_class);
1576	rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp.ah.dgid.data);	1594	rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
1577	rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp.ah.sl);	1595	rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
1578	ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp.ah.dmac);	1596	ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
1579	qp_attr->path_mtu = __to_ib_mtu(qplib_qp.path_mtu);	1597	qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
1580	qp_attr->timeout = qplib_qp.timeout;	1598	qp_attr->timeout = qplib_qp->timeout;
1581	qp_attr->retry_cnt = qplib_qp.retry_cnt;	1599	qp_attr->retry_cnt = qplib_qp->retry_cnt;
1582	qp_attr->rnr_retry = qplib_qp.rnr_retry;	1600	qp_attr->rnr_retry = qplib_qp->rnr_retry;
1583	qp_attr->min_rnr_timer = qplib_qp.min_rnr_timer;	1601	qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
1584	qp_attr->rq_psn = qplib_qp.rq.psn;	1602	qp_attr->rq_psn = qplib_qp->rq.psn;
1585	qp_attr->max_rd_atomic = qplib_qp.max_rd_atomic;	1603	qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
1586	qp_attr->sq_psn = qplib_qp.sq.psn;	1604	qp_attr->sq_psn = qplib_qp->sq.psn;
1587	qp_attr->max_dest_rd_atomic = qplib_qp.max_dest_rd_atomic;	1605	qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
1588	qp_init_attr->sq_sig_type = qplib_qp.sig_type ? IB_SIGNAL_ALL_WR :	1606	qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
1589	IB_SIGNAL_REQ_WR;	1607	IB_SIGNAL_REQ_WR;
1590	qp_attr->dest_qp_num = qplib_qp.dest_qpn;	1608	qp_attr->dest_qp_num = qplib_qp->dest_qpn;
1591		1609
1592	qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;	1610	qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
1593	qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;	1611	qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
@@ -1596,7 +1614,9 @@ int bnxt_re_query_qp(struct ib_qp ib_qp, struct ib_qp_attr qp_attr, · 2 unmodified lines
1596	qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;	1614	qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
1597	qp_init_attr->cap = qp_attr->cap;	1615	qp_init_attr->cap = qp_attr->cap;
1598		1616
1599	return 0;	1617	out:
		1618	kfree(qplib_qp);
		1619	return rc;
1600	}	1620	}
1601		1621
1602	/* Routine for sending QP1 packets for RoCE V1 an V2	1622	/* Routine for sending QP1 packets for RoCE V1 an V2
@@ -1908,6 +1928,7 @@ static int bnxt_re_build_atomic_wqe(struct ib_send_wr *wr, · 305 unmodified lines
1908	switch (wr->opcode) {	1928	switch (wr->opcode) {
1909	case IB_WR_ATOMIC_CMP_AND_SWP:	1929	case IB_WR_ATOMIC_CMP_AND_SWP:
1910	wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;	1930	wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
		1931	wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
1911	wqe->atomic.swap_data = atomic_wr(wr)->swap;	1932	wqe->atomic.swap_data = atomic_wr(wr)->swap;
1912	break;	1933	break;
1913	case IB_WR_ATOMIC_FETCH_AND_ADD:	1934	case IB_WR_ATOMIC_FETCH_AND_ADD:
@@ -3062,7 +3083,7 @@ int bnxt_re_dereg_mr(struct ib_mr *ib_mr) · 1148 unmodified lines
3062	return rc;	3083	return rc;
3063	}	3084	}
3064		3085
3065	if (mr->npages && mr->pages) {	3086	if (mr->pages) {
3066	rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,	3087	rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3067	&mr->qplib_frpl);	3088	&mr->qplib_frpl);
3068	kfree(mr->pages);	3089	kfree(mr->pages);

drivers/infiniband/hw/bnxt_re/main.c+28−0

 		}
 	}
 	set_bit(BNXT_RE_FLAG_IBDEV_REGISTERED, &rdev->flags);
+	ib_get_eth_speed(&rdev->ibdev, 1, &rdev->active_speed,
+			 &rdev->active_width);
 	bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, IB_EVENT_PORT_ACTIVE);
 	bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, IB_EVENT_GID_CHANGE);
 		else if (netif_carrier_ok(rdev->netdev))
 			bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1,
 					       IB_EVENT_PORT_ACTIVE);
+		ib_get_eth_speed(&rdev->ibdev, 1, &rdev->active_speed,
+				 &rdev->active_width);
 		break;
 	default:
 		break;
 	}
+	smp_mb__before_atomic();
+	clear_bit(BNXT_RE_FLAG_TASK_IN_PROG, &rdev->flags);
 	kfree(re_work);
 }
 		break;
 	case NETDEV_UNREGISTER:
+		/* netdev notifier will call NETDEV_UNREGISTER again later since
+		 * we are still holding the reference to the netdev
+		 */
+		if (test_bit(BNXT_RE_FLAG_TASK_IN_PROG, &rdev->flags))
+			goto exit;
 		bnxt_re_ib_unreg(rdev, false);
 		bnxt_re_remove_one(rdev);
 		bnxt_re_dev_unreg(rdev);
 			re_work->vlan_dev = (real_dev == netdev ?
 					     NULL : netdev);
 			INIT_WORK(&re_work->work, bnxt_re_task);
+			set_bit(BNXT_RE_FLAG_TASK_IN_PROG, &rdev->flags);
 			queue_work(bnxt_re_wq, &re_work->work);
 		}
 	}
 static void __exit bnxt_re_mod_exit(void)
 {
+	struct bnxt_re_dev *rdev;
+	LIST_HEAD(to_be_deleted);
+	mutex_lock(&bnxt_re_dev_lock);
+	/* Free all adapter allocated resources */
+	if (!list_empty(&bnxt_re_dev_list))
+		list_splice_init(&bnxt_re_dev_list, &to_be_deleted);
+	mutex_unlock(&bnxt_re_dev_lock);
+	list_for_each_entry(rdev, &to_be_deleted, list) {
+		dev_info(rdev_to_dev(rdev), "Unregistering Device");
+		bnxt_re_dev_stop(rdev);
+		bnxt_re_ib_unreg(rdev, true);
+		bnxt_re_remove_one(rdev);
+		bnxt_re_dev_unreg(rdev);
+	}
 	unregister_netdevice_notifier(&bnxt_re_netdev_notifier);
 	if (bnxt_re_wq)
 		destroy_workqueue(bnxt_re_wq);

drivers/infiniband/hw/bnxt_re/qplib_rcfw.c+4−0

 		return -EINVAL;
 	}
+	if (test_bit(FIRMWARE_TIMED_OUT, &rcfw->flags))
+		return -ETIMEDOUT;
 	/* Cmdq are in 16-byte units, each request can consume 1 or more
 	 * cmdqe
 	 */
 		/* timed out */
 		dev_err(&rcfw->pdev->dev, "QPLIB: cmdq[%#x]=%#x timedout (%d)msec",
 			cookie, opcode, RCFW_CMD_WAIT_TIME_MS);
+		set_bit(FIRMWARE_TIMED_OUT, &rcfw->flags);
 		return rc;
 	}

drivers/infiniband/hw/bnxt_re/qplib_rcfw.h+2−1

 	unsigned long		*cmdq_bitmap;
 	u32			bmap_size;
 	unsigned long		flags;
-#define FIRMWARE_INITIALIZED_FLAG	1
+#define FIRMWARE_INITIALIZED_FLAG	BIT(0)
 #define FIRMWARE_FIRST_FLAG		BIT(31)
+#define FIRMWARE_TIMED_OUT		BIT(3)
 	wait_queue_head_t	waitq;
 	int			(*aeq_handler)(struct bnxt_qplib_rcfw *,
 					       struct creq_func_event *);

drivers/infiniband/hw/cxgb4/cm.c+7−2

@@ -2333,9 +2333,14 @@ static int close_listsrv_rpl(struct c4iw_dev dev, struct sk_buff skb) · 2332 unmodified lines
2333	unsigned int stid = GET_TID(rpl);	2333	unsigned int stid = GET_TID(rpl);
2334	struct c4iw_listen_ep *ep = get_ep_from_stid(dev, stid);	2334	struct c4iw_listen_ep *ep = get_ep_from_stid(dev, stid);
2335		2335
		2336	if (!ep) {
		2337	pr_debug("%s stid %d lookup failure!\n", __func__, stid);
		2338	goto out;
		2339	}
2336	pr_debug("%s ep %p\n", __func__, ep);	2340	pr_debug("%s ep %p\n", __func__, ep);
2337	c4iw_wake_up(&ep->com.wr_wait, status2errno(rpl->status));	2341	c4iw_wake_up(&ep->com.wr_wait, status2errno(rpl->status));
2338	c4iw_put_ep(&ep->com);	2342	c4iw_put_ep(&ep->com);
		2343	out:
2339	return 0;	2344	return 0;
2340	}	2345	}
2341		2346
@@ -2594,9 +2599,9 @@ fail: · 252 unmodified lines
2594	c4iw_put_ep(&child_ep->com);	2599	c4iw_put_ep(&child_ep->com);
2595	reject:	2600	reject:
2596	reject_cr(dev, hwtid, skb);	2601	reject_cr(dev, hwtid, skb);
		2602	out:
2597	if (parent_ep)	2603	if (parent_ep)
2598	c4iw_put_ep(&parent_ep->com);	2604	c4iw_put_ep(&parent_ep->com);
2599	out:
2600	return 0;	2605	return 0;
2601	}	2606	}
2602		2607
@@ -3457,7 +3462,7 @@ int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog) · 854 unmodified lines
3457	cm_id->provider_data = ep;	3462	cm_id->provider_data = ep;
3458	goto out;	3463	goto out;
3459	}	3464	}
3460		3465	remove_handle(ep->com.dev, &ep->com.dev->stid_idr, ep->stid);
3461	cxgb4_free_stid(ep->com.dev->rdev.lldi.tids, ep->stid,	3466	cxgb4_free_stid(ep->com.dev->rdev.lldi.tids, ep->stid,
3462	ep->com.local_addr.ss_family);	3467	ep->com.local_addr.ss_family);
3463	fail2:	3468	fail2:

drivers/infiniband/hw/hfi1/chip.c+78−23

 static int thermal_init(struct hfi1_devdata *dd);
 static void update_statusp(struct hfi1_pportdata *ppd, u32 state);
+static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd,
+					    int msecs);
 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
 				  int msecs);
 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state);
 	u64 regs[CCE_NUM_INT_CSRS];
 	u32 bit;
 	int i;
+	irqreturn_t handled = IRQ_NONE;
 	this_cpu_inc(*dd->int_counter);
 	for_each_set_bit(bit, (unsigned long *)&regs[0],
 			 CCE_NUM_INT_CSRS * 64) {
 		is_interrupt(dd, bit);
+		handled = IRQ_HANDLED;
 	}
-	return IRQ_HANDLED;
+	return handled;
 }
 static irqreturn_t sdma_interrupt(int irq, void *data)
 	write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
 }
-void reset_qsfp(struct hfi1_pportdata *ppd)
+int reset_qsfp(struct hfi1_pportdata *ppd)
 {
 	struct hfi1_devdata *dd = ppd->dd;
 	u64 mask, qsfp_mask;
 	 * for alarms and warnings
 	 */
 	set_qsfp_int_n(ppd, 1);
+	/*
+	 * After the reset, AOC transmitters are enabled by default. They need
+	 * to be turned off to complete the QSFP setup before they can be
+	 * enabled again.
+	 */
+	return set_qsfp_tx(ppd, 0);
 }
 static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd,
 {
 	struct hfi1_devdata *dd = ppd->dd;
 	u32 previous_state;
+	int offline_state_ret;
 	int ret;
 	update_lcb_cache(dd);
 		ppd->offline_disabled_reason =
 		HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
-	/*
+	offline_state_ret = wait_phys_link_offline_substates(ppd, 10000);
-	 * Wait for offline transition. It can take a while for
+	if (offline_state_ret < 0)
-	 * the link to go down.
+		return offline_state_ret;
-	 */
-	ret = wait_physical_linkstate(ppd, PLS_OFFLINE, 10000);
-	if (ret < 0)
-		return ret;
-	/*
-	 * Now in charge of LCB - must be after the physical state is
-	 * offline.quiet and before host_link_state is changed.
-	 */
-	set_host_lcb_access(dd);
-	write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
-	/* make sure the logical state is also down */
-	ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
-	if (ret)
-		force_logical_link_state_down(ppd);
-	ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
+	/* Disabling AOC transmitters */
 	if (ppd->port_type == PORT_TYPE_QSFP &&
 	    ppd->qsfp_info.limiting_active &&
 	    qsfp_mod_present(ppd)) {
 		}
 	}
+	/*
+	 * Wait for the offline.Quiet transition if it hasn't happened yet. It
+	 * can take a while for the link to go down.
+	 */
+	if (offline_state_ret != PLS_OFFLINE_QUIET) {
+		ret = wait_physical_linkstate(ppd, PLS_OFFLINE, 30000);
+		if (ret < 0)
+			return ret;
+	}
+	/*
+	 * Now in charge of LCB - must be after the physical state is
+	 * offline.quiet and before host_link_state is changed.
+	 */
+	set_host_lcb_access(dd);
+	write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
+	/* make sure the logical state is also down */
+	ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
+	if (ret)
+		force_logical_link_state_down(ppd);
+	ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
 	/*
 	 * The LNI has a mandatory wait time after the physical state
 	 * moves to Offline.Quiet.  The wait time may be different
 			& (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
 		/* went down while attempting link up */
 		check_lni_states(ppd);
+		/* The QSFP doesn't need to be reset on LNI failure */
+		ppd->qsfp_info.reset_needed = 0;
 	}
 	/* the active link width (downgrade) is 0 on link down */
 	return 0;
 }
+/*
+ * wait_phys_link_offline_quiet_substates - wait for any offline substate
+ * @ppd: port device
+ * @msecs: the number of milliseconds to wait
+ *
+ * Wait up to msecs milliseconds for any offline physical link
+ * state change to occur.
+ * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT.
+ */
+static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd,
+					    int msecs)
+{
+	u32 read_state;
+	unsigned long timeout;
+	timeout = jiffies + msecs_to_jiffies(msecs);
+	while (1) {
+		read_state = read_physical_state(ppd->dd);
+		if ((read_state & 0xF0) == PLS_OFFLINE)
+			break;
+		if (time_after(jiffies, timeout)) {
+			dd_dev_err(ppd->dd,
+				   "timeout waiting for phy link offline.quiet substates. Read state 0x%x, %dms\n",
+				   read_state, msecs);
+			return -ETIMEDOUT;
+		}
+		usleep_range(1950, 2050); /* sleep 2ms-ish */
+	}
+	log_state_transition(ppd, read_state);
+	return read_state;
+}
 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)

drivers/infiniband/hw/hfi1/chip.h+2−1

 #define PLS_OFFLINE_READY_TO_QUIET_LT	   0x92
 #define PLS_OFFLINE_REPORT_FAILURE		   0x93
 #define PLS_OFFLINE_READY_TO_QUIET_BCC	   0x94
+#define PLS_OFFLINE_QUIET_DURATION	   0x95
 #define PLS_POLLING				   0x20
 #define PLS_POLLING_QUIET			   0x20
 #define PLS_POLLING_ACTIVE			   0x21
 void handle_link_bounce(struct work_struct *work);
 void handle_start_link(struct work_struct *work);
 void handle_sma_message(struct work_struct *work);
-void reset_qsfp(struct hfi1_pportdata *ppd);
+int reset_qsfp(struct hfi1_pportdata *ppd);
 void qsfp_event(struct work_struct *work);
 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags);
 int send_idle_sma(struct hfi1_devdata *dd, u64 message);

drivers/infiniband/hw/hfi1/eprom.c+15−5

 	return ret;
 }
-/* magic character sequence that trails an image */
+/* magic character sequence that begins an image */
+#define IMAGE_START_MAGIC "APO="
+/* magic character sequence that might trail an image */
 #define IMAGE_TRAIL_MAGIC "egamiAPO"
 /* EPROM file types */
 {
 	void *buffer;
 	void *p;
+	u32 length;
 	int ret;
 	buffer = kmalloc(P1_SIZE, GFP_KERNEL);
 		return ret;
 	}
-	/* scan for image magic that may trail the actual data */
+	/* config partition is valid only if it starts with IMAGE_START_MAGIC */
-	p = strnstr(buffer, IMAGE_TRAIL_MAGIC, P1_SIZE);
+	if (memcmp(buffer, IMAGE_START_MAGIC, strlen(IMAGE_START_MAGIC))) {
-	if (!p) {
 		kfree(buffer);
 		return -ENOENT;
 	}
+	/* scan for image magic that may trail the actual data */
+	p = strnstr(buffer, IMAGE_TRAIL_MAGIC, P1_SIZE);
+	if (p)
+		length = p - buffer;
+	else
+		length = P1_SIZE;
 	*data = buffer;
-	*size = p - buffer;
+	*size = length;
 	return 0;
 }

drivers/infiniband/hw/hfi1/file_ops.c+22−19

 	switch (ret) {
 	case 0:
 		ret = setup_base_ctxt(fd, uctxt);
-		if (uctxt->subctxt_cnt) {
+		if (ret)
-			/*
+			deallocate_ctxt(uctxt);
-			 * Base context is done (successfully or not), notify
-			 * anybody using a sub-context that is waiting for
-			 * this completion.
-			 */
-			clear_bit(HFI1_CTXT_BASE_UNINIT, &uctxt->event_flags);
-			wake_up(&uctxt->wait);
-		}
 		break;
 	case 1:
 		ret = complete_subctxt(fd);
 	/* Now allocate the RcvHdr queue and eager buffers. */
 	ret = hfi1_create_rcvhdrq(dd, uctxt);
 	if (ret)
-		return ret;
+		goto done;
 	ret = hfi1_setup_eagerbufs(uctxt);
 	if (ret)
-		goto setup_failed;
+		goto done;
 	/* If sub-contexts are enabled, do the appropriate setup */
 	if (uctxt->subctxt_cnt)
 		ret = setup_subctxt(uctxt);
 	if (ret)
-		goto setup_failed;
+		goto done;
 	ret = hfi1_alloc_ctxt_rcv_groups(uctxt);
 	if (ret)
-		goto setup_failed;
+		goto done;
 	ret = init_user_ctxt(fd, uctxt);
 	if (ret)
-		goto setup_failed;
+		goto done;
 	user_init(uctxt);
 	fd->uctxt = uctxt;
 	hfi1_rcd_get(uctxt);
-	return 0;
+done:
+	if (uctxt->subctxt_cnt) {
+		/*
+		 * On error, set the failed bit so sub-contexts will clean up
+		 * correctly.
+		 */
+		if (ret)
+			set_bit(HFI1_CTXT_BASE_FAILED, &uctxt->event_flags);
-setup_failed:
+		/*
-	/* Set the failed bit so sub-context init can do the right thing */
+		 * Base context is done (successfully or not), notify anybody
-	set_bit(HFI1_CTXT_BASE_FAILED, &uctxt->event_flags);
+		 * using a sub-context that is waiting for this completion.
-	deallocate_ctxt(uctxt);
+		 */
+		clear_bit(HFI1_CTXT_BASE_UNINIT, &uctxt->event_flags);
+		wake_up(&uctxt->wait);
+	}
 	return ret;
 }

drivers/infiniband/hw/hfi1/pcie.c+21−29

 /*
  * Code to adjust PCIe capabilities.
  */
-static int tune_pcie_caps(struct hfi1_devdata *);
+static void tune_pcie_caps(struct hfi1_devdata *);
 /*
  * Do all the common PCIe setup and initialization.
  */
 int request_msix(struct hfi1_devdata *dd, u32 msireq)
 {
-	int nvec, ret;
+	int nvec;
 	nvec = pci_alloc_irq_vectors(dd->pcidev, 1, msireq,
 				     PCI_IRQ_MSIX | PCI_IRQ_LEGACY);
 		return nvec;
 	}
-	ret = tune_pcie_caps(dd);
+	tune_pcie_caps(dd);
-	if (ret) {
-		dd_dev_err(dd, "tune_pcie_caps() failed: %d\n", ret);
-		pci_free_irq_vectors(dd->pcidev);
-		return ret;
-	}
 	/* check for legacy IRQ */
 	if (nvec == 1 && !dd->pcidev->msix_enabled)
 module_param_named(aspm, aspm_mode, uint, S_IRUGO);
 MODULE_PARM_DESC(aspm, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic");
-static int tune_pcie_caps(struct hfi1_devdata *dd)
+static void tune_pcie_caps(struct hfi1_devdata *dd)
 {
 	struct pci_dev *parent;
 	u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
 	 * Turn on extended tags in DevCtl in case the BIOS has turned it off
 	 * to improve WFR SDMA bandwidth
 	 */
-	ret = pcie_capability_read_word(dd->pcidev,
+	ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
-					PCI_EXP_DEVCTL, &ectl);
+	if ((!ret) && !(ectl & PCI_EXP_DEVCTL_EXT_TAG)) {
-	if (ret) {
-		dd_dev_err(dd, "Unable to read from PCI config\n");
-		return ret;
-	}
-	if (!(ectl & PCI_EXP_DEVCTL_EXT_TAG)) {
 		dd_dev_info(dd, "Enabling PCIe extended tags\n");
 		ectl |= PCI_EXP_DEVCTL_EXT_TAG;
 		ret = pcie_capability_write_word(dd->pcidev,
 						 PCI_EXP_DEVCTL, ectl);
-		if (ret) {
+		if (ret)
-			dd_dev_err(dd, "Unable to write to PCI config\n");
+			dd_dev_info(dd, "Unable to write to PCI config\n");
-			return ret;
-		}
 	}
 	/* Find out supported and configured values for parent (root) */
 	parent = dd->pcidev->bus->self;
 	 * The driver cannot perform the tuning if it does not have
 	 * access to the upstream component.
 	 */
-	if (!parent)
+	if (!parent) {
-		return -EINVAL;
+		dd_dev_info(dd, "Parent not found\n");
+		return;
+	}
 	if (!pci_is_root_bus(parent->bus)) {
 		dd_dev_info(dd, "Parent not root\n");
-		return -EINVAL;
+		return;
+	}
+	if (!pci_is_pcie(parent)) {
+		dd_dev_info(dd, "Parent is not PCI Express capable\n");
+		return;
+	}
+	if (!pci_is_pcie(dd->pcidev)) {
+		dd_dev_info(dd, "PCI device is not PCI Express capable\n");
+		return;
 	}
-	if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
-		return -EINVAL;
 	rc_mpss = parent->pcie_mpss;
 	rc_mps = ffs(pcie_get_mps(parent)) - 8;
 	/* Find out supported and configured values for endpoint (us) */
 		ep_mrrs = max_mrrs;
 		pcie_set_readrq(dd->pcidev, ep_mrrs);
 	}
-	return 0;
 }
 /* End of PCIe capability tuning */

drivers/infiniband/hw/hfi1/platform.c+3−1

 	 * reuse of stale settings established in our previous pass through.
 	 */
 	if (ppd->qsfp_info.reset_needed) {
-		reset_qsfp(ppd);
+		ret = reset_qsfp(ppd);
+		if (ret)
+			return ret;
 		refresh_qsfp_cache(ppd, &ppd->qsfp_info);
 	} else {
 		ppd->qsfp_info.reset_needed = 1;

drivers/infiniband/hw/i40iw/i40iw.h+0−1

@@ -201,7 +201,6 @@ enum init_completion_state { · 200 unmodified lines
201	CEQ_CREATED,	201	CEQ_CREATED,
202	ILQ_CREATED,	202	ILQ_CREATED,
203	IEQ_CREATED,	203	IEQ_CREATED,
204	INET_NOTIFIER,
205	IP_ADDR_REGISTERED,	204	IP_ADDR_REGISTERED,
206	RDMA_DEV_REGISTERED	205	RDMA_DEV_REGISTERED
207	};	206	};

drivers/infiniband/hw/i40iw/i40iw_cm.c+77−77

@@ -1504,23 +1504,40 @@ static void i40iw_add_hte_node(struct i40iw_cm_core *cm_core, · 1503 unmodified lines
1504	}	1504	}
1505		1505
1506	/**	1506	/**
1507	* listen_port_in_use - determine if port is in use	1507	* i40iw_port_in_use - determine if port is in use
1508	* @port: Listen port number	1508	* @port: port number
		1509	* @active_side: flag for listener side vs active side
1509	*/	1510	*/
1510	static bool i40iw_listen_port_in_use(struct i40iw_cm_core *cm_core, u16 port)	1511	static bool i40iw_port_in_use(struct i40iw_cm_core *cm_core, u16 port, bool active_side)
1511	{	1512	{
1512	struct i40iw_cm_listener *listen_node;	1513	struct i40iw_cm_listener *listen_node;
		1514	struct i40iw_cm_node *cm_node;
1513	unsigned long flags;	1515	unsigned long flags;
1514	bool ret = false;	1516	bool ret = false;
1515		1517
1516	spin_lock_irqsave(&cm_core->listen_list_lock, flags);	1518	if (active_side) {
1517	list_for_each_entry(listen_node, &cm_core->listen_nodes, list) {	1519	/* search connected node list */
1518	if (listen_node->loc_port == port) {	1520	spin_lock_irqsave(&cm_core->ht_lock, flags);
1519	ret = true;	1521	list_for_each_entry(cm_node, &cm_core->connected_nodes, list) {
1520	break;	1522	if (cm_node->loc_port == port) {
		1523	ret = true;
		1524	break;
		1525	}
		1526	}
		1527	if (!ret)
		1528	clear_bit(port, cm_core->active_side_ports);
		1529	spin_unlock_irqrestore(&cm_core->ht_lock, flags);
		1530	} else {
		1531	spin_lock_irqsave(&cm_core->listen_list_lock, flags);
		1532	list_for_each_entry(listen_node, &cm_core->listen_nodes, list) {
		1533	if (listen_node->loc_port == port) {
		1534	ret = true;
		1535	break;
		1536	}
1521	}	1537	}
		1538	spin_unlock_irqrestore(&cm_core->listen_list_lock, flags);
1522	}	1539	}
1523	spin_unlock_irqrestore(&cm_core->listen_list_lock, flags);	1540
1524	return ret;	1541	return ret;
1525	}	1542	}
1526		1543
@@ -1868,7 +1885,7 @@ static int i40iw_dec_refcnt_listen(struct i40iw_cm_core *cm_core, · 341 unmodified lines
1868	spin_unlock_irqrestore(&cm_core->listen_list_lock, flags);	1885	spin_unlock_irqrestore(&cm_core->listen_list_lock, flags);
1869		1886
1870	if (listener->iwdev) {	1887	if (listener->iwdev) {
1871	if (apbvt_del && !i40iw_listen_port_in_use(cm_core, listener->loc_port))	1888	if (apbvt_del && !i40iw_port_in_use(cm_core, listener->loc_port, false))
1872	i40iw_manage_apbvt(listener->iwdev,	1889	i40iw_manage_apbvt(listener->iwdev,
1873	listener->loc_port,	1890	listener->loc_port,
1874	I40IW_MANAGE_APBVT_DEL);	1891	I40IW_MANAGE_APBVT_DEL);
@@ -2247,21 +2264,21 @@ static void i40iw_rem_ref_cm_node(struct i40iw_cm_node *cm_node) · 372 unmodified lines
2247	if (cm_node->listener) {	2264	if (cm_node->listener) {
2248	i40iw_dec_refcnt_listen(cm_core, cm_node->listener, 0, true);	2265	i40iw_dec_refcnt_listen(cm_core, cm_node->listener, 0, true);
2249	} else {	2266	} else {
2250	if (!i40iw_listen_port_in_use(cm_core, cm_node->loc_port) &&	2267	if (!i40iw_port_in_use(cm_core, cm_node->loc_port, true) && cm_node->apbvt_set) {
2251	cm_node->apbvt_set) {
2252	i40iw_manage_apbvt(cm_node->iwdev,	2268	i40iw_manage_apbvt(cm_node->iwdev,
2253	cm_node->loc_port,	2269	cm_node->loc_port,
2254	I40IW_MANAGE_APBVT_DEL);	2270	I40IW_MANAGE_APBVT_DEL);
2255	i40iw_get_addr_info(cm_node, &nfo);	2271	cm_node->apbvt_set = 0;
2256	if (cm_node->qhash_set) {	2272	}
2257	i40iw_manage_qhash(cm_node->iwdev,	2273	i40iw_get_addr_info(cm_node, &nfo);
2258	&nfo,	2274	if (cm_node->qhash_set) {
2259	I40IW_QHASH_TYPE_TCP_ESTABLISHED,	2275	i40iw_manage_qhash(cm_node->iwdev,
2260	I40IW_QHASH_MANAGE_TYPE_DELETE,	2276	&nfo,
2261	NULL,	2277	I40IW_QHASH_TYPE_TCP_ESTABLISHED,
2262	false);	2278	I40IW_QHASH_MANAGE_TYPE_DELETE,
2263	cm_node->qhash_set = 0;	2279	NULL,
2264	}	2280	false);
		2281	cm_node->qhash_set = 0;
2265	}	2282	}
2266	}	2283	}
2267		2284
@@ -3255,7 +3272,8 @@ static void i40iw_init_tcp_ctx(struct i40iw_cm_node *cm_node, · 987 unmodified lines
3255	tcp_info->snd_mss = cpu_to_le32(((u32)cm_node->tcp_cntxt.mss));	3272	tcp_info->snd_mss = cpu_to_le32(((u32)cm_node->tcp_cntxt.mss));
3256	if (cm_node->vlan_id < VLAN_TAG_PRESENT) {	3273	if (cm_node->vlan_id < VLAN_TAG_PRESENT) {
3257	tcp_info->insert_vlan_tag = true;	3274	tcp_info->insert_vlan_tag = true;
3258	tcp_info->vlan_tag = cpu_to_le16(cm_node->vlan_id);	3275	tcp_info->vlan_tag = cpu_to_le16(((u16)cm_node->user_pri << I40IW_VLAN_PRIO_SHIFT) \|
		3276	cm_node->vlan_id);
3259	}	3277	}
3260	if (cm_node->ipv4) {	3278	if (cm_node->ipv4) {
3261	tcp_info->src_port = cpu_to_le16(cm_node->loc_port);	3279	tcp_info->src_port = cpu_to_le16(cm_node->loc_port);
@@ -3737,10 +3755,8 @@ int i40iw_connect(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param) · 475 unmodified lines
3737	struct sockaddr_in *raddr;	3755	struct sockaddr_in *raddr;
3738	struct sockaddr_in6 *laddr6;	3756	struct sockaddr_in6 *laddr6;
3739	struct sockaddr_in6 *raddr6;	3757	struct sockaddr_in6 *raddr6;
3740	bool qhash_set = false;	3758	int ret = 0;
3741	int apbvt_set = 0;	3759	unsigned long flags;
3742	int err = 0;
3743	enum i40iw_status_code status;
3744		3760
3745	ibqp = i40iw_get_qp(cm_id->device, conn_param->qpn);	3761	ibqp = i40iw_get_qp(cm_id->device, conn_param->qpn);
3746	if (!ibqp)	3762	if (!ibqp)
@@ -3789,32 +3805,6 @@ int i40iw_connect(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param) · 42 unmodified lines
3789	cm_info.user_pri = rt_tos2priority(cm_id->tos);	3805	cm_info.user_pri = rt_tos2priority(cm_id->tos);
3790	i40iw_debug(&iwdev->sc_dev, I40IW_DEBUG_DCB, "%s TOS:[%d] UP:[%d]\n",	3806	i40iw_debug(&iwdev->sc_dev, I40IW_DEBUG_DCB, "%s TOS:[%d] UP:[%d]\n",
3791	__func__, cm_id->tos, cm_info.user_pri);	3807	__func__, cm_id->tos, cm_info.user_pri);
3792	if ((cm_info.ipv4 && (laddr->sin_addr.s_addr != raddr->sin_addr.s_addr)) \|\|
3793	(!cm_info.ipv4 && memcmp(laddr6->sin6_addr.in6_u.u6_addr32,
3794	raddr6->sin6_addr.in6_u.u6_addr32,
3795	sizeof(laddr6->sin6_addr.in6_u.u6_addr32)))) {
3796	status = i40iw_manage_qhash(iwdev,
3797	&cm_info,
3798	I40IW_QHASH_TYPE_TCP_ESTABLISHED,
3799	I40IW_QHASH_MANAGE_TYPE_ADD,
3800	NULL,
3801	true);
3802	if (status)
3803	return -EINVAL;
3804	qhash_set = true;
3805	}
3806	status = i40iw_manage_apbvt(iwdev, cm_info.loc_port, I40IW_MANAGE_APBVT_ADD);
3807	if (status) {
3808	i40iw_manage_qhash(iwdev,
3809	&cm_info,
3810	I40IW_QHASH_TYPE_TCP_ESTABLISHED,
3811	I40IW_QHASH_MANAGE_TYPE_DELETE,
3812	NULL,
3813	false);
3814	return -EINVAL;
3815	}
3816
3817	apbvt_set = 1;
3818	cm_id->add_ref(cm_id);	3808	cm_id->add_ref(cm_id);
3819	cm_node = i40iw_create_cm_node(&iwdev->cm_core, iwdev,	3809	cm_node = i40iw_create_cm_node(&iwdev->cm_core, iwdev,
3820	conn_param->private_data_len,	3810	conn_param->private_data_len,
@@ -3822,17 +3812,40 @@ int i40iw_connect(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param) · 1 unmodified line
3822	&cm_info);	3812	&cm_info);
3823		3813
3824	if (IS_ERR(cm_node)) {	3814	if (IS_ERR(cm_node)) {
3825	err = PTR_ERR(cm_node);	3815	ret = PTR_ERR(cm_node);
3826	goto err_out;	3816	cm_id->rem_ref(cm_id);
		3817	return ret;
		3818	}
		3819
		3820	if ((cm_info.ipv4 && (laddr->sin_addr.s_addr != raddr->sin_addr.s_addr)) \|\|
		3821	(!cm_info.ipv4 && memcmp(laddr6->sin6_addr.in6_u.u6_addr32,
		3822	raddr6->sin6_addr.in6_u.u6_addr32,
		3823	sizeof(laddr6->sin6_addr.in6_u.u6_addr32)))) {
		3824	if (i40iw_manage_qhash(iwdev, &cm_info, I40IW_QHASH_TYPE_TCP_ESTABLISHED,
		3825	I40IW_QHASH_MANAGE_TYPE_ADD, NULL, true)) {
		3826	ret = -EINVAL;
		3827	goto err;
		3828	}
		3829	cm_node->qhash_set = true;
3827	}	3830	}
3828		3831
		3832	spin_lock_irqsave(&iwdev->cm_core.ht_lock, flags);
		3833	if (!test_and_set_bit(cm_info.loc_port, iwdev->cm_core.active_side_ports)) {
		3834	spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags);
		3835	if (i40iw_manage_apbvt(iwdev, cm_info.loc_port, I40IW_MANAGE_APBVT_ADD)) {
		3836	ret = -EINVAL;
		3837	goto err;
		3838	}
		3839	} else {
		3840	spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags);
		3841	}
		3842
		3843	cm_node->apbvt_set = true;
3829	i40iw_record_ird_ord(cm_node, (u16)conn_param->ird, (u16)conn_param->ord);	3844	i40iw_record_ird_ord(cm_node, (u16)conn_param->ird, (u16)conn_param->ord);
3830	if (cm_node->send_rdma0_op == SEND_RDMA_READ_ZERO &&	3845	if (cm_node->send_rdma0_op == SEND_RDMA_READ_ZERO &&
3831	!cm_node->ord_size)	3846	!cm_node->ord_size)
3832	cm_node->ord_size = 1;	3847	cm_node->ord_size = 1;
3833		3848
3834	cm_node->apbvt_set = apbvt_set;
3835	cm_node->qhash_set = qhash_set;
3836	iwqp->cm_node = cm_node;	3849	iwqp->cm_node = cm_node;
3837	cm_node->iwqp = iwqp;	3850	cm_node->iwqp = iwqp;
3838	iwqp->cm_id = cm_id;	3851	iwqp->cm_id = cm_id;
@@ -3840,11 +3853,9 @@ int i40iw_connect(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param) · 1 unmodified line
3840		3853
3841	if (cm_node->state != I40IW_CM_STATE_OFFLOADED) {	3854	if (cm_node->state != I40IW_CM_STATE_OFFLOADED) {
3842	cm_node->state = I40IW_CM_STATE_SYN_SENT;	3855	cm_node->state = I40IW_CM_STATE_SYN_SENT;
3843	err = i40iw_send_syn(cm_node, 0);	3856	ret = i40iw_send_syn(cm_node, 0);
3844	if (err) {	3857	if (ret)
3845	i40iw_rem_ref_cm_node(cm_node);	3858	goto err;
3846	goto err_out;
3847	}
3848	}	3859	}
3849		3860
3850	i40iw_debug(cm_node->dev,	3861	i40iw_debug(cm_node->dev,
@@ -3853,9 +3864,10 @@ int i40iw_connect(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param) · 2 unmodified lines
3853	cm_node->rem_port,	3864	cm_node->rem_port,
3854	cm_node,	3865	cm_node,
3855	cm_node->cm_id);	3866	cm_node->cm_id);
		3867
3856	return 0;	3868	return 0;
3857		3869
3858	err_out:	3870	err:
3859	if (cm_info.ipv4)	3871	if (cm_info.ipv4)
3860	i40iw_debug(&iwdev->sc_dev,	3872	i40iw_debug(&iwdev->sc_dev,
3861	I40IW_DEBUG_CM,	3873	I40IW_DEBUG_CM,
@@ -3867,22 +3879,10 @@ err_out: · 5 unmodified lines
3867	"Api - connect() FAILED: dest addr=%pI6",	3879	"Api - connect() FAILED: dest addr=%pI6",
3868	cm_info.rem_addr);	3880	cm_info.rem_addr);
3869		3881
3870	if (qhash_set)	3882	i40iw_rem_ref_cm_node(cm_node);
3871	i40iw_manage_qhash(iwdev,
3872	&cm_info,
3873	I40IW_QHASH_TYPE_TCP_ESTABLISHED,
3874	I40IW_QHASH_MANAGE_TYPE_DELETE,
3875	NULL,
3876	false);
3877
3878	if (apbvt_set && !i40iw_listen_port_in_use(&iwdev->cm_core,
3879	cm_info.loc_port))
3880	i40iw_manage_apbvt(iwdev,
3881	cm_info.loc_port,
3882	I40IW_MANAGE_APBVT_DEL);
3883	cm_id->rem_ref(cm_id);	3883	cm_id->rem_ref(cm_id);
3884	iwdev->cm_core.stats_connect_errs++;	3884	iwdev->cm_core.stats_connect_errs++;
3885	return err;	3885	return ret;
3886	}	3886	}
3887		3887
3888	/**	3888	/**

drivers/infiniband/hw/i40iw/i40iw_cm.h+5−0

 #define	I40IW_HW_IRD_SETTING_32	32
 #define	I40IW_HW_IRD_SETTING_64	64
+#define MAX_PORTS		65536
+#define I40IW_VLAN_PRIO_SHIFT   13
 enum ietf_mpa_flags {
 	IETF_MPA_FLAGS_MARKERS = 0x80,	/* receive Markers */
 	IETF_MPA_FLAGS_CRC = 0x40,	/* receive Markers */
 	spinlock_t ht_lock; /* manage hash table */
 	spinlock_t listen_list_lock; /* listen list */
+	unsigned long active_side_ports[BITS_TO_LONGS(MAX_PORTS)];
 	u64	stats_nodes_created;
 	u64	stats_nodes_destroyed;
 	u64	stats_listen_created;

drivers/infiniband/hw/i40iw/i40iw_ctrl.c+1−1

@@ -48,7 +48,7 @@ · 47 unmodified lines
48	* @wqe: cqp wqe for header	48	* @wqe: cqp wqe for header
49	* @header: header for the cqp wqe	49	* @header: header for the cqp wqe
50	*/	50	*/
51	static inline void i40iw_insert_wqe_hdr(u64 *wqe, u64 header)	51	void i40iw_insert_wqe_hdr(u64 *wqe, u64 header)
52	{	52	{
53	wmb(); /* make sure WQE is populated before polarity is set */	53	wmb(); /* make sure WQE is populated before polarity is set */
54	set_64bit_val(wqe, 24, header);	54	set_64bit_val(wqe, 24, header);

drivers/infiniband/hw/i40iw/i40iw_main.c+23−16

@@ -99,8 +99,6 @@ static struct notifier_block i40iw_net_notifier = { · 98 unmodified lines
99	.notifier_call = i40iw_net_event	99	.notifier_call = i40iw_net_event
100	};	100	};
101		101
102	static atomic_t i40iw_notifiers_registered;
103
104	/**	102	/**
105	* i40iw_find_i40e_handler - find a handler given a client info	103	* i40iw_find_i40e_handler - find a handler given a client info
106	* @ldev: pointer to a client info	104	* @ldev: pointer to a client info
@@ -1376,11 +1374,20 @@ error: · 1269 unmodified lines
1376	*/	1374	*/
1377	static void i40iw_register_notifiers(void)	1375	static void i40iw_register_notifiers(void)
1378	{	1376	{
1379	if (atomic_inc_return(&i40iw_notifiers_registered) == 1) {	1377	register_inetaddr_notifier(&i40iw_inetaddr_notifier);
1380	register_inetaddr_notifier(&i40iw_inetaddr_notifier);	1378	register_inet6addr_notifier(&i40iw_inetaddr6_notifier);
1381	register_inet6addr_notifier(&i40iw_inetaddr6_notifier);	1379	register_netevent_notifier(&i40iw_net_notifier);
1382	register_netevent_notifier(&i40iw_net_notifier);	1380	}
1383	}	1381
		1382	/**
		1383	* i40iw_unregister_notifiers - unregister tcp ip notifiers
		1384	*/
		1385
		1386	static void i40iw_unregister_notifiers(void)
		1387	{
		1388	unregister_netevent_notifier(&i40iw_net_notifier);
		1389	unregister_inetaddr_notifier(&i40iw_inetaddr_notifier);
		1390	unregister_inet6addr_notifier(&i40iw_inetaddr6_notifier);
1384	}	1391	}
1385		1392
1386	/**	1393	/**
@@ -1400,6 +1407,11 @@ static enum i40iw_status_code i40iw_save_msix_info(struct i40iw_device *iwdev, · 13 unmodified lines
1400	u32 i;	1407	u32 i;
1401	u32 size;	1408	u32 size;
1402		1409
		1410	if (!ldev->msix_count) {
		1411	i40iw_pr_err("No MSI-X vectors\n");
		1412	return I40IW_ERR_CONFIG;
		1413	}
		1414
1403	iwdev->msix_count = ldev->msix_count;	1415	iwdev->msix_count = ldev->msix_count;
1404		1416
1405	size = sizeof(struct i40iw_msix_vector) * iwdev->msix_count;	1417	size = sizeof(struct i40iw_msix_vector) * iwdev->msix_count;
@@ -1462,12 +1474,6 @@ static void i40iw_deinit_device(struct i40iw_device *iwdev) · 56 unmodified lines
1462	if (!iwdev->reset)	1474	if (!iwdev->reset)
1463	i40iw_del_macip_entry(iwdev, (u8)iwdev->mac_ip_table_idx);	1475	i40iw_del_macip_entry(iwdev, (u8)iwdev->mac_ip_table_idx);
1464	/* fallthrough */	1476	/* fallthrough */
1465	case INET_NOTIFIER:
1466	if (!atomic_dec_return(&i40iw_notifiers_registered)) {
1467	unregister_netevent_notifier(&i40iw_net_notifier);
1468	unregister_inetaddr_notifier(&i40iw_inetaddr_notifier);
1469	unregister_inet6addr_notifier(&i40iw_inetaddr6_notifier);
1470	}
1471	/* fallthrough */	1477	/* fallthrough */
1472	case PBLE_CHUNK_MEM:	1478	case PBLE_CHUNK_MEM:
1473	i40iw_destroy_pble_pool(dev, iwdev->pble_rsrc);	1479	i40iw_destroy_pble_pool(dev, iwdev->pble_rsrc);
@@ -1550,7 +1556,7 @@ static enum i40iw_status_code i40iw_setup_init_state(struct i40iw_handler *hdl, · 76 unmodified lines
1550		1556
1551	status = i40iw_save_msix_info(iwdev, ldev);	1557	status = i40iw_save_msix_info(iwdev, ldev);
1552	if (status)	1558	if (status)
1553	goto exit;	1559	return status;
1554	iwdev->hw.dev_context = (void *)ldev->pcidev;	1560	iwdev->hw.dev_context = (void *)ldev->pcidev;
1555	iwdev->hw.hw_addr = ldev->hw_addr;	1561	iwdev->hw.hw_addr = ldev->hw_addr;
1556	status = i40iw_allocate_dma_mem(&iwdev->hw,	1562	status = i40iw_allocate_dma_mem(&iwdev->hw,
@@ -1667,8 +1673,6 @@ static int i40iw_open(struct i40e_info ldev, struct i40e_client client) · 110 unmodified lines
1667	break;	1673	break;
1668	iwdev->init_state = PBLE_CHUNK_MEM;	1674	iwdev->init_state = PBLE_CHUNK_MEM;
1669	iwdev->virtchnl_wq = alloc_ordered_workqueue("iwvch", WQ_MEM_RECLAIM);	1675	iwdev->virtchnl_wq = alloc_ordered_workqueue("iwvch", WQ_MEM_RECLAIM);
1670	i40iw_register_notifiers();
1671	iwdev->init_state = INET_NOTIFIER;
1672	status = i40iw_add_mac_ip(iwdev);	1676	status = i40iw_add_mac_ip(iwdev);
1673	if (status)	1677	if (status)
1674	break;	1678	break;
@@ -2018,6 +2022,8 @@ static int __init i40iw_init_module(void) · 343 unmodified lines
2018	i40iw_client.type = I40E_CLIENT_IWARP;	2022	i40iw_client.type = I40E_CLIENT_IWARP;
2019	spin_lock_init(&i40iw_handler_lock);	2023	spin_lock_init(&i40iw_handler_lock);
2020	ret = i40e_register_client(&i40iw_client);	2024	ret = i40e_register_client(&i40iw_client);
		2025	i40iw_register_notifiers();
		2026
2021	return ret;	2027	return ret;
2022	}	2028	}
2023		2029
@@ -2029,6 +2035,7 @@ static int __init i40iw_init_module(void) · 5 unmodified lines
2029	*/	2035	*/
2030	static void __exit i40iw_exit_module(void)	2036	static void __exit i40iw_exit_module(void)
2031	{	2037	{
		2038	i40iw_unregister_notifiers();
2032	i40e_unregister_client(&i40iw_client);	2039	i40e_unregister_client(&i40iw_client);
2033	}	2040	}
2034		2041

drivers/infiniband/hw/i40iw/i40iw_p.h+2−0

@@ -59,6 +59,8 @@ enum i40iw_status_code i40iw_sc_mr_fast_register(struct i40iw_sc_qp *qp, · 58 unmodified lines
59	struct i40iw_fast_reg_stag_info *info,	59	struct i40iw_fast_reg_stag_info *info,
60	bool post_sq);	60	bool post_sq);
61		61
		62	void i40iw_insert_wqe_hdr(u64 *wqe, u64 header);
		63
62	/* HMC/FPM functions */	64	/* HMC/FPM functions */
63	enum i40iw_status_code i40iw_sc_init_iw_hmc(struct i40iw_sc_dev *dev,	65	enum i40iw_status_code i40iw_sc_init_iw_hmc(struct i40iw_sc_dev *dev,
64	u8 hmc_fn_id);	66	u8 hmc_fn_id);

drivers/infiniband/hw/i40iw/i40iw_puda.c+4−7

 		get_64bit_val(wqe, 24, &offset24);
 	offset24 = (offset24) ? 0 : LS_64(1, I40IWQPSQ_VALID);
-	set_64bit_val(wqe, 24, offset24);
 	set_64bit_val(wqe, 0, buf->mem.pa);
 	set_64bit_val(wqe, 8,
 		      LS_64(buf->mem.size, I40IWQPSQ_FRAG_LEN));
-	set_64bit_val(wqe, 24, offset24);
+	i40iw_insert_wqe_hdr(wqe, offset24);
 }
 /**
 	set_64bit_val(wqe, 8, LS_64(info->len, I40IWQPSQ_FRAG_LEN));
 	set_64bit_val(wqe, 16, header[0]);
-	/* Ensure all data is written before writing valid bit */
+	i40iw_insert_wqe_hdr(wqe, header[1]);
-	wmb();
-	set_64bit_val(wqe, 24, header[1]);
 	i40iw_debug_buf(qp->dev, I40IW_DEBUG_PUDA, "PUDA SEND WQE", wqe, 32);
 	i40iw_qp_post_wr(&qp->qp_uk);
 		 LS_64(2, I40IW_CQPSQ_QP_NEXTIWSTATE) |
 		 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
-	set_64bit_val(wqe, 24, header);
+	i40iw_insert_wqe_hdr(wqe, header);
 	i40iw_debug_buf(cqp->dev, I40IW_DEBUG_PUDA, "PUDA CQE", wqe, 32);
 	i40iw_sc_cqp_post_sq(cqp);
 	    LS_64(1, I40IW_CQPSQ_CQ_ENCEQEMASK) |
 	    LS_64(1, I40IW_CQPSQ_CQ_CEQIDVALID) |
 	    LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
-	set_64bit_val(wqe, 24, header);
+	i40iw_insert_wqe_hdr(wqe, header);
 	i40iw_debug_buf(dev, I40IW_DEBUG_PUDA, "PUDA CQE",
 			wqe, I40IW_CQP_WQE_SIZE * 8);

drivers/infiniband/hw/i40iw/i40iw_utils.c+3−3

@@ -160,7 +160,7 @@ int i40iw_inetaddr_event(struct notifier_block *notifier, · 159 unmodified lines
160	return NOTIFY_DONE;	160	return NOTIFY_DONE;
161		161
162	iwdev = &hdl->device;	162	iwdev = &hdl->device;
163	if (iwdev->init_state < INET_NOTIFIER)	163	if (iwdev->init_state < IP_ADDR_REGISTERED \|\| iwdev->closing)
164	return NOTIFY_DONE;	164	return NOTIFY_DONE;
165		165
166	netdev = iwdev->ldev->netdev;	166	netdev = iwdev->ldev->netdev;
@@ -217,7 +217,7 @@ int i40iw_inet6addr_event(struct notifier_block *notifier, · 50 unmodified lines
217	return NOTIFY_DONE;	217	return NOTIFY_DONE;
218		218
219	iwdev = &hdl->device;	219	iwdev = &hdl->device;
220	if (iwdev->init_state < INET_NOTIFIER)	220	if (iwdev->init_state < IP_ADDR_REGISTERED \|\| iwdev->closing)
221	return NOTIFY_DONE;	221	return NOTIFY_DONE;
222		222
223	netdev = iwdev->ldev->netdev;	223	netdev = iwdev->ldev->netdev;
@@ -266,7 +266,7 @@ int i40iw_net_event(struct notifier_block notifier, unsigned long event, void · 42 unmodified lines
266	if (!iwhdl)	266	if (!iwhdl)
267	return NOTIFY_DONE;	267	return NOTIFY_DONE;
268	iwdev = &iwhdl->device;	268	iwdev = &iwhdl->device;
269	if (iwdev->init_state < INET_NOTIFIER)	269	if (iwdev->init_state < IP_ADDR_REGISTERED \|\| iwdev->closing)
270	return NOTIFY_DONE;	270	return NOTIFY_DONE;
271	p = (__be32 *)neigh->primary_key;	271	p = (__be32 *)neigh->primary_key;
272	i40iw_copy_ip_ntohl(local_ipaddr, p);	272	i40iw_copy_ip_ntohl(local_ipaddr, p);

drivers/infiniband/hw/i40iw/i40iw_verbs.c+14−0

 	attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
 	attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
 	attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
+	attr->port_num = 1;
 	init_attr->event_handler = iwqp->ibqp.event_handler;
 	init_attr->qp_context = iwqp->ibqp.qp_context;
 	init_attr->send_cq = iwqp->ibqp.send_cq;
 	init_attr->recv_cq = iwqp->ibqp.recv_cq;
 	init_attr->srq = iwqp->ibqp.srq;
 	init_attr->cap = attr->cap;
+	init_attr->port_num = 1;
 	return 0;
 }
 				iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSED;
 				iwqp->last_aeq = I40IW_AE_RESET_SENT;
 				spin_unlock_irqrestore(&iwqp->lock, flags);
+				i40iw_cm_disconn(iwqp);
 			}
+		} else {
+			spin_lock_irqsave(&iwqp->lock, flags);
+			if (iwqp->cm_id) {
+				if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
+					iwqp->cm_id->add_ref(iwqp->cm_id);
+					i40iw_schedule_cm_timer(iwqp->cm_node,
+								(struct i40iw_puda_buf *)iwqp,
+								 I40IW_TIMER_TYPE_CLOSE, 1, 0);
+				}
+			}
+			spin_unlock_irqrestore(&iwqp->lock, flags);
 		}
 	}
 	return 0;

drivers/infiniband/hw/mlx5/main.c+10−10

 	}
 	if (MLX5_CAP_GEN(mdev, tag_matching)) {
-		props->xrq_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
+		props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
-		props->xrq_caps.max_num_tags =
+		props->tm_caps.max_num_tags =
 			(1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
-		props->xrq_caps.flags = IB_TM_CAP_RC;
+		props->tm_caps.flags = IB_TM_CAP_RC;
-		props->xrq_caps.max_ops =
+		props->tm_caps.max_ops =
 			1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
-		props->xrq_caps.max_sge = MLX5_TM_MAX_SGE;
+		props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
 	}
 	if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 	if (!dbg)
 		return -ENOMEM;
+	dev->delay_drop.dbg = dbg;
 	dbg->dir_debugfs =
 		debugfs_create_dir("delay_drop",
 				   dev->mdev->priv.dbg_root);
 	if (!dbg->dir_debugfs)
-		return -ENOMEM;
+		goto out_debugfs;
 	dbg->events_cnt_debugfs =
 		debugfs_create_atomic_t("num_timeout_events", 0400,
 	if (!dbg->timeout_debugfs)
 		goto out_debugfs;
-	dev->delay_drop.dbg = dbg;
 	return 0;
 out_debugfs:
 err_uar_page:
 	mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
-err_cnt:
-	mlx5_ib_cleanup_cong_debugfs(dev);
 err_cong:
+	mlx5_ib_cleanup_cong_debugfs(dev);
+err_cnt:
 	if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
 		mlx5_ib_dealloc_counters(dev);

drivers/infiniband/hw/mlx5/mem.c+17−30

@@ -50,13 +50,9 @@ void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, · 49 unmodified lines
50	{	50	{
51	unsigned long tmp;	51	unsigned long tmp;
52	unsigned long m;	52	unsigned long m;
53	int i, k;	53	u64 base = ~0, p = 0;
54	u64 base = 0;	54	u64 len, pfn;
55	int p = 0;	55	int i = 0;
56	int skip;
57	int mask;
58	u64 len;
59	u64 pfn;
60	struct scatterlist *sg;	56	struct scatterlist *sg;
61	int entry;	57	int entry;
62	unsigned long page_shift = umem->page_shift;	58	unsigned long page_shift = umem->page_shift;
@@ -76,33 +72,24 @@ void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, · 13 unmodified lines
76	m = find_first_bit(&tmp, BITS_PER_LONG);	72	m = find_first_bit(&tmp, BITS_PER_LONG);
77	if (max_page_shift)	73	if (max_page_shift)
78	m = min_t(unsigned long, max_page_shift - page_shift, m);	74	m = min_t(unsigned long, max_page_shift - page_shift, m);
79	skip = 1 << m;	75
80	mask = skip - 1;
81	i = 0;
82	for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {	76	for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
83	len = sg_dma_len(sg) >> page_shift;	77	len = sg_dma_len(sg) >> page_shift;
84	pfn = sg_dma_address(sg) >> page_shift;	78	pfn = sg_dma_address(sg) >> page_shift;
85	for (k = 0; k < len; k++) {	79	if (base + p != pfn) {
86	if (!(i & mask)) {	80	/* If either the offset or the new
87	tmp = (unsigned long)pfn;	81	* base are unaligned update m
88	m = min_t(unsigned long, m, find_first_bit(&tmp, BITS_PER_LONG));	82	*/
89	skip = 1 << m;	83	tmp = (unsigned long)(pfn \| p);
90	mask = skip - 1;	84	if (!IS_ALIGNED(tmp, 1 << m))
91	base = pfn;	85	m = find_first_bit(&tmp, BITS_PER_LONG);
92	p = 0;	86
93	} else {	87	base = pfn;
94	if (base + p != pfn) {	88	p = 0;
95	tmp = (unsigned long)p;
96	m = find_first_bit(&tmp, BITS_PER_LONG);
97	skip = 1 << m;
98	mask = skip - 1;
99	base = pfn;
100	p = 0;
101	}
102	}
103	p++;
104	i++;
105	}	89	}
		90
		91	p += len;
		92	i += len;
106	}	93	}
107		94
108	if (i) {	95	if (i) {

drivers/infiniband/hw/mlx5/mr.c+17−10

 #define MLX5_UMR_ALIGN 2048
-static int clean_mr(struct mlx5_ib_mr *mr);
+static int clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
+static int dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
 static int mr_cache_max_order(struct mlx5_ib_dev *dev);
 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
 		err = mlx5_ib_update_xlt(mr, 0, ncont, page_shift,
 					 update_xlt_flags);
 		if (err) {
-			mlx5_ib_dereg_mr(&mr->ibmr);
+			dereg_mr(dev, mr);
 			return ERR_PTR(err);
 		}
 	}
 		err = mr_umem_get(pd, addr, len, access_flags, &mr->umem,
 				  &npages, &page_shift, &ncont, &order);
 		if (err < 0) {
-			clean_mr(mr);
+			clean_mr(dev, mr);
 			return err;
 		}
 	}
 		if (err) {
 			mlx5_ib_warn(dev, "Failed to rereg UMR\n");
 			ib_umem_release(mr->umem);
-			clean_mr(mr);
+			clean_mr(dev, mr);
 			return err;
 		}
 	}
 	}
 }
-static int clean_mr(struct mlx5_ib_mr *mr)
+static int clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
 {
-	struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device);
 	int allocated_from_cache = mr->allocated_from_cache;
 	int err;
 	return 0;
 }
-int mlx5_ib_dereg_mr(struct ib_mr *ibmr)
+static int dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
 {
-	struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
-	struct mlx5_ib_mr *mr = to_mmr(ibmr);
 	int npages = mr->npages;
 	struct ib_umem *umem = mr->umem;
 	}
 #endif
-	clean_mr(mr);
+	clean_mr(dev, mr);
 	if (umem) {
 		ib_umem_release(umem);
 	return 0;
 }
+int mlx5_ib_dereg_mr(struct ib_mr *ibmr)
+{
+	struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
+	struct mlx5_ib_mr *mr = to_mmr(ibmr);
+	return dereg_mr(dev, mr);
+}
 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
 			       enum ib_mr_type mr_type,
 			       u32 max_num_sg)

drivers/infiniband/hw/nes/nes_verbs.c+2−2

@@ -3232,7 +3232,7 @@ static int nes_post_send(struct ib_qp ibqp, struct ib_send_wr ib_wr, · 3231 unmodified lines
3232	mr->ibmr.iova);	3232	mr->ibmr.iova);
3233	set_wqe_32bit_value(wqe->wqe_words,	3233	set_wqe_32bit_value(wqe->wqe_words,
3234	NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX,	3234	NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX,
3235	mr->ibmr.length);	3235	lower_32_bits(mr->ibmr.length));
3236	set_wqe_32bit_value(wqe->wqe_words,	3236	set_wqe_32bit_value(wqe->wqe_words,
3237	NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX, 0);	3237	NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX, 0);
3238	set_wqe_32bit_value(wqe->wqe_words,	3238	set_wqe_32bit_value(wqe->wqe_words,
@@ -3274,7 +3274,7 @@ static int nes_post_send(struct ib_qp ibqp, struct ib_send_wr ib_wr, · 35 unmodified lines
3274	mr->npages * 8);	3274	mr->npages * 8);
3275		3275
3276	nes_debug(NES_DBG_IW_TX, "SQ_REG_MR: iova_start: %llx, "	3276	nes_debug(NES_DBG_IW_TX, "SQ_REG_MR: iova_start: %llx, "
3277	"length: %d, rkey: %0x, pgl_paddr: %llx, "	3277	"length: %lld, rkey: %0x, pgl_paddr: %llx, "
3278	"page_list_len: %u, wqe_misc: %x\n",	3278	"page_list_len: %u, wqe_misc: %x\n",
3279	(unsigned long long) mr->ibmr.iova,	3279	(unsigned long long) mr->ibmr.iova,
3280	mr->ibmr.length,	3280	mr->ibmr.length,

drivers/infiniband/hw/ocrdma/ocrdma_hw.c+3−0

 		case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
 			err_num = -EAGAIN;
 			break;
+		default:
+			err_num = -EFAULT;
 		}
+		break;
 	default:
 		err_num = -EFAULT;
 	}

drivers/infiniband/hw/qedr/qedr.h+1−1

@@ -387,7 +387,7 @@ struct qedr_qp { · 386 unmodified lines
387	u8 wqe_size;	387	u8 wqe_size;
388		388
389	u8 smac[ETH_ALEN];	389	u8 smac[ETH_ALEN];
390	u16 vlan_id;	390	u16 vlan;
391	int rc;	391	int rc;
392	} *rqe_wr_id;	392	} *rqe_wr_id;
393		393

drivers/infiniband/hw/qedr/qedr_cm.c+9−3

@@ -105,7 +105,7 @@ void qedr_ll2_complete_rx_packet(void *cxt, · 104 unmodified lines
105		105
106	qp->rqe_wr_id[qp->rq.gsi_cons].rc = data->u.data_length_error ?	106	qp->rqe_wr_id[qp->rq.gsi_cons].rc = data->u.data_length_error ?
107	-EINVAL : 0;	107	-EINVAL : 0;
108	qp->rqe_wr_id[qp->rq.gsi_cons].vlan_id = data->vlan;	108	qp->rqe_wr_id[qp->rq.gsi_cons].vlan = data->vlan;
109	/* note: length stands for data length i.e. GRH is excluded */	109	/* note: length stands for data length i.e. GRH is excluded */
110	qp->rqe_wr_id[qp->rq.gsi_cons].sg_list[0].length =	110	qp->rqe_wr_id[qp->rq.gsi_cons].sg_list[0].length =
111	data->length.data_length;	111	data->length.data_length;
@@ -694,6 +694,7 @@ int qedr_gsi_poll_cq(struct ib_cq ibcq, int num_entries, struct ib_wc wc) · 582 unmodified lines
694	struct qedr_cq *cq = get_qedr_cq(ibcq);	694	struct qedr_cq *cq = get_qedr_cq(ibcq);
695	struct qedr_qp *qp = dev->gsi_qp;	695	struct qedr_qp *qp = dev->gsi_qp;
696	unsigned long flags;	696	unsigned long flags;
		697	u16 vlan_id;
697	int i = 0;	698	int i = 0;
698		699
699	spin_lock_irqsave(&cq->cq_lock, flags);	700	spin_lock_irqsave(&cq->cq_lock, flags);
@@ -712,9 +713,14 @@ int qedr_gsi_poll_cq(struct ib_cq ibcq, int num_entries, struct ib_wc wc) · 12 unmodified lines
712	wc[i].wc_flags \|= IB_WC_GRH \| IB_WC_IP_CSUM_OK;	713	wc[i].wc_flags \|= IB_WC_GRH \| IB_WC_IP_CSUM_OK;
713	ether_addr_copy(wc[i].smac, qp->rqe_wr_id[qp->rq.cons].smac);	714	ether_addr_copy(wc[i].smac, qp->rqe_wr_id[qp->rq.cons].smac);
714	wc[i].wc_flags \|= IB_WC_WITH_SMAC;	715	wc[i].wc_flags \|= IB_WC_WITH_SMAC;
715	if (qp->rqe_wr_id[qp->rq.cons].vlan_id) {	716
		717	vlan_id = qp->rqe_wr_id[qp->rq.cons].vlan &
		718	VLAN_VID_MASK;
		719	if (vlan_id) {
716	wc[i].wc_flags \|= IB_WC_WITH_VLAN;	720	wc[i].wc_flags \|= IB_WC_WITH_VLAN;
717	wc[i].vlan_id = qp->rqe_wr_id[qp->rq.cons].vlan_id;	721	wc[i].vlan_id = vlan_id;
		722	wc[i].sl = (qp->rqe_wr_id[qp->rq.cons].vlan &
		723	VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
718	}	724	}
719		725
720	qedr_inc_sw_cons(&qp->rq);	726	qedr_inc_sw_cons(&qp->rq);

drivers/infiniband/hw/vmw_pvrdma/pvrdma.h+28−3

@@ -416,9 +416,34 @@ static inline enum ib_wc_status pvrdma_wc_status_to_ib( · 415 unmodified lines
416	return (enum ib_wc_status)status;	416	return (enum ib_wc_status)status;
417	}	417	}
418		418
419	static inline int pvrdma_wc_opcode_to_ib(int opcode)	419	static inline int pvrdma_wc_opcode_to_ib(unsigned int opcode)
420	{	420	{
421	return opcode;	421	switch (opcode) {
		422	case PVRDMA_WC_SEND:
		423	return IB_WC_SEND;
		424	case PVRDMA_WC_RDMA_WRITE:
		425	return IB_WC_RDMA_WRITE;
		426	case PVRDMA_WC_RDMA_READ:
		427	return IB_WC_RDMA_READ;
		428	case PVRDMA_WC_COMP_SWAP:
		429	return IB_WC_COMP_SWAP;
		430	case PVRDMA_WC_FETCH_ADD:
		431	return IB_WC_FETCH_ADD;
		432	case PVRDMA_WC_LOCAL_INV:
		433	return IB_WC_LOCAL_INV;
		434	case PVRDMA_WC_FAST_REG_MR:
		435	return IB_WC_REG_MR;
		436	case PVRDMA_WC_MASKED_COMP_SWAP:
		437	return IB_WC_MASKED_COMP_SWAP;
		438	case PVRDMA_WC_MASKED_FETCH_ADD:
		439	return IB_WC_MASKED_FETCH_ADD;
		440	case PVRDMA_WC_RECV:
		441	return IB_WC_RECV;
		442	case PVRDMA_WC_RECV_RDMA_WITH_IMM:
		443	return IB_WC_RECV_RDMA_WITH_IMM;
		444	default:
		445	return IB_WC_SEND;
		446	}
422	}	447	}
423		448
424	static inline int pvrdma_wc_flags_to_ib(int flags)	449	static inline int pvrdma_wc_flags_to_ib(int flags)

drivers/infiniband/ulp/ipoib/ipoib_cm.c+11−5

 	    wc->status != IB_WC_WR_FLUSH_ERR) {
 		struct ipoib_neigh *neigh;
-		if (wc->status != IB_WC_RNR_RETRY_EXC_ERR)
+		/* IB_WC[_RNR]_RETRY_EXC_ERR error is part of the life cycle,
-			ipoib_warn(priv, "failed cm send event (status=%d, wrid=%d vend_err %x)\n",
+		 * so don't make waves.
-				   wc->status, wr_id, wc->vendor_err);
+		 */
+		if (wc->status == IB_WC_RNR_RETRY_EXC_ERR ||
+		    wc->status == IB_WC_RETRY_EXC_ERR)
+			ipoib_dbg(priv,
+				  "%s: failed cm send event (status=%d, wrid=%d vend_err 0x%x)\n",
+				   __func__, wc->status, wr_id, wc->vendor_err);
 		else
-			ipoib_dbg(priv, "failed cm send event (status=%d, wrid=%d vend_err %x)\n",
+			ipoib_warn(priv,
-				  wc->status, wr_id, wc->vendor_err);
+				    "%s: failed cm send event (status=%d, wrid=%d vend_err 0x%x)\n",
+				   __func__, wc->status, wr_id, wc->vendor_err);
 		spin_lock_irqsave(&priv->lock, flags);
 		neigh = tx->neigh;

drivers/infiniband/ulp/ipoib/ipoib_ib.c+0−13

@@ -1000,19 +1000,6 @@ static inline int update_parent_pkey(struct ipoib_dev_priv *priv) · 999 unmodified lines
1000	*/	1000	*/
1001	priv->dev->broadcast[8] = priv->pkey >> 8;	1001	priv->dev->broadcast[8] = priv->pkey >> 8;
1002	priv->dev->broadcast[9] = priv->pkey & 0xff;	1002	priv->dev->broadcast[9] = priv->pkey & 0xff;
1003
1004	/*
1005	* Update the broadcast address in the priv->broadcast object,
1006	* in case it already exists, otherwise no one will do that.
1007	*/
1008	if (priv->broadcast) {
1009	spin_lock_irq(&priv->lock);
1010	memcpy(priv->broadcast->mcmember.mgid.raw,
1011	priv->dev->broadcast + 4,
1012	sizeof(union ib_gid));
1013	spin_unlock_irq(&priv->lock);
1014	}
1015
1016	return 0;	1003	return 0;
1017	}	1004	}
1018		1005

drivers/infiniband/ulp/ipoib/ipoib_main.c+11−4

 {
 	struct ipoib_dev_priv *priv;
 	struct ib_port_attr attr;
+	struct rdma_netdev *rn;
 	int result = -ENOMEM;
 	priv = ipoib_intf_alloc(hca, port, format);
 	ipoib_dev_cleanup(priv->dev);
 device_init_failed:
-	free_netdev(priv->dev);
+	rn = netdev_priv(priv->dev);
+	rn->free_rdma_netdev(priv->dev);
 	kfree(priv);
 alloc_mem_failed:
 		return;
 	list_for_each_entry_safe(priv, tmp, dev_list, list) {
-		struct rdma_netdev *rn = netdev_priv(priv->dev);
+		struct rdma_netdev *parent_rn = netdev_priv(priv->dev);
 		ib_unregister_event_handler(&priv->event_handler);
 		flush_workqueue(ipoib_workqueue);
 		unregister_netdev(priv->dev);
 		mutex_unlock(&priv->sysfs_mutex);
-		rn->free_rdma_netdev(priv->dev);
+		parent_rn->free_rdma_netdev(priv->dev);
+		list_for_each_entry_safe(cpriv, tcpriv, &priv->child_intfs, list) {
+			struct rdma_netdev *child_rn;
-		list_for_each_entry_safe(cpriv, tcpriv, &priv->child_intfs, list)
+			child_rn = netdev_priv(cpriv->dev);
+			child_rn->free_rdma_netdev(cpriv->dev);
 			kfree(cpriv);
+		}
 		kfree(priv);
 	}

drivers/infiniband/ulp/ipoib/ipoib_vlan.c+22−8

 		return restart_syscall();
 	}
-	priv = ipoib_intf_alloc(ppriv->ca, ppriv->port, intf_name);
+	if (!down_write_trylock(&ppriv->vlan_rwsem)) {
-	if (!priv) {
 		rtnl_unlock();
 		mutex_unlock(&ppriv->sysfs_mutex);
-		return -ENOMEM;
+		return restart_syscall();
 	}
-	down_write(&ppriv->vlan_rwsem);
+	priv = ipoib_intf_alloc(ppriv->ca, ppriv->port, intf_name);
+	if (!priv) {
+		result = -ENOMEM;
+		goto out;
+	}
 	/*
 	 * First ensure this isn't a duplicate. We check the parent device and
 	rtnl_unlock();
 	mutex_unlock(&ppriv->sysfs_mutex);
-	if (result) {
+	if (result && priv) {
-		free_netdev(priv->dev);
+		struct rdma_netdev *rn;
+		rn = netdev_priv(priv->dev);
+		rn->free_rdma_netdev(priv->dev);
 		kfree(priv);
 	}
 		return restart_syscall();
 	}
-	down_write(&ppriv->vlan_rwsem);
+	if (!down_write_trylock(&ppriv->vlan_rwsem)) {
+		rtnl_unlock();
+		mutex_unlock(&ppriv->sysfs_mutex);
+		return restart_syscall();
+	}
 	list_for_each_entry_safe(priv, tpriv, &ppriv->child_intfs, list) {
 		if (priv->pkey == pkey &&
 		    priv->child_type == IPOIB_LEGACY_CHILD) {
 	mutex_unlock(&ppriv->sysfs_mutex);
 	if (dev) {
-		free_netdev(dev);
+		struct rdma_netdev *rn;
+		rn = netdev_priv(dev);
+		rn->free_rdma_netdev(priv->dev);
 		kfree(priv);
 		return 0;
 	}

drivers/infiniband/ulp/iser/iser_memory.c+1−1

@@ -154,7 +154,7 @@ static void iser_dump_page_vec(struct iser_page_vec *page_vec) · 153 unmodified lines
154	{	154	{
155	int i;	155	int i;
156		156
157	iser_err("page vec npages %d data length %d\n",	157	iser_err("page vec npages %d data length %lld\n",
158	page_vec->npages, page_vec->fake_mr.length);	158	page_vec->npages, page_vec->fake_mr.length);
159	for (i = 0; i < page_vec->npages; i++)	159	for (i = 0; i < page_vec->npages; i++)
160	iser_err("vec[%d]: %llx\n", i, page_vec->pages[i]);	160	iser_err("vec[%d]: %llx\n", i, page_vec->pages[i]);

drivers/input/ff-core.c+10−3

 EXPORT_SYMBOL_GPL(input_ff_erase);
 /*
- * flush_effects - erase all effects owned by a file handle
+ * input_ff_flush - erase all effects owned by a file handle
+ * @dev: input device to erase effect from
+ * @file: purported owner of the effects
+ *
+ * This function erases all force-feedback effects associated with
+ * the given owner from specified device. Note that @file may be %NULL,
+ * in which case all effects will be erased.
  */
-static int flush_effects(struct input_dev *dev, struct file *file)
+int input_ff_flush(struct input_dev *dev, struct file *file)
 {
 	struct ff_device *ff = dev->ff;
 	int i;
 	return 0;
 }
+EXPORT_SYMBOL_GPL(input_ff_flush);
 /**
  * input_ff_event() - generic handler for force-feedback events
 	mutex_init(&ff->mutex);
 	dev->ff = ff;
-	dev->flush = flush_effects;
+	dev->flush = input_ff_flush;
 	dev->event = input_ff_event;
 	__set_bit(EV_FF, dev->evbit);

drivers/input/misc/uinput.c+39−18

 					uinput_request_alloc_id(udev, request));
 }
-static void uinput_request_done(struct uinput_device *udev,
+static void uinput_request_release_slot(struct uinput_device *udev,
-				struct uinput_request *request)
+					unsigned int id)
 {
 	/* Mark slot as available */
-	udev->requests[request->id] = NULL;
+	spin_lock(&udev->requests_lock);
-	wake_up(&udev->requests_waitq);
+	udev->requests[id] = NULL;
+	spin_unlock(&udev->requests_lock);
-	complete(&request->done);
+	wake_up(&udev->requests_waitq);
 }
 static int uinput_request_send(struct uinput_device *udev,
 static int uinput_request_submit(struct uinput_device *udev,
 				 struct uinput_request *request)
 {
-	int error;
+	int retval;
-	error = uinput_request_reserve_slot(udev, request);
+	retval = uinput_request_reserve_slot(udev, request);
-	if (error)
+	if (retval)
-		return error;
+		return retval;
-	error = uinput_request_send(udev, request);
+	retval = uinput_request_send(udev, request);
-	if (error) {
+	if (retval)
-		uinput_request_done(udev, request);
+		goto out;
-		return error;
-	}
 	wait_for_completion(&request->done);
-	return request->retval;
+	retval = request->retval;
+ out:
+	uinput_request_release_slot(udev, request->id);
+	return retval;
 }
 /*
 		request = udev->requests[i];
 		if (request) {
 			request->retval = -ENODEV;
-			uinput_request_done(udev, request);
+			complete(&request->done);
 		}
 	}
 	return uinput_request_submit(udev, &request);
 }
+static int uinput_dev_flush(struct input_dev *dev, struct file *file)
+{
+	/*
+	 * If we are called with file == NULL that means we are tearing
+	 * down the device, and therefore we can not handle FF erase
+	 * requests: either we are handling UI_DEV_DESTROY (and holding
+	 * the udev->mutex), or the file descriptor is closed and there is
+	 * nobody on the other side anymore.
+	 */
+	return file ? input_ff_flush(dev, file) : 0;
+}
 static void uinput_destroy_device(struct uinput_device *udev)
 {
 	const char *name, *phys;
 		dev->ff->playback = uinput_dev_playback;
 		dev->ff->set_gain = uinput_dev_set_gain;
 		dev->ff->set_autocenter = uinput_dev_set_autocenter;
+		/*
+		 * The standard input_ff_flush() implementation does
+		 * not quite work for uinput as we can't reasonably
+		 * handle FF requests during device teardown.
+		 */
+		dev->flush = uinput_dev_flush;
 	}
 	error = input_register_device(udev->dev);
 			}
 			req->retval = ff_up.retval;
-			uinput_request_done(udev, req);
+			complete(&req->done);
 			goto out;
 		case UI_END_FF_ERASE:
 			}
 			req->retval = ff_erase.retval;
-			uinput_request_done(udev, req);
+			complete(&req->done);
 			goto out;
 	}

drivers/input/mouse/elan_i2c_i2c.c+1−1

@@ -598,7 +598,7 @@ static int elan_i2c_write_fw_block(struct i2c_client *client, · 597 unmodified lines
598	}	598	}
599		599
600	/* Wait for F/W to update one page ROM data. */	600	/* Wait for F/W to update one page ROM data. */
601	msleep(20);	601	msleep(35);
602		602
603	error = elan_i2c_read_cmd(client, ETP_I2C_IAP_CTRL_CMD, val);	603	error = elan_i2c_read_cmd(client, ETP_I2C_IAP_CTRL_CMD, val);
604	if (error) {	604	if (error) {

drivers/iommu/Kconfig+3−2

 config IPMMU_VMSA
 	bool "Renesas VMSA-compatible IPMMU"
 	depends on ARM || IOMMU_DMA
-	depends on ARCH_RENESAS || COMPILE_TEST
+	depends on ARCH_RENESAS || (COMPILE_TEST && !GENERIC_ATOMIC64)
 	select IOMMU_API
 	select IOMMU_IO_PGTABLE_LPAE
 	select ARM_DMA_USE_IOMMU
 config QCOM_IOMMU
 	# Note: iommu drivers cannot (yet?) be built as modules
 	bool "Qualcomm IOMMU Support"
-	depends on ARCH_QCOM || COMPILE_TEST
+	depends on ARCH_QCOM || (COMPILE_TEST && !GENERIC_ATOMIC64)
+	depends on HAS_DMA
 	select IOMMU_API
 	select IOMMU_IO_PGTABLE_LPAE
 	select ARM_DMA_USE_IOMMU

drivers/iommu/amd_iommu_init.c+4−4

@@ -874,7 +874,7 @@ static bool copy_device_table(void) · 873 unmodified lines
874	hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);	874	hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);
875	entry = (((u64) hi) << 32) + lo;	875	entry = (((u64) hi) << 32) + lo;
876	if (last_entry && last_entry != entry) {	876	if (last_entry && last_entry != entry) {
877	pr_err("IOMMU:%d should use the same dev table as others!/n",	877	pr_err("IOMMU:%d should use the same dev table as others!\n",
878	iommu->index);	878	iommu->index);
879	return false;	879	return false;
880	}	880	}
@@ -882,7 +882,7 @@ static bool copy_device_table(void) · 1 unmodified line
882		882
883	old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12;	883	old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12;
884	if (old_devtb_size != dev_table_size) {	884	if (old_devtb_size != dev_table_size) {
885	pr_err("The device table size of IOMMU:%d is not expected!/n",	885	pr_err("The device table size of IOMMU:%d is not expected!\n",
886	iommu->index);	886	iommu->index);
887	return false;	887	return false;
888	}	888	}
@@ -890,7 +890,7 @@ static bool copy_device_table(void) · 1 unmodified line
890		890
891	old_devtb_phys = entry & PAGE_MASK;	891	old_devtb_phys = entry & PAGE_MASK;
892	if (old_devtb_phys >= 0x100000000ULL) {	892	if (old_devtb_phys >= 0x100000000ULL) {
893	pr_err("The address of old device table is above 4G, not trustworthy!/n");	893	pr_err("The address of old device table is above 4G, not trustworthy!\n");
894	return false;	894	return false;
895	}	895	}
896	old_devtb = memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB);	896	old_devtb = memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB);
@@ -901,7 +901,7 @@ static bool copy_device_table(void) · 4 unmodified lines
901	old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag,	901	old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag,
902	get_order(dev_table_size));	902	get_order(dev_table_size));
903	if (old_dev_tbl_cpy == NULL) {	903	if (old_dev_tbl_cpy == NULL) {
904	pr_err("Failed to allocate memory for copying old device table!/n");	904	pr_err("Failed to allocate memory for copying old device table!\n");
905	return false;	905	return false;
906	}	906	}
907		907

drivers/iommu/dmar.c+1−1

@@ -497,7 +497,7 @@ static int dmar_parse_one_rhsa(struct acpi_dmar_header header, void arg) · 496 unmodified lines
497	#define dmar_parse_one_rhsa dmar_res_noop	497	#define dmar_parse_one_rhsa dmar_res_noop
498	#endif	498	#endif
499		499
500	static void __init	500	static void
501	dmar_table_print_dmar_entry(struct acpi_dmar_header *header)	501	dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
502	{	502	{
503	struct acpi_dmar_hardware_unit *drhd;	503	struct acpi_dmar_hardware_unit *drhd;

drivers/iommu/io-pgtable-arm-v7s.c+1−1

@@ -245,7 +245,7 @@ static void __arm_v7s_free_table(void *table, int lvl, · 244 unmodified lines
245	static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries,	245	static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries,
246	struct io_pgtable_cfg *cfg)	246	struct io_pgtable_cfg *cfg)
247	{	247	{
248	if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA))	248	if (cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA)
249	return;	249	return;
250		250
251	dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep),	251	dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep),

drivers/iommu/mtk_iommu.c+2−1

@@ -371,7 +371,8 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, · 370 unmodified lines
371	int ret;	371	int ret;
372		372
373	spin_lock_irqsave(&dom->pgtlock, flags);	373	spin_lock_irqsave(&dom->pgtlock, flags);
374	ret = dom->iop->map(dom->iop, iova, paddr, size, prot);	374	ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
		375	size, prot);
375	spin_unlock_irqrestore(&dom->pgtlock, flags);	376	spin_unlock_irqrestore(&dom->pgtlock, flags);
376		377
377	return ret;	378	return ret;

drivers/iommu/of_iommu.c+1−4

@@ -157,10 +157,7 @@ static int of_pci_iommu_init(struct pci_dev pdev, u16 alias, void data) · 156 unmodified lines
157		157
158	err = of_iommu_xlate(info->dev, &iommu_spec);	158	err = of_iommu_xlate(info->dev, &iommu_spec);
159	of_node_put(iommu_spec.np);	159	of_node_put(iommu_spec.np);
160	if (err)	160	return err;
161	return err;
162
163	return info->np == pdev->bus->dev.of_node;
164	}	161	}
165		162
166	const struct iommu_ops of_iommu_configure(struct device dev,	163	const struct iommu_ops of_iommu_configure(struct device dev,

drivers/irqchip/irq-gic-v3.c+4−4

@@ -1042,7 +1042,7 @@ static int get_cpu_number(struct device_node *dn) · 1041 unmodified lines
1042	{	1042	{
1043	const __be32 *cell;	1043	const __be32 *cell;
1044	u64 hwid;	1044	u64 hwid;
1045	int i;	1045	int cpu;
1046		1046
1047	cell = of_get_property(dn, "reg", NULL);	1047	cell = of_get_property(dn, "reg", NULL);
1048	if (!cell)	1048	if (!cell)
@@ -1056,9 +1056,9 @@ static int get_cpu_number(struct device_node *dn) · 7 unmodified lines
1056	if (hwid & ~MPIDR_HWID_BITMASK)	1056	if (hwid & ~MPIDR_HWID_BITMASK)
1057	return -1;	1057	return -1;
1058		1058
1059	for (i = 0; i < num_possible_cpus(); i++)	1059	for_each_possible_cpu(cpu)
1060	if (cpu_logical_map(i) == hwid)	1060	if (cpu_logical_map(cpu) == hwid)
1061	return i;	1061	return cpu;
1062		1062
1063	return -1;	1063	return -1;
1064	}	1064	}

drivers/irqchip/irq-gic-v4.c+9−3

 {
 	struct its_cmd_info info = {
 		.cmd_type = MAP_VLPI,
-		.map      = map,
+		{
+			.map      = map,
+		},
 	};
 	/*
 {
 	struct its_cmd_info info = {
 		.cmd_type = GET_VLPI,
-		.map      = map,
+		{
+			.map      = map,
+		},
 	};
 	return irq_set_vcpu_affinity(irq, &info);
 {
 	struct its_cmd_info info = {
 		.cmd_type = inv ? PROP_UPDATE_AND_INV_VLPI : PROP_UPDATE_VLPI,
-		.config   = config,
+		{
+			.config   = config,
+		},
 	};
 	return irq_set_vcpu_affinity(irq, &info);

drivers/irqchip/irq-mips-gic.c+11−8

 {
 	unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
-	write_gic_rmask(BIT(intr));
+	write_gic_rmask(intr);
 	gic_clear_pcpu_masks(intr);
 }
 static void gic_unmask_irq(struct irq_data *d)
 {
-	struct cpumask *affinity = irq_data_get_affinity_mask(d);
 	unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
 	unsigned int cpu;
-	write_gic_smask(BIT(intr));
+	write_gic_smask(intr);
 	gic_clear_pcpu_masks(intr);
-	cpu = cpumask_first_and(affinity, cpu_online_mask);
+	cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
 	set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
 }
 				     irq_hw_number_t hw, unsigned int cpu)
 {
 	int intr = GIC_HWIRQ_TO_SHARED(hw);
+	struct irq_data *data;
 	unsigned long flags;
+	data = irq_get_irq_data(virq);
 	spin_lock_irqsave(&gic_lock, flags);
 	write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
 	write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
 	gic_clear_pcpu_masks(intr);
 	set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
+	irq_data_update_effective_affinity(data, cpumask_of(cpu));
 	spin_unlock_irqrestore(&gic_lock, flags);
 	return 0;
 	/* Find the first available CPU vector. */
 	i = 0;
-	reserved = (C_SW0 | C_SW1) >> __fls(C_SW0);
+	reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
 	while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
 					   i++, &cpu_vec))
 		reserved |= BIT(cpu_vec);
 	gicconfig = read_gic_config();
 	gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS;
-	gic_shared_intrs >>= __fls(GIC_CONFIG_NUMINTERRUPTS);
+	gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS);
 	gic_shared_intrs = (gic_shared_intrs + 1) * 8;
 	gic_vpes = gicconfig & GIC_CONFIG_PVPS;
-	gic_vpes >>= __fls(GIC_CONFIG_PVPS);
+	gic_vpes >>= __ffs(GIC_CONFIG_PVPS);
 	gic_vpes = gic_vpes + 1;
 	if (cpu_has_veic) {
 	for (i = 0; i < gic_shared_intrs; i++) {
 		change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
 		change_gic_trig(i, GIC_TRIG_LEVEL);
-		write_gic_rmask(BIT(i));
+		write_gic_rmask(i);
 	}
 	for (i = 0; i < gic_vpes; i++) {

drivers/isdn/i4l/isdn_ppp.c+25−12

@@ -825,7 +825,6 @@ isdn_ppp_write(int min, struct file file, const char __user buf, int count) · 824 unmodified lines
825	isdn_net_local *lp;	825	isdn_net_local *lp;
826	struct ippp_struct *is;	826	struct ippp_struct *is;
827	int proto;	827	int proto;
828	unsigned char protobuf[4];
829		828
830	is = file->private_data;	829	is = file->private_data;
831		830
@@ -839,24 +838,28 @@ isdn_ppp_write(int min, struct file file, const char __user buf, int count) · 7 unmodified lines
839	if (!lp)	838	if (!lp)
840	printk(KERN_DEBUG "isdn_ppp_write: lp == NULL\n");	839	printk(KERN_DEBUG "isdn_ppp_write: lp == NULL\n");
841	else {	840	else {
842	/*	841	if (lp->isdn_device < 0 \|\| lp->isdn_channel < 0) {
843	* Don't reset huptimer for	842	unsigned char protobuf[4];
844	* LCP packets. (Echo requests).	843	/*
845	*/	844	* Don't reset huptimer for
846	if (copy_from_user(protobuf, buf, 4))	845	* LCP packets. (Echo requests).
847	return -EFAULT;	846	*/
848	proto = PPP_PROTOCOL(protobuf);	847	if (copy_from_user(protobuf, buf, 4))
849	if (proto != PPP_LCP)	848	return -EFAULT;
850	lp->huptimer = 0;	849
		850	proto = PPP_PROTOCOL(protobuf);
		851	if (proto != PPP_LCP)
		852	lp->huptimer = 0;
851		853
852	if (lp->isdn_device < 0 \|\| lp->isdn_channel < 0)
853	return 0;	854	return 0;
		855	}
854		856
855	if ((dev->drv[lp->isdn_device]->flags & DRV_FLAG_RUNNING) &&	857	if ((dev->drv[lp->isdn_device]->flags & DRV_FLAG_RUNNING) &&
856	lp->dialstate == 0 &&	858	lp->dialstate == 0 &&
857	(lp->flags & ISDN_NET_CONNECTED)) {	859	(lp->flags & ISDN_NET_CONNECTED)) {
858	unsigned short hl;	860	unsigned short hl;
859	struct sk_buff *skb;	861	struct sk_buff *skb;
		862	unsigned char *cpy_buf;
860	/*	863	/*
861	* we need to reserve enough space in front of	864	* we need to reserve enough space in front of
862	* sk_buff. old call to dev_alloc_skb only reserved	865	* sk_buff. old call to dev_alloc_skb only reserved
@@ -869,11 +872,21 @@ isdn_ppp_write(int min, struct file file, const char __user buf, int count) · 6 unmodified lines
869	return count;	872	return count;
870	}	873	}
871	skb_reserve(skb, hl);	874	skb_reserve(skb, hl);
872	if (copy_from_user(skb_put(skb, count), buf, count))	875	cpy_buf = skb_put(skb, count);
		876	if (copy_from_user(cpy_buf, buf, count))
873	{	877	{
874	kfree_skb(skb);	878	kfree_skb(skb);
875	return -EFAULT;	879	return -EFAULT;
876	}	880	}
		881
		882	/*
		883	* Don't reset huptimer for
		884	* LCP packets. (Echo requests).
		885	*/
		886	proto = PPP_PROTOCOL(cpy_buf);
		887	if (proto != PPP_LCP)
		888	lp->huptimer = 0;
		889
877	if (is->debug & 0x40) {	890	if (is->debug & 0x40) {
878	printk(KERN_DEBUG "ppp xmit: len %d\n", (int) skb->len);	891	printk(KERN_DEBUG "ppp xmit: len %d\n", (int) skb->len);
879	isdn_ppp_frame_log("xmit", skb->data, skb->len, 32, is->unit, lp->ppp_slot);	892	isdn_ppp_frame_log("xmit", skb->data, skb->len, 32, is->unit, lp->ppp_slot);

drivers/leds/leds-as3645a.c+26−3

 #define AS_PEAK_mA_TO_REG(a) \
 	((min_t(u32, AS_PEAK_mA_MAX, a) - 1250) / 250)
+/* LED numbers for Devicetree */
+#define AS_LED_FLASH				0
+#define AS_LED_INDICATOR			1
 enum as_mode {
 	AS_MODE_EXT_TORCH = 0 << AS_CONTROL_MODE_SETTING_SHIFT,
 	AS_MODE_INDICATOR = 1 << AS_CONTROL_MODE_SETTING_SHIFT,
 			      struct device_node *node)
 {
 	struct as3645a_config *cfg = &flash->cfg;
+	struct device_node *child;
 	const char *name;
 	int rval;
-	flash->flash_node = of_get_child_by_name(node, "flash");
+	for_each_child_of_node(node, child) {
+		u32 id = 0;
+		of_property_read_u32(child, "reg", &id);
+		switch (id) {
+		case AS_LED_FLASH:
+			flash->flash_node = of_node_get(child);
+			break;
+		case AS_LED_INDICATOR:
+			flash->indicator_node = of_node_get(child);
+			break;
+		default:
+			dev_warn(&flash->client->dev,
+				 "unknown LED %u encountered, ignoring\n", id);
+			break;
+		}
+	}
 	if (!flash->flash_node) {
 		dev_err(&flash->client->dev, "can't find flash node\n");
 		return -ENODEV;
 	of_property_read_u32(flash->flash_node, "voltage-reference",
 			     &cfg->voltage_reference);
-	of_property_read_u32(flash->flash_node, "peak-current-limit",
+	of_property_read_u32(flash->flash_node, "ams,input-max-microamp",
 			     &cfg->peak);
 	cfg->peak = AS_PEAK_mA_TO_REG(cfg->peak);
-	flash->indicator_node = of_get_child_by_name(node, "indicator");
 	if (!flash->indicator_node) {
 		dev_warn(&flash->client->dev,
 			 "can't find indicator node\n");
 	as3645a_set_control(flash, AS_MODE_EXT_TORCH, false);
 	v4l2_flash_release(flash->vf);
+	v4l2_flash_release(flash->vfind);
 	led_classdev_flash_unregister(&flash->fled);
 	led_classdev_unregister(&flash->iled_cdev);

drivers/md/bcache/closure.c+2−2

@@ -64,7 +64,7 @@ EXPORT_SYMBOL(closure_put); · 63 unmodified lines
64	void __closure_wake_up(struct closure_waitlist *wait_list)	64	void __closure_wake_up(struct closure_waitlist *wait_list)
65	{	65	{
66	struct llist_node *list;	66	struct llist_node *list;
67	struct closure *cl;	67	struct closure cl, t;
68	struct llist_node *reverse = NULL;	68	struct llist_node *reverse = NULL;
69		69
70	list = llist_del_all(&wait_list->list);	70	list = llist_del_all(&wait_list->list);
@@ -73,7 +73,7 @@ void __closure_wake_up(struct closure_waitlist *wait_list) · 2 unmodified lines
73	reverse = llist_reverse_order(list);	73	reverse = llist_reverse_order(list);
74		74
75	/* Then do the wakeups */	75	/* Then do the wakeups */
76	llist_for_each_entry(cl, reverse, list) {	76	llist_for_each_entry_safe(cl, t, reverse, list) {
77	closure_set_waiting(cl, 0);	77	closure_set_waiting(cl, 0);
78	closure_sub(cl, CLOSURE_WAITING + 1);	78	closure_sub(cl, CLOSURE_WAITING + 1);
79	}	79	}

drivers/md/dm-core.h+1−0

@@ -149,5 +149,6 @@ static inline bool dm_message_test_buffer_overflow(char *result, unsigned maxlen · 148 unmodified lines
149		149
150	extern atomic_t dm_global_event_nr;	150	extern atomic_t dm_global_event_nr;
151	extern wait_queue_head_t dm_global_eventq;	151	extern wait_queue_head_t dm_global_eventq;
		152	void dm_issue_global_event(void);
152		153
153	#endif	154	#endif

drivers/md/dm-crypt.c+5−0

 		kfree(cipher_api);
 		return ret;
 	}
+	kfree(cipher_api);
 	return 0;
 bad_mem:
 				ti->error = "Invalid feature value for sector_size";
 				return -EINVAL;
 			}
+			if (ti->len & ((cc->sector_size >> SECTOR_SHIFT) - 1)) {
+				ti->error = "Device size is not multiple of sector_size feature";
+				return -EINVAL;
+			}
 			cc->sector_shift = __ffs(cc->sector_size) - SECTOR_SHIFT;
 		} else if (!strcasecmp(opt_string, "iv_large_sectors"))
 			set_bit(CRYPT_IV_LARGE_SECTORS, &cc->cipher_flags);

drivers/md/dm-ioctl.c+24−13

  * Round up the ptr to an 8-byte boundary.
  */
 #define ALIGN_MASK 7
+static inline size_t align_val(size_t val)
+{
+	return (val + ALIGN_MASK) & ~ALIGN_MASK;
+}
 static inline void *align_ptr(void *ptr)
 {
-	return (void *) (((size_t) (ptr + ALIGN_MASK)) & ~ALIGN_MASK);
+	return (void *)align_val((size_t)ptr);
 }
 /*
 	struct hash_cell *hc;
 	size_t len, needed = 0;
 	struct gendisk *disk;
-	struct dm_name_list *nl, *old_nl = NULL;
+	struct dm_name_list *orig_nl, *nl, *old_nl = NULL;
 	uint32_t *event_nr;
 	down_write(&_hash_lock);
 	 */
 	for (i = 0; i < NUM_BUCKETS; i++) {
 		list_for_each_entry (hc, _name_buckets + i, name_list) {
-			needed += sizeof(struct dm_name_list);
+			needed += align_val(offsetof(struct dm_name_list, name) + strlen(hc->name) + 1);
-			needed += strlen(hc->name) + 1;
+			needed += align_val(sizeof(uint32_t));
-			needed += ALIGN_MASK;
-			needed += (sizeof(uint32_t) + ALIGN_MASK) & ~ALIGN_MASK;
 		}
 	}
 	/*
 	 * Grab our output buffer.
 	 */
-	nl = get_result_buffer(param, param_size, &len);
+	nl = orig_nl = get_result_buffer(param, param_size, &len);
 	if (len < needed) {
 		param->flags |= DM_BUFFER_FULL_FLAG;
 		goto out;
 			strcpy(nl->name, hc->name);
 			old_nl = nl;
-			event_nr = align_ptr(((void *) (nl + 1)) + strlen(hc->name) + 1);
+			event_nr = align_ptr(nl->name + strlen(hc->name) + 1);
 			*event_nr = dm_get_event_nr(hc->md);
 			nl = align_ptr(event_nr + 1);
 		}
 	}
+	/*
+	 * If mismatch happens, security may be compromised due to buffer
+	 * overflow, so it's better to crash.
+	 */
+	BUG_ON((char *)nl - (char *)orig_nl != needed);
  out:
 	up_write(&_hash_lock);
  * which has a variable size, is not used by the function processing
  * the ioctl.
  */
-#define IOCTL_FLAGS_NO_PARAMS	1
+#define IOCTL_FLAGS_NO_PARAMS		1
+#define IOCTL_FLAGS_ISSUE_GLOBAL_EVENT	2
 /*-----------------------------------------------------------------
  * Implementation of open/close/ioctl on the special char
 		ioctl_fn fn;
 	} _ioctls[] = {
 		{DM_VERSION_CMD, 0, NULL}, /* version is dealt with elsewhere */
-		{DM_REMOVE_ALL_CMD, IOCTL_FLAGS_NO_PARAMS, remove_all},
+		{DM_REMOVE_ALL_CMD, IOCTL_FLAGS_NO_PARAMS | IOCTL_FLAGS_ISSUE_GLOBAL_EVENT, remove_all},
 		{DM_LIST_DEVICES_CMD, 0, list_devices},
-		{DM_DEV_CREATE_CMD, IOCTL_FLAGS_NO_PARAMS, dev_create},
+		{DM_DEV_CREATE_CMD, IOCTL_FLAGS_NO_PARAMS | IOCTL_FLAGS_ISSUE_GLOBAL_EVENT, dev_create},
-		{DM_DEV_REMOVE_CMD, IOCTL_FLAGS_NO_PARAMS, dev_remove},
+		{DM_DEV_REMOVE_CMD, IOCTL_FLAGS_NO_PARAMS | IOCTL_FLAGS_ISSUE_GLOBAL_EVENT, dev_remove},
-		{DM_DEV_RENAME_CMD, 0, dev_rename},
+		{DM_DEV_RENAME_CMD, IOCTL_FLAGS_ISSUE_GLOBAL_EVENT, dev_rename},
 		{DM_DEV_SUSPEND_CMD, IOCTL_FLAGS_NO_PARAMS, dev_suspend},
 		{DM_DEV_STATUS_CMD, IOCTL_FLAGS_NO_PARAMS, dev_status},
 		{DM_DEV_WAIT_CMD, 0, dev_wait},
 	    unlikely(ioctl_flags & IOCTL_FLAGS_NO_PARAMS))
 		DMERR("ioctl %d tried to output some data but has IOCTL_FLAGS_NO_PARAMS set", cmd);
+	if (!r && ioctl_flags & IOCTL_FLAGS_ISSUE_GLOBAL_EVENT)
+		dm_issue_global_event();
 	/*
 	 * Copy the results back to userland.
 	 */

drivers/md/dm-raid.c+7−6

 	if (unlikely(bio_end_sector(bio) > mddev->array_sectors))
 		return DM_MAPIO_REQUEUE;
-	mddev->pers->make_request(mddev, bio);
+	md_handle_request(mddev, bio);
 	return DM_MAPIO_SUBMITTED;
 }
 static sector_t rs_get_progress(struct raid_set *rs,
 				sector_t resync_max_sectors, bool *array_in_sync)
 {
-	sector_t r, recovery_cp, curr_resync_completed;
+	sector_t r, curr_resync_completed;
 	struct mddev *mddev = &rs->md;
 	curr_resync_completed = mddev->curr_resync_completed ?: mddev->recovery_cp;
-	recovery_cp = mddev->recovery_cp;
 	*array_in_sync = false;
 	if (rs_is_raid0(rs)) {
 		} else if (test_bit(MD_RECOVERY_RUNNING, &mddev->recovery))
 			r = curr_resync_completed;
 		else
-			r = recovery_cp;
+			r = mddev->recovery_cp;
-		if (r == MaxSector) {
+		if ((r == MaxSector) ||
+		    (test_bit(MD_RECOVERY_DONE, &mddev->recovery) &&
+		     (mddev->curr_resync_completed == resync_max_sectors))) {
 			/*
 			 * Sync complete.
 			 */
 static struct target_type raid_target = {
 	.name = "raid",
-	.version = {1, 12, 1},
+	.version = {1, 13, 0},
 	.module = THIS_MODULE,
 	.ctr = raid_ctr,
 	.dtr = raid_dtr,

drivers/md/dm.c+8−2

 atomic_t dm_global_event_nr = ATOMIC_INIT(0);
 DECLARE_WAIT_QUEUE_HEAD(dm_global_eventq);
+void dm_issue_global_event(void)
+{
+	atomic_inc(&dm_global_event_nr);
+	wake_up(&dm_global_eventq);
+}
 /*
  * One of these is allocated per bio.
  */
 	dm_send_uevents(&uevents, &disk_to_dev(md->disk)->kobj);
 	atomic_inc(&md->event_nr);
-	atomic_inc(&dm_global_event_nr);
 	wake_up(&md->eventq);
-	wake_up(&dm_global_eventq);
+	dm_issue_global_event();
 }
 /*
 	}
 	map = __bind(md, table, &limits);
+	dm_issue_global_event();
 out:
 	mutex_unlock(&md->suspend_lock);

drivers/md/md.c+43−29

@@ -266,6 +266,37 @@ static DEFINE_SPINLOCK(all_mddevs_lock); · 265 unmodified lines
266	* call has finished, the bio has been linked into some internal structure	266	* call has finished, the bio has been linked into some internal structure
267	* and so is visible to ->quiesce(), so we don't need the refcount any more.	267	* and so is visible to ->quiesce(), so we don't need the refcount any more.
268	*/	268	*/
		269	void md_handle_request(struct mddev mddev, struct bio bio)
		270	{
		271	check_suspended:
		272	rcu_read_lock();
		273	if (mddev->suspended) {
		274	DEFINE_WAIT(__wait);
		275	for (;;) {
		276	prepare_to_wait(&mddev->sb_wait, &__wait,
		277	TASK_UNINTERRUPTIBLE);
		278	if (!mddev->suspended)
		279	break;
		280	rcu_read_unlock();
		281	schedule();
		282	rcu_read_lock();
		283	}
		284	finish_wait(&mddev->sb_wait, &__wait);
		285	}
		286	atomic_inc(&mddev->active_io);
		287	rcu_read_unlock();
		288
		289	if (!mddev->pers->make_request(mddev, bio)) {
		290	atomic_dec(&mddev->active_io);
		291	wake_up(&mddev->sb_wait);
		292	goto check_suspended;
		293	}
		294
		295	if (atomic_dec_and_test(&mddev->active_io) && mddev->suspended)
		296	wake_up(&mddev->sb_wait);
		297	}
		298	EXPORT_SYMBOL(md_handle_request);
		299
269	static blk_qc_t md_make_request(struct request_queue q, struct bio bio)	300	static blk_qc_t md_make_request(struct request_queue q, struct bio bio)
270	{	301	{
271	const int rw = bio_data_dir(bio);	302	const int rw = bio_data_dir(bio);
@@ -285,23 +316,6 @@ static blk_qc_t md_make_request(struct request_queue q, struct bio bio) · 13 unmodified lines
285	bio_endio(bio);	316	bio_endio(bio);
286	return BLK_QC_T_NONE;	317	return BLK_QC_T_NONE;
287	}	318	}
288	check_suspended:
289	rcu_read_lock();
290	if (mddev->suspended) {
291	DEFINE_WAIT(__wait);
292	for (;;) {
293	prepare_to_wait(&mddev->sb_wait, &__wait,
294	TASK_UNINTERRUPTIBLE);
295	if (!mddev->suspended)
296	break;
297	rcu_read_unlock();
298	schedule();
299	rcu_read_lock();
300	}
301	finish_wait(&mddev->sb_wait, &__wait);
302	}
303	atomic_inc(&mddev->active_io);
304	rcu_read_unlock();
305		319
306	/*	320	/*
307	* save the sectors now since our bio can	321	* save the sectors now since our bio can
@@ -310,20 +324,14 @@ check_suspended: · 2 unmodified lines
310	sectors = bio_sectors(bio);	324	sectors = bio_sectors(bio);
311	/* bio could be mergeable after passing to underlayer */	325	/* bio could be mergeable after passing to underlayer */
312	bio->bi_opf &= ~REQ_NOMERGE;	326	bio->bi_opf &= ~REQ_NOMERGE;
313	if (!mddev->pers->make_request(mddev, bio)) {	327
314	atomic_dec(&mddev->active_io);	328	md_handle_request(mddev, bio);
315	wake_up(&mddev->sb_wait);
316	goto check_suspended;
317	}
318		329
319	cpu = part_stat_lock();	330	cpu = part_stat_lock();
320	part_stat_inc(cpu, &mddev->gendisk->part0, ios[rw]);	331	part_stat_inc(cpu, &mddev->gendisk->part0, ios[rw]);
321	part_stat_add(cpu, &mddev->gendisk->part0, sectors[rw], sectors);	332	part_stat_add(cpu, &mddev->gendisk->part0, sectors[rw], sectors);
322	part_stat_unlock();	333	part_stat_unlock();
323		334
324	if (atomic_dec_and_test(&mddev->active_io) && mddev->suspended)
325	wake_up(&mddev->sb_wait);
326
327	return BLK_QC_T_NONE;	335	return BLK_QC_T_NONE;
328	}	336	}
329		337
@@ -439,16 +447,22 @@ static void md_submit_flush_data(struct work_struct *ws) · 109 unmodified lines
439	struct mddev *mddev = container_of(ws, struct mddev, flush_work);	447	struct mddev *mddev = container_of(ws, struct mddev, flush_work);
440	struct bio *bio = mddev->flush_bio;	448	struct bio *bio = mddev->flush_bio;
441		449
		450	/*
		451	* must reset flush_bio before calling into md_handle_request to avoid a
		452	* deadlock, because other bios passed md_handle_request suspend check
		453	* could wait for this and below md_handle_request could wait for those
		454	* bios because of suspend check
		455	*/
		456	mddev->flush_bio = NULL;
		457	wake_up(&mddev->sb_wait);
		458
442	if (bio->bi_iter.bi_size == 0)	459	if (bio->bi_iter.bi_size == 0)
443	/* an empty barrier - all done */	460	/* an empty barrier - all done */
444	bio_endio(bio);	461	bio_endio(bio);
445	else {	462	else {
446	bio->bi_opf &= ~REQ_PREFLUSH;	463	bio->bi_opf &= ~REQ_PREFLUSH;
447	mddev->pers->make_request(mddev, bio);	464	md_handle_request(mddev, bio);
448	}	465	}
449
450	mddev->flush_bio = NULL;
451	wake_up(&mddev->sb_wait);
452	}	466	}
453		467
454	void md_flush_request(struct mddev mddev, struct bio bio)	468	void md_flush_request(struct mddev mddev, struct bio bio)

drivers/md/md.h+1−0

@@ -692,6 +692,7 @@ extern void md_stop_writes(struct mddev *mddev); · 691 unmodified lines
692	extern int md_rdev_init(struct md_rdev *rdev);	692	extern int md_rdev_init(struct md_rdev *rdev);
693	extern void md_rdev_clear(struct md_rdev *rdev);	693	extern void md_rdev_clear(struct md_rdev *rdev);
694		694
		695	extern void md_handle_request(struct mddev mddev, struct bio bio);
695	extern void mddev_suspend(struct mddev *mddev);	696	extern void mddev_suspend(struct mddev *mddev);
696	extern void mddev_resume(struct mddev *mddev);	697	extern void mddev_resume(struct mddev *mddev);
697	extern struct bio *bio_alloc_mddev(gfp_t gfp_mask, int nr_iovecs,	698	extern struct bio *bio_alloc_mddev(gfp_t gfp_mask, int nr_iovecs,

drivers/md/raid5.c+15−5

 			spin_unlock(&head->batch_head->batch_lock);
 			goto unlock_out;
 		}
+		/*
+		 * We must assign batch_head of this stripe within the
+		 * batch_lock, otherwise clear_batch_ready of batch head
+		 * stripe could clear BATCH_READY bit of this stripe and
+		 * this stripe->batch_head doesn't get assigned, which
+		 * could confuse clear_batch_ready for this stripe
+		 */
+		sh->batch_head = head->batch_head;
 		/*
 		 * at this point, head's BATCH_READY could be cleared, but we
 		 */
 		list_add(&sh->batch_list, &head->batch_list);
 		spin_unlock(&head->batch_head->batch_lock);
-		sh->batch_head = head->batch_head;
 	} else {
 		head->batch_head = head;
 		sh->batch_head = head->batch_head;
 		set_mask_bits(&sh->state, ~(STRIPE_EXPAND_SYNC_FLAGS |
 					    (1 << STRIPE_PREREAD_ACTIVE) |
-					    (1 << STRIPE_DEGRADED)),
+					    (1 << STRIPE_DEGRADED) |
+					    (1 << STRIPE_ON_UNPLUG_LIST)),
 			      head_sh->state & (1 << STRIPE_INSYNC));
 		sh->check_state = head_sh->check_state;
 raid5_store_group_thread_cnt(struct mddev *mddev, const char *page, size_t len)
 {
 	struct r5conf *conf;
-	unsigned long new;
+	unsigned int new;
 	int err;
 	struct r5worker_group *new_groups, *old_groups;
 	int group_cnt, worker_cnt_per_group;
 	if (len >= PAGE_SIZE)
 		return -EINVAL;
-	if (kstrtoul(page, 10, &new))
+	if (kstrtouint(page, 10, &new))
+		return -EINVAL;
+	/* 8192 should be big enough */
+	if (new > 8192)
 		return -EINVAL;
 	err = mddev_lock(mddev);

drivers/media/rc/ir-sharp-decoder.c+1−1

@@ -245,5 +245,5 @@ module_init(ir_sharp_decode_init); · 244 unmodified lines
245	module_exit(ir_sharp_decode_exit);	245	module_exit(ir_sharp_decode_exit);
246		246
247	MODULE_LICENSE("GPL");	247	MODULE_LICENSE("GPL");
248	MODULE_AUTHOR("James Hogan <james.hogan@imgtec.com>");	248	MODULE_AUTHOR("James Hogan <jhogan@kernel.org>");
249	MODULE_DESCRIPTION("Sharp IR protocol decoder");	249	MODULE_DESCRIPTION("Sharp IR protocol decoder");

drivers/misc/cxl/cxllib.c+11−2

@@ -219,8 +219,17 @@ int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags) · 218 unmodified lines
219		219
220	down_read(&mm->mmap_sem);	220	down_read(&mm->mmap_sem);
221		221
222	for (dar = addr; dar < addr + size; dar += page_size) {	222	vma = find_vma(mm, addr);
223	if (!vma \|\| dar < vma->vm_start \|\| dar > vma->vm_end) {	223	if (!vma) {
		224	pr_err("Can't find vma for addr %016llx\n", addr);
		225	rc = -EFAULT;
		226	goto out;
		227	}
		228	/* get the size of the pages allocated */
		229	page_size = vma_kernel_pagesize(vma);
		230
		231	for (dar = (addr & ~(page_size - 1)); dar < (addr + size); dar += page_size) {
		232	if (dar < vma->vm_start \|\| dar >= vma->vm_end) {
224	vma = find_vma(mm, addr);	233	vma = find_vma(mm, addr);
225	if (!vma) {	234	if (!vma) {
226	pr_err("Can't find vma for addr %016llx\n", addr);	235	pr_err("Can't find vma for addr %016llx\n", addr);

drivers/mmc/core/block.c+0−3

 	}
 	mqrq->areq.mrq = &brq->mrq;
-	mmc_queue_bounce_pre(mqrq);
 }
 static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
 		brq = &mq_rq->brq;
 		old_req = mmc_queue_req_to_req(mq_rq);
 		type = rq_data_dir(old_req) == READ ? MMC_BLK_READ : MMC_BLK_WRITE;
-		mmc_queue_bounce_post(mq_rq);
 		switch (status) {
 		case MMC_BLK_SUCCESS:

drivers/mmc/core/mmc.c+19−17

 	return err;
 }
+static void mmc_select_driver_type(struct mmc_card *card)
+{
+	int card_drv_type, drive_strength, drv_type;
+	card_drv_type = card->ext_csd.raw_driver_strength |
+			mmc_driver_type_mask(0);
+	drive_strength = mmc_select_drive_strength(card,
+						   card->ext_csd.hs200_max_dtr,
+						   card_drv_type, &drv_type);
+	card->drive_strength = drive_strength;
+	if (drv_type)
+		mmc_set_driver_type(card->host, drv_type);
+}
 static int mmc_select_hs400es(struct mmc_card *card)
 {
 	struct mmc_host *host = card->host;
 		goto out_err;
 	}
+	mmc_select_driver_type(card);
 	/* Switch card to HS400 */
 	val = EXT_CSD_TIMING_HS400 |
 	      card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
 	return err;
 }
-static void mmc_select_driver_type(struct mmc_card *card)
-{
-	int card_drv_type, drive_strength, drv_type;
-	card_drv_type = card->ext_csd.raw_driver_strength |
-			mmc_driver_type_mask(0);
-	drive_strength = mmc_select_drive_strength(card,
-						   card->ext_csd.hs200_max_dtr,
-						   card_drv_type, &drv_type);
-	card->drive_strength = drive_strength;
-	if (drv_type)
-		mmc_set_driver_type(card->host, drv_type);
-}
 /*
  * For device supporting HS200 mode, the following sequence
  * should be done before executing the tuning process.

drivers/mmc/core/queue.c+9−111

@@ -23,8 +23,6 @@ · 22 unmodified lines
23	#include "core.h"	23	#include "core.h"
24	#include "card.h"	24	#include "card.h"
25		25
26	#define MMC_QUEUE_BOUNCESZ 65536
27
28	/*	26	/*
29	* Prepare a MMC request. This just filters out odd stuff.	27	* Prepare a MMC request. This just filters out odd stuff.
30	*/	28	*/
@@ -150,26 +148,6 @@ static void mmc_queue_setup_discard(struct request_queue *q, · 119 unmodified lines
150	queue_flag_set_unlocked(QUEUE_FLAG_SECERASE, q);	148	queue_flag_set_unlocked(QUEUE_FLAG_SECERASE, q);
151	}	149	}
152		150
153	static unsigned int mmc_queue_calc_bouncesz(struct mmc_host *host)
154	{
155	unsigned int bouncesz = MMC_QUEUE_BOUNCESZ;
156
157	if (host->max_segs != 1 \|\| (host->caps & MMC_CAP_NO_BOUNCE_BUFF))
158	return 0;
159
160	if (bouncesz > host->max_req_size)
161	bouncesz = host->max_req_size;
162	if (bouncesz > host->max_seg_size)
163	bouncesz = host->max_seg_size;
164	if (bouncesz > host->max_blk_count * 512)
165	bouncesz = host->max_blk_count * 512;
166
167	if (bouncesz <= 512)
168	return 0;
169
170	return bouncesz;
171	}
172
173	/**	151	/**
174	* mmc_init_request() - initialize the MMC-specific per-request data	152	* mmc_init_request() - initialize the MMC-specific per-request data
175	* @q: the request queue	153	* @q: the request queue
@@ -184,26 +162,9 @@ static int mmc_init_request(struct request_queue q, struct request req, · 8 unmodified lines
184	struct mmc_card *card = mq->card;	162	struct mmc_card *card = mq->card;
185	struct mmc_host *host = card->host;	163	struct mmc_host *host = card->host;
186		164
187	if (card->bouncesz) {	165	mq_rq->sg = mmc_alloc_sg(host->max_segs, gfp);
188	mq_rq->bounce_buf = kmalloc(card->bouncesz, gfp);	166	if (!mq_rq->sg)
189	if (!mq_rq->bounce_buf)	167	return -ENOMEM;
190	return -ENOMEM;
191	if (card->bouncesz > 512) {
192	mq_rq->sg = mmc_alloc_sg(1, gfp);
193	if (!mq_rq->sg)
194	return -ENOMEM;
195	mq_rq->bounce_sg = mmc_alloc_sg(card->bouncesz / 512,
196	gfp);
197	if (!mq_rq->bounce_sg)
198	return -ENOMEM;
199	}
200	} else {
201	mq_rq->bounce_buf = NULL;
202	mq_rq->bounce_sg = NULL;
203	mq_rq->sg = mmc_alloc_sg(host->max_segs, gfp);
204	if (!mq_rq->sg)
205	return -ENOMEM;
206	}
207		168
208	return 0;	169	return 0;
209	}	170	}
@@ -212,13 +173,6 @@ static void mmc_exit_request(struct request_queue q, struct request req) · 2 unmodified lines
212	{	173	{
213	struct mmc_queue_req *mq_rq = req_to_mmc_queue_req(req);	174	struct mmc_queue_req *mq_rq = req_to_mmc_queue_req(req);
214		175
215	/* It is OK to kfree(NULL) so this will be smooth */
216	kfree(mq_rq->bounce_sg);
217	mq_rq->bounce_sg = NULL;
218
219	kfree(mq_rq->bounce_buf);
220	mq_rq->bounce_buf = NULL;
221
222	kfree(mq_rq->sg);	176	kfree(mq_rq->sg);
223	mq_rq->sg = NULL;	177	mq_rq->sg = NULL;
224	}	178	}
@@ -265,18 +219,11 @@ int mmc_init_queue(struct mmc_queue mq, struct mmc_card card, · 40 unmodified lines
265	if (mmc_can_erase(card))	219	if (mmc_can_erase(card))
266	mmc_queue_setup_discard(mq->queue, card);	220	mmc_queue_setup_discard(mq->queue, card);
267		221
268	card->bouncesz = mmc_queue_calc_bouncesz(host);	222	blk_queue_bounce_limit(mq->queue, limit);
269	if (card->bouncesz) {	223	blk_queue_max_hw_sectors(mq->queue,
270	blk_queue_max_hw_sectors(mq->queue, card->bouncesz / 512);	224	min(host->max_blk_count, host->max_req_size / 512));
271	blk_queue_max_segments(mq->queue, card->bouncesz / 512);	225	blk_queue_max_segments(mq->queue, host->max_segs);
272	blk_queue_max_segment_size(mq->queue, card->bouncesz);	226	blk_queue_max_segment_size(mq->queue, host->max_seg_size);
273	} else {
274	blk_queue_bounce_limit(mq->queue, limit);
275	blk_queue_max_hw_sectors(mq->queue,
276	min(host->max_blk_count, host->max_req_size / 512));
277	blk_queue_max_segments(mq->queue, host->max_segs);
278	blk_queue_max_segment_size(mq->queue, host->max_seg_size);
279	}
280		227
281	sema_init(&mq->thread_sem, 1);	228	sema_init(&mq->thread_sem, 1);
282		229
@@ -365,56 +312,7 @@ void mmc_queue_resume(struct mmc_queue *mq) · 82 unmodified lines
365	*/	312	*/
366	unsigned int mmc_queue_map_sg(struct mmc_queue mq, struct mmc_queue_req mqrq)	313	unsigned int mmc_queue_map_sg(struct mmc_queue mq, struct mmc_queue_req mqrq)
367	{	314	{
368	unsigned int sg_len;
369	size_t buflen;
370	struct scatterlist *sg;
371	struct request *req = mmc_queue_req_to_req(mqrq);	315	struct request *req = mmc_queue_req_to_req(mqrq);
372	int i;
373
374	if (!mqrq->bounce_buf)
375	return blk_rq_map_sg(mq->queue, req, mqrq->sg);
376
377	sg_len = blk_rq_map_sg(mq->queue, req, mqrq->bounce_sg);
378
379	mqrq->bounce_sg_len = sg_len;
380
381	buflen = 0;
382	for_each_sg(mqrq->bounce_sg, sg, sg_len, i)
383	buflen += sg->length;
384
385	sg_init_one(mqrq->sg, mqrq->bounce_buf, buflen);
386
387	return 1;
388	}
389
390	/*
391	* If writing, bounce the data to the buffer before the request
392	* is sent to the host driver
393	*/
394	void mmc_queue_bounce_pre(struct mmc_queue_req *mqrq)
395	{
396	if (!mqrq->bounce_buf)
397	return;
398
399	if (rq_data_dir(mmc_queue_req_to_req(mqrq)) != WRITE)
400	return;
401
402	sg_copy_to_buffer(mqrq->bounce_sg, mqrq->bounce_sg_len,
403	mqrq->bounce_buf, mqrq->sg[0].length);
404	}
405
406	/*
407	* If reading, bounce the data from the buffer after the request
408	* has been handled by the host driver
409	*/
410	void mmc_queue_bounce_post(struct mmc_queue_req *mqrq)
411	{
412	if (!mqrq->bounce_buf)
413	return;
414
415	if (rq_data_dir(mmc_queue_req_to_req(mqrq)) != READ)
416	return;
417		316
418	sg_copy_from_buffer(mqrq->bounce_sg, mqrq->bounce_sg_len,	317	return blk_rq_map_sg(mq->queue, req, mqrq->sg);
419	mqrq->bounce_buf, mqrq->sg[0].length);
420	}	318	}

drivers/mmc/core/queue.h+0−6

 struct mmc_queue_req {
 	struct mmc_blk_request	brq;
 	struct scatterlist	*sg;
-	char			*bounce_buf;
-	struct scatterlist	*bounce_sg;
-	unsigned int		bounce_sg_len;
 	struct mmc_async_req	areq;
 	enum mmc_drv_op		drv_op;
 	int			drv_op_result;
 extern void mmc_cleanup_queue(struct mmc_queue *);
 extern void mmc_queue_suspend(struct mmc_queue *);
 extern void mmc_queue_resume(struct mmc_queue *);
 extern unsigned int mmc_queue_map_sg(struct mmc_queue *,
 				     struct mmc_queue_req *);
-extern void mmc_queue_bounce_pre(struct mmc_queue_req *);
-extern void mmc_queue_bounce_post(struct mmc_queue_req *);
 extern int mmc_access_rpmb(struct mmc_queue *);

drivers/mmc/host/Kconfig+1−1

@@ -5,7 +5,7 @@ · 4 unmodified lines
5	comment "MMC/SD/SDIO Host Controller Drivers"	5	comment "MMC/SD/SDIO Host Controller Drivers"
6		6
7	config MMC_DEBUG	7	config MMC_DEBUG
8	bool "MMC host drivers debugginG"	8	bool "MMC host drivers debugging"
9	depends on MMC != n	9	depends on MMC != n
10	help	10	help
11	This is an option for use by developers; most people should	11	This is an option for use by developers; most people should

drivers/mmc/host/cavium-thunderx.c+5−1

  *
  * Copyright (C) 2016 Cavium Inc.
  */
+#include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/interrupt.h>
 #include <linux/mmc/mmc.h>
 	for (i = 0; i < CAVIUM_MAX_MMC; i++) {
 		if (host->slot[i])
 			cvm_mmc_of_slot_remove(host->slot[i]);
-		if (host->slot_pdev[i])
+		if (host->slot_pdev[i]) {
+			get_device(&host->slot_pdev[i]->dev);
 			of_platform_device_destroy(&host->slot_pdev[i]->dev, NULL);
+			put_device(&host->slot_pdev[i]->dev);
+		}
 	}
 	clk_disable_unprepare(host->clk);
 	return ret;

drivers/mmc/host/cavium.c+1−1

@@ -1038,7 +1038,7 @@ int cvm_mmc_of_slot_probe(struct device dev, struct cvm_mmc_host host) · 1037 unmodified lines
1038	*/	1038	*/
1039	mmc->caps \|= MMC_CAP_MMC_HIGHSPEED \| MMC_CAP_SD_HIGHSPEED \|	1039	mmc->caps \|= MMC_CAP_MMC_HIGHSPEED \| MMC_CAP_SD_HIGHSPEED \|
1040	MMC_CAP_ERASE \| MMC_CAP_CMD23 \| MMC_CAP_POWER_OFF_CARD \|	1040	MMC_CAP_ERASE \| MMC_CAP_CMD23 \| MMC_CAP_POWER_OFF_CARD \|
1041	MMC_CAP_3_3V_DDR \| MMC_CAP_NO_BOUNCE_BUFF;	1041	MMC_CAP_3_3V_DDR;
1042		1042
1043	if (host->use_sg)	1043	if (host->use_sg)
1044	mmc->max_segs = 16;	1044	mmc->max_segs = 16;

drivers/mmc/host/meson-gx-mmc.c+22−4

 	div->shift = __ffs(CLK_DIV_MASK);
 	div->width = __builtin_popcountl(CLK_DIV_MASK);
 	div->hw.init = &init;
-	div->flags = (CLK_DIVIDER_ONE_BASED |
+	div->flags = CLK_DIVIDER_ONE_BASED;
-		      CLK_DIVIDER_ROUND_CLOSEST);
 	clk = devm_clk_register(host->dev, &div->hw);
 	if (WARN_ON(IS_ERR(clk)))
 static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 {
 	struct meson_host *host = mmc_priv(mmc);
+	int ret;
+	/*
+	 * If this is the initial tuning, try to get a sane Rx starting
+	 * phase before doing the actual tuning.
+	 */
+	if (!mmc->doing_retune) {
+		ret = meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
+		if (ret)
+			return ret;
+	}
+	ret = meson_mmc_clk_phase_tuning(mmc, opcode, host->tx_clk);
+	if (ret)
+		return ret;
 	return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
 }
 	case MMC_POWER_UP:
 		if (!IS_ERR(mmc->supply.vmmc))
 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
+		/* Reset phases */
+		clk_set_phase(host->rx_clk, 0);
+		clk_set_phase(host->tx_clk, 270);
 		break;
 	case MMC_POWER_ON:
 				host->vqmmc_enabled = true;
 		}
-		/* Reset rx phase */
-		clk_set_phase(host->rx_clk, 0);
 		break;
 	}

drivers/mmc/host/pxamci.c+1−5

 	pxamci_init_ocr(host);
-	/*
+	mmc->caps = 0;
-	 * This architecture used to disable bounce buffers through its
-	 * defconfig, now it is done at runtime as a host property.
-	 */
-	mmc->caps = MMC_CAP_NO_BOUNCE_BUFF;
 	host->cmdat = 0;
 	if (!cpu_is_pxa25x()) {
 		mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;

drivers/mmc/host/sdhci-pci-core.c+15−0

 enum {
 	INTEL_DSM_FNS		=  0,
+	INTEL_DSM_V18_SWITCH	=  3,
 	INTEL_DSM_DRV_STRENGTH	=  9,
 	INTEL_DSM_D3_RETUNE	= 10,
 };
 	sdhci_writel(host, val, INTEL_HS400_ES_REG);
 }
+static void sdhci_intel_voltage_switch(struct sdhci_host *host)
+{
+	struct sdhci_pci_slot *slot = sdhci_priv(host);
+	struct intel_host *intel_host = sdhci_pci_priv(slot);
+	struct device *dev = &slot->chip->pdev->dev;
+	u32 result = 0;
+	int err;
+	err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result);
+	pr_debug("%s: %s DSM error %d result %u\n",
+		 mmc_hostname(host->mmc), __func__, err, result);
+}
 static const struct sdhci_ops sdhci_intel_byt_ops = {
 	.set_clock		= sdhci_set_clock,
 	.set_power		= sdhci_intel_set_power,
 	.reset			= sdhci_reset,
 	.set_uhs_signaling	= sdhci_set_uhs_signaling,
 	.hw_reset		= sdhci_pci_hw_reset,
+	.voltage_switch		= sdhci_intel_voltage_switch,
 };
 static void byt_read_dsm(struct sdhci_pci_slot *slot)

drivers/mmc/host/sdhci-xenon.c+20−4

@@ -466,6 +466,7 @@ static int xenon_probe(struct platform_device *pdev) · 465 unmodified lines
466	{	466	{
467	struct sdhci_pltfm_host *pltfm_host;	467	struct sdhci_pltfm_host *pltfm_host;
468	struct sdhci_host *host;	468	struct sdhci_host *host;
		469	struct xenon_priv *priv;
469	int err;	470	int err;
470		471
471	host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,	472	host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
@@ -474,6 +475,7 @@ static int xenon_probe(struct platform_device *pdev) · 2 unmodified lines
474	return PTR_ERR(host);	475	return PTR_ERR(host);
475		476
476	pltfm_host = sdhci_priv(host);	477	pltfm_host = sdhci_priv(host);
		478	priv = sdhci_pltfm_priv(pltfm_host);
477		479
478	/*	480	/*
479	* Link Xenon specific mmc_host_ops function,	481	* Link Xenon specific mmc_host_ops function,
@@ -491,9 +493,20 @@ static int xenon_probe(struct platform_device *pdev) · 11 unmodified lines
491	if (err)	493	if (err)
492	goto free_pltfm;	494	goto free_pltfm;
493		495
		496	priv->axi_clk = devm_clk_get(&pdev->dev, "axi");
		497	if (IS_ERR(priv->axi_clk)) {
		498	err = PTR_ERR(priv->axi_clk);
		499	if (err == -EPROBE_DEFER)
		500	goto err_clk;
		501	} else {
		502	err = clk_prepare_enable(priv->axi_clk);
		503	if (err)
		504	goto err_clk;
		505	}
		506
494	err = mmc_of_parse(host->mmc);	507	err = mmc_of_parse(host->mmc);
495	if (err)	508	if (err)
496	goto err_clk;	509	goto err_clk_axi;
497		510
498	sdhci_get_of_property(pdev);	511	sdhci_get_of_property(pdev);
499		512
@@ -502,11 +515,11 @@ static int xenon_probe(struct platform_device *pdev) · 2 unmodified lines
502	/* Xenon specific dt parse */	515	/* Xenon specific dt parse */
503	err = xenon_probe_dt(pdev);	516	err = xenon_probe_dt(pdev);
504	if (err)	517	if (err)
505	goto err_clk;	518	goto err_clk_axi;
506		519
507	err = xenon_sdhc_prepare(host);	520	err = xenon_sdhc_prepare(host);
508	if (err)	521	if (err)
509	goto err_clk;	522	goto err_clk_axi;
510		523
511	pm_runtime_get_noresume(&pdev->dev);	524	pm_runtime_get_noresume(&pdev->dev);
512	pm_runtime_set_active(&pdev->dev);	525	pm_runtime_set_active(&pdev->dev);
@@ -527,6 +540,8 @@ remove_sdhc: · 14 unmodified lines
527	pm_runtime_disable(&pdev->dev);	540	pm_runtime_disable(&pdev->dev);
528	pm_runtime_put_noidle(&pdev->dev);	541	pm_runtime_put_noidle(&pdev->dev);
529	xenon_sdhc_unprepare(host);	542	xenon_sdhc_unprepare(host);
		543	err_clk_axi:
		544	clk_disable_unprepare(priv->axi_clk);
530	err_clk:	545	err_clk:
531	clk_disable_unprepare(pltfm_host->clk);	546	clk_disable_unprepare(pltfm_host->clk);
532	free_pltfm:	547	free_pltfm:
@@ -538,6 +553,7 @@ static int xenon_remove(struct platform_device *pdev) · 5 unmodified lines
538	{	553	{
539	struct sdhci_host *host = platform_get_drvdata(pdev);	554	struct sdhci_host *host = platform_get_drvdata(pdev);
540	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);	555	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
		556	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
541		557
542	pm_runtime_get_sync(&pdev->dev);	558	pm_runtime_get_sync(&pdev->dev);
543	pm_runtime_disable(&pdev->dev);	559	pm_runtime_disable(&pdev->dev);
@@ -546,7 +562,7 @@ static int xenon_remove(struct platform_device *pdev) · 2 unmodified lines
546	sdhci_remove_host(host, 0);	562	sdhci_remove_host(host, 0);
547		563
548	xenon_sdhc_unprepare(host);	564	xenon_sdhc_unprepare(host);
549		565	clk_disable_unprepare(priv->axi_clk);
550	clk_disable_unprepare(pltfm_host->clk);	566	clk_disable_unprepare(pltfm_host->clk);
551		567
552	sdhci_pltfm_free(pdev);	568	sdhci_pltfm_free(pdev);

drivers/mmc/host/sdhci-xenon.h+1−0

@@ -83,6 +83,7 @@ struct xenon_priv { · 82 unmodified lines
83	unsigned char bus_width;	83	unsigned char bus_width;
84	unsigned char timing;	84	unsigned char timing;
85	unsigned int clock;	85	unsigned int clock;
		86	struct clk *axi_clk;
86		87
87	int phy_type;	88	int phy_type;
88	/*	89	/*

drivers/mmc/host/tmio_mmc_core.c+0−47

@@ -129,50 +129,6 @@ static int tmio_mmc_next_sg(struct tmio_mmc_host *host) · 128 unmodified lines
129		129
130	#define CMDREQ_TIMEOUT 5000	130	#define CMDREQ_TIMEOUT 5000
131		131
132	#ifdef CONFIG_MMC_DEBUG
133
134	#define STATUS_TO_TEXT(a, status, i) \
135	do { \
136	if ((status) & TMIO_STAT_##a) { \
137	if ((i)++) \
138	printk(KERN_DEBUG " \| "); \
139	printk(KERN_DEBUG #a); \
140	} \
141	} while (0)
142
143	static void pr_debug_status(u32 status)
144	{
145	int i = 0;
146
147	pr_debug("status: %08x = ", status);
148	STATUS_TO_TEXT(CARD_REMOVE, status, i);
149	STATUS_TO_TEXT(CARD_INSERT, status, i);
150	STATUS_TO_TEXT(SIGSTATE, status, i);
151	STATUS_TO_TEXT(WRPROTECT, status, i);
152	STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
153	STATUS_TO_TEXT(CARD_INSERT_A, status, i);
154	STATUS_TO_TEXT(SIGSTATE_A, status, i);
155	STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
156	STATUS_TO_TEXT(STOPBIT_ERR, status, i);
157	STATUS_TO_TEXT(ILL_FUNC, status, i);
158	STATUS_TO_TEXT(CMD_BUSY, status, i);
159	STATUS_TO_TEXT(CMDRESPEND, status, i);
160	STATUS_TO_TEXT(DATAEND, status, i);
161	STATUS_TO_TEXT(CRCFAIL, status, i);
162	STATUS_TO_TEXT(DATATIMEOUT, status, i);
163	STATUS_TO_TEXT(CMDTIMEOUT, status, i);
164	STATUS_TO_TEXT(RXOVERFLOW, status, i);
165	STATUS_TO_TEXT(TXUNDERRUN, status, i);
166	STATUS_TO_TEXT(RXRDY, status, i);
167	STATUS_TO_TEXT(TXRQ, status, i);
168	STATUS_TO_TEXT(ILL_ACCESS, status, i);
169	printk("\n");
170	}
171
172	#else
173	#define pr_debug_status(s) do { } while (0)
174	#endif
175
176	static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)	132	static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
177	{	133	{
178	struct tmio_mmc_host *host = mmc_priv(mmc);	134	struct tmio_mmc_host *host = mmc_priv(mmc);
@@ -762,9 +718,6 @@ irqreturn_t tmio_mmc_irq(int irq, void *devid) · 583 unmodified lines
762	status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);	718	status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);
763	ireg = status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;	719	ireg = status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;
764		720
765	pr_debug_status(status);
766	pr_debug_status(ireg);
767
768	/* Clear the status except the interrupt status */	721	/* Clear the status except the interrupt status */
769	sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, TMIO_MASK_IRQ);	722	sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, TMIO_MASK_IRQ);
770		723

drivers/mtd/mtdpart.c+8−0

@@ -581,6 +581,14 @@ static struct mtd_part allocate_partition(struct mtd_info parent, · 580 unmodified lines
581	slave->mtd.erasesize = parent->erasesize;	581	slave->mtd.erasesize = parent->erasesize;
582	}	582	}
583		583
		584	/*
		585	* Slave erasesize might differ from the master one if the master
		586	* exposes several regions with different erasesize. Adjust
		587	* wr_alignment accordingly.
		588	*/
		589	if (!(slave->mtd.flags & MTD_NO_ERASE))
		590	wr_alignment = slave->mtd.erasesize;
		591
584	tmp = slave->offset;	592	tmp = slave->offset;
585	remainder = do_div(tmp, wr_alignment);	593	remainder = do_div(tmp, wr_alignment);
586	if ((slave->mtd.flags & MTD_WRITEABLE) && remainder) {	594	if ((slave->mtd.flags & MTD_WRITEABLE) && remainder) {

drivers/mtd/nand/atmel/pmecc.c+1−1

@@ -363,7 +363,7 @@ atmel_pmecc_create_user(struct atmel_pmecc *pmecc, · 362 unmodified lines
363	size += (req->ecc.strength + 1) * sizeof(u16);	363	size += (req->ecc.strength + 1) * sizeof(u16);
364	/* Reserve space for mu, dmu and delta. */	364	/* Reserve space for mu, dmu and delta. */
365	size = ALIGN(size, sizeof(s32));	365	size = ALIGN(size, sizeof(s32));
366	size += (req->ecc.strength + 1) * sizeof(s32);	366	size += (req->ecc.strength + 1) * sizeof(s32) * 3;
367		367
368	user = kzalloc(size, GFP_KERNEL);	368	user = kzalloc(size, GFP_KERNEL);
369	if (!user)	369	if (!user)

drivers/mtd/nand/lpc32xx_mlc.c+2−1

 	}
 	res = clk_prepare_enable(host->clk);
 	if (res)
-		goto err_exit1;
+		goto err_put_clk;
 	nand_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
 	nand_chip->dev_ready = lpc32xx_nand_device_ready;
 		dma_release_channel(host->dma_chan);
 err_exit2:
 	clk_disable_unprepare(host->clk);
+err_put_clk:
 	clk_put(host->clk);
 err_exit1:
 	lpc32xx_wp_enable(host);

drivers/mtd/nand/nand_base.c+1−2

 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 			     struct mtd_oob_ops *ops)
 {
-	int chipnr, realpage, page, blockmask, column;
+	int chipnr, realpage, page, column;
 	struct nand_chip *chip = mtd_to_nand(mtd);
 	uint32_t writelen = ops->len;
 	realpage = (int)(to >> chip->page_shift);
 	page = realpage & chip->pagemask;
-	blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
 	/* Invalidate the page cache, when we write to the cached page */
 	if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&

drivers/mtd/spi-nor/spi-nor.c+42−3

@@ -1784,7 +1784,7 @@ spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, · 1783 unmodified lines
1784	* @nor: pointer to a 'struct spi_nor'	1784	* @nor: pointer to a 'struct spi_nor'
1785	* @addr: offset in the SFDP area to start reading data from	1785	* @addr: offset in the SFDP area to start reading data from
1786	* @len: number of bytes to read	1786	* @len: number of bytes to read
1787	* @buf: buffer where the SFDP data are copied into	1787	* @buf: buffer where the SFDP data are copied into (dma-safe memory)
1788	*	1788	*
1789	* Whatever the actual numbers of bytes for address and dummy cycles are	1789	* Whatever the actual numbers of bytes for address and dummy cycles are
1790	* for (Fast) Read commands, the Read SFDP (5Ah) instruction is always	1790	* for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
@@ -1829,6 +1829,36 @@ read_err: · 38 unmodified lines
1829	return ret;	1829	return ret;
1830	}	1830	}
1831		1831
		1832	/**
		1833	* spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters.
		1834	* @nor: pointer to a 'struct spi_nor'
		1835	* @addr: offset in the SFDP area to start reading data from
		1836	* @len: number of bytes to read
		1837	* @buf: buffer where the SFDP data are copied into
		1838	*
		1839	* Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not
		1840	* guaranteed to be dma-safe.
		1841	*
		1842	* Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp()
		1843	* otherwise.
		1844	*/
		1845	static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
		1846	size_t len, void *buf)
		1847	{
		1848	void *dma_safe_buf;
		1849	int ret;
		1850
		1851	dma_safe_buf = kmalloc(len, GFP_KERNEL);
		1852	if (!dma_safe_buf)
		1853	return -ENOMEM;
		1854
		1855	ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf);
		1856	memcpy(buf, dma_safe_buf, len);
		1857	kfree(dma_safe_buf);
		1858
		1859	return ret;
		1860	}
		1861
1832	struct sfdp_parameter_header {	1862	struct sfdp_parameter_header {
1833	u8 id_lsb;	1863	u8 id_lsb;
1834	u8 minor;	1864	u8 minor;
@@ -2101,7 +2131,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, · 266 unmodified lines
2101	bfpt_header->length * sizeof(u32));	2131	bfpt_header->length * sizeof(u32));
2102	addr = SFDP_PARAM_HEADER_PTP(bfpt_header);	2132	addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
2103	memset(&bfpt, 0, sizeof(bfpt));	2133	memset(&bfpt, 0, sizeof(bfpt));
2104	err = spi_nor_read_sfdp(nor, addr, len, &bfpt);	2134	err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt);
2105	if (err < 0)	2135	if (err < 0)
2106	return err;	2136	return err;
2107		2137
@@ -2127,6 +2157,15 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, · 19 unmodified lines
2127	params->size = bfpt.dwords[BFPT_DWORD(2)];	2157	params->size = bfpt.dwords[BFPT_DWORD(2)];
2128	if (params->size & BIT(31)) {	2158	if (params->size & BIT(31)) {
2129	params->size &= ~BIT(31);	2159	params->size &= ~BIT(31);
		2160
		2161	/*
		2162	* Prevent overflows on params->size. Anyway, a NOR of 2^64
		2163	* bits is unlikely to exist so this error probably means
		2164	* the BFPT we are reading is corrupted/wrong.
		2165	*/
		2166	if (params->size > 63)
		2167	return -EINVAL;
		2168
2130	params->size = 1ULL << params->size;	2169	params->size = 1ULL << params->size;
2131	} else {	2170	} else {
2132	params->size++;	2171	params->size++;
@@ -2243,7 +2282,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, · 110 unmodified lines
2243	int i, err;	2282	int i, err;
2244		2283
2245	/* Get the SFDP header. */	2284	/* Get the SFDP header. */
2246	err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);	2285	err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header);
2247	if (err < 0)	2286	if (err < 0)
2248	return err;	2287	return err;
2249		2288

drivers/net/dsa/mv88e6xxx/chip.c+6−0

 	};
 	int i, err;
+	/* DSA and CPU ports have to be members of multiple vlans */
+	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
+		return 0;
 	if (!vid_begin)
 		return -EOPNOTSUPP;
 	if (chip->irq > 0) {
 		if (chip->info->g2_irqs > 0)
 			mv88e6xxx_g2_irq_free(chip);
+		mutex_lock(&chip->reg_lock);
 		mv88e6xxx_g1_irq_free(chip);
+		mutex_unlock(&chip->reg_lock);
 	}
 }

drivers/net/ethernet/aquantia/atlantic/aq_cfg.h+4−0

@@ -51,6 +51,10 @@ · 50 unmodified lines
51		51
52	#define AQ_CFG_SKB_FRAGS_MAX 32U	52	#define AQ_CFG_SKB_FRAGS_MAX 32U
53		53
		54	/* Number of descriptors available in one ring to resume this ring queue
		55	*/
		56	#define AQ_CFG_RESTART_DESC_THRES (AQ_CFG_SKB_FRAGS_MAX * 2)
		57
54	#define AQ_CFG_NAPI_WEIGHT 64U	58	#define AQ_CFG_NAPI_WEIGHT 64U
55		59
56	#define AQ_CFG_MULTICAST_ADDRESS_MAX 32U	60	#define AQ_CFG_MULTICAST_ADDRESS_MAX 32U

drivers/net/ethernet/aquantia/atlantic/aq_nic.c+68−77

 	return 0;
 }
+static int aq_nic_update_link_status(struct aq_nic_s *self)
+{
+	int err = self->aq_hw_ops.hw_get_link_status(self->aq_hw);
+	if (err)
+		return err;
+	if (self->link_status.mbps != self->aq_hw->aq_link_status.mbps)
+		pr_info("%s: link change old %d new %d\n",
+			AQ_CFG_DRV_NAME, self->link_status.mbps,
+			self->aq_hw->aq_link_status.mbps);
+	self->link_status = self->aq_hw->aq_link_status;
+	if (!netif_carrier_ok(self->ndev) && self->link_status.mbps) {
+		aq_utils_obj_set(&self->header.flags,
+				 AQ_NIC_FLAG_STARTED);
+		aq_utils_obj_clear(&self->header.flags,
+				   AQ_NIC_LINK_DOWN);
+		netif_carrier_on(self->ndev);
+		netif_tx_wake_all_queues(self->ndev);
+	}
+	if (netif_carrier_ok(self->ndev) && !self->link_status.mbps) {
+		netif_carrier_off(self->ndev);
+		netif_tx_disable(self->ndev);
+		aq_utils_obj_set(&self->header.flags, AQ_NIC_LINK_DOWN);
+	}
+	return 0;
+}
 static void aq_nic_service_timer_cb(unsigned long param)
 {
 	struct aq_nic_s *self = (struct aq_nic_s *)param;
 	if (aq_utils_obj_test(&self->header.flags, AQ_NIC_FLAGS_IS_NOT_READY))
 		goto err_exit;
-	err = self->aq_hw_ops.hw_get_link_status(self->aq_hw);
+	err = aq_nic_update_link_status(self);
-	if (err < 0)
+	if (err)
 		goto err_exit;
-	self->link_status = self->aq_hw->aq_link_status;
 	self->aq_hw_ops.hw_interrupt_moderation_set(self->aq_hw,
 		    self->aq_nic_cfg.is_interrupt_moderation);
-	if (self->link_status.mbps) {
-		aq_utils_obj_set(&self->header.flags,
-				 AQ_NIC_FLAG_STARTED);
-		aq_utils_obj_clear(&self->header.flags,
-				   AQ_NIC_LINK_DOWN);
-		netif_carrier_on(self->ndev);
-	} else {
-		netif_carrier_off(self->ndev);
-		aq_utils_obj_set(&self->header.flags, AQ_NIC_LINK_DOWN);
-	}
 	memset(&stats_rx, 0U, sizeof(struct aq_ring_stats_rx_s));
 	memset(&stats_tx, 0U, sizeof(struct aq_ring_stats_tx_s));
 	for (i = AQ_DIMOF(self->aq_vec); i--;) {
 	SET_NETDEV_DEV(ndev, dev);
 	ndev->if_port = port;
-	ndev->min_mtu = ETH_MIN_MTU;
 	self->ndev = ndev;
 	self->aq_pci_func = aq_pci_func;
 int aq_nic_ndev_register(struct aq_nic_s *self)
 {
 	int err = 0;
-	unsigned int i = 0U;
 	if (!self->ndev) {
 		err = -EINVAL;
 	netif_carrier_off(self->ndev);
-	for (i = AQ_CFG_VECS_MAX; i--;)
+	netif_tx_disable(self->ndev);
-		aq_nic_ndev_queue_stop(self, i);
 	err = register_netdev(self->ndev);
 	if (err < 0)
 	self->ndev->features = aq_hw_caps->hw_features;
 	self->ndev->priv_flags = aq_hw_caps->hw_priv_flags;
 	self->ndev->mtu = aq_nic_cfg->mtu - ETH_HLEN;
+	self->ndev->max_mtu = self->aq_hw_caps.mtu - ETH_FCS_LEN - ETH_HLEN;
 	return 0;
 }
 		err = -EINVAL;
 		goto err_exit;
 	}
-	if (netif_running(ndev)) {
+	if (netif_running(ndev))
-		unsigned int i;
+		netif_tx_disable(ndev);
-		for (i = AQ_CFG_VECS_MAX; i--;)
-			netif_stop_subqueue(ndev, i);
-	}
 	for (self->aq_vecs = 0; self->aq_vecs < self->aq_nic_cfg.vecs;
 		self->aq_vecs++) {
 	return err;
 }
-void aq_nic_ndev_queue_start(struct aq_nic_s *self, unsigned int idx)
-{
-	netif_start_subqueue(self->ndev, idx);
-}
-void aq_nic_ndev_queue_stop(struct aq_nic_s *self, unsigned int idx)
-{
-	netif_stop_subqueue(self->ndev, idx);
-}
 int aq_nic_start(struct aq_nic_s *self)
 {
 	struct aq_vec_s *aq_vec = NULL;
 			goto err_exit;
 	}
-	for (i = 0U, aq_vec = self->aq_vec[0];
-		self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
-		aq_nic_ndev_queue_start(self, i);
 	err = netif_set_real_num_tx_queues(self->ndev, self->aq_vecs);
 	if (err < 0)
 		goto err_exit;
 	if (err < 0)
 		goto err_exit;
+	netif_tx_start_all_queues(self->ndev);
 err_exit:
 	return err;
 }
 	unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
 	unsigned int frag_count = 0U;
 	unsigned int dx = ring->sw_tail;
+	struct aq_ring_buff_s *first = NULL;
 	struct aq_ring_buff_s *dx_buff = &ring->buff_ring[dx];
 	if (unlikely(skb_is_gso(skb))) {
 		dx_buff->len_l4 = tcp_hdrlen(skb);
 		dx_buff->mss = skb_shinfo(skb)->gso_size;
 		dx_buff->is_txc = 1U;
+		dx_buff->eop_index = 0xffffU;
 		dx_buff->is_ipv6 =
 			(ip_hdr(skb)->version == 6) ? 1U : 0U;
 	if (unlikely(dma_mapping_error(aq_nic_get_dev(self), dx_buff->pa)))
 		goto exit;
+	first = dx_buff;
 	dx_buff->len_pkt = skb->len;
 	dx_buff->is_sop = 1U;
 	dx_buff->is_mapped = 1U;
 	for (; nr_frags--; ++frag_count) {
 		unsigned int frag_len = 0U;
+		unsigned int buff_offset = 0U;
+		unsigned int buff_size = 0U;
 		dma_addr_t frag_pa;
 		skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_count];
 		frag_len = skb_frag_size(frag);
-		frag_pa = skb_frag_dma_map(aq_nic_get_dev(self), frag, 0,
-					   frag_len, DMA_TO_DEVICE);
-		if (unlikely(dma_mapping_error(aq_nic_get_dev(self), frag_pa)))
+		while (frag_len) {
-			goto mapping_error;
+			if (frag_len > AQ_CFG_TX_FRAME_MAX)
+				buff_size = AQ_CFG_TX_FRAME_MAX;
+			else
+				buff_size = frag_len;
+			frag_pa = skb_frag_dma_map(aq_nic_get_dev(self),
+						   frag,
+						   buff_offset,
+						   buff_size,
+						   DMA_TO_DEVICE);
+			if (unlikely(dma_mapping_error(aq_nic_get_dev(self),
+						       frag_pa)))
+				goto mapping_error;
-		while (frag_len > AQ_CFG_TX_FRAME_MAX) {
 			dx = aq_ring_next_dx(ring, dx);
 			dx_buff = &ring->buff_ring[dx];
 			dx_buff->flags = 0U;
-			dx_buff->len = AQ_CFG_TX_FRAME_MAX;
+			dx_buff->len = buff_size;
 			dx_buff->pa = frag_pa;
 			dx_buff->is_mapped = 1U;
+			dx_buff->eop_index = 0xffffU;
+			frag_len -= buff_size;
+			buff_offset += buff_size;
-			frag_len -= AQ_CFG_TX_FRAME_MAX;
-			frag_pa += AQ_CFG_TX_FRAME_MAX;
 			++ret;
 		}
-		dx = aq_ring_next_dx(ring, dx);
-		dx_buff = &ring->buff_ring[dx];
-		dx_buff->flags = 0U;
-		dx_buff->len = frag_len;
-		dx_buff->pa = frag_pa;
-		dx_buff->is_mapped = 1U;
-		++ret;
 	}
+	first->eop_index = dx;
 	dx_buff->is_eop = 1U;
 	dx_buff->skb = skb;
 	goto exit;
 	unsigned int vec = skb->queue_mapping % self->aq_nic_cfg.vecs;
 	unsigned int tc = 0U;
 	int err = NETDEV_TX_OK;
-	bool is_nic_in_bad_state;
 	frags = skb_shinfo(skb)->nr_frags + 1;
 		goto err_exit;
 	}
-	is_nic_in_bad_state = aq_utils_obj_test(&self->header.flags,
+	aq_ring_update_queue_state(ring);
-						AQ_NIC_FLAGS_IS_NOT_TX_READY) ||
-						(aq_ring_avail_dx(ring) <
-						AQ_CFG_SKB_FRAGS_MAX);
-	if (is_nic_in_bad_state) {
+	/* Above status update may stop the queue. Check this. */
-		aq_nic_ndev_queue_stop(self, ring->idx);
+	if (__netif_subqueue_stopped(self->ndev, ring->idx)) {
 		err = NETDEV_TX_BUSY;
 		goto err_exit;
 	}
 						      ring,
 						      frags);
 		if (err >= 0) {
-			if (aq_ring_avail_dx(ring) < AQ_CFG_SKB_FRAGS_MAX + 1)
-				aq_nic_ndev_queue_stop(self, ring->idx);
 			++ring->stats.tx.packets;
 			ring->stats.tx.bytes += skb->len;
 		}
 int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu)
 {
-	int err = 0;
-	if (new_mtu > self->aq_hw_caps.mtu) {
-		err = -EINVAL;
-		goto err_exit;
-	}
 	self->aq_nic_cfg.mtu = new_mtu;
-err_exit:
+	return 0;
-	return err;
 }
 int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev)
 	struct aq_vec_s *aq_vec = NULL;
 	unsigned int i = 0U;
-	for (i = 0U, aq_vec = self->aq_vec[0];
+	netif_tx_disable(self->ndev);
-		self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
-		aq_nic_ndev_queue_stop(self, i);
 	del_timer_sync(&self->service_timer);

drivers/net/ethernet/aquantia/atlantic/aq_nic.h+0−2

 int aq_nic_init(struct aq_nic_s *self);
 int aq_nic_cfg_start(struct aq_nic_s *self);
 int aq_nic_ndev_register(struct aq_nic_s *self);
-void aq_nic_ndev_queue_start(struct aq_nic_s *self, unsigned int idx);
-void aq_nic_ndev_queue_stop(struct aq_nic_s *self, unsigned int idx);
 void aq_nic_ndev_free(struct aq_nic_s *self);
 int aq_nic_start(struct aq_nic_s *self);
 int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb);

drivers/net/ethernet/aquantia/atlantic/aq_ring.c+45−8

@@ -104,6 +104,38 @@ int aq_ring_init(struct aq_ring_s *self) · 103 unmodified lines
104	return 0;	104	return 0;
105	}	105	}
106		106
		107	static inline bool aq_ring_dx_in_range(unsigned int h, unsigned int i,
		108	unsigned int t)
		109	{
		110	return (h < t) ? ((h < i) && (i < t)) : ((h < i) \|\| (i < t));
		111	}
		112
		113	void aq_ring_update_queue_state(struct aq_ring_s *ring)
		114	{
		115	if (aq_ring_avail_dx(ring) <= AQ_CFG_SKB_FRAGS_MAX)
		116	aq_ring_queue_stop(ring);
		117	else if (aq_ring_avail_dx(ring) > AQ_CFG_RESTART_DESC_THRES)
		118	aq_ring_queue_wake(ring);
		119	}
		120
		121	void aq_ring_queue_wake(struct aq_ring_s *ring)
		122	{
		123	struct net_device *ndev = aq_nic_get_ndev(ring->aq_nic);
		124
		125	if (__netif_subqueue_stopped(ndev, ring->idx)) {
		126	netif_wake_subqueue(ndev, ring->idx);
		127	ring->stats.tx.queue_restarts++;
		128	}
		129	}
		130
		131	void aq_ring_queue_stop(struct aq_ring_s *ring)
		132	{
		133	struct net_device *ndev = aq_nic_get_ndev(ring->aq_nic);
		134
		135	if (!__netif_subqueue_stopped(ndev, ring->idx))
		136	netif_stop_subqueue(ndev, ring->idx);
		137	}
		138
107	void aq_ring_tx_clean(struct aq_ring_s *self)	139	void aq_ring_tx_clean(struct aq_ring_s *self)
108	{	140	{
109	struct device *dev = aq_nic_get_dev(self->aq_nic);	141	struct device *dev = aq_nic_get_dev(self->aq_nic);
@@ -113,23 +145,28 @@ void aq_ring_tx_clean(struct aq_ring_s *self) · 3 unmodified lines
113	struct aq_ring_buff_s *buff = &self->buff_ring[self->sw_head];	145	struct aq_ring_buff_s *buff = &self->buff_ring[self->sw_head];
114		146
115	if (likely(buff->is_mapped)) {	147	if (likely(buff->is_mapped)) {
116	if (unlikely(buff->is_sop))	148	if (unlikely(buff->is_sop)) {
		149	if (!buff->is_eop &&
		150	buff->eop_index != 0xffffU &&
		151	(!aq_ring_dx_in_range(self->sw_head,
		152	buff->eop_index,
		153	self->hw_head)))
		154	break;
		155
117	dma_unmap_single(dev, buff->pa, buff->len,	156	dma_unmap_single(dev, buff->pa, buff->len,
118	DMA_TO_DEVICE);	157	DMA_TO_DEVICE);
119	else	158	} else {
120	dma_unmap_page(dev, buff->pa, buff->len,	159	dma_unmap_page(dev, buff->pa, buff->len,
121	DMA_TO_DEVICE);	160	DMA_TO_DEVICE);
		161	}
122	}	162	}
123		163
124	if (unlikely(buff->is_eop))	164	if (unlikely(buff->is_eop))
125	dev_kfree_skb_any(buff->skb);	165	dev_kfree_skb_any(buff->skb);
126	}
127	}
128		166
129	static inline unsigned int aq_ring_dx_in_range(unsigned int h, unsigned int i,	167	buff->pa = 0U;
130	unsigned int t)	168	buff->eop_index = 0xffffU;
131	{	169	}
132	return (h < t) ? ((h < i) && (i < t)) : ((h < i) \|\| (i < t));
133	}	170	}
134		171
135	#define AQ_SKB_ALIGN SKB_DATA_ALIGN(sizeof(struct skb_shared_info))	172	#define AQ_SKB_ALIGN SKB_DATA_ALIGN(sizeof(struct skb_shared_info))

drivers/net/ethernet/aquantia/atlantic/aq_ring.h+8−2

 	};
 	union {
 		struct {
-			u32 len:16;
+			u16 len;
 			u32 is_ip_cso:1;
 			u32 is_udp_cso:1;
 			u32 is_tcp_cso:1;
 			u32 is_cleaned:1;
 			u32 is_error:1;
 			u32 rsvd3:6;
+			u16 eop_index;
+			u16 rsvd4;
 		};
-		u32 flags;
+		u64 flags;
 	};
 };
 	u64 errors;
 	u64 packets;
 	u64 bytes;
+	u64 queue_restarts;
 };
 union aq_ring_stats_s {
 int aq_ring_init(struct aq_ring_s *self);
 void aq_ring_rx_deinit(struct aq_ring_s *self);
 void aq_ring_free(struct aq_ring_s *self);
+void aq_ring_update_queue_state(struct aq_ring_s *ring);
+void aq_ring_queue_wake(struct aq_ring_s *ring);
+void aq_ring_queue_stop(struct aq_ring_s *ring);
 void aq_ring_tx_clean(struct aq_ring_s *self);
 int aq_ring_rx_clean(struct aq_ring_s *self,
 		     struct napi_struct *napi,

drivers/net/ethernet/aquantia/atlantic/aq_vec.c+2−6

@@ -59,12 +59,7 @@ static int aq_vec_poll(struct napi_struct *napi, int budget) · 58 unmodified lines
59	if (ring[AQ_VEC_TX_ID].sw_head !=	59	if (ring[AQ_VEC_TX_ID].sw_head !=
60	ring[AQ_VEC_TX_ID].hw_head) {	60	ring[AQ_VEC_TX_ID].hw_head) {
61	aq_ring_tx_clean(&ring[AQ_VEC_TX_ID]);	61	aq_ring_tx_clean(&ring[AQ_VEC_TX_ID]);
62		62	aq_ring_update_queue_state(&ring[AQ_VEC_TX_ID]);
63	if (aq_ring_avail_dx(&ring[AQ_VEC_TX_ID]) >
64	AQ_CFG_SKB_FRAGS_MAX) {
65	aq_nic_ndev_queue_start(self->aq_nic,
66	ring[AQ_VEC_TX_ID].idx);
67	}
68	was_tx_cleaned = true;	63	was_tx_cleaned = true;
69	}	64	}
70		65
@@ -364,6 +359,7 @@ void aq_vec_add_stats(struct aq_vec_s *self, · 293 unmodified lines
364	stats_tx->packets += tx->packets;	359	stats_tx->packets += tx->packets;
365	stats_tx->bytes += tx->bytes;	360	stats_tx->bytes += tx->bytes;
366	stats_tx->errors += tx->errors;	361	stats_tx->errors += tx->errors;
		362	stats_tx->queue_restarts += tx->queue_restarts;
367	}	363	}
368	}	364	}
369		365

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h+1−1

@@ -16,7 +16,7 @@ · 15 unmodified lines
16		16
17	#include "../aq_common.h"	17	#include "../aq_common.h"
18		18
19	#define HW_ATL_B0_MTU_JUMBO (16000U)	19	#define HW_ATL_B0_MTU_JUMBO 16352U
20	#define HW_ATL_B0_MTU 1514U	20	#define HW_ATL_B0_MTU 1514U
21		21
22	#define HW_ATL_B0_TX_RINGS 4U	22	#define HW_ATL_B0_TX_RINGS 4U

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c+1−2

@@ -351,8 +351,7 @@ int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self) · 350 unmodified lines
351	break;	351	break;
352		352
353	default:	353	default:
354	link_status->mbps = 0U;	354	return -EBUSY;
355	break;
356	}	355	}
357	}	356	}
358		357

drivers/net/ethernet/broadcom/bcmsysport.c+32−20

 	netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n");
 }
+static void bcm_sysport_update_tx_stats(struct bcm_sysport_priv *priv,
+					u64 *tx_bytes, u64 *tx_packets)
+{
+	struct bcm_sysport_tx_ring *ring;
+	u64 bytes = 0, packets = 0;
+	unsigned int start;
+	unsigned int q;
+	for (q = 0; q < priv->netdev->num_tx_queues; q++) {
+		ring = &priv->tx_rings[q];
+		do {
+			start = u64_stats_fetch_begin_irq(&priv->syncp);
+			bytes = ring->bytes;
+			packets = ring->packets;
+		} while (u64_stats_fetch_retry_irq(&priv->syncp, start));
+		*tx_bytes += bytes;
+		*tx_packets += packets;
+	}
+}
 static void bcm_sysport_get_stats(struct net_device *dev,
 				  struct ethtool_stats *stats, u64 *data)
 {
 	struct bcm_sysport_stats64 *stats64 = &priv->stats64;
 	struct u64_stats_sync *syncp = &priv->syncp;
 	struct bcm_sysport_tx_ring *ring;
+	u64 tx_bytes = 0, tx_packets = 0;
 	unsigned int start;
 	int i, j;
-	if (netif_running(dev))
+	if (netif_running(dev)) {
 		bcm_sysport_update_mib_counters(priv);
+		bcm_sysport_update_tx_stats(priv, &tx_bytes, &tx_packets);
+		stats64->tx_bytes = tx_bytes;
+		stats64->tx_packets = tx_packets;
+	}
 	for (i =  0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
 		const struct bcm_sysport_stats *s;
 			continue;
 		p += s->stat_offset;
-		if (s->stat_sizeof == sizeof(u64))
+		if (s->stat_sizeof == sizeof(u64) &&
+		    s->type == BCM_SYSPORT_STAT_NETDEV64) {
 			do {
 				start = u64_stats_fetch_begin_irq(syncp);
 				data[i] = *(u64 *)p;
 			} while (u64_stats_fetch_retry_irq(syncp, start));
-		else
+		} else
 			data[i] = *(u32 *)p;
 		j++;
 	}
 {
 	struct bcm_sysport_priv *priv = netdev_priv(dev);
 	struct bcm_sysport_stats64 *stats64 = &priv->stats64;
-	struct bcm_sysport_tx_ring *ring;
-	u64 tx_packets = 0, tx_bytes = 0;
 	unsigned int start;
-	unsigned int q;
 	netdev_stats_to_stats64(stats, &dev->stats);
-	for (q = 0; q < dev->num_tx_queues; q++) {
+	bcm_sysport_update_tx_stats(priv, &stats->tx_bytes,
-		ring = &priv->tx_rings[q];
+				    &stats->tx_packets);
-		do {
-			start = u64_stats_fetch_begin_irq(&priv->syncp);
-			tx_bytes = ring->bytes;
-			tx_packets = ring->packets;
-		} while (u64_stats_fetch_retry_irq(&priv->syncp, start));
-		stats->tx_bytes += tx_bytes;
-		stats->tx_packets += tx_packets;
-	}
-	stats64->tx_bytes = stats->tx_bytes;
-	stats64->tx_packets = stats->tx_packets;
 	do {
 		start = u64_stats_fetch_begin_irq(&priv->syncp);

drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c+4−0

 {
 	int rc = 0;
+	if (!is_classid_clsact_ingress(cls_flower->common.classid) ||
+	    cls_flower->common.chain_index)
+		return -EOPNOTSUPP;
 	switch (cls_flower->command) {
 	case TC_CLSFLOWER_REPLACE:
 		rc = bnxt_tc_add_flow(bp, src_fid, cls_flower);

drivers/net/ethernet/broadcom/cnic.c+1−1

@@ -1278,7 +1278,7 @@ static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev) · 1277 unmodified lines
1278		1278
1279	ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);	1279	ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1280	if (ret)	1280	if (ret)
1281	return -ENOMEM;	1281	goto error;
1282		1282
1283	n = CNIC_PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;	1283	n = CNIC_PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
1284	for (i = 0, j = 0; i < cp->max_cid_space; i++) {	1284	for (i = 0, j = 0; i < cp->max_cid_space; i++) {

drivers/net/ethernet/freescale/fec.h+2−2

@@ -374,8 +374,8 @@ struct bufdesc_ex { · 373 unmodified lines
374	#define FEC_ENET_TS_AVAIL ((uint)0x00010000)	374	#define FEC_ENET_TS_AVAIL ((uint)0x00010000)
375	#define FEC_ENET_TS_TIMER ((uint)0x00008000)	375	#define FEC_ENET_TS_TIMER ((uint)0x00008000)
376		376
377	#define FEC_DEFAULT_IMASK (FEC_ENET_TXF \| FEC_ENET_RXF \| FEC_ENET_MII \| FEC_ENET_TS_TIMER)	377	#define FEC_DEFAULT_IMASK (FEC_ENET_TXF \| FEC_ENET_RXF \| FEC_ENET_MII)
378	#define FEC_NAPI_IMASK (FEC_ENET_MII \| FEC_ENET_TS_TIMER)	378	#define FEC_NAPI_IMASK FEC_ENET_MII
379	#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))	379	#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
380		380
381	/* ENET interrupt coalescing macro define */	381	/* ENET interrupt coalescing macro define */

drivers/net/ethernet/freescale/fec_main.c+4−4

@@ -1559,14 +1559,14 @@ fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) · 1558 unmodified lines
1559	if (int_events == 0)	1559	if (int_events == 0)
1560	return false;	1560	return false;
1561		1561
1562	if (int_events & FEC_ENET_RXF)	1562	if (int_events & FEC_ENET_RXF_0)
1563	fep->work_rx \|= (1 << 2);	1563	fep->work_rx \|= (1 << 2);
1564	if (int_events & FEC_ENET_RXF_1)	1564	if (int_events & FEC_ENET_RXF_1)
1565	fep->work_rx \|= (1 << 0);	1565	fep->work_rx \|= (1 << 0);
1566	if (int_events & FEC_ENET_RXF_2)	1566	if (int_events & FEC_ENET_RXF_2)
1567	fep->work_rx \|= (1 << 1);	1567	fep->work_rx \|= (1 << 1);
1568		1568
1569	if (int_events & FEC_ENET_TXF)	1569	if (int_events & FEC_ENET_TXF_0)
1570	fep->work_tx \|= (1 << 2);	1570	fep->work_tx \|= (1 << 2);
1571	if (int_events & FEC_ENET_TXF_1)	1571	if (int_events & FEC_ENET_TXF_1)
1572	fep->work_tx \|= (1 << 0);	1572	fep->work_tx \|= (1 << 0);
@@ -1604,8 +1604,8 @@ fec_enet_interrupt(int irq, void *dev_id) · 31 unmodified lines
1604	}	1604	}
1605		1605
1606	if (fep->ptp_clock)	1606	if (fep->ptp_clock)
1607	fec_ptp_check_pps_event(fep);	1607	if (fec_ptp_check_pps_event(fep))
1608		1608	ret = IRQ_HANDLED;
1609	return ret;	1609	return ret;
1610	}	1610	}
1611		1611

drivers/net/ethernet/hisilicon/hns3/hnae3.c+9−34

 }
 static int hnae3_match_n_instantiate(struct hnae3_client *client,
-				     struct hnae3_ae_dev *ae_dev,
+				     struct hnae3_ae_dev *ae_dev, bool is_reg)
-				     bool is_reg, bool *matched)
 {
 	int ret;
-	*matched = false;
 	/* check if this client matches the type of ae_dev */
 	if (!(hnae3_client_match(client->type, ae_dev->dev_type) &&
 	      hnae_get_bit(ae_dev->flag, HNAE3_DEV_INITED_B))) {
 		return 0;
 	}
-	/* there is a match of client and dev */
-	*matched = true;
 	/* now, (un-)instantiate client by calling lower layer */
 	if (is_reg) {
 {
 	struct hnae3_client *client_tmp;
 	struct hnae3_ae_dev *ae_dev;
-	bool matched;
 	int ret = 0;
 	mutex_lock(&hnae3_common_lock);
 		/* if the client could not be initialized on current port, for
 		 * any error reasons, move on to next available port
 		 */
-		ret = hnae3_match_n_instantiate(client, ae_dev, true, &matched);
+		ret = hnae3_match_n_instantiate(client, ae_dev, true);
 		if (ret)
 			dev_err(&ae_dev->pdev->dev,
 				"match and instantiation failed for port\n");
 void hnae3_unregister_client(struct hnae3_client *client)
 {
 	struct hnae3_ae_dev *ae_dev;
-	bool matched;
 	mutex_lock(&hnae3_common_lock);
 	/* un-initialize the client on every matched port */
 	list_for_each_entry(ae_dev, &hnae3_ae_dev_list, node) {
-		hnae3_match_n_instantiate(client, ae_dev, false, &matched);
+		hnae3_match_n_instantiate(client, ae_dev, false);
 	}
 	list_del(&client->node);
 	const struct pci_device_id *id;
 	struct hnae3_ae_dev *ae_dev;
 	struct hnae3_client *client;
-	bool matched;
 	int ret = 0;
 	mutex_lock(&hnae3_common_lock);
 		 * initialize the figure out client instance
 		 */
 		list_for_each_entry(client, &hnae3_client_list, node) {
-			ret = hnae3_match_n_instantiate(client, ae_dev, true,
+			ret = hnae3_match_n_instantiate(client, ae_dev, true);
-							&matched);
 			if (ret)
 				dev_err(&ae_dev->pdev->dev,
 					"match and instantiation failed\n");
-			if (matched)
-				break;
 		}
 	}
 	const struct pci_device_id *id;
 	struct hnae3_ae_dev *ae_dev;
 	struct hnae3_client *client;
-	bool matched;
 	mutex_lock(&hnae3_common_lock);
 	/* Check if there are matched ae_dev */
 		/* check the client list for the match with this ae_dev type and
 		 * un-initialize the figure out client instance
 		 */
-		list_for_each_entry(client, &hnae3_client_list, node) {
+		list_for_each_entry(client, &hnae3_client_list, node)
-			hnae3_match_n_instantiate(client, ae_dev, false,
+			hnae3_match_n_instantiate(client, ae_dev, false);
-						  &matched);
-			if (matched)
-				break;
-		}
 		ae_algo->ops->uninit_ae_dev(ae_dev);
 		hnae_set_bit(ae_dev->flag, HNAE3_DEV_INITED_B, 0);
 	const struct pci_device_id *id;
 	struct hnae3_ae_algo *ae_algo;
 	struct hnae3_client *client;
-	bool matched;
 	int ret = 0;
 	mutex_lock(&hnae3_common_lock);
 	 * initialize the figure out client instance
 	 */
 	list_for_each_entry(client, &hnae3_client_list, node) {
-		ret = hnae3_match_n_instantiate(client, ae_dev, true,
+		ret = hnae3_match_n_instantiate(client, ae_dev, true);
-						&matched);
 		if (ret)
 			dev_err(&ae_dev->pdev->dev,
 				"match and instantiation failed\n");
-		if (matched)
-			break;
 	}
 out_err:
 	const struct pci_device_id *id;
 	struct hnae3_ae_algo *ae_algo;
 	struct hnae3_client *client;
-	bool matched;
 	mutex_lock(&hnae3_common_lock);
 	/* Check if there are matched ae_algo */
 		if (!id)
 			continue;
-		list_for_each_entry(client, &hnae3_client_list, node) {
+		list_for_each_entry(client, &hnae3_client_list, node)
-			hnae3_match_n_instantiate(client, ae_dev, false,
+			hnae3_match_n_instantiate(client, ae_dev, false);
-						  &matched);
-			if (matched)
-				break;
-		}
 		ae_algo->ops->uninit_ae_dev(ae_dev);
 		hnae_set_bit(ae_dev->flag, HNAE3_DEV_INITED_B, 0);

drivers/net/ethernet/hisilicon/hns3/hnae3.h+13−2

 #define HNAE3_CLASS_NAME_SIZE 16
 #define HNAE3_DEV_INITED_B			0x0
-#define HNAE_DEV_SUPPORT_ROCE_B			0x1
+#define HNAE3_DEV_SUPPORT_ROCE_B		0x1
+#define HNAE3_DEV_SUPPORT_DCB_B			0x2
+#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\
+		BIT(HNAE3_DEV_SUPPORT_ROCE_B))
+#define hnae3_dev_roce_supported(hdev) \
+	hnae_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
+#define hnae3_dev_dcb_supported(hdev) \
+	hnae_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
 #define ring_ptr_move_fw(ring, p) \
 	((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
 struct hnae3_tc_info {
 	u16	tqp_offset;	/* TQP offset from base TQP */
 	u16	tqp_count;	/* Total TQPs */
-	u8	up;		/* user priority */
 	u8	tc;		/* TC index */
 	bool	enable;		/* If this TC is enable or not */
 };
 #define HNAE3_MAX_TC		8
+#define HNAE3_MAX_USER_PRIO	8
 struct hnae3_knic_private_info {
 	struct net_device *netdev; /* Set by KNIC client when init instance */
 	u16 rss_size;		   /* Allocated RSS queues */
 	u16 num_desc;
 	u8 num_tc;		   /* Total number of enabled TCs */
+	u8 prio_tc[HNAE3_MAX_USER_PRIO];  /* TC indexed by prio */
 	struct hnae3_tc_info tc_info[HNAE3_MAX_TC]; /* Idx of array is HW TC */
 	u16 num_tqps;		  /* total number of TQPs in this handle */

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h+9−3

 	u8 rsv[18];
 };
-#define HCLGE_VECTOR_ELEMENTS_PER_CMD	11
+#define HCLGE_VECTOR_ELEMENTS_PER_CMD	10
 enum hclge_int_type {
 	HCLGE_INT_TX,
 #define HCLGE_INT_TYPE_S	0
 #define HCLGE_INT_TYPE_M	0x3
 #define HCLGE_TQP_ID_S		2
-#define HCLGE_TQP_ID_M		(0x3fff << HCLGE_TQP_ID_S)
+#define HCLGE_TQP_ID_M		(0x7ff << HCLGE_TQP_ID_S)
+#define HCLGE_INT_GL_IDX_S	13
+#define HCLGE_INT_GL_IDX_M	(0x3 << HCLGE_INT_GL_IDX_S)
 	__le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
+	u8 vfid;
+	u8 rsv;
 };
 #define HCLGE_TC_NUM		8
 struct hclge_rx_priv_buff {
 	__le16 buf_num[HCLGE_TC_NUM];
-	u8 rsv[8];
+	__le16 shared_buf;
+	u8 rsv[6];
 };
 struct hclge_query_version {
 #define HCLGE_DEFAULT_TX_BUF		0x4000	 /* 16k  bytes */
 #define HCLGE_TOTAL_PKT_BUF		0x108000 /* 1.03125M bytes */
 #define HCLGE_DEFAULT_DV		0xA000	 /* 40k byte */
+#define HCLGE_DEFAULT_NON_DCB_DV	0x7800	/* 30K byte */
 #define HCLGE_TYPE_CRQ			0
 #define HCLGE_TYPE_CSQ			1

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c+105−79

@@ -46,17 +46,7 @@ static const struct pci_device_id ae_algo_pci_tbl[] = { · 45 unmodified lines
46	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},	46	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
47	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},	47	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
48	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},	48	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
49	/* Required last entry */	49	/* required last entry */
50	{0, }
51	};
52
53	static const struct pci_device_id roce_pci_tbl[] = {
54	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
55	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
56	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
57	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
58	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
59	/* Required last entry */
60	{0, }	50	{0, }
61	};	51	};
62		52
@@ -894,7 +884,7 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev) · 831 unmodified lines
894	hdev->num_tqps = __le16_to_cpu(req->tqp_num);	884	hdev->num_tqps = __le16_to_cpu(req->tqp_num);
895	hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;	885	hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
896		886
897	if (hnae_get_bit(hdev->ae_dev->flag, HNAE_DEV_SUPPORT_ROCE_B)) {	887	if (hnae3_dev_roce_supported(hdev)) {
898	hdev->num_roce_msix =	888	hdev->num_roce_msix =
899	hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),	889	hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
900	HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);	890	HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
@@ -1063,9 +1053,9 @@ static int hclge_configure(struct hclge_dev *hdev) · 162 unmodified lines
1063	hdev->base_tqp_pid = 0;	1053	hdev->base_tqp_pid = 0;
1064	hdev->rss_size_max = 1;	1054	hdev->rss_size_max = 1;
1065	hdev->rx_buf_len = cfg.rx_buf_len;	1055	hdev->rx_buf_len = cfg.rx_buf_len;
1066	for (i = 0; i < ETH_ALEN; i++)	1056	ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1067	hdev->hw.mac.mac_addr[i] = cfg.mac_addr[i];
1068	hdev->hw.mac.media_type = cfg.media_type;	1057	hdev->hw.mac.media_type = cfg.media_type;
		1058	hdev->hw.mac.phy_addr = cfg.phy_addr;
1069	hdev->num_desc = cfg.tqp_desc_num;	1059	hdev->num_desc = cfg.tqp_desc_num;
1070	hdev->tm_info.num_pg = 1;	1060	hdev->tm_info.num_pg = 1;
1071	hdev->tm_info.num_tc = cfg.tc_num;	1061	hdev->tm_info.num_tc = cfg.tc_num;
@@ -1454,7 +1444,11 @@ static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, u32 rx_all) · 382 unmodified lines
1454	tc_num = hclge_get_tc_num(hdev);	1444	tc_num = hclge_get_tc_num(hdev);
1455	pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);	1445	pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1456		1446
1457	shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;	1447	if (hnae3_dev_dcb_supported(hdev))
		1448	shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
		1449	else
		1450	shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
		1451
1458	shared_buf_tc = pfc_enable_num * hdev->mps +	1452	shared_buf_tc = pfc_enable_num * hdev->mps +
1459	(tc_num - pfc_enable_num) * hdev->mps / 2 +	1453	(tc_num - pfc_enable_num) * hdev->mps / 2 +
1460	hdev->mps;	1454	hdev->mps;
@@ -1495,6 +1489,16 @@ int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size) · 34 unmodified lines
1495	struct hclge_priv_buf *priv;	1489	struct hclge_priv_buf *priv;
1496	int i;	1490	int i;
1497		1491
		1492	/* When DCB is not supported, rx private
		1493	* buffer is not allocated.
		1494	*/
		1495	if (!hnae3_dev_dcb_supported(hdev)) {
		1496	if (!hclge_is_rx_buf_ok(hdev, rx_all))
		1497	return -ENOMEM;
		1498
		1499	return 0;
		1500	}
		1501
1498	/* step 1, try to alloc private buffer for all enabled tc */	1502	/* step 1, try to alloc private buffer for all enabled tc */
1499	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {	1503	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1500	priv = &hdev->priv_buf[i];	1504	priv = &hdev->priv_buf[i];
@@ -1510,6 +1514,11 @@ int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size) · 9 unmodified lines
1510	priv->wl.high = 2 * hdev->mps;	1514	priv->wl.high = 2 * hdev->mps;
1511	priv->buf_size = priv->wl.high;	1515	priv->buf_size = priv->wl.high;
1512	}	1516	}
		1517	} else {
		1518	priv->enable = 0;
		1519	priv->wl.low = 0;
		1520	priv->wl.high = 0;
		1521	priv->buf_size = 0;
1513	}	1522	}
1514	}	1523	}
1515		1524
@@ -1522,8 +1531,15 @@ int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size) · 6 unmodified lines
1522	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {	1531	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1523	priv = &hdev->priv_buf[i];	1532	priv = &hdev->priv_buf[i];
1524		1533
1525	if (hdev->hw_tc_map & BIT(i))	1534	priv->enable = 0;
1526	priv->enable = 1;	1535	priv->wl.low = 0;
		1536	priv->wl.high = 0;
		1537	priv->buf_size = 0;
		1538
		1539	if (!(hdev->hw_tc_map & BIT(i)))
		1540	continue;
		1541
		1542	priv->enable = 1;
1527		1543
1528	if (hdev->tm_info.hw_pfc_map & BIT(i)) {	1544	if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1529	priv->wl.low = 128;	1545	priv->wl.low = 128;
@@ -1616,6 +1632,10 @@ static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev) · 86 unmodified lines
1616	cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B);	1632	cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B);
1617	}	1633	}
1618		1634
		1635	req->shared_buf =
		1636	cpu_to_le16((hdev->s_buf.buf_size >> HCLGE_BUF_UNIT_S) \|
		1637	(1 << HCLGE_TC0_PRI_BUF_EN_B));
		1638
1619	ret = hclge_cmd_send(&hdev->hw, &desc, 1);	1639	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1620	if (ret) {	1640	if (ret) {
1621	dev_err(&hdev->pdev->dev,	1641	dev_err(&hdev->pdev->dev,
@@ -1782,18 +1802,22 @@ int hclge_buffer_alloc(struct hclge_dev *hdev) · 160 unmodified lines
1782	return ret;	1802	return ret;
1783	}	1803	}
1784		1804
1785	ret = hclge_rx_priv_wl_config(hdev);	1805	if (hnae3_dev_dcb_supported(hdev)) {
1786	if (ret) {	1806	ret = hclge_rx_priv_wl_config(hdev);
1787	dev_err(&hdev->pdev->dev,	1807	if (ret) {
1788	"could not configure rx private waterline %d\n", ret);	1808	dev_err(&hdev->pdev->dev,
1789	return ret;	1809	"could not configure rx private waterline %d\n",
1790	}	1810	ret);
		1811	return ret;
		1812	}
1791		1813
1792	ret = hclge_common_thrd_config(hdev);	1814	ret = hclge_common_thrd_config(hdev);
1793	if (ret) {	1815	if (ret) {
1794	dev_err(&hdev->pdev->dev,	1816	dev_err(&hdev->pdev->dev,
1795	"could not configure common threshold %d\n", ret);	1817	"could not configure common threshold %d\n",
1796	return ret;	1818	ret);
		1819	return ret;
		1820	}
1797	}	1821	}
1798		1822
1799	ret = hclge_common_wl_config(hdev);	1823	ret = hclge_common_wl_config(hdev);
@@ -2582,6 +2606,7 @@ static int hclge_rss_init_hw(struct hclge_dev *hdev) · 782 unmodified lines
2582	u16 tc_valid[HCLGE_MAX_TC_NUM];	2606	u16 tc_valid[HCLGE_MAX_TC_NUM];
2583	u16 tc_size[HCLGE_MAX_TC_NUM];	2607	u16 tc_size[HCLGE_MAX_TC_NUM];
2584	u32 *rss_indir = NULL;	2608	u32 *rss_indir = NULL;
		2609	u16 rss_size = 0, roundup_size;
2585	const u8 *key;	2610	const u8 *key;
2586	int i, ret, j;	2611	int i, ret, j;
2587		2612
@@ -2596,7 +2621,13 @@ static int hclge_rss_init_hw(struct hclge_dev *hdev) · 8 unmodified lines
2596	for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {	2621	for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
2597	for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {	2622	for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
2598	vport[j].rss_indirection_tbl[i] =	2623	vport[j].rss_indirection_tbl[i] =
2599	i % hdev->rss_size_max;	2624	i % vport[j].alloc_rss_size;
		2625
		2626	/* vport 0 is for PF */
		2627	if (j != 0)
		2628	continue;
		2629
		2630	rss_size = vport[j].alloc_rss_size;
2600	rss_indir[i] = vport[j].rss_indirection_tbl[i];	2631	rss_indir[i] = vport[j].rss_indirection_tbl[i];
2601	}	2632	}
2602	}	2633	}
@@ -2613,42 +2644,32 @@ static int hclge_rss_init_hw(struct hclge_dev *hdev) · 10 unmodified lines
2613	if (ret)	2644	if (ret)
2614	goto err;	2645	goto err;
2615		2646
		2647	/* Each TC have the same queue size, and tc_size set to hardware is
		2648	* the log2 of roundup power of two of rss_size, the acutal queue
		2649	* size is limited by indirection table.
		2650	*/
		2651	if (rss_size > HCLGE_RSS_TC_SIZE_7 \|\| rss_size == 0) {
		2652	dev_err(&hdev->pdev->dev,
		2653	"Configure rss tc size failed, invalid TC_SIZE = %d\n",
		2654	rss_size);
		2655	ret = -EINVAL;
		2656	goto err;
		2657	}
		2658
		2659	roundup_size = roundup_pow_of_two(rss_size);
		2660	roundup_size = ilog2(roundup_size);
		2661
2616	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {	2662	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2617	if (hdev->hw_tc_map & BIT(i))	2663	tc_valid[i] = 0;
2618	tc_valid[i] = 1;
2619	else
2620	tc_valid[i] = 0;
2621		2664
2622	switch (hdev->rss_size_max) {	2665	if (!(hdev->hw_tc_map & BIT(i)))
2623	case HCLGE_RSS_TC_SIZE_0:	2666	continue;
2624	tc_size[i] = 0;	2667
2625	break;	2668	tc_valid[i] = 1;
2626	case HCLGE_RSS_TC_SIZE_1:	2669	tc_size[i] = roundup_size;
2627	tc_size[i] = 1;	2670	tc_offset[i] = rss_size * i;
2628	break;
2629	case HCLGE_RSS_TC_SIZE_2:
2630	tc_size[i] = 2;
2631	break;
2632	case HCLGE_RSS_TC_SIZE_3:
2633	tc_size[i] = 3;
2634	break;
2635	case HCLGE_RSS_TC_SIZE_4:
2636	tc_size[i] = 4;
2637	break;
2638	case HCLGE_RSS_TC_SIZE_5:
2639	tc_size[i] = 5;
2640	break;
2641	case HCLGE_RSS_TC_SIZE_6:
2642	tc_size[i] = 6;
2643	break;
2644	case HCLGE_RSS_TC_SIZE_7:
2645	tc_size[i] = 7;
2646	break;
2647	default:
2648	break;
2649	}
2650	tc_offset[i] = hdev->rss_size_max * i;
2651	}	2671	}
		2672
2652	ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);	2673	ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
2653		2674
2654	err:	2675	err:
@@ -2679,7 +2700,11 @@ int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id, · 24 unmodified lines
2679	hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));	2700	hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2680	hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,	2701	hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2681	HCLGE_TQP_ID_S, node->tqp_index);	2702	HCLGE_TQP_ID_S, node->tqp_index);
		2703	hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
		2704	HCLGE_INT_GL_IDX_S,
		2705	hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2682	req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);	2706	req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
		2707	req->vfid = vport->vport_id;
2683		2708
2684	if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {	2709	if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2685	req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;	2710	req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
@@ -2763,8 +2788,12 @@ static int hclge_unmap_ring_from_vector( · 77 unmodified lines
2763	hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));	2788	hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2764	hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,	2789	hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2765	HCLGE_TQP_ID_S, node->tqp_index);	2790	HCLGE_TQP_ID_S, node->tqp_index);
		2791	hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
		2792	HCLGE_INT_GL_IDX_S,
		2793	hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2766		2794
2767	req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);	2795	req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
		2796	req->vfid = vport->vport_id;
2768		2797
2769	if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {	2798	if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2770	req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;	2799	req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
@@ -2778,7 +2807,7 @@ static int hclge_unmap_ring_from_vector( · 7 unmodified lines
2778	}	2807	}
2779	i = 0;	2808	i = 0;
2780	hclge_cmd_setup_basic_desc(&desc,	2809	hclge_cmd_setup_basic_desc(&desc,
2781	HCLGE_OPC_ADD_RING_TO_VECTOR,	2810	HCLGE_OPC_DEL_RING_TO_VECTOR,
2782	false);	2811	false);
2783	req->int_vector_id = vector_id;	2812	req->int_vector_id = vector_id;
2784	}	2813	}
@@ -3665,6 +3694,7 @@ static int hclge_init_vlan_config(struct hclge_dev *hdev) · 880 unmodified lines
3665	{	3694	{
3666	#define HCLGE_VLAN_TYPE_VF_TABLE 0	3695	#define HCLGE_VLAN_TYPE_VF_TABLE 0
3667	#define HCLGE_VLAN_TYPE_PORT_TABLE 1	3696	#define HCLGE_VLAN_TYPE_PORT_TABLE 1
		3697	struct hnae3_handle *handle;
3668	int ret;	3698	int ret;
3669		3699
3670	ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,	3700	ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
@@ -3674,8 +3704,11 @@ static int hclge_init_vlan_config(struct hclge_dev *hdev) · 3 unmodified lines
3674		3704
3675	ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,	3705	ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
3676	true);	3706	true);
		3707	if (ret)
		3708	return ret;
3677		3709
3678	return ret;	3710	handle = &hdev->vport[0].nic;
		3711	return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
3679	}	3712	}
3680		3713
3681	static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)	3714	static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
@@ -3920,8 +3953,7 @@ static int hclge_init_client_instance(struct hnae3_client *client, · 238 unmodified lines
3920	goto err;	3953	goto err;
3921		3954
3922	if (hdev->roce_client &&	3955	if (hdev->roce_client &&
3923	hnae_get_bit(hdev->ae_dev->flag,	3956	hnae3_dev_roce_supported(hdev)) {
3924	HNAE_DEV_SUPPORT_ROCE_B)) {
3925	struct hnae3_client *rc = hdev->roce_client;	3957	struct hnae3_client *rc = hdev->roce_client;
3926		3958
3927	ret = hclge_init_roce_base_info(vport);	3959	ret = hclge_init_roce_base_info(vport);
@@ -3944,8 +3976,7 @@ static int hclge_init_client_instance(struct hnae3_client *client, · 16 unmodified lines
3944		3976
3945	break;	3977	break;
3946	case HNAE3_CLIENT_ROCE:	3978	case HNAE3_CLIENT_ROCE:
3947	if (hnae_get_bit(hdev->ae_dev->flag,	3979	if (hnae3_dev_roce_supported(hdev)) {
3948	HNAE_DEV_SUPPORT_ROCE_B)) {
3949	hdev->roce_client = client;	3980	hdev->roce_client = client;
3950	vport->roce.client = client;	3981	vport->roce.client = client;
3951	}	3982	}
@@ -4057,7 +4088,6 @@ static void hclge_pci_uninit(struct hclge_dev *hdev) · 105 unmodified lines
4057	static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)	4088	static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4058	{	4089	{
4059	struct pci_dev *pdev = ae_dev->pdev;	4090	struct pci_dev *pdev = ae_dev->pdev;
4060	const struct pci_device_id *id;
4061	struct hclge_dev *hdev;	4091	struct hclge_dev *hdev;
4062	int ret;	4092	int ret;
4063		4093
@@ -4072,10 +4102,6 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) · 8 unmodified lines
4072	hdev->ae_dev = ae_dev;	4102	hdev->ae_dev = ae_dev;
4073	ae_dev->priv = hdev;	4103	ae_dev->priv = hdev;
4074		4104
4075	id = pci_match_id(roce_pci_tbl, ae_dev->pdev);
4076	if (id)
4077	hnae_set_bit(ae_dev->flag, HNAE_DEV_SUPPORT_ROCE_B, 1);
4078
4079	ret = hclge_pci_init(hdev);	4105	ret = hclge_pci_init(hdev);
4080	if (ret) {	4106	if (ret) {
4081	dev_err(&pdev->dev, "PCI init failed\n");	4107	dev_err(&pdev->dev, "PCI init failed\n");
@@ -4138,12 +4164,6 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) · 56 unmodified lines
4138	return ret;	4164	return ret;
4139	}	4165	}
4140		4166
4141	ret = hclge_rss_init_hw(hdev);
4142	if (ret) {
4143	dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4144	return ret;
4145	}
4146
4147	ret = hclge_init_vlan_config(hdev);	4167	ret = hclge_init_vlan_config(hdev);
4148	if (ret) {	4168	if (ret) {
4149	dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);	4169	dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
@@ -4156,6 +4176,12 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) · 6 unmodified lines
4156	return ret;	4176	return ret;
4157	}	4177	}
4158		4178
		4179	ret = hclge_rss_init_hw(hdev);
		4180	if (ret) {
		4181	dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
		4182	return ret;
		4183	}
		4184
4159	setup_timer(&hdev->service_timer, hclge_service_timer,	4185	setup_timer(&hdev->service_timer, hclge_service_timer,
4160	(unsigned long)hdev);	4186	(unsigned long)hdev);
4161	INIT_WORK(&hdev->service_task, hclge_service_task);	4187	INIT_WORK(&hdev->service_task, hclge_service_task);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h+2−1

 struct hclge_tc_info {
 	u8 tc_id;
 	u8 tc_sch_mode;		/* 0: sp; 1: dwrr */
-	u8 up;
 	u8 pgid;
 	u32 bw_limit;
 };
 	u8 num_tc;
 	u8 num_pg;      /* It must be 1 if vNET-Base schd */
 	u8 pg_dwrr[HCLGE_PG_NUM];
+	u8 prio_tc[HNAE3_MAX_USER_PRIO];
 	struct hclge_pg_info pg_info[HCLGE_PG_NUM];
 	struct hclge_tc_info tc_info[HNAE3_MAX_TC];
 	enum hclge_fc_mode fc_mode;
 	u8  rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
 	/* User configured lookup table entries */
 	u8  rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
+	u16 alloc_rss_size;
 	u16 qs_offset;
 	u16 bw_limit;		/* VSI BW Limit (0 = disabled) */

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c+24−17

 {
 	u8 tc;
-	for (tc = 0; tc < hdev->tm_info.num_tc; tc++)
+	tc = hdev->tm_info.prio_tc[pri_id];
-		if (hdev->tm_info.tc_info[tc].up == pri_id)
-			break;
 	if (tc >= hdev->tm_info.num_tc)
 		return -EINVAL;
 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false);
-	for (pri_id = 0; pri_id < hdev->tm_info.num_tc; pri_id++) {
+	for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) {
 		ret = hclge_fill_pri_array(hdev, pri, pri_id);
 		if (ret)
 			return ret;
 	shap_cfg_cmd->pg_id = pg_id;
-	hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_B, ir_b);
+	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_B, ir_b);
-	hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_U, ir_u);
+	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_U, ir_u);
-	hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_S, ir_s);
+	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_S, ir_s);
-	hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, BS_B, bs_b);
+	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_B, bs_b);
-	hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, BS_S, bs_s);
+	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_S, bs_s);
 	return hclge_cmd_send(&hdev->hw, &desc, 1);
 }
 	shap_cfg_cmd->pri_id = pri_id;
-	hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_B, ir_b);
+	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_B, ir_b);
-	hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_U, ir_u);
+	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_U, ir_u);
-	hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_S, ir_s);
+	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_S, ir_s);
-	hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, BS_B, bs_b);
+	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_B, bs_b);
-	hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, BS_S, bs_s);
+	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_S, bs_s);
 	return hclge_cmd_send(&hdev->hw, &desc, 1);
 }
 			kinfo->num_tqps / kinfo->num_tc);
 	vport->qs_offset = hdev->tm_info.num_tc * vport->vport_id;
 	vport->dwrr = 100;  /* 100 percent as init */
+	vport->alloc_rss_size = kinfo->rss_size;
 	for (i = 0; i < kinfo->num_tc; i++) {
 		if (hdev->hw_tc_map & BIT(i)) {
 			kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
 			kinfo->tc_info[i].tqp_count = kinfo->rss_size;
 			kinfo->tc_info[i].tc = i;
-			kinfo->tc_info[i].up = hdev->tm_info.tc_info[i].up;
 		} else {
 			/* Set to default queue if TC is disable */
 			kinfo->tc_info[i].enable = false;
 			kinfo->tc_info[i].tqp_offset = 0;
 			kinfo->tc_info[i].tqp_count = 1;
 			kinfo->tc_info[i].tc = 0;
-			kinfo->tc_info[i].up = 0;
 		}
 	}
+	memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc,
+	       FIELD_SIZEOF(struct hnae3_knic_private_info, prio_tc));
 }
 static void hclge_tm_vport_info_update(struct hclge_dev *hdev)
 	for (i = 0; i < hdev->tm_info.num_tc; i++) {
 		hdev->tm_info.tc_info[i].tc_id = i;
 		hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR;
-		hdev->tm_info.tc_info[i].up = i;
 		hdev->tm_info.tc_info[i].pgid = 0;
 		hdev->tm_info.tc_info[i].bw_limit =
 			hdev->tm_info.pg_info[0].bw_limit;
 	}
+	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
+		hdev->tm_info.prio_tc[i] =
+			(i >= hdev->tm_info.num_tc) ? 0 : i;
 	hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
 }
 	if (ret)
 		return ret;
+	/* Only DCB-supported dev supports qset back pressure setting */
+	if (!hnae3_dev_dcb_supported(hdev))
+		return 0;
 	for (i = 0; i < hdev->tm_info.num_tc; i++) {
 		ret = hclge_tm_qs_bp_cfg(hdev, i);
 		if (ret)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h+2−2

@@ -94,10 +94,10 @@ struct hclge_bp_to_qs_map_cmd { · 93 unmodified lines
94	u32 rsvd1;	94	u32 rsvd1;
95	};	95	};
96		96
97	#define hclge_tm_set_feild(dest, string, val) \	97	#define hclge_tm_set_field(dest, string, val) \
98	hnae_set_field((dest), (HCLGE_TM_SHAP_##string##_MSK), \	98	hnae_set_field((dest), (HCLGE_TM_SHAP_##string##_MSK), \
99	(HCLGE_TM_SHAP_##string##_LSH), val)	99	(HCLGE_TM_SHAP_##string##_LSH), val)
100	#define hclge_tm_get_feild(src, string) \	100	#define hclge_tm_get_field(src, string) \
101	hnae_get_field((src), (HCLGE_TM_SHAP_##string##_MSK), \	101	hnae_get_field((src), (HCLGE_TM_SHAP_##string##_MSK), \
102	(HCLGE_TM_SHAP_##string##_LSH))	102	(HCLGE_TM_SHAP_##string##_LSH))
103		103

drivers/net/ethernet/hisilicon/hns3/hns3pf/hns3_enet.c+15−8

 static const struct pci_device_id hns3_pci_tbl[] = {
 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
-	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
+	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
-	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
+	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
-	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
+	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
-	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
+	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
-	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
+	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
+	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
+	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
+	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
+	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
+	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
 	/* required last entry */
 	{0, }
 };
 	}
 	ae_dev->pdev = pdev;
+	ae_dev->flag = ent->driver_data;
 	ae_dev->dev_type = HNAE3_DEV_KNIC;
 	pci_set_drvdata(pdev, ae_dev);
 		eth_hw_addr_random(netdev);
 		dev_warn(priv->dev, "using random MAC address %pM\n",
 			 netdev->dev_addr);
-		/* Also copy this new MAC address into hdev */
-		if (h->ae_algo->ops->set_mac_addr)
-			h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr);
 	}
+	if (h->ae_algo->ops->set_mac_addr)
+		h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr);
 }
 static void hns3_nic_set_priv_ops(struct net_device *netdev)

drivers/net/ethernet/ibm/emac/mal.c+1−2

@@ -402,7 +402,7 @@ static int mal_poll(struct napi_struct *napi, int budget) · 401 unmodified lines
402	unsigned long flags;	402	unsigned long flags;
403		403
404	MAL_DBG2(mal, "poll(%d)" NL, budget);	404	MAL_DBG2(mal, "poll(%d)" NL, budget);
405	again:	405
406	/* Process TX skbs */	406	/* Process TX skbs */
407	list_for_each(l, &mal->poll_list) {	407	list_for_each(l, &mal->poll_list) {
408	struct mal_commac *mc =	408	struct mal_commac *mc =
@@ -451,7 +451,6 @@ static int mal_poll(struct napi_struct *napi, int budget) · 42 unmodified lines
451	spin_lock_irqsave(&mal->lock, flags);	451	spin_lock_irqsave(&mal->lock, flags);
452	mal_disable_eob_irq(mal);	452	mal_disable_eob_irq(mal);
453	spin_unlock_irqrestore(&mal->lock, flags);	453	spin_unlock_irqrestore(&mal->lock, flags);
454	goto again;
455	}	454	}
456	mc->ops->poll_tx(mc->dev);	455	mc->ops->poll_tx(mc->dev);
457	}	456	}

drivers/net/ethernet/marvell/mvpp2.c+35−11

@@ -333,7 +333,7 @@ · 332 unmodified lines
333	#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)	333	#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
334	#define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1)	334	#define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1)
335	#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)	335	#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
336	#define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)	336	#define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4)
337	#define MVPP2_GMAC_DISABLE_PADDING BIT(5)	337	#define MVPP2_GMAC_DISABLE_PADDING BIT(5)
338	#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)	338	#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
339	#define MVPP2_GMAC_AUTONEG_CONFIG 0xc	339	#define MVPP2_GMAC_AUTONEG_CONFIG 0xc
@@ -676,6 +676,7 @@ enum mvpp2_tag_type { · 336 unmodified lines
676	#define MVPP2_PRS_RI_L3_MCAST BIT(15)	676	#define MVPP2_PRS_RI_L3_MCAST BIT(15)
677	#define MVPP2_PRS_RI_L3_BCAST (BIT(15) \| BIT(16))	677	#define MVPP2_PRS_RI_L3_BCAST (BIT(15) \| BIT(16))
678	#define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000	678	#define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
		679	#define MVPP2_PRS_RI_IP_FRAG_TRUE BIT(17)
679	#define MVPP2_PRS_RI_UDF3_MASK 0x300000	680	#define MVPP2_PRS_RI_UDF3_MASK 0x300000
680	#define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)	681	#define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
681	#define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000	682	#define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
@@ -792,6 +793,7 @@ struct mvpp2 { · 110 unmodified lines
792	struct clk *pp_clk;	793	struct clk *pp_clk;
793	struct clk *gop_clk;	794	struct clk *gop_clk;
794	struct clk *mg_clk;	795	struct clk *mg_clk;
		796	struct clk *axi_clk;
795		797
796	/* List of pointers to port structures */	798	/* List of pointers to port structures */
797	struct mvpp2_port **port_list;	799	struct mvpp2_port **port_list;
@@ -2315,7 +2317,7 @@ static int mvpp2_prs_ip4_proto(struct mvpp2 *priv, unsigned short proto, · 1517 unmodified lines
2315	(proto != IPPROTO_IGMP))	2317	(proto != IPPROTO_IGMP))
2316	return -EINVAL;	2318	return -EINVAL;
2317		2319
2318	/* Fragmented packet */	2320	/* Not fragmented packet */
2319	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,	2321	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2320	MVPP2_PE_LAST_FREE_TID);	2322	MVPP2_PE_LAST_FREE_TID);
2321	if (tid < 0)	2323	if (tid < 0)
@@ -2334,8 +2336,12 @@ static int mvpp2_prs_ip4_proto(struct mvpp2 *priv, unsigned short proto, · 12 unmodified lines
2334	MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);	2336	MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2335	mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,	2337	mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
2336	MVPP2_PRS_IPV4_DIP_AI_BIT);	2338	MVPP2_PRS_IPV4_DIP_AI_BIT);
2337	mvpp2_prs_sram_ri_update(&pe, ri \| MVPP2_PRS_RI_IP_FRAG_MASK,	2339	mvpp2_prs_sram_ri_update(&pe, ri, ri_mask \| MVPP2_PRS_RI_IP_FRAG_MASK);
2338	ri_mask \| MVPP2_PRS_RI_IP_FRAG_MASK);	2340
		2341	mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00,
		2342	MVPP2_PRS_TCAM_PROTO_MASK_L);
		2343	mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00,
		2344	MVPP2_PRS_TCAM_PROTO_MASK);
2339		2345
2340	mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK);	2346	mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK);
2341	mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);	2347	mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
@@ -2346,7 +2352,7 @@ static int mvpp2_prs_ip4_proto(struct mvpp2 *priv, unsigned short proto, · 4 unmodified lines
2346	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);	2352	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2347	mvpp2_prs_hw_write(priv, &pe);	2353	mvpp2_prs_hw_write(priv, &pe);
2348		2354
2349	/* Not fragmented packet */	2355	/* Fragmented packet */
2350	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,	2356	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2351	MVPP2_PE_LAST_FREE_TID);	2357	MVPP2_PE_LAST_FREE_TID);
2352	if (tid < 0)	2358	if (tid < 0)
@@ -2358,8 +2364,11 @@ static int mvpp2_prs_ip4_proto(struct mvpp2 *priv, unsigned short proto, · 5 unmodified lines
2358	pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;	2364	pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2359	mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);	2365	mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
2360		2366
2361	mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, MVPP2_PRS_TCAM_PROTO_MASK_L);	2367	mvpp2_prs_sram_ri_update(&pe, ri \| MVPP2_PRS_RI_IP_FRAG_TRUE,
2362	mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, MVPP2_PRS_TCAM_PROTO_MASK);	2368	ri_mask \| MVPP2_PRS_RI_IP_FRAG_MASK);
		2369
		2370	mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0);
		2371	mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0);
2363		2372
2364	/* Update shadow table and hw entry */	2373	/* Update shadow table and hw entry */
2365	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);	2374	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
@@ -4591,7 +4600,6 @@ static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port) · 2225 unmodified lines
4591	val \|= MVPP2_GMAC_INBAND_AN_MASK \| MVPP2_GMAC_PCS_ENABLE_MASK;	4600	val \|= MVPP2_GMAC_INBAND_AN_MASK \| MVPP2_GMAC_PCS_ENABLE_MASK;
4592	} else if (phy_interface_mode_is_rgmii(port->phy_interface)) {	4601	} else if (phy_interface_mode_is_rgmii(port->phy_interface)) {
4593	val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;	4602	val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
4594	val \|= MVPP2_GMAC_PORT_RGMII_MASK;
4595	}	4603	}
4596	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);	4604	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
4597		4605
@@ -7496,7 +7504,7 @@ static void mvpp2_port_copy_mac_addr(struct net_device dev, struct mvpp2 priv, · 2898 unmodified lines
7496	/* Ports initialization */	7504	/* Ports initialization */
7497	static int mvpp2_port_probe(struct platform_device *pdev,	7505	static int mvpp2_port_probe(struct platform_device *pdev,
7498	struct device_node *port_node,	7506	struct device_node *port_node,
7499	struct mvpp2 *priv)	7507	struct mvpp2 *priv, int index)
7500	{	7508	{
7501	struct device_node *phy_node;	7509	struct device_node *phy_node;
7502	struct phy *comphy;	7510	struct phy *comphy;
@@ -7670,7 +7678,7 @@ static int mvpp2_port_probe(struct platform_device *pdev, · 167 unmodified lines
7670	}	7678	}
7671	netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);	7679	netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
7672		7680
7673	priv->port_list[id] = port;	7681	priv->port_list[index] = port;
7674	return 0;	7682	return 0;
7675		7683
7676	err_free_port_pcpu:	7684	err_free_port_pcpu:
@@ -7963,6 +7971,18 @@ static int mvpp2_probe(struct platform_device *pdev) · 286 unmodified lines
7963	err = clk_prepare_enable(priv->mg_clk);	7971	err = clk_prepare_enable(priv->mg_clk);
7964	if (err < 0)	7972	if (err < 0)
7965	goto err_gop_clk;	7973	goto err_gop_clk;
		7974
		7975	priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
		7976	if (IS_ERR(priv->axi_clk)) {
		7977	err = PTR_ERR(priv->axi_clk);
		7978	if (err == -EPROBE_DEFER)
		7979	goto err_gop_clk;
		7980	priv->axi_clk = NULL;
		7981	} else {
		7982	err = clk_prepare_enable(priv->axi_clk);
		7983	if (err < 0)
		7984	goto err_gop_clk;
		7985	}
7966	}	7986	}
7967		7987
7968	/* Get system's tclk rate */	7988	/* Get system's tclk rate */
@@ -8005,16 +8025,19 @@ static int mvpp2_probe(struct platform_device *pdev) · 36 unmodified lines
8005	}	8025	}
8006		8026
8007	/* Initialize ports */	8027	/* Initialize ports */
		8028	i = 0;
8008	for_each_available_child_of_node(dn, port_node) {	8029	for_each_available_child_of_node(dn, port_node) {
8009	err = mvpp2_port_probe(pdev, port_node, priv);	8030	err = mvpp2_port_probe(pdev, port_node, priv, i);
8010	if (err < 0)	8031	if (err < 0)
8011	goto err_mg_clk;	8032	goto err_mg_clk;
		8033	i++;
8012	}	8034	}
8013		8035
8014	platform_set_drvdata(pdev, priv);	8036	platform_set_drvdata(pdev, priv);
8015	return 0;	8037	return 0;
8016		8038
8017	err_mg_clk:	8039	err_mg_clk:
		8040	clk_disable_unprepare(priv->axi_clk);
8018	if (priv->hw_version == MVPP22)	8041	if (priv->hw_version == MVPP22)
8019	clk_disable_unprepare(priv->mg_clk);	8042	clk_disable_unprepare(priv->mg_clk);
8020	err_gop_clk:	8043	err_gop_clk:
@@ -8052,6 +8075,7 @@ static int mvpp2_remove(struct platform_device *pdev) · 31 unmodified lines
8052	aggr_txq->descs_dma);	8075	aggr_txq->descs_dma);
8053	}	8076	}
8054		8077
		8078	clk_disable_unprepare(priv->axi_clk);
8055	clk_disable_unprepare(priv->mg_clk);	8079	clk_disable_unprepare(priv->mg_clk);
8056	clk_disable_unprepare(priv->pp_clk);	8080	clk_disable_unprepare(priv->pp_clk);
8057	clk_disable_unprepare(priv->gop_clk);	8081	clk_disable_unprepare(priv->gop_clk);

drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h+2−2

@@ -139,7 +139,7 @@ TRACE_EVENT(mlx5_fs_del_fg, · 138 unmodified lines
139	{MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO, "NEXT_PRIO"}	139	{MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO, "NEXT_PRIO"}
140		140
141	TRACE_EVENT(mlx5_fs_set_fte,	141	TRACE_EVENT(mlx5_fs_set_fte,
142	TP_PROTO(const struct fs_fte *fte, bool new_fte),	142	TP_PROTO(const struct fs_fte *fte, int new_fte),
143	TP_ARGS(fte, new_fte),	143	TP_ARGS(fte, new_fte),
144	TP_STRUCT__entry(	144	TP_STRUCT__entry(
145	__field(const struct fs_fte *, fte)	145	__field(const struct fs_fte *, fte)
@@ -149,7 +149,7 @@ TRACE_EVENT(mlx5_fs_set_fte, · 3 unmodified lines
149	__field(u32, action)	149	__field(u32, action)
150	__field(u32, flow_tag)	150	__field(u32, flow_tag)
151	__field(u8, mask_enable)	151	__field(u8, mask_enable)
152	__field(bool, new_fte)	152	__field(int, new_fte)
153	__array(u32, mask_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))	153	__array(u32, mask_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
154	__array(u32, mask_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))	154	__array(u32, mask_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
155	__array(u32, mask_misc, MLX5_ST_SZ_DW(fte_match_set_misc))	155	__array(u32, mask_misc, MLX5_ST_SZ_DW(fte_match_set_misc))

drivers/net/ethernet/mellanox/mlx5/core/en_fs.c+2−2

@@ -291,7 +291,7 @@ void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv) · 290 unmodified lines
291	priv->fs.vlan.filter_disabled = false;	291	priv->fs.vlan.filter_disabled = false;
292	if (priv->netdev->flags & IFF_PROMISC)	292	if (priv->netdev->flags & IFF_PROMISC)
293	return;	293	return;
294	mlx5e_del_any_vid_rules(priv);	294	mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_ANY_CTAG_VID, 0);
295	}	295	}
296		296
297	void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv)	297	void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv)
@@ -302,7 +302,7 @@ void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv) · 4 unmodified lines
302	priv->fs.vlan.filter_disabled = true;	302	priv->fs.vlan.filter_disabled = true;
303	if (priv->netdev->flags & IFF_PROMISC)	303	if (priv->netdev->flags & IFF_PROMISC)
304	return;	304	return;
305	mlx5e_add_any_vid_rules(priv);	305	mlx5e_add_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_ANY_CTAG_VID, 0);
306	}	306	}
307		307
308	int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,	308	int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,

drivers/net/ethernet/mellanox/mlx5/core/en_main.c+5−8

 	struct mlx5e_sw_stats temp, *s = &temp;
 	struct mlx5e_rq_stats *rq_stats;
 	struct mlx5e_sq_stats *sq_stats;
-	u64 tx_offload_none = 0;
 	int i, j;
 	memset(s, 0, sizeof(*s));
 		s->rx_lro_bytes	+= rq_stats->lro_bytes;
 		s->rx_csum_none	+= rq_stats->csum_none;
 		s->rx_csum_complete += rq_stats->csum_complete;
+		s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
 		s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 		s->rx_xdp_drop += rq_stats->xdp_drop;
 		s->rx_xdp_tx += rq_stats->xdp_tx;
 			s->tx_queue_dropped	+= sq_stats->dropped;
 			s->tx_xmit_more		+= sq_stats->xmit_more;
 			s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
-			tx_offload_none		+= sq_stats->csum_none;
+			s->tx_csum_none		+= sq_stats->csum_none;
+			s->tx_csum_partial	+= sq_stats->csum_partial;
 		}
 	}
-	/* Update calculated offload counters */
-	s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
-	s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 	s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 				priv->stats.pport.phy_counters,
 				counter_set.phys_layer_cntrs.link_down_events);
 	err = feature_handler(netdev, enable);
 	if (err) {
-		netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
+		netdev_err(netdev, "%s feature %pNF failed, err %d\n",
-			   enable ? "Enable" : "Disable", feature, err);
+			   enable ? "Enable" : "Disable", &feature, err);
 		return err;
 	}

drivers/net/ethernet/mellanox/mlx5/core/en_rx.c+3−0

 	if (lro) {
 		skb->ip_summed = CHECKSUM_UNNECESSARY;
+		rq->stats.csum_unnecessary++;
 		return;
 	}
 			skb->csum_level = 1;
 			skb->encapsulation = 1;
 			rq->stats.csum_unnecessary_inner++;
+			return;
 		}
+		rq->stats.csum_unnecessary++;
 		return;
 	}
 csum_none:

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h+6−0

 	u64 rx_xdp_drop;
 	u64 rx_xdp_tx;
 	u64 rx_xdp_tx_full;
+	u64 tx_csum_none;
 	u64 tx_csum_partial;
 	u64 tx_csum_partial_inner;
 	u64 tx_queue_stopped;
 	{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
 	{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx) },
 	{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
+	{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
 	{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
 	{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
 	{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
 	u64 packets;
 	u64 bytes;
 	u64 csum_complete;
+	u64 csum_unnecessary;
 	u64 csum_unnecessary_inner;
 	u64 csum_none;
 	u64 lro_packets;
 	{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
 	{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
 	{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
+	{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
 	{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
 	{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
 	{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
 	u64 tso_bytes;
 	u64 tso_inner_packets;
 	u64 tso_inner_bytes;
+	u64 csum_partial;
 	u64 csum_partial_inner;
 	u64 nop;
 	/* less likely accessed in data path */
 	{ MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
 	{ MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
 	{ MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
+	{ MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
 	{ MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
 	{ MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
 	{ MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c+83−8

 	return true;
 }
+static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
+					  struct tcf_exts *exts)
+{
+	const struct tc_action *a;
+	bool modify_ip_header;
+	LIST_HEAD(actions);
+	u8 htype, ip_proto;
+	void *headers_v;
+	u16 ethertype;
+	int nkeys, i;
+	headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
+	ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
+	/* for non-IP we only re-write MACs, so we're okay */
+	if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
+		goto out_ok;
+	modify_ip_header = false;
+	tcf_exts_to_list(exts, &actions);
+	list_for_each_entry(a, &actions, list) {
+		if (!is_tcf_pedit(a))
+			continue;
+		nkeys = tcf_pedit_nkeys(a);
+		for (i = 0; i < nkeys; i++) {
+			htype = tcf_pedit_htype(a, i);
+			if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
+			    htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
+				modify_ip_header = true;
+				break;
+			}
+		}
+	}
+	ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
+	if (modify_ip_header && ip_proto != IPPROTO_TCP && ip_proto != IPPROTO_UDP) {
+		pr_info("can't offload re-write of ip proto %d\n", ip_proto);
+		return false;
+	}
+out_ok:
+	return true;
+}
+static bool actions_match_supported(struct mlx5e_priv *priv,
+				    struct tcf_exts *exts,
+				    struct mlx5e_tc_flow_parse_attr *parse_attr,
+				    struct mlx5e_tc_flow *flow)
+{
+	u32 actions;
+	if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
+		actions = flow->esw_attr->action;
+	else
+		actions = flow->nic_attr->action;
+	if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
+		return modify_header_match_supported(&parse_attr->spec, exts);
+	return true;
+}
 static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
 				struct mlx5e_tc_flow_parse_attr *parse_attr,
 				struct mlx5e_tc_flow *flow)
 		return -EINVAL;
 	}
+	if (!actions_match_supported(priv, exts, parse_attr, flow))
+		return -EOPNOTSUPP;
 	return 0;
 }
 		break;
 	default:
 		err = -EOPNOTSUPP;
-		goto out;
+		goto free_encap;
 	}
 	fl4.flowi4_tos = tun_key->tos;
 	fl4.daddr = tun_key->u.ipv4.dst;
 	err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
 				      &fl4, &n, &ttl);
 	if (err)
-		goto out;
+		goto free_encap;
 	/* used by mlx5e_detach_encap to lookup a neigh hash table
 	 * entry in the neigh hash table when a user deletes a rule
 	 */
 	err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
 	if (err)
-		goto out;
+		goto free_encap;
 	read_lock_bh(&n->lock);
 	nud_state = n->nud_state;
 destroy_neigh_entry:
 	mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
-out:
+free_encap:
 	kfree(encap_header);
+out:
 	if (n)
 		neigh_release(n);
 	return err;
 		break;
 	default:
 		err = -EOPNOTSUPP;
-		goto out;
+		goto free_encap;
 	}
 	fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
 	err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
 				      &fl6, &n, &ttl);
 	if (err)
-		goto out;
+		goto free_encap;
 	/* used by mlx5e_detach_encap to lookup a neigh hash table
 	 * entry in the neigh hash table when a user deletes a rule
 	 */
 	err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
 	if (err)
-		goto out;
+		goto free_encap;
 	read_lock_bh(&n->lock);
 	nud_state = n->nud_state;
 destroy_neigh_entry:
 	mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
-out:
+free_encap:
 	kfree(encap_header);
+out:
 	if (n)
 		neigh_release(n);
 	return err;
 		}
 	}
+	/* must verify if encap is valid or not */
 	if (found)
 		goto attach_flow;
 	*encap_dev = e->out_dev;
 	if (e->flags & MLX5_ENCAP_ENTRY_VALID)
 		attr->encap_id = e->encap_id;
+	else
+		err = -EAGAIN;
 	return err;
 		return -EINVAL;
 	}
+	if (!actions_match_supported(priv, exts, parse_attr, flow))
+		return -EOPNOTSUPP;
 	return err;
 }

drivers/net/ethernet/mellanox/mlx5/core/en_tx.c+1−0

@@ -193,6 +193,7 @@ mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq sq, struct sk_buff skb, struct · 192 unmodified lines
193	sq->stats.csum_partial_inner++;	193	sq->stats.csum_partial_inner++;
194	} else {	194	} else {
195	eseg->cs_flags \|= MLX5_ETH_WQE_L4_CSUM;	195	eseg->cs_flags \|= MLX5_ETH_WQE_L4_CSUM;
		196	sq->stats.csum_partial++;
196	}	197	}
197	} else	198	} else
198	sq->stats.csum_none++;	199	sq->stats.csum_none++;

drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.c+2−2

@@ -71,11 +71,11 @@ int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr, · 70 unmodified lines
71	return 0;	71	return 0;
72	}	72	}
73		73
74	int mlx5_fpga_caps(struct mlx5_core_dev dev, u32 caps)	74	int mlx5_fpga_caps(struct mlx5_core_dev *dev)
75	{	75	{
76	u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};	76	u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
77		77
78	return mlx5_core_access_reg(dev, in, sizeof(in), caps,	78	return mlx5_core_access_reg(dev, in, sizeof(in), dev->caps.fpga,
79	MLX5_ST_SZ_BYTES(fpga_cap),	79	MLX5_ST_SZ_BYTES(fpga_cap),
80	MLX5_REG_FPGA_CAP, 0, 0);	80	MLX5_REG_FPGA_CAP, 0, 0);
81	}	81	}

drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h+1−1

@@ -65,7 +65,7 @@ struct mlx5_fpga_qp_counters { · 64 unmodified lines
65	u64 rx_total_drop;	65	u64 rx_total_drop;
66	};	66	};
67		67
68	int mlx5_fpga_caps(struct mlx5_core_dev dev, u32 caps);	68	int mlx5_fpga_caps(struct mlx5_core_dev *dev);
69	int mlx5_fpga_query(struct mlx5_core_dev dev, struct mlx5_fpga_query query);	69	int mlx5_fpga_query(struct mlx5_core_dev dev, struct mlx5_fpga_query query);
70	int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);	70	int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
71	int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,	71	int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,

drivers/net/ethernet/mellanox/mlx5/core/fpga/core.c+1−2

@@ -139,8 +139,7 @@ int mlx5_fpga_device_start(struct mlx5_core_dev *mdev) · 138 unmodified lines
139	if (err)	139	if (err)
140	goto out;	140	goto out;
141		141
142	err = mlx5_fpga_caps(fdev->mdev,	142	err = mlx5_fpga_caps(fdev->mdev);
143	fdev->mdev->caps.hca_cur[MLX5_CAP_FPGA]);
144	if (err)	143	if (err)
145	goto out;	144	goto out;
146		145

drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c+8−0

 	}
 	if (fte->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
+		int max_list_size = BIT(MLX5_CAP_FLOWTABLE_TYPE(dev,
+					log_max_flow_counter,
+					ft->type));
 		int list_size = 0;
 		list_for_each_entry(dst, &fte->node.children, node.list) {
 			in_dests += MLX5_ST_SZ_BYTES(dest_format_struct);
 			list_size++;
 		}
+		if (list_size > max_list_size) {
+			err = -EINVAL;
+			goto err_out;
+		}
 		MLX5_SET(flow_context, in_flow_context, flow_counter_list_size,
 			 list_size);
 	}
 	err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
+err_out:
 	kvfree(in);
 	return err;
 }

drivers/net/ethernet/mellanox/mlx5/core/fs_core.h+11−0

@@ -52,6 +52,7 @@ enum fs_flow_table_type { · 51 unmodified lines
52	FS_FT_FDB = 0X4,	52	FS_FT_FDB = 0X4,
53	FS_FT_SNIFFER_RX = 0X5,	53	FS_FT_SNIFFER_RX = 0X5,
54	FS_FT_SNIFFER_TX = 0X6,	54	FS_FT_SNIFFER_TX = 0X6,
		55	FS_FT_MAX_TYPE = FS_FT_SNIFFER_TX,
55	};	56	};
56		57
57	enum fs_flow_table_op_mod {	58	enum fs_flow_table_op_mod {
@@ -260,4 +261,14 @@ void mlx5_cleanup_fs(struct mlx5_core_dev *dev); · 202 unmodified lines
260	#define fs_for_each_dst(pos, fte) \	261	#define fs_for_each_dst(pos, fte) \
261	fs_list_for_each_entry(pos, &(fte)->node.children)	262	fs_list_for_each_entry(pos, &(fte)->node.children)
262		263
		264	#define MLX5_CAP_FLOWTABLE_TYPE(mdev, cap, type) ( \
		265	(type == FS_FT_NIC_RX) ? MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) : \
		266	(type == FS_FT_ESW_EGRESS_ACL) ? MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) : \
		267	(type == FS_FT_ESW_INGRESS_ACL) ? MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) : \
		268	(type == FS_FT_FDB) ? MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) : \
		269	(type == FS_FT_SNIFFER_RX) ? MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) : \
		270	(type == FS_FT_SNIFFER_TX) ? MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) : \
		271	(BUILD_BUG_ON_ZERO(FS_FT_SNIFFER_TX != FS_FT_MAX_TYPE))\
		272	)
		273
263	#endif	274	#endif

drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c+2−1

 {
 	struct mlx5e_priv          *priv    = mlx5i_epriv(netdev);
 	const struct mlx5e_profile *profile = priv->profile;
+	struct mlx5_core_dev       *mdev    = priv->mdev;
 	mlx5e_detach_netdev(priv);
 	profile->cleanup(priv);
 	destroy_workqueue(priv->wq);
 	free_netdev(netdev);
-	mlx5e_destroy_mdev_resources(priv->mdev);
+	mlx5e_destroy_mdev_resources(mdev);
 }
 EXPORT_SYMBOL(mlx5_rdma_netdev_free);

drivers/net/ethernet/mellanox/mlx5/core/sriov.c+1−1

@@ -109,7 +109,7 @@ static int mlx5_device_enable_sriov(struct mlx5_core_dev *dev, int num_vfs) · 108 unmodified lines
109	mlx5_core_warn(dev,	109	mlx5_core_warn(dev,
110	"failed to restore VF %d settings, err %d\n",	110	"failed to restore VF %d settings, err %d\n",
111	vf, err);	111	vf, err);
112	continue;	112	continue;
113	}	113	}
114	}	114	}
115	mlx5_core_dbg(dev, "successfully enabled VF* %d\n", vf);	115	mlx5_core_dbg(dev, "successfully enabled VF* %d\n", vf);

drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c+14−4

 		mlxsw_sp_nexthop_rif_fini(nh);
 		break;
 	case MLXSW_SP_NEXTHOP_TYPE_IPIP:
+		mlxsw_sp_nexthop_rif_fini(nh);
 		mlxsw_sp_nexthop_ipip_fini(mlxsw_sp, nh);
 		break;
 	}
 	    router->ipip_ops_arr[ipipt]->can_offload(mlxsw_sp, dev,
 						     MLXSW_SP_L3_PROTO_IPV4)) {
 		nh->type = MLXSW_SP_NEXTHOP_TYPE_IPIP;
-		return mlxsw_sp_nexthop_ipip_init(mlxsw_sp, ipipt, nh, dev);
+		err = mlxsw_sp_nexthop_ipip_init(mlxsw_sp, ipipt, nh, dev);
+		if (err)
+			return err;
+		mlxsw_sp_nexthop_rif_init(nh, &nh->ipip_entry->ol_lb->common);
+		return 0;
 	}
 	nh->type = MLXSW_SP_NEXTHOP_TYPE_ETH;
 	    router->ipip_ops_arr[ipipt]->can_offload(mlxsw_sp, dev,
 						     MLXSW_SP_L3_PROTO_IPV6)) {
 		nh->type = MLXSW_SP_NEXTHOP_TYPE_IPIP;
-		return mlxsw_sp_nexthop_ipip_init(mlxsw_sp, ipipt, nh, dev);
+		err = mlxsw_sp_nexthop_ipip_init(mlxsw_sp, ipipt, nh, dev);
+		if (err)
+			return err;
+		mlxsw_sp_nexthop_rif_init(nh, &nh->ipip_entry->ol_lb->common);
+		return 0;
 	}
 	nh->type = MLXSW_SP_NEXTHOP_TYPE_ETH;
 	vr = mlxsw_sp_vr_get(mlxsw_sp, tb_id ? : RT_TABLE_MAIN);
 	if (IS_ERR(vr))
 		return ERR_CAST(vr);
+	vr->rif_count++;
 	err = mlxsw_sp_rif_index_alloc(mlxsw_sp, &rif_index);
 	if (err)
 	mlxsw_sp_rif_counters_alloc(rif);
 	mlxsw_sp->router->rifs[rif_index] = rif;
-	vr->rif_count++;
 	return rif;
 	kfree(rif);
 err_rif_alloc:
 err_rif_index_alloc:
+	vr->rif_count--;
 	mlxsw_sp_vr_put(vr);
 	return ERR_PTR(err);
 }
 	mlxsw_sp_router_rif_gone_sync(mlxsw_sp, rif);
 	vr = &mlxsw_sp->router->vrs[rif->vr_id];
-	vr->rif_count--;
 	mlxsw_sp->router->rifs[rif->rif_index] = NULL;
 	mlxsw_sp_rif_counters_free(rif);
 	ops->deconfigure(rif);
 		/* Loopback RIFs are not associated with a FID. */
 		mlxsw_sp_fid_put(fid);
 	kfree(rif);
+	vr->rif_count--;
 	mlxsw_sp_vr_put(vr);
 }

drivers/net/ethernet/qualcomm/emac/emac-ethtool.c+30−0

@@ -88,6 +88,8 @@ static void emac_set_msglevel(struct net_device *netdev, u32 data) · 87 unmodified lines
88	static int emac_get_sset_count(struct net_device *netdev, int sset)	88	static int emac_get_sset_count(struct net_device *netdev, int sset)
89	{	89	{
90	switch (sset) {	90	switch (sset) {
		91	case ETH_SS_PRIV_FLAGS:
		92	return 1;
91	case ETH_SS_STATS:	93	case ETH_SS_STATS:
92	return EMAC_STATS_LEN;	94	return EMAC_STATS_LEN;
93	default:	95	default:
@@ -100,6 +102,10 @@ static void emac_get_strings(struct net_device netdev, u32 stringset, u8 data) · 6 unmodified lines
100	unsigned int i;	102	unsigned int i;
101		103
102	switch (stringset) {	104	switch (stringset) {
		105	case ETH_SS_PRIV_FLAGS:
		106	strcpy(data, "single-pause-mode");
		107	break;
		108
103	case ETH_SS_STATS:	109	case ETH_SS_STATS:
104	for (i = 0; i < EMAC_STATS_LEN; i++) {	110	for (i = 0; i < EMAC_STATS_LEN; i++) {
105	strlcpy(data, emac_ethtool_stat_strings[i],	111	strlcpy(data, emac_ethtool_stat_strings[i],
@@ -230,6 +236,27 @@ static int emac_get_regs_len(struct net_device *netdev) · 124 unmodified lines
230	return EMAC_MAX_REG_SIZE * sizeof(u32);	236	return EMAC_MAX_REG_SIZE * sizeof(u32);
231	}	237	}
232		238
		239	#define EMAC_PRIV_ENABLE_SINGLE_PAUSE BIT(0)
		240
		241	static int emac_set_priv_flags(struct net_device *netdev, u32 flags)
		242	{
		243	struct emac_adapter *adpt = netdev_priv(netdev);
		244
		245	adpt->single_pause_mode = !!(flags & EMAC_PRIV_ENABLE_SINGLE_PAUSE);
		246
		247	if (netif_running(netdev))
		248	return emac_reinit_locked(adpt);
		249
		250	return 0;
		251	}
		252
		253	static u32 emac_get_priv_flags(struct net_device *netdev)
		254	{
		255	struct emac_adapter *adpt = netdev_priv(netdev);
		256
		257	return adpt->single_pause_mode ? EMAC_PRIV_ENABLE_SINGLE_PAUSE : 0;
		258	}
		259
233	static const struct ethtool_ops emac_ethtool_ops = {	260	static const struct ethtool_ops emac_ethtool_ops = {
234	.get_link_ksettings = phy_ethtool_get_link_ksettings,	261	.get_link_ksettings = phy_ethtool_get_link_ksettings,
235	.set_link_ksettings = phy_ethtool_set_link_ksettings,	262	.set_link_ksettings = phy_ethtool_set_link_ksettings,
@@ -253,6 +280,9 @@ static const struct ethtool_ops emac_ethtool_ops = { · 17 unmodified lines
253		280
254	.get_regs_len = emac_get_regs_len,	281	.get_regs_len = emac_get_regs_len,
255	.get_regs = emac_get_regs,	282	.get_regs = emac_get_regs,
		283
		284	.set_priv_flags = emac_set_priv_flags,
		285	.get_priv_flags = emac_get_priv_flags,
256	};	286	};
257		287
258	void emac_set_ethtool_ops(struct net_device *netdev)	288	void emac_set_ethtool_ops(struct net_device *netdev)

drivers/net/ethernet/qualcomm/emac/emac-mac.c+24−1

@@ -551,6 +551,28 @@ static void emac_mac_start(struct emac_adapter *adpt) · 550 unmodified lines
551	mac &= ~(HUGEN \| VLAN_STRIP \| TPAUSE \| SIMR \| HUGE \| MULTI_ALL \|	551	mac &= ~(HUGEN \| VLAN_STRIP \| TPAUSE \| SIMR \| HUGE \| MULTI_ALL \|
552	DEBUG_MODE \| SINGLE_PAUSE_MODE);	552	DEBUG_MODE \| SINGLE_PAUSE_MODE);
553		553
		554	/* Enable single-pause-frame mode if requested.
		555	*
		556	* If enabled, the EMAC will send a single pause frame when the RX
		557	* queue is full. This normally leads to packet loss because
		558	* the pause frame disables the remote MAC only for 33ms (the quanta),
		559	* and then the remote MAC continues sending packets even though
		560	* the RX queue is still full.
		561	*
		562	* If disabled, the EMAC sends a pause frame every 31ms until the RX
		563	* queue is no longer full. Normally, this is the preferred
		564	* method of operation. However, when the system is hung (e.g.
		565	* cores are halted), the EMAC interrupt handler is never called
		566	* and so the RX queue fills up quickly and stays full. The resuling
		567	* non-stop "flood" of pause frames sometimes has the effect of
		568	* disabling nearby switches. In some cases, other nearby switches
		569	* are also affected, shutting down the entire network.
		570	*
		571	* The user can enable or disable single-pause-frame mode
		572	* via ethtool.
		573	*/
		574	mac \|= adpt->single_pause_mode ? SINGLE_PAUSE_MODE : 0;
		575
554	writel_relaxed(csr1, adpt->csr + EMAC_EMAC_WRAPPER_CSR1);	576	writel_relaxed(csr1, adpt->csr + EMAC_EMAC_WRAPPER_CSR1);
555		577
556	writel_relaxed(mac, adpt->base + EMAC_MAC_CTRL);	578	writel_relaxed(mac, adpt->base + EMAC_MAC_CTRL);
@@ -876,7 +898,8 @@ static void emac_mac_rx_descs_refill(struct emac_adapter *adpt, · 319 unmodified lines
876		898
877	curr_rxbuf->dma_addr =	899	curr_rxbuf->dma_addr =
878	dma_map_single(adpt->netdev->dev.parent, skb->data,	900	dma_map_single(adpt->netdev->dev.parent, skb->data,
879	curr_rxbuf->length, DMA_FROM_DEVICE);	901	adpt->rxbuf_size, DMA_FROM_DEVICE);
		902
880	ret = dma_mapping_error(adpt->netdev->dev.parent,	903	ret = dma_mapping_error(adpt->netdev->dev.parent,
881	curr_rxbuf->dma_addr);	904	curr_rxbuf->dma_addr);
882	if (ret) {	905	if (ret) {

drivers/net/ethernet/qualcomm/emac/emac.c+3−0

@@ -443,6 +443,9 @@ static void emac_init_adapter(struct emac_adapter *adpt) · 442 unmodified lines
443		443
444	/* default to automatic flow control */	444	/* default to automatic flow control */
445	adpt->automatic = true;	445	adpt->automatic = true;
		446
		447	/* Disable single-pause-frame mode by default */
		448	adpt->single_pause_mode = false;
446	}	449	}
447		450
448	/* Get the clock */	451	/* Get the clock */

drivers/net/ethernet/qualcomm/emac/emac.h+3−0

@@ -363,6 +363,9 @@ struct emac_adapter { · 362 unmodified lines
363	bool tx_flow_control;	363	bool tx_flow_control;
364	bool rx_flow_control;	364	bool rx_flow_control;
365		365
		366	/* True == use single-pause-frame mode. */
		367	bool single_pause_mode;
		368
366	/* Ring parameter */	369	/* Ring parameter */
367	u8 tpd_burst;	370	u8 tpd_burst;
368	u8 rfd_burst;	371	u8 rfd_burst;

drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c+1−4

@@ -51,10 +51,7 @@ struct rmnet_walk_data { · 50 unmodified lines
51		51
52	static int rmnet_is_real_dev_registered(const struct net_device *real_dev)	52	static int rmnet_is_real_dev_registered(const struct net_device *real_dev)
53	{	53	{
54	rx_handler_func_t *rx_handler;	54	return rcu_access_pointer(real_dev->rx_handler) == rmnet_rx_handler;
55
56	rx_handler = rcu_dereference(real_dev->rx_handler);
57	return (rx_handler == rmnet_rx_handler);
58	}	55	}
59		56
60	/* Needs rtnl lock */	57	/* Needs rtnl lock */

drivers/net/ethernet/realtek/8139too.c+3−2

 	if (likely(RTL_R16(IntrStatus) & RxAckBits))
 		work_done += rtl8139_rx(dev, tp, budget);
-	if (work_done < budget && napi_complete_done(napi, work_done)) {
+	if (work_done < budget) {
 		unsigned long flags;
 		spin_lock_irqsave(&tp->lock, flags);
-		RTL_W16_F(IntrMask, rtl8139_intr_mask);
+		if (napi_complete_done(napi, work_done))
+			RTL_W16_F(IntrMask, rtl8139_intr_mask);
 		spin_unlock_irqrestore(&tp->lock, flags);
 	}
 	spin_unlock(&tp->rx_lock);

drivers/net/ethernet/rocker/rocker_tlv.h+30−18

@@ -139,40 +139,52 @@ rocker_tlv_start(struct rocker_desc_info *desc_info) · 138 unmodified lines
139	int rocker_tlv_put(struct rocker_desc_info *desc_info,	139	int rocker_tlv_put(struct rocker_desc_info *desc_info,
140	int attrtype, int attrlen, const void *data);	140	int attrtype, int attrlen, const void *data);
141		141
142	static inline int rocker_tlv_put_u8(struct rocker_desc_info *desc_info,	142	static inline int
143	int attrtype, u8 value)	143	rocker_tlv_put_u8(struct rocker_desc_info *desc_info, int attrtype, u8 value)
144	{	144	{
145	return rocker_tlv_put(desc_info, attrtype, sizeof(u8), &value);	145	u8 tmp = value; /* work around GCC PR81715 */
		146
		147	return rocker_tlv_put(desc_info, attrtype, sizeof(u8), &tmp);
146	}	148	}
147		149
148	static inline int rocker_tlv_put_u16(struct rocker_desc_info *desc_info,	150	static inline int
149	int attrtype, u16 value)	151	rocker_tlv_put_u16(struct rocker_desc_info *desc_info, int attrtype, u16 value)
150	{	152	{
151	return rocker_tlv_put(desc_info, attrtype, sizeof(u16), &value);	153	u16 tmp = value;
		154
		155	return rocker_tlv_put(desc_info, attrtype, sizeof(u16), &tmp);
152	}	156	}
153		157
154	static inline int rocker_tlv_put_be16(struct rocker_desc_info *desc_info,	158	static inline int
155	int attrtype, __be16 value)	159	rocker_tlv_put_be16(struct rocker_desc_info *desc_info, int attrtype, __be16 value)
156	{	160	{
157	return rocker_tlv_put(desc_info, attrtype, sizeof(__be16), &value);	161	__be16 tmp = value;
		162
		163	return rocker_tlv_put(desc_info, attrtype, sizeof(__be16), &tmp);
158	}	164	}
159		165
160	static inline int rocker_tlv_put_u32(struct rocker_desc_info *desc_info,	166	static inline int
161	int attrtype, u32 value)	167	rocker_tlv_put_u32(struct rocker_desc_info *desc_info, int attrtype, u32 value)
162	{	168	{
163	return rocker_tlv_put(desc_info, attrtype, sizeof(u32), &value);	169	u32 tmp = value;
		170
		171	return rocker_tlv_put(desc_info, attrtype, sizeof(u32), &tmp);
164	}	172	}
165		173
166	static inline int rocker_tlv_put_be32(struct rocker_desc_info *desc_info,	174	static inline int
167	int attrtype, __be32 value)	175	rocker_tlv_put_be32(struct rocker_desc_info *desc_info, int attrtype, __be32 value)
168	{	176	{
169	return rocker_tlv_put(desc_info, attrtype, sizeof(__be32), &value);	177	__be32 tmp = value;
		178
		179	return rocker_tlv_put(desc_info, attrtype, sizeof(__be32), &tmp);
170	}	180	}
171		181
172	static inline int rocker_tlv_put_u64(struct rocker_desc_info *desc_info,	182	static inline int
173	int attrtype, u64 value)	183	rocker_tlv_put_u64(struct rocker_desc_info *desc_info, int attrtype, u64 value)
174	{	184	{
175	return rocker_tlv_put(desc_info, attrtype, sizeof(u64), &value);	185	u64 tmp = value;
		186
		187	return rocker_tlv_put(desc_info, attrtype, sizeof(u64), &tmp);
176	}	188	}
177		189
178	static inline struct rocker_tlv *	190	static inline struct rocker_tlv *

drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c+1−0

@@ -511,6 +511,7 @@ static struct platform_driver dwc_eth_dwmac_driver = { · 510 unmodified lines
511	.remove = dwc_eth_dwmac_remove,	511	.remove = dwc_eth_dwmac_remove,
512	.driver = {	512	.driver = {
513	.name = "dwc-eth-dwmac",	513	.name = "dwc-eth-dwmac",
		514	.pm = &stmmac_pltfr_pm_ops,
514	.of_match_table = dwc_eth_dwmac_match,	515	.of_match_table = dwc_eth_dwmac_match,
515	},	516	},
516	};	517	};

drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c+112−0

@@ -83,6 +83,117 @@ struct rk_priv_data { · 82 unmodified lines
83	(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) \| \	83	(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) \| \
84	((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))	84	((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
85		85
		86	#define RK3128_GRF_MAC_CON0 0x0168
		87	#define RK3128_GRF_MAC_CON1 0x016c
		88
		89	/* RK3128_GRF_MAC_CON0 */
		90	#define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
		91	#define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
		92	#define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
		93	#define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
		94	#define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
		95	#define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
		96
		97	/* RK3128_GRF_MAC_CON1 */
		98	#define RK3128_GMAC_PHY_INTF_SEL_RGMII \
		99	(GRF_BIT(6) \| GRF_CLR_BIT(7) \| GRF_CLR_BIT(8))
		100	#define RK3128_GMAC_PHY_INTF_SEL_RMII \
		101	(GRF_CLR_BIT(6) \| GRF_CLR_BIT(7) \| GRF_BIT(8))
		102	#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
		103	#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
		104	#define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
		105	#define RK3128_GMAC_SPEED_100M GRF_BIT(10)
		106	#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
		107	#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
		108	#define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) \| GRF_CLR_BIT(13))
		109	#define RK3128_GMAC_CLK_25M (GRF_BIT(12) \| GRF_BIT(13))
		110	#define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) \| GRF_BIT(13))
		111	#define RK3128_GMAC_RMII_MODE GRF_BIT(14)
		112	#define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
		113
		114	static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
		115	int tx_delay, int rx_delay)
		116	{
		117	struct device *dev = &bsp_priv->pdev->dev;
		118
		119	if (IS_ERR(bsp_priv->grf)) {
		120	dev_err(dev, "Missing rockchip,grf property\n");
		121	return;
		122	}
		123
		124	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
		125	RK3128_GMAC_PHY_INTF_SEL_RGMII \|
		126	RK3128_GMAC_RMII_MODE_CLR);
		127	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
		128	DELAY_ENABLE(RK3128, tx_delay, rx_delay) \|
		129	RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) \|
		130	RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
		131	}
		132
		133	static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
		134	{
		135	struct device *dev = &bsp_priv->pdev->dev;
		136
		137	if (IS_ERR(bsp_priv->grf)) {
		138	dev_err(dev, "Missing rockchip,grf property\n");
		139	return;
		140	}
		141
		142	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
		143	RK3128_GMAC_PHY_INTF_SEL_RMII \| RK3128_GMAC_RMII_MODE);
		144	}
		145
		146	static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
		147	{
		148	struct device *dev = &bsp_priv->pdev->dev;
		149
		150	if (IS_ERR(bsp_priv->grf)) {
		151	dev_err(dev, "Missing rockchip,grf property\n");
		152	return;
		153	}
		154
		155	if (speed == 10)
		156	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
		157	RK3128_GMAC_CLK_2_5M);
		158	else if (speed == 100)
		159	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
		160	RK3128_GMAC_CLK_25M);
		161	else if (speed == 1000)
		162	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
		163	RK3128_GMAC_CLK_125M);
		164	else
		165	dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
		166	}
		167
		168	static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
		169	{
		170	struct device *dev = &bsp_priv->pdev->dev;
		171
		172	if (IS_ERR(bsp_priv->grf)) {
		173	dev_err(dev, "Missing rockchip,grf property\n");
		174	return;
		175	}
		176
		177	if (speed == 10) {
		178	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
		179	RK3128_GMAC_RMII_CLK_2_5M \|
		180	RK3128_GMAC_SPEED_10M);
		181	} else if (speed == 100) {
		182	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
		183	RK3128_GMAC_RMII_CLK_25M \|
		184	RK3128_GMAC_SPEED_100M);
		185	} else {
		186	dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
		187	}
		188	}
		189
		190	static const struct rk_gmac_ops rk3128_ops = {
		191	.set_to_rgmii = rk3128_set_to_rgmii,
		192	.set_to_rmii = rk3128_set_to_rmii,
		193	.set_rgmii_speed = rk3128_set_rgmii_speed,
		194	.set_rmii_speed = rk3128_set_rmii_speed,
		195	};
		196
86	#define RK3228_GRF_MAC_CON0 0x0900	197	#define RK3228_GRF_MAC_CON0 0x0900
87	#define RK3228_GRF_MAC_CON1 0x0904	198	#define RK3228_GRF_MAC_CON1 0x0904
88		199
@@ -1313,6 +1424,7 @@ static int rk_gmac_resume(struct device *dev) · 1224 unmodified lines
1313	static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);	1424	static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
1314		1425
1315	static const struct of_device_id rk_gmac_dwmac_match[] = {	1426	static const struct of_device_id rk_gmac_dwmac_match[] = {
		1427	{ .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1316	{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },	1428	{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1317	{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },	1429	{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1318	{ .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },	1430	{ .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c+7−0

 {
 	void __iomem *ioaddr = hw->pcsr;
 	unsigned int pmt = 0;
+	u32 config;
 	if (mode & WAKE_MAGIC) {
 		pr_debug("GMAC: WOL Magic frame\n");
 		pmt |= power_down | global_unicast | wake_up_frame_en;
 	}
+	if (pmt) {
+		/* The receiver must be enabled for WOL before powering down */
+		config = readl(ioaddr + GMAC_CONFIG);
+		config |= GMAC_CONFIG_RE;
+		writel(config, ioaddr + GMAC_CONFIG);
+	}
 	writel(pmt, ioaddr + GMAC_PMT);
 }

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c+1−0

@@ -315,6 +315,7 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, · 314 unmodified lines
315	{ .compatible = "allwinner,sun8i-h3-emac" },	315	{ .compatible = "allwinner,sun8i-h3-emac" },
316	{ .compatible = "allwinner,sun8i-v3s-emac" },	316	{ .compatible = "allwinner,sun8i-v3s-emac" },
317	{ .compatible = "allwinner,sun50i-a64-emac" },	317	{ .compatible = "allwinner,sun50i-a64-emac" },
		318	{},
318	};	319	};
319		320
320	/* If phy-handle property is passed from DT, use it as the PHY */	321	/* If phy-handle property is passed from DT, use it as the PHY */

drivers/net/hyperv/hyperv_net.h+2−0

@@ -150,6 +150,8 @@ struct netvsc_device_info { · 149 unmodified lines
150	u32 num_chn;	150	u32 num_chn;
151	u32 send_sections;	151	u32 send_sections;
152	u32 recv_sections;	152	u32 recv_sections;
		153	u32 send_section_size;
		154	u32 recv_section_size;
153	};	155	};
154		156
155	enum rndis_device_state {	157	enum rndis_device_state {

drivers/net/hyperv/netvsc.c+2−5

 	net_device->max_pkt = RNDIS_MAX_PKT_DEFAULT;
 	net_device->pkt_align = RNDIS_PKT_ALIGN_DEFAULT;
-	net_device->recv_section_size = NETVSC_RECV_SECTION_SIZE;
-	net_device->send_section_size = NETVSC_SEND_SECTION_SIZE;
 	init_completion(&net_device->channel_init_wait);
 	init_waitqueue_head(&net_device->subchan_open);
 	INIT_WORK(&net_device->subchan_work, rndis_set_subchannel);
 	int ret = 0;
 	/* Get receive buffer area. */
-	buf_size = device_info->recv_sections * net_device->recv_section_size;
+	buf_size = device_info->recv_sections * device_info->recv_section_size;
 	buf_size = roundup(buf_size, PAGE_SIZE);
 	net_device->recv_buf = vzalloc(buf_size);
 		goto cleanup;
 	/* Now setup the send buffer. */
-	buf_size = device_info->send_sections * net_device->send_section_size;
+	buf_size = device_info->send_sections * device_info->send_section_size;
 	buf_size = round_up(buf_size, PAGE_SIZE);
 	net_device->send_buf = vzalloc(buf_size);

drivers/net/hyperv/netvsc_drv.c+8−0

 	device_info.num_chn = count;
 	device_info.ring_size = ring_size;
 	device_info.send_sections = nvdev->send_section_cnt;
+	device_info.send_section_size = nvdev->send_section_size;
 	device_info.recv_sections = nvdev->recv_section_cnt;
+	device_info.recv_section_size = nvdev->recv_section_size;
 	rndis_filter_device_remove(dev, nvdev);
 	device_info.ring_size = ring_size;
 	device_info.num_chn = nvdev->num_chn;
 	device_info.send_sections = nvdev->send_section_cnt;
+	device_info.send_section_size = nvdev->send_section_size;
 	device_info.recv_sections = nvdev->recv_section_cnt;
+	device_info.recv_section_size = nvdev->recv_section_size;
 	rndis_filter_device_remove(hdev, nvdev);
 	device_info.num_chn = nvdev->num_chn;
 	device_info.ring_size = ring_size;
 	device_info.send_sections = new_tx;
+	device_info.send_section_size = nvdev->send_section_size;
 	device_info.recv_sections = new_rx;
+	device_info.recv_section_size = nvdev->recv_section_size;
 	netif_device_detach(ndev);
 	was_opened = rndis_filter_opened(nvdev);
 	device_info.ring_size = ring_size;
 	device_info.num_chn = VRSS_CHANNEL_DEFAULT;
 	device_info.send_sections = NETVSC_DEFAULT_TX;
+	device_info.send_section_size = NETVSC_SEND_SECTION_SIZE;
 	device_info.recv_sections = NETVSC_DEFAULT_RX;
+	device_info.recv_section_size = NETVSC_RECV_SECTION_SIZE;
 	nvdev = rndis_filter_device_add(dev, &device_info);
 	if (IS_ERR(nvdev)) {

drivers/net/phy/Kconfig+9−9

 endif
-menuconfig PHYLIB
-	tristate "PHY Device support and infrastructure"
-	depends on NETDEVICES
-	select MDIO_DEVICE
-	help
-	  Ethernet controllers are usually attached to PHY
-	  devices.  This option provides infrastructure for
-	  managing PHY devices.
 config PHYLINK
 	tristate
 	depends on NETDEVICES
 	  configuration links, PHYs, and Serdes links with MAC level
 	  autonegotiation modes.
+menuconfig PHYLIB
+	tristate "PHY Device support and infrastructure"
+	depends on NETDEVICES
+	select MDIO_DEVICE
+	help
+	  Ethernet controllers are usually attached to PHY
+	  devices.  This option provides infrastructure for
+	  managing PHY devices.
 if PHYLIB
 config SWPHY

drivers/net/phy/phy.c+2−1

@@ -373,7 +373,8 @@ void phy_ethtool_ksettings_get(struct phy_device *phydev, · 372 unmodified lines
373	cmd->base.port = PORT_BNC;	373	cmd->base.port = PORT_BNC;
374	else	374	else
375	cmd->base.port = PORT_MII;	375	cmd->base.port = PORT_MII;
376		376	cmd->base.transceiver = phy_is_internal(phydev) ?
		377	XCVR_INTERNAL : XCVR_EXTERNAL;
377	cmd->base.phy_address = phydev->mdio.addr;	378	cmd->base.phy_address = phydev->mdio.addr;
378	cmd->base.autoneg = phydev->autoneg;	379	cmd->base.autoneg = phydev->autoneg;
379	cmd->base.eth_tp_mdix_ctrl = phydev->mdix_ctrl;	380	cmd->base.eth_tp_mdix_ctrl = phydev->mdix_ctrl;

drivers/net/phy/phy_device.c+1−1

@@ -879,7 +879,7 @@ void phy_attached_print(struct phy_device phydev, const char fmt, ...) · 878 unmodified lines
879	{	879	{
880	const char *drv_name = phydev->drv ? phydev->drv->name : "unbound";	880	const char *drv_name = phydev->drv ? phydev->drv->name : "unbound";
881	char *irq_str;	881	char *irq_str;
882	char irq_num[4];	882	char irq_num[8];
883		883
884	switch(phydev->irq) {	884	switch(phydev->irq) {
885	case PHY_POLL:	885	case PHY_POLL:

drivers/net/phy/xilinx_gmii2rgmii.c+1−1

@@ -44,7 +44,7 @@ static int xgmiitorgmii_read_status(struct phy_device *phydev) · 43 unmodified lines
44	priv->phy_drv->read_status(phydev);	44	priv->phy_drv->read_status(phydev);
45		45
46	val = mdiobus_read(phydev->mdio.bus, priv->addr, XILINX_GMII2RGMII_REG);	46	val = mdiobus_read(phydev->mdio.bus, priv->addr, XILINX_GMII2RGMII_REG);
47	val &= XILINX_GMII2RGMII_SPEED_MASK;	47	val &= ~XILINX_GMII2RGMII_SPEED_MASK;
48		48
49	if (phydev->speed == SPEED_1000)	49	if (phydev->speed == SPEED_1000)
50	val \|= BMCR_SPEED1000;	50	val \|= BMCR_SPEED1000;

drivers/net/ppp/ppp_generic.c+1−1

@@ -120,7 +120,7 @@ struct ppp { · 119 unmodified lines
120	int n_channels; /* how many channels are attached 54 */	120	int n_channels; /* how many channels are attached 54 */
121	spinlock_t rlock; /* lock for receive side 58 */	121	spinlock_t rlock; /* lock for receive side 58 */
122	spinlock_t wlock; /* lock for transmit side 5c */	122	spinlock_t wlock; /* lock for transmit side 5c */
123	int xmit_recursion __percpu; / xmit recursion detect */	123	int __percpu xmit_recursion; / xmit recursion detect */
124	int mru; /* max receive unit 60 */	124	int mru; /* max receive unit 60 */
125	unsigned int flags; /* control bits 64 */	125	unsigned int flags; /* control bits 64 */
126	unsigned int xstate; /* transmit state bits 68 */	126	unsigned int xstate; /* transmit state bits 68 */

drivers/net/tun.c+5−3

@@ -1496,11 +1496,13 @@ static ssize_t tun_get_user(struct tun_struct tun, struct tun_file tfile, · 1495 unmodified lines
1496	switch (tun->flags & TUN_TYPE_MASK) {	1496	switch (tun->flags & TUN_TYPE_MASK) {
1497	case IFF_TUN:	1497	case IFF_TUN:
1498	if (tun->flags & IFF_NO_PI) {	1498	if (tun->flags & IFF_NO_PI) {
1499	switch (skb->data[0] & 0xf0) {	1499	u8 ip_version = skb->len ? (skb->data[0] >> 4) : 0;
1500	case 0x40:	1500
		1501	switch (ip_version) {
		1502	case 4:
1501	pi.proto = htons(ETH_P_IP);	1503	pi.proto = htons(ETH_P_IP);
1502	break;	1504	break;
1503	case 0x60:	1505	case 6:
1504	pi.proto = htons(ETH_P_IPV6);	1506	pi.proto = htons(ETH_P_IPV6);
1505	break;	1507	break;
1506	default:	1508	default:

drivers/net/usb/cdc_ether.c+20−1

 		desc->bInterfaceProtocol == 3);
 }
+static int is_novatel_rndis(struct usb_interface_descriptor *desc)
+{
+	return (desc->bInterfaceClass == USB_CLASS_MISC &&
+		desc->bInterfaceSubClass == 4 &&
+		desc->bInterfaceProtocol == 1);
+}
 #else
 #define is_rndis(desc)		0
 #define is_activesync(desc)	0
 #define is_wireless_rndis(desc)	0
+#define is_novatel_rndis(desc)	0
 #endif
 	 */
 	rndis = (is_rndis(&intf->cur_altsetting->desc) ||
 		 is_activesync(&intf->cur_altsetting->desc) ||
-		 is_wireless_rndis(&intf->cur_altsetting->desc));
+		 is_wireless_rndis(&intf->cur_altsetting->desc) ||
+		 is_novatel_rndis(&intf->cur_altsetting->desc));
 	memset(info, 0, sizeof(*info));
 	info->control = intf;
 #define REALTEK_VENDOR_ID	0x0bda
 #define SAMSUNG_VENDOR_ID	0x04e8
 #define LENOVO_VENDOR_ID	0x17ef
+#define LINKSYS_VENDOR_ID	0x13b1
 #define NVIDIA_VENDOR_ID	0x0955
 #define HP_VENDOR_ID		0x03f0
 #define MICROSOFT_VENDOR_ID	0x045e
 	.driver_info = 0,
 },
+#if IS_ENABLED(CONFIG_USB_RTL8152)
+/* Linksys USB3GIGV1 Ethernet Adapter */
+{
+	USB_DEVICE_AND_INTERFACE_INFO(LINKSYS_VENDOR_ID, 0x0041, USB_CLASS_COMM,
+			USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
+	.driver_info = 0,
+},
+#endif
 /* ThinkPad USB-C Dock (based on Realtek RTL8153) */
 {
 	USB_DEVICE_AND_INTERFACE_INFO(LENOVO_VENDOR_ID, 0x3062, USB_CLASS_COMM,

drivers/net/usb/lan78xx.c+24−10

 				      struct ethtool_eeprom *ee, u8 *data)
 {
 	struct lan78xx_net *dev = netdev_priv(netdev);
+	int ret;
+	ret = usb_autopm_get_interface(dev->intf);
+	if (ret)
+		return ret;
 	ee->magic = LAN78XX_EEPROM_MAGIC;
-	return lan78xx_read_raw_eeprom(dev, ee->offset, ee->len, data);
+	ret = lan78xx_read_raw_eeprom(dev, ee->offset, ee->len, data);
+	usb_autopm_put_interface(dev->intf);
+	return ret;
 }
 static int lan78xx_ethtool_set_eeprom(struct net_device *netdev,
 				      struct ethtool_eeprom *ee, u8 *data)
 {
 	struct lan78xx_net *dev = netdev_priv(netdev);
+	int ret;
+	ret = usb_autopm_get_interface(dev->intf);
+	if (ret)
+		return ret;
-	/* Allow entire eeprom update only */
+	/* Invalid EEPROM_INDICATOR at offset zero will result in a failure
-	if ((ee->magic == LAN78XX_EEPROM_MAGIC) &&
+	 * to load data from EEPROM
-	    (ee->offset == 0) &&
+	 */
-	    (ee->len == 512) &&
+	if (ee->magic == LAN78XX_EEPROM_MAGIC)
-	    (data[0] == EEPROM_INDICATOR))
+		ret = lan78xx_write_raw_eeprom(dev, ee->offset, ee->len, data);
-		return lan78xx_write_raw_eeprom(dev, ee->offset, ee->len, data);
 	else if ((ee->magic == LAN78XX_OTP_MAGIC) &&
 		 (ee->offset == 0) &&
 		 (ee->len == 512) &&
 		 (data[0] == OTP_INDICATOR_1))
-		return lan78xx_write_raw_otp(dev, ee->offset, ee->len, data);
+		ret = lan78xx_write_raw_otp(dev, ee->offset, ee->len, data);
+	usb_autopm_put_interface(dev->intf);
-	return -EINVAL;
+	return ret;
 }
 static void lan78xx_get_strings(struct net_device *netdev, u32 stringset,
 	/* LAN7801 only has RGMII mode */
 	if (dev->chipid == ID_REV_CHIP_ID_7801_)
 		buf &= ~MAC_CR_GMII_EN_;
-	buf |= MAC_CR_AUTO_DUPLEX_ | MAC_CR_AUTO_SPEED_;
 	ret = lan78xx_write_reg(dev, MAC_CR, buf);
 	ret = lan78xx_read_reg(dev, MAC_TX, &buf);

drivers/net/usb/r8152.c+2−0

 #define VENDOR_ID_MICROSOFT		0x045e
 #define VENDOR_ID_SAMSUNG		0x04e8
 #define VENDOR_ID_LENOVO		0x17ef
+#define VENDOR_ID_LINKSYS		0x13b1
 #define VENDOR_ID_NVIDIA		0x0955
 #define MCU_TYPE_PLA			0x0100
 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
+	{REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
 	{REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
 	{}
 };

drivers/net/usb/rndis_host.c+4−0

 	/* RNDIS for tethering */
 	USB_INTERFACE_INFO(USB_CLASS_WIRELESS_CONTROLLER, 1, 3),
 	.driver_info = (unsigned long) &rndis_info,
+}, {
+	/* Novatel Verizon USB730L */
+	USB_INTERFACE_INFO(USB_CLASS_MISC, 4, 1),
+	.driver_info = (unsigned long) &rndis_info,
 },
 	{ },		// END
 };

drivers/net/wireless/ath/ath10k/pci.c+2−5

 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
-#ifdef CONFIG_PM
+static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev)
-static int ath10k_pci_pm_suspend(struct device *dev)
 {
 	struct ath10k *ar = dev_get_drvdata(dev);
 	int ret;
 	return ret;
 }
-static int ath10k_pci_pm_resume(struct device *dev)
+static __maybe_unused int ath10k_pci_pm_resume(struct device *dev)
 {
 	struct ath10k *ar = dev_get_drvdata(dev);
 	int ret;
 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops,
 			 ath10k_pci_pm_suspend,
 			 ath10k_pci_pm_resume);
-#endif
 static struct pci_driver ath10k_pci_driver = {
 	.name = "ath10k_pci",

drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c+19−18

 	eth_broadcast_addr(params_le->bssid);
 	params_le->bss_type = DOT11_BSSTYPE_ANY;
-	params_le->scan_type = 0;
+	params_le->scan_type = BRCMF_SCANTYPE_ACTIVE;
 	params_le->channel_num = 0;
 	params_le->nprobes = cpu_to_le32(-1);
 	params_le->active_time = cpu_to_le32(-1);
 	params_le->home_time = cpu_to_le32(-1);
 	memset(&params_le->ssid_le, 0, sizeof(params_le->ssid_le));
-	/* if request is null exit so it will be all channel broadcast scan */
-	if (!request)
-		return;
 	n_ssids = request->n_ssids;
 	n_channels = request->n_channels;
 	/* Copy channel array if applicable */
 	brcmf_dbg(SCAN, "### List of channelspecs to scan ### %d\n",
 		  n_channels);
 			ptr += sizeof(ssid_le);
 		}
 	} else {
-		brcmf_dbg(SCAN, "Broadcast scan %p\n", request->ssids);
+		brcmf_dbg(SCAN, "Performing passive scan\n");
-		if ((request->ssids) && request->ssids->ssid_len) {
+		params_le->scan_type = BRCMF_SCANTYPE_PASSIVE;
-			brcmf_dbg(SCAN, "SSID %s len=%d\n",
-				  params_le->ssid_le.SSID,
-				  request->ssids->ssid_len);
-			params_le->ssid_le.SSID_len =
-				cpu_to_le32(request->ssids->ssid_len);
-			memcpy(&params_le->ssid_le.SSID, request->ssids->ssid,
-				request->ssids->ssid_len);
-		}
 	}
 	/* Adding mask to channel numbers */
 	params_le->channel_num =
 	struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
 	s32 status;
 	struct brcmf_escan_result_le *escan_result_le;
+	u32 escan_buflen;
 	struct brcmf_bss_info_le *bss_info_le;
 	struct brcmf_bss_info_le *bss = NULL;
 	u32 bi_length;
 	if (status == BRCMF_E_STATUS_PARTIAL) {
 		brcmf_dbg(SCAN, "ESCAN Partial result\n");
+		if (e->datalen < sizeof(*escan_result_le)) {
+			brcmf_err("invalid event data length\n");
+			goto exit;
+		}
 		escan_result_le = (struct brcmf_escan_result_le *) data;
 		if (!escan_result_le) {
 			brcmf_err("Invalid escan result (NULL pointer)\n");
 			goto exit;
 		}
+		escan_buflen = le32_to_cpu(escan_result_le->buflen);
+		if (escan_buflen > BRCMF_ESCAN_BUF_SIZE ||
+		    escan_buflen > e->datalen ||
+		    escan_buflen < sizeof(*escan_result_le)) {
+			brcmf_err("Invalid escan buffer length: %d\n",
+				  escan_buflen);
+			goto exit;
+		}
 		if (le16_to_cpu(escan_result_le->bss_count) != 1) {
 			brcmf_err("Invalid bss_count %d: ignoring\n",
 				  escan_result_le->bss_count);
 		}
 		bi_length = le32_to_cpu(bss_info_le->length);
-		if (bi_length != (le32_to_cpu(escan_result_le->buflen) -
+		if (bi_length != escan_buflen -	WL_ESCAN_RESULTS_FIXED_SIZE) {
-					WL_ESCAN_RESULTS_FIXED_SIZE)) {
+			brcmf_err("Ignoring invalid bss_info length: %d\n",
-			brcmf_err("Invalid bss_info length %d: ignoring\n",
 				  bi_length);
 			goto exit;
 		}

drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h+5−0

 #define BRCMF_SCAN_PARAMS_COUNT_MASK	0x0000ffff
 #define BRCMF_SCAN_PARAMS_NSSID_SHIFT	16
+/* scan type definitions */
+#define BRCMF_SCANTYPE_DEFAULT		0xFF
+#define BRCMF_SCANTYPE_ACTIVE		0
+#define BRCMF_SCANTYPE_PASSIVE		1
 #define BRCMF_WSEC_MAX_PSK_LEN		32
 #define	BRCMF_WSEC_PASSPHRASE		BIT(0)

drivers/net/wireless/intel/iwlwifi/mvm/d3.c+1−1

@@ -2167,7 +2167,7 @@ out: · 2166 unmodified lines
2167	* 1. We are not using a unified image	2167	* 1. We are not using a unified image
2168	* 2. We are using a unified image but had an error while exiting D3	2168	* 2. We are using a unified image but had an error while exiting D3
2169	*/	2169	*/
2170	set_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status);	2170	set_bit(IWL_MVM_STATUS_HW_RESTART_REQUESTED, &mvm->status);
2171	set_bit(IWL_MVM_STATUS_D3_RECONFIG, &mvm->status);	2171	set_bit(IWL_MVM_STATUS_D3_RECONFIG, &mvm->status);
2172	/*	2172	/*
2173	* When switching images we return 1, which causes mac80211	2173	* When switching images we return 1, which causes mac80211

drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c+59−3

@@ -1546,6 +1546,11 @@ static void iwl_mvm_mc_iface_iterator(void _data, u8 mac, · 1545 unmodified lines
1546	struct iwl_mvm_mc_iter_data *data = _data;	1546	struct iwl_mvm_mc_iter_data *data = _data;
1547	struct iwl_mvm *mvm = data->mvm;	1547	struct iwl_mvm *mvm = data->mvm;
1548	struct iwl_mcast_filter_cmd *cmd = mvm->mcast_filter_cmd;	1548	struct iwl_mcast_filter_cmd *cmd = mvm->mcast_filter_cmd;
		1549	struct iwl_host_cmd hcmd = {
		1550	.id = MCAST_FILTER_CMD,
		1551	.flags = CMD_ASYNC,
		1552	.dataflags[0] = IWL_HCMD_DFL_NOCOPY,
		1553	};
1549	int ret, len;	1554	int ret, len;
1550		1555
1551	/* if we don't have free ports, mcast frames will be dropped */	1556	/* if we don't have free ports, mcast frames will be dropped */
@@ -1560,7 +1565,10 @@ static void iwl_mvm_mc_iface_iterator(void _data, u8 mac, · 8 unmodified lines
1560	memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);	1565	memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
1561	len = roundup(sizeof(cmd) + cmd->count ETH_ALEN, 4);	1566	len = roundup(sizeof(cmd) + cmd->count ETH_ALEN, 4);
1562		1567
1563	ret = iwl_mvm_send_cmd_pdu(mvm, MCAST_FILTER_CMD, CMD_ASYNC, len, cmd);	1568	hcmd.len[0] = len;
		1569	hcmd.data[0] = cmd;
		1570
		1571	ret = iwl_mvm_send_cmd(mvm, &hcmd);
1564	if (ret)	1572	if (ret)
1565	IWL_ERR(mvm, "mcast filter cmd error. ret=%d\n", ret);	1573	IWL_ERR(mvm, "mcast filter cmd error. ret=%d\n", ret);
1566	}	1574	}
@@ -1635,6 +1643,12 @@ static void iwl_mvm_configure_filter(struct ieee80211_hw *hw, · 68 unmodified lines
1635	if (!cmd)	1643	if (!cmd)
1636	goto out;	1644	goto out;
1637		1645
		1646	if (changed_flags & FIF_ALLMULTI)
		1647	cmd->pass_all = !!(*total_flags & FIF_ALLMULTI);
		1648
		1649	if (cmd->pass_all)
		1650	cmd->count = 0;
		1651
1638	iwl_mvm_recalc_multicast(mvm);	1652	iwl_mvm_recalc_multicast(mvm);
1639	out:	1653	out:
1640	mutex_unlock(&mvm->mutex);	1654	mutex_unlock(&mvm->mutex);
@@ -2563,7 +2577,7 @@ static void iwl_mvm_purge_deferred_tx_frames(struct iwl_mvm *mvm, · 922 unmodified lines
2563	* queues, so we should never get a second deferred	2577	* queues, so we should never get a second deferred
2564	* frame for the RA/TID.	2578	* frame for the RA/TID.
2565	*/	2579	*/
2566	iwl_mvm_start_mac_queues(mvm, info->hw_queue);	2580	iwl_mvm_start_mac_queues(mvm, BIT(info->hw_queue));
2567	ieee80211_free_txskb(mvm->hw, skb);	2581	ieee80211_free_txskb(mvm->hw, skb);
2568	}	2582	}
2569	}	2583	}
@@ -3975,6 +3989,43 @@ out_unlock: · 1405 unmodified lines
3975	return ret;	3989	return ret;
3976	}	3990	}
3977		3991
		3992	static void iwl_mvm_flush_no_vif(struct iwl_mvm *mvm, u32 queues, bool drop)
		3993	{
		3994	if (drop) {
		3995	if (iwl_mvm_has_new_tx_api(mvm))
		3996	/* TODO new tx api */
		3997	WARN_ONCE(1,
		3998	"Need to implement flush TX queue\n");
		3999	else
		4000	iwl_mvm_flush_tx_path(mvm,
		4001	iwl_mvm_flushable_queues(mvm) & queues,
		4002	0);
		4003	} else {
		4004	if (iwl_mvm_has_new_tx_api(mvm)) {
		4005	struct ieee80211_sta *sta;
		4006	int i;
		4007
		4008	mutex_lock(&mvm->mutex);
		4009
		4010	for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++) {
		4011	sta = rcu_dereference_protected(
		4012	mvm->fw_id_to_mac_id[i],
		4013	lockdep_is_held(&mvm->mutex));
		4014	if (IS_ERR_OR_NULL(sta))
		4015	continue;
		4016
		4017	iwl_mvm_wait_sta_queues_empty(mvm,
		4018	iwl_mvm_sta_from_mac80211(sta));
		4019	}
		4020
		4021	mutex_unlock(&mvm->mutex);
		4022	} else {
		4023	iwl_trans_wait_tx_queues_empty(mvm->trans,
		4024	queues);
		4025	}
		4026	}
		4027	}
		4028
3978	static void iwl_mvm_mac_flush(struct ieee80211_hw *hw,	4029	static void iwl_mvm_mac_flush(struct ieee80211_hw *hw,
3979	struct ieee80211_vif *vif, u32 queues, bool drop)	4030	struct ieee80211_vif *vif, u32 queues, bool drop)
3980	{	4031	{
@@ -3985,7 +4036,12 @@ static void iwl_mvm_mac_flush(struct ieee80211_hw *hw, · 4 unmodified lines
3985	int i;	4036	int i;
3986	u32 msk = 0;	4037	u32 msk = 0;
3987		4038
3988	if (!vif \|\| vif->type != NL80211_IFTYPE_STATION)	4039	if (!vif) {
		4040	iwl_mvm_flush_no_vif(mvm, queues, drop);
		4041	return;
		4042	}
		4043
		4044	if (vif->type != NL80211_IFTYPE_STATION)
3989	return;	4045	return;
3990		4046
3991	/* Make sure we're done with the deferred traffic before flushing */	4047	/* Make sure we're done with the deferred traffic before flushing */

drivers/net/wireless/intel/iwlwifi/mvm/rs.c+2−1

@@ -661,7 +661,8 @@ static void rs_tl_turn_on_agg(struct iwl_mvm mvm, struct iwl_mvm_sta mvmsta, · 660 unmodified lines
661	(lq_sta->tx_agg_tid_en & BIT(tid)) &&	661	(lq_sta->tx_agg_tid_en & BIT(tid)) &&
662	(tid_data->tx_count_last >= IWL_MVM_RS_AGG_START_THRESHOLD)) {	662	(tid_data->tx_count_last >= IWL_MVM_RS_AGG_START_THRESHOLD)) {
663	IWL_DEBUG_RATE(mvm, "try to aggregate tid %d\n", tid);	663	IWL_DEBUG_RATE(mvm, "try to aggregate tid %d\n", tid);
664	rs_tl_turn_on_agg_for_tid(mvm, lq_sta, tid, sta);	664	if (rs_tl_turn_on_agg_for_tid(mvm, lq_sta, tid, sta) == 0)
		665	tid_data->state = IWL_AGG_QUEUED;
665	}	666	}
666	}	667	}
667		668

drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c+4−3

 	 * If there was a significant jump in the nssn - adjust.
 	 * If the SN is smaller than the NSSN it might need to first go into
 	 * the reorder buffer, in which case we just release up to it and the
-	 * rest of the function will take of storing it and releasing up to the
+	 * rest of the function will take care of storing it and releasing up to
-	 * nssn
+	 * the nssn
 	 */
 	if (!iwl_mvm_is_sn_less(nssn, buffer->head_sn + buffer->buf_size,
-				buffer->buf_size)) {
+				buffer->buf_size) ||
+	    !ieee80211_sn_less(sn, buffer->head_sn + buffer->buf_size)) {
 		u16 min_sn = ieee80211_sn_less(sn, nssn) ? sn : nssn;
 		iwl_mvm_release_frames(mvm, sta, napi, buffer, min_sn);

drivers/net/wireless/intel/iwlwifi/mvm/scan.c+1−1

@@ -555,7 +555,7 @@ static int iwl_mvm_lmac_scan_abort(struct iwl_mvm *mvm) · 554 unmodified lines
555	struct iwl_host_cmd cmd = {	555	struct iwl_host_cmd cmd = {
556	.id = SCAN_OFFLOAD_ABORT_CMD,	556	.id = SCAN_OFFLOAD_ABORT_CMD,
557	};	557	};
558	u32 status;	558	u32 status = CAN_ABORT_STATUS;
559		559
560	ret = iwl_mvm_send_cmd_status(mvm, &cmd, &status);	560	ret = iwl_mvm_send_cmd_status(mvm, &cmd, &status);
561	if (ret)	561	if (ret)

drivers/net/wireless/intel/iwlwifi/mvm/sta.c+5−3

 {
 	struct iwl_mvm_add_sta_cmd cmd;
 	int ret;
-	u32 status;
+	u32 status = ADD_STA_SUCCESS;
 	lockdep_assert_held(&mvm->mutex);
 	if (WARN_ON_ONCE(tid >= IWL_MAX_TID_COUNT))
 		return -EINVAL;
-	if (mvmsta->tid_data[tid].state != IWL_AGG_OFF) {
+	if (mvmsta->tid_data[tid].state != IWL_AGG_QUEUED &&
-		IWL_ERR(mvm, "Start AGG when state is not IWL_AGG_OFF %d!\n",
+	    mvmsta->tid_data[tid].state != IWL_AGG_OFF) {
+		IWL_ERR(mvm,
+			"Start AGG when state is not IWL_AGG_QUEUED or IWL_AGG_OFF %d!\n",
 			mvmsta->tid_data[tid].state);
 		return -ENXIO;
 	}

drivers/net/wireless/intel/iwlwifi/mvm/sta.h+2−0

  * These states relate to a specific RA / TID.
  *
  * @IWL_AGG_OFF: aggregation is not used
+ * @IWL_AGG_QUEUED: aggregation start work has been queued
  * @IWL_AGG_STARTING: aggregation are starting (between start and oper)
  * @IWL_AGG_ON: aggregation session is up
  * @IWL_EMPTYING_HW_QUEUE_ADDBA: establishing a BA session - waiting for the
  */
 enum iwl_mvm_agg_state {
 	IWL_AGG_OFF = 0,
+	IWL_AGG_QUEUED,
 	IWL_AGG_STARTING,
 	IWL_AGG_ON,
 	IWL_EMPTYING_HW_QUEUE_ADDBA,

drivers/net/wireless/intel/iwlwifi/mvm/tt.c+1−0

@@ -529,6 +529,7 @@ int iwl_mvm_ctdp_command(struct iwl_mvm *mvm, u32 op, u32 state) · 528 unmodified lines
529		529
530	lockdep_assert_held(&mvm->mutex);	530	lockdep_assert_held(&mvm->mutex);
531		531
		532	status = 0;
532	ret = iwl_mvm_send_cmd_pdu_status(mvm, WIDE_ID(PHY_OPS_GROUP,	533	ret = iwl_mvm_send_cmd_pdu_status(mvm, WIDE_ID(PHY_OPS_GROUP,
533	CTDP_CONFIG_CMD),	534	CTDP_CONFIG_CMD),
534	sizeof(cmd), &cmd, &status);	535	sizeof(cmd), &cmd, &status);

drivers/net/wireless/intel/iwlwifi/mvm/tx.c+5−5

@@ -564,8 +564,8 @@ static int iwl_mvm_get_ctrl_vif_queue(struct iwl_mvm *mvm, · 563 unmodified lines
564	case NL80211_IFTYPE_AP:	564	case NL80211_IFTYPE_AP:
565	case NL80211_IFTYPE_ADHOC:	565	case NL80211_IFTYPE_ADHOC:
566	/*	566	/*
567	* Handle legacy hostapd as well, where station will be added	567	* Non-bufferable frames use the broadcast station, thus they
568	* only just before sending the association response.	568	* use the probe queue.
569	* Also take care of the case where we send a deauth to a	569	* Also take care of the case where we send a deauth to a
570	* station that we don't have, or similarly an association	570	* station that we don't have, or similarly an association
571	* response (with non-success status) for a station we can't	571	* response (with non-success status) for a station we can't
@@ -573,9 +573,9 @@ static int iwl_mvm_get_ctrl_vif_queue(struct iwl_mvm *mvm, · 1 unmodified line
573	* Also, disassociate frames might happen, particular with	573	* Also, disassociate frames might happen, particular with
574	* reason 7 ("Class 3 frame received from nonassociated STA").	574	* reason 7 ("Class 3 frame received from nonassociated STA").
575	*/	575	*/
576	if (ieee80211_is_probe_resp(fc) \|\| ieee80211_is_auth(fc) \|\|	576	if (ieee80211_is_mgmt(fc) &&
577	ieee80211_is_deauth(fc) \|\| ieee80211_is_assoc_resp(fc) \|\|	577	(!ieee80211_is_bufferable_mmpdu(fc) \|\|
578	ieee80211_is_disassoc(fc))	578	ieee80211_is_deauth(fc) \|\| ieee80211_is_disassoc(fc)))
579	return mvm->probe_queue;	579	return mvm->probe_queue;
580	if (info->hw_queue == info->control.vif->cab_queue)	580	if (info->hw_queue == info->control.vif->cab_queue)
581	return mvmvif->cab_queue;	581	return mvmvif->cab_queue;

drivers/net/wireless/quantenna/qtnfmac/cfg80211.c+6−3

 	vif = qtnf_netdev_get_priv(wdev->netdev);
+	qtnf_scan_done(vif->mac, true);
 	if (qtnf_cmd_send_del_intf(vif))
 		pr_err("VIF%u.%u: failed to delete VIF\n", vif->mac->macid,
 		       vif->vifid);
 	struct qtnf_vif *vif = qtnf_netdev_get_priv(dev);
 	int ret;
+	qtnf_scan_done(vif->mac, true);
 	ret = qtnf_cmd_send_stop_ap(vif);
 	if (ret) {
 		pr_err("VIF%u.%u: failed to stop AP operation in FW\n",
 	    !qtnf_sta_list_lookup(&vif->sta_list, params->mac))
 		return 0;
-	qtnf_scan_done(vif->mac, true);
 	ret = qtnf_cmd_send_del_sta(vif, params);
 	if (ret)
 		pr_err("VIF%u.%u: failed to delete STA %pM\n",
 		}
 		vif->sta_state = QTNF_STA_DISCONNECTED;
-		qtnf_scan_done(mac, true);
 	}
+	qtnf_scan_done(mac, true);
 }
 void qtnf_cfg80211_vif_reset(struct qtnf_vif *vif)

drivers/net/wireless/quantenna/qtnfmac/cfg80211.h+3−0

@@ -34,6 +34,9 @@ static inline void qtnf_scan_done(struct qtnf_wmac *mac, bool aborted) · 33 unmodified lines
34	.aborted = aborted,	34	.aborted = aborted,
35	};	35	};
36		36
		37	if (timer_pending(&mac->scan_timeout))
		38	del_timer_sync(&mac->scan_timeout);
		39
37	mutex_lock(&mac->mac_lock);	40	mutex_lock(&mac->mac_lock);
38		41
39	if (mac->scan_req) {	42	if (mac->scan_req) {

drivers/net/wireless/quantenna/qtnfmac/event.c+0−2

@@ -345,8 +345,6 @@ qtnf_event_handle_scan_complete(struct qtnf_wmac *mac, · 344 unmodified lines
345	return -EINVAL;	345	return -EINVAL;
346	}	346	}
347		347
348	if (timer_pending(&mac->scan_timeout))
349	del_timer_sync(&mac->scan_timeout);
350	qtnf_scan_done(mac, le32_to_cpu(status->flags) & QLINK_SCAN_ABORTED);	348	qtnf_scan_done(mac, le32_to_cpu(status->flags) & QLINK_SCAN_ABORTED);
351		349
352	return 0;	350	return 0;

drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c+8−1

 	struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus);
 	dma_addr_t txbd_paddr, skb_paddr;
 	struct qtnf_tx_bd *txbd;
+	unsigned long flags;
 	int len, i;
 	u32 info;
 	int ret = 0;
+	spin_lock_irqsave(&priv->tx0_lock, flags);
 	if (!qtnf_tx_queue_ready(priv)) {
 		if (skb->dev)
 			netif_stop_queue(skb->dev);
+		spin_unlock_irqrestore(&priv->tx0_lock, flags);
 		return NETDEV_TX_BUSY;
 	}
 		dev_kfree_skb_any(skb);
 	}
-	qtnf_pcie_data_tx_reclaim(priv);
 	priv->tx_done_count++;
+	spin_unlock_irqrestore(&priv->tx0_lock, flags);
+	qtnf_pcie_data_tx_reclaim(priv);
 	return NETDEV_TX_OK;
 }
 	strcpy(bus->fwname, QTN_PCI_PEARL_FW_NAME);
 	init_completion(&bus->request_firmware_complete);
 	mutex_init(&bus->bus_lock);
+	spin_lock_init(&pcie_priv->tx0_lock);
 	spin_lock_init(&pcie_priv->irq_lock);
 	spin_lock_init(&pcie_priv->tx_reclaim_lock);

drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_bus_priv.h+2−0

@@ -34,6 +34,8 @@ struct qtnf_pcie_bus_priv { · 33 unmodified lines
34		34
35	/* lock for tx reclaim operations */	35	/* lock for tx reclaim operations */
36	spinlock_t tx_reclaim_lock;	36	spinlock_t tx_reclaim_lock;
		37	/* lock for tx0 operations */
		38	spinlock_t tx0_lock;
37	u8 msi_enabled;	39	u8 msi_enabled;
38	int mps;	40	int mps;
39		41

drivers/nvdimm/namespace_devs.c+9−0

@@ -1417,6 +1417,15 @@ static int btt_claim_class(struct device *dev) · 1416 unmodified lines
1417	struct nvdimm_drvdata *ndd = to_ndd(nd_mapping);	1417	struct nvdimm_drvdata *ndd = to_ndd(nd_mapping);
1418	struct nd_namespace_index *nsindex;	1418	struct nd_namespace_index *nsindex;
1419		1419
		1420	/*
		1421	* If any of the DIMMs do not support labels the only
		1422	* possible BTT format is v1.
		1423	*/
		1424	if (!ndd) {
		1425	loop_bitmask = 0;
		1426	break;
		1427	}
		1428
1420	nsindex = to_namespace_index(ndd, ndd->ns_current);	1429	nsindex = to_namespace_index(ndd, ndd->ns_current);
1421	if (nsindex == NULL)	1430	if (nsindex == NULL)
1422	loop_bitmask \|= 1;	1431	loop_bitmask \|= 1;

drivers/nvme/host/core.c+5−6

 		return false;
 	if (nvme_req(req)->status & NVME_SC_DNR)
 		return false;
-	if (jiffies - req->start_time >= req->timeout)
-		return false;
 	if (nvme_req(req)->retries >= nvme_max_retries)
 		return false;
 	return true;
 	struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
 	if (a == &dev_attr_uuid.attr) {
-		if (uuid_is_null(&ns->uuid) ||
+		if (uuid_is_null(&ns->uuid) &&
 		    !memchr_inv(ns->nguid, 0, sizeof(ns->nguid)))
 			return 0;
 	}
 		container_of(work, struct nvme_ctrl, async_event_work);
 	spin_lock_irq(&ctrl->lock);
-	while (ctrl->event_limit > 0) {
+	while (ctrl->state == NVME_CTRL_LIVE && ctrl->event_limit > 0) {
 		int aer_idx = --ctrl->event_limit;
 		spin_unlock_irq(&ctrl->lock);
 		/*FALLTHRU*/
 	case NVME_SC_ABORT_REQ:
 		++ctrl->event_limit;
-		queue_work(nvme_wq, &ctrl->async_event_work);
+		if (ctrl->state == NVME_CTRL_LIVE)
+			queue_work(nvme_wq, &ctrl->async_event_work);
 		break;
 	default:
 		break;
 		nvme_queue_scan(ctrl);
 		break;
 	case NVME_AER_NOTICE_FW_ACT_STARTING:
-		schedule_work(&ctrl->fw_act_work);
+		queue_work(nvme_wq, &ctrl->fw_act_work);
 		break;
 	default:
 		dev_warn(ctrl->device, "async event result %08x\n", result);

drivers/nvme/host/fabrics.c+9−9

 	opts->queue_size = NVMF_DEF_QUEUE_SIZE;
 	opts->nr_io_queues = num_online_cpus();
 	opts->reconnect_delay = NVMF_DEF_RECONNECT_DELAY;
+	opts->kato = NVME_DEFAULT_KATO;
 	options = o = kstrdup(buf, GFP_KERNEL);
 	if (!options)
 				goto out;
 			}
-			if (opts->discovery_nqn) {
-				pr_err("Discovery controllers cannot accept keep_alive_tmo != 0\n");
-				ret = -EINVAL;
-				goto out;
-			}
 			if (token < 0) {
 				pr_err("Invalid keep_alive_tmo %d\n", token);
 				ret = -EINVAL;
 				goto out;
-			} else if (token == 0) {
+			} else if (token == 0 && !opts->discovery_nqn) {
 				/* Allowed for debug */
 				pr_warn("keep_alive_tmo 0 won't execute keep alives!!!\n");
 			}
 			opts->kato = token;
+			if (opts->discovery_nqn && opts->kato) {
+				pr_err("Discovery controllers cannot accept KATO != 0\n");
+				ret = -EINVAL;
+				goto out;
+			}
 			break;
 		case NVMF_OPT_CTRL_LOSS_TMO:
 			if (match_int(args, &token)) {
 	uuid_copy(&opts->host->id, &hostid);
 out:
-	if (!opts->discovery_nqn && !opts->kato)
-		opts->kato = NVME_DEFAULT_KATO;
 	kfree(options);
 	return ret;
 }

drivers/nvme/host/fc.c+11−10

 	if (atomic_read(&op->state) == FCPOP_STATE_ABORTED)
 		status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
 	else if (freq->status)
-		status = cpu_to_le16(NVME_SC_FC_TRANSPORT_ERROR << 1);
+		status = cpu_to_le16(NVME_SC_INTERNAL << 1);
 	/*
 	 * For the linux implementation, if we have an unsuccesful
 		 */
 		if (freq->transferred_length !=
 			be32_to_cpu(op->cmd_iu.data_len)) {
-			status = cpu_to_le16(NVME_SC_FC_TRANSPORT_ERROR << 1);
+			status = cpu_to_le16(NVME_SC_INTERNAL << 1);
 			goto done;
 		}
 		result.u64 = 0;
 					freq->transferred_length ||
 			     op->rsp_iu.status_code ||
 			     sqe->common.command_id != cqe->command_id)) {
-			status = cpu_to_le16(NVME_SC_FC_TRANSPORT_ERROR << 1);
+			status = cpu_to_le16(NVME_SC_INTERNAL << 1);
 			goto done;
 		}
 		result = cqe->result;
 		break;
 	default:
-		status = cpu_to_le16(NVME_SC_FC_TRANSPORT_ERROR << 1);
+		status = cpu_to_le16(NVME_SC_INTERNAL << 1);
 		goto done;
 	}
 	 * as well as those by FC-NVME spec.
 	 */
 	WARN_ON_ONCE(sqe->common.metadata);
-	WARN_ON_ONCE(sqe->common.dptr.prp1);
-	WARN_ON_ONCE(sqe->common.dptr.prp2);
 	sqe->common.flags |= NVME_CMD_SGL_METABUF;
 	/*
-	 * format SQE DPTR field per FC-NVME rules
+	 * format SQE DPTR field per FC-NVME rules:
-	 *    type=data block descr; subtype=offset;
+	 *    type=0x5     Transport SGL Data Block Descriptor
-	 *    offset is currently 0.
+	 *    subtype=0xA  Transport-specific value
+	 *    address=0
+	 *    length=length of the data series
 	 */
-	sqe->rw.dptr.sgl.type = NVME_SGL_FMT_OFFSET;
+	sqe->rw.dptr.sgl.type = (NVME_TRANSPORT_SGL_DATA_DESC << 4) |
+					NVME_SGL_FMT_TRANSPORT_A;
 	sqe->rw.dptr.sgl.length = cpu_to_le32(data_len);
 	sqe->rw.dptr.sgl.addr = 0;

drivers/nvme/host/pci.c+27−21

 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
+#include <linux/once.h>
 #include <linux/pci.h>
 #include <linux/poison.h>
 #include <linux/t10-pi.h>
 	struct mutex shutdown_lock;
 	bool subsystem;
 	void __iomem *cmb;
-	dma_addr_t cmb_dma_addr;
+	pci_bus_addr_t cmb_bus_addr;
 	u64 cmb_size;
 	u32 cmbsz;
 	u32 cmbloc;
 }
 #endif
+static void nvme_print_sgl(struct scatterlist *sgl, int nents)
+{
+	int i;
+	struct scatterlist *sg;
+	for_each_sg(sgl, sg, nents, i) {
+		dma_addr_t phys = sg_phys(sg);
+		pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
+			"dma_address:%pad dma_length:%d\n",
+			i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
+			sg_dma_len(sg));
+	}
+}
 static blk_status_t nvme_setup_prps(struct nvme_dev *dev, struct request *req)
 {
 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 	return BLK_STS_OK;
  bad_sgl:
-	if (WARN_ONCE(1, "Invalid SGL for payload:%d nents:%d\n",
+	WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
-				blk_rq_payload_bytes(req), iod->nents)) {
+			"Invalid SGL for payload:%d nents:%d\n",
-		for_each_sg(iod->sg, sg, iod->nents, i) {
+			blk_rq_payload_bytes(req), iod->nents);
-			dma_addr_t phys = sg_phys(sg);
-			pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
-			       "dma_address:%pad dma_length:%d\n", i, &phys,
-					sg->offset, sg->length,
-					&sg_dma_address(sg),
-					sg_dma_len(sg));
-		}
-	}
 	return BLK_STS_IOERR;
 }
 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 	if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
 		unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
 						      dev->ctrl.page_size);
-		nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
+		nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
 		nvmeq->sq_cmds_io = dev->cmb + offset;
 	} else {
 		nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
 	if (result < 0)
 		goto release_cq;
+	nvme_init_queue(nvmeq, qid);
 	result = queue_request_irq(nvmeq);
 	if (result < 0)
 		goto release_sq;
-	nvme_init_queue(nvmeq, qid);
 	return result;
  release_sq:
 		return result;
 	nvmeq->cq_vector = 0;
+	nvme_init_queue(nvmeq, 0);
 	result = queue_request_irq(nvmeq);
 	if (result) {
 		nvmeq->cq_vector = -1;
 	resource_size_t bar_size;
 	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	void __iomem *cmb;
-	dma_addr_t dma_addr;
+	int bar;
 	dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
 	if (!(NVME_CMB_SZ(dev->cmbsz)))
 	szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
 	size = szu * NVME_CMB_SZ(dev->cmbsz);
 	offset = szu * NVME_CMB_OFST(dev->cmbloc);
-	bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
+	bar = NVME_CMB_BIR(dev->cmbloc);
+	bar_size = pci_resource_len(pdev, bar);
 	if (offset > bar_size)
 		return NULL;
 	if (size > bar_size - offset)
 		size = bar_size - offset;
-	dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
+	cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
-	cmb = ioremap_wc(dma_addr, size);
 	if (!cmb)
 		return NULL;
-	dev->cmb_dma_addr = dma_addr;
+	dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
 	dev->cmb_size = size;
 	return cmb;
 }
 	if (result)
 		goto out;
-	nvme_init_queue(dev->queues[0], 0);
 	result = nvme_alloc_admin_tags(dev);
 	if (result)
 		goto out;

drivers/nvme/host/rdma.c+7−2

 	}
 	changed = nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_LIVE);
-	WARN_ON_ONCE(!changed);
+	if (!changed) {
+		/* state change failure is ok if we're in DELETING state */
+		WARN_ON_ONCE(ctrl->ctrl.state != NVME_CTRL_DELETING);
+		return;
+	}
 	ctrl->ctrl.nr_reconnects = 0;
 	nvme_start_ctrl(&ctrl->ctrl);
 	struct nvme_rdma_ctrl *ctrl = container_of(work,
 			struct nvme_rdma_ctrl, err_work);
-	nvme_stop_ctrl(&ctrl->ctrl);
+	nvme_stop_keep_alive(&ctrl->ctrl);
 	if (ctrl->ctrl.queue_count > 1) {
 		nvme_stop_queues(&ctrl->ctrl);

drivers/nvme/target/core.c+5−4

@@ -390,10 +390,10 @@ static void __nvmet_req_complete(struct nvmet_req *req, u16 status) · 389 unmodified lines
390	if (status)	390	if (status)
391	nvmet_set_status(req, status);	391	nvmet_set_status(req, status);
392		392
393	/* XXX: need to fill in something useful for sq_head */	393	if (req->sq->size)
394	req->rsp->sq_head = 0;	394	req->sq->sqhd = (req->sq->sqhd + 1) % req->sq->size;
395	if (likely(req->sq)) /* may happen during early failure */	395	req->rsp->sq_head = cpu_to_le16(req->sq->sqhd);
396	req->rsp->sq_id = cpu_to_le16(req->sq->qid);	396	req->rsp->sq_id = cpu_to_le16(req->sq->qid);
397	req->rsp->command_id = req->cmd->common.command_id;	397	req->rsp->command_id = req->cmd->common.command_id;
398		398

9 more lines aren’t shown here.

drivers/nvme/target/fabrics-cmd.c+7−2

This diff is large: its 17 lines aren’t shown here.

drivers/nvme/target/fc.c+14−10

This diff is large: its 86 lines aren’t shown here.

drivers/nvme/target/fcloop.c+39−65

This diff is large: its 206 lines aren’t shown here.

drivers/nvme/target/nvmet.h+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/nvmem/core.c+2−1

This diff is large: its 17 lines aren’t shown here.

drivers/pci/endpoint/functions/pci-epf-test.c+6−7

This diff is large: its 61 lines aren’t shown here.

drivers/pci/pci-sysfs.c+9−2

This diff is large: its 39 lines aren’t shown here.

drivers/perf/arm_pmu_acpi.c+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/platform/x86/fujitsu-laptop.c+6−4

This diff is large: its 17 lines aren’t shown here.

drivers/rapidio/devices/tsi721.c+7−0

This diff is large: its 35 lines aren’t shown here.

drivers/rapidio/rio-access.c+5−35

This diff is large: its 94 lines aren’t shown here.

drivers/reset/Kconfig+5−4

This diff is large: its 17 lines aren’t shown here.

drivers/reset/Makefile+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/reset/reset-hsdk.crenamed from drivers/reset/reset-hsdk-v1.c+22−22

This diff is large: its 111 lines aren’t shown here.

drivers/s390/block/dasd.c+9−3

This diff is large: its 33 lines aren’t shown here.

drivers/s390/block/scm_blk.c+3−3

This diff is large: its 27 lines aren’t shown here.

drivers/s390/cio/device.c+9−3

This diff is large: its 40 lines aren’t shown here.

drivers/s390/cio/device.h+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/s390/cio/device_fsm.c+12−0

This diff is large: its 26 lines aren’t shown here.

drivers/s390/cio/io_sch.h+2−0

This diff is large: its 9 lines aren’t shown here.

drivers/scsi/aacraid/aachba.c+6−6

This diff is large: its 20 lines aren’t shown here.

drivers/scsi/aacraid/aacraid.h+5−0

This diff is large: its 12 lines aren’t shown here.

drivers/scsi/aacraid/linit.c+12−8

This diff is large: its 38 lines aren’t shown here.

drivers/scsi/aacraid/src.c+2−0

This diff is large: its 9 lines aren’t shown here.

drivers/scsi/arm/acornscsi.c+3−3

This diff is large: its 21 lines aren’t shown here.

drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/scsi/libiscsi.c+4−4

This diff is large: its 29 lines aren’t shown here.

drivers/scsi/lpfc/lpfc_init.c+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/scsi/lpfc/lpfc_nvme.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/scsi/qla2xxx/qla_nvme.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/scsi/scsi_error.c+2−1

This diff is large: its 10 lines aren’t shown here.

drivers/scsi/scsi_scan.c+3−0

This diff is large: its 10 lines aren’t shown here.

drivers/scsi/scsi_transport_fc.c+4−12

This diff is large: its 44 lines aren’t shown here.

drivers/scsi/scsi_transport_iscsi.c+1−17

This diff is large: its 32 lines aren’t shown here.

drivers/scsi/sd.c+26−11

This diff is large: its 75 lines aren’t shown here.

drivers/scsi/sg.c+36−28

This diff is large: its 82 lines aren’t shown here.

drivers/staging/iio/adc/ad7192.c+1−3

This diff is large: its 13 lines aren’t shown here.

drivers/staging/mt29f_spinand/mt29f_spinand.c+6−2

This diff is large: its 15 lines aren’t shown here.

drivers/staging/pi433/rf69.c+3−6

This diff is large: its 23 lines aren’t shown here.

drivers/staging/rtl8723bs/core/rtw_mlme.c+1−2

This diff is large: its 11 lines aren’t shown here.

drivers/staging/rtl8723bs/os_dep/rtw_proc.c+2−0

This diff is large: its 9 lines aren’t shown here.

drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx.c+2−2

This diff is large: its 14 lines aren’t shown here.

drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_func_88xx.c+7−6

This diff is large: its 56 lines aren’t shown here.

drivers/staging/speakup/main.c+12−3

This diff is large: its 51 lines aren’t shown here.

drivers/staging/unisys/visorbus/visorchipset.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c+4−2

This diff is large: its 23 lines aren’t shown here.

drivers/tty/mxser.c+11−5

This diff is large: its 41 lines aren’t shown here.

drivers/tty/serial/bcm63xx_uart.c+5−0

This diff is large: its 15 lines aren’t shown here.

drivers/tty/serial/fsl_lpuart.c+17−23

This diff is large: its 107 lines aren’t shown here.

drivers/tty/serial/sccnxp.c+11−2

This diff is large: its 27 lines aren’t shown here.

drivers/usb/class/cdc-wdm.c+3−1

This diff is large: its 12 lines aren’t shown here.

drivers/usb/core/config.c+12−4

This diff is large: its 36 lines aren’t shown here.

drivers/usb/core/devio.c+10−1

This diff is large: its 32 lines aren’t shown here.

drivers/usb/core/hub.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/usb/core/message.c+4−0

This diff is large: its 11 lines aren’t shown here.

drivers/usb/dwc3/dwc3-of-simple.c+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/usb/dwc3/ep0.c+7−0

This diff is large: its 28 lines aren’t shown here.

drivers/usb/gadget/function/f_fs.c+13−4

This diff is large: its 63 lines aren’t shown here.

drivers/usb/gadget/function/f_mass_storage.c+7−20

This diff is large: its 59 lines aren’t shown here.

drivers/usb/gadget/function/f_mass_storage.h+0−14

This diff is large: its 28 lines aren’t shown here.

drivers/usb/gadget/function/f_printer.c+6−1

This diff is large: its 21 lines aren’t shown here.

drivers/usb/gadget/function/u_fs.h+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/usb/gadget/legacy/inode.c+40−6

This diff is large: its 160 lines aren’t shown here.

drivers/usb/gadget/legacy/mass_storage.c+3−23

This diff is large: its 57 lines aren’t shown here.

drivers/usb/gadget/udc/Kconfig+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/usb/gadget/udc/atmel_usba_udc.c+3−1

This diff is large: its 18 lines aren’t shown here.

drivers/usb/gadget/udc/core.c+1−2

This diff is large: its 10 lines aren’t shown here.

drivers/usb/gadget/udc/dummy_hcd.c+54−11

This diff is large: its 185 lines aren’t shown here.

drivers/usb/gadget/udc/renesas_usb3.c+15−4

This diff is large: its 47 lines aren’t shown here.

drivers/usb/host/pci-quirks.c+5−5

This diff is large: its 39 lines aren’t shown here.

drivers/usb/host/xhci-hub.c+10−4

This diff is large: its 35 lines aren’t shown here.

drivers/usb/host/xhci-pci.c+0−12

This diff is large: its 26 lines aren’t shown here.

drivers/usb/host/xhci-plat.c+10−6

This diff is large: its 25 lines aren’t shown here.

drivers/usb/host/xhci.c+2−1

This diff is large: its 10 lines aren’t shown here.

drivers/usb/host/xhci.h+6−4

This diff is large: its 38 lines aren’t shown here.

drivers/usb/renesas_usbhs/fifo.c+18−3

This diff is large: its 30 lines aren’t shown here.

drivers/usb/storage/transport.c+13−1

This diff is large: its 27 lines aren’t shown here.

drivers/usb/storage/uas-detect.h+8−7

This diff is large: its 42 lines aren’t shown here.

drivers/usb/storage/uas.c+5−5

This diff is large: its 20 lines aren’t shown here.

drivers/usb/storage/unusual_devs.h+7−0

This diff is large: its 14 lines aren’t shown here.

drivers/uwb/hwa-rc.c+2−0

This diff is large: its 9 lines aren’t shown here.

drivers/uwb/uwbd.c+8−4

This diff is large: its 27 lines aren’t shown here.

drivers/xen/xen-pciback/conf_space_header.c+10−1

This diff is large: its 25 lines aren’t shown here.

drivers/xen/xenbus/xenbus_client.c+67−63

This diff is large: its 167 lines aren’t shown here.

fs/binfmt_misc.c+26−30

This diff is large: its 142 lines aren’t shown here.

fs/binfmt_script.c+9−8

This diff is large: its 58 lines aren’t shown here.

fs/btrfs/compression.c+17−1

This diff is large: its 32 lines aren’t shown here.

fs/btrfs/ctree.h+1−2

This diff is large: its 17 lines aren’t shown here.

fs/btrfs/disk-io.c+8−1

This diff is large: its 16 lines aren’t shown here.

fs/btrfs/extent_io.c+3−7

This diff is large: its 38 lines aren’t shown here.

fs/btrfs/inode.c+22−5

This diff is large: its 70 lines aren’t shown here.

fs/btrfs/ioctl.c+8−4

This diff is large: its 33 lines aren’t shown here.

fs/btrfs/qgroup.c+2−4

This diff is large: its 34 lines aren’t shown here.

fs/btrfs/relocation.c+1−1

This diff is large: its 13 lines aren’t shown here.

fs/btrfs/send.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/btrfs/tree-log.c+10−2

This diff is large: its 43 lines aren’t shown here.

fs/btrfs/volumes.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/ceph/mds_client.c+10−8

This diff is large: its 47 lines aren’t shown here.

fs/ceph/mds_client.h+3−0

This diff is large: its 17 lines aren’t shown here.

fs/ceph/snap.c+3−5

This diff is large: its 16 lines aren’t shown here.

fs/cifs/cifs_debug.c+7−2

This diff is large: its 16 lines aren’t shown here.

fs/cifs/cifsfs.c+3−1

This diff is large: its 18 lines aren’t shown here.

fs/cifs/cifsfs.h+1−1

This diff is large: its 7 lines aren’t shown here.

fs/cifs/cifsglob.h+6−0

This diff is large: its 20 lines aren’t shown here.

fs/cifs/connect.c+25−7

This diff is large: its 75 lines aren’t shown here.

fs/cifs/file.c+15−4

This diff is large: its 40 lines aren’t shown here.

fs/cifs/inode.c+15−0

This diff is large: its 29 lines aren’t shown here.

fs/cifs/smb2ops.c+42−0

This diff is large: its 63 lines aren’t shown here.

fs/cifs/smb2pdu.c+93−18

This diff is large: its 190 lines aren’t shown here.

fs/cifs/smb2pdu.h+1−1

This diff is large: its 9 lines aren’t shown here.

fs/direct-io.c+43−6

This diff is large: its 85 lines aren’t shown here.

fs/exec.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/fcntl.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/gfs2/glock.c+5−9

This diff is large: its 61 lines aren’t shown here.

fs/iomap.c+23−20

This diff is large: its 73 lines aren’t shown here.

fs/isofs/inode.c+2−0

This diff is large: its 12 lines aren’t shown here.

fs/namespace.c+3−1

This diff is large: its 11 lines aren’t shown here.

fs/overlayfs/copy_up.c+2−4

This diff is large: its 13 lines aren’t shown here.

fs/overlayfs/dir.c+0−20

This diff is large: its 27 lines aren’t shown here.

fs/overlayfs/namei.c+1−0

This diff is large: its 8 lines aren’t shown here.

fs/overlayfs/overlayfs.h+1−0

This diff is large: its 8 lines aren’t shown here.

fs/overlayfs/ovl_entry.h+3−0

This diff is large: its 10 lines aren’t shown here.

fs/overlayfs/readdir.c+4−2

This diff is large: its 35 lines aren’t shown here.

fs/overlayfs/super.c+19−8

This diff is large: its 61 lines aren’t shown here.

fs/overlayfs/util.c+23−1

This diff is large: its 42 lines aren’t shown here.

fs/proc/array.c+24−20

This diff is large: its 70 lines aren’t shown here.

fs/quota/dquot.c+2−0

This diff is large: its 10 lines aren’t shown here.

fs/quota/quota_v2.c+4−0

This diff is large: its 17 lines aren’t shown here.

fs/read_write.c+2−2

This diff is large: its 18 lines aren’t shown here.

fs/userfaultfd.c+56−10

This diff is large: its 90 lines aren’t shown here.

fs/xattr.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/xfs/libxfs/xfs_ag_resv.c+10−2

This diff is large: its 26 lines aren’t shown here.

fs/xfs/libxfs/xfs_bmap.c+2−15

This diff is large: its 44 lines aren’t shown here.

fs/xfs/xfs_aops.c+2−1

This diff is large: its 10 lines aren’t shown here.

fs/xfs/xfs_bmap_util.c+35−3

This diff is large: its 55 lines aren’t shown here.

fs/xfs/xfs_buf.c+0−2

This diff is large: its 9 lines aren’t shown here.

fs/xfs/xfs_error.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/xfs/xfs_file.c+21−18

This diff is large: its 82 lines aren’t shown here.

fs/xfs/xfs_inode.c+5−3

This diff is large: its 16 lines aren’t shown here.

fs/xfs/xfs_inode_item.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/xfs/xfs_ioctl.c+2−1

This diff is large: its 17 lines aren’t shown here.

fs/xfs/xfs_iomap.c+5−2

This diff is large: its 28 lines aren’t shown here.

fs/xfs/xfs_iomap.h+1−1

This diff is large: its 9 lines aren’t shown here.

fs/xfs/xfs_pnfs.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/xfs/xfs_reflink.c+8−1

This diff is large: its 23 lines aren’t shown here.

fs/xfs/xfs_super.c+10−0

This diff is large: its 17 lines aren’t shown here.

include/acpi/acpi_bus.h+4−14

This diff is large: its 34 lines aren’t shown here.

include/asm-generic/percpu.h+22−2

This diff is large: its 38 lines aren’t shown here.

include/dt-bindings/reset/snps,hsdk-reset.h+17−0

This diff is large: its 18 lines aren’t shown here.

include/dt-bindings/reset/snps,hsdk-v1-reset.h+0−17

This diff is large: its 18 lines aren’t shown here.

include/linux/audit.h+1−5

This diff is large: its 13 lines aren’t shown here.

include/linux/binfmts.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/linux/bitfield.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/linux/blkdev.h+1−0

This diff is large: its 8 lines aren’t shown here.

include/linux/cpuhotplug.h+20−1

This diff is large: its 29 lines aren’t shown here.

include/linux/device.h+1−3

This diff is large: its 18 lines aren’t shown here.

include/linux/fs.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/linux/iio/adc/ad_sigma_delta.h+3−0

This diff is large: its 10 lines aren’t shown here.

include/linux/input.h+1−0

This diff is large: its 8 lines aren’t shown here.

include/linux/iommu.h+1−1

This diff is large: its 13 lines aren’t shown here.

include/linux/irq.h+1−4

This diff is large: its 12 lines aren’t shown here.

include/linux/key.h+2−0

This diff is large: its 16 lines aren’t shown here.

include/linux/mlx5/device.h+2−3

This diff is large: its 21 lines aren’t shown here.

include/linux/mlx5/driver.h+1−0

This diff is large: its 8 lines aren’t shown here.

include/linux/mlx5/mlx5_ifc.h+2−1

This diff is large: its 10 lines aren’t shown here.

include/linux/mm.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/linux/mmc/host.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/linux/mmu_notifier.h+5−0

This diff is large: its 12 lines aren’t shown here.

include/linux/mmzone.h+8−2

This diff is large: its 17 lines aren’t shown here.

include/linux/nmi.h+62−59

This diff is large: its 185 lines aren’t shown here.

include/linux/nvme-fc-driver.h+8−5

This diff is large: its 32 lines aren’t shown here.

include/linux/nvme.h+6−13

This diff is large: its 52 lines aren’t shown here.

include/linux/of_platform.h+7−0

This diff is large: its 15 lines aren’t shown here.

include/linux/pci.h+2−0

This diff is large: its 9 lines aren’t shown here.

include/linux/sched.h+40−24

This diff is large: its 92 lines aren’t shown here.

include/linux/sched/mm.h+6−0

This diff is large: its 13 lines aren’t shown here.

include/linux/seccomp.h+2−1

This diff is large: its 10 lines aren’t shown here.

include/linux/smpboot.h+2−2

This diff is large: its 10 lines aren’t shown here.

include/linux/syscalls.h+8−4

This diff is large: its 30 lines aren’t shown here.

include/linux/timer.h+14−0

This diff is large: its 21 lines aren’t shown here.

include/linux/trace_events.h+1−0

This diff is large: its 8 lines aren’t shown here.

include/net/dst.h+4−18

This diff is large: its 51 lines aren’t shown here.

include/net/netlink.h+55−18

This diff is large: its 199 lines aren’t shown here.

include/net/protocol.h+2−2

This diff is large: its 11 lines aren’t shown here.

include/net/route.h+4−2

This diff is large: its 20 lines aren’t shown here.

include/net/sock.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/net/tcp.h+1−2

This diff is large: its 17 lines aren’t shown here.

include/net/udp.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/rdma/ib_verbs.h+3−3

This diff is large: its 27 lines aren’t shown here.

include/scsi/scsi_device.h+1−0

This diff is large: its 8 lines aren’t shown here.

include/scsi/scsi_devinfo.h+1−0

This diff is large: its 7 lines aren’t shown here.

include/scsi/scsi_transport_iscsi.h+0−1

This diff is large: its 8 lines aren’t shown here.

include/sound/hda_verbs.h+1−0

This diff is large: its 8 lines aren’t shown here.

include/trace/events/sched.h+12−7

This diff is large: its 33 lines aren’t shown here.

include/uapi/linux/bpf.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/uapi/linux/dm-ioctl.h+2−2

This diff is large: its 12 lines aren’t shown here.

include/uapi/linux/ethtool.h+5−1

This diff is large: its 20 lines aren’t shown here.

include/uapi/linux/kfd_ioctl.h+86−86

This diff is large: its 280 lines aren’t shown here.

include/uapi/linux/seccomp.h+15−8

This diff is large: its 43 lines aren’t shown here.

include/uapi/linux/usb/ch9.h+1−0

This diff is large: its 8 lines aren’t shown here.

include/uapi/rdma/ib_user_verbs.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/xen/arm/page.h+0−10

This diff is large: its 17 lines aren’t shown here.

ipc/shm.c+2−2

This diff is large: its 18 lines aren’t shown here.

kernel/bpf/core.c+1−1

This diff is large: its 9 lines aren’t shown here.

kernel/bpf/devmap.c+4−2

This diff is large: its 28 lines aren’t shown here.

kernel/bpf/syscall.c+4−2

This diff is large: its 20 lines aren’t shown here.

kernel/bpf/verifier.c+6−1

This diff is large: its 14 lines aren’t shown here.

kernel/cgroup/cgroup.c+8−0

This diff is large: its 15 lines aren’t shown here.

kernel/cpu.c+370−142

This diff is large: its 828 lines aren’t shown here.

kernel/events/core.c+2−1

This diff is large: its 17 lines aren’t shown here.

kernel/events/ring_buffer.c+15−5

This diff is large: its 43 lines aren’t shown here.

kernel/exit.c+10−13

This diff is large: its 40 lines aren’t shown here.

kernel/extable.c+31−14

This diff is large: its 65 lines aren’t shown here.

kernel/fork.c+18−0

This diff is large: its 25 lines aren’t shown here.

kernel/futex.c+22−11

This diff is large: its 86 lines aren’t shown here.

kernel/irq/chip.c+1−1

This diff is large: its 9 lines aren’t shown here.

kernel/irq/generic-chip.c+0−1

This diff is large: its 8 lines aren’t shown here.

kernel/irq/irqdomain.c+2−2

This diff is large: its 18 lines aren’t shown here.

kernel/irq/manage.c+4−0

This diff is large: its 11 lines aren’t shown here.

kernel/kcmp.c+1−1

This diff is large: its 9 lines aren’t shown here.

kernel/locking/rwsem-xadd.c+27−0

This diff is large: its 34 lines aren’t shown here.

kernel/memremap.c+3−1

This diff is large: its 18 lines aren’t shown here.

kernel/params.c+16−19

This diff is large: its 99 lines aren’t shown here.

kernel/power/suspend.c+11−7

This diff is large: its 34 lines aren’t shown here.

kernel/rcu/tree.c+10−0

This diff is large: its 24 lines aren’t shown here.

kernel/sched/core.c+23−1

This diff is large: its 38 lines aren’t shown here.

kernel/sched/debug.c+0−2

This diff is large: its 9 lines aren’t shown here.

kernel/seccomp.c+326−18

This diff is large: its 513 lines aren’t shown here.

kernel/smpboot.c+8−17

This diff is large: its 48 lines aren’t shown here.

kernel/sysctl.c+11−16

This diff is large: its 65 lines aren’t shown here.

kernel/trace/blktrace.c+12−6

This diff is large: its 67 lines aren’t shown here.

kernel/trace/ftrace.c+0−14

This diff is large: its 28 lines aren’t shown here.

kernel/trace/trace.c+16−3

This diff is large: its 43 lines aren’t shown here.

kernel/trace/trace.h+2−0

This diff is large: its 9 lines aren’t shown here.

kernel/trace/trace_mmiotrace.c+1−0

This diff is large: its 8 lines aren’t shown here.

kernel/trace/trace_output.c+6−15

This diff is large: its 49 lines aren’t shown here.

kernel/trace/trace_sched_wakeup.c+4−4

This diff is large: its 26 lines aren’t shown here.

kernel/trace/trace_stack.c+0−15

This diff is large: its 32 lines aren’t shown here.

kernel/watchdog.c+238−405

This diff is large: its 887 lines aren’t shown here.

kernel/watchdog_hld.c+111−85

This diff is large: its 241 lines aren’t shown here.

lib/Kconfig.debug+2−1

This diff is large: its 10 lines aren’t shown here.

lib/idr.c+2−2

This diff is large: its 11 lines aren’t shown here.

lib/iov_iter.c+4−2

This diff is large: its 13 lines aren’t shown here.

lib/kobject_uevent.c+41−8

This diff is large: its 65 lines aren’t shown here.

lib/lz4/lz4_decompress.c+2−2

This diff is large: its 11 lines aren’t shown here.

lib/ratelimit.c+3−1

This diff is large: its 11 lines aren’t shown here.

lib/rhashtable.c+5−4

This diff is large: its 23 lines aren’t shown here.

mm/compaction.c+5−8

This diff is large: its 23 lines aren’t shown here.

mm/filemap.c+16−2

This diff is large: its 33 lines aren’t shown here.

mm/ksm.c+4−1

This diff is large: its 21 lines aren’t shown here.

mm/list_lru.c+6−6

This diff is large: its 48 lines aren’t shown here.

mm/madvise.c+10−2

This diff is large: its 29 lines aren’t shown here.

mm/memcontrol.c+17−6

This diff is large: its 60 lines aren’t shown here.

mm/memory.c+1−1

This diff is large: its 9 lines aren’t shown here.

mm/memory_hotplug.c+4−3

This diff is large: its 35 lines aren’t shown here.

mm/oom_kill.c+16−0

This diff is large: its 30 lines aren’t shown here.

mm/page_alloc.c+2−1

This diff is large: its 17 lines aren’t shown here.

mm/percpu-stats.c+1−1

This diff is large: its 9 lines aren’t shown here.

mm/percpu.c+4−0

This diff is large: its 18 lines aren’t shown here.

mm/rodata_test.c+1−1

This diff is large: its 9 lines aren’t shown here.

mm/slab_common.c+15−7

This diff is large: its 49 lines aren’t shown here.

mm/swap.c+2−2

This diff is large: its 18 lines aren’t shown here.

mm/swap_state.c+11−0

This diff is large: its 18 lines aren’t shown here.

mm/z3fold.c+5−5

This diff is large: its 48 lines aren’t shown here.

net/8021q/vlan_core.c+6−0

This diff is large: its 13 lines aren’t shown here.

net/bluetooth/Kconfig+0−10

This diff is large: its 15 lines aren’t shown here.

net/bluetooth/hci_sock.c+0−6

This diff is large: its 28 lines aren’t shown here.

net/ceph/osdmap.c+25−10

This diff is large: its 45 lines aren’t shown here.

net/compat.c+7−0

This diff is large: its 14 lines aren’t shown here.

net/core/dev.c+7−2

This diff is large: its 23 lines aren’t shown here.

net/core/ethtool.c+2−0

This diff is large: its 9 lines aren’t shown here.

net/core/filter.c+23−13

This diff is large: its 99 lines aren’t shown here.

net/core/rtnetlink.c+3−0

This diff is large: its 10 lines aren’t shown here.

net/core/sock.c+6−1

This diff is large: its 27 lines aren’t shown here.

net/dsa/slave.c+18−13

This diff is large: its 47 lines aren’t shown here.

net/ipv4/inet_connection_sock.c+4−2

This diff is large: its 33 lines aren’t shown here.

net/ipv4/inetpeer.c+2−2

This diff is large: its 12 lines aren’t shown here.

net/ipv4/ip_gre.c+7−5

This diff is large: its 53 lines aren’t shown here.

net/ipv4/ip_input.c+15−10

This diff is large: its 54 lines aren’t shown here.

net/ipv4/ip_vti.c+2−1

This diff is large: its 17 lines aren’t shown here.

net/ipv4/route.c+26−20

This diff is large: its 84 lines aren’t shown here.

net/ipv4/tcp_ipv4.c+5−4

This diff is large: its 36 lines aren’t shown here.

net/ipv4/tcp_output.c+9−34

This diff is large: its 64 lines aren’t shown here.

net/ipv4/udp.c+18−6

This diff is large: its 74 lines aren’t shown here.

net/ipv6/addrconf.c+23−9

This diff is large: its 91 lines aren’t shown here.

net/ipv6/ip6_gre.c+12−10

This diff is large: its 44 lines aren’t shown here.

net/ipv6/ip6_tunnel.c+6−2

This diff is large: its 36 lines aren’t shown here.

net/ipv6/ip6_vti.c+2−1

This diff is large: its 17 lines aren’t shown here.

net/ipv6/udp.c+1−0

This diff is large: its 8 lines aren’t shown here.

net/l2tp/l2tp_core.c+10−6

This diff is large: its 39 lines aren’t shown here.

net/l2tp/l2tp_core.h+5−1

This diff is large: its 27 lines aren’t shown here.

net/l2tp/l2tp_eth.c+2−49

This diff is large: its 117 lines aren’t shown here.

net/l2tp/l2tp_ppp.c+4−4

This diff is large: its 16 lines aren’t shown here.

net/netfilter/ipset/ip_set_hash_gen.h+13−1

This diff is large: its 26 lines aren’t shown here.

net/netfilter/nf_nat_core.c+6−6

This diff is large: its 41 lines aren’t shown here.

net/netlink/af_netlink.c+5−2

This diff is large: its 16 lines aren’t shown here.

net/packet/af_packet.c+19−9

This diff is large: its 81 lines aren’t shown here.

net/sched/cls_flower.c+9−6

This diff is large: its 53 lines aren’t shown here.

net/sched/cls_matchall.c+1−0

This diff is large: its 8 lines aren’t shown here.

net/sched/sch_generic.c+1−0

This diff is large: its 8 lines aren’t shown here.

net/sched/sch_hfsc.c+19−4

This diff is large: its 44 lines aren’t shown here.

net/sctp/sctp_diag.c+3−1

This diff is large: its 18 lines aren’t shown here.

net/smc/af_smc.c+9−7

This diff is large: its 56 lines aren’t shown here.

net/smc/smc.h+1−1

This diff is large: its 9 lines aren’t shown here.

net/smc/smc_clc.c+5−5

This diff is large: its 32 lines aren’t shown here.

net/smc/smc_clc.h+1−2

This diff is large: its 10 lines aren’t shown here.

net/smc/smc_close.c+15−12

This diff is large: its 85 lines aren’t shown here.

net/smc/smc_core.c+12−4

This diff is large: its 30 lines aren’t shown here.

net/smc/smc_ib.c+1−0

This diff is large: its 8 lines aren’t shown here.

net/smc/smc_pnet.c+3−1

This diff is large: its 12 lines aren’t shown here.

net/smc/smc_rx.c+2−0

This diff is large: its 9 lines aren’t shown here.

net/smc/smc_tx.c+8−4

This diff is large: its 46 lines aren’t shown here.

net/smc/smc_wr.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/sunrpc/xprtrdma/frwr_ops.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/tipc/msg.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/wireless/nl80211.c+6−0

This diff is large: its 20 lines aren’t shown here.

scripts/Makefile.build+2−0

This diff is large: its 9 lines aren’t shown here.

scripts/checkpatch.pl+1−1

This diff is large: its 9 lines aren’t shown here.

scripts/dtc/dtx_diff+9−13

This diff is large: its 55 lines aren’t shown here.

scripts/mkversion+0−6

This diff is large: its 7 lines aren’t shown here.

scripts/package/Makefile+0−5

This diff is large: its 19 lines aren’t shown here.

scripts/package/builddeb+1−21

This diff is large: its 56 lines aren’t shown here.

scripts/package/mkspec+4−10

This diff is large: its 50 lines aren’t shown here.

scripts/spelling.txt+33−0

This diff is large: its 235 lines aren’t shown here.

security/apparmor/.gitignore+1−0

This diff is large: its 7 lines aren’t shown here.

security/apparmor/Makefile+41−2

This diff is large: its 64 lines aren’t shown here.

security/apparmor/apparmorfs.c+39−6

This diff is large: its 137 lines aren’t shown here.

security/apparmor/domain.c+2−2

This diff is large: its 11 lines aren’t shown here.

security/apparmor/file.c+30−0

This diff is large: its 51 lines aren’t shown here.

security/apparmor/include/apparmor.h+2−0

This diff is large: its 10 lines aren’t shown here.

security/apparmor/include/audit.h+30−9

This diff is large: its 65 lines aren’t shown here.

security/apparmor/include/domain.h+5−0

This diff is large: its 19 lines aren’t shown here.

security/apparmor/include/ipc.h+6−0

This diff is large: its 15 lines aren’t shown here.

security/apparmor/include/label.h+1−0

This diff is large: its 8 lines aren’t shown here.

security/apparmor/include/mount.h+54−0

This diff is large: its 55 lines aren’t shown here.

security/apparmor/include/net.h+114−0

This diff is large: its 115 lines aren’t shown here.

security/apparmor/include/perms.h+3−2

This diff is large: its 13 lines aren’t shown here.

security/apparmor/include/policy.h+13−0

This diff is large: its 41 lines aren’t shown here.

security/apparmor/include/sig_names.h+98−0

This diff is large: its 99 lines aren’t shown here.

security/apparmor/ipc.c+99−0

This diff is large: its 110 lines aren’t shown here.

security/apparmor/label.c+19−17

This diff is large: its 94 lines aren’t shown here.

security/apparmor/lib.c+3−2

This diff is large: its 19 lines aren’t shown here.

security/apparmor/lsm.c+472−0

This diff is large: its 518 lines aren’t shown here.

security/apparmor/mount.c+696−0

This diff is large: its 697 lines aren’t shown here.

security/apparmor/net.c+184−0

This diff is large: its 185 lines aren’t shown here.

security/apparmor/policy.c+87−79

This diff is large: its 180 lines aren’t shown here.

security/apparmor/policy_ns.c+2−0

This diff is large: its 9 lines aren’t shown here.

security/apparmor/policy_unpack.c+87−18

This diff is large: its 259 lines aren’t shown here.

security/commoncap.c+3−3

This diff is large: its 14 lines aren’t shown here.

security/keys/Kconfig+1−3

This diff is large: its 12 lines aren’t shown here.

security/keys/big_key.c+65−74

This diff is large: its 277 lines aren’t shown here.

security/keys/internal.h+1−1

This diff is large: its 9 lines aren’t shown here.

security/keys/key.c+4−2

This diff is large: its 22 lines aren’t shown here.

security/keys/keyctl.c+8−5

This diff is large: its 33 lines aren’t shown here.

security/keys/keyring.c+19−18

This diff is large: its 81 lines aren’t shown here.

security/keys/proc.c+2−6

This diff is large: its 22 lines aren’t shown here.

security/keys/process_keys.c+4−2

This diff is large: its 20 lines aren’t shown here.

security/keys/request_key_auth.c+33−41

This diff is large: its 130 lines aren’t shown here.

security/smack/smack_lsm.c+25−30

This diff is large: its 77 lines aren’t shown here.

sound/core/compress_offload.c+1−2

This diff is large: its 16 lines aren’t shown here.

sound/core/pcm_compat.c+1−0

This diff is large: its 8 lines aren’t shown here.

sound/pci/asihpi/hpioctl.c+8−4

This diff is large: its 38 lines aren’t shown here.

sound/pci/echoaudio/echoaudio.c+3−3

This diff is large: its 42 lines aren’t shown here.

sound/pci/hda/patch_hdmi.c+21−0

This diff is large: its 35 lines aren’t shown here.

sound/usb/card.c+20−0

This diff is large: its 46 lines aren’t shown here.

sound/usb/quirks.c+2−0

This diff is large: its 9 lines aren’t shown here.

sound/usb/usx2y/usb_stream.c+4−2

This diff is large: its 20 lines aren’t shown here.

tools/arch/s390/include/uapi/asm/kvm.h+6−0

This diff is large: its 13 lines aren’t shown here.

tools/arch/x86/include/asm/cpufeatures.h+2−0

This diff is large: its 16 lines aren’t shown here.

tools/arch/x86/include/asm/disabled-features.h+3−1

This diff is large: its 23 lines aren’t shown here.

tools/include/asm-generic/hugetlb_encode.h+34−0

This diff is large: its 35 lines aren’t shown here.

tools/include/uapi/asm-generic/mman-common.h+3−11

This diff is large: its 24 lines aren’t shown here.

tools/include/uapi/drm/drm.h+22−0

This diff is large: its 43 lines aren’t shown here.

tools/include/uapi/drm/i915_drm.h+49−2

This diff is large: its 100 lines aren’t shown here.

tools/include/uapi/linux/bpf.h+20−12

This diff is large: its 72 lines aren’t shown here.

tools/include/uapi/linux/kvm.h+2−1

This diff is large: its 10 lines aren’t shown here.

tools/include/uapi/linux/mman.h+23−1

This diff is large: its 36 lines aren’t shown here.

tools/objtool/Documentation/stack-validation.txt+3−3

This diff is large: its 14 lines aren’t shown here.

tools/objtool/arch/x86/decode.c+11−6

This diff is large: its 38 lines aren’t shown here.

tools/objtool/check.c+29−14

This diff is large: its 54 lines aren’t shown here.

tools/objtool/elf.c+20−13

This diff is large: its 68 lines aren’t shown here.

tools/perf/MANIFEST+2−85

This diff is large: its 98 lines aren’t shown here.

tools/perf/arch/s390/util/Build+0−1

This diff is large: its 6 lines aren’t shown here.

tools/perf/arch/s390/util/sym-handling.c+0−29

This diff is large: its 30 lines aren’t shown here.

tools/perf/util/callchain.c+21−14

This diff is large: its 70 lines aren’t shown here.

tools/perf/util/evsel.c+6−1

This diff is large: its 19 lines aren’t shown here.

tools/perf/util/symbol-elf.c+1−7

This diff is large: its 22 lines aren’t shown here.

tools/perf/util/symbol.h+0−3

This diff is large: its 10 lines aren’t shown here.

tools/perf/util/syscalltbl.c+1−1

This diff is large: its 11 lines aren’t shown here.

tools/testing/nvdimm/test/nfit.c+0−3

This diff is large: its 10 lines aren’t shown here.

tools/testing/selftests/Makefile+11−7

This diff is large: its 67 lines aren’t shown here.

tools/testing/selftests/bpf/bpf_util.h+9−8

This diff is large: its 34 lines aren’t shown here.

tools/testing/selftests/breakpoints/Makefile+4−4

This diff is large: its 19 lines aren’t shown here.

tools/testing/selftests/ftrace/test.d/kprobe/multiple_kprobes.tc+2−0

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/futex/Makefile+6−3

This diff is large: its 29 lines aren’t shown here.

tools/testing/selftests/intel_pstate/Makefile+2−0

This diff is large: its 10 lines aren’t shown here.

tools/testing/selftests/intel_pstate/run.sh+5−6

This diff is large: its 19 lines aren’t shown here.

tools/testing/selftests/lib.mk+40−8

This diff is large: its 100 lines aren’t shown here.

tools/testing/selftests/memfd/run_tests.sh+0−0

File mode changed from 100644 to 100755.

tools/testing/selftests/mqueue/Makefile+2−2

This diff is large: its 11 lines aren’t shown here.

tools/testing/selftests/net/.gitignore+1−0

This diff is large: its 5 lines aren’t shown here.

tools/testing/selftests/net/Makefile+3−3

This diff is large: its 13 lines aren’t shown here.

tools/testing/selftests/net/msg_zerocopy.c+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/net/netdevice.sh+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/net/reuseaddr_conflict.c+114−0

This diff is large: its 115 lines aren’t shown here.

tools/testing/selftests/seccomp/Makefile+13−5

This diff is large: its 22 lines aren’t shown here.

tools/testing/selftests/seccomp/seccomp_benchmark.c+99−0

This diff is large: its 100 lines aren’t shown here.

tools/testing/selftests/seccomp/seccomp_bpf.c+527−101

This diff is large: its 897 lines aren’t shown here.

tools/testing/selftests/sigaltstack/sas.c+4−0

This diff is large: its 12 lines aren’t shown here.

tools/testing/selftests/sync/Makefile+19−5

This diff is large: its 39 lines aren’t shown here.

tools/testing/selftests/timers/set-timer-lat.c+7−6

This diff is large: its 43 lines aren’t shown here.

tools/testing/selftests/watchdog/Makefile+1−6

This diff is large: its 10 lines aren’t shown here.

virt/kvm/eventfd.c+0−2

This diff is large: its 9 lines aren’t shown here.

@@ -39,8 +39,8 @@ up. · 38 unmodified lines
39	Although MT wq wasted a lot of resource, the level of concurrency	39	Although MT wq wasted a lot of resource, the level of concurrency
40	provided was unsatisfactory. The limitation was common to both ST and	40	provided was unsatisfactory. The limitation was common to both ST and
41	MT wq albeit less severe on MT. Each wq maintained its own separate	41	MT wq albeit less severe on MT. Each wq maintained its own separate
42	worker pool. A MT wq could provide only one execution context per CPU	42	worker pool. An MT wq could provide only one execution context per CPU
43	while a ST wq one for the whole system. Work items had to compete for	43	while an ST wq one for the whole system. Work items had to compete for
44	those very limited execution contexts leading to various problems	44	those very limited execution contexts leading to various problems
45	including proneness to deadlocks around the single execution context.	45	including proneness to deadlocks around the single execution context.
46		46
@@ -151,7 +151,7 @@ Application Programming Interface (API) · 104 unmodified lines
151		151
152	``alloc_workqueue()`` allocates a wq. The original	152	``alloc_workqueue()`` allocates a wq. The original
153	``create_*workqueue()`` functions are deprecated and scheduled for	153	``create_*workqueue()`` functions are deprecated and scheduled for
154	removal. ``alloc_workqueue()`` takes three arguments - @``name``,	154	removal. ``alloc_workqueue()`` takes three arguments - ``@name``,
155	``@flags`` and ``@max_active``. ``@name`` is the name of the wq and	155	``@flags`` and ``@max_active``. ``@name`` is the name of the wq and
156	also used as the name of the rescuer thread if there is one.	156	also used as the name of the rescuer thread if there is one.
157		157
@@ -197,7 +197,7 @@ resources, scheduled and executed. · 39 unmodified lines
197	served by worker threads with elevated nice level.	197	served by worker threads with elevated nice level.
198		198
199	Note that normal and highpri worker-pools don't interact with	199	Note that normal and highpri worker-pools don't interact with
200	each other. Each maintain its separate pool of workers and	200	each other. Each maintains its separate pool of workers and
201	implements concurrency management among its workers.	201	implements concurrency management among its workers.
202		202
203	``WQ_CPU_INTENSIVE``	203	``WQ_CPU_INTENSIVE``
@@ -249,8 +249,8 @@ unbound worker-pools and only one work item could be active at any given · 45 unmodified lines
249	time thus achieving the same ordering property as ST wq.	249	time thus achieving the same ordering property as ST wq.
250		250
251	In the current implementation the above configuration only guarantees	251	In the current implementation the above configuration only guarantees
252	ST behavior within a given NUMA node. Instead alloc_ordered_queue should	252	ST behavior within a given NUMA node. Instead ``alloc_ordered_queue()`` should
253	be used to achieve system wide ST behavior.	253	be used to achieve system-wide ST behavior.
254		254
255		255
256	Example Execution Scenarios	256	Example Execution Scenarios