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Merge tag 'mlx5-updates-2019-09-01-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

Saeed Mahameed says: ==================== mlx5-updates-2019-09-01 (Software steering support) Abstract: -------- Mellanox ConnetX devices supports packet matching, packet modification and redirection. These functionalities are also referred to as flow-steering. To configure a steering rule, the rule is written to the device owned memory, this memory is accessed and cached by the device when processing a packet. Steering rules are constructed from multiple steering entries (STE). Rules are configured using the Firmware command interface. The Firmware processes the given driver command and translates them to STEs, then writes them to the device memory in the current steering tables. This process is slow due to the architecture of the command interface and the processing complexity of each rule. The highlight of this patchset is to cut the middle man (The firmware) and do steering rules programming into device directly from the driver, with no firmware intervention whatsoever. Motivation: ----------- Software (driver managed) steering allows for high rule insertion rates compared to the FW steering described above, this is achieved by using internal RDMA writes to the device owned memory instead of the slow command interface to program steering rules. Software (driver managed) steering, doesn't depend on new FW for new steering functionality, new implementations can be done in the driver skipping the FW layer. Performance: ------------ The insertion rate on a single core using the new approach allows programming ~300K rules per sec. (Done via direct raw test to the new mlx5 sw steering layer, without any kernel layer involved). Test: TC L2 rules 33K/s with Software steering (this patchset). 5K/s with FW and current driver. This will improve OVS based solution performance. Architecture and implementation details: ---------------------------------------- Software steering will be dynamically selected via devlink device parameter. Example: $ devlink dev param show pci/0000:06:00.0 name flow_steering_mode pci/0000:06:00.0: name flow_steering_mode type driver-specific values: cmode runtime value smfs mlx5 software steering module a.k.a (DR - Direct Rule) is implemented and contained in mlx5/core/steering directory and controlled by MLX5_SW_STEERING kconfig flag. mlx5 core steering layer (fs_core) already provides a shim layer for implementing different steering mechanisms, software steering will leverage that as seen at the end of this series. When Software Steering for a specific steering domain (NIC/RDMA/Vport/ESwitch, etc ..) is supported, it will cause rules targeting this domain to be created using SW steering instead of FW. The implementation includes: Domain - The steering domain is the object that all other object resides in. It holds the memory allocator, send engine, locks and other shared data needed by lower objects such as table, matcher, rule, action. Each domain can contain multiple tables. Domain is equivalent to namespaces e.g (NIC/RDMA/Vport/ESwitch, etc ..) as implemented currently in mlx5_core fs_core (flow steering core). Table - Table objects are used for holding multiple matchers, each table has a level used to prevent processing loops. Packets are being directed to this table once it is set as the root table, this is done by fs_core using a FW command. A packet is being processed inside the table matcher by matcher until a successful hit, otherwise the packet will perform the default action. Matcher - Matchers objects are used to specify the fields mask for matching when processing a packet. A matcher belongs to a table, each matcher can hold multiple rules, each rule with different matching values corresponding to the matcher mask. Each matcher has a priority used for rule processing order inside the table. Action - Action objects are created to specify different steering actions such as count, reformat (encapsulate, decapsulate, ...), modify header, forward to table and many other actions. When creating a rule a sequence of actions can be provided to be executed on a successful match. Rule - Rule objects are used to specify a specific match on packets as well as the actions that should be executed. A rule belongs to a matcher. STE - This layer is used to hold the specific STE format for the device and to convert the requested rule to STEs. Each rule is constructed of an STE chain, Multiple rules construct a steering graph. Each node in the graph is a hash table containing multiple STEs. The index of each STE in the hash table is being calculated using a CRC32 hash function. Memory pool - Used for managing and caching device owned memory for rule insertion. The memory is being allocated using DM (device memory) API. Communication with device - layer for standard RDMA operation using RC QP to configure the device steering. Command utility - This module holds all of the FW commands that are required for SW steering to function. Patch planning and files: ------------------------- 1) First patch, adds the support to Add flow steering actions to fs_cmd shim layer. 2) Next 12 patch will add a file per each Software steering functionality/module as described above. (See patches with title: DR, *) 3) Add CONFIG_MLX5_SW_STEERING for software steering support and enable build with the new files 4) Next two patches will add the support for software steering in mlx5 steering shim layer net/mlx5: Add API to set the namespace steering mode net/mlx5: Add direct rule fs_cmd implementation 5) Last two patches will add the new devlink parameter to select mlx5 steering mode, will be valid only for switchdev mode for now. Two modes are supported: 1. DMFS - Device managed flow steering 2. SMFS - Software/Driver managed flow steering. In the DMFS mode, the HW steering entities are created through the FW. In the SMFS mode this entities are created though the driver directly. The driver will use the devlink steering mode only if the steering domain supports it, for now SMFS will manages only the switchdev eswitch steering domain. User command examples: - Set SMFS flow steering mode:: $ devlink dev param set pci/0000:06:00.0 name flow_steering_mode value "smfs" cmode runtime - Read device flow steering mode:: $ devlink dev param show pci/0000:06:00.0 name flow_steering_mode pci/0000:06:00.0: name flow_steering_mode type driver-specific values: cmode runtime value smfs ====================

David S. Miller committed 7 years ago

Commit 94810bd2 parents 67538eb e890acd44 files · +12464 −371Browse files

Showing the changes to include/linux (5 of 44 files). Show all

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5 files
  1. include/linux/mlx5/device.h +7 −0
  2. include/linux/mlx5/driver.h +14 −0
  3. include/linux/mlx5/eswitch.h +7 −1
  4. include/linux/mlx5/fs.h +16 −17
  5. include/linux/mlx5/mlx5_ifc.h +198 −37
include/linux/mlx5/device.h+7−0
@@ -1162,6 +1162,9 @@ enum mlx5_qcam_feature_groups { · 1161 unmodified lines
1162#define MLX5_CAP_FLOWTABLE(mdev, cap) \1162#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1163 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)1163 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1164 1164
1165#define MLX5_CAP64_FLOWTABLE(mdev, cap) \
1166 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1167
1165#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \1168#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1166 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)1169 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1167 1170
@@ -1225,6 +1228,10 @@ enum mlx5_qcam_feature_groups { · 57 unmodified lines
1225 MLX5_GET(e_switch_cap, \1228 MLX5_GET(e_switch_cap, \
1226 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)1229 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1227 1230
1231#define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
1232 MLX5_GET64(flow_table_eswitch_cap, \
1233 (mdev)->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1234
1228#define MLX5_CAP_ESW_MAX(mdev, cap) \1235#define MLX5_CAP_ESW_MAX(mdev, cap) \
1229 MLX5_GET(e_switch_cap, \1236 MLX5_GET(e_switch_cap, \
1230 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)1237 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
include/linux/mlx5/driver.h+14−0
@@ -626,6 +626,11 @@ struct mlx5e_resources { · 625 unmodified lines
626 struct mlx5_sq_bfreg bfreg;626 struct mlx5_sq_bfreg bfreg;
627};627};
628 628
629enum mlx5_sw_icm_type {
630 MLX5_SW_ICM_TYPE_STEERING,
631 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
632};
633
629#define MLX5_MAX_RESERVED_GIDS 8634#define MLX5_MAX_RESERVED_GIDS 8
630 635
631struct mlx5_rsvd_gids {636struct mlx5_rsvd_gids {
@@ -657,11 +662,15 @@ struct mlx5_clock { · 25 unmodified lines
657 struct mlx5_pps pps_info;662 struct mlx5_pps pps_info;
658};663};
659 664
665struct mlx5_dm;
660struct mlx5_fw_tracer;666struct mlx5_fw_tracer;
661struct mlx5_vxlan;667struct mlx5_vxlan;
662struct mlx5_geneve;668struct mlx5_geneve;
663struct mlx5_hv_vhca;669struct mlx5_hv_vhca;
664 670
671#define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
672#define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
673
665struct mlx5_core_dev {674struct mlx5_core_dev {
666 struct device *device;675 struct device *device;
667 enum mlx5_coredev_type coredev_type;676 enum mlx5_coredev_type coredev_type;
@@ -695,6 +704,7 @@ struct mlx5_core_dev { · 27 unmodified lines
695 atomic_t num_qps;704 atomic_t num_qps;
696 u32 issi;705 u32 issi;
697 struct mlx5e_resources mlx5e_res;706 struct mlx5e_resources mlx5e_res;
707 struct mlx5_dm *dm;
698 struct mlx5_vxlan *vxlan;708 struct mlx5_vxlan *vxlan;
699 struct mlx5_geneve *geneve;709 struct mlx5_geneve *geneve;
700 struct {710 struct {
@@ -1078,6 +1088,10 @@ int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, · 377 unmodified lines
1078 size_t *offsets);1088 size_t *offsets);
1079struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);1089struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1080void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);1090void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1091int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1092 u64 length, u16 uid, phys_addr_t *addr, u32 *obj_id);
1093int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1094 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1081 1095
1082#ifdef CONFIG_MLX5_CORE_IPOIB1096#ifdef CONFIG_MLX5_CORE_IPOIB
1083struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,1097struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
include/linux/mlx5/eswitch.h+7−1
@@ -60,7 +60,6 @@ void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw, · 59 unmodified lines
60struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,60struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
61 u16 vport_num);61 u16 vport_num);
62void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type);62void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type);
63u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw);
64struct mlx5_flow_handle *63struct mlx5_flow_handle *
65mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw,64mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw,
66 u16 vport_num, u32 sqn);65 u16 vport_num, u32 sqn);
@@ -74,7 +73,14 @@ mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev); · 7 unmodified lines
74bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw);73bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw);
75u32 mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw,74u32 mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw,
76 u16 vport_num);75 u16 vport_num);
76u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw);
77#else /* CONFIG_MLX5_ESWITCH */77#else /* CONFIG_MLX5_ESWITCH */
78
79static inline u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw)
80{
81 return MLX5_ESWITCH_NONE;
82}
83
78static inline enum devlink_eswitch_encap_mode84static inline enum devlink_eswitch_encap_mode
79mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev)85mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev)
80{86{
include/linux/mlx5/fs.h+16−17
@@ -84,6 +84,8 @@ enum { · 83 unmodified lines
84 FDB_SLOW_PATH,84 FDB_SLOW_PATH,
85};85};
86 86
87struct mlx5_pkt_reformat;
88struct mlx5_modify_hdr;
87struct mlx5_flow_table;89struct mlx5_flow_table;
88struct mlx5_flow_group;90struct mlx5_flow_group;
89struct mlx5_flow_namespace;91struct mlx5_flow_namespace;
@@ -121,7 +123,7 @@ struct mlx5_flow_destination { · 31 unmodified lines
121 struct {123 struct {
122 u16 num;124 u16 num;
123 u16 vhca_id;125 u16 vhca_id;
124 u32 reformat_id;126 struct mlx5_pkt_reformat *pkt_reformat;
125 u8 flags;127 u8 flags;
126 } vport;128 } vport;
127 };129 };
@@ -195,8 +197,8 @@ enum { · 67 unmodified lines
195 197
196struct mlx5_flow_act {198struct mlx5_flow_act {
197 u32 action;199 u32 action;
198 u32 reformat_id;200 struct mlx5_modify_hdr *modify_hdr;
199 u32 modify_id;201 struct mlx5_pkt_reformat *pkt_reformat;
200 uintptr_t esp_id;202 uintptr_t esp_id;
201 u32 flags;203 u32 flags;
202 struct mlx5_fs_vlan vlan[MLX5_FS_VLAN_DEPTH];204 struct mlx5_fs_vlan vlan[MLX5_FS_VLAN_DEPTH];
@@ -205,8 +207,6 @@ struct mlx5_flow_act { · 2 unmodified lines
205 207
206#define MLX5_DECLARE_FLOW_ACT(name) \208#define MLX5_DECLARE_FLOW_ACT(name) \
207 struct mlx5_flow_act name = { .action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,\209 struct mlx5_flow_act name = { .action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,\
208 .reformat_id = 0, \
209 .modify_id = 0, \
210 .flags = 0, }210 .flags = 0, }
211 211
212/* Single destination per rule.212/* Single destination per rule.
@@ -236,19 +236,18 @@ u32 mlx5_fc_id(struct mlx5_fc *counter); · 23 unmodified lines
236int mlx5_fs_add_rx_underlay_qpn(struct mlx5_core_dev *dev, u32 underlay_qpn);236int mlx5_fs_add_rx_underlay_qpn(struct mlx5_core_dev *dev, u32 underlay_qpn);
237int mlx5_fs_remove_rx_underlay_qpn(struct mlx5_core_dev *dev, u32 underlay_qpn);237int mlx5_fs_remove_rx_underlay_qpn(struct mlx5_core_dev *dev, u32 underlay_qpn);
238 238
239int mlx5_modify_header_alloc(struct mlx5_core_dev *dev,239struct mlx5_modify_hdr *mlx5_modify_header_alloc(struct mlx5_core_dev *dev,
240 u8 namespace, u8 num_actions,240 u8 ns_type, u8 num_actions,
241 void *modify_actions, u32 *modify_header_id);241 void *modify_actions);
242void mlx5_modify_header_dealloc(struct mlx5_core_dev *dev,242void mlx5_modify_header_dealloc(struct mlx5_core_dev *dev,
243 u32 modify_header_id);243 struct mlx5_modify_hdr *modify_hdr);
244 244
245int mlx5_packet_reformat_alloc(struct mlx5_core_dev *dev,245struct mlx5_pkt_reformat *mlx5_packet_reformat_alloc(struct mlx5_core_dev *dev,
246 int reformat_type,246 int reformat_type,
247 size_t size,247 size_t size,
248 void *reformat_data,248 void *reformat_data,
249 enum mlx5_flow_namespace_type namespace,249 enum mlx5_flow_namespace_type ns_type);
250 u32 *packet_reformat_id);
251void mlx5_packet_reformat_dealloc(struct mlx5_core_dev *dev,250void mlx5_packet_reformat_dealloc(struct mlx5_core_dev *dev,
252 u32 packet_reformat_id);251 struct mlx5_pkt_reformat *reformat);
253 252
254#endif253#endif
include/linux/mlx5/mlx5_ifc.h+198−37
@@ -282,6 +282,7 @@ enum { · 281 unmodified lines
282 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,282 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
283 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,283 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
284 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,284 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
285 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
285 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,286 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
286 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,287 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
287 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,288 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
@@ -485,7 +486,11 @@ union mlx5_ifc_gre_key_bits { · 197 unmodified lines
485};486};
486 487
487struct mlx5_ifc_fte_match_set_misc_bits {488struct mlx5_ifc_fte_match_set_misc_bits {
488 u8 reserved_at_0[0x8];489 u8 gre_c_present[0x1];
490 u8 reserved_auto1[0x1];
491 u8 gre_k_present[0x1];
492 u8 gre_s_present[0x1];
493 u8 source_vhca_port[0x4];
489 u8 source_sqn[0x18];494 u8 source_sqn[0x18];
490 495
491 u8 source_eswitch_owner_vhca_id[0x10];496 u8 source_eswitch_owner_vhca_id[0x10];
@@ -565,12 +570,38 @@ struct mlx5_ifc_fte_match_set_misc2_bits { · 73 unmodified lines
565 570
566 u8 metadata_reg_a[0x20];571 u8 metadata_reg_a[0x20];
567 572
568 u8 reserved_at_1a0[0x60];573 u8 metadata_reg_b[0x20];
574
575 u8 reserved_at_1c0[0x40];
569};576};
570 577
571struct mlx5_ifc_fte_match_set_misc3_bits {578struct mlx5_ifc_fte_match_set_misc3_bits {
572 u8 reserved_at_0[0x120];579 u8 inner_tcp_seq_num[0x20];
580
581 u8 outer_tcp_seq_num[0x20];
582
583 u8 inner_tcp_ack_num[0x20];
584
585 u8 outer_tcp_ack_num[0x20];
586
587 u8 reserved_at_80[0x8];
588 u8 outer_vxlan_gpe_vni[0x18];
589
590 u8 outer_vxlan_gpe_next_protocol[0x8];
591 u8 outer_vxlan_gpe_flags[0x8];
592 u8 reserved_at_b0[0x10];
593
594 u8 icmp_header_data[0x20];
595
596 u8 icmpv6_header_data[0x20];
597
598 u8 icmp_type[0x8];
599 u8 icmp_code[0x8];
600 u8 icmpv6_type[0x8];
601 u8 icmpv6_code[0x8];
602
573 u8 geneve_tlv_option_0_data[0x20];603 u8 geneve_tlv_option_0_data[0x20];
604
574 u8 reserved_at_140[0xc0];605 u8 reserved_at_140[0xc0];
575};606};
576 607
@@ -666,7 +697,15 @@ struct mlx5_ifc_flow_table_nic_cap_bits { · 89 unmodified lines
666 697
667 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;698 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
668 699
669 u8 reserved_at_e00[0x7200];700 u8 reserved_at_e00[0x1200];
701
702 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
703
704 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
705
706 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
707
708 u8 reserved_at_20c0[0x5f40];
670};709};
671 710
672enum {711enum {
@@ -698,7 +737,17 @@ struct mlx5_ifc_flow_table_eswitch_cap_bits { · 25 unmodified lines
698 737
699 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;738 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
700 739
701 u8 reserved_at_800[0x7800];740 u8 reserved_at_800[0x1000];
741
742 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
743
744 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
745
746 u8 sw_steering_uplink_icm_address_rx[0x40];
747
748 u8 sw_steering_uplink_icm_address_tx[0x40];
749
750 u8 reserved_at_1900[0x6700];
702};751};
703 752
704enum {753enum {
@@ -849,6 +898,25 @@ struct mlx5_ifc_roce_cap_bits { · 144 unmodified lines
849 u8 reserved_at_100[0x700];898 u8 reserved_at_100[0x700];
850};899};
851 900
901struct mlx5_ifc_sync_steering_in_bits {
902 u8 opcode[0x10];
903 u8 uid[0x10];
904
905 u8 reserved_at_20[0x10];
906 u8 op_mod[0x10];
907
908 u8 reserved_at_40[0xc0];
909};
910
911struct mlx5_ifc_sync_steering_out_bits {
912 u8 status[0x8];
913 u8 reserved_at_8[0x18];
914
915 u8 syndrome[0x20];
916
917 u8 reserved_at_40[0x40];
918};
919
852struct mlx5_ifc_device_mem_cap_bits {920struct mlx5_ifc_device_mem_cap_bits {
853 u8 memic[0x1];921 u8 memic[0x1];
854 u8 reserved_at_1[0x1f];922 u8 reserved_at_1[0x1f];
@@ -1041,6 +1109,12 @@ enum { · 186 unmodified lines
1041 MLX5_CAP_UMR_FENCE_NONE = 0x2,1109 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1042};1110};
1043 1111
1112enum {
1113 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1114 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1115 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1116};
1117
1044enum {1118enum {
1045 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,1119 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1046 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,1120 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
@@ -1414,7 +1488,14 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 367 unmodified lines
1414 1488
1415 u8 reserved_at_6c0[0x4];1489 u8 reserved_at_6c0[0x4];
1416 u8 flex_parser_id_geneve_tlv_option_0[0x4];1490 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1417 u8 reserved_at_6c8[0x28];1491 u8 flex_parser_id_icmp_dw1[0x4];
1492 u8 flex_parser_id_icmp_dw0[0x4];
1493 u8 flex_parser_id_icmpv6_dw1[0x4];
1494 u8 flex_parser_id_icmpv6_dw0[0x4];
1495 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1496 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1497
1498 u8 reserved_at_6e0[0x10];
1418 u8 sf_base_id[0x10];1499 u8 sf_base_id[0x10];
1419 1500
1420 u8 reserved_at_700[0x80];1501 u8 reserved_at_700[0x80];
@@ -2652,6 +2733,7 @@ union mlx5_ifc_hca_cap_union_bits { · 1231 unmodified lines
2652 struct mlx5_ifc_debug_cap_bits debug_cap;2733 struct mlx5_ifc_debug_cap_bits debug_cap;
2653 struct mlx5_ifc_fpga_cap_bits fpga_cap;2734 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2654 struct mlx5_ifc_tls_cap_bits tls_cap;2735 struct mlx5_ifc_tls_cap_bits tls_cap;
2736 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2655 u8 reserved_at_0[0x8000];2737 u8 reserved_at_0[0x8000];
2656};2738};
2657 2739
@@ -3255,7 +3337,11 @@ struct mlx5_ifc_esw_vport_context_bits { · 597 unmodified lines
3255 u8 cvlan_pcp[0x3];3337 u8 cvlan_pcp[0x3];
3256 u8 cvlan_id[0xc];3338 u8 cvlan_id[0xc];
3257 3339
3258 u8 reserved_at_60[0x7a0];3340 u8 reserved_at_60[0x720];
3341
3342 u8 sw_steering_vport_icm_address_rx[0x40];
3343
3344 u8 sw_steering_vport_icm_address_tx[0x40];
3259};3345};
3260 3346
3261enum {3347enum {
@@ -4941,23 +5027,98 @@ struct mlx5_ifc_query_hca_cap_in_bits { · 1679 unmodified lines
4941 u8 reserved_at_20[0x10];5027 u8 reserved_at_20[0x10];
4942 u8 op_mod[0x10];5028 u8 op_mod[0x10];
4943 5029
4944 u8 reserved_at_40[0x40];5030 u8 other_function[0x1];
5031 u8 reserved_at_41[0xf];
5032 u8 function_id[0x10];
5033
5034 u8 reserved_at_60[0x20];
4945};5035};
4946 5036
4947struct mlx5_ifc_query_flow_table_out_bits {5037struct mlx5_ifc_other_hca_cap_bits {
5038 u8 roce[0x1];
5039 u8 reserved_0[0x27f];
5040};
5041
5042struct mlx5_ifc_query_other_hca_cap_out_bits {
4948 u8 status[0x8];5043 u8 status[0x8];
4949 u8 reserved_at_8[0x18];5044 u8 reserved_0[0x18];
4950 5045
4951 u8 syndrome[0x20];5046 u8 syndrome[0x20];
4952 5047
4953 u8 reserved_at_40[0x80];5048 u8 reserved_1[0x40];
4954 5049
4955 u8 reserved_at_c0[0x8];5050 struct mlx5_ifc_other_hca_cap_bits other_capability;
5051};
5052
5053struct mlx5_ifc_query_other_hca_cap_in_bits {
5054 u8 opcode[0x10];
5055 u8 reserved_0[0x10];
5056
5057 u8 reserved_1[0x10];
5058 u8 op_mod[0x10];
5059
5060 u8 reserved_2[0x10];
5061 u8 function_id[0x10];
5062
5063 u8 reserved_3[0x20];
5064};
5065
5066struct mlx5_ifc_modify_other_hca_cap_out_bits {
5067 u8 status[0x8];
5068 u8 reserved_0[0x18];
5069
5070 u8 syndrome[0x20];
5071
5072 u8 reserved_1[0x40];
5073};
5074
5075struct mlx5_ifc_modify_other_hca_cap_in_bits {
5076 u8 opcode[0x10];
5077 u8 reserved_0[0x10];
5078
5079 u8 reserved_1[0x10];
5080 u8 op_mod[0x10];
5081
5082 u8 reserved_2[0x10];
5083 u8 function_id[0x10];
5084 u8 field_select[0x20];
5085
5086 struct mlx5_ifc_other_hca_cap_bits other_capability;
5087};
5088
5089struct mlx5_ifc_flow_table_context_bits {
5090 u8 reformat_en[0x1];
5091 u8 decap_en[0x1];
5092 u8 sw_owner[0x1];
5093 u8 termination_table[0x1];
5094 u8 table_miss_action[0x4];
4956 u8 level[0x8];5095 u8 level[0x8];
4957 u8 reserved_at_d0[0x8];5096 u8 reserved_at_10[0x8];
4958 u8 log_size[0x8];5097 u8 log_size[0x8];
4959 5098
4960 u8 reserved_at_e0[0x120];5099 u8 reserved_at_20[0x8];
5100 u8 table_miss_id[0x18];
5101
5102 u8 reserved_at_40[0x8];
5103 u8 lag_master_next_table_id[0x18];
5104
5105 u8 reserved_at_60[0x60];
5106
5107 u8 sw_owner_icm_root_1[0x40];
5108
5109 u8 sw_owner_icm_root_0[0x40];
5110
5111};
5112
5113struct mlx5_ifc_query_flow_table_out_bits {
5114 u8 status[0x8];
5115 u8 reserved_at_8[0x18];
5116
5117 u8 syndrome[0x20];
5118
5119 u8 reserved_at_40[0x80];
5120
5121 struct mlx5_ifc_flow_table_context_bits flow_table_context;
4961};5122};
4962 5123
4963struct mlx5_ifc_query_flow_table_in_bits {5124struct mlx5_ifc_query_flow_table_in_bits {
@@ -5227,7 +5388,7 @@ struct mlx5_ifc_alloc_packet_reformat_context_out_bits { · 263 unmodified lines
5227 u8 reserved_at_60[0x20];5388 u8 reserved_at_60[0x20];
5228};5389};
5229 5390
5230enum {5391enum mlx5_reformat_ctx_type {
5231 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,5392 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5232 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,5393 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5233 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,5394 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
@@ -5323,7 +5484,16 @@ enum { · 89 unmodified lines
5323 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,5484 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5324 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,5485 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5325 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,5486 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5487 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5488 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
5326 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,5489 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5490 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5491 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5492 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5493 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5494 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5495 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5496 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5327};5497};
5328 5498
5329struct mlx5_ifc_alloc_modify_header_context_out_bits {5499struct mlx5_ifc_alloc_modify_header_context_out_bits {
@@ -7371,35 +7541,26 @@ struct mlx5_ifc_create_mkey_in_bits { · 2041 unmodified lines
7371 u8 klm_pas_mtt[0][0x20];7541 u8 klm_pas_mtt[0][0x20];
7372};7542};
7373 7543
7544enum {
7545 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7546 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7547 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7548 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7549 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7550 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7551 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7552};
7553
7374struct mlx5_ifc_create_flow_table_out_bits {7554struct mlx5_ifc_create_flow_table_out_bits {
7375 u8 status[0x8];7555 u8 status[0x8];
7376 u8 reserved_at_8[0x18];7556 u8 icm_address_63_40[0x18];
7377 7557
7378 u8 syndrome[0x20];7558 u8 syndrome[0x20];
7379 7559
7380 u8 reserved_at_40[0x8];7560 u8 icm_address_39_32[0x8];
7381 u8 table_id[0x18];7561 u8 table_id[0x18];
7382 7562
7383 u8 reserved_at_60[0x20];7563 u8 icm_address_31_0[0x20];
7384};
7385
7386struct mlx5_ifc_flow_table_context_bits {
7387 u8 reformat_en[0x1];
7388 u8 decap_en[0x1];
7389 u8 reserved_at_2[0x1];
7390 u8 termination_table[0x1];
7391 u8 table_miss_action[0x4];
7392 u8 level[0x8];
7393 u8 reserved_at_10[0x8];
7394 u8 log_size[0x8];
7395
7396 u8 reserved_at_20[0x8];
7397 u8 table_miss_id[0x18];
7398
7399 u8 reserved_at_40[0x8];
7400 u8 lag_master_next_table_id[0x18];
7401
7402 u8 reserved_at_60[0xe0];
7403};7564};
7404 7565
7405struct mlx5_ifc_create_flow_table_in_bits {7566struct mlx5_ifc_create_flow_table_in_bits {

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