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Merge tag 'mlx5-updates-2019-09-01-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

Saeed Mahameed says: ==================== mlx5-updates-2019-09-01 (Software steering support) Abstract: -------- Mellanox ConnetX devices supports packet matching, packet modification and redirection. These functionalities are also referred to as flow-steering. To configure a steering rule, the rule is written to the device owned memory, this memory is accessed and cached by the device when processing a packet. Steering rules are constructed from multiple steering entries (STE). Rules are configured using the Firmware command interface. The Firmware processes the given driver command and translates them to STEs, then writes them to the device memory in the current steering tables. This process is slow due to the architecture of the command interface and the processing complexity of each rule. The highlight of this patchset is to cut the middle man (The firmware) and do steering rules programming into device directly from the driver, with no firmware intervention whatsoever. Motivation: ----------- Software (driver managed) steering allows for high rule insertion rates compared to the FW steering described above, this is achieved by using internal RDMA writes to the device owned memory instead of the slow command interface to program steering rules. Software (driver managed) steering, doesn't depend on new FW for new steering functionality, new implementations can be done in the driver skipping the FW layer. Performance: ------------ The insertion rate on a single core using the new approach allows programming ~300K rules per sec. (Done via direct raw test to the new mlx5 sw steering layer, without any kernel layer involved). Test: TC L2 rules 33K/s with Software steering (this patchset). 5K/s with FW and current driver. This will improve OVS based solution performance. Architecture and implementation details: ---------------------------------------- Software steering will be dynamically selected via devlink device parameter. Example: $ devlink dev param show pci/0000:06:00.0 name flow_steering_mode pci/0000:06:00.0: name flow_steering_mode type driver-specific values: cmode runtime value smfs mlx5 software steering module a.k.a (DR - Direct Rule) is implemented and contained in mlx5/core/steering directory and controlled by MLX5_SW_STEERING kconfig flag. mlx5 core steering layer (fs_core) already provides a shim layer for implementing different steering mechanisms, software steering will leverage that as seen at the end of this series. When Software Steering for a specific steering domain (NIC/RDMA/Vport/ESwitch, etc ..) is supported, it will cause rules targeting this domain to be created using SW steering instead of FW. The implementation includes: Domain - The steering domain is the object that all other object resides in. It holds the memory allocator, send engine, locks and other shared data needed by lower objects such as table, matcher, rule, action. Each domain can contain multiple tables. Domain is equivalent to namespaces e.g (NIC/RDMA/Vport/ESwitch, etc ..) as implemented currently in mlx5_core fs_core (flow steering core). Table - Table objects are used for holding multiple matchers, each table has a level used to prevent processing loops. Packets are being directed to this table once it is set as the root table, this is done by fs_core using a FW command. A packet is being processed inside the table matcher by matcher until a successful hit, otherwise the packet will perform the default action. Matcher - Matchers objects are used to specify the fields mask for matching when processing a packet. A matcher belongs to a table, each matcher can hold multiple rules, each rule with different matching values corresponding to the matcher mask. Each matcher has a priority used for rule processing order inside the table. Action - Action objects are created to specify different steering actions such as count, reformat (encapsulate, decapsulate, ...), modify header, forward to table and many other actions. When creating a rule a sequence of actions can be provided to be executed on a successful match. Rule - Rule objects are used to specify a specific match on packets as well as the actions that should be executed. A rule belongs to a matcher. STE - This layer is used to hold the specific STE format for the device and to convert the requested rule to STEs. Each rule is constructed of an STE chain, Multiple rules construct a steering graph. Each node in the graph is a hash table containing multiple STEs. The index of each STE in the hash table is being calculated using a CRC32 hash function. Memory pool - Used for managing and caching device owned memory for rule insertion. The memory is being allocated using DM (device memory) API. Communication with device - layer for standard RDMA operation using RC QP to configure the device steering. Command utility - This module holds all of the FW commands that are required for SW steering to function. Patch planning and files: ------------------------- 1) First patch, adds the support to Add flow steering actions to fs_cmd shim layer. 2) Next 12 patch will add a file per each Software steering functionality/module as described above. (See patches with title: DR, *) 3) Add CONFIG_MLX5_SW_STEERING for software steering support and enable build with the new files 4) Next two patches will add the support for software steering in mlx5 steering shim layer net/mlx5: Add API to set the namespace steering mode net/mlx5: Add direct rule fs_cmd implementation 5) Last two patches will add the new devlink parameter to select mlx5 steering mode, will be valid only for switchdev mode for now. Two modes are supported: 1. DMFS - Device managed flow steering 2. SMFS - Software/Driver managed flow steering. In the DMFS mode, the HW steering entities are created through the FW. In the SMFS mode this entities are created though the driver directly. The driver will use the devlink steering mode only if the steering domain supports it, for now SMFS will manages only the switchdev eswitch steering domain. User command examples: - Set SMFS flow steering mode:: $ devlink dev param set pci/0000:06:00.0 name flow_steering_mode value "smfs" cmode runtime - Read device flow steering mode:: $ devlink dev param show pci/0000:06:00.0 name flow_steering_mode pci/0000:06:00.0: name flow_steering_mode type driver-specific values: cmode runtime value smfs ====================

David S. Miller committed 7 years ago

Commit 94810bd2 parents 67538eb e890acd44 files · +12464 −371Browse files

Showing the changes to include/linux (5 of 44 files). Show all

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5 files
  1. include/linux/mlx5/device.h +7 −0
  2. include/linux/mlx5/driver.h +14 −0
  3. include/linux/mlx5/eswitch.h +7 −1
  4. include/linux/mlx5/fs.h +16 −17
  5. include/linux/mlx5/mlx5_ifc.h +198 −37
include/linux/mlx5/device.h+7−0
@@ -1162,6 +1162,9 @@ enum mlx5_qcam_feature_groups { · 1161 unmodified lines
11621162 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
11631163 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
11641164
1165+#define MLX5_CAP64_FLOWTABLE(mdev, cap) \
1166+ MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1167+
11651168 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
11661169 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
11671170
@@ -1225,6 +1228,10 @@ enum mlx5_qcam_feature_groups { · 57 unmodified lines
12251228 MLX5_GET(e_switch_cap, \
12261229 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
12271230
1231+#define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
1232+ MLX5_GET64(flow_table_eswitch_cap, \
1233+ (mdev)->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1234+
12281235 #define MLX5_CAP_ESW_MAX(mdev, cap) \
12291236 MLX5_GET(e_switch_cap, \
12301237 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
include/linux/mlx5/driver.h+14−0
@@ -626,6 +626,11 @@ struct mlx5e_resources { · 625 unmodified lines
626626 struct mlx5_sq_bfreg bfreg;
627627 };
628628
629+enum mlx5_sw_icm_type {
630+ MLX5_SW_ICM_TYPE_STEERING,
631+ MLX5_SW_ICM_TYPE_HEADER_MODIFY,
632+};
633+
629634 #define MLX5_MAX_RESERVED_GIDS 8
630635
631636 struct mlx5_rsvd_gids {
@@ -657,11 +662,15 @@ struct mlx5_clock { · 25 unmodified lines
657662 struct mlx5_pps pps_info;
658663 };
659664
665+struct mlx5_dm;
660666 struct mlx5_fw_tracer;
661667 struct mlx5_vxlan;
662668 struct mlx5_geneve;
663669 struct mlx5_hv_vhca;
664670
671+#define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
672+#define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
673+
665674 struct mlx5_core_dev {
666675 struct device *device;
667676 enum mlx5_coredev_type coredev_type;
@@ -695,6 +704,7 @@ struct mlx5_core_dev { · 27 unmodified lines
695704 atomic_t num_qps;
696705 u32 issi;
697706 struct mlx5e_resources mlx5e_res;
707+ struct mlx5_dm *dm;
698708 struct mlx5_vxlan *vxlan;
699709 struct mlx5_geneve *geneve;
700710 struct {
@@ -1078,6 +1088,10 @@ int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, · 377 unmodified lines
10781088 size_t *offsets);
10791089 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
10801090 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1091+int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1092+ u64 length, u16 uid, phys_addr_t *addr, u32 *obj_id);
1093+int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1094+ u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
10811095
10821096 #ifdef CONFIG_MLX5_CORE_IPOIB
10831097 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
include/linux/mlx5/eswitch.h+7−1
@@ -60,7 +60,6 @@ void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw, · 59 unmodified lines
6060 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
6161 u16 vport_num);
6262 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type);
63−u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw);
6463 struct mlx5_flow_handle *
6564 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw,
6665 u16 vport_num, u32 sqn);
@@ -74,7 +73,14 @@ mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev); · 7 unmodified lines
7473 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw);
7574 u32 mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw,
7675 u16 vport_num);
76+u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw);
7777 #else /* CONFIG_MLX5_ESWITCH */
78+
79+static inline u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw)
80+{
81+ return MLX5_ESWITCH_NONE;
82+}
83+
7884 static inline enum devlink_eswitch_encap_mode
7985 mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev)
8086 {
include/linux/mlx5/fs.h+16−17
@@ -84,6 +84,8 @@ enum { · 83 unmodified lines
8484 FDB_SLOW_PATH,
8585 };
8686
87+struct mlx5_pkt_reformat;
88+struct mlx5_modify_hdr;
8789 struct mlx5_flow_table;
8890 struct mlx5_flow_group;
8991 struct mlx5_flow_namespace;
@@ -121,7 +123,7 @@ struct mlx5_flow_destination { · 31 unmodified lines
121123 struct {
122124 u16 num;
123125 u16 vhca_id;
124− u32 reformat_id;
126+ struct mlx5_pkt_reformat *pkt_reformat;
125127 u8 flags;
126128 } vport;
127129 };
@@ -195,8 +197,8 @@ enum { · 67 unmodified lines
195197
196198 struct mlx5_flow_act {
197199 u32 action;
198− u32 reformat_id;
199− u32 modify_id;
200+ struct mlx5_modify_hdr *modify_hdr;
201+ struct mlx5_pkt_reformat *pkt_reformat;
200202 uintptr_t esp_id;
201203 u32 flags;
202204 struct mlx5_fs_vlan vlan[MLX5_FS_VLAN_DEPTH];
@@ -205,8 +207,6 @@ struct mlx5_flow_act { · 2 unmodified lines
205207
206208 #define MLX5_DECLARE_FLOW_ACT(name) \
207209 struct mlx5_flow_act name = { .action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,\
208− .reformat_id = 0, \
209− .modify_id = 0, \
210210 .flags = 0, }
211211
212212 /* Single destination per rule.
@@ -236,19 +236,18 @@ u32 mlx5_fc_id(struct mlx5_fc *counter); · 23 unmodified lines
236236 int mlx5_fs_add_rx_underlay_qpn(struct mlx5_core_dev *dev, u32 underlay_qpn);
237237 int mlx5_fs_remove_rx_underlay_qpn(struct mlx5_core_dev *dev, u32 underlay_qpn);
238238
239−int mlx5_modify_header_alloc(struct mlx5_core_dev *dev,
240− u8 namespace, u8 num_actions,
241− void *modify_actions, u32 *modify_header_id);
239+struct mlx5_modify_hdr *mlx5_modify_header_alloc(struct mlx5_core_dev *dev,
240+ u8 ns_type, u8 num_actions,
241+ void *modify_actions);
242242 void mlx5_modify_header_dealloc(struct mlx5_core_dev *dev,
243− u32 modify_header_id);
244−
245−int mlx5_packet_reformat_alloc(struct mlx5_core_dev *dev,
246− int reformat_type,
247− size_t size,
248− void *reformat_data,
249− enum mlx5_flow_namespace_type namespace,
250− u32 *packet_reformat_id);
243+ struct mlx5_modify_hdr *modify_hdr);
244+
245+struct mlx5_pkt_reformat *mlx5_packet_reformat_alloc(struct mlx5_core_dev *dev,
246+ int reformat_type,
247+ size_t size,
248+ void *reformat_data,
249+ enum mlx5_flow_namespace_type ns_type);
251250 void mlx5_packet_reformat_dealloc(struct mlx5_core_dev *dev,
252− u32 packet_reformat_id);
251+ struct mlx5_pkt_reformat *reformat);
253252
254253 #endif
include/linux/mlx5/mlx5_ifc.h+198−37
@@ -282,6 +282,7 @@ enum { · 281 unmodified lines
282282 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
283283 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
284284 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
285+ MLX5_CMD_OP_SYNC_STEERING = 0xb00,
285286 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
286287 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
287288 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
@@ -485,7 +486,11 @@ union mlx5_ifc_gre_key_bits { · 197 unmodified lines
485486 };
486487
487488 struct mlx5_ifc_fte_match_set_misc_bits {
488− u8 reserved_at_0[0x8];
489+ u8 gre_c_present[0x1];
490+ u8 reserved_auto1[0x1];
491+ u8 gre_k_present[0x1];
492+ u8 gre_s_present[0x1];
493+ u8 source_vhca_port[0x4];
489494 u8 source_sqn[0x18];
490495
491496 u8 source_eswitch_owner_vhca_id[0x10];
@@ -565,12 +570,38 @@ struct mlx5_ifc_fte_match_set_misc2_bits { · 73 unmodified lines
565570
566571 u8 metadata_reg_a[0x20];
567572
568− u8 reserved_at_1a0[0x60];
573+ u8 metadata_reg_b[0x20];
574+
575+ u8 reserved_at_1c0[0x40];
569576 };
570577
571578 struct mlx5_ifc_fte_match_set_misc3_bits {
572− u8 reserved_at_0[0x120];
579+ u8 inner_tcp_seq_num[0x20];
580+
581+ u8 outer_tcp_seq_num[0x20];
582+
583+ u8 inner_tcp_ack_num[0x20];
584+
585+ u8 outer_tcp_ack_num[0x20];
586+
587+ u8 reserved_at_80[0x8];
588+ u8 outer_vxlan_gpe_vni[0x18];
589+
590+ u8 outer_vxlan_gpe_next_protocol[0x8];
591+ u8 outer_vxlan_gpe_flags[0x8];
592+ u8 reserved_at_b0[0x10];
593+
594+ u8 icmp_header_data[0x20];
595+
596+ u8 icmpv6_header_data[0x20];
597+
598+ u8 icmp_type[0x8];
599+ u8 icmp_code[0x8];
600+ u8 icmpv6_type[0x8];
601+ u8 icmpv6_code[0x8];
602+
573603 u8 geneve_tlv_option_0_data[0x20];
604+
574605 u8 reserved_at_140[0xc0];
575606 };
576607
@@ -666,7 +697,15 @@ struct mlx5_ifc_flow_table_nic_cap_bits { · 89 unmodified lines
666697
667698 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
668699
669− u8 reserved_at_e00[0x7200];
700+ u8 reserved_at_e00[0x1200];
701+
702+ u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
703+
704+ u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
705+
706+ u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
707+
708+ u8 reserved_at_20c0[0x5f40];
670709 };
671710
672711 enum {
@@ -698,7 +737,17 @@ struct mlx5_ifc_flow_table_eswitch_cap_bits { · 25 unmodified lines
698737
699738 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
700739
701− u8 reserved_at_800[0x7800];
740+ u8 reserved_at_800[0x1000];
741+
742+ u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
743+
744+ u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
745+
746+ u8 sw_steering_uplink_icm_address_rx[0x40];
747+
748+ u8 sw_steering_uplink_icm_address_tx[0x40];
749+
750+ u8 reserved_at_1900[0x6700];
702751 };
703752
704753 enum {
@@ -849,6 +898,25 @@ struct mlx5_ifc_roce_cap_bits { · 144 unmodified lines
849898 u8 reserved_at_100[0x700];
850899 };
851900
901+struct mlx5_ifc_sync_steering_in_bits {
902+ u8 opcode[0x10];
903+ u8 uid[0x10];
904+
905+ u8 reserved_at_20[0x10];
906+ u8 op_mod[0x10];
907+
908+ u8 reserved_at_40[0xc0];
909+};
910+
911+struct mlx5_ifc_sync_steering_out_bits {
912+ u8 status[0x8];
913+ u8 reserved_at_8[0x18];
914+
915+ u8 syndrome[0x20];
916+
917+ u8 reserved_at_40[0x40];
918+};
919+
852920 struct mlx5_ifc_device_mem_cap_bits {
853921 u8 memic[0x1];
854922 u8 reserved_at_1[0x1f];
@@ -1041,6 +1109,12 @@ enum { · 186 unmodified lines
10411109 MLX5_CAP_UMR_FENCE_NONE = 0x2,
10421110 };
10431111
1112+enum {
1113+ MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1114+ MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1115+ MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1116+};
1117+
10441118 enum {
10451119 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
10461120 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
@@ -1414,7 +1488,14 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 367 unmodified lines
14141488
14151489 u8 reserved_at_6c0[0x4];
14161490 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1417− u8 reserved_at_6c8[0x28];
1491+ u8 flex_parser_id_icmp_dw1[0x4];
1492+ u8 flex_parser_id_icmp_dw0[0x4];
1493+ u8 flex_parser_id_icmpv6_dw1[0x4];
1494+ u8 flex_parser_id_icmpv6_dw0[0x4];
1495+ u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1496+ u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1497+
1498+ u8 reserved_at_6e0[0x10];
14181499 u8 sf_base_id[0x10];
14191500
14201501 u8 reserved_at_700[0x80];
@@ -2652,6 +2733,7 @@ union mlx5_ifc_hca_cap_union_bits { · 1231 unmodified lines
26522733 struct mlx5_ifc_debug_cap_bits debug_cap;
26532734 struct mlx5_ifc_fpga_cap_bits fpga_cap;
26542735 struct mlx5_ifc_tls_cap_bits tls_cap;
2736+ struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
26552737 u8 reserved_at_0[0x8000];
26562738 };
26572739
@@ -3255,7 +3337,11 @@ struct mlx5_ifc_esw_vport_context_bits { · 597 unmodified lines
32553337 u8 cvlan_pcp[0x3];
32563338 u8 cvlan_id[0xc];
32573339
3258− u8 reserved_at_60[0x7a0];
3340+ u8 reserved_at_60[0x720];
3341+
3342+ u8 sw_steering_vport_icm_address_rx[0x40];
3343+
3344+ u8 sw_steering_vport_icm_address_tx[0x40];
32593345 };
32603346
32613347 enum {
@@ -4941,23 +5027,98 @@ struct mlx5_ifc_query_hca_cap_in_bits { · 1679 unmodified lines
49415027 u8 reserved_at_20[0x10];
49425028 u8 op_mod[0x10];
49435029
4944− u8 reserved_at_40[0x40];
5030+ u8 other_function[0x1];
5031+ u8 reserved_at_41[0xf];
5032+ u8 function_id[0x10];
5033+
5034+ u8 reserved_at_60[0x20];
49455035 };
49465036
4947−struct mlx5_ifc_query_flow_table_out_bits {
5037+struct mlx5_ifc_other_hca_cap_bits {
5038+ u8 roce[0x1];
5039+ u8 reserved_0[0x27f];
5040+};
5041+
5042+struct mlx5_ifc_query_other_hca_cap_out_bits {
49485043 u8 status[0x8];
4949− u8 reserved_at_8[0x18];
5044+ u8 reserved_0[0x18];
49505045
49515046 u8 syndrome[0x20];
49525047
4953− u8 reserved_at_40[0x80];
5048+ u8 reserved_1[0x40];
49545049
4955− u8 reserved_at_c0[0x8];
5050+ struct mlx5_ifc_other_hca_cap_bits other_capability;
5051+};
5052+
5053+struct mlx5_ifc_query_other_hca_cap_in_bits {
5054+ u8 opcode[0x10];
5055+ u8 reserved_0[0x10];
5056+
5057+ u8 reserved_1[0x10];
5058+ u8 op_mod[0x10];
5059+
5060+ u8 reserved_2[0x10];
5061+ u8 function_id[0x10];
5062+
5063+ u8 reserved_3[0x20];
5064+};
5065+
5066+struct mlx5_ifc_modify_other_hca_cap_out_bits {
5067+ u8 status[0x8];
5068+ u8 reserved_0[0x18];
5069+
5070+ u8 syndrome[0x20];
5071+
5072+ u8 reserved_1[0x40];
5073+};
5074+
5075+struct mlx5_ifc_modify_other_hca_cap_in_bits {
5076+ u8 opcode[0x10];
5077+ u8 reserved_0[0x10];
5078+
5079+ u8 reserved_1[0x10];
5080+ u8 op_mod[0x10];
5081+
5082+ u8 reserved_2[0x10];
5083+ u8 function_id[0x10];
5084+ u8 field_select[0x20];
5085+
5086+ struct mlx5_ifc_other_hca_cap_bits other_capability;
5087+};
5088+
5089+struct mlx5_ifc_flow_table_context_bits {
5090+ u8 reformat_en[0x1];
5091+ u8 decap_en[0x1];
5092+ u8 sw_owner[0x1];
5093+ u8 termination_table[0x1];
5094+ u8 table_miss_action[0x4];
49565095 u8 level[0x8];
4957− u8 reserved_at_d0[0x8];
5096+ u8 reserved_at_10[0x8];
49585097 u8 log_size[0x8];
49595098
4960− u8 reserved_at_e0[0x120];
5099+ u8 reserved_at_20[0x8];
5100+ u8 table_miss_id[0x18];
5101+
5102+ u8 reserved_at_40[0x8];
5103+ u8 lag_master_next_table_id[0x18];
5104+
5105+ u8 reserved_at_60[0x60];
5106+
5107+ u8 sw_owner_icm_root_1[0x40];
5108+
5109+ u8 sw_owner_icm_root_0[0x40];
5110+
5111+};
5112+
5113+struct mlx5_ifc_query_flow_table_out_bits {
5114+ u8 status[0x8];
5115+ u8 reserved_at_8[0x18];
5116+
5117+ u8 syndrome[0x20];
5118+
5119+ u8 reserved_at_40[0x80];
5120+
5121+ struct mlx5_ifc_flow_table_context_bits flow_table_context;
49615122 };
49625123
49635124 struct mlx5_ifc_query_flow_table_in_bits {
@@ -5227,7 +5388,7 @@ struct mlx5_ifc_alloc_packet_reformat_context_out_bits { · 263 unmodified lines
52275388 u8 reserved_at_60[0x20];
52285389 };
52295390
5230−enum {
5391+enum mlx5_reformat_ctx_type {
52315392 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
52325393 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
52335394 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
@@ -5323,7 +5484,16 @@ enum { · 89 unmodified lines
53235484 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
53245485 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
53255486 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5487+ MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5488+ MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
53265489 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5490+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5491+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5492+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5493+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5494+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5495+ MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5496+ MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
53275497 };
53285498
53295499 struct mlx5_ifc_alloc_modify_header_context_out_bits {
@@ -7371,35 +7541,26 @@ struct mlx5_ifc_create_mkey_in_bits { · 2041 unmodified lines
73717541 u8 klm_pas_mtt[0][0x20];
73727542 };
73737543
7544+enum {
7545+ MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7546+ MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7547+ MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7548+ MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7549+ MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7550+ MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7551+ MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7552+};
7553+
73747554 struct mlx5_ifc_create_flow_table_out_bits {
73757555 u8 status[0x8];
7376− u8 reserved_at_8[0x18];
7556+ u8 icm_address_63_40[0x18];
73777557
73787558 u8 syndrome[0x20];
73797559
7380− u8 reserved_at_40[0x8];
7560+ u8 icm_address_39_32[0x8];
73817561 u8 table_id[0x18];
73827562
7383− u8 reserved_at_60[0x20];
7384−};
7385−
7386−struct mlx5_ifc_flow_table_context_bits {
7387− u8 reformat_en[0x1];
7388− u8 decap_en[0x1];
7389− u8 reserved_at_2[0x1];
7390− u8 termination_table[0x1];
7391− u8 table_miss_action[0x4];
7392− u8 level[0x8];
7393− u8 reserved_at_10[0x8];
7394− u8 log_size[0x8];
7395−
7396− u8 reserved_at_20[0x8];
7397− u8 table_miss_id[0x18];
7398−
7399− u8 reserved_at_40[0x8];
7400− u8 lag_master_next_table_id[0x18];
7401−
7402− u8 reserved_at_60[0xe0];
7563+ u8 icm_address_31_0[0x20];
74037564 };
74047565
74057566 struct mlx5_ifc_create_flow_table_in_bits {

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