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drm/amdgpu: Add support to change mtype for 2nd part of gart BOs on GFX9

This change prepares for a workaround in amdkfd for a GFX9 HW bug. It requires the control stack memory of compute queues, which is allocated from the second page of MQD gart BOs, to have mtype NC, rather than the default UC.

Yong Zhao committed 8 years ago

Commit 959a2091 parent 8eb77193 files · +51 −12Browse files

Showing the changes to include/uapi (1 of 3 files). Show all

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include/uapi/drm/amdgpu_drm.h+4−0
@@ -101,6 +101,10 @@ extern "C" { · 100 unmodified lines
101#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)101#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
102/* Flag that BO sharing will be explicitly synchronized */102/* Flag that BO sharing will be explicitly synchronized */
103#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)103#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
104/* Flag that indicates allocating MQD gart on GFX9, where the mtype
105 * for the second page onward should be set to NC.
106 */
107#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
104 108
105struct drm_amdgpu_gem_create_in {109struct drm_amdgpu_gem_create_in {
106 /** the requested memory size */110 /** the requested memory size */

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