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Merge branch 'for-net-next' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

Saeed Mahameed says: ==================== Mellanox, mlx5 E-Switch chains and prios This series has two parts, 1) A merge commit with mlx5-next branch that include updates for mlx5 HW layouts needed for this and upcoming submissions. 2) From Paul, Increase the number of chains and prios Currently the Mellanox driver supports offloading tc rules that are defined on the first 4 chains and the first 16 priorities. The restriction stems from the firmware flow level enforcement requiring a flow table of a certain level to point to a flow table of a higher level. This limitation may be ignored by setting the ignore_flow_level bit when creating flow table entries. Use unmanaged tables and ignore flow level to create more tables than declared by fs_core steering. Manually manage the connections between the tables themselves. HW table is instantiated for every tc <chain,prio> tuple. The miss rule of every table either jumps to the next <chain,prio> table, or continues to slow_fdb. This logic is realized by following this sequence: 1. Create an auto-grouped flow table for the specified priority with reserved entries Reserved entries are allocated at the end of the flow table. Flow groups are evaluated in sequence and therefore it is guaranteed that the flow group defined on the last FTEs will be the last to evaluate. Define a "match all" flow group on the reserved entries, providing the platform to add table miss actions. 2. Set the miss rule action to jump to the next <chain,prio> table or the slow_fdb. 3. Link the previous priority table to point to the new table by updating its miss rule. Please pull and let me know if there's any problem. ====================

David S. Miller committed 6 years ago

Commit 95ae2d12 parents 0c58ac1 278d51f20 files · +1253 −361Browse files

Showing the changes to include/linux (4 of 20 files). Show all

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4 files
  1. include/linux/mlx5/device.h +22 −1
  2. include/linux/mlx5/driver.h +3 −1
  3. include/linux/mlx5/fs.h +12 −8
  4. include/linux/mlx5/mlx5_ifc.h +230 −7
include/linux/mlx5/device.h+22−1
@@ -1105,6 +1105,7 @@ enum mlx5_cap_type { · 1104 unmodified lines
1105 MLX5_CAP_DEV_MEM,1105 MLX5_CAP_DEV_MEM,
1106 MLX5_CAP_RESERVED_16,1106 MLX5_CAP_RESERVED_16,
1107 MLX5_CAP_TLS,1107 MLX5_CAP_TLS,
1108 MLX5_CAP_VDPA_EMULATION = 0x13,
1108 MLX5_CAP_DEV_EVENT = 0x14,1109 MLX5_CAP_DEV_EVENT = 0x14,
1109 /* NUM OF CAP Types */1110 /* NUM OF CAP Types */
1110 MLX5_CAP_NUM1111 MLX5_CAP_NUM
@@ -1120,6 +1121,9 @@ enum mlx5_pcam_feature_groups { · 9 unmodified lines
1120 1121
1121enum mlx5_mcam_reg_groups {1122enum mlx5_mcam_reg_groups {
1122 MLX5_MCAM_REGS_FIRST_128 = 0x0,1123 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1124 MLX5_MCAM_REGS_0x9080_0x90FF = 0x1,
1125 MLX5_MCAM_REGS_0x9100_0x917F = 0x2,
1126 MLX5_MCAM_REGS_NUM = 0x3,
1123};1127};
1124 1128
1125enum mlx5_mcam_feature_groups {1129enum mlx5_mcam_feature_groups {
@@ -1268,7 +1272,16 @@ enum mlx5_qcam_feature_groups { · 142 unmodified lines
1268 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)1272 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1269 1273
1270#define MLX5_CAP_MCAM_REG(mdev, reg) \1274#define MLX5_CAP_MCAM_REG(mdev, reg) \
1271 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)1275 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
1276 mng_access_reg_cap_mask.access_regs.reg)
1277
1278#define MLX5_CAP_MCAM_REG1(mdev, reg) \
1279 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \
1280 mng_access_reg_cap_mask.access_regs1.reg)
1281
1282#define MLX5_CAP_MCAM_REG2(mdev, reg) \
1283 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
1284 mng_access_reg_cap_mask.access_regs2.reg)
1272 1285
1273#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \1286#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1274 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)1287 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
@@ -1297,6 +1310,14 @@ enum mlx5_qcam_feature_groups { · 22 unmodified lines
1297#define MLX5_CAP_DEV_EVENT(mdev, cap)\1310#define MLX5_CAP_DEV_EVENT(mdev, cap)\
1298 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)1311 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
1299 1312
1313#define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\
1314 MLX5_GET(device_virtio_emulation_cap, \
1315 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1316
1317#define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\
1318 MLX5_GET64(device_virtio_emulation_cap, \
1319 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1320
1300enum {1321enum {
1301 MLX5_CMD_STAT_OK = 0x0,1322 MLX5_CMD_STAT_OK = 0x0,
1302 MLX5_CMD_STAT_INT_ERR = 0x1,1323 MLX5_CMD_STAT_INT_ERR = 0x1,
include/linux/mlx5/driver.h+3−1
@@ -145,6 +145,8 @@ enum { · 144 unmodified lines
145 MLX5_REG_MCC = 0x9062,145 MLX5_REG_MCC = 0x9062,
146 MLX5_REG_MCDA = 0x9063,146 MLX5_REG_MCDA = 0x9063,
147 MLX5_REG_MCAM = 0x907f,147 MLX5_REG_MCAM = 0x907f,
148 MLX5_REG_MIRC = 0x9162,
149 MLX5_REG_RESOURCE_DUMP = 0xC000,
148};150};
149 151
150enum mlx5_qpts_trust_state {152enum mlx5_qpts_trust_state {
@@ -684,7 +686,7 @@ struct mlx5_core_dev { · 533 unmodified lines
684 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];686 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
685 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];687 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
686 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];688 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
687 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];689 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
688 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];690 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
689 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];691 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
690 u8 embedded_cpu;692 u8 embedded_cpu;
include/linux/mlx5/fs.h+12−8
@@ -48,6 +48,7 @@ enum { · 47 unmodified lines
48 MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT = BIT(0),48 MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT = BIT(0),
49 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = BIT(1),49 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = BIT(1),
50 MLX5_FLOW_TABLE_TERMINATION = BIT(2),50 MLX5_FLOW_TABLE_TERMINATION = BIT(2),
51 MLX5_FLOW_TABLE_UNMANAGED = BIT(3),
51};52};
52 53
53#define LEFTOVERS_RULE_NUM 254#define LEFTOVERS_RULE_NUM 2
@@ -145,25 +146,27 @@ mlx5_get_flow_vport_acl_namespace(struct mlx5_core_dev *dev, · 91 unmodified lines
145 enum mlx5_flow_namespace_type type,146 enum mlx5_flow_namespace_type type,
146 int vport);147 int vport);
147 148
148struct mlx5_flow_table *
149mlx5_create_auto_grouped_flow_table(struct mlx5_flow_namespace *ns,
150 int prio,
151 int num_flow_table_entries,
152 int max_num_groups,
153 u32 level,
154 u32 flags);
155
156struct mlx5_flow_table_attr {149struct mlx5_flow_table_attr {
157 int prio;150 int prio;
158 int max_fte;151 int max_fte;
159 u32 level;152 u32 level;
160 u32 flags;153 u32 flags;
154 struct mlx5_flow_table *next_ft;
155
156 struct {
157 int max_num_groups;
158 int num_reserved_entries;
159 } autogroup;
161};160};
162 161
163struct mlx5_flow_table *162struct mlx5_flow_table *
164mlx5_create_flow_table(struct mlx5_flow_namespace *ns,163mlx5_create_flow_table(struct mlx5_flow_namespace *ns,
165 struct mlx5_flow_table_attr *ft_attr);164 struct mlx5_flow_table_attr *ft_attr);
166 165
166struct mlx5_flow_table *
167mlx5_create_auto_grouped_flow_table(struct mlx5_flow_namespace *ns,
168 struct mlx5_flow_table_attr *ft_attr);
169
167struct mlx5_flow_table *170struct mlx5_flow_table *
168mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,171mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,
169 int prio,172 int prio,
@@ -194,6 +197,7 @@ struct mlx5_fs_vlan { · 24 unmodified lines
194 197
195enum {198enum {
196 FLOW_ACT_NO_APPEND = BIT(0),199 FLOW_ACT_NO_APPEND = BIT(0),
200 FLOW_ACT_IGNORE_FLOW_LEVEL = BIT(1),
197};201};
198 202
199struct mlx5_flow_act {203struct mlx5_flow_act {
include/linux/mlx5/mlx5_ifc.h+230−7
@@ -87,6 +87,7 @@ enum { · 86 unmodified lines
87enum {87enum {
88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
90};91};
91 92
92enum {93enum {
@@ -374,8 +375,17 @@ struct mlx5_ifc_flow_table_fields_supported_bits { · 281 unmodified lines
374 u8 outer_esp_spi[0x1];375 u8 outer_esp_spi[0x1];
375 u8 reserved_at_58[0x2];376 u8 reserved_at_58[0x2];
376 u8 bth_dst_qp[0x1];377 u8 bth_dst_qp[0x1];
378 u8 reserved_at_5b[0x5];
377 379
378 u8 reserved_at_5b[0x25];380 u8 reserved_at_60[0x18];
381 u8 metadata_reg_c_7[0x1];
382 u8 metadata_reg_c_6[0x1];
383 u8 metadata_reg_c_5[0x1];
384 u8 metadata_reg_c_4[0x1];
385 u8 metadata_reg_c_3[0x1];
386 u8 metadata_reg_c_2[0x1];
387 u8 metadata_reg_c_1[0x1];
388 u8 metadata_reg_c_0[0x1];
379};389};
380 390
381struct mlx5_ifc_flow_table_prop_layout_bits {391struct mlx5_ifc_flow_table_prop_layout_bits {
@@ -400,7 +410,8 @@ struct mlx5_ifc_flow_table_prop_layout_bits { · 18 unmodified lines
400 u8 reformat_l3_tunnel_to_l2[0x1];410 u8 reformat_l3_tunnel_to_l2[0x1];
401 u8 reformat_l2_to_l3_tunnel[0x1];411 u8 reformat_l2_to_l3_tunnel[0x1];
402 u8 reformat_and_modify_action[0x1];412 u8 reformat_and_modify_action[0x1];
403 u8 reserved_at_15[0x2];413 u8 ignore_flow_level[0x1];
414 u8 reserved_at_16[0x1];
404 u8 table_miss_action_domain[0x1];415 u8 table_miss_action_domain[0x1];
405 u8 termination_table[0x1];416 u8 termination_table[0x1];
406 u8 reserved_at_19[0x7];417 u8 reserved_at_19[0x7];
@@ -721,7 +732,9 @@ enum { · 314 unmodified lines
721 732
722struct mlx5_ifc_flow_table_eswitch_cap_bits {733struct mlx5_ifc_flow_table_eswitch_cap_bits {
723 u8 fdb_to_vport_reg_c_id[0x8];734 u8 fdb_to_vport_reg_c_id[0x8];
724 u8 reserved_at_8[0xf];735 u8 reserved_at_8[0xd];
736 u8 fdb_modify_header_fwd_to_table[0x1];
737 u8 reserved_at_16[0x1];
725 u8 flow_source[0x1];738 u8 flow_source[0x1];
726 u8 reserved_at_18[0x2];739 u8 reserved_at_18[0x2];
727 u8 multi_fdb_encap[0x1];740 u8 multi_fdb_encap[0x1];
@@ -822,7 +835,9 @@ struct mlx5_ifc_qos_cap_bits { · 94 unmodified lines
822struct mlx5_ifc_debug_cap_bits {835struct mlx5_ifc_debug_cap_bits {
823 u8 core_dump_general[0x1];836 u8 core_dump_general[0x1];
824 u8 core_dump_qp[0x1];837 u8 core_dump_qp[0x1];
825 u8 reserved_at_2[0x1e];838 u8 reserved_at_2[0x7];
839 u8 resource_dump[0x1];
840 u8 reserved_at_a[0x16];
826 841
827 u8 reserved_at_20[0x2];842 u8 reserved_at_20[0x2];
828 u8 stall_detect[0x1];843 u8 stall_detect[0x1];
@@ -953,6 +968,19 @@ struct mlx5_ifc_device_event_cap_bits { · 124 unmodified lines
953 u8 user_unaffiliated_events[4][0x40];968 u8 user_unaffiliated_events[4][0x40];
954};969};
955 970
971struct mlx5_ifc_device_virtio_emulation_cap_bits {
972 u8 reserved_at_0[0x20];
973
974 u8 reserved_at_20[0x13];
975 u8 log_doorbell_stride[0x5];
976 u8 reserved_at_38[0x3];
977 u8 log_doorbell_bar_size[0x5];
978
979 u8 doorbell_bar_offset[0x40];
980
981 u8 reserved_at_80[0x780];
982};
983
956enum {984enum {
957 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,985 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
958 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,986 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
@@ -1753,6 +1781,132 @@ struct mlx5_ifc_resize_field_select_bits { · 794 unmodified lines
1753 u8 resize_field_select[0x20];1781 u8 resize_field_select[0x20];
1754};1782};
1755 1783
1784struct mlx5_ifc_resource_dump_bits {
1785 u8 more_dump[0x1];
1786 u8 inline_dump[0x1];
1787 u8 reserved_at_2[0xa];
1788 u8 seq_num[0x4];
1789 u8 segment_type[0x10];
1790
1791 u8 reserved_at_20[0x10];
1792 u8 vhca_id[0x10];
1793
1794 u8 index1[0x20];
1795
1796 u8 index2[0x20];
1797
1798 u8 num_of_obj1[0x10];
1799 u8 num_of_obj2[0x10];
1800
1801 u8 reserved_at_a0[0x20];
1802
1803 u8 device_opaque[0x40];
1804
1805 u8 mkey[0x20];
1806
1807 u8 size[0x20];
1808
1809 u8 address[0x40];
1810
1811 u8 inline_data[52][0x20];
1812};
1813
1814struct mlx5_ifc_resource_dump_menu_record_bits {
1815 u8 reserved_at_0[0x4];
1816 u8 num_of_obj2_supports_active[0x1];
1817 u8 num_of_obj2_supports_all[0x1];
1818 u8 must_have_num_of_obj2[0x1];
1819 u8 support_num_of_obj2[0x1];
1820 u8 num_of_obj1_supports_active[0x1];
1821 u8 num_of_obj1_supports_all[0x1];
1822 u8 must_have_num_of_obj1[0x1];
1823 u8 support_num_of_obj1[0x1];
1824 u8 must_have_index2[0x1];
1825 u8 support_index2[0x1];
1826 u8 must_have_index1[0x1];
1827 u8 support_index1[0x1];
1828 u8 segment_type[0x10];
1829
1830 u8 segment_name[4][0x20];
1831
1832 u8 index1_name[4][0x20];
1833
1834 u8 index2_name[4][0x20];
1835};
1836
1837struct mlx5_ifc_resource_dump_segment_header_bits {
1838 u8 length_dw[0x10];
1839 u8 segment_type[0x10];
1840};
1841
1842struct mlx5_ifc_resource_dump_command_segment_bits {
1843 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1844
1845 u8 segment_called[0x10];
1846 u8 vhca_id[0x10];
1847
1848 u8 index1[0x20];
1849
1850 u8 index2[0x20];
1851
1852 u8 num_of_obj1[0x10];
1853 u8 num_of_obj2[0x10];
1854};
1855
1856struct mlx5_ifc_resource_dump_error_segment_bits {
1857 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1858
1859 u8 reserved_at_20[0x10];
1860 u8 syndrome_id[0x10];
1861
1862 u8 reserved_at_40[0x40];
1863
1864 u8 error[8][0x20];
1865};
1866
1867struct mlx5_ifc_resource_dump_info_segment_bits {
1868 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1869
1870 u8 reserved_at_20[0x18];
1871 u8 dump_version[0x8];
1872
1873 u8 hw_version[0x20];
1874
1875 u8 fw_version[0x20];
1876};
1877
1878struct mlx5_ifc_resource_dump_menu_segment_bits {
1879 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1880
1881 u8 reserved_at_20[0x10];
1882 u8 num_of_records[0x10];
1883
1884 struct mlx5_ifc_resource_dump_menu_record_bits record[0];
1885};
1886
1887struct mlx5_ifc_resource_dump_resource_segment_bits {
1888 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1889
1890 u8 reserved_at_20[0x20];
1891
1892 u8 index1[0x20];
1893
1894 u8 index2[0x20];
1895
1896 u8 payload[0][0x20];
1897};
1898
1899struct mlx5_ifc_resource_dump_terminate_segment_bits {
1900 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1901};
1902
1903struct mlx5_ifc_menu_resource_dump_response_bits {
1904 struct mlx5_ifc_resource_dump_info_segment_bits info;
1905 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
1906 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
1907 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
1908};
1909
1756enum {1910enum {
1757 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,1911 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1758 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,1912 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
@@ -2026,7 +2180,9 @@ struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { · 267 unmodified lines
2026 2180
2027 u8 rx_pause_transition_low[0x20];2181 u8 rx_pause_transition_low[0x20];
2028 2182
2029 u8 reserved_at_3c0[0x40];2183 u8 rx_discards_high[0x20];
2184
2185 u8 rx_discards_low[0x20];
2030 2186
2031 u8 device_stall_minor_watermark_cnt_high[0x20];2187 u8 device_stall_minor_watermark_cnt_high[0x20];
2032 2188
@@ -2751,6 +2907,7 @@ union mlx5_ifc_hca_cap_union_bits { · 718 unmodified lines
2751 struct mlx5_ifc_fpga_cap_bits fpga_cap;2907 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2752 struct mlx5_ifc_tls_cap_bits tls_cap;2908 struct mlx5_ifc_tls_cap_bits tls_cap;
2753 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;2909 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2910 struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap;
2754 u8 reserved_at_0[0x8000];2911 u8 reserved_at_0[0x8000];
2755};2912};
2756 2913
@@ -3998,7 +4155,8 @@ struct mlx5_ifc_set_fte_in_bits { · 1241 unmodified lines
3998 u8 reserved_at_a0[0x8];4155 u8 reserved_at_a0[0x8];
3999 u8 table_id[0x18];4156 u8 table_id[0x18];
4000 4157
4001 u8 reserved_at_c0[0x18];4158 u8 ignore_flow_level[0x1];
4159 u8 reserved_at_c1[0x17];
4002 u8 modify_enable_mask[0x8];4160 u8 modify_enable_mask[0x8];
4003 4161
4004 u8 reserved_at_e0[0x20];4162 u8 reserved_at_e0[0x20];
@@ -5466,15 +5624,32 @@ struct mlx5_ifc_add_action_in_bits { · 1461 unmodified lines
5466 u8 data[0x20];5624 u8 data[0x20];
5467};5625};
5468 5626
5627struct mlx5_ifc_copy_action_in_bits {
5628 u8 action_type[0x4];
5629 u8 src_field[0xc];
5630 u8 reserved_at_10[0x3];
5631 u8 src_offset[0x5];
5632 u8 reserved_at_18[0x3];
5633 u8 length[0x5];
5634
5635 u8 reserved_at_20[0x4];
5636 u8 dst_field[0xc];
5637 u8 reserved_at_30[0x3];
5638 u8 dst_offset[0x5];
5639 u8 reserved_at_38[0x8];
5640};
5641
5469union mlx5_ifc_set_action_in_add_action_in_auto_bits {5642union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5470 struct mlx5_ifc_set_action_in_bits set_action_in;5643 struct mlx5_ifc_set_action_in_bits set_action_in;
5471 struct mlx5_ifc_add_action_in_bits add_action_in;5644 struct mlx5_ifc_add_action_in_bits add_action_in;
5645 struct mlx5_ifc_copy_action_in_bits copy_action_in;
5472 u8 reserved_at_0[0x40];5646 u8 reserved_at_0[0x40];
5473};5647};
5474 5648
5475enum {5649enum {
5476 MLX5_ACTION_TYPE_SET = 0x1,5650 MLX5_ACTION_TYPE_SET = 0x1,
5477 MLX5_ACTION_TYPE_ADD = 0x2,5651 MLX5_ACTION_TYPE_ADD = 0x2,
5652 MLX5_ACTION_TYPE_COPY = 0x3,
5478};5653};
5479 5654
5480enum {5655enum {
@@ -5510,6 +5685,8 @@ enum { · 29 unmodified lines
5510 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,5685 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5511 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,5686 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5512 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,5687 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5688 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
5689 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
5513 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,5690 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5514 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,5691 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5515};5692};
@@ -8406,6 +8583,18 @@ struct mlx5_ifc_pplm_reg_bits { · 2890 unmodified lines
8406 u8 fec_override_admin_50g[0x4];8583 u8 fec_override_admin_50g[0x4];
8407 u8 fec_override_admin_25g[0x4];8584 u8 fec_override_admin_25g[0x4];
8408 u8 fec_override_admin_10g_40g[0x4];8585 u8 fec_override_admin_10g_40g[0x4];
8586
8587 u8 fec_override_cap_400g_8x[0x10];
8588 u8 fec_override_cap_200g_4x[0x10];
8589
8590 u8 fec_override_cap_100g_2x[0x10];
8591 u8 fec_override_cap_50g_1x[0x10];
8592
8593 u8 fec_override_admin_400g_8x[0x10];
8594 u8 fec_override_admin_200g_4x[0x10];
8595
8596 u8 fec_override_admin_100g_2x[0x10];
8597 u8 fec_override_admin_50g_1x[0x10];
8409};8598};
8410 8599
8411struct mlx5_ifc_ppcnt_reg_bits {8600struct mlx5_ifc_ppcnt_reg_bits {
@@ -8732,7 +8921,9 @@ struct mlx5_ifc_mpegc_reg_bits { · 320 unmodified lines
8732};8921};
8733 8922
8734struct mlx5_ifc_pcam_enhanced_features_bits {8923struct mlx5_ifc_pcam_enhanced_features_bits {
8735 u8 reserved_at_0[0x6d];8924 u8 reserved_at_0[0x68];
8925 u8 fec_50G_per_lane_in_pplm[0x1];
8926 u8 reserved_at_69[0x4];
8736 u8 rx_icrc_encapsulated_counter[0x1];8927 u8 rx_icrc_encapsulated_counter[0x1];
8737 u8 reserved_at_6e[0x4];8928 u8 reserved_at_6e[0x4];
8738 u8 ptys_extended_ethernet[0x1];8929 u8 ptys_extended_ethernet[0x1];
@@ -8817,6 +9008,28 @@ struct mlx5_ifc_mcam_access_reg_bits { · 78 unmodified lines
8817 u8 regs_31_to_0[0x20];9008 u8 regs_31_to_0[0x20];
8818};9009};
8819 9010
9011struct mlx5_ifc_mcam_access_reg_bits1 {
9012 u8 regs_127_to_96[0x20];
9013
9014 u8 regs_95_to_64[0x20];
9015
9016 u8 regs_63_to_32[0x20];
9017
9018 u8 regs_31_to_0[0x20];
9019};
9020
9021struct mlx5_ifc_mcam_access_reg_bits2 {
9022 u8 regs_127_to_99[0x1d];
9023 u8 mirc[0x1];
9024 u8 regs_97_to_96[0x2];
9025
9026 u8 regs_95_to_64[0x20];
9027
9028 u8 regs_63_to_32[0x20];
9029
9030 u8 regs_31_to_0[0x20];
9031};
9032
8820struct mlx5_ifc_mcam_reg_bits {9033struct mlx5_ifc_mcam_reg_bits {
8821 u8 reserved_at_0[0x8];9034 u8 reserved_at_0[0x8];
8822 u8 feature_group[0x8];9035 u8 feature_group[0x8];
@@ -8827,6 +9040,8 @@ struct mlx5_ifc_mcam_reg_bits { · 4 unmodified lines
8827 9040
8828 union {9041 union {
8829 struct mlx5_ifc_mcam_access_reg_bits access_regs;9042 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9043 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9044 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
8830 u8 reserved_at_0[0x80];9045 u8 reserved_at_0[0x80];
8831 } mng_access_reg_cap_mask;9046 } mng_access_reg_cap_mask;
8832 9047
@@ -9432,6 +9647,13 @@ struct mlx5_ifc_mcda_reg_bits { · 599 unmodified lines
9432 u8 data[0][0x20];9647 u8 data[0][0x20];
9433};9648};
9434 9649
9650struct mlx5_ifc_mirc_reg_bits {
9651 u8 reserved_at_0[0x18];
9652 u8 status_code[0x8];
9653
9654 u8 reserved_at_20[0x20];
9655};
9656
9435union mlx5_ifc_ports_control_registers_document_bits {9657union mlx5_ifc_ports_control_registers_document_bits {
9436 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;9658 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9437 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;9659 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
@@ -9487,6 +9709,7 @@ union mlx5_ifc_ports_control_registers_document_bits { · 49 unmodified lines
9487 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;9709 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9488 struct mlx5_ifc_mcc_reg_bits mcc_reg;9710 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9489 struct mlx5_ifc_mcda_reg_bits mcda_reg;9711 struct mlx5_ifc_mcda_reg_bits mcda_reg;
9712 struct mlx5_ifc_mirc_reg_bits mirc_reg;
9490 u8 reserved_at_0[0x60e0];9713 u8 reserved_at_0[0x60e0];
9491};9714};
9492 9715