History

Merge branch 'for-net-next' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

Saeed Mahameed says: ==================== Mellanox, mlx5 E-Switch chains and prios This series has two parts, 1) A merge commit with mlx5-next branch that include updates for mlx5 HW layouts needed for this and upcoming submissions. 2) From Paul, Increase the number of chains and prios Currently the Mellanox driver supports offloading tc rules that are defined on the first 4 chains and the first 16 priorities. The restriction stems from the firmware flow level enforcement requiring a flow table of a certain level to point to a flow table of a higher level. This limitation may be ignored by setting the ignore_flow_level bit when creating flow table entries. Use unmanaged tables and ignore flow level to create more tables than declared by fs_core steering. Manually manage the connections between the tables themselves. HW table is instantiated for every tc <chain,prio> tuple. The miss rule of every table either jumps to the next <chain,prio> table, or continues to slow_fdb. This logic is realized by following this sequence: 1. Create an auto-grouped flow table for the specified priority with reserved entries Reserved entries are allocated at the end of the flow table. Flow groups are evaluated in sequence and therefore it is guaranteed that the flow group defined on the last FTEs will be the last to evaluate. Define a "match all" flow group on the reserved entries, providing the platform to add table miss actions. 2. Set the miss rule action to jump to the next <chain,prio> table or the slow_fdb. 3. Link the previous priority table to point to the new table by updating its miss rule. Please pull and let me know if there's any problem. ====================

David S. Miller committed 6 years ago

Commit 95ae2d12 parents 0c58ac1 278d51f20 files · +1253 −361Browse files

Showing the changes to include/linux (4 of 20 files). Show all

Unified · Split

4 files
  1. include/linux/mlx5/device.h +22 −1
  2. include/linux/mlx5/driver.h +3 −1
  3. include/linux/mlx5/fs.h +12 −8
  4. include/linux/mlx5/mlx5_ifc.h +230 −7
include/linux/mlx5/device.h+22−1
@@ -1105,6 +1105,7 @@ enum mlx5_cap_type { · 1104 unmodified lines
11051105 MLX5_CAP_DEV_MEM,
11061106 MLX5_CAP_RESERVED_16,
11071107 MLX5_CAP_TLS,
1108+ MLX5_CAP_VDPA_EMULATION = 0x13,
11081109 MLX5_CAP_DEV_EVENT = 0x14,
11091110 /* NUM OF CAP Types */
11101111 MLX5_CAP_NUM
@@ -1120,6 +1121,9 @@ enum mlx5_pcam_feature_groups { · 9 unmodified lines
11201121
11211122 enum mlx5_mcam_reg_groups {
11221123 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1124+ MLX5_MCAM_REGS_0x9080_0x90FF = 0x1,
1125+ MLX5_MCAM_REGS_0x9100_0x917F = 0x2,
1126+ MLX5_MCAM_REGS_NUM = 0x3,
11231127 };
11241128
11251129 enum mlx5_mcam_feature_groups {
@@ -1268,7 +1272,16 @@ enum mlx5_qcam_feature_groups { · 142 unmodified lines
12681272 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
12691273
12701274 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1271− MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1275+ MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
1276+ mng_access_reg_cap_mask.access_regs.reg)
1277+
1278+#define MLX5_CAP_MCAM_REG1(mdev, reg) \
1279+ MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \
1280+ mng_access_reg_cap_mask.access_regs1.reg)
1281+
1282+#define MLX5_CAP_MCAM_REG2(mdev, reg) \
1283+ MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
1284+ mng_access_reg_cap_mask.access_regs2.reg)
12721285
12731286 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
12741287 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
@@ -1297,6 +1310,14 @@ enum mlx5_qcam_feature_groups { · 22 unmodified lines
12971310 #define MLX5_CAP_DEV_EVENT(mdev, cap)\
12981311 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
12991312
1313+#define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\
1314+ MLX5_GET(device_virtio_emulation_cap, \
1315+ (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1316+
1317+#define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\
1318+ MLX5_GET64(device_virtio_emulation_cap, \
1319+ (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1320+
13001321 enum {
13011322 MLX5_CMD_STAT_OK = 0x0,
13021323 MLX5_CMD_STAT_INT_ERR = 0x1,
include/linux/mlx5/driver.h+3−1
@@ -145,6 +145,8 @@ enum { · 144 unmodified lines
145145 MLX5_REG_MCC = 0x9062,
146146 MLX5_REG_MCDA = 0x9063,
147147 MLX5_REG_MCAM = 0x907f,
148+ MLX5_REG_MIRC = 0x9162,
149+ MLX5_REG_RESOURCE_DUMP = 0xC000,
148150 };
149151
150152 enum mlx5_qpts_trust_state {
@@ -684,7 +686,7 @@ struct mlx5_core_dev { · 533 unmodified lines
684686 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
685687 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
686688 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
687− u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
689+ u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
688690 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
689691 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
690692 u8 embedded_cpu;
include/linux/mlx5/fs.h+12−8
@@ -48,6 +48,7 @@ enum { · 47 unmodified lines
4848 MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT = BIT(0),
4949 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = BIT(1),
5050 MLX5_FLOW_TABLE_TERMINATION = BIT(2),
51+ MLX5_FLOW_TABLE_UNMANAGED = BIT(3),
5152 };
5253
5354 #define LEFTOVERS_RULE_NUM 2
@@ -145,25 +146,27 @@ mlx5_get_flow_vport_acl_namespace(struct mlx5_core_dev *dev, · 91 unmodified lines
145146 enum mlx5_flow_namespace_type type,
146147 int vport);
147148
148−struct mlx5_flow_table *
149−mlx5_create_auto_grouped_flow_table(struct mlx5_flow_namespace *ns,
150− int prio,
151− int num_flow_table_entries,
152− int max_num_groups,
153− u32 level,
154− u32 flags);
155−
156149 struct mlx5_flow_table_attr {
157150 int prio;
158151 int max_fte;
159152 u32 level;
160153 u32 flags;
154+ struct mlx5_flow_table *next_ft;
155+
156+ struct {
157+ int max_num_groups;
158+ int num_reserved_entries;
159+ } autogroup;
161160 };
162161
163162 struct mlx5_flow_table *
164163 mlx5_create_flow_table(struct mlx5_flow_namespace *ns,
165164 struct mlx5_flow_table_attr *ft_attr);
166165
166+struct mlx5_flow_table *
167+mlx5_create_auto_grouped_flow_table(struct mlx5_flow_namespace *ns,
168+ struct mlx5_flow_table_attr *ft_attr);
169+
167170 struct mlx5_flow_table *
168171 mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,
169172 int prio,
@@ -194,6 +197,7 @@ struct mlx5_fs_vlan { · 24 unmodified lines
194197
195198 enum {
196199 FLOW_ACT_NO_APPEND = BIT(0),
200+ FLOW_ACT_IGNORE_FLOW_LEVEL = BIT(1),
197201 };
198202
199203 struct mlx5_flow_act {
include/linux/mlx5/mlx5_ifc.h+230−7
@@ -87,6 +87,7 @@ enum { · 86 unmodified lines
8787 enum {
8888 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
8989 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90+ MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
9091 };
9192
9293 enum {
@@ -374,8 +375,17 @@ struct mlx5_ifc_flow_table_fields_supported_bits { · 281 unmodified lines
374375 u8 outer_esp_spi[0x1];
375376 u8 reserved_at_58[0x2];
376377 u8 bth_dst_qp[0x1];
378+ u8 reserved_at_5b[0x5];
377379
378− u8 reserved_at_5b[0x25];
380+ u8 reserved_at_60[0x18];
381+ u8 metadata_reg_c_7[0x1];
382+ u8 metadata_reg_c_6[0x1];
383+ u8 metadata_reg_c_5[0x1];
384+ u8 metadata_reg_c_4[0x1];
385+ u8 metadata_reg_c_3[0x1];
386+ u8 metadata_reg_c_2[0x1];
387+ u8 metadata_reg_c_1[0x1];
388+ u8 metadata_reg_c_0[0x1];
379389 };
380390
381391 struct mlx5_ifc_flow_table_prop_layout_bits {
@@ -400,7 +410,8 @@ struct mlx5_ifc_flow_table_prop_layout_bits { · 18 unmodified lines
400410 u8 reformat_l3_tunnel_to_l2[0x1];
401411 u8 reformat_l2_to_l3_tunnel[0x1];
402412 u8 reformat_and_modify_action[0x1];
403− u8 reserved_at_15[0x2];
413+ u8 ignore_flow_level[0x1];
414+ u8 reserved_at_16[0x1];
404415 u8 table_miss_action_domain[0x1];
405416 u8 termination_table[0x1];
406417 u8 reserved_at_19[0x7];
@@ -721,7 +732,9 @@ enum { · 314 unmodified lines
721732
722733 struct mlx5_ifc_flow_table_eswitch_cap_bits {
723734 u8 fdb_to_vport_reg_c_id[0x8];
724− u8 reserved_at_8[0xf];
735+ u8 reserved_at_8[0xd];
736+ u8 fdb_modify_header_fwd_to_table[0x1];
737+ u8 reserved_at_16[0x1];
725738 u8 flow_source[0x1];
726739 u8 reserved_at_18[0x2];
727740 u8 multi_fdb_encap[0x1];
@@ -822,7 +835,9 @@ struct mlx5_ifc_qos_cap_bits { · 94 unmodified lines
822835 struct mlx5_ifc_debug_cap_bits {
823836 u8 core_dump_general[0x1];
824837 u8 core_dump_qp[0x1];
825− u8 reserved_at_2[0x1e];
838+ u8 reserved_at_2[0x7];
839+ u8 resource_dump[0x1];
840+ u8 reserved_at_a[0x16];
826841
827842 u8 reserved_at_20[0x2];
828843 u8 stall_detect[0x1];
@@ -953,6 +968,19 @@ struct mlx5_ifc_device_event_cap_bits { · 124 unmodified lines
953968 u8 user_unaffiliated_events[4][0x40];
954969 };
955970
971+struct mlx5_ifc_device_virtio_emulation_cap_bits {
972+ u8 reserved_at_0[0x20];
973+
974+ u8 reserved_at_20[0x13];
975+ u8 log_doorbell_stride[0x5];
976+ u8 reserved_at_38[0x3];
977+ u8 log_doorbell_bar_size[0x5];
978+
979+ u8 doorbell_bar_offset[0x40];
980+
981+ u8 reserved_at_80[0x780];
982+};
983+
956984 enum {
957985 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
958986 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
@@ -1753,6 +1781,132 @@ struct mlx5_ifc_resize_field_select_bits { · 794 unmodified lines
17531781 u8 resize_field_select[0x20];
17541782 };
17551783
1784+struct mlx5_ifc_resource_dump_bits {
1785+ u8 more_dump[0x1];
1786+ u8 inline_dump[0x1];
1787+ u8 reserved_at_2[0xa];
1788+ u8 seq_num[0x4];
1789+ u8 segment_type[0x10];
1790+
1791+ u8 reserved_at_20[0x10];
1792+ u8 vhca_id[0x10];
1793+
1794+ u8 index1[0x20];
1795+
1796+ u8 index2[0x20];
1797+
1798+ u8 num_of_obj1[0x10];
1799+ u8 num_of_obj2[0x10];
1800+
1801+ u8 reserved_at_a0[0x20];
1802+
1803+ u8 device_opaque[0x40];
1804+
1805+ u8 mkey[0x20];
1806+
1807+ u8 size[0x20];
1808+
1809+ u8 address[0x40];
1810+
1811+ u8 inline_data[52][0x20];
1812+};
1813+
1814+struct mlx5_ifc_resource_dump_menu_record_bits {
1815+ u8 reserved_at_0[0x4];
1816+ u8 num_of_obj2_supports_active[0x1];
1817+ u8 num_of_obj2_supports_all[0x1];
1818+ u8 must_have_num_of_obj2[0x1];
1819+ u8 support_num_of_obj2[0x1];
1820+ u8 num_of_obj1_supports_active[0x1];
1821+ u8 num_of_obj1_supports_all[0x1];
1822+ u8 must_have_num_of_obj1[0x1];
1823+ u8 support_num_of_obj1[0x1];
1824+ u8 must_have_index2[0x1];
1825+ u8 support_index2[0x1];
1826+ u8 must_have_index1[0x1];
1827+ u8 support_index1[0x1];
1828+ u8 segment_type[0x10];
1829+
1830+ u8 segment_name[4][0x20];
1831+
1832+ u8 index1_name[4][0x20];
1833+
1834+ u8 index2_name[4][0x20];
1835+};
1836+
1837+struct mlx5_ifc_resource_dump_segment_header_bits {
1838+ u8 length_dw[0x10];
1839+ u8 segment_type[0x10];
1840+};
1841+
1842+struct mlx5_ifc_resource_dump_command_segment_bits {
1843+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1844+
1845+ u8 segment_called[0x10];
1846+ u8 vhca_id[0x10];
1847+
1848+ u8 index1[0x20];
1849+
1850+ u8 index2[0x20];
1851+
1852+ u8 num_of_obj1[0x10];
1853+ u8 num_of_obj2[0x10];
1854+};
1855+
1856+struct mlx5_ifc_resource_dump_error_segment_bits {
1857+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1858+
1859+ u8 reserved_at_20[0x10];
1860+ u8 syndrome_id[0x10];
1861+
1862+ u8 reserved_at_40[0x40];
1863+
1864+ u8 error[8][0x20];
1865+};
1866+
1867+struct mlx5_ifc_resource_dump_info_segment_bits {
1868+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1869+
1870+ u8 reserved_at_20[0x18];
1871+ u8 dump_version[0x8];
1872+
1873+ u8 hw_version[0x20];
1874+
1875+ u8 fw_version[0x20];
1876+};
1877+
1878+struct mlx5_ifc_resource_dump_menu_segment_bits {
1879+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1880+
1881+ u8 reserved_at_20[0x10];
1882+ u8 num_of_records[0x10];
1883+
1884+ struct mlx5_ifc_resource_dump_menu_record_bits record[0];
1885+};
1886+
1887+struct mlx5_ifc_resource_dump_resource_segment_bits {
1888+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1889+
1890+ u8 reserved_at_20[0x20];
1891+
1892+ u8 index1[0x20];
1893+
1894+ u8 index2[0x20];
1895+
1896+ u8 payload[0][0x20];
1897+};
1898+
1899+struct mlx5_ifc_resource_dump_terminate_segment_bits {
1900+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1901+};
1902+
1903+struct mlx5_ifc_menu_resource_dump_response_bits {
1904+ struct mlx5_ifc_resource_dump_info_segment_bits info;
1905+ struct mlx5_ifc_resource_dump_command_segment_bits cmd;
1906+ struct mlx5_ifc_resource_dump_menu_segment_bits menu;
1907+ struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
1908+};
1909+
17561910 enum {
17571911 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
17581912 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
@@ -2026,7 +2180,9 @@ struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { · 267 unmodified lines
20262180
20272181 u8 rx_pause_transition_low[0x20];
20282182
2029− u8 reserved_at_3c0[0x40];
2183+ u8 rx_discards_high[0x20];
2184+
2185+ u8 rx_discards_low[0x20];
20302186
20312187 u8 device_stall_minor_watermark_cnt_high[0x20];
20322188
@@ -2751,6 +2907,7 @@ union mlx5_ifc_hca_cap_union_bits { · 718 unmodified lines
27512907 struct mlx5_ifc_fpga_cap_bits fpga_cap;
27522908 struct mlx5_ifc_tls_cap_bits tls_cap;
27532909 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2910+ struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap;
27542911 u8 reserved_at_0[0x8000];
27552912 };
27562913
@@ -3998,7 +4155,8 @@ struct mlx5_ifc_set_fte_in_bits { · 1241 unmodified lines
39984155 u8 reserved_at_a0[0x8];
39994156 u8 table_id[0x18];
40004157
4001− u8 reserved_at_c0[0x18];
4158+ u8 ignore_flow_level[0x1];
4159+ u8 reserved_at_c1[0x17];
40024160 u8 modify_enable_mask[0x8];
40034161
40044162 u8 reserved_at_e0[0x20];
@@ -5466,15 +5624,32 @@ struct mlx5_ifc_add_action_in_bits { · 1461 unmodified lines
54665624 u8 data[0x20];
54675625 };
54685626
5627+struct mlx5_ifc_copy_action_in_bits {
5628+ u8 action_type[0x4];
5629+ u8 src_field[0xc];
5630+ u8 reserved_at_10[0x3];
5631+ u8 src_offset[0x5];
5632+ u8 reserved_at_18[0x3];
5633+ u8 length[0x5];
5634+
5635+ u8 reserved_at_20[0x4];
5636+ u8 dst_field[0xc];
5637+ u8 reserved_at_30[0x3];
5638+ u8 dst_offset[0x5];
5639+ u8 reserved_at_38[0x8];
5640+};
5641+
54695642 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
54705643 struct mlx5_ifc_set_action_in_bits set_action_in;
54715644 struct mlx5_ifc_add_action_in_bits add_action_in;
5645+ struct mlx5_ifc_copy_action_in_bits copy_action_in;
54725646 u8 reserved_at_0[0x40];
54735647 };
54745648
54755649 enum {
54765650 MLX5_ACTION_TYPE_SET = 0x1,
54775651 MLX5_ACTION_TYPE_ADD = 0x2,
5652+ MLX5_ACTION_TYPE_COPY = 0x3,
54785653 };
54795654
54805655 enum {
@@ -5510,6 +5685,8 @@ enum { · 29 unmodified lines
55105685 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
55115686 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
55125687 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5688+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
5689+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
55135690 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
55145691 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
55155692 };
@@ -8406,6 +8583,18 @@ struct mlx5_ifc_pplm_reg_bits { · 2890 unmodified lines
84068583 u8 fec_override_admin_50g[0x4];
84078584 u8 fec_override_admin_25g[0x4];
84088585 u8 fec_override_admin_10g_40g[0x4];
8586+
8587+ u8 fec_override_cap_400g_8x[0x10];
8588+ u8 fec_override_cap_200g_4x[0x10];
8589+
8590+ u8 fec_override_cap_100g_2x[0x10];
8591+ u8 fec_override_cap_50g_1x[0x10];
8592+
8593+ u8 fec_override_admin_400g_8x[0x10];
8594+ u8 fec_override_admin_200g_4x[0x10];
8595+
8596+ u8 fec_override_admin_100g_2x[0x10];
8597+ u8 fec_override_admin_50g_1x[0x10];
84098598 };
84108599
84118600 struct mlx5_ifc_ppcnt_reg_bits {
@@ -8732,7 +8921,9 @@ struct mlx5_ifc_mpegc_reg_bits { · 320 unmodified lines
87328921 };
87338922
87348923 struct mlx5_ifc_pcam_enhanced_features_bits {
8735− u8 reserved_at_0[0x6d];
8924+ u8 reserved_at_0[0x68];
8925+ u8 fec_50G_per_lane_in_pplm[0x1];
8926+ u8 reserved_at_69[0x4];
87368927 u8 rx_icrc_encapsulated_counter[0x1];
87378928 u8 reserved_at_6e[0x4];
87388929 u8 ptys_extended_ethernet[0x1];
@@ -8817,6 +9008,28 @@ struct mlx5_ifc_mcam_access_reg_bits { · 78 unmodified lines
88179008 u8 regs_31_to_0[0x20];
88189009 };
88199010
9011+struct mlx5_ifc_mcam_access_reg_bits1 {
9012+ u8 regs_127_to_96[0x20];
9013+
9014+ u8 regs_95_to_64[0x20];
9015+
9016+ u8 regs_63_to_32[0x20];
9017+
9018+ u8 regs_31_to_0[0x20];
9019+};
9020+
9021+struct mlx5_ifc_mcam_access_reg_bits2 {
9022+ u8 regs_127_to_99[0x1d];
9023+ u8 mirc[0x1];
9024+ u8 regs_97_to_96[0x2];
9025+
9026+ u8 regs_95_to_64[0x20];
9027+
9028+ u8 regs_63_to_32[0x20];
9029+
9030+ u8 regs_31_to_0[0x20];
9031+};
9032+
88209033 struct mlx5_ifc_mcam_reg_bits {
88219034 u8 reserved_at_0[0x8];
88229035 u8 feature_group[0x8];
@@ -8827,6 +9040,8 @@ struct mlx5_ifc_mcam_reg_bits { · 4 unmodified lines
88279040
88289041 union {
88299042 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9043+ struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9044+ struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
88309045 u8 reserved_at_0[0x80];
88319046 } mng_access_reg_cap_mask;
88329047
@@ -9432,6 +9647,13 @@ struct mlx5_ifc_mcda_reg_bits { · 599 unmodified lines
94329647 u8 data[0][0x20];
94339648 };
94349649
9650+struct mlx5_ifc_mirc_reg_bits {
9651+ u8 reserved_at_0[0x18];
9652+ u8 status_code[0x8];
9653+
9654+ u8 reserved_at_20[0x20];
9655+};
9656+
94359657 union mlx5_ifc_ports_control_registers_document_bits {
94369658 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
94379659 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
@@ -9487,6 +9709,7 @@ union mlx5_ifc_ports_control_registers_document_bits { · 49 unmodified lines
94879709 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
94889710 struct mlx5_ifc_mcc_reg_bits mcc_reg;
94899711 struct mlx5_ifc_mcda_reg_bits mcda_reg;
9712+ struct mlx5_ifc_mirc_reg_bits mirc_reg;
94909713 u8 reserved_at_0[0x60e0];
94919714 };
94929715