lael-labs/linux

drivers/gpu/drm/amd/amdgpu/Makefile+4−0

 amdgpu-y += \
 	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o
+# add DF block
+amdgpu-y += \
+	df_v1_7.o
 # add GMC block
 amdgpu-y += \
 	gmc_v7_0.o \

drivers/gpu/drm/amd/amdgpu/amdgpu.h+40−3

@@ -129,6 +129,7 @@ extern int amdgpu_lbpw; · 128 unmodified lines
129	extern int amdgpu_compute_multipipe;	129	extern int amdgpu_compute_multipipe;
130	extern int amdgpu_gpu_recovery;	130	extern int amdgpu_gpu_recovery;
131	extern int amdgpu_emu_mode;	131	extern int amdgpu_emu_mode;
		132	extern uint amdgpu_smu_memory_pool_size;
132		133
133	#ifdef CONFIG_DRM_AMDGPU_SI	134	#ifdef CONFIG_DRM_AMDGPU_SI
134	extern int amdgpu_si_support;	135	extern int amdgpu_si_support;
@@ -137,6 +138,7 @@ extern int amdgpu_si_support; · 2 unmodified lines
137	extern int amdgpu_cik_support;	138	extern int amdgpu_cik_support;
138	#endif	139	#endif
139		140
		141	#define AMDGPU_SG_THRESHOLD (25610241024)
140	#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */	142	#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
141	#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000	143	#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
142	#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */	144	#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
@@ -222,10 +224,10 @@ enum amdgpu_kiq_irq { · 79 unmodified lines
222	AMDGPU_CP_KIQ_IRQ_LAST	224	AMDGPU_CP_KIQ_IRQ_LAST
223	};	225	};
224		226
225	int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,	227	int amdgpu_device_ip_set_clockgating_state(void *dev,
226	enum amd_ip_block_type block_type,	228	enum amd_ip_block_type block_type,
227	enum amd_clockgating_state state);	229	enum amd_clockgating_state state);
228	int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,	230	int amdgpu_device_ip_set_powergating_state(void *dev,
229	enum amd_ip_block_type block_type,	231	enum amd_ip_block_type block_type,
230	enum amd_powergating_state state);	232	enum amd_powergating_state state);
231	void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,	233	void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
@@ -681,6 +683,8 @@ int amdgpu_ctx_ioctl(struct drm_device dev, void data, · 449 unmodified lines
681	int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);	683	int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
682		684
683	void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);	685	void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
		686	void amdgpu_ctx_mgr_entity_cleanup(struct amdgpu_ctx_mgr *mgr);
		687	void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
684	void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);	688	void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
685		689
686		690
@@ -771,9 +775,18 @@ struct amdgpu_rlc { · 84 unmodified lines
771	u32 starting_offsets_start;	775	u32 starting_offsets_start;
772	u32 reg_list_format_size_bytes;	776	u32 reg_list_format_size_bytes;
773	u32 reg_list_size_bytes;	777	u32 reg_list_size_bytes;
		778	u32 reg_list_format_direct_reg_list_length;
		779	u32 save_restore_list_cntl_size_bytes;
		780	u32 save_restore_list_gpm_size_bytes;
		781	u32 save_restore_list_srm_size_bytes;
774		782
775	u32 *register_list_format;	783	u32 *register_list_format;
776	u32 *register_restore;	784	u32 *register_restore;
		785	u8 *save_restore_list_cntl;
		786	u8 *save_restore_list_gpm;
		787	u8 *save_restore_list_srm;
		788
		789	bool is_rlc_v2_1;
777	};	790	};
778		791
779	#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES	792	#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
@@ -867,6 +880,8 @@ struct amdgpu_gfx_config { · 87 unmodified lines
867		880
868	/* gfx configure feature */	881	/* gfx configure feature */
869	uint32_t double_offchip_lds_buf;	882	uint32_t double_offchip_lds_buf;
		883	/* cached value of DB_DEBUG2 */
		884	uint32_t db_debug2;
870	};	885	};
871		886
872	struct amdgpu_cu_info {	887	struct amdgpu_cu_info {
@@ -938,6 +953,12 @@ struct amdgpu_gfx { · 65 unmodified lines
938	uint32_t ce_feature_version;	953	uint32_t ce_feature_version;
939	uint32_t pfp_feature_version;	954	uint32_t pfp_feature_version;
940	uint32_t rlc_feature_version;	955	uint32_t rlc_feature_version;
		956	uint32_t rlc_srlc_fw_version;
		957	uint32_t rlc_srlc_feature_version;
		958	uint32_t rlc_srlg_fw_version;
		959	uint32_t rlc_srlg_feature_version;
		960	uint32_t rlc_srls_fw_version;
		961	uint32_t rlc_srls_feature_version;
941	uint32_t mec_feature_version;	962	uint32_t mec_feature_version;
942	uint32_t mec2_feature_version;	963	uint32_t mec2_feature_version;
943	struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];	964	struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
@@ -1204,6 +1225,8 @@ struct amdgpu_asic_funcs { · 260 unmodified lines
1204	/* invalidate hdp read cache */	1225	/* invalidate hdp read cache */
1205	void (invalidate_hdp)(struct amdgpu_device adev,	1226	void (invalidate_hdp)(struct amdgpu_device adev,
1206	struct amdgpu_ring *ring);	1227	struct amdgpu_ring *ring);
		1228	/* check if the asic needs a full reset of if soft reset will work */
		1229	bool (need_full_reset)(struct amdgpu_device adev);
1207	};	1230	};
1208		1231
1209	/*	1232	/*
@@ -1368,7 +1391,17 @@ struct amdgpu_nbio_funcs { · 158 unmodified lines
1368	void (detect_hw_virt)(struct amdgpu_device adev);	1391	void (detect_hw_virt)(struct amdgpu_device adev);
1369	};	1392	};
1370		1393
1371		1394	struct amdgpu_df_funcs {
		1395	void (init)(struct amdgpu_device adev);
		1396	void (enable_broadcast_mode)(struct amdgpu_device adev,
		1397	bool enable);
		1398	u32 (get_fb_channel_number)(struct amdgpu_device adev);
		1399	u32 (get_hbm_channel_number)(struct amdgpu_device adev);
		1400	void (update_medium_grain_clock_gating)(struct amdgpu_device adev,
		1401	bool enable);
		1402	void (get_clockgating_state)(struct amdgpu_device adev,
		1403	u32 *flags);
		1404	};
1372	/* Define the HW IP blocks will be used in driver , add more if necessary */	1405	/* Define the HW IP blocks will be used in driver , add more if necessary */
1373	enum amd_hw_ip_block_type {	1406	enum amd_hw_ip_block_type {
1374	GC_HWIP = 1,	1407	GC_HWIP = 1,
@@ -1398,6 +1431,7 @@ enum amd_hw_ip_block_type { · 23 unmodified lines
1398	struct amd_powerplay {	1431	struct amd_powerplay {
1399	void *pp_handle;	1432	void *pp_handle;
1400	const struct amd_pm_funcs *pp_funcs;	1433	const struct amd_pm_funcs *pp_funcs;
		1434	uint32_t pp_feature;
1401	};	1435	};
1402		1436
1403	#define AMDGPU_RESET_MAGIC_NUM 64	1437	#define AMDGPU_RESET_MAGIC_NUM 64
@@ -1590,6 +1624,7 @@ struct amdgpu_device { · 186 unmodified lines
1590	uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];	1624	uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1591		1625
1592	const struct amdgpu_nbio_funcs *nbio_funcs;	1626	const struct amdgpu_nbio_funcs *nbio_funcs;
		1627	const struct amdgpu_df_funcs *df_funcs;
1593		1628
1594	/* delayed work_func for deferring clockgating during resume */	1629	/* delayed work_func for deferring clockgating during resume */
1595	struct delayed_work late_init_work;	1630	struct delayed_work late_init_work;
@@ -1764,6 +1799,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) · 168 unmodified lines
1764	#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))	1799	#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1765	#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))	1800	#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1766	#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))	1801	#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
		1802	#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1767	#define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))	1803	#define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
1768	#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))	1804	#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
1769	#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))	1805	#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
@@ -1790,6 +1826,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) · 20 unmodified lines
1790	#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))	1826	#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1791	#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))	1827	#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
1792	#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))	1828	#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
		1829	#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
1793	#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))	1830	#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
1794	#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))	1831	#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
1795	#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))	1832	#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c+5−6

@@ -290,12 +290,11 @@ static int acp_hw_init(void *handle) · 289 unmodified lines
290	else if (r)	290	else if (r)
291	return r;	291	return r;
292		292
293	r = cgs_get_pci_resource(adev->acp.cgs_device, CGS_RESOURCE_TYPE_MMIO,	293	if (adev->rmmio_size == 0 \|\| adev->rmmio_size < 0x5289)
294	0x5289, 0, &acp_base);	294	return -EINVAL;
295	if (r == -ENODEV)	295
296	return 0;	296	acp_base = adev->rmmio_base;
297	else if (r)	297
298	return r;
299	if (adev->asic_type != CHIP_STONEY) {	298	if (adev->asic_type != CHIP_STONEY) {
300	adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);	299	adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
301	if (adev->acp.acp_genpd == NULL)	300	if (adev->acp.acp_genpd == NULL)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c+9−3

 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 	struct amdgpu_bo *bo = NULL;
+	struct amdgpu_bo_param bp;
 	int r;
 	uint64_t gpu_addr_tmp = 0;
 	void *cpu_ptr_tmp = NULL;
-	r = amdgpu_bo_create(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
+	memset(&bp, 0, sizeof(bp));
-			     AMDGPU_GEM_CREATE_CPU_GTT_USWC, ttm_bo_type_kernel,
+	bp.size = size;
-			     NULL, &bo);
+	bp.byte_align = PAGE_SIZE;
+	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
+	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+	bp.type = ttm_bo_type_kernel;
+	bp.resv = NULL;
+	r = amdgpu_bo_create(adev, &bp, &bo);
 	if (r) {
 		dev_err(adev->dev,
 			"failed to allocate BO for amdkfd (%d)\n", r);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c+9−2

 	struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
 	uint64_t user_addr = 0;
 	struct amdgpu_bo *bo;
+	struct amdgpu_bo_param bp;
 	int byte_align;
 	u32 domain, alloc_domain;
 	u64 alloc_flags;
 	pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",
 			va, size, domain_string(alloc_domain));
-	ret = amdgpu_bo_create(adev, size, byte_align,
+	memset(&bp, 0, sizeof(bp));
-				alloc_domain, alloc_flags, ttm_bo_type_device, NULL, &bo);
+	bp.size = size;
+	bp.byte_align = byte_align;
+	bp.domain = alloc_domain;
+	bp.flags = alloc_flags;
+	bp.type = ttm_bo_type_device;
+	bp.resv = NULL;
+	ret = amdgpu_bo_create(adev, &bp, &bo);
 	if (ret) {
 		pr_debug("Failed to create BO on domain %s. ret %d\n",
 				domain_string(alloc_domain), ret);

drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c+1−1

@@ -550,7 +550,7 @@ static int amdgpu_atpx_init(void) · 549 unmodified lines
550	* look up whether we are the integrated or discrete GPU (all asics).	550	* look up whether we are the integrated or discrete GPU (all asics).
551	* Returns the client id.	551	* Returns the client id.
552	*/	552	*/
553	static int amdgpu_atpx_get_client_id(struct pci_dev *pdev)	553	static enum vga_switcheroo_client_id amdgpu_atpx_get_client_id(struct pci_dev *pdev)
554	{	554	{
555	if (amdgpu_atpx_priv.dhandle == ACPI_HANDLE(&pdev->dev))	555	if (amdgpu_atpx_priv.dhandle == ACPI_HANDLE(&pdev->dev))
556	return VGA_SWITCHEROO_IGD;	556	return VGA_SWITCHEROO_IGD;

drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c+11−4

 {
 	struct amdgpu_bo *dobj = NULL;
 	struct amdgpu_bo *sobj = NULL;
+	struct amdgpu_bo_param bp;
 	uint64_t saddr, daddr;
 	int r, n;
 	int time;
+	memset(&bp, 0, sizeof(bp));
+	bp.size = size;
+	bp.byte_align = PAGE_SIZE;
+	bp.domain = sdomain;
+	bp.flags = 0;
+	bp.type = ttm_bo_type_kernel;
+	bp.resv = NULL;
 	n = AMDGPU_BENCHMARK_ITERATIONS;
-	r = amdgpu_bo_create(adev, size, PAGE_SIZE,sdomain, 0,
+	r = amdgpu_bo_create(adev, &bp, &sobj);
-			     ttm_bo_type_kernel, NULL, &sobj);
 	if (r) {
 		goto out_cleanup;
 	}
 	if (r) {
 		goto out_cleanup;
 	}
-	r = amdgpu_bo_create(adev, size, PAGE_SIZE, ddomain, 0,
+	bp.domain = ddomain;
-			     ttm_bo_type_kernel, NULL, &dobj);
+	r = amdgpu_bo_create(adev, &bp, &dobj);
 	if (r) {
 		goto out_cleanup;
 	}

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c+3−241

@@ -23,7 +23,6 @@ · 22 unmodified lines
23	*/	23	*/
24	#include <linux/list.h>	24	#include <linux/list.h>
25	#include <linux/slab.h>	25	#include <linux/slab.h>
26	#include <linux/pci.h>
27	#include <drm/drmP.h>	26	#include <drm/drmP.h>
28	#include <linux/firmware.h>	27	#include <linux/firmware.h>
29	#include <drm/amdgpu_drm.h>	28	#include <drm/amdgpu_drm.h>
@@ -109,121 +108,6 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device, · 79 unmodified lines
109	WARN(1, "Invalid indirect register space");	108	WARN(1, "Invalid indirect register space");
110	}	109	}
111		110
112	static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
113	enum cgs_resource_type resource_type,
114	uint64_t size,
115	uint64_t offset,
116	uint64_t *resource_base)
117	{
118	CGS_FUNC_ADEV;
119
120	if (resource_base == NULL)
121	return -EINVAL;
122
123	switch (resource_type) {
124	case CGS_RESOURCE_TYPE_MMIO:
125	if (adev->rmmio_size == 0)
126	return -ENOENT;
127	if ((offset + size) > adev->rmmio_size)
128	return -EINVAL;
129	*resource_base = adev->rmmio_base;
130	return 0;
131	case CGS_RESOURCE_TYPE_DOORBELL:
132	if (adev->doorbell.size == 0)
133	return -ENOENT;
134	if ((offset + size) > adev->doorbell.size)
135	return -EINVAL;
136	*resource_base = adev->doorbell.base;
137	return 0;
138	case CGS_RESOURCE_TYPE_FB:
139	case CGS_RESOURCE_TYPE_IO:
140	case CGS_RESOURCE_TYPE_ROM:
141	default:
142	return -EINVAL;
143	}
144	}
145
146	static const void amdgpu_cgs_atom_get_data_table(struct cgs_device cgs_device,
147	unsigned table, uint16_t *size,
148	uint8_t frev, uint8_t crev)
149	{
150	CGS_FUNC_ADEV;
151	uint16_t data_start;
152
153	if (amdgpu_atom_parse_data_header(
154	adev->mode_info.atom_context, table, size,
155	frev, crev, &data_start))
156	return (uint8_t*)adev->mode_info.atom_context->bios +
157	data_start;
158
159	return NULL;
160	}
161
162	static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table,
163	uint8_t frev, uint8_t crev)
164	{
165	CGS_FUNC_ADEV;
166
167	if (amdgpu_atom_parse_cmd_header(
168	adev->mode_info.atom_context, table,
169	frev, crev))
170	return 0;
171
172	return -EINVAL;
173	}
174
175	static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table,
176	void *args)
177	{
178	CGS_FUNC_ADEV;
179
180	return amdgpu_atom_execute_table(
181	adev->mode_info.atom_context, table, args);
182	}
183
184	static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
185	enum amd_ip_block_type block_type,
186	enum amd_clockgating_state state)
187	{
188	CGS_FUNC_ADEV;
189	int i, r = -1;
190
191	for (i = 0; i < adev->num_ip_blocks; i++) {
192	if (!adev->ip_blocks[i].status.valid)
193	continue;
194
195	if (adev->ip_blocks[i].version->type == block_type) {
196	r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
197	(void *)adev,
198	state);
199	break;
200	}
201	}
202	return r;
203	}
204
205	static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
206	enum amd_ip_block_type block_type,
207	enum amd_powergating_state state)
208	{
209	CGS_FUNC_ADEV;
210	int i, r = -1;
211
212	for (i = 0; i < adev->num_ip_blocks; i++) {
213	if (!adev->ip_blocks[i].status.valid)
214	continue;
215
216	if (adev->ip_blocks[i].version->type == block_type) {
217	r = adev->ip_blocks[i].version->funcs->set_powergating_state(
218	(void *)adev,
219	state);
220	break;
221	}
222	}
223	return r;
224	}
225
226
227	static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)	111	static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
228	{	112	{
229	CGS_FUNC_ADEV;	113	CGS_FUNC_ADEV;
@@ -271,18 +155,6 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) · 41 unmodified lines
271	return result;	155	return result;
272	}	156	}
273		157
274	static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
275	{
276	CGS_FUNC_ADEV;
277	if ((CGS_UCODE_ID_SMU == type) \|\| (CGS_UCODE_ID_SMU_SK == type)) {
278	release_firmware(adev->pm.fw);
279	adev->pm.fw = NULL;
280	return 0;
281	}
282	/* cannot release other firmware because they are not created by cgs */
283	return -EINVAL;
284	}
285
286	static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,	158	static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
287	enum cgs_ucode_id type)	159	enum cgs_ucode_id type)
288	{	160	{
@@ -326,34 +198,6 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device, · 37 unmodified lines
326	return fw_version;	198	return fw_version;
327	}	199	}
328		200
329	static int amdgpu_cgs_enter_safe_mode(struct cgs_device *cgs_device,
330	bool en)
331	{
332	CGS_FUNC_ADEV;
333
334	if (adev->gfx.rlc.funcs->enter_safe_mode == NULL \|\|
335	adev->gfx.rlc.funcs->exit_safe_mode == NULL)
336	return 0;
337
338	if (en)
339	adev->gfx.rlc.funcs->enter_safe_mode(adev);
340	else
341	adev->gfx.rlc.funcs->exit_safe_mode(adev);
342
343	return 0;
344	}
345
346	static void amdgpu_cgs_lock_grbm_idx(struct cgs_device *cgs_device,
347	bool lock)
348	{
349	CGS_FUNC_ADEV;
350
351	if (lock)
352	mutex_lock(&adev->grbm_idx_mutex);
353	else
354	mutex_unlock(&adev->grbm_idx_mutex);
355	}
356
357	static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,	201	static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
358	enum cgs_ucode_id type,	202	enum cgs_ucode_id type,
359	struct cgs_firmware_info *info)	203	struct cgs_firmware_info *info)
@@ -541,6 +385,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, · 181 unmodified lines
541	case CHIP_POLARIS12:	385	case CHIP_POLARIS12:
542	strcpy(fw_name, "amdgpu/polaris12_smc.bin");	386	strcpy(fw_name, "amdgpu/polaris12_smc.bin");
543	break;	387	break;
		388	case CHIP_VEGAM:
		389	strcpy(fw_name, "amdgpu/vegam_smc.bin");
		390	break;
544	case CHIP_VEGA10:	391	case CHIP_VEGA10:
545	if ((adev->pdev->device == 0x687f) &&	392	if ((adev->pdev->device == 0x687f) &&
546	((adev->pdev->revision == 0xc0) \|\|	393	((adev->pdev->revision == 0xc0) \|\|
@@ -598,97 +445,12 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, · 51 unmodified lines
598	return 0;	445	return 0;
599	}	446	}
600		447
601	static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device)
602	{
603	CGS_FUNC_ADEV;
604	return amdgpu_sriov_vf(adev);
605	}
606
607	static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
608	struct cgs_display_info *info)
609	{
610	CGS_FUNC_ADEV;
611	struct cgs_mode_info *mode_info;
612
613	if (info == NULL)
614	return -EINVAL;
615
616	mode_info = info->mode_info;
617	if (mode_info)
618	/* if the displays are off, vblank time is max */
619	mode_info->vblank_time_us = 0xffffffff;
620
621	if (!amdgpu_device_has_dc_support(adev)) {
622	struct amdgpu_crtc *amdgpu_crtc;
623	struct drm_device *ddev = adev->ddev;
624	struct drm_crtc *crtc;
625	uint32_t line_time_us, vblank_lines;
626
627	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
628	list_for_each_entry(crtc,
629	&ddev->mode_config.crtc_list, head) {
630	amdgpu_crtc = to_amdgpu_crtc(crtc);
631	if (crtc->enabled) {
632	info->active_display_mask \|= (1 << amdgpu_crtc->crtc_id);
633	info->display_count++;
634	}
635	if (mode_info != NULL &&
636	crtc->enabled && amdgpu_crtc->enabled &&
637	amdgpu_crtc->hw_mode.clock) {
638	line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
639	amdgpu_crtc->hw_mode.clock;
640	vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
641	amdgpu_crtc->hw_mode.crtc_vdisplay +
642	(amdgpu_crtc->v_border * 2);
643	mode_info->vblank_time_us = vblank_lines * line_time_us;
644	mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
645	/* we have issues with mclk switching with refresh rates
646	* over 120 hz on the non-DC code.
647	*/
648	if (mode_info->refresh_rate > 120)
649	mode_info->vblank_time_us = 0;
650	mode_info = NULL;
651	}
652	}
653	}
654	} else {
655	info->display_count = adev->pm.pm_display_cfg.num_display;
656	if (mode_info != NULL) {
657	mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time;
658	mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh;
659	}
660	}
661	return 0;
662	}
663
664
665	static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
666	{
667	CGS_FUNC_ADEV;
668
669	adev->pm.dpm_enabled = enabled;
670
671	return 0;
672	}
673
674	static const struct cgs_ops amdgpu_cgs_ops = {	448	static const struct cgs_ops amdgpu_cgs_ops = {
675	.read_register = amdgpu_cgs_read_register,	449	.read_register = amdgpu_cgs_read_register,
676	.write_register = amdgpu_cgs_write_register,	450	.write_register = amdgpu_cgs_write_register,
677	.read_ind_register = amdgpu_cgs_read_ind_register,	451	.read_ind_register = amdgpu_cgs_read_ind_register,
678	.write_ind_register = amdgpu_cgs_write_ind_register,	452	.write_ind_register = amdgpu_cgs_write_ind_register,
679	.get_pci_resource = amdgpu_cgs_get_pci_resource,
680	.atom_get_data_table = amdgpu_cgs_atom_get_data_table,
681	.atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
682	.atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
683	.get_firmware_info = amdgpu_cgs_get_firmware_info,	453	.get_firmware_info = amdgpu_cgs_get_firmware_info,
684	.rel_firmware = amdgpu_cgs_rel_firmware,
685	.set_powergating_state = amdgpu_cgs_set_powergating_state,
686	.set_clockgating_state = amdgpu_cgs_set_clockgating_state,
687	.get_active_displays_info = amdgpu_cgs_get_active_displays_info,
688	.notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
689	.is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
690	.enter_safe_mode = amdgpu_cgs_enter_safe_mode,
691	.lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
692	};	454	};
693		455
694	struct cgs_device amdgpu_cgs_create_device(struct amdgpu_device adev)	456	struct cgs_device amdgpu_cgs_create_device(struct amdgpu_device adev)

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c+4−4

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+5−11

 	p->bytes_moved += ctx.bytes_moved;
 	if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
-	    bo->tbo.mem.mem_type == TTM_PL_VRAM &&
+	    amdgpu_bo_in_cpu_visible_vram(bo))
-	    bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
 		p->bytes_moved_vis += ctx.bytes_moved;
 	if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 		struct amdgpu_bo_list_entry *candidate = p->evictable;
 		struct amdgpu_bo *bo = candidate->robj;
 		struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
-		u64 initial_bytes_moved, bytes_moved;
 		bool update_bytes_moved_vis;
 		uint32_t other;
 			continue;
 		/* Good we can try to move this BO somewhere else */
-		amdgpu_ttm_placement_from_domain(bo, other);
 		update_bytes_moved_vis =
 			adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
-			bo->tbo.mem.mem_type == TTM_PL_VRAM &&
+			amdgpu_bo_in_cpu_visible_vram(bo);
-			bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT;
+		amdgpu_ttm_placement_from_domain(bo, other);
-		initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 		r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
-		bytes_moved = atomic64_read(&adev->num_bytes_moved) -
+		p->bytes_moved += ctx.bytes_moved;
-			initial_bytes_moved;
-		p->bytes_moved += bytes_moved;
 		if (update_bytes_moved_vis)
-			p->bytes_moved_vis += bytes_moved;
+			p->bytes_moved_vis += ctx.bytes_moved;
 		if (unlikely(r))
 			break;

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c+61−11

 			continue;
 		r = drm_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
-					  rq, amdgpu_sched_jobs, &ctx->guilty);
+					  rq, &ctx->guilty);
 		if (r)
 			goto failed;
 	}
 	return r;
 }
-static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
+static void amdgpu_ctx_fini(struct kref *ref)
 {
+	struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount);
 	struct amdgpu_device *adev = ctx->adev;
 	unsigned i, j;
 	kfree(ctx->fences);
 	ctx->fences = NULL;
-	for (i = 0; i < adev->num_rings; i++)
-		drm_sched_entity_fini(&adev->rings[i]->sched,
-				      &ctx->rings[i].entity);
 	amdgpu_queue_mgr_fini(adev, &ctx->queue_mgr);
 	mutex_destroy(&ctx->lock);
+	kfree(ctx);
 }
 static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
 static void amdgpu_ctx_do_release(struct kref *ref)
 {
 	struct amdgpu_ctx *ctx;
+	u32 i;
 	ctx = container_of(ref, struct amdgpu_ctx, refcount);
-	amdgpu_ctx_fini(ctx);
+	for (i = 0; i < ctx->adev->num_rings; i++)
+		drm_sched_entity_fini(&ctx->adev->rings[i]->sched,
+			&ctx->rings[i].entity);
-	kfree(ctx);
+	amdgpu_ctx_fini(ref);
 }
 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
 	if (other) {
 		signed long r;
-		r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
+		r = dma_fence_wait(other, true);
 		if (r < 0) {
-			DRM_ERROR("Error (%ld) waiting for fence!\n", r);
+			if (r != -ERESTARTSYS)
+				DRM_ERROR("Error (%ld) waiting for fence!\n", r);
 			return r;
 		}
 	}
 	idr_init(&mgr->ctx_handles);
 }
+void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
+{
+	struct amdgpu_ctx *ctx;
+	struct idr *idp;
+	uint32_t id, i;
+	idp = &mgr->ctx_handles;
+	idr_for_each_entry(idp, ctx, id) {
+		if (!ctx->adev)
+			return;
+		for (i = 0; i < ctx->adev->num_rings; i++)
+			if (kref_read(&ctx->refcount) == 1)
+				drm_sched_entity_do_release(&ctx->adev->rings[i]->sched,
+						  &ctx->rings[i].entity);
+			else
+				DRM_ERROR("ctx %p is still alive\n", ctx);
+	}
+}
+void amdgpu_ctx_mgr_entity_cleanup(struct amdgpu_ctx_mgr *mgr)
+{
+	struct amdgpu_ctx *ctx;
+	struct idr *idp;
+	uint32_t id, i;
+	idp = &mgr->ctx_handles;
+	idr_for_each_entry(idp, ctx, id) {
+		if (!ctx->adev)
+			return;
+		for (i = 0; i < ctx->adev->num_rings; i++)
+			if (kref_read(&ctx->refcount) == 1)
+				drm_sched_entity_cleanup(&ctx->adev->rings[i]->sched,
+					&ctx->rings[i].entity);
+			else
+				DRM_ERROR("ctx %p is still alive\n", ctx);
+	}
+}
 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
 {
 	struct amdgpu_ctx *ctx;
 	struct idr *idp;
 	uint32_t id;
+	amdgpu_ctx_mgr_entity_cleanup(mgr);
 	idp = &mgr->ctx_handles;
 	idr_for_each_entry(idp, ctx, id) {
-		if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
+		if (kref_put(&ctx->refcount, amdgpu_ctx_fini) != 1)
 			DRM_ERROR("ctx %p is still alive\n", ctx);
 	}

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c+190−5

@@ -28,8 +28,13 @@ · 27 unmodified lines
28	#include <linux/debugfs.h>	28	#include <linux/debugfs.h>
29	#include "amdgpu.h"	29	#include "amdgpu.h"
30		30
31	/*	31	/**
32	* Debugfs	32	* amdgpu_debugfs_add_files - Add simple debugfs entries
		33	*
		34	* @adev: Device to attach debugfs entries to
		35	* @files: Array of function callbacks that respond to reads
		36	* @nfiles: Number of callbacks to register
		37	*
33	*/	38	*/
34	int amdgpu_debugfs_add_files(struct amdgpu_device *adev,	39	int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
35	const struct drm_info_list *files,	40	const struct drm_info_list *files,
@@ -64,7 +69,33 @@ int amdgpu_debugfs_add_files(struct amdgpu_device *adev, · 28 unmodified lines
64		69
65	#if defined(CONFIG_DEBUG_FS)	70	#if defined(CONFIG_DEBUG_FS)
66		71
67		72	/**
		73	* amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
		74	*
		75	* @read: True if reading
		76	* @f: open file handle
		77	* @buf: User buffer to write/read to
		78	* @size: Number of bytes to write/read
		79	* @pos: Offset to seek to
		80	*
		81	* This debugfs entry has special meaning on the offset being sought.
		82	* Various bits have different meanings:
		83	*
		84	* Bit 62: Indicates a GRBM bank switch is needed
		85	* Bit 61: Indicates a SRBM bank switch is needed (implies bit 62 is
		86	* zero)
		87	* Bits 24..33: The SE or ME selector if needed
		88	* Bits 34..43: The SH (or SA) or PIPE selector if needed
		89	* Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
		90	*
		91	* Bit 23: Indicates that the PM power gating lock should be held
		92	* This is necessary to read registers that might be
		93	* unreliable during a power gating transistion.
		94	*
		95	* The lower bits are the BYTE offset of the register to read. This
		96	* allows reading multiple registers in a single call and having
		97	* the returned size reflect that.
		98	*/
68	static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,	99	static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
69	char __user buf, size_t size, loff_t pos)	100	char __user buf, size_t size, loff_t pos)
70	{	101	{
@@ -164,19 +195,37 @@ end: · 93 unmodified lines
164	return result;	195	return result;
165	}	196	}
166		197
167		198	/**
		199	* amdgpu_debugfs_regs_read - Callback for reading MMIO registers
		200	*/
168	static ssize_t amdgpu_debugfs_regs_read(struct file f, char __user buf,	201	static ssize_t amdgpu_debugfs_regs_read(struct file f, char __user buf,
169	size_t size, loff_t *pos)	202	size_t size, loff_t *pos)
170	{	203	{
171	return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);	204	return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
172	}	205	}
173		206
		207	/**
		208	* amdgpu_debugfs_regs_write - Callback for writing MMIO registers
		209	*/
174	static ssize_t amdgpu_debugfs_regs_write(struct file f, const char __user buf,	210	static ssize_t amdgpu_debugfs_regs_write(struct file f, const char __user buf,
175	size_t size, loff_t *pos)	211	size_t size, loff_t *pos)
176	{	212	{
177	return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);	213	return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
178	}	214	}
179		215
		216
		217	/**
		218	* amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
		219	*
		220	* @f: open file handle
		221	* @buf: User buffer to store read data in
		222	* @size: Number of bytes to read
		223	* @pos: Offset to seek to
		224	*
		225	* The lower bits are the BYTE offset of the register to read. This
		226	* allows reading multiple registers in a single call and having
		227	* the returned size reflect that.
		228	*/
180	static ssize_t amdgpu_debugfs_regs_pcie_read(struct file f, char __user buf,	229	static ssize_t amdgpu_debugfs_regs_pcie_read(struct file f, char __user buf,
181	size_t size, loff_t *pos)	230	size_t size, loff_t *pos)
182	{	231	{
@@ -204,6 +253,18 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file f, char __user buf, · 21 unmodified lines
204	return result;	253	return result;
205	}	254	}
206		255
		256	/**
		257	* amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
		258	*
		259	* @f: open file handle
		260	* @buf: User buffer to write data from
		261	* @size: Number of bytes to write
		262	* @pos: Offset to seek to
		263	*
		264	* The lower bits are the BYTE offset of the register to write. This
		265	* allows writing multiple registers in a single call and having
		266	* the returned size reflect that.
		267	*/
207	static ssize_t amdgpu_debugfs_regs_pcie_write(struct file f, const char __user buf,	268	static ssize_t amdgpu_debugfs_regs_pcie_write(struct file f, const char __user buf,
208	size_t size, loff_t *pos)	269	size_t size, loff_t *pos)
209	{	270	{
@@ -232,6 +293,18 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user · 22 unmodified lines
232	return result;	293	return result;
233	}	294	}
234		295
		296	/**
		297	* amdgpu_debugfs_regs_didt_read - Read from a DIDT register
		298	*
		299	* @f: open file handle
		300	* @buf: User buffer to store read data in
		301	* @size: Number of bytes to read
		302	* @pos: Offset to seek to
		303	*
		304	* The lower bits are the BYTE offset of the register to read. This
		305	* allows reading multiple registers in a single call and having
		306	* the returned size reflect that.
		307	*/
235	static ssize_t amdgpu_debugfs_regs_didt_read(struct file f, char __user buf,	308	static ssize_t amdgpu_debugfs_regs_didt_read(struct file f, char __user buf,
236	size_t size, loff_t *pos)	309	size_t size, loff_t *pos)
237	{	310	{
@@ -259,6 +332,18 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file f, char __user buf, · 21 unmodified lines
259	return result;	332	return result;
260	}	333	}
261		334
		335	/**
		336	* amdgpu_debugfs_regs_didt_write - Write to a DIDT register
		337	*
		338	* @f: open file handle
		339	* @buf: User buffer to write data from
		340	* @size: Number of bytes to write
		341	* @pos: Offset to seek to
		342	*
		343	* The lower bits are the BYTE offset of the register to write. This
		344	* allows writing multiple registers in a single call and having
		345	* the returned size reflect that.
		346	*/
262	static ssize_t amdgpu_debugfs_regs_didt_write(struct file f, const char __user buf,	347	static ssize_t amdgpu_debugfs_regs_didt_write(struct file f, const char __user buf,
263	size_t size, loff_t *pos)	348	size_t size, loff_t *pos)
264	{	349	{
@@ -287,6 +372,18 @@ static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user · 22 unmodified lines
287	return result;	372	return result;
288	}	373	}
289		374
		375	/**
		376	* amdgpu_debugfs_regs_smc_read - Read from a SMC register
		377	*
		378	* @f: open file handle
		379	* @buf: User buffer to store read data in
		380	* @size: Number of bytes to read
		381	* @pos: Offset to seek to
		382	*
		383	* The lower bits are the BYTE offset of the register to read. This
		384	* allows reading multiple registers in a single call and having
		385	* the returned size reflect that.
		386	*/
290	static ssize_t amdgpu_debugfs_regs_smc_read(struct file f, char __user buf,	387	static ssize_t amdgpu_debugfs_regs_smc_read(struct file f, char __user buf,
291	size_t size, loff_t *pos)	388	size_t size, loff_t *pos)
292	{	389	{
@@ -314,6 +411,18 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file f, char __user buf, · 21 unmodified lines
314	return result;	411	return result;
315	}	412	}
316		413
		414	/**
		415	* amdgpu_debugfs_regs_smc_write - Write to a SMC register
		416	*
		417	* @f: open file handle
		418	* @buf: User buffer to write data from
		419	* @size: Number of bytes to write
		420	* @pos: Offset to seek to
		421	*
		422	* The lower bits are the BYTE offset of the register to write. This
		423	* allows writing multiple registers in a single call and having
		424	* the returned size reflect that.
		425	*/
317	static ssize_t amdgpu_debugfs_regs_smc_write(struct file f, const char __user buf,	426	static ssize_t amdgpu_debugfs_regs_smc_write(struct file f, const char __user buf,
318	size_t size, loff_t *pos)	427	size_t size, loff_t *pos)
319	{	428	{
@@ -342,6 +451,20 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file f, const char __user · 22 unmodified lines
342	return result;	451	return result;
343	}	452	}
344		453
		454	/**
		455	* amdgpu_debugfs_gca_config_read - Read from gfx config data
		456	*
		457	* @f: open file handle
		458	* @buf: User buffer to store read data in
		459	* @size: Number of bytes to read
		460	* @pos: Offset to seek to
		461	*
		462	* This file is used to access configuration data in a somewhat
		463	* stable fashion. The format is a series of DWORDs with the first
		464	* indicating which revision it is. New content is appended to the
		465	* end so that older software can still read the data.
		466	*/
		467
345	static ssize_t amdgpu_debugfs_gca_config_read(struct file f, char __user buf,	468	static ssize_t amdgpu_debugfs_gca_config_read(struct file f, char __user buf,
346	size_t size, loff_t *pos)	469	size_t size, loff_t *pos)
347	{	470	{
@@ -418,6 +541,19 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file f, char __user buf, · 70 unmodified lines
418	return result;	541	return result;
419	}	542	}
420		543
		544	/**
		545	* amdgpu_debugfs_sensor_read - Read from the powerplay sensors
		546	*
		547	* @f: open file handle
		548	* @buf: User buffer to store read data in
		549	* @size: Number of bytes to read
		550	* @pos: Offset to seek to
		551	*
		552	* The offset is treated as the BYTE address of one of the sensors
		553	* enumerated in amd/include/kgd_pp_interface.h under the
		554	* 'amd_pp_sensors' enumeration. For instance to read the UVD VCLK
		555	* you would use the offset 3 * 4 = 12.
		556	*/
421	static ssize_t amdgpu_debugfs_sensor_read(struct file f, char __user buf,	557	static ssize_t amdgpu_debugfs_sensor_read(struct file f, char __user buf,
422	size_t size, loff_t *pos)	558	size_t size, loff_t *pos)
423	{	559	{
@@ -428,7 +564,7 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file f, char __user buf, · 4 unmodified lines
428	if (size & 3 \|\| *pos & 0x3)	564	if (size & 3 \|\| *pos & 0x3)
429	return -EINVAL;	565	return -EINVAL;
430		566
431	if (amdgpu_dpm == 0)	567	if (!adev->pm.dpm_enabled)
432	return -EINVAL;	568	return -EINVAL;
433		569
434	/* convert offset to sensor number */	570	/* convert offset to sensor number */
@@ -457,6 +593,27 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file f, char __user buf, · 22 unmodified lines
457	return !r ? outsize : r;	593	return !r ? outsize : r;
458	}	594	}
459		595
		596	/** amdgpu_debugfs_wave_read - Read WAVE STATUS data
		597	*
		598	* @f: open file handle
		599	* @buf: User buffer to store read data in
		600	* @size: Number of bytes to read
		601	* @pos: Offset to seek to
		602	*
		603	* The offset being sought changes which wave that the status data
		604	* will be returned for. The bits are used as follows:
		605	*
		606	* Bits 0..6: Byte offset into data
		607	* Bits 7..14: SE selector
		608	* Bits 15..22: SH/SA selector
		609	* Bits 23..30: CU/{WGP+SIMD} selector
		610	* Bits 31..36: WAVE ID selector
		611	* Bits 37..44: SIMD ID selector
		612	*
		613	* The returned data begins with one DWORD of version information
		614	* Followed by WAVE STATUS registers relevant to the GFX IP version
		615	* being used. See gfx_v8_0_read_wave_data() for an example output.
		616	*/
460	static ssize_t amdgpu_debugfs_wave_read(struct file f, char __user buf,	617	static ssize_t amdgpu_debugfs_wave_read(struct file f, char __user buf,
461	size_t size, loff_t *pos)	618	size_t size, loff_t *pos)
462	{	619	{
@@ -507,6 +664,28 @@ static ssize_t amdgpu_debugfs_wave_read(struct file f, char __user buf, · 44 unmodified lines
507	return result;	664	return result;
508	}	665	}
509		666
		667	/** amdgpu_debugfs_gpr_read - Read wave gprs
		668	*
		669	* @f: open file handle
		670	* @buf: User buffer to store read data in
		671	* @size: Number of bytes to read
		672	* @pos: Offset to seek to
		673	*
		674	* The offset being sought changes which wave that the status data
		675	* will be returned for. The bits are used as follows:
		676	*
		677	* Bits 0..11: Byte offset into data
		678	* Bits 12..19: SE selector
		679	* Bits 20..27: SH/SA selector
		680	* Bits 28..35: CU/{WGP+SIMD} selector
		681	* Bits 36..43: WAVE ID selector
		682	* Bits 37..44: SIMD ID selector
		683	* Bits 52..59: Thread selector
		684	* Bits 60..61: Bank selector (VGPR=0,SGPR=1)
		685	*
		686	* The return data comes from the SGPR or VGPR register bank for
		687	* the selected operational unit.
		688	*/
510	static ssize_t amdgpu_debugfs_gpr_read(struct file f, char __user buf,	689	static ssize_t amdgpu_debugfs_gpr_read(struct file f, char __user buf,
511	size_t size, loff_t *pos)	690	size_t size, loff_t *pos)
512	{	691	{
@@ -637,6 +816,12 @@ static const char *debugfs_regs_names[] = { · 124 unmodified lines
637	"amdgpu_gpr",	816	"amdgpu_gpr",
638	};	817	};
639		818
		819	/**
		820	* amdgpu_debugfs_regs_init - Initialize debugfs entries that provide
		821	* register access.
		822	*
		823	* @adev: The device to attach the debugfs entries to
		824	*/
640	int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)	825	int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
641	{	826	{
642	struct drm_minor *minor = adev->ddev->primary;	827	struct drm_minor *minor = adev->ddev->primary;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+80−25

 	"POLARIS10",
 	"POLARIS11",
 	"POLARIS12",
+	"VEGAM",
 	"VEGA10",
 	"VEGA12",
 	"RAVEN",
 {
 	u64 size_af, size_bf;
+	mc->gart_size += adev->pm.smu_prv_buffer_size;
 	size_af = adev->gmc.mc_mask - mc->vram_end;
 	size_bf = mc->vram_start;
 	if (size_bf > size_af) {
 	}
 }
+static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
+{
+	struct sysinfo si;
+	bool is_os_64 = (sizeof(void *) == 8) ? true : false;
+	uint64_t total_memory;
+	uint64_t dram_size_seven_GB = 0x1B8000000;
+	uint64_t dram_size_three_GB = 0xB8000000;
+	if (amdgpu_smu_memory_pool_size == 0)
+		return;
+	if (!is_os_64) {
+		DRM_WARN("Not 64-bit OS, feature not supported\n");
+		goto def_value;
+	}
+	si_meminfo(&si);
+	total_memory = (uint64_t)si.totalram * si.mem_unit;
+	if ((amdgpu_smu_memory_pool_size == 1) ||
+		(amdgpu_smu_memory_pool_size == 2)) {
+		if (total_memory < dram_size_three_GB)
+			goto def_value1;
+	} else if ((amdgpu_smu_memory_pool_size == 4) ||
+		(amdgpu_smu_memory_pool_size == 8)) {
+		if (total_memory < dram_size_seven_GB)
+			goto def_value1;
+	} else {
+		DRM_WARN("Smu memory pool size not supported\n");
+		goto def_value;
+	}
+	adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
+	return;
+def_value1:
+	DRM_WARN("No enough system memory\n");
+def_value:
+	adev->pm.smu_prv_buffer_size = 0;
+}
 /**
  * amdgpu_device_check_arguments - validate module params
  *
 		amdgpu_vm_fragment_size = -1;
 	}
+	amdgpu_device_check_smu_prv_buffer_size(adev);
 	amdgpu_device_check_vm_size(adev);
 	amdgpu_device_check_block_size(adev);
  * the hardware IP specified.
  * Returns the error code from the last instance.
  */
-int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
+int amdgpu_device_ip_set_clockgating_state(void *dev,
 					   enum amd_ip_block_type block_type,
 					   enum amd_clockgating_state state)
 {
+	struct amdgpu_device *adev = dev;
 	int i, r = 0;
 	for (i = 0; i < adev->num_ip_blocks; i++) {
  * the hardware IP specified.
  * Returns the error code from the last instance.
  */
-int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
+int amdgpu_device_ip_set_powergating_state(void *dev,
 					   enum amd_ip_block_type block_type,
 					   enum amd_powergating_state state)
 {
+	struct amdgpu_device *adev = dev;
 	int i, r = 0;
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 	case CHIP_TOPAZ:
 	case CHIP_TONGA:
 	case CHIP_FIJI:
-	case CHIP_POLARIS11:
 	case CHIP_POLARIS10:
+	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
+	case CHIP_VEGAM:
 	case CHIP_CARRIZO:
 	case CHIP_STONEY:
 #ifdef CONFIG_DRM_AMDGPU_SI
 	case CHIP_TOPAZ:
 	case CHIP_TONGA:
 	case CHIP_FIJI:
-	case CHIP_POLARIS11:
 	case CHIP_POLARIS10:
+	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
+	case CHIP_VEGAM:
 	case CHIP_CARRIZO:
 	case CHIP_STONEY:
 		if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
 			return -EAGAIN;
 	}
+	adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
 			DRM_ERROR("disabled ip block: %d <%s>\n",
 	if (amdgpu_emu_mode == 1)
 		return 0;
+	r = amdgpu_ib_ring_tests(adev);
+	if (r)
+		DRM_ERROR("ib ring test failed (%d).\n", r);
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if (!adev->ip_blocks[i].status.valid)
 			continue;
 		}
 	}
-	mod_delayed_work(system_wq, &adev->late_init_work,
+	queue_delayed_work(system_wq, &adev->late_init_work,
-			msecs_to_jiffies(AMDGPU_RESUME_MS));
+			   msecs_to_jiffies(AMDGPU_RESUME_MS));
 	amdgpu_device_fill_reset_magic(adev);
 	if (amdgpu_sriov_vf(adev))
 		amdgpu_virt_request_full_gpu(adev, false);
+	/* ungate SMC block powergating */
+	if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
+		amdgpu_device_ip_set_powergating_state(adev,
+						       AMD_IP_BLOCK_TYPE_SMC,
+						       AMD_CG_STATE_UNGATE);
 	/* ungate SMC block first */
 	r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
 						   AMD_CG_STATE_UNGATE);
 	case CHIP_MULLINS:
 	case CHIP_CARRIZO:
 	case CHIP_STONEY:
-	case CHIP_POLARIS11:
 	case CHIP_POLARIS10:
+	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
+	case CHIP_VEGAM:
 	case CHIP_TONGA:
 	case CHIP_FIJI:
-#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
-		return amdgpu_dc != 0;
-#endif
 	case CHIP_VEGA10:
 	case CHIP_VEGA12:
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 		goto failed;
 	}
-	r = amdgpu_ib_ring_tests(adev);
-	if (r)
-		DRM_ERROR("ib ring test failed (%d).\n", r);
 	if (amdgpu_sriov_vf(adev))
 		amdgpu_virt_init_data_exchange(adev);
 	/* unpin the front buffers and cursors */
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-		struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
+		struct drm_framebuffer *fb = crtc->primary->fb;
 		struct amdgpu_bo *robj;
 		if (amdgpu_crtc->cursor_bo) {
 			}
 		}
-		if (rfb == NULL || rfb->obj == NULL) {
+		if (fb == NULL || fb->obj[0] == NULL) {
 			continue;
 		}
-		robj = gem_to_amdgpu_bo(rfb->obj);
+		robj = gem_to_amdgpu_bo(fb->obj[0]);
 		/* don't unpin kernel fb objects */
 		if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
 			r = amdgpu_bo_reserve(robj, true);
 	}
 	amdgpu_fence_driver_resume(adev);
-	if (resume) {
-		r = amdgpu_ib_ring_tests(adev);
-		if (r)
-			DRM_ERROR("ib ring test failed (%d).\n", r);
-	}
 	r = amdgpu_device_ip_late_init(adev);
 	if (r)
 	if (amdgpu_sriov_vf(adev))
 		return true;
+	if (amdgpu_asic_need_full_reset(adev))
+		return true;
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if (!adev->ip_blocks[i].status.valid)
 			continue;
 {
 	int i;
+	if (amdgpu_asic_need_full_reset(adev))
+		return true;
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if (!adev->ip_blocks[i].status.valid)
 			continue;
 	/* now we are okay to resume SMC/CP/SDMA */
 	r = amdgpu_device_ip_reinit_late_sriov(adev);
-	amdgpu_virt_release_full_gpu(adev, true);
 	if (r)
 		goto error;
 	amdgpu_irq_gpu_reset_resume_helper(adev);
 	r = amdgpu_ib_ring_tests(adev);
+error:
+	amdgpu_virt_release_full_gpu(adev, true);
 	if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
 		atomic_inc(&adev->vram_lost_counter);
 		r = amdgpu_device_handle_vram_lost(adev);
 	}
-error:
 	return r;
 }

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c+9−31

 #include <linux/pm_runtime.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_edid.h>
+#include <drm/drm_gem_framebuffer_helper.h>
 #include <drm/drm_fb_helper.h>
 static void amdgpu_display_flip_callback(struct dma_fence *f,
 	struct drm_device *dev = crtc->dev;
 	struct amdgpu_device *adev = dev->dev_private;
 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-	struct amdgpu_framebuffer *old_amdgpu_fb;
-	struct amdgpu_framebuffer *new_amdgpu_fb;
 	struct drm_gem_object *obj;
 	struct amdgpu_flip_work *work;
 	struct amdgpu_bo *new_abo;
 	work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 	/* schedule unpin of the old buffer */
-	old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
+	obj = crtc->primary->fb->obj[0];
-	obj = old_amdgpu_fb->obj;
 	/* take a reference to the old object */
 	work->old_abo = gem_to_amdgpu_bo(obj);
 	amdgpu_bo_ref(work->old_abo);
-	new_amdgpu_fb = to_amdgpu_framebuffer(fb);
+	obj = fb->obj[0];
-	obj = new_amdgpu_fb->obj;
 	new_abo = gem_to_amdgpu_bo(obj);
 	/* pin the new buffer */
 		goto cleanup;
 	}
-	r = amdgpu_bo_pin(new_abo, amdgpu_display_framebuffer_domains(adev), &base);
+	r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev), &base);
 	if (unlikely(r != 0)) {
 		DRM_ERROR("failed to pin new abo buffer before flip\n");
 		goto unreserve;
 	return true;
 }
-static void amdgpu_display_user_framebuffer_destroy(struct drm_framebuffer *fb)
-{
-	struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
-	drm_gem_object_put_unlocked(amdgpu_fb->obj);
-	drm_framebuffer_cleanup(fb);
-	kfree(amdgpu_fb);
-}
-static int amdgpu_display_user_framebuffer_create_handle(
-			struct drm_framebuffer *fb,
-			struct drm_file *file_priv,
-			unsigned int *handle)
-{
-	struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
-	return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle);
-}
 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
-	.destroy = amdgpu_display_user_framebuffer_destroy,
+	.destroy = drm_gem_fb_destroy,
-	.create_handle = amdgpu_display_user_framebuffer_create_handle,
+	.create_handle = drm_gem_fb_create_handle,
 };
-uint32_t amdgpu_display_framebuffer_domains(struct amdgpu_device *adev)
+uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
 {
 	uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 				    struct drm_gem_object *obj)
 {
 	int ret;
-	rfb->obj = obj;
+	rfb->base.obj[0] = obj;
 	drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
 	ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
 	if (ret) {
-		rfb->obj = NULL;
+		rfb->base.obj[0] = NULL;
 		return ret;
 	}
 	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_display.h+1−1

@@ -23,7 +23,7 @@ · 22 unmodified lines
23	#ifndef __AMDGPU_DISPLAY_H__	23	#ifndef __AMDGPU_DISPLAY_H__
24	#define __AMDGPU_DISPLAY_H__	24	#define __AMDGPU_DISPLAY_H__
25		25
26	uint32_t amdgpu_display_framebuffer_domains(struct amdgpu_device *adev);	26	uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev);
27	struct drm_framebuffer *	27	struct drm_framebuffer *
28	amdgpu_display_user_framebuffer_create(struct drm_device *dev,	28	amdgpu_display_user_framebuffer_create(struct drm_device *dev,
29	struct drm_file *file_priv,	29	struct drm_file *file_priv,

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c+20−0

@@ -115,6 +115,26 @@ void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, · 114 unmodified lines
115	pr_cont("\n");	115	pr_cont("\n");
116	}	116	}
117		117
		118	void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev)
		119	{
		120	struct drm_device *ddev = adev->ddev;
		121	struct drm_crtc *crtc;
		122	struct amdgpu_crtc *amdgpu_crtc;
		123
		124	adev->pm.dpm.new_active_crtcs = 0;
		125	adev->pm.dpm.new_active_crtc_count = 0;
		126	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
		127	list_for_each_entry(crtc,
		128	&ddev->mode_config.crtc_list, head) {
		129	amdgpu_crtc = to_amdgpu_crtc(crtc);
		130	if (amdgpu_crtc->enabled) {
		131	adev->pm.dpm.new_active_crtcs \|= (1 << amdgpu_crtc->crtc_id);
		132	adev->pm.dpm.new_active_crtc_count++;
		133	}
		134	}
		135	}
		136	}
		137
118		138
119	u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)	139	u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)
120	{	140	{

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h+3−8

 	AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
 };
-#define SCLK_DEEP_SLEEP_MASK 0x8
 struct amdgpu_ps {
 	u32 caps; /* vbios flags */
 	u32 class; /* vbios flags */
 		((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
 			(adev)->powerplay.pp_handle, msg_id))
-#define amdgpu_dpm_notify_smu_memory_info(adev, virtual_addr_low, \
-			virtual_addr_hi, mc_addr_low, mc_addr_hi, size) \
-		((adev)->powerplay.pp_funcs->notify_smu_memory_info)( \
-			(adev)->powerplay.pp_handle, virtual_addr_low, \
-			virtual_addr_hi, mc_addr_low, mc_addr_hi, size)
 #define amdgpu_dpm_get_power_profile_mode(adev, buf) \
 		((adev)->powerplay.pp_funcs->get_power_profile_mode(\
 			(adev)->powerplay.pp_handle, buf))
 	uint32_t                pcie_gen_mask;
 	uint32_t                pcie_mlw_mask;
 	struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
+	uint32_t                smu_prv_buffer_size;
+	struct amdgpu_bo        *smu_prv_buffer;
 };
 #define R600_SSTU_DFLT                               0
 				struct amdgpu_ps *rps);
 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
+void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev);
 bool amdgpu_is_uvd_state(u32 class, u32 class2);
 void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
 			      u32 *p, u32 *u);

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+12−2

  * - 3.23.0 - Add query for VRAM lost counter
  * - 3.24.0 - Add high priority compute support for gfx9
  * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
+ * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
  */
 #define KMS_DRIVER_MAJOR	3
-#define KMS_DRIVER_MINOR	25
+#define KMS_DRIVER_MINOR	26
 #define KMS_DRIVER_PATCHLEVEL	0
 int amdgpu_vram_limit = 0;
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-uint amdgpu_pp_feature_mask = 0xffffbfff;
+uint amdgpu_pp_feature_mask = 0xffff3fff; /* gfxoff (bit 15) disabled by default */
 int amdgpu_ngg = 0;
 int amdgpu_prim_buf_per_se = 0;
 int amdgpu_pos_buf_per_se = 0;
 int amdgpu_compute_multipipe = -1;
 int amdgpu_gpu_recovery = -1; /* auto */
 int amdgpu_emu_mode = 0;
+uint amdgpu_smu_memory_pool_size = 0;
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
 #endif
+MODULE_PARM_DESC(smu_memory_pool_size,
+	"reserve gtt for smu debug usage, 0 = disable,"
+		"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
+module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
 static const struct pci_device_id pciidlist[] = {
 #ifdef  CONFIG_DRM_AMDGPU_SI
 	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 	{0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 	{0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 	{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
+	/* VEGAM */
+	{0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
+	{0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
 	/* Vega 10 */
 	{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 	{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},

drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c+6−6

@@ -137,7 +137,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, · 136 unmodified lines
137	/* need to align pitch with crtc limits */	137	/* need to align pitch with crtc limits */
138	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,	138	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
139	fb_tiled);	139	fb_tiled);
140	domain = amdgpu_display_framebuffer_domains(adev);	140	domain = amdgpu_display_supported_domains(adev);
141		141
142	height = ALIGN(mode_cmd->height, 8);	142	height = ALIGN(mode_cmd->height, 8);
143	size = mode_cmd->pitches[0] * height;	143	size = mode_cmd->pitches[0] * height;
@@ -292,9 +292,9 @@ static int amdgpu_fbdev_destroy(struct drm_device dev, struct amdgpu_fbdev rfb · 148 unmodified lines
292		292
293	drm_fb_helper_unregister_fbi(&rfbdev->helper);	293	drm_fb_helper_unregister_fbi(&rfbdev->helper);
294		294
295	if (rfb->obj) {	295	if (rfb->base.obj[0]) {
296	amdgpufb_destroy_pinned_object(rfb->obj);	296	amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
297	rfb->obj = NULL;	297	rfb->base.obj[0] = NULL;
298	drm_framebuffer_unregister_private(&rfb->base);	298	drm_framebuffer_unregister_private(&rfb->base);
299	drm_framebuffer_cleanup(&rfb->base);	299	drm_framebuffer_cleanup(&rfb->base);
300	}	300	}
@@ -377,7 +377,7 @@ int amdgpu_fbdev_total_size(struct amdgpu_device *adev) · 76 unmodified lines
377	if (!adev->mode_info.rfbdev)	377	if (!adev->mode_info.rfbdev)
378	return 0;	378	return 0;
379		379
380	robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);	380	robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]);
381	size += amdgpu_bo_size(robj);	381	size += amdgpu_bo_size(robj);
382	return size;	382	return size;
383	}	383	}
@@ -386,7 +386,7 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device adev, struct amdgpu_bo robj) · 2 unmodified lines
386	{	386	{
387	if (!adev->mode_info.rfbdev)	387	if (!adev->mode_info.rfbdev)
388	return false;	388	return false;
389	if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))	389	if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]))
390	return true;	390	return true;
391	return false;	391	return false;
392	}	392	}

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c+3−2

  * Emits a fence command on the requested ring (all asics).
  * Returns 0 on success, -ENOMEM on failure.
  */
-int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f)
+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
+		      unsigned flags)
 {
 	struct amdgpu_device *adev = ring->adev;
 	struct amdgpu_fence *fence;
 		       adev->fence_context + ring->idx,
 		       seq);
 	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
-			       seq, AMDGPU_FENCE_FLAG_INT);
+			       seq, flags | AMDGPU_FENCE_FLAG_INT);
 	ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 	/* This function can't be called concurrently anyway, otherwise

drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c+11−6

@@ -113,12 +113,17 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) · 112 unmodified lines
113	int r;	113	int r;
114		114
115	if (adev->gart.robj == NULL) {	115	if (adev->gart.robj == NULL) {
116	r = amdgpu_bo_create(adev, adev->gart.table_size, PAGE_SIZE,	116	struct amdgpu_bo_param bp;
117	AMDGPU_GEM_DOMAIN_VRAM,	117
118	AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|	118	memset(&bp, 0, sizeof(bp));
119	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,	119	bp.size = adev->gart.table_size;
120	ttm_bo_type_kernel, NULL,	120	bp.byte_align = PAGE_SIZE;
121	&adev->gart.robj);	121	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
		122	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|
		123	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
		124	bp.type = ttm_bo_type_kernel;
		125	bp.resv = NULL;
		126	r = amdgpu_bo_create(adev, &bp, &adev->gart.robj);
122	if (r) {	127	if (r) {
123	return r;	128	return r;
124	}	129	}

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+37−13

 			     struct drm_gem_object **obj)
 {
 	struct amdgpu_bo *bo;
+	struct amdgpu_bo_param bp;
 	int r;
+	memset(&bp, 0, sizeof(bp));
 	*obj = NULL;
 	/* At least align on page size */
 	if (alignment < PAGE_SIZE) {
 		alignment = PAGE_SIZE;
 	}
+	bp.size = size;
+	bp.byte_align = alignment;
+	bp.type = type;
+	bp.resv = resv;
+	bp.preferred_domain = initial_domain;
 retry:
-	r = amdgpu_bo_create(adev, size, alignment, initial_domain,
+	bp.flags = flags;
-			     flags, type, resv, &bo);
+	bp.domain = initial_domain;
+	r = amdgpu_bo_create(adev, &bp, &bo);
 	if (r) {
 		if (r != -ERESTARTSYS) {
 			if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
 		return -EINVAL;
 	/* reject invalid gem domains */
-	if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
+	if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
-				 AMDGPU_GEM_DOMAIN_GTT |
-				 AMDGPU_GEM_DOMAIN_VRAM |
-				 AMDGPU_GEM_DOMAIN_GDS |
-				 AMDGPU_GEM_DOMAIN_GWS |
-				 AMDGPU_GEM_DOMAIN_OA))
 		return -EINVAL;
 	/* create a gem object to contain this object in */
 }
 #if defined(CONFIG_DEBUG_FS)
+#define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag)	\
+	if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) {	\
+		seq_printf((m), " " #flag);		\
+	}
 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
 {
 	struct drm_gem_object *gobj = ptr;
 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
 	struct seq_file *m = data;
+	struct dma_buf_attachment *attachment;
+	struct dma_buf *dma_buf;
 	unsigned domain;
 	const char *placement;
 	unsigned pin_count;
-	uint64_t offset;
 	domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 	switch (domain) {
 	seq_printf(m, "\t0x%08x: %12ld byte %s",
 		   id, amdgpu_bo_size(bo), placement);
-	offset = READ_ONCE(bo->tbo.mem.start);
-	if (offset != AMDGPU_BO_INVALID_OFFSET)
-		seq_printf(m, " @ 0x%010Lx", offset);
 	pin_count = READ_ONCE(bo->pin_count);
 	if (pin_count)
 		seq_printf(m, " pin count %d", pin_count);
+	dma_buf = READ_ONCE(bo->gem_base.dma_buf);
+	attachment = READ_ONCE(bo->gem_base.import_attach);
+	if (attachment)
+		seq_printf(m, " imported from %p", dma_buf);
+	else if (dma_buf)
+		seq_printf(m, " exported as %p", dma_buf);
+	amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
+	amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS);
+	amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC);
+	amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED);
+	amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW);
+	amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
+	amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID);
+	amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC);
 	seq_printf(m, "\n");
 	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c+6−2

 	struct amdgpu_vm *vm;
 	uint64_t fence_ctx;
 	uint32_t status = 0, alloc_size;
+	unsigned fence_flags = 0;
 	unsigned i;
 	int r = 0;
 #endif
 		amdgpu_asic_invalidate_hdp(adev, ring);
-	r = amdgpu_fence_emit(ring, f);
+	if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
+		fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
+	r = amdgpu_fence_emit(ring, f, fence_flags);
 	if (r) {
 		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
 		if (job && job->vmid)
 	/* wrap the last IB with fence */
 	if (job && job->uf_addr) {
 		amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
-				       AMDGPU_FENCE_FLAG_64BIT);
+				       fence_flags | AMDGPU_FENCE_FLAG_64BIT);
 	}
 	if (patch_offset != ~0 && ring->funcs->patch_cond_exec)

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+50−8

@@ -31,6 +31,7 @@ · 30 unmodified lines
31	#include "amdgpu_sched.h"	31	#include "amdgpu_sched.h"
32	#include "amdgpu_uvd.h"	32	#include "amdgpu_uvd.h"
33	#include "amdgpu_vce.h"	33	#include "amdgpu_vce.h"
		34	#include "atom.h"
34		35
35	#include <linux/vga_switcheroo.h>	36	#include <linux/vga_switcheroo.h>
36	#include <linux/slab.h>	37	#include <linux/slab.h>
@@ -214,6 +215,18 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, · 177 unmodified lines
214	fw_info->ver = adev->gfx.rlc_fw_version;	215	fw_info->ver = adev->gfx.rlc_fw_version;
215	fw_info->feature = adev->gfx.rlc_feature_version;	216	fw_info->feature = adev->gfx.rlc_feature_version;
216	break;	217	break;
		218	case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
		219	fw_info->ver = adev->gfx.rlc_srlc_fw_version;
		220	fw_info->feature = adev->gfx.rlc_srlc_feature_version;
		221	break;
		222	case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
		223	fw_info->ver = adev->gfx.rlc_srlg_fw_version;
		224	fw_info->feature = adev->gfx.rlc_srlg_feature_version;
		225	break;
		226	case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
		227	fw_info->ver = adev->gfx.rlc_srls_fw_version;
		228	fw_info->feature = adev->gfx.rlc_srls_feature_version;
		229	break;
217	case AMDGPU_INFO_FW_GFX_MEC:	230	case AMDGPU_INFO_FW_GFX_MEC:
218	if (query_fw->index == 0) {	231	if (query_fw->index == 0) {
219	fw_info->ver = adev->gfx.mec_fw_version;	232	fw_info->ver = adev->gfx.mec_fw_version;
@@ -279,6 +292,9 @@ static int amdgpu_info_ioctl(struct drm_device dev, void data, struct drm_file · 59 unmodified lines
279	if (!info->return_size \|\| !info->return_pointer)	292	if (!info->return_size \|\| !info->return_pointer)
280	return -EINVAL;	293	return -EINVAL;
281		294
		295	/* Ensure IB tests are run on ring */
		296	flush_delayed_work(&adev->late_init_work);
		297
282	switch (info->query) {	298	switch (info->query) {
283	case AMDGPU_INFO_ACCEL_WORKING:	299	case AMDGPU_INFO_ACCEL_WORKING:
284	ui32 = adev->accel_working;	300	ui32 = adev->accel_working;
@@ -701,10 +717,7 @@ static int amdgpu_info_ioctl(struct drm_device dev, void data, struct drm_file · 416 unmodified lines
701	}	717	}
702	}	718	}
703	case AMDGPU_INFO_SENSOR: {	719	case AMDGPU_INFO_SENSOR: {
704	struct pp_gpu_power query = {0};	720	if (!adev->pm.dpm_enabled)
705	int query_size = sizeof(query);
706
707	if (amdgpu_dpm == 0)
708	return -ENOENT;	721	return -ENOENT;
709		722
710	switch (info->sensor_info.type) {	723	switch (info->sensor_info.type) {
@@ -746,10 +759,10 @@ static int amdgpu_info_ioctl(struct drm_device dev, void data, struct drm_file · 35 unmodified lines
746	/* get average GPU power */	759	/* get average GPU power */
747	if (amdgpu_dpm_read_sensor(adev,	760	if (amdgpu_dpm_read_sensor(adev,
748	AMDGPU_PP_SENSOR_GPU_POWER,	761	AMDGPU_PP_SENSOR_GPU_POWER,
749	(void *)&query, &query_size)) {	762	(void *)&ui32, &ui32_size)) {
750	return -EINVAL;	763	return -EINVAL;
751	}	764	}
752	ui32 = query.average_gpu_power >> 8;	765	ui32 >>= 8;
753	break;	766	break;
754	case AMDGPU_INFO_SENSOR_VDDNB:	767	case AMDGPU_INFO_SENSOR_VDDNB:
755	/* get VDDNB in millivolts */	768	/* get VDDNB in millivolts */
@@ -913,8 +926,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, · 157 unmodified lines
913	return;	926	return;
914		927
915	pm_runtime_get_sync(dev->dev);	928	pm_runtime_get_sync(dev->dev);
916		929	amdgpu_ctx_mgr_entity_fini(&fpriv->ctx_mgr);
917	amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
918		930
919	if (adev->asic_type != CHIP_RAVEN) {	931	if (adev->asic_type != CHIP_RAVEN) {
920	amdgpu_uvd_free_handles(adev, file_priv);	932	amdgpu_uvd_free_handles(adev, file_priv);
@@ -935,6 +947,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, · 14 unmodified lines
935	pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);	947	pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
936		948
937	amdgpu_vm_fini(adev, &fpriv->vm);	949	amdgpu_vm_fini(adev, &fpriv->vm);
		950	amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
		951
938	if (pasid)	952	if (pasid)
939	amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);	953	amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
940	amdgpu_bo_unref(&pd);	954	amdgpu_bo_unref(&pd);
@@ -1088,6 +1102,7 @@ static int amdgpu_debugfs_firmware_info(struct seq_file m, void data) · 147 unmodified lines
1088	struct amdgpu_device *adev = dev->dev_private;	1102	struct amdgpu_device *adev = dev->dev_private;
1089	struct drm_amdgpu_info_firmware fw_info;	1103	struct drm_amdgpu_info_firmware fw_info;
1090	struct drm_amdgpu_query_fw query_fw;	1104	struct drm_amdgpu_query_fw query_fw;
		1105	struct atom_context *ctx = adev->mode_info.atom_context;
1091	int ret, i;	1106	int ret, i;
1092		1107
1093	/* VCE */	1108	/* VCE */
@@ -1146,6 +1161,30 @@ static int amdgpu_debugfs_firmware_info(struct seq_file m, void data) · 52 unmodified lines
1146	seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",	1161	seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1147	fw_info.feature, fw_info.ver);	1162	fw_info.feature, fw_info.ver);
1148		1163
		1164	/* RLC SAVE RESTORE LIST CNTL */
		1165	query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
		1166	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
		1167	if (ret)
		1168	return ret;
		1169	seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
		1170	fw_info.feature, fw_info.ver);
		1171
		1172	/* RLC SAVE RESTORE LIST GPM MEM */
		1173	query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
		1174	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
		1175	if (ret)
		1176	return ret;
		1177	seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
		1178	fw_info.feature, fw_info.ver);
		1179
		1180	/* RLC SAVE RESTORE LIST SRM MEM */
		1181	query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
		1182	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
		1183	if (ret)
		1184	return ret;
		1185	seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
		1186	fw_info.feature, fw_info.ver);
		1187
1149	/* MEC */	1188	/* MEC */
1150	query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;	1189	query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1151	query_fw.index = 0;	1190	query_fw.index = 0;
@@ -1210,6 +1249,9 @@ static int amdgpu_debugfs_firmware_info(struct seq_file m, void data) · 58 unmodified lines
1210	seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",	1249	seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1211	fw_info.feature, fw_info.ver);	1250	fw_info.feature, fw_info.ver);
1212		1251
		1252
		1253	seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
		1254
1213	return 0;	1255	return 0;
1214	}	1256	}
1215		1257

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h+0−1

@@ -308,7 +308,6 @@ struct amdgpu_display_funcs { · 307 unmodified lines
308		308
309	struct amdgpu_framebuffer {	309	struct amdgpu_framebuffer {
310	struct drm_framebuffer base;	310	struct drm_framebuffer base;
311	struct drm_gem_object *obj;
312		311
313	/* caching for later use */	312	/* caching for later use */
314	uint64_t address;	313	uint64_t address;

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+72−48

 			      u32 domain, struct amdgpu_bo **bo_ptr,
 			      u64 *gpu_addr, void **cpu_addr)
 {
+	struct amdgpu_bo_param bp;
 	bool free = false;
 	int r;
+	memset(&bp, 0, sizeof(bp));
+	bp.size = size;
+	bp.byte_align = align;
+	bp.domain = domain;
+	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+		AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+	bp.type = ttm_bo_type_kernel;
+	bp.resv = NULL;
 	if (!*bo_ptr) {
-		r = amdgpu_bo_create(adev, size, align, domain,
+		r = amdgpu_bo_create(adev, &bp, bo_ptr);
-				     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-				     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
-				     ttm_bo_type_kernel, NULL, bo_ptr);
 		if (r) {
 			dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 				r);
 	return false;
 }
-static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size,
+static int amdgpu_bo_do_create(struct amdgpu_device *adev,
-			       int byte_align, u32 domain,
+			       struct amdgpu_bo_param *bp,
-			       u64 flags, enum ttm_bo_type type,
-			       struct reservation_object *resv,
 			       struct amdgpu_bo **bo_ptr)
 {
 	struct ttm_operation_ctx ctx = {
-		.interruptible = (type != ttm_bo_type_kernel),
+		.interruptible = (bp->type != ttm_bo_type_kernel),
 		.no_wait_gpu = false,
-		.resv = resv,
+		.resv = bp->resv,
 		.flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
 	};
 	struct amdgpu_bo *bo;
-	unsigned long page_align;
+	unsigned long page_align, size = bp->size;
 	size_t acc_size;
 	int r;
-	page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
+	page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 	size = ALIGN(size, PAGE_SIZE);
-	if (!amdgpu_bo_validate_size(adev, size, domain))
+	if (!amdgpu_bo_validate_size(adev, size, bp->domain))
 		return -ENOMEM;
 	*bo_ptr = NULL;
 	drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
 	INIT_LIST_HEAD(&bo->shadow_list);
 	INIT_LIST_HEAD(&bo->va);
-	bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
+	bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
-					 AMDGPU_GEM_DOMAIN_GTT |
+		bp->domain;
-					 AMDGPU_GEM_DOMAIN_CPU |
-					 AMDGPU_GEM_DOMAIN_GDS |
-					 AMDGPU_GEM_DOMAIN_GWS |
-					 AMDGPU_GEM_DOMAIN_OA);
 	bo->allowed_domains = bo->preferred_domains;
-	if (type != ttm_bo_type_kernel &&
+	if (bp->type != ttm_bo_type_kernel &&
 	    bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 		bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
-	bo->flags = flags;
+	bo->flags = bp->flags;
 #ifdef CONFIG_X86_32
 	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 #endif
 	bo->tbo.bdev = &adev->mman.bdev;
-	amdgpu_ttm_placement_from_domain(bo, domain);
+	amdgpu_ttm_placement_from_domain(bo, bp->domain);
+	if (bp->type == ttm_bo_type_kernel)
+		bo->tbo.priority = 1;
-	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
+	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
 				 &bo->placement, page_align, &ctx, acc_size,
-				 NULL, resv, &amdgpu_ttm_bo_destroy);
+				 NULL, bp->resv, &amdgpu_ttm_bo_destroy);
 	if (unlikely(r != 0))
 		return r;
 	else
 		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
-	if (type == ttm_bo_type_kernel)
+	if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
-		bo->tbo.priority = 1;
-	if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 	    bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 		struct dma_fence *fence;
 		bo->tbo.moving = dma_fence_get(fence);
 		dma_fence_put(fence);
 	}
-	if (!resv)
+	if (!bp->resv)
 		amdgpu_bo_unreserve(bo);
 	*bo_ptr = bo;
 	trace_amdgpu_bo_create(bo);
 	/* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
-	if (type == ttm_bo_type_device)
+	if (bp->type == ttm_bo_type_device)
 		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 	return 0;
 fail_unreserve:
-	if (!resv)
+	if (!bp->resv)
 		ww_mutex_unlock(&bo->tbo.resv->lock);
 	amdgpu_bo_unref(&bo);
 	return r;
 				   unsigned long size, int byte_align,
 				   struct amdgpu_bo *bo)
 {
+	struct amdgpu_bo_param bp;
 	int r;
 	if (bo->shadow)
 		return 0;
-	r = amdgpu_bo_do_create(adev, size, byte_align, AMDGPU_GEM_DOMAIN_GTT,
+	memset(&bp, 0, sizeof(bp));
-				AMDGPU_GEM_CREATE_CPU_GTT_USWC |
+	bp.size = size;
-				AMDGPU_GEM_CREATE_SHADOW,
+	bp.byte_align = byte_align;
-				ttm_bo_type_kernel,
+	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
-				bo->tbo.resv, &bo->shadow);
+	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC |
+		AMDGPU_GEM_CREATE_SHADOW;
+	bp.type = ttm_bo_type_kernel;
+	bp.resv = bo->tbo.resv;
+	r = amdgpu_bo_do_create(adev, &bp, &bo->shadow);
 	if (!r) {
 		bo->shadow->parent = amdgpu_bo_ref(bo);
 		mutex_lock(&adev->shadow_list_lock);
 	return r;
 }
-int amdgpu_bo_create(struct amdgpu_device *adev, unsigned long size,
+int amdgpu_bo_create(struct amdgpu_device *adev,
-		     int byte_align, u32 domain,
+		     struct amdgpu_bo_param *bp,
-		     u64 flags, enum ttm_bo_type type,
-		     struct reservation_object *resv,
 		     struct amdgpu_bo **bo_ptr)
 {
-	uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
+	u64 flags = bp->flags;
 	int r;
-	r = amdgpu_bo_do_create(adev, size, byte_align, domain,
+	bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
-				parent_flags, type, resv, bo_ptr);
+	r = amdgpu_bo_do_create(adev, bp, bo_ptr);
 	if (r)
 		return r;
 	if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
-		if (!resv)
+		if (!bp->resv)
 			WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 							NULL));
-		r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
+		r = amdgpu_bo_create_shadow(adev, bp->size, bp->byte_align, (*bo_ptr));
-		if (!resv)
+		if (!bp->resv)
 			reservation_object_unlock((*bo_ptr)->tbo.resv);
 		if (r)
 		return -EINVAL;
 	/* A shared bo cannot be migrated to VRAM */
-	if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
+	if (bo->prime_shared_count) {
-		return -EINVAL;
+		if (domain & AMDGPU_GEM_DOMAIN_GTT)
+			domain = AMDGPU_GEM_DOMAIN_GTT;
+		else
+			return -EINVAL;
+	}
+	/* This assumes only APU display buffers are pinned with (VRAM|GTT).
+	 * See function amdgpu_display_supported_domains()
+	 */
+	if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
+		domain = AMDGPU_GEM_DOMAIN_VRAM;
+		if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
+			domain = AMDGPU_GEM_DOMAIN_GTT;
+	}
 	if (bo->pin_count) {
 		uint32_t mem_type = bo->tbo.mem.mem_type;
 	return amdgpu_ttm_init(adev);
 }
+int amdgpu_bo_late_init(struct amdgpu_device *adev)
+{
+	amdgpu_ttm_late_init(adev);
+	return 0;
+}
 void amdgpu_bo_fini(struct amdgpu_device *adev)
 {
 	amdgpu_ttm_fini(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h+34−4

@@ -33,6 +33,16 @@ · 32 unmodified lines
33		33
34	#define AMDGPU_BO_INVALID_OFFSET LONG_MAX	34	#define AMDGPU_BO_INVALID_OFFSET LONG_MAX
35		35
		36	struct amdgpu_bo_param {
		37	unsigned long size;
		38	int byte_align;
		39	u32 domain;
		40	u32 preferred_domain;
		41	u64 flags;
		42	enum ttm_bo_type type;
		43	struct reservation_object *resv;
		44	};
		45
36	/* bo virtual addresses in a vm */	46	/* bo virtual addresses in a vm */
37	struct amdgpu_bo_va_mapping {	47	struct amdgpu_bo_va_mapping {
38	struct amdgpu_bo_va *bo_va;	48	struct amdgpu_bo_va *bo_va;
@@ -195,6 +205,27 @@ static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo) · 156 unmodified lines
195	}	205	}
196	}	206	}
197		207
		208	/**
		209	* amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM
		210	*/
		211	static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
		212	{
		213	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
		214	unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
		215	struct drm_mm_node *node = bo->tbo.mem.mm_node;
		216	unsigned long pages_left;
		217
		218	if (bo->tbo.mem.mem_type != TTM_PL_VRAM)
		219	return false;
		220
		221	for (pages_left = bo->tbo.mem.num_pages; pages_left;
		222	pages_left -= node->size, node++)
		223	if (node->start < fpfn)
		224	return true;
		225
		226	return false;
		227	}
		228
198	/**	229	/**
199	* amdgpu_bo_explicit_sync - return whether the bo is explicitly synced	230	* amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
200	*/	231	*/
@@ -203,10 +234,8 @@ static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo) · 2 unmodified lines
203	return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;	234	return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
204	}	235	}
205		236
206	int amdgpu_bo_create(struct amdgpu_device *adev, unsigned long size,	237	int amdgpu_bo_create(struct amdgpu_device *adev,
207	int byte_align, u32 domain,	238	struct amdgpu_bo_param *bp,
208	u64 flags, enum ttm_bo_type type,
209	struct reservation_object *resv,
210	struct amdgpu_bo **bo_ptr);	239	struct amdgpu_bo **bo_ptr);
211	int amdgpu_bo_create_reserved(struct amdgpu_device *adev,	240	int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
212	unsigned long size, int align,	241	unsigned long size, int align,
@@ -230,6 +259,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, · 17 unmodified lines
230	int amdgpu_bo_unpin(struct amdgpu_bo *bo);	259	int amdgpu_bo_unpin(struct amdgpu_bo *bo);
231	int amdgpu_bo_evict_vram(struct amdgpu_device *adev);	260	int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
232	int amdgpu_bo_init(struct amdgpu_device *adev);	261	int amdgpu_bo_init(struct amdgpu_device *adev);
		262	int amdgpu_bo_late_init(struct amdgpu_device *adev);
233	void amdgpu_bo_fini(struct amdgpu_device *adev);	263	void amdgpu_bo_fini(struct amdgpu_device *adev);
234	int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,	264	int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
235	struct vm_area_struct *vma);	265	struct vm_area_struct *vma);

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c+282−83

@@ -77,6 +77,37 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) · 76 unmodified lines
77	}	77	}
78	}	78	}
79		79
		80	/**
		81	* DOC: power_dpm_state
		82	*
		83	* This is a legacy interface and is only provided for backwards compatibility.
		84	* The amdgpu driver provides a sysfs API for adjusting certain power
		85	* related parameters. The file power_dpm_state is used for this.
		86	* It accepts the following arguments:
		87	* - battery
		88	* - balanced
		89	* - performance
		90	*
		91	* battery
		92	*
		93	* On older GPUs, the vbios provided a special power state for battery
		94	* operation. Selecting battery switched to this state. This is no
		95	* longer provided on newer GPUs so the option does nothing in that case.
		96	*
		97	* balanced
		98	*
		99	* On older GPUs, the vbios provided a special power state for balanced
		100	* operation. Selecting balanced switched to this state. This is no
		101	* longer provided on newer GPUs so the option does nothing in that case.
		102	*
		103	* performance
		104	*
		105	* On older GPUs, the vbios provided a special power state for performance
		106	* operation. Selecting performance switched to this state. This is no
		107	* longer provided on newer GPUs so the option does nothing in that case.
		108	*
		109	*/
		110
80	static ssize_t amdgpu_get_dpm_state(struct device *dev,	111	static ssize_t amdgpu_get_dpm_state(struct device *dev,
81	struct device_attribute *attr,	112	struct device_attribute *attr,
82	char *buf)	113	char *buf)
@@ -131,6 +162,59 @@ fail: · 48 unmodified lines
131	return count;	162	return count;
132	}	163	}
133		164
		165
		166	/**
		167	* DOC: power_dpm_force_performance_level
		168	*
		169	* The amdgpu driver provides a sysfs API for adjusting certain power
		170	* related parameters. The file power_dpm_force_performance_level is
		171	* used for this. It accepts the following arguments:
		172	* - auto
		173	* - low
		174	* - high
		175	* - manual
		176	* - GPU fan
		177	* - profile_standard
		178	* - profile_min_sclk
		179	* - profile_min_mclk
		180	* - profile_peak
		181	*
		182	* auto
		183	*
		184	* When auto is selected, the driver will attempt to dynamically select
		185	* the optimal power profile for current conditions in the driver.
		186	*
		187	* low
		188	*
		189	* When low is selected, the clocks are forced to the lowest power state.
		190	*
		191	* high
		192	*
		193	* When high is selected, the clocks are forced to the highest power state.
		194	*
		195	* manual
		196	*
		197	* When manual is selected, the user can manually adjust which power states
		198	* are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
		199	* and pp_dpm_pcie files and adjust the power state transition heuristics
		200	* via the pp_power_profile_mode sysfs file.
		201	*
		202	* profile_standard
		203	* profile_min_sclk
		204	* profile_min_mclk
		205	* profile_peak
		206	*
		207	* When the profiling modes are selected, clock and power gating are
		208	* disabled and the clocks are set for different profiling cases. This
		209	* mode is recommended for profiling specific work loads where you do
		210	* not want clock or power gating for clock fluctuation to interfere
		211	* with your results. profile_standard sets the clocks to a fixed clock
		212	* level which varies from asic to asic. profile_min_sclk forces the sclk
		213	* to the lowest level. profile_min_mclk forces the mclk to the lowest level.
		214	* profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
		215	*
		216	*/
		217
134	static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,	218	static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
135	struct device_attribute *attr,	219	struct device_attribute *attr,
136	char *buf)	220	char *buf)
@@ -324,6 +408,17 @@ fail: · 187 unmodified lines
324	return count;	408	return count;
325	}	409	}
326		410
		411	/**
		412	* DOC: pp_table
		413	*
		414	* The amdgpu driver provides a sysfs API for uploading new powerplay
		415	* tables. The file pp_table is used for this. Reading the file
		416	* will dump the current power play table. Writing to the file
		417	* will attempt to upload a new powerplay table and re-initialize
		418	* powerplay using that new table.
		419	*
		420	*/
		421
327	static ssize_t amdgpu_get_pp_table(struct device *dev,	422	static ssize_t amdgpu_get_pp_table(struct device *dev,
328	struct device_attribute *attr,	423	struct device_attribute *attr,
329	char *buf)	424	char *buf)
@@ -360,6 +455,29 @@ static ssize_t amdgpu_set_pp_table(struct device *dev, · 30 unmodified lines
360	return count;	455	return count;
361	}	456	}
362		457
		458	/**
		459	* DOC: pp_od_clk_voltage
		460	*
		461	* The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
		462	* in each power level within a power state. The pp_od_clk_voltage is used for
		463	* this.
		464	*
		465	* Reading the file will display:
		466	* - a list of engine clock levels and voltages labeled OD_SCLK
		467	* - a list of memory clock levels and voltages labeled OD_MCLK
		468	* - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
		469	*
		470	* To manually adjust these settings, first select manual using
		471	* power_dpm_force_performance_level. Enter a new value for each
		472	* level by writing a string that contains "s/m level clock voltage" to
		473	* the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
		474	* at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
		475	* 810 mV. When you have edited all of the states as needed, write
		476	* "c" (commit) to the file to commit your changes. If you want to reset to the
		477	* default power levels, write "r" (reset) to the file to reset them.
		478	*
		479	*/
		480
363	static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,	481	static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
364	struct device_attribute *attr,	482	struct device_attribute *attr,
365	const char *buf,	483	const char *buf,
@@ -437,6 +555,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, · 71 unmodified lines
437	if (adev->powerplay.pp_funcs->print_clock_levels) {	555	if (adev->powerplay.pp_funcs->print_clock_levels) {
438	size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);	556	size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
439	size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);	557	size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
		558	size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
440	return size;	559	return size;
441	} else {	560	} else {
442	return snprintf(buf, PAGE_SIZE, "\n");	561	return snprintf(buf, PAGE_SIZE, "\n");
@@ -444,6 +563,23 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, · 1 unmodified line
444		563
445	}	564	}
446		565
		566	/**
		567	* DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
		568	*
		569	* The amdgpu driver provides a sysfs API for adjusting what power levels
		570	* are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
		571	* and pp_dpm_pcie are used for this.
		572	*
		573	* Reading back the files will show you the available power levels within
		574	* the power state and the clock information for those levels.
		575	*
		576	* To manually adjust these states, first select manual using
		577	* power_dpm_force_performance_level.
		578	* Secondly,Enter a new value for each level by inputing a string that
		579	* contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
		580	* E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
		581	*/
		582
447	static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,	583	static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
448	struct device_attribute *attr,	584	struct device_attribute *attr,
449	char *buf)	585	char *buf)
@@ -466,23 +602,27 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, · 16 unmodified lines
466	struct amdgpu_device *adev = ddev->dev_private;	602	struct amdgpu_device *adev = ddev->dev_private;
467	int ret;	603	int ret;
468	long level;	604	long level;
469	uint32_t i, mask = 0;	605	uint32_t mask = 0;
470	char sub_str[2];	606	char *sub_str = NULL;
		607	char *tmp;
		608	char buf_cpy[count];
		609	const char delimiter[3] = {' ', '\n', '\0'};
471		610
472	for (i = 0; i < strlen(buf); i++) {	611	memcpy(buf_cpy, buf, count+1);
473	if (*(buf + i) == '\n')	612	tmp = buf_cpy;
474	continue;	613	while (tmp[0]) {
475	sub_str[0] = *(buf + i);	614	sub_str = strsep(&tmp, delimiter);
476	sub_str[1] = '\0';	615	if (strlen(sub_str)) {
477	ret = kstrtol(sub_str, 0, &level);	616	ret = kstrtol(sub_str, 0, &level);
478		617
479	if (ret) {	618	if (ret) {
480	count = -EINVAL;	619	count = -EINVAL;
481	goto fail;	620	goto fail;
482	}	621	}
483	mask \|= 1 << level;	622	mask \|= 1 << level;
		623	} else
		624	break;
484	}	625	}
485
486	if (adev->powerplay.pp_funcs->force_clock_level)	626	if (adev->powerplay.pp_funcs->force_clock_level)
487	amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);	627	amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
488		628
@@ -512,21 +652,26 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, · 23 unmodified lines
512	struct amdgpu_device *adev = ddev->dev_private;	652	struct amdgpu_device *adev = ddev->dev_private;
513	int ret;	653	int ret;
514	long level;	654	long level;
515	uint32_t i, mask = 0;	655	uint32_t mask = 0;
516	char sub_str[2];	656	char *sub_str = NULL;
		657	char *tmp;
		658	char buf_cpy[count];
		659	const char delimiter[3] = {' ', '\n', '\0'};
517		660
518	for (i = 0; i < strlen(buf); i++) {	661	memcpy(buf_cpy, buf, count+1);
519	if (*(buf + i) == '\n')	662	tmp = buf_cpy;
520	continue;	663	while (tmp[0]) {
521	sub_str[0] = *(buf + i);	664	sub_str = strsep(&tmp, delimiter);
522	sub_str[1] = '\0';	665	if (strlen(sub_str)) {
523	ret = kstrtol(sub_str, 0, &level);	666	ret = kstrtol(sub_str, 0, &level);
524		667
525	if (ret) {	668	if (ret) {
526	count = -EINVAL;	669	count = -EINVAL;
527	goto fail;	670	goto fail;
528	}	671	}
529	mask \|= 1 << level;	672	mask \|= 1 << level;
		673	} else
		674	break;
530	}	675	}
531	if (adev->powerplay.pp_funcs->force_clock_level)	676	if (adev->powerplay.pp_funcs->force_clock_level)
532	amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);	677	amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
@@ -557,21 +702,27 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, · 24 unmodified lines
557	struct amdgpu_device *adev = ddev->dev_private;	702	struct amdgpu_device *adev = ddev->dev_private;
558	int ret;	703	int ret;
559	long level;	704	long level;
560	uint32_t i, mask = 0;	705	uint32_t mask = 0;
561	char sub_str[2];	706	char *sub_str = NULL;
		707	char *tmp;
		708	char buf_cpy[count];
		709	const char delimiter[3] = {' ', '\n', '\0'};
562		710
563	for (i = 0; i < strlen(buf); i++) {	711	memcpy(buf_cpy, buf, count+1);
564	if (*(buf + i) == '\n')	712	tmp = buf_cpy;
565	continue;
566	sub_str[0] = *(buf + i);
567	sub_str[1] = '\0';
568	ret = kstrtol(sub_str, 0, &level);
569		713
570	if (ret) {	714	while (tmp[0]) {
571	count = -EINVAL;	715	sub_str = strsep(&tmp, delimiter);
572	goto fail;	716	if (strlen(sub_str)) {
573	}	717	ret = kstrtol(sub_str, 0, &level);
574	mask \|= 1 << level;	718
		719	if (ret) {
		720	count = -EINVAL;
		721	goto fail;
		722	}
		723	mask \|= 1 << level;
		724	} else
		725	break;
575	}	726	}
576	if (adev->powerplay.pp_funcs->force_clock_level)	727	if (adev->powerplay.pp_funcs->force_clock_level)
577	amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);	728	amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
@@ -668,6 +819,26 @@ fail: · 90 unmodified lines
668	return count;	819	return count;
669	}	820	}
670		821
		822	/**
		823	* DOC: pp_power_profile_mode
		824	*
		825	* The amdgpu driver provides a sysfs API for adjusting the heuristics
		826	* related to switching between power levels in a power state. The file
		827	* pp_power_profile_mode is used for this.
		828	*
		829	* Reading this file outputs a list of all of the predefined power profiles
		830	* and the relevant heuristics settings for that profile.
		831	*
		832	* To select a profile or create a custom profile, first select manual using
		833	* power_dpm_force_performance_level. Writing the number of a predefined
		834	* profile to pp_power_profile_mode will enable those heuristics. To
		835	* create a custom set of heuristics, write a string of numbers to the file
		836	* starting with the number of the custom profile along with a setting
		837	* for each heuristic parameter. Due to differences across asic families
		838	* the heuristic parameters vary from family to family.
		839	*
		840	*/
		841
671	static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,	842	static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
672	struct device_attribute *attr,	843	struct device_attribute *attr,
673	char *buf)	844	char *buf)
@@ -1020,8 +1191,8 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, · 346 unmodified lines
1020	{	1191	{
1021	struct amdgpu_device *adev = dev_get_drvdata(dev);	1192	struct amdgpu_device *adev = dev_get_drvdata(dev);
1022	struct drm_device *ddev = adev->ddev;	1193	struct drm_device *ddev = adev->ddev;
1023	struct pp_gpu_power query = {0};	1194	u32 query = 0;
1024	int r, size = sizeof(query);	1195	int r, size = sizeof(u32);
1025	unsigned uw;	1196	unsigned uw;
1026		1197
1027	/* Can't get power when the card is off */	1198	/* Can't get power when the card is off */
@@ -1041,7 +1212,7 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, · 13 unmodified lines
1041	return r;	1212	return r;
1042		1213
1043	/* convert to microwatts */	1214	/* convert to microwatts */
1044	uw = (query.average_gpu_power >> 8) * 1000000;	1215	uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1045		1216
1046	return snprintf(buf, PAGE_SIZE, "%u\n", uw);	1217	return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1047	}	1218	}
@@ -1109,6 +1280,46 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, · 61 unmodified lines
1109	return count;	1280	return count;
1110	}	1281	}
1111		1282
		1283
		1284	/**
		1285	* DOC: hwmon
		1286	*
		1287	* The amdgpu driver exposes the following sensor interfaces:
		1288	* - GPU temperature (via the on-die sensor)
		1289	* - GPU voltage
		1290	* - Northbridge voltage (APUs only)
		1291	* - GPU power
		1292	* - GPU fan
		1293	*
		1294	* hwmon interfaces for GPU temperature:
		1295	* - temp1_input: the on die GPU temperature in millidegrees Celsius
		1296	* - temp1_crit: temperature critical max value in millidegrees Celsius
		1297	* - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
		1298	*
		1299	* hwmon interfaces for GPU voltage:
		1300	* - in0_input: the voltage on the GPU in millivolts
		1301	* - in1_input: the voltage on the Northbridge in millivolts
		1302	*
		1303	* hwmon interfaces for GPU power:
		1304	* - power1_average: average power used by the GPU in microWatts
		1305	* - power1_cap_min: minimum cap supported in microWatts
		1306	* - power1_cap_max: maximum cap supported in microWatts
		1307	* - power1_cap: selected power cap in microWatts
		1308	*
		1309	* hwmon interfaces for GPU fan:
		1310	* - pwm1: pulse width modulation fan level (0-255)
		1311	* - pwm1_enable: pulse width modulation fan control method
		1312	* 0: no fan speed control
		1313	* 1: manual fan speed control using pwm interface
		1314	* 2: automatic fan speed control
		1315	* - pwm1_min: pulse width modulation fan control minimum level (0)
		1316	* - pwm1_max: pulse width modulation fan control maximum level (255)
		1317	* - fan1_input: fan speed in RPM
		1318	*
		1319	* You can use hwmon tools like sensors to view this information on your system.
		1320	*
		1321	*/
		1322
1112	static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);	1323	static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1113	static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);	1324	static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1114	static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);	1325	static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
@@ -1153,19 +1364,14 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, · 38 unmodified lines
1153	struct amdgpu_device *adev = dev_get_drvdata(dev);	1364	struct amdgpu_device *adev = dev_get_drvdata(dev);
1154	umode_t effective_mode = attr->mode;	1365	umode_t effective_mode = attr->mode;
1155		1366
1156	/* handle non-powerplay limitations */	1367
1157	if (!adev->powerplay.pp_handle) {	1368	/* Skip fan attributes if fan is not present */
1158	/* Skip fan attributes if fan is not present */	1369	if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr \|\|
1159	if (adev->pm.no_fan &&	1370	attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr \|\|
1160	(attr == &sensor_dev_attr_pwm1.dev_attr.attr \|\|	1371	attr == &sensor_dev_attr_pwm1_max.dev_attr.attr \|\|
1161	attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr \|\|	1372	attr == &sensor_dev_attr_pwm1_min.dev_attr.attr \|\|
1162	attr == &sensor_dev_attr_pwm1_max.dev_attr.attr \|\|	1373	attr == &sensor_dev_attr_fan1_input.dev_attr.attr))
1163	attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))	1374	return 0;
1164	return 0;
1165	/* requires powerplay */
1166	if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
1167	return 0;
1168	}
1169		1375
1170	/* Skip limit attributes if DPM is not enabled */	1376	/* Skip limit attributes if DPM is not enabled */
1171	if (!adev->pm.dpm_enabled &&	1377	if (!adev->pm.dpm_enabled &&
@@ -1658,9 +1864,6 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) · 486 unmodified lines
1658		1864
1659	void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)	1865	void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1660	{	1866	{
1661	struct drm_device *ddev = adev->ddev;
1662	struct drm_crtc *crtc;
1663	struct amdgpu_crtc *amdgpu_crtc;
1664	int i = 0;	1867	int i = 0;
1665		1868
1666	if (!adev->pm.dpm_enabled)	1869	if (!adev->pm.dpm_enabled)
@@ -1676,21 +1879,25 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) · 9 unmodified lines
1676	}	1879	}
1677		1880
1678	if (adev->powerplay.pp_funcs->dispatch_tasks) {	1881	if (adev->powerplay.pp_funcs->dispatch_tasks) {
		1882	if (!amdgpu_device_has_dc_support(adev)) {
		1883	mutex_lock(&adev->pm.mutex);
		1884	amdgpu_dpm_get_active_displays(adev);
		1885	adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
		1886	adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
		1887	adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
		1888	/* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
		1889	if (adev->pm.pm_display_cfg.vrefresh > 120)
		1890	adev->pm.pm_display_cfg.min_vblank_time = 0;
		1891	if (adev->powerplay.pp_funcs->display_configuration_change)
		1892	adev->powerplay.pp_funcs->display_configuration_change(
		1893	adev->powerplay.pp_handle,
		1894	&adev->pm.pm_display_cfg);
		1895	mutex_unlock(&adev->pm.mutex);
		1896	}
1679	amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);	1897	amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1680	} else {	1898	} else {
1681	mutex_lock(&adev->pm.mutex);	1899	mutex_lock(&adev->pm.mutex);
1682	adev->pm.dpm.new_active_crtcs = 0;	1900	amdgpu_dpm_get_active_displays(adev);
1683	adev->pm.dpm.new_active_crtc_count = 0;
1684	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1685	list_for_each_entry(crtc,
1686	&ddev->mode_config.crtc_list, head) {
1687	amdgpu_crtc = to_amdgpu_crtc(crtc);
1688	if (amdgpu_crtc->enabled) {
1689	adev->pm.dpm.new_active_crtcs \|= (1 << amdgpu_crtc->crtc_id);
1690	adev->pm.dpm.new_active_crtc_count++;
1691	}
1692	}
1693	}
1694	/* update battery/ac status */	1901	/* update battery/ac status */
1695	if (power_supply_is_system_supplied() > 0)	1902	if (power_supply_is_system_supplied() > 0)
1696	adev->pm.dpm.ac_power = true;	1903	adev->pm.dpm.ac_power = true;
@@ -1711,7 +1918,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) · 14 unmodified lines
1711	static int amdgpu_debugfs_pm_info_pp(struct seq_file m, struct amdgpu_device adev)	1918	static int amdgpu_debugfs_pm_info_pp(struct seq_file m, struct amdgpu_device adev)
1712	{	1919	{
1713	uint32_t value;	1920	uint32_t value;
1714	struct pp_gpu_power query = {0};	1921	uint32_t query = 0;
1715	int size;	1922	int size;
1716		1923
1717	/* sanity check PP is enabled */	1924	/* sanity check PP is enabled */
@@ -1734,17 +1941,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file m, struct amdgpu_device a · 16 unmodified lines
1734	seq_printf(m, "\t%u mV (VDDGFX)\n", value);	1941	seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1735	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))	1942	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1736	seq_printf(m, "\t%u mV (VDDNB)\n", value);	1943	seq_printf(m, "\t%u mV (VDDNB)\n", value);
1737	size = sizeof(query);	1944	size = sizeof(uint32_t);
1738	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) {	1945	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
1739	seq_printf(m, "\t%u.%u W (VDDC)\n", query.vddc_power >> 8,	1946	seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
1740	query.vddc_power & 0xff);
1741	seq_printf(m, "\t%u.%u W (VDDCI)\n", query.vddci_power >> 8,
1742	query.vddci_power & 0xff);
1743	seq_printf(m, "\t%u.%u W (max GPU)\n", query.max_gpu_power >> 8,
1744	query.max_gpu_power & 0xff);
1745	seq_printf(m, "\t%u.%u W (average GPU)\n", query.average_gpu_power >> 8,
1746	query.average_gpu_power & 0xff);
1747	}
1748	size = sizeof(value);	1947	size = sizeof(value);
1749	seq_printf(m, "\n");	1948	seq_printf(m, "\n");
1750		1949

drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c+10−4

 	struct reservation_object *resv = attach->dmabuf->resv;
 	struct amdgpu_device *adev = dev->dev_private;
 	struct amdgpu_bo *bo;
+	struct amdgpu_bo_param bp;
 	int ret;
+	memset(&bp, 0, sizeof(bp));
+	bp.size = attach->dmabuf->size;
+	bp.byte_align = PAGE_SIZE;
+	bp.domain = AMDGPU_GEM_DOMAIN_CPU;
+	bp.flags = 0;
+	bp.type = ttm_bo_type_sg;
+	bp.resv = resv;
 	ww_mutex_lock(&resv->lock, NULL);
-	ret = amdgpu_bo_create(adev, attach->dmabuf->size, PAGE_SIZE,
+	ret = amdgpu_bo_create(adev, &bp, &bo);
-			       AMDGPU_GEM_DOMAIN_CPU, 0, ttm_bo_type_sg,
-			       resv, &bo);
 	if (ret)
 		goto error;
 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 	struct ttm_operation_ctx ctx = { true, false };
-	u32 domain = amdgpu_display_framebuffer_domains(adev);
+	u32 domain = amdgpu_display_supported_domains(adev);
 	int ret;
 	bool reads = (direction == DMA_BIDIRECTIONAL ||
 		      direction == DMA_FROM_DEVICE);

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c+20−0

@@ -459,6 +459,26 @@ void amdgpu_ring_lru_touch(struct amdgpu_device adev, struct amdgpu_ring ring) · 458 unmodified lines
459	spin_unlock(&adev->ring_lru_list_lock);	459	spin_unlock(&adev->ring_lru_list_lock);
460	}	460	}
461		461
		462	/**
		463	* amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
		464	*
		465	* @adev: amdgpu_device pointer
		466	* @reg0: register to write
		467	* @reg1: register to wait on
		468	* @ref: reference value to write/wait on
		469	* @mask: mask to wait on
		470	*
		471	* Helper for rings that don't support write and wait in a
		472	* single oneshot packet.
		473	*/
		474	void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
		475	uint32_t reg0, uint32_t reg1,
		476	uint32_t ref, uint32_t mask)
		477	{
		478	amdgpu_ring_emit_wreg(ring, reg0, ref);
		479	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
		480	}
		481
462	/*	482	/*
463	* Debugfs info	483	* Debugfs info
464	*/	484	*/

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h+10−1

 #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
 #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
+#define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)
 enum amdgpu_ring_type {
 	AMDGPU_RING_TYPE_GFX,
 				   unsigned irq_type);
 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
-int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence);
+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence,
+		      unsigned flags);
 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
 void amdgpu_fence_process(struct amdgpu_ring *ring);
 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
 	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
 	void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
 			      uint32_t val, uint32_t mask);
+	void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
+					uint32_t reg0, uint32_t reg1,
+					uint32_t ref, uint32_t mask);
 	void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
 	/* priority functions */
 	void (*set_priority) (struct amdgpu_ring *ring,
 			int *blacklist, int num_blacklist,
 			bool lru_pipe_order, struct amdgpu_ring **ring);
 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring);
+void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
+						uint32_t reg0, uint32_t val0,
+						uint32_t reg1, uint32_t val1);
 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
 {
 	int i = 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_test.c+12−6

@@ -33,6 +33,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) · 32 unmodified lines
33	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;	33	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
34	struct amdgpu_bo *vram_obj = NULL;	34	struct amdgpu_bo *vram_obj = NULL;
35	struct amdgpu_bo **gtt_obj = NULL;	35	struct amdgpu_bo **gtt_obj = NULL;
		36	struct amdgpu_bo_param bp;
36	uint64_t gart_addr, vram_addr;	37	uint64_t gart_addr, vram_addr;
37	unsigned n, size;	38	unsigned n, size;
38	int i, r;	39	int i, r;
@@ -58,9 +59,15 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) · 19 unmodified lines
58	r = 1;	59	r = 1;
59	goto out_cleanup;	60	goto out_cleanup;
60	}	61	}
61		62	memset(&bp, 0, sizeof(bp));
62	r = amdgpu_bo_create(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 0,	63	bp.size = size;
63	ttm_bo_type_kernel, NULL, &vram_obj);	64	bp.byte_align = PAGE_SIZE;
		65	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
		66	bp.flags = 0;
		67	bp.type = ttm_bo_type_kernel;
		68	bp.resv = NULL;
		69
		70	r = amdgpu_bo_create(adev, &bp, &vram_obj);
64	if (r) {	71	if (r) {
65	DRM_ERROR("Failed to create VRAM object\n");	72	DRM_ERROR("Failed to create VRAM object\n");
66	goto out_cleanup;	73	goto out_cleanup;
@@ -79,9 +86,8 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) · 12 unmodified lines
79	void vram_start, vram_end;	86	void vram_start, vram_end;
80	struct dma_fence *fence = NULL;	87	struct dma_fence *fence = NULL;
81		88
82	r = amdgpu_bo_create(adev, size, PAGE_SIZE,	89	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
83	AMDGPU_GEM_DOMAIN_GTT, 0,	90	r = amdgpu_bo_create(adev, &bp, gtt_obj + i);
84	ttm_bo_type_kernel, NULL, gtt_obj + i);
85	if (r) {	91	if (r) {
86	DRM_ERROR("Failed to create GTT object %d\n", i);	92	DRM_ERROR("Failed to create GTT object %d\n", i);
87	goto out_lclean;	93	goto out_lclean;

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h+1−1

@@ -275,7 +275,7 @@ TRACE_EVENT(amdgpu_vm_bo_unmap, · 274 unmodified lines
275	),	275	),
276		276
277	TP_fast_assign(	277	TP_fast_assign(
278	__entry->bo = bo_va->base.bo;	278	__entry->bo = bo_va ? bo_va->base.bo : NULL;
279	__entry->start = mapping->start;	279	__entry->start = mapping->start;
280	__entry->last = mapping->last;	280	__entry->last = mapping->last;
281	__entry->offset = mapping->offset;	281	__entry->offset = mapping->offset;

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+71−39

@@ -111,7 +111,7 @@ static int amdgpu_ttm_global_init(struct amdgpu_device *adev) · 110 unmodified lines
111	ring = adev->mman.buffer_funcs_ring;	111	ring = adev->mman.buffer_funcs_ring;
112	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];	112	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
113	r = drm_sched_entity_init(&ring->sched, &adev->mman.entity,	113	r = drm_sched_entity_init(&ring->sched, &adev->mman.entity,
114	rq, amdgpu_sched_jobs, NULL);	114	rq, NULL);
115	if (r) {	115	if (r) {
116	DRM_ERROR("Failed setting up TTM BO move run queue.\n");	116	DRM_ERROR("Failed setting up TTM BO move run queue.\n");
117	goto error_entity;	117	goto error_entity;
@@ -223,20 +223,8 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, · 105 unmodified lines
223	if (!adev->mman.buffer_funcs_enabled) {	223	if (!adev->mman.buffer_funcs_enabled) {
224	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);	224	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
225	} else if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&	225	} else if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
226	!(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {	226	!(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
227	unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;	227	amdgpu_bo_in_cpu_visible_vram(abo)) {
228	struct drm_mm_node *node = bo->mem.mm_node;
229	unsigned long pages_left;
230
231	for (pages_left = bo->mem.num_pages;
232	pages_left;
233	pages_left -= node->size, node++) {
234	if (node->start < fpfn)
235	break;
236	}
237
238	if (!pages_left)
239	goto gtt;
240		228
241	/* Try evicting to the CPU inaccessible part of VRAM	229	/* Try evicting to the CPU inaccessible part of VRAM
242	* first, but only set GTT as busy placement, so this	230	* first, but only set GTT as busy placement, so this
@@ -245,12 +233,11 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, · 2 unmodified lines
245	*/	233	*/
246	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM \|	234	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM \|
247	AMDGPU_GEM_DOMAIN_GTT);	235	AMDGPU_GEM_DOMAIN_GTT);
248	abo->placements[0].fpfn = fpfn;	236	abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
249	abo->placements[0].lpfn = 0;	237	abo->placements[0].lpfn = 0;
250	abo->placement.busy_placement = &abo->placements[1];	238	abo->placement.busy_placement = &abo->placements[1];
251	abo->placement.num_busy_placement = 1;	239	abo->placement.num_busy_placement = 1;
252	} else {	240	} else {
253	gtt:
254	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);	241	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
255	}	242	}
256	break;	243	break;
@@ -856,6 +843,45 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) · 599 unmodified lines
856	sg_free_table(ttm->sg);	843	sg_free_table(ttm->sg);
857	}	844	}
858		845
		846	int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
		847	struct ttm_buffer_object *tbo,
		848	uint64_t flags)
		849	{
		850	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
		851	struct ttm_tt *ttm = tbo->ttm;
		852	struct amdgpu_ttm_tt gtt = (void )ttm;
		853	int r;
		854
		855	if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
		856	uint64_t page_idx = 1;
		857
		858	r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
		859	ttm->pages, gtt->ttm.dma_address, flags);
		860	if (r)
		861	goto gart_bind_fail;
		862
		863	/* Patch mtype of the second part BO */
		864	flags &= ~AMDGPU_PTE_MTYPE_MASK;
		865	flags \|= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);
		866
		867	r = amdgpu_gart_bind(adev,
		868	gtt->offset + (page_idx << PAGE_SHIFT),
		869	ttm->num_pages - page_idx,
		870	&ttm->pages[page_idx],
		871	&(gtt->ttm.dma_address[page_idx]), flags);
		872	} else {
		873	r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
		874	ttm->pages, gtt->ttm.dma_address, flags);
		875	}
		876
		877	gart_bind_fail:
		878	if (r)
		879	DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
		880	ttm->num_pages, gtt->offset);
		881
		882	return r;
		883	}
		884
859	static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,	885	static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
860	struct ttm_mem_reg *bo_mem)	886	struct ttm_mem_reg *bo_mem)
861	{	887	{
@@ -929,8 +955,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) · 67 unmodified lines
929		955
930	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);	956	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
931	gtt->offset = (u64)tmp.start << PAGE_SHIFT;	957	gtt->offset = (u64)tmp.start << PAGE_SHIFT;
932	r = amdgpu_gart_bind(adev, gtt->offset, bo->ttm->num_pages,	958	r = amdgpu_ttm_gart_bind(adev, bo, flags);
933	bo->ttm->pages, gtt->ttm.dma_address, flags);
934	if (unlikely(r)) {	959	if (unlikely(r)) {
935	ttm_bo_mem_put(bo, &tmp);	960	ttm_bo_mem_put(bo, &tmp);
936	return r;	961	return r;
@@ -947,19 +972,15 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) · 10 unmodified lines
947	int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)	972	int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
948	{	973	{
949	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);	974	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
950	struct amdgpu_ttm_tt gtt = (void )tbo->ttm;
951	uint64_t flags;	975	uint64_t flags;
952	int r;	976	int r;
953		977
954	if (!gtt)	978	if (!tbo->ttm)
955	return 0;	979	return 0;
956		980
957	flags = amdgpu_ttm_tt_pte_flags(adev, &gtt->ttm.ttm, &tbo->mem);	981	flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
958	r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,	982	r = amdgpu_ttm_gart_bind(adev, tbo, flags);
959	gtt->ttm.ttm.pages, gtt->ttm.dma_address, flags);	983
960	if (r)
961	DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
962	gtt->ttm.ttm.num_pages, gtt->offset);
963	return r;	984	return r;
964	}	985	}
965		986
@@ -1349,6 +1370,7 @@ static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) · 383 unmodified lines
1349	static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)	1370	static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1350	{	1371	{
1351	struct ttm_operation_ctx ctx = { false, false };	1372	struct ttm_operation_ctx ctx = { false, false };
		1373	struct amdgpu_bo_param bp;
1352	int r = 0;	1374	int r = 0;
1353	int i;	1375	int i;
1354	u64 vram_size = adev->gmc.visible_vram_size;	1376	u64 vram_size = adev->gmc.visible_vram_size;
@@ -1356,17 +1378,21 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) · 1 unmodified line
1356	u64 size = adev->fw_vram_usage.size;	1378	u64 size = adev->fw_vram_usage.size;
1357	struct amdgpu_bo *bo;	1379	struct amdgpu_bo *bo;
1358		1380
		1381	memset(&bp, 0, sizeof(bp));
		1382	bp.size = adev->fw_vram_usage.size;
		1383	bp.byte_align = PAGE_SIZE;
		1384	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
		1385	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|
		1386	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
		1387	bp.type = ttm_bo_type_kernel;
		1388	bp.resv = NULL;
1359	adev->fw_vram_usage.va = NULL;	1389	adev->fw_vram_usage.va = NULL;
1360	adev->fw_vram_usage.reserved_bo = NULL;	1390	adev->fw_vram_usage.reserved_bo = NULL;
1361		1391
1362	if (adev->fw_vram_usage.size > 0 &&	1392	if (adev->fw_vram_usage.size > 0 &&
1363	adev->fw_vram_usage.size <= vram_size) {	1393	adev->fw_vram_usage.size <= vram_size) {
1364		1394
1365	r = amdgpu_bo_create(adev, adev->fw_vram_usage.size, PAGE_SIZE,	1395	r = amdgpu_bo_create(adev, &bp,
1366	AMDGPU_GEM_DOMAIN_VRAM,
1367	AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|
1368	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1369	ttm_bo_type_kernel, NULL,
1370	&adev->fw_vram_usage.reserved_bo);	1396	&adev->fw_vram_usage.reserved_bo);
1371	if (r)	1397	if (r)
1372	goto error_create;	1398	goto error_create;
@@ -1474,12 +1500,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) · 101 unmodified lines
1474	return r;	1500	return r;
1475	}	1501	}
1476		1502
1477	r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,	1503	if (adev->gmc.stolen_size) {
1478	AMDGPU_GEM_DOMAIN_VRAM,	1504	r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1479	&adev->stolen_vga_memory,	1505	AMDGPU_GEM_DOMAIN_VRAM,
1480	NULL, NULL);	1506	&adev->stolen_vga_memory,
1481	if (r)	1507	NULL, NULL);
1482	return r;	1508	if (r)
		1509	return r;
		1510	}
1483	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",	1511	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1484	(unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));	1512	(unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1485		1513
@@ -1548,13 +1576,17 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) · 62 unmodified lines
1548	return 0;	1576	return 0;
1549	}	1577	}
1550		1578
		1579	void amdgpu_ttm_late_init(struct amdgpu_device *adev)
		1580	{
		1581	amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
		1582	}
		1583
1551	void amdgpu_ttm_fini(struct amdgpu_device *adev)	1584	void amdgpu_ttm_fini(struct amdgpu_device *adev)
1552	{	1585	{
1553	if (!adev->mman.initialized)	1586	if (!adev->mman.initialized)
1554	return;	1587	return;
1555		1588
1556	amdgpu_ttm_debugfs_fini(adev);	1589	amdgpu_ttm_debugfs_fini(adev);
1557	amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1558	amdgpu_ttm_fw_reserve_vram_fini(adev);	1590	amdgpu_ttm_fw_reserve_vram_fini(adev);
1559	if (adev->mman.aper_base_kaddr)	1591	if (adev->mman.aper_base_kaddr)
1560	iounmap(adev->mman.aper_base_kaddr);	1592	iounmap(adev->mman.aper_base_kaddr);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h+1−0

@@ -77,6 +77,7 @@ uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man); · 76 unmodified lines
77	uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);	77	uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
78		78
79	int amdgpu_ttm_init(struct amdgpu_device *adev);	79	int amdgpu_ttm_init(struct amdgpu_device *adev);
		80	void amdgpu_ttm_late_init(struct amdgpu_device *adev);
80	void amdgpu_ttm_fini(struct amdgpu_device *adev);	81	void amdgpu_ttm_fini(struct amdgpu_device *adev);
81	void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,	82	void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
82	bool enable);	83	bool enable);

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c+49−3

@@ -161,8 +161,38 @@ void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) · 160 unmodified lines
161	le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));	161	le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
162	DRM_DEBUG("reg_list_separate_size_bytes: %u\n",	162	DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
163	le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));	163	le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
164	DRM_DEBUG("reg_list_separate_size_bytes: %u\n",	164	DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
165	le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));	165	le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
		166	if (version_minor == 1) {
		167	const struct rlc_firmware_header_v2_1 *v2_1 =
		168	container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
		169	DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
		170	le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
		171	DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
		172	le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
		173	DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
		174	le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
		175	DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
		176	le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
		177	DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
		178	le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
		179	DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
		180	le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
		181	DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
		182	le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
		183	DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
		184	le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
		185	DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
		186	le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
		187	DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
		188	le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
		189	DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
		190	le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
		191	DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
		192	le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
		193	DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
		194	le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
		195	}
166	} else {	196	} else {
167	DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);	197	DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
168	}	198	}
@@ -265,6 +295,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) · 96 unmodified lines
265	case CHIP_POLARIS10:	295	case CHIP_POLARIS10:
266	case CHIP_POLARIS11:	296	case CHIP_POLARIS11:
267	case CHIP_POLARIS12:	297	case CHIP_POLARIS12:
		298	case CHIP_VEGAM:
268	if (!load_type)	299	if (!load_type)
269	return AMDGPU_FW_LOAD_DIRECT;	300	return AMDGPU_FW_LOAD_DIRECT;
270	else	301	else
@@ -307,7 +338,10 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, · 36 unmodified lines
307	(ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&	338	(ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
308	ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&	339	ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
309	ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&	340	ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
310	ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT)) {	341	ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
		342	ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
		343	ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
		344	ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
311	ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);	345	ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
312		346
313	memcpy(ucode->kaddr, (void )((uint8_t )ucode->fw->data +	347	memcpy(ucode->kaddr, (void )((uint8_t )ucode->fw->data +
@@ -329,6 +363,18 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, · 15 unmodified lines
329	le32_to_cpu(header->ucode_array_offset_bytes) +	363	le32_to_cpu(header->ucode_array_offset_bytes) +
330	le32_to_cpu(cp_hdr->jt_offset) * 4),	364	le32_to_cpu(cp_hdr->jt_offset) * 4),
331	ucode->ucode_size);	365	ucode->ucode_size);
		366	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
		367	ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
		368	memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
		369	ucode->ucode_size);
		370	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {
		371	ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
		372	memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
		373	ucode->ucode_size);
		374	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
		375	ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
		376	memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
		377	ucode->ucode_size);
332	}	378	}
333		379
334	return 0;	380	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h+22−0

@@ -98,6 +98,24 @@ struct rlc_firmware_header_v2_0 { · 97 unmodified lines
98	uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */	98	uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
99	};	99	};
100		100
		101	/* version_major=2, version_minor=1 */
		102	struct rlc_firmware_header_v2_1 {
		103	struct rlc_firmware_header_v2_0 v2_0;
		104	uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
		105	uint32_t save_restore_list_cntl_ucode_ver;
		106	uint32_t save_restore_list_cntl_feature_ver;
		107	uint32_t save_restore_list_cntl_size_bytes;
		108	uint32_t save_restore_list_cntl_offset_bytes;
		109	uint32_t save_restore_list_gpm_ucode_ver;
		110	uint32_t save_restore_list_gpm_feature_ver;
		111	uint32_t save_restore_list_gpm_size_bytes;
		112	uint32_t save_restore_list_gpm_offset_bytes;
		113	uint32_t save_restore_list_srm_ucode_ver;
		114	uint32_t save_restore_list_srm_feature_ver;
		115	uint32_t save_restore_list_srm_size_bytes;
		116	uint32_t save_restore_list_srm_offset_bytes;
		117	};
		118
101	/* version_major=1, version_minor=0 */	119	/* version_major=1, version_minor=0 */
102	struct sdma_firmware_header_v1_0 {	120	struct sdma_firmware_header_v1_0 {
103	struct common_firmware_header header;	121	struct common_firmware_header header;
@@ -148,6 +166,7 @@ union amdgpu_firmware_header { · 44 unmodified lines
148	struct gfx_firmware_header_v1_0 gfx;	166	struct gfx_firmware_header_v1_0 gfx;
149	struct rlc_firmware_header_v1_0 rlc;	167	struct rlc_firmware_header_v1_0 rlc;
150	struct rlc_firmware_header_v2_0 rlc_v2_0;	168	struct rlc_firmware_header_v2_0 rlc_v2_0;
		169	struct rlc_firmware_header_v2_1 rlc_v2_1;
151	struct sdma_firmware_header_v1_0 sdma;	170	struct sdma_firmware_header_v1_0 sdma;
152	struct sdma_firmware_header_v1_1 sdma_v1_1;	171	struct sdma_firmware_header_v1_1 sdma_v1_1;
153	struct gpu_info_firmware_header_v1_0 gpu_info;	172	struct gpu_info_firmware_header_v1_0 gpu_info;
@@ -168,6 +187,9 @@ enum AMDGPU_UCODE_ID { · 14 unmodified lines
168	AMDGPU_UCODE_ID_CP_MEC2,	187	AMDGPU_UCODE_ID_CP_MEC2,
169	AMDGPU_UCODE_ID_CP_MEC2_JT,	188	AMDGPU_UCODE_ID_CP_MEC2_JT,
170	AMDGPU_UCODE_ID_RLC_G,	189	AMDGPU_UCODE_ID_RLC_G,
		190	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
		191	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
		192	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
171	AMDGPU_UCODE_ID_STORAGE,	193	AMDGPU_UCODE_ID_STORAGE,
172	AMDGPU_UCODE_ID_SMC,	194	AMDGPU_UCODE_ID_SMC,
173	AMDGPU_UCODE_ID_UVD,	195	AMDGPU_UCODE_ID_UVD,

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c+6−1

 #define FIRMWARE_POLARIS10	"amdgpu/polaris10_uvd.bin"
 #define FIRMWARE_POLARIS11	"amdgpu/polaris11_uvd.bin"
 #define FIRMWARE_POLARIS12	"amdgpu/polaris12_uvd.bin"
+#define FIRMWARE_VEGAM		"amdgpu/vegam_uvd.bin"
 #define FIRMWARE_VEGA10		"amdgpu/vega10_uvd.bin"
 #define FIRMWARE_VEGA12		"amdgpu/vega12_uvd.bin"
 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
+MODULE_FIRMWARE(FIRMWARE_VEGAM);
 MODULE_FIRMWARE(FIRMWARE_VEGA10);
 MODULE_FIRMWARE(FIRMWARE_VEGA12);
 	case CHIP_VEGA12:
 		fw_name = FIRMWARE_VEGA12;
 		break;
+	case CHIP_VEGAM:
+		fw_name = FIRMWARE_VEGAM;
+		break;
 	default:
 		return -EINVAL;
 	}
 	ring = &adev->uvd.ring;
 	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 	r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity,
-				  rq, amdgpu_sched_jobs, NULL);
+				  rq, NULL);
 	if (r != 0) {
 		DRM_ERROR("Failed setting up UVD run queue.\n");
 		return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c+32−3

 #define FIRMWARE_FIJI		"amdgpu/fiji_vce.bin"
 #define FIRMWARE_STONEY		"amdgpu/stoney_vce.bin"
 #define FIRMWARE_POLARIS10	"amdgpu/polaris10_vce.bin"
-#define FIRMWARE_POLARIS11         "amdgpu/polaris11_vce.bin"
+#define FIRMWARE_POLARIS11	"amdgpu/polaris11_vce.bin"
-#define FIRMWARE_POLARIS12         "amdgpu/polaris12_vce.bin"
+#define FIRMWARE_POLARIS12	"amdgpu/polaris12_vce.bin"
+#define FIRMWARE_VEGAM		"amdgpu/vegam_vce.bin"
 #define FIRMWARE_VEGA10		"amdgpu/vega10_vce.bin"
 #define FIRMWARE_VEGA12		"amdgpu/vega12_vce.bin"
 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
+MODULE_FIRMWARE(FIRMWARE_VEGAM);
 MODULE_FIRMWARE(FIRMWARE_VEGA10);
 MODULE_FIRMWARE(FIRMWARE_VEGA12);
 	case CHIP_POLARIS12:
 		fw_name = FIRMWARE_POLARIS12;
 		break;
+	case CHIP_VEGAM:
+		fw_name = FIRMWARE_VEGAM;
+		break;
 	case CHIP_VEGA10:
 		fw_name = FIRMWARE_VEGA10;
 		break;
 	ring = &adev->vce.ring[0];
 	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 	r = drm_sched_entity_init(&ring->sched, &adev->vce.entity,
-				  rq, amdgpu_sched_jobs, NULL);
+				  rq, NULL);
 	if (r != 0) {
 		DRM_ERROR("Failed setting up VCE run queue.\n");
 		return r;
 			if (r)
 				goto out;
 			break;
+		case 0x0500000d: /* MV buffer */
+			r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
+							idx + 2, 0, 0);
+			if (r)
+				goto out;
+			r = amdgpu_vce_validate_bo(p, ib_idx, idx + 8,
+							idx + 7, 0, 0);
+			if (r)
+				goto out;
+			break;
 		}
 		idx += len / 4;
 				goto out;
 			break;
+		case 0x0500000d: /* MV buffer */
+			r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3,
+							idx + 2, *size, 0);
+			if (r)
+				goto out;
+			r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 8,
+							idx + 7, *size / 12, 0);
+			if (r)
+				goto out;
+			break;
 		default:
 			DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 			r = -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c+2−2

@@ -105,7 +105,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) · 104 unmodified lines
105	ring = &adev->vcn.ring_dec;	105	ring = &adev->vcn.ring_dec;
106	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];	106	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
107	r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_dec,	107	r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_dec,
108	rq, amdgpu_sched_jobs, NULL);	108	rq, NULL);
109	if (r != 0) {	109	if (r != 0) {
110	DRM_ERROR("Failed setting up VCN dec run queue.\n");	110	DRM_ERROR("Failed setting up VCN dec run queue.\n");
111	return r;	111	return r;
@@ -114,7 +114,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) · 2 unmodified lines
114	ring = &adev->vcn.ring_enc[0];	114	ring = &adev->vcn.ring_enc[0];
115	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];	115	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
116	r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_enc,	116	r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_enc,
117	rq, amdgpu_sched_jobs, NULL);	117	rq, NULL);
118	if (r != 0) {	118	if (r != 0) {
119	DRM_ERROR("Failed setting up VCN enc run queue.\n");	119	DRM_ERROR("Failed setting up VCN enc run queue.\n");
120	return r;	120	return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+71−43

@@ -94,6 +94,36 @@ struct amdgpu_prt_cb { · 93 unmodified lines
94	struct dma_fence_cb cb;	94	struct dma_fence_cb cb;
95	};	95	};
96		96
		97	static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
		98	struct amdgpu_vm *vm,
		99	struct amdgpu_bo *bo)
		100	{
		101	base->vm = vm;
		102	base->bo = bo;
		103	INIT_LIST_HEAD(&base->bo_list);
		104	INIT_LIST_HEAD(&base->vm_status);
		105
		106	if (!bo)
		107	return;
		108	list_add_tail(&base->bo_list, &bo->va);
		109
		110	if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
		111	return;
		112
		113	if (bo->preferred_domains &
		114	amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
		115	return;
		116
		117	/*
		118	* we checked all the prerequisites, but it looks like this per vm bo
		119	* is currently evicted. add the bo to the evicted list to make sure it
		120	* is validated on next vm use to avoid fault.
		121	* */
		122	spin_lock(&vm->status_lock);
		123	list_move_tail(&base->vm_status, &vm->evicted);
		124	spin_unlock(&vm->status_lock);
		125	}
		126
97	/**	127	/**
98	* amdgpu_vm_level_shift - return the addr shift for each level	128	* amdgpu_vm_level_shift - return the addr shift for each level
99	*	129	*
@@ -412,11 +442,16 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, · 312 unmodified lines
412	struct amdgpu_bo *pt;	442	struct amdgpu_bo *pt;
413		443
414	if (!entry->base.bo) {	444	if (!entry->base.bo) {
415	r = amdgpu_bo_create(adev,	445	struct amdgpu_bo_param bp;
416	amdgpu_vm_bo_size(adev, level),	446
417	AMDGPU_GPU_PAGE_SIZE,	447	memset(&bp, 0, sizeof(bp));
418	AMDGPU_GEM_DOMAIN_VRAM, flags,	448	bp.size = amdgpu_vm_bo_size(adev, level);
419	ttm_bo_type_kernel, resv, &pt);	449	bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
		450	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
		451	bp.flags = flags;
		452	bp.type = ttm_bo_type_kernel;
		453	bp.resv = resv;
		454	r = amdgpu_bo_create(adev, &bp, &pt);
420	if (r)	455	if (r)
421	return r;	456	return r;
422		457
@@ -441,11 +476,9 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, · 18 unmodified lines
441	*/	476	*/
442	pt->parent = amdgpu_bo_ref(parent->base.bo);	477	pt->parent = amdgpu_bo_ref(parent->base.bo);
443		478
444	entry->base.vm = vm;	479	amdgpu_vm_bo_base_init(&entry->base, vm, pt);
445	entry->base.bo = pt;
446	list_add_tail(&entry->base.bo_list, &pt->va);
447	spin_lock(&vm->status_lock);	480	spin_lock(&vm->status_lock);
448	list_add(&entry->base.vm_status, &vm->relocated);	481	list_move(&entry->base.vm_status, &vm->relocated);
449	spin_unlock(&vm->status_lock);	482	spin_unlock(&vm->status_lock);
450	}	483	}
451		484
@@ -628,7 +661,7 @@ int amdgpu_vm_flush(struct amdgpu_ring ring, struct amdgpu_job job, bool need_ · 176 unmodified lines
628	amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);	661	amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
629		662
630	if (vm_flush_needed \|\| pasid_mapping_needed) {	663	if (vm_flush_needed \|\| pasid_mapping_needed) {
631	r = amdgpu_fence_emit(ring, &fence);	664	r = amdgpu_fence_emit(ring, &fence, 0);
632	if (r)	665	if (r)
633	return r;	666	return r;
634	}	667	}
@@ -1557,6 +1590,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, · 922 unmodified lines
1557		1590
1558	spin_lock(&vm->status_lock);	1591	spin_lock(&vm->status_lock);
1559	list_del_init(&bo_va->base.vm_status);	1592	list_del_init(&bo_va->base.vm_status);
		1593
		1594	/* If the BO is not in its preferred location add it back to
		1595	* the evicted list so that it gets validated again on the
		1596	* next command submission.
		1597	*/
		1598	if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
		1599	!(bo->preferred_domains &
		1600	amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)))
		1601	list_add_tail(&bo_va->base.vm_status, &vm->evicted);
1560	spin_unlock(&vm->status_lock);	1602	spin_unlock(&vm->status_lock);
1561		1603
1562	list_splice_init(&bo_va->invalids, &bo_va->valids);	1604	list_splice_init(&bo_va->invalids, &bo_va->valids);
@@ -1827,36 +1869,12 @@ struct amdgpu_bo_va amdgpu_vm_bo_add(struct amdgpu_device adev, · 264 unmodified lines
1827	if (bo_va == NULL) {	1869	if (bo_va == NULL) {
1828	return NULL;	1870	return NULL;
1829	}	1871	}
1830	bo_va->base.vm = vm;	1872	amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1831	bo_va->base.bo = bo;
1832	INIT_LIST_HEAD(&bo_va->base.bo_list);
1833	INIT_LIST_HEAD(&bo_va->base.vm_status);
1834		1873
1835	bo_va->ref_count = 1;	1874	bo_va->ref_count = 1;
1836	INIT_LIST_HEAD(&bo_va->valids);	1875	INIT_LIST_HEAD(&bo_va->valids);
1837	INIT_LIST_HEAD(&bo_va->invalids);	1876	INIT_LIST_HEAD(&bo_va->invalids);
1838		1877
1839	if (!bo)
1840	return bo_va;
1841
1842	list_add_tail(&bo_va->base.bo_list, &bo->va);
1843
1844	if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
1845	return bo_va;
1846
1847	if (bo->preferred_domains &
1848	amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
1849	return bo_va;
1850
1851	/*
1852	* We checked all the prerequisites, but it looks like this per VM BO
1853	* is currently evicted. add the BO to the evicted list to make sure it
1854	* is validated on next VM use to avoid fault.
1855	* */
1856	spin_lock(&vm->status_lock);
1857	list_move_tail(&bo_va->base.vm_status, &vm->evicted);
1858	spin_unlock(&vm->status_lock);
1859
1860	return bo_va;	1878	return bo_va;
1861	}	1879	}
1862		1880
@@ -2234,6 +2252,10 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, · 371 unmodified lines
2234	{	2252	{
2235	struct amdgpu_vm_bo_base *bo_base;	2253	struct amdgpu_vm_bo_base *bo_base;
2236		2254
		2255	/* shadow bo doesn't have bo base, its validation needs its parent */
		2256	if (bo->parent && bo->parent->shadow == bo)
		2257	bo = bo->parent;
		2258
2237	list_for_each_entry(bo_base, &bo->va, bo_list) {	2259	list_for_each_entry(bo_base, &bo->va, bo_list) {
2238	struct amdgpu_vm *vm = bo_base->vm;	2260	struct amdgpu_vm *vm = bo_base->vm;
2239		2261
@@ -2355,6 +2377,8 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, · 115 unmodified lines
2355	int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm,	2377	int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm,
2356	int vm_context, unsigned int pasid)	2378	int vm_context, unsigned int pasid)
2357	{	2379	{
		2380	struct amdgpu_bo_param bp;
		2381	struct amdgpu_bo *root;
2358	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,	2382	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
2359	AMDGPU_VM_PTE_COUNT(adev) * 8);	2383	AMDGPU_VM_PTE_COUNT(adev) * 8);
2360	unsigned ring_instance;	2384	unsigned ring_instance;
@@ -2380,7 +2404,7 @@ int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm, · 19 unmodified lines
2380	ring = adev->vm_manager.vm_pte_rings[ring_instance];	2404	ring = adev->vm_manager.vm_pte_rings[ring_instance];
2381	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];	2405	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
2382	r = drm_sched_entity_init(&ring->sched, &vm->entity,	2406	r = drm_sched_entity_init(&ring->sched, &vm->entity,
2383	rq, amdgpu_sched_jobs, NULL);	2407	rq, NULL);
2384	if (r)	2408	if (r)
2385	return r;	2409	return r;
2386		2410
@@ -2409,24 +2433,28 @@ int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm, · 22 unmodified lines
2409	flags \|= AMDGPU_GEM_CREATE_SHADOW;	2433	flags \|= AMDGPU_GEM_CREATE_SHADOW;
2410		2434
2411	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);	2435	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
2412	r = amdgpu_bo_create(adev, size, align, AMDGPU_GEM_DOMAIN_VRAM, flags,	2436	memset(&bp, 0, sizeof(bp));
2413	ttm_bo_type_kernel, NULL, &vm->root.base.bo);	2437	bp.size = size;
		2438	bp.byte_align = align;
		2439	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
		2440	bp.flags = flags;
		2441	bp.type = ttm_bo_type_kernel;
		2442	bp.resv = NULL;
		2443	r = amdgpu_bo_create(adev, &bp, &root);
2414	if (r)	2444	if (r)
2415	goto error_free_sched_entity;	2445	goto error_free_sched_entity;
2416		2446
2417	r = amdgpu_bo_reserve(vm->root.base.bo, true);	2447	r = amdgpu_bo_reserve(root, true);
2418	if (r)	2448	if (r)
2419	goto error_free_root;	2449	goto error_free_root;
2420		2450
2421	r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,	2451	r = amdgpu_vm_clear_bo(adev, vm, root,
2422	adev->vm_manager.root_level,	2452	adev->vm_manager.root_level,
2423	vm->pte_support_ats);	2453	vm->pte_support_ats);
2424	if (r)	2454	if (r)
2425	goto error_unreserve;	2455	goto error_unreserve;
2426		2456
2427	vm->root.base.vm = vm;	2457	amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2428	list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va);
2429	list_add_tail(&vm->root.base.vm_status, &vm->evicted);
2430	amdgpu_bo_unreserve(vm->root.base.bo);	2458	amdgpu_bo_unreserve(vm->root.base.bo);
2431		2459
2432	if (pasid) {	2460	if (pasid) {

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h+3−2

@@ -75,11 +75,12 @@ struct amdgpu_bo_list_entry; · 74 unmodified lines
75	/* PDE Block Fragment Size for VEGA10 */	75	/* PDE Block Fragment Size for VEGA10 */
76	#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)	76	#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
77		77
78	/* VEGA10 only */	78
		79	/* For GFX9 */
79	#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)	80	#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
80	#define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)	81	#define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
81		82
82	/* For Raven */	83	#define AMDGPU_MTYPE_NC 0
83	#define AMDGPU_MTYPE_CC 2	84	#define AMDGPU_MTYPE_CC 2
84		85
85	#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \	86	#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \

drivers/gpu/drm/amd/amdgpu/ci_dpm.c+2−2

@@ -5903,7 +5903,7 @@ static int ci_dpm_init(struct amdgpu_device *adev) · 5902 unmodified lines
5903	pi->pcie_dpm_key_disabled = 0;	5903	pi->pcie_dpm_key_disabled = 0;
5904	pi->thermal_sclk_dpm_enabled = 0;	5904	pi->thermal_sclk_dpm_enabled = 0;
5905		5905
5906	if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)	5906	if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
5907	pi->caps_sclk_ds = true;	5907	pi->caps_sclk_ds = true;
5908	else	5908	else
5909	pi->caps_sclk_ds = false;	5909	pi->caps_sclk_ds = false;
@@ -6255,7 +6255,7 @@ static int ci_dpm_late_init(void *handle) · 345 unmodified lines
6255	int ret;	6255	int ret;
6256	struct amdgpu_device adev = (struct amdgpu_device )handle;	6256	struct amdgpu_device adev = (struct amdgpu_device )handle;
6257		6257
6258	if (!amdgpu_dpm)	6258	if (!adev->pm.dpm_enabled)
6259	return 0;	6259	return 0;
6260		6260
6261	/* init the sysfs and debugfs files late */	6261	/* init the sysfs and debugfs files late */

drivers/gpu/drm/amd/amdgpu/cik.c+7−0

 	}
 }
+static bool cik_need_full_reset(struct amdgpu_device *adev)
+{
+	/* change this when we support soft reset */
+	return true;
+}
 static const struct amdgpu_asic_funcs cik_asic_funcs =
 {
 	.read_disabled_bios = &cik_read_disabled_bios,
 	.get_config_memsize = &cik_get_config_memsize,
 	.flush_hdp = &cik_flush_hdp,
 	.invalidate_hdp = &cik_invalidate_hdp,
+	.need_full_reset = &cik_need_full_reset,
 };
 static int cik_common_early_init(void *handle)

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c+5−12

 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct amdgpu_device *adev = dev->dev_private;
-	struct amdgpu_framebuffer *amdgpu_fb;
 	struct drm_framebuffer *target_fb;
 	struct drm_gem_object *obj;
 	struct amdgpu_bo *abo;
 		return 0;
 	}
-	if (atomic) {
+	if (atomic)
-		amdgpu_fb = to_amdgpu_framebuffer(fb);
 		target_fb = fb;
-	} else {
+	else
-		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
 		target_fb = crtc->primary->fb;
-	}
 	/* If atomic, assume fb object is pinned & idle & fenced and
 	 * just update base pointers
 	 */
-	obj = amdgpu_fb->obj;
+	obj = target_fb->obj[0];
 	abo = gem_to_amdgpu_bo(obj);
 	r = amdgpu_bo_reserve(abo, false);
 	if (unlikely(r != 0))
 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
 	if (!atomic && fb && fb != crtc->primary->fb) {
-		amdgpu_fb = to_amdgpu_framebuffer(fb);
+		abo = gem_to_amdgpu_bo(fb->obj[0]);
-		abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r != 0))
 			return r;
 	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 	if (crtc->primary->fb) {
 		int r;
-		struct amdgpu_framebuffer *amdgpu_fb;
 		struct amdgpu_bo *abo;
-		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
+		abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
-		abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r))
 			DRM_ERROR("failed to reserve abo before unpin\n");

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c+15−15

 							ARRAY_SIZE(polaris11_golden_settings_a11));
 		break;
 	case CHIP_POLARIS10:
+	case CHIP_VEGAM:
 		amdgpu_device_program_register_sequence(adev,
 							polaris10_golden_settings_a11,
 							ARRAY_SIZE(polaris10_golden_settings_a11));
 		num_crtc = 2;
 		break;
 	case CHIP_POLARIS10:
+	case CHIP_VEGAM:
 		num_crtc = 6;
 		break;
 	case CHIP_POLARIS11:
 		adev->mode_info.audio.num_pins = 7;
 		break;
 	case CHIP_POLARIS10:
+	case CHIP_VEGAM:
 		adev->mode_info.audio.num_pins = 8;
 		break;
 	case CHIP_POLARIS11:
 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct amdgpu_device *adev = dev->dev_private;
-	struct amdgpu_framebuffer *amdgpu_fb;
 	struct drm_framebuffer *target_fb;
 	struct drm_gem_object *obj;
 	struct amdgpu_bo *abo;
 		return 0;
 	}
-	if (atomic) {
+	if (atomic)
-		amdgpu_fb = to_amdgpu_framebuffer(fb);
 		target_fb = fb;
-	} else {
+	else
-		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
 		target_fb = crtc->primary->fb;
-	}
 	/* If atomic, assume fb object is pinned & idle & fenced and
 	 * just update base pointers
 	 */
-	obj = amdgpu_fb->obj;
+	obj = target_fb->obj[0];
 	abo = gem_to_amdgpu_bo(obj);
 	r = amdgpu_bo_reserve(abo, false);
 	if (unlikely(r != 0))
 	WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
 	if (!atomic && fb && fb != crtc->primary->fb) {
-		amdgpu_fb = to_amdgpu_framebuffer(fb);
+		abo = gem_to_amdgpu_bo(fb->obj[0]);
-		abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r != 0))
 			return r;
 	if ((adev->asic_type == CHIP_POLARIS10) ||
 	    (adev->asic_type == CHIP_POLARIS11) ||
-	    (adev->asic_type == CHIP_POLARIS12)) {
+	    (adev->asic_type == CHIP_POLARIS12) ||
+	    (adev->asic_type == CHIP_VEGAM)) {
 		struct amdgpu_encoder *amdgpu_encoder =
 			to_amdgpu_encoder(amdgpu_crtc->encoder);
 		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 	dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 	if (crtc->primary->fb) {
 		int r;
-		struct amdgpu_framebuffer *amdgpu_fb;
 		struct amdgpu_bo *abo;
-		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
+		abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
-		abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r))
 			DRM_ERROR("failed to reserve abo before unpin\n");
 	if ((adev->asic_type == CHIP_POLARIS10) ||
 	    (adev->asic_type == CHIP_POLARIS11) ||
-	    (adev->asic_type == CHIP_POLARIS12)) {
+	    (adev->asic_type == CHIP_POLARIS12) ||
+	    (adev->asic_type == CHIP_VEGAM)) {
 		struct amdgpu_encoder *amdgpu_encoder =
 			to_amdgpu_encoder(amdgpu_crtc->encoder);
 		int encoder_mode =
 		adev->mode_info.num_dig = 9;
 		break;
 	case CHIP_POLARIS10:
+	case CHIP_VEGAM:
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 6;
 		break;
 	amdgpu_atombios_encoder_init_dig(adev);
 	if ((adev->asic_type == CHIP_POLARIS10) ||
 	    (adev->asic_type == CHIP_POLARIS11) ||
-	    (adev->asic_type == CHIP_POLARIS12)) {
+	    (adev->asic_type == CHIP_POLARIS12) ||
+	    (adev->asic_type == CHIP_VEGAM)) {
 		amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
 						   DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
 		amdgpu_atombios_crtc_set_dce_clock(adev, 0,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c+5−12

 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct amdgpu_device *adev = dev->dev_private;
-	struct amdgpu_framebuffer *amdgpu_fb;
 	struct drm_framebuffer *target_fb;
 	struct drm_gem_object *obj;
 	struct amdgpu_bo *abo;
 		return 0;
 	}
-	if (atomic) {
+	if (atomic)
-		amdgpu_fb = to_amdgpu_framebuffer(fb);
 		target_fb = fb;
-	} else {
+	else
-		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
 		target_fb = crtc->primary->fb;
-	}
 	/* If atomic, assume fb object is pinned & idle & fenced and
 	 * just update base pointers
 	 */
-	obj = amdgpu_fb->obj;
+	obj = target_fb->obj[0];
 	abo = gem_to_amdgpu_bo(obj);
 	r = amdgpu_bo_reserve(abo, false);
 	if (unlikely(r != 0))
 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
 	if (!atomic && fb && fb != crtc->primary->fb) {
-		amdgpu_fb = to_amdgpu_framebuffer(fb);
+		abo = gem_to_amdgpu_bo(fb->obj[0]);
-		abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r != 0))
 			return r;
 	dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 	if (crtc->primary->fb) {
 		int r;
-		struct amdgpu_framebuffer *amdgpu_fb;
 		struct amdgpu_bo *abo;
-		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
+		abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
-		abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r))
 			DRM_ERROR("failed to reserve abo before unpin\n");

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c+5−12

 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct amdgpu_device *adev = dev->dev_private;
-	struct amdgpu_framebuffer *amdgpu_fb;
 	struct drm_framebuffer *target_fb;
 	struct drm_gem_object *obj;
 	struct amdgpu_bo *abo;
 		return 0;
 	}
-	if (atomic) {
+	if (atomic)
-		amdgpu_fb = to_amdgpu_framebuffer(fb);
 		target_fb = fb;
-	} else {
+	else
-		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
 		target_fb = crtc->primary->fb;
-	}
 	/* If atomic, assume fb object is pinned & idle & fenced and
 	 * just update base pointers
 	 */
-	obj = amdgpu_fb->obj;
+	obj = target_fb->obj[0];
 	abo = gem_to_amdgpu_bo(obj);
 	r = amdgpu_bo_reserve(abo, false);
 	if (unlikely(r != 0))
 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
 	if (!atomic && fb && fb != crtc->primary->fb) {
-		amdgpu_fb = to_amdgpu_framebuffer(fb);
+		abo = gem_to_amdgpu_bo(fb->obj[0]);
-		abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r != 0))
 			return r;
 	dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 	if (crtc->primary->fb) {
 		int r;
-		struct amdgpu_framebuffer *amdgpu_fb;
 		struct amdgpu_bo *abo;
-		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
+		abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
-		abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r))
 			DRM_ERROR("failed to reserve abo before unpin\n");

drivers/gpu/drm/amd/amdgpu/dce_virtual.c+4−5

 	dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 	if (crtc->primary->fb) {
 		int r;
-		struct amdgpu_framebuffer *amdgpu_fb;
 		struct amdgpu_bo *abo;
-		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
+		abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
-		abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r))
 			DRM_ERROR("failed to reserve abo before unpin\n");
 	return 0;
 }
-static int dce_virtual_mode_valid(struct drm_connector *connector,
+static enum drm_mode_status dce_virtual_mode_valid(struct drm_connector *connector,
 				  struct drm_display_mode *mode)
 {
 	return MODE_OK;
 		break;
 	case CHIP_CARRIZO:
 	case CHIP_STONEY:
-	case CHIP_POLARIS11:
 	case CHIP_POLARIS10:
+	case CHIP_POLARIS11:
+	case CHIP_VEGAM:
 		dce_v11_0_disable_dce(adev);
 		break;
 	case CHIP_TOPAZ:

drivers/gpu/drm/amd/amdgpu/df_v1_7.c+112−0

@@ -0,0 +1,112 @@
	1	/*
	2	* Copyright 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "amdgpu.h"
	24	#include "df_v1_7.h"
	25
	26	#include "df/df_1_7_default.h"
	27	#include "df/df_1_7_offset.h"
	28	#include "df/df_1_7_sh_mask.h"
	29
	30	static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
	31
	32	static void df_v1_7_init (struct amdgpu_device *adev)
	33	{
	34	}
	35
	36	static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev,
	37	bool enable)
	38	{
	39	u32 tmp;
	40
	41	if (enable) {
	42	tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
	43	tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
	44	WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
	45	} else
	46	WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
	47	mmFabricConfigAccessControl_DEFAULT);
	48	}
	49
	50	static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev)
	51	{
	52	u32 tmp;
	53
	54	tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
	55	tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
	56	tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
	57
	58	return tmp;
	59	}
	60
	61	static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)
	62	{
	63	int fb_channel_number;
	64
	65	fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
	66
	67	return df_v1_7_channel_number[fb_channel_number];
	68	}
	69
	70	static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
	71	bool enable)
	72	{
	73	u32 tmp;
	74
	75	/* Put DF on broadcast mode */
	76	adev->df_funcs->enable_broadcast_mode(adev, true);
	77
	78	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
	79	tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
	80	tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
	81	tmp \|= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
	82	WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
	83	} else {
	84	tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
	85	tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
	86	tmp \|= DF_V1_7_MGCG_DISABLE;
	87	WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
	88	}
	89
	90	/* Exit boradcast mode */
	91	adev->df_funcs->enable_broadcast_mode(adev, false);
	92	}
	93
	94	static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
	95	u32 *flags)
	96	{
	97	u32 tmp;
	98
	99	/* AMD_CG_SUPPORT_DF_MGCG */
	100	tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
	101	if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)
	102	*flags \|= AMD_CG_SUPPORT_DF_MGCG;
	103	}
	104
	105	const struct amdgpu_df_funcs df_v1_7_funcs = {
	106	.init = df_v1_7_init,
	107	.enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
	108	.get_fb_channel_number = df_v1_7_get_fb_channel_number,
	109	.get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
	110	.update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
	111	.get_clockgating_state = df_v1_7_get_clockgating_state,
	112	};

drivers/gpu/drm/amd/amdgpu/df_v1_7.hrenamed from drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h+13−25

 /*
- * Copyright 2016 Advanced Micro Devices, Inc.
+ * Copyright 2018 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  */
-#ifndef PP_SOC15_H
-#define PP_SOC15_H
-#include "soc15_hw_ip.h"
+#ifndef __DF_V1_7_H__
-#include "vega10_ip_offset.h"
+#define __DF_V1_7_H__
-inline static uint32_t soc15_get_register_offset(
+#include "soc15_common.h"
-		uint32_t hw_id,
+enum DF_V1_7_MGCG
-		uint32_t inst,
-		uint32_t segment,
-		uint32_t offset)
 {
-	uint32_t reg = 0;
+	DF_V1_7_MGCG_DISABLE = 0,
+	DF_V1_7_MGCG_ENABLE_00_CYCLE_DELAY =1,
+	DF_V1_7_MGCG_ENABLE_01_CYCLE_DELAY =2,
+	DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY =13,
+	DF_V1_7_MGCG_ENABLE_31_CYCLE_DELAY =14,
+	DF_V1_7_MGCG_ENABLE_63_CYCLE_DELAY =15
+};
-	if (hw_id == THM_HWID)
+extern const struct amdgpu_df_funcs df_v1_7_funcs;
-		reg = THM_BASE.instance[inst].segment[segment] + offset;
-	else if (hw_id == NBIF_HWID)
-		reg = NBIF_BASE.instance[inst].segment[segment] + offset;
-	else if (hw_id == MP1_HWID)
-		reg = MP1_BASE.instance[inst].segment[segment] + offset;
-	else if (hw_id == DF_HWID)
-		reg = DF_BASE.instance[inst].segment[segment] + offset;
-	else if (hw_id == GC_HWID)
-		reg = GC_BASE.instance[inst].segment[segment] + offset;
-	else if (hw_id == SMUIO_HWID)
-		reg = SMUIO_BASE.instance[inst].segment[segment] + offset;
-	return reg;
-}
 #endif

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c+80−22

 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
-MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
-MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
-MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
-MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
-MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
-MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
-MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
-MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
-MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
-MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
-MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
 MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
 MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
 MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
 MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
 MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
 MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
 MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
 MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
 MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
 MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
+MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
+MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
+MODULE_FIRMWARE("amdgpu/vegam_me.bin");
+MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
+MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
+MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
 {
 	{mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 };
+static const u32 golden_settings_vegam_a11[] =
+{
+	mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
+	mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
+	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
+	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
+	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
+	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
+	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
+	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
+	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
+	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
+	mmSQ_CONFIG, 0x07f80000, 0x01180000,
+	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
+	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
+	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
+	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
+	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
+	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
+};
+static const u32 vegam_golden_common_all[] =
+{
+	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
+	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
+	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
+	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
+	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
+	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
+};
 static const u32 golden_settings_polaris11_a11[] =
 {
 	mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
 							tonga_golden_common_all,
 							ARRAY_SIZE(tonga_golden_common_all));
 		break;
+	case CHIP_VEGAM:
+		amdgpu_device_program_register_sequence(adev,
+							golden_settings_vegam_a11,
+							ARRAY_SIZE(golden_settings_vegam_a11));
+		amdgpu_device_program_register_sequence(adev,
+							vegam_golden_common_all,
+							ARRAY_SIZE(vegam_golden_common_all));
+		break;
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
 		amdgpu_device_program_register_sequence(adev,
 	case CHIP_FIJI:
 		chip_name = "fiji";
 		break;
-	case CHIP_POLARIS11:
+	case CHIP_STONEY:
-		chip_name = "polaris11";
+		chip_name = "stoney";
 		break;
 	case CHIP_POLARIS10:
 		chip_name = "polaris10";
 		break;
+	case CHIP_POLARIS11:
+		chip_name = "polaris11";
+		break;
 	case CHIP_POLARIS12:
 		chip_name = "polaris12";
 		break;
-	case CHIP_STONEY:
+	case CHIP_VEGAM:
-		chip_name = "stoney";
+		chip_name = "vegam";
 		break;
 	default:
 		BUG();
 		gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
 		break;
 	case CHIP_POLARIS10:
+	case CHIP_VEGAM:
 		ret = amdgpu_atombios_get_gfx_info(adev);
 		if (ret)
 			return ret;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	switch (adev->asic_type) {
-	case CHIP_FIJI:
 	case CHIP_TONGA:
+	case CHIP_CARRIZO:
+	case CHIP_FIJI:
+	case CHIP_POLARIS10:
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
-	case CHIP_POLARIS10:
+	case CHIP_VEGAM:
-	case CHIP_CARRIZO:
 		adev->gfx.mec.num_mec = 2;
 		break;
 	case CHIP_TOPAZ:
 		break;
 	case CHIP_FIJI:
+	case CHIP_VEGAM:
 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 				PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 {
 	switch (adev->asic_type) {
 	case CHIP_FIJI:
+	case CHIP_VEGAM:
 		*rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
 			  RB_XSEL2(1) | PKR_MAP(2) |
 			  PKR_XSEL(1) | PKR_YSEL(1) |
 		gfx_v8_0_init_power_gating(adev);
 		WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
 	} else if ((adev->asic_type == CHIP_POLARIS11) ||
-		   (adev->asic_type == CHIP_POLARIS12)) {
+		   (adev->asic_type == CHIP_POLARIS12) ||
+		   (adev->asic_type == CHIP_VEGAM)) {
 		gfx_v8_0_init_csb(adev);
 		gfx_v8_0_init_save_restore_list(adev);
 		gfx_v8_0_enable_save_restore_machine(adev);
 	WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
 	if (adev->asic_type == CHIP_POLARIS11 ||
 	    adev->asic_type == CHIP_POLARIS10 ||
-	    adev->asic_type == CHIP_POLARIS12) {
+	    adev->asic_type == CHIP_POLARIS12 ||
+	    adev->asic_type == CHIP_VEGAM) {
 		tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D);
 		tmp &= ~0x3;
 		WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp);
 						       bool enable)
 {
 	if ((adev->asic_type == CHIP_POLARIS11) ||
-	    (adev->asic_type == CHIP_POLARIS12))
+	    (adev->asic_type == CHIP_POLARIS12) ||
+	    (adev->asic_type == CHIP_VEGAM))
 		/* Send msg to SMU via Powerplay */
 		amdgpu_device_ip_set_powergating_state(adev,
 						       AMD_IP_BLOCK_TYPE_SMC,
 		break;
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
+	case CHIP_VEGAM:
 		if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
 			gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
 		else
 	case CHIP_POLARIS10:
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
+	case CHIP_VEGAM:
 		gfx_v8_0_polaris_update_gfx_clock_gating(adev, state);
 		break;
 	default:

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+185−82

@@ -41,7 +41,6 @@ · 40 unmodified lines
41	#define GFX9_MEC_HPD_SIZE 2048	41	#define GFX9_MEC_HPD_SIZE 2048
42	#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L	42	#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43	#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L	43	#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44	#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
45		44
46	#define mmPWR_MISC_CNTL_STATUS 0x0183	45	#define mmPWR_MISC_CNTL_STATUS 0x0183
47	#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0	46	#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
@@ -185,6 +184,30 @@ static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = · 137 unmodified lines
185	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000)	184	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000)
186	};	185	};
187		186
		187	static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
		188	{
		189	mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
		190	mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
		191	mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
		192	mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
		193	mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
		194	mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
		195	mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
		196	mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
		197	};
		198
		199	static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
		200	{
		201	mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
		202	mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
		203	mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
		204	mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
		205	mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
		206	mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
		207	mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
		208	mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
		209	};
		210
188	#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042	211	#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
189	#define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041	212	#define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
190	#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042	213	#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
@@ -401,6 +424,27 @@ static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) · 210 unmodified lines
401	kfree(adev->gfx.rlc.register_list_format);	424	kfree(adev->gfx.rlc.register_list_format);
402	}	425	}
403		426
		427	static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
		428	{
		429	const struct rlc_firmware_header_v2_1 *rlc_hdr;
		430
		431	rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
		432	adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
		433	adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
		434	adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
		435	adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
		436	adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
		437	adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
		438	adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
		439	adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
		440	adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
		441	adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
		442	adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
		443	adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
		444	adev->gfx.rlc.reg_list_format_direct_reg_list_length =
		445	le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
		446	}
		447
404	static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)	448	static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
405	{	449	{
406	const char *chip_name;	450	const char *chip_name;
@@ -412,6 +456,8 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) · 5 unmodified lines
412	const struct rlc_firmware_header_v2_0 *rlc_hdr;	456	const struct rlc_firmware_header_v2_0 *rlc_hdr;
413	unsigned int *tmp = NULL;	457	unsigned int *tmp = NULL;
414	unsigned int i = 0;	458	unsigned int i = 0;
		459	uint16_t version_major;
		460	uint16_t version_minor;
415		461
416	DRM_DEBUG("\n");	462	DRM_DEBUG("\n");
417		463
@@ -468,6 +514,12 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) · 50 unmodified lines
468	goto out;	514	goto out;
469	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);	515	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
470	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;	516	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
		517
		518	version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
		519	version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
		520	if (version_major == 2 && version_minor == 1)
		521	adev->gfx.rlc.is_rlc_v2_1 = true;
		522
471	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);	523	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
472	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);	524	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
473	adev->gfx.rlc.save_and_restore_offset =	525	adev->gfx.rlc.save_and_restore_offset =
@@ -508,6 +560,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) · 34 unmodified lines
508	for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)	560	for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
509	adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);	561	adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
510		562
		563	if (adev->gfx.rlc.is_rlc_v2_1)
		564	gfx_v9_0_init_rlc_ext_microcode(adev);
		565
511	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);	566	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
512	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);	567	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
513	if (err)	568	if (err)
@@ -566,6 +621,26 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) · 52 unmodified lines
566	adev->firmware.fw_size +=	621	adev->firmware.fw_size +=
567	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);	622	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
568		623
		624	if (adev->gfx.rlc.is_rlc_v2_1) {
		625	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
		626	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
		627	info->fw = adev->gfx.rlc_fw;
		628	adev->firmware.fw_size +=
		629	ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
		630
		631	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
		632	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
		633	info->fw = adev->gfx.rlc_fw;
		634	adev->firmware.fw_size +=
		635	ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
		636
		637	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
		638	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
		639	info->fw = adev->gfx.rlc_fw;
		640	adev->firmware.fw_size +=
		641	ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
		642	}
		643
569	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];	644	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
570	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;	645	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
571	info->fw = adev->gfx.mec_fw;	646	info->fw = adev->gfx.mec_fw;
@@ -1600,6 +1675,7 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) · 1028 unmodified lines
1600		1675
1601	gfx_v9_0_setup_rb(adev);	1676	gfx_v9_0_setup_rb(adev);
1602	gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);	1677	gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
		1678	adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
1603		1679
1604	/* XXX SH_MEM regs */	1680	/* XXX SH_MEM regs */
1605	/* where to put LDS, scratch, GPUVM in FSA64 space */	1681	/* where to put LDS, scratch, GPUVM in FSA64 space */
@@ -1616,7 +1692,10 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) · 10 unmodified lines
1616	tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,	1692	tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1617	SH_MEM_ALIGNMENT_MODE_UNALIGNED);	1693	SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1618	WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);	1694	WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1619	tmp = adev->gmc.shared_aperture_start >> 48;	1695	tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
		1696	(adev->gmc.private_aperture_start >> 48));
		1697	tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
		1698	(adev->gmc.shared_aperture_start >> 48));
1620	WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);	1699	WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1621	}	1700	}
1622	}	1701	}
@@ -1708,55 +1787,42 @@ static void gfx_v9_0_init_csb(struct amdgpu_device *adev) · 85 unmodified lines
1708	adev->gfx.rlc.clear_state_size);	1787	adev->gfx.rlc.clear_state_size);
1709	}	1788	}
1710		1789
1711	static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,	1790	static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
1712	int indirect_offset,	1791	int indirect_offset,
1713	int list_size,	1792	int list_size,
1714	int *unique_indirect_regs,	1793	int *unique_indirect_regs,
1715	int *unique_indirect_reg_count,	1794	int *unique_indirect_reg_count,
1716	int max_indirect_reg_count,
1717	int *indirect_start_offsets,	1795	int *indirect_start_offsets,
1718	int *indirect_start_offsets_count,	1796	int *indirect_start_offsets_count)
1719	int max_indirect_start_offsets_count)
1720	{	1797	{
1721	int idx;	1798	int idx;
1722	bool new_entry = true;
1723		1799
1724	for (; indirect_offset < list_size; indirect_offset++) {	1800	for (; indirect_offset < list_size; indirect_offset++) {
		1801	indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
		1802	indirect_start_offsets_count = indirect_start_offsets_count + 1;
1725		1803
1726	if (new_entry) {	1804	while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
1727	new_entry = false;	1805	indirect_offset += 2;
1728	indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1729	indirect_start_offsets_count = indirect_start_offsets_count + 1;
1730	BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1731	}
1732		1806
1733	if (register_list_format[indirect_offset] == 0xFFFFFFFF) {	1807	/* look for the matching indice */
1734	new_entry = true;	1808	for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1735	continue;	1809	if (unique_indirect_regs[idx] ==
1736	}	1810	register_list_format[indirect_offset] \|\|
		1811	!unique_indirect_regs[idx])
		1812	break;
		1813	}
1737		1814
1738	indirect_offset += 2;	1815	BUG_ON(idx >= *unique_indirect_reg_count);
1739		1816
1740	/* look for the matching indice */	1817	if (!unique_indirect_regs[idx])
1741	for (idx = 0; idx < *unique_indirect_reg_count; idx++) {	1818	unique_indirect_regs[idx] = register_list_format[indirect_offset];
1742	if (unique_indirect_regs[idx] ==
1743	register_list_format[indirect_offset])
1744	break;
1745	}
1746		1819
1747	if (idx >= *unique_indirect_reg_count) {	1820	indirect_offset++;
1748	unique_indirect_regs[*unique_indirect_reg_count] =
1749	register_list_format[indirect_offset];
1750	idx = *unique_indirect_reg_count;
1751	unique_indirect_reg_count = unique_indirect_reg_count + 1;
1752	BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1753	}	1821	}
1754
1755	register_list_format[indirect_offset] = idx;
1756	}	1822	}
1757	}	1823	}
1758		1824
1759	static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)	1825	static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
1760	{	1826	{
1761	int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};	1827	int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1762	int unique_indirect_reg_count = 0;	1828	int unique_indirect_reg_count = 0;
@@ -1765,7 +1831,7 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) · 2 unmodified lines
1765	int indirect_start_offsets_count = 0;	1831	int indirect_start_offsets_count = 0;
1766		1832
1767	int list_size = 0;	1833	int list_size = 0;
1768	int i = 0;	1834	int i = 0, j = 0;
1769	u32 tmp = 0;	1835	u32 tmp = 0;
1770		1836
1771	u32 *register_list_format =	1837	u32 *register_list_format =
@@ -1776,15 +1842,14 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) · 4 unmodified lines
1776	adev->gfx.rlc.reg_list_format_size_bytes);	1842	adev->gfx.rlc.reg_list_format_size_bytes);
1777		1843
1778	/* setup unique_indirect_regs array and indirect_start_offsets array */	1844	/* setup unique_indirect_regs array and indirect_start_offsets array */
1779	gfx_v9_0_parse_ind_reg_list(register_list_format,	1845	unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
1780	GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,	1846	gfx_v9_1_parse_ind_reg_list(register_list_format,
1781	adev->gfx.rlc.reg_list_format_size_bytes >> 2,	1847	adev->gfx.rlc.reg_list_format_direct_reg_list_length,
1782	unique_indirect_regs,	1848	adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1783	&unique_indirect_reg_count,	1849	unique_indirect_regs,
1784	ARRAY_SIZE(unique_indirect_regs),	1850	&unique_indirect_reg_count,
1785	indirect_start_offsets,	1851	indirect_start_offsets,
1786	&indirect_start_offsets_count,	1852	&indirect_start_offsets_count);
1787	ARRAY_SIZE(indirect_start_offsets));
1788		1853
1789	/* enable auto inc in case it is disabled */	1854	/* enable auto inc in case it is disabled */
1790	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));	1855	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
@@ -1798,19 +1863,37 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) · 7 unmodified lines
1798	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),	1863	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1799	adev->gfx.rlc.register_restore[i]);	1864	adev->gfx.rlc.register_restore[i]);
1800		1865
1801	/* load direct register */
1802	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1803	for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1804	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1805	adev->gfx.rlc.register_restore[i]);
1806
1807	/* load indirect register */	1866	/* load indirect register */
1808	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),	1867	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1809	adev->gfx.rlc.reg_list_format_start);	1868	adev->gfx.rlc.reg_list_format_start);
1810	for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)	1869
		1870	/* direct register portion */
		1871	for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
1811	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),	1872	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1812	register_list_format[i]);	1873	register_list_format[i]);
1813		1874
		1875	/* indirect register portion */
		1876	while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
		1877	if (register_list_format[i] == 0xFFFFFFFF) {
		1878	WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
		1879	continue;
		1880	}
		1881
		1882	WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
		1883	WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
		1884
		1885	for (j = 0; j < unique_indirect_reg_count; j++) {
		1886	if (register_list_format[i] == unique_indirect_regs[j]) {
		1887	WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
		1888	break;
		1889	}
		1890	}
		1891
		1892	BUG_ON(j >= unique_indirect_reg_count);
		1893
		1894	i++;
		1895	}
		1896
1814	/* set save/restore list size */	1897	/* set save/restore list size */
1815	list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;	1898	list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1816	list_size = list_size >> 1;	1899	list_size = list_size >> 1;
@@ -1823,14 +1906,19 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) · 6 unmodified lines
1823	adev->gfx.rlc.starting_offsets_start);	1906	adev->gfx.rlc.starting_offsets_start);
1824	for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)	1907	for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
1825	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),	1908	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1826	indirect_start_offsets[i]);	1909	indirect_start_offsets[i]);
1827		1910
1828	/* load unique indirect regs*/	1911	/* load unique indirect regs*/
1829	for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {	1912	for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
1830	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,	1913	if (unique_indirect_regs[i] != 0) {
1831	unique_indirect_regs[i] & 0x3FFFF);	1914	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
1832	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,	1915	+ GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
1833	unique_indirect_regs[i] >> 20);	1916	unique_indirect_regs[i] & 0x3FFFF);
		1917
		1918	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
		1919	+ GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
		1920	unique_indirect_regs[i] >> 20);
		1921	}
1834	}	1922	}
1835		1923
1836	kfree(register_list_format);	1924	kfree(register_list_format);
@@ -2010,6 +2098,9 @@ static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *ad · 173 unmodified lines
2010		2098
2011	static void gfx_v9_0_init_pg(struct amdgpu_device *adev)	2099	static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2012	{	2100	{
		2101	if (!adev->gfx.rlc.is_rlc_v2_1)
		2102	return;
		2103
2013	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG \|	2104	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG \|
2014	AMD_PG_SUPPORT_GFX_SMG \|	2105	AMD_PG_SUPPORT_GFX_SMG \|
2015	AMD_PG_SUPPORT_GFX_DMG \|	2106	AMD_PG_SUPPORT_GFX_DMG \|
@@ -2017,27 +2108,12 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev) · 1 unmodified line
2017	AMD_PG_SUPPORT_GDS \|	2108	AMD_PG_SUPPORT_GDS \|
2018	AMD_PG_SUPPORT_RLC_SMU_HS)) {	2109	AMD_PG_SUPPORT_RLC_SMU_HS)) {
2019	gfx_v9_0_init_csb(adev);	2110	gfx_v9_0_init_csb(adev);
2020	gfx_v9_0_init_rlc_save_restore_list(adev);	2111	gfx_v9_1_init_rlc_save_restore_list(adev);
2021	gfx_v9_0_enable_save_restore_machine(adev);	2112	gfx_v9_0_enable_save_restore_machine(adev);
2022		2113
2023	if (adev->asic_type == CHIP_RAVEN) {	2114	WREG32(mmRLC_JUMP_TABLE_RESTORE,
2024	WREG32(mmRLC_JUMP_TABLE_RESTORE,	2115	adev->gfx.rlc.cp_table_gpu_addr >> 8);
2025	adev->gfx.rlc.cp_table_gpu_addr >> 8);	2116	gfx_v9_0_init_gfx_power_gating(adev);
2026	gfx_v9_0_init_gfx_power_gating(adev);
2027
2028	if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
2029	gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
2030	gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
2031	} else {
2032	gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
2033	gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
2034	}
2035
2036	if (adev->pg_flags & AMD_PG_SUPPORT_CP)
2037	gfx_v9_0_enable_cp_power_gating(adev, true);
2038	else
2039	gfx_v9_0_enable_cp_power_gating(adev, false);
2040	}
2041	}	2117	}
2042	}	2118	}
2043		2119
@@ -3061,6 +3137,9 @@ static int gfx_v9_0_hw_fini(void *handle) · 1017 unmodified lines
3061	struct amdgpu_device adev = (struct amdgpu_device )handle;	3137	struct amdgpu_device adev = (struct amdgpu_device )handle;
3062	int i;	3138	int i;
3063		3139
		3140	amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
		3141	AMD_PG_STATE_UNGATE);
		3142
3064	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);	3143	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3065	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);	3144	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3066		3145
@@ -3279,6 +3358,11 @@ static int gfx_v9_0_late_init(void *handle) · 212 unmodified lines
3279	if (r)	3358	if (r)
3280	return r;	3359	return r;
3281		3360
		3361	r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
		3362	AMD_PG_STATE_GATE);
		3363	if (r)
		3364	return r;
		3365
3282	return 0;	3366	return 0;
3283	}	3367	}
3284		3368
@@ -3339,8 +3423,7 @@ static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev) · 54 unmodified lines
3339	static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,	3423	static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3340	bool enable)	3424	bool enable)
3341	{	3425	{
3342	/* TODO: double check if we need to perform under safe mdoe */	3426	gfx_v9_0_enter_rlc_safe_mode(adev);
3343	/* gfx_v9_0_enter_rlc_safe_mode(adev); */
3344		3427
3345	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {	3428	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3346	gfx_v9_0_enable_gfx_cg_power_gating(adev, true);	3429	gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
@@ -3351,7 +3434,7 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, · 4 unmodified lines
3351	gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);	3434	gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3352	}	3435	}
3353		3436
3354	/* gfx_v9_0_exit_rlc_safe_mode(adev); */	3437	gfx_v9_0_exit_rlc_safe_mode(adev);
3355	}	3438	}
3356		3439
3357	static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,	3440	static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
@@ -3742,7 +3825,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, · 384 unmodified lines
3742	}	3825	}
3743		3826
3744	amdgpu_ring_write(ring, header);	3827	amdgpu_ring_write(ring, header);
3745	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */	3828	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3746	amdgpu_ring_write(ring,	3829	amdgpu_ring_write(ring,
3747	#ifdef __BIG_ENDIAN	3830	#ifdef __BIG_ENDIAN
3748	(2 << 0) \|	3831	(2 << 0) \|
@@ -3774,13 +3857,16 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, · 25 unmodified lines
3774	{	3857	{
3775	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;	3858	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3776	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;	3859	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
		3860	bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
3777		3861
3778	/* RELEASE_MEM - flush caches, send int */	3862	/* RELEASE_MEM - flush caches, send int */
3779	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));	3863	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3780	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN \|	3864	amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN \|
3781	EOP_TC_ACTION_EN \|	3865	EOP_TC_NC_ACTION_EN) :
3782	EOP_TC_WB_ACTION_EN \|	3866	(EOP_TCL1_ACTION_EN \|
3783	EOP_TC_MD_ACTION_EN \|	3867	EOP_TC_ACTION_EN \|
		3868	EOP_TC_WB_ACTION_EN \|
		3869	EOP_TC_MD_ACTION_EN)) \|
3784	EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) \|	3870	EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) \|
3785	EVENT_INDEX(5)));	3871	EVENT_INDEX(5)));
3786	amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) \| INT_SEL(int_sel ? 2 : 0));	3872	amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) \| INT_SEL(int_sel ? 2 : 0));
@@ -4137,6 +4223,20 @@ static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, · 350 unmodified lines
4137	gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);	4223	gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4138	}	4224	}
4139		4225
		4226	static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
		4227	uint32_t reg0, uint32_t reg1,
		4228	uint32_t ref, uint32_t mask)
		4229	{
		4230	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
		4231
		4232	if (amdgpu_sriov_vf(ring->adev))
		4233	gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
		4234	ref, mask, 0x20);
		4235	else
		4236	amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
		4237	ref, mask);
		4238	}
		4239
4140	static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,	4240	static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4141	enum amdgpu_interrupt_state state)	4241	enum amdgpu_interrupt_state state)
4142	{	4242	{
@@ -4458,6 +4558,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { · 315 unmodified lines
4458	.emit_tmz = gfx_v9_0_ring_emit_tmz,	4558	.emit_tmz = gfx_v9_0_ring_emit_tmz,
4459	.emit_wreg = gfx_v9_0_ring_emit_wreg,	4559	.emit_wreg = gfx_v9_0_ring_emit_wreg,
4460	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,	4560	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
		4561	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4461	};	4562	};
4462		4563
4463	static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {	4564	static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
@@ -4492,6 +4593,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { · 28 unmodified lines
4492	.set_priority = gfx_v9_0_ring_set_priority_compute,	4593	.set_priority = gfx_v9_0_ring_set_priority_compute,
4493	.emit_wreg = gfx_v9_0_ring_emit_wreg,	4594	.emit_wreg = gfx_v9_0_ring_emit_wreg,
4494	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,	4595	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
		4596	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4495	};	4597	};
4496		4598
4497	static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {	4599	static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
@@ -4522,6 +4624,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { · 24 unmodified lines
4522	.emit_rreg = gfx_v9_0_ring_emit_rreg,	4624	.emit_rreg = gfx_v9_0_ring_emit_rreg,
4523	.emit_wreg = gfx_v9_0_ring_emit_wreg,	4625	.emit_wreg = gfx_v9_0_ring_emit_wreg,
4524	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,	4626	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
		4627	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4525	};	4628	};
4526		4629
4527	static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)	4630	static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c+23−2

 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	amdgpu_bo_late_init(adev);
 	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 		return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 	else
 		return 0;
 }
+static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
+{
+	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
+	unsigned size;
+	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
+		size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
+	} else {
+		u32 viewport = RREG32(mmVIEWPORT_SIZE);
+		size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
+			REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
+			4);
+	}
+	/* return 0 if the pre-OS buffer uses up most of vram */
+	if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
+		return 0;
+	return size;
+}
 static int gmc_v6_0_sw_init(void *handle)
 {
 	int r;
 	adev->gmc.mc_mask = 0xffffffffffULL;
-	adev->gmc.stolen_size = 256 * 1024;
 	adev->need_dma32 = false;
 	dma_bits = adev->need_dma32 ? 32 : 40;
 	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 	if (r)
 		return r;
+	adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev);
 	r = amdgpu_bo_init(adev);
 	if (r)
 		return r;

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c+23−2

 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	amdgpu_bo_late_init(adev);
 	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 		return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 	else
 		return 0;
 }
+static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
+{
+	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
+	unsigned size;
+	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
+		size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
+	} else {
+		u32 viewport = RREG32(mmVIEWPORT_SIZE);
+		size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
+			REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
+			4);
+	}
+	/* return 0 if the pre-OS buffer uses up most of vram */
+	if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
+		return 0;
+	return size;
+}
 static int gmc_v7_0_sw_init(void *handle)
 {
 	int r;
 	 */
 	adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
-	adev->gmc.stolen_size = 256 * 1024;
 	/* set DMA mask + need_dma32 flags.
 	 * PCIE - can handle 40-bits.
 	 * IGP - can handle 40-bits
 	if (r)
 		return r;
+	adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev);
 	/* Memory manager */
 	r = amdgpu_bo_init(adev);
 	if (r)

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c+29−4

 		break;
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
+	case CHIP_VEGAM:
 		amdgpu_device_program_register_sequence(adev,
 							golden_settings_polaris11_a11,
 							ARRAY_SIZE(golden_settings_polaris11_a11));
 	case CHIP_FIJI:
 	case CHIP_CARRIZO:
 	case CHIP_STONEY:
+	case CHIP_VEGAM:
 		return 0;
 	default: BUG();
 	}
 	/* set the gart size */
 	if (amdgpu_gart_size == -1) {
 		switch (adev->asic_type) {
-		case CHIP_POLARIS11: /* all engines support GPUVM */
 		case CHIP_POLARIS10: /* all engines support GPUVM */
+		case CHIP_POLARIS11: /* all engines support GPUVM */
 		case CHIP_POLARIS12: /* all engines support GPUVM */
+		case CHIP_VEGAM:     /* all engines support GPUVM */
 		default:
 			adev->gmc.gart_size = 256ULL << 20;
 			break;
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	amdgpu_bo_late_init(adev);
 	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 		return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 	else
 		return 0;
 }
+static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
+{
+	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
+	unsigned size;
+	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
+		size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
+	} else {
+		u32 viewport = RREG32(mmVIEWPORT_SIZE);
+		size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
+			REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
+			4);
+	}
+	/* return 0 if the pre-OS buffer uses up most of vram */
+	if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
+		return 0;
+	return size;
+}
 #define mmMC_SEQ_MISC0_FIJI 0xA71
 static int gmc_v8_0_sw_init(void *handle)
 	} else {
 		u32 tmp;
-		if (adev->asic_type == CHIP_FIJI)
+		if ((adev->asic_type == CHIP_FIJI) ||
+		    (adev->asic_type == CHIP_VEGAM))
 			tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
 		else
 			tmp = RREG32(mmMC_SEQ_MISC0);
 	 */
 	adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
-	adev->gmc.stolen_size = 256 * 1024;
 	/* set DMA mask + need_dma32 flags.
 	 * PCIE - can handle 40-bits.
 	 * IGP - can handle 40-bits
 	if (r)
 		return r;
+	adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev);
 	/* Memory manager */
 	r = amdgpu_bo_init(adev);
 	if (r)

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+77−60

@@ -43,19 +43,13 @@ · 42 unmodified lines
43	#include "gfxhub_v1_0.h"	43	#include "gfxhub_v1_0.h"
44	#include "mmhub_v1_0.h"	44	#include "mmhub_v1_0.h"
45		45
46	#define mmDF_CS_AON0_DramBaseAddress0 0x0044	46	/* add these here since we already include dce12 headers and these are for DCN */
47	#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0	47	#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
48	//DF_CS_AON0_DramBaseAddress0	48	#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
49	#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0	49	#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
50	#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1	50	#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
51	#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4	51	#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
52	#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8	52	#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
53	#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
54	#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
55	#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
56	#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
57	#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
58	#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
59		53
60	/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/	54	/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
61	#define AMDGPU_NUM_OF_VMIDS 8	55	#define AMDGPU_NUM_OF_VMIDS 8
@@ -385,11 +379,9 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, · 323 unmodified lines
385	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),	379	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
386	upper_32_bits(pd_addr));	380	upper_32_bits(pd_addr));
387		381
388	amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);	382	amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
389		383	hub->vm_inv_eng0_ack + eng,
390	/* wait for the invalidate to complete */	384	req, 1 << vmid);
391	amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,
392	1 << vmid, 1 << vmid);
393		385
394	return pd_addr;	386	return pd_addr;
395	}	387	}
@@ -556,8 +548,7 @@ static int gmc_v9_0_early_init(void *handle) · 160 unmodified lines
556	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;	548	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
557	adev->gmc.shared_aperture_end =	549	adev->gmc.shared_aperture_end =
558	adev->gmc.shared_aperture_start + (4ULL << 30) - 1;	550	adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
559	adev->gmc.private_aperture_start =	551	adev->gmc.private_aperture_start = 0x1000000000000000ULL;
560	adev->gmc.shared_aperture_end + 1;
561	adev->gmc.private_aperture_end =	552	adev->gmc.private_aperture_end =
562	adev->gmc.private_aperture_start + (4ULL << 30) - 1;	553	adev->gmc.private_aperture_start + (4ULL << 30) - 1;
563		554
@@ -659,6 +650,11 @@ static int gmc_v9_0_late_init(void *handle) · 95 unmodified lines
659	unsigned i;	650	unsigned i;
660	int r;	651	int r;
661		652
		653	/*
		654	* TODO - Uncomment once GART corruption issue is fixed.
		655	*/
		656	/* amdgpu_bo_late_init(adev); */
		657
662	for(i = 0; i < adev->num_rings; ++i) {	658	for(i = 0; i < adev->num_rings; ++i) {
663	struct amdgpu_ring *ring = adev->rings[i];	659	struct amdgpu_ring *ring = adev->rings[i];
664	unsigned vmhub = ring->funcs->vmhub;	660	unsigned vmhub = ring->funcs->vmhub;
@@ -714,7 +710,6 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, · 49 unmodified lines
714	*/	710	*/
715	static int gmc_v9_0_mc_init(struct amdgpu_device *adev)	711	static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
716	{	712	{
717	u32 tmp;
718	int chansize, numchan;	713	int chansize, numchan;
719	int r;	714	int r;
720		715
@@ -727,39 +722,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) · 6 unmodified lines
727	else	722	else
728	chansize = 128;	723	chansize = 128;
729		724
730	tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);	725	numchan = adev->df_funcs->get_hbm_channel_number(adev);
731	tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
732	tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
733	switch (tmp) {
734	case 0:
735	default:
736	numchan = 1;
737	break;
738	case 1:
739	numchan = 2;
740	break;
741	case 2:
742	numchan = 0;
743	break;
744	case 3:
745	numchan = 4;
746	break;
747	case 4:
748	numchan = 0;
749	break;
750	case 5:
751	numchan = 8;
752	break;
753	case 6:
754	numchan = 0;
755	break;
756	case 7:
757	numchan = 16;
758	break;
759	case 8:
760	numchan = 2;
761	break;
762	}
763	adev->gmc.vram_width = numchan * chansize;	726	adev->gmc.vram_width = numchan * chansize;
764	}	727	}
765		728
@@ -826,6 +789,52 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev) · 60 unmodified lines
826	return amdgpu_gart_table_vram_alloc(adev);	789	return amdgpu_gart_table_vram_alloc(adev);
827	}	790	}
828		791
		792	static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
		793	{
		794	#if 0
		795	u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
		796	#endif
		797	unsigned size;
		798
		799	/*
		800	* TODO Remove once GART corruption is resolved
		801	* Check related code in gmc_v9_0_sw_fini
		802	* */
		803	size = 9 * 1024 * 1024;
		804
		805	#if 0
		806	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
		807	size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
		808	} else {
		809	u32 viewport;
		810
		811	switch (adev->asic_type) {
		812	case CHIP_RAVEN:
		813	viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
		814	size = (REG_GET_FIELD(viewport,
		815	HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
		816	REG_GET_FIELD(viewport,
		817	HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
		818	4);
		819	break;
		820	case CHIP_VEGA10:
		821	case CHIP_VEGA12:
		822	default:
		823	viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
		824	size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
		825	REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
		826	4);
		827	break;
		828	}
		829	}
		830	/* return 0 if the pre-OS buffer uses up most of vram */
		831	if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
		832	return 0;
		833
		834	#endif
		835	return size;
		836	}
		837
829	static int gmc_v9_0_sw_init(void *handle)	838	static int gmc_v9_0_sw_init(void *handle)
830	{	839	{
831	int r;	840	int r;
@@ -877,12 +886,6 @@ static int gmc_v9_0_sw_init(void *handle) · 45 unmodified lines
877	*/	886	*/
878	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */	887	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
879		888
880	/*
881	* It needs to reserve 8M stolen memory for vega10
882	* TODO: Figure out how to avoid that...
883	*/
884	adev->gmc.stolen_size = 8 * 1024 * 1024;
885
886	/* set DMA mask + need_dma32 flags.	889	/* set DMA mask + need_dma32 flags.
887	* PCIE - can handle 44-bits.	890	* PCIE - can handle 44-bits.
888	* IGP - can handle 44-bits	891	* IGP - can handle 44-bits
@@ -907,6 +910,8 @@ static int gmc_v9_0_sw_init(void *handle) · 18 unmodified lines
907	if (r)	910	if (r)
908	return r;	911	return r;
909		912
		913	adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
		914
910	/* Memory manager */	915	/* Memory manager */
911	r = amdgpu_bo_init(adev);	916	r = amdgpu_bo_init(adev);
912	if (r)	917	if (r)
@@ -950,6 +955,18 @@ static int gmc_v9_0_sw_fini(void *handle) · 37 unmodified lines
950	amdgpu_gem_force_release(adev);	955	amdgpu_gem_force_release(adev);
951	amdgpu_vm_manager_fini(adev);	956	amdgpu_vm_manager_fini(adev);
952	gmc_v9_0_gart_fini(adev);	957	gmc_v9_0_gart_fini(adev);
		958
		959	/*
		960	* TODO:
		961	* Currently there is a bug where some memory client outside
		962	* of the driver writes to first 8M of VRAM on S3 resume,
		963	* this overrides GART which by default gets placed in first 8M and
		964	* causes VM_FAULTS once GTT is accessed.
		965	* Keep the stolen memory reservation until the while this is not solved.
		966	* Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
		967	*/
		968	amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
		969
953	amdgpu_bo_fini(adev);	970	amdgpu_bo_fini(adev);
954		971
955	return 0;	972	return 0;

drivers/gpu/drm/amd/amdgpu/kv_dpm.c+2−2

@@ -2817,7 +2817,7 @@ static int kv_dpm_init(struct amdgpu_device *adev) · 2816 unmodified lines
2817	pi->caps_tcp_ramping = true;	2817	pi->caps_tcp_ramping = true;
2818	}	2818	}
2819		2819
2820	if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)	2820	if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
2821	pi->caps_sclk_ds = true;	2821	pi->caps_sclk_ds = true;
2822	else	2822	else
2823	pi->caps_sclk_ds = false;	2823	pi->caps_sclk_ds = false;
@@ -2974,7 +2974,7 @@ static int kv_dpm_late_init(void *handle) · 150 unmodified lines
2974	/* powerdown unused blocks for now */	2974	/* powerdown unused blocks for now */
2975	struct amdgpu_device adev = (struct amdgpu_device )handle;	2975	struct amdgpu_device adev = (struct amdgpu_device )handle;
2976		2976
2977	if (!amdgpu_dpm)	2977	if (!adev->pm.dpm_enabled)
2978	return 0;	2978	return 0;
2979		2979
2980	kv_dpm_powergate_acp(adev, true);	2980	kv_dpm_powergate_acp(adev, true);

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c+3−1

 	} while (timeout > 1);
 flr_done:
-	if (locked)
+	if (locked) {
+		adev->in_gpu_reset = 0;
 		mutex_unlock(&adev->lock_reset);
+	}
 	/* Trigger recovery for world switch failure if no TDR */
 	if (amdgpu_lockup_timeout == 0)

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h+46−21

@@ -40,11 +40,20 @@ enum psp_gfx_crtl_cmd_id · 39 unmodified lines
40	GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */	40	GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */
41	GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */	41	GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */
42	GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */	42	GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */
		43	GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
		44	GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
		45	GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */
43		46
44	GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */	47	GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
45	};	48	};
46		49
47		50
		51	/*-----------------------------------------------------------------------------
		52	NOTE: All physical addresses used in this interface are actually
		53	GPU Virtual Addresses.
		54	*/
		55
		56
48	/* Control registers of the TEE Gfx interface. These are located in	57	/* Control registers of the TEE Gfx interface. These are located in
49	* SRBM-to-PSP mailbox registers (total 8 registers).	58	* SRBM-to-PSP mailbox registers (total 8 registers).
50	*/	59	*/
@@ -55,8 +64,8 @@ struct psp_gfx_ctrl · 4 unmodified lines
55	volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */	64	volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */
56	volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */	65	volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */
57	volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */	66	volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */
58	volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of physical address of ring buffer */	67	volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
59	volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of physical address of ring buffer */	68	volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */
60	volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */	69	volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */
61		70
62	};	71	};
@@ -78,6 +87,8 @@ enum psp_gfx_cmd_id · 15 unmodified lines
78	GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */	87	GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */
79	GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */	88	GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */
80	GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */	89	GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */
		90	GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */
		91	GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */
81		92
82	};	93	};
83		94
@@ -85,11 +96,11 @@ enum psp_gfx_cmd_id · 1 unmodified line
85	/* Command to load Trusted Application binary into PSP OS. */	96	/* Command to load Trusted Application binary into PSP OS. */
86	struct psp_gfx_cmd_load_ta	97	struct psp_gfx_cmd_load_ta
87	{	98	{
88	uint32_t app_phy_addr_lo; /* bits [31:0] of the physical address of the TA binary (must be 4 KB aligned) */	99	uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
89	uint32_t app_phy_addr_hi; /* bits [63:32] of the physical address of the TA binary */	100	uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */
90	uint32_t app_len; /* length of the TA binary in bytes */	101	uint32_t app_len; /* length of the TA binary in bytes */
91	uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the physical address of CMD buffer (must be 4 KB aligned) */	102	uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
92	uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the physical address of CMD buffer */	103	uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
93	uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */	104	uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */
94		105
95	/* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided	106	/* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
@@ -111,8 +122,8 @@ struct psp_gfx_cmd_unload_ta · 15 unmodified lines
111	*/	122	*/
112	struct psp_gfx_buf_desc	123	struct psp_gfx_buf_desc
113	{	124	{
114	uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of the buffer (must be 4 KB aligned) */	125	uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
115	uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of the buffer */	126	uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
116	uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */	127	uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
117		128
118	};	129	};
@@ -145,8 +156,8 @@ struct psp_gfx_cmd_invoke_cmd · 26 unmodified lines
145	/* Command to setup TMR region. */	156	/* Command to setup TMR region. */
146	struct psp_gfx_cmd_setup_tmr	157	struct psp_gfx_cmd_setup_tmr
147	{	158	{
148	uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of TMR buffer (must be 4 KB aligned) */	159	uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
149	uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of TMR buffer */	160	uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
150	uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */	161	uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */
151		162
152	};	163	};
@@ -174,18 +185,32 @@ enum psp_gfx_fw_type · 21 unmodified lines
174	GFX_FW_TYPE_ISP = 16,	185	GFX_FW_TYPE_ISP = 16,
175	GFX_FW_TYPE_ACP = 17,	186	GFX_FW_TYPE_ACP = 17,
176	GFX_FW_TYPE_SMU = 18,	187	GFX_FW_TYPE_SMU = 18,
		188	GFX_FW_TYPE_MMSCH = 19,
		189	GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20,
		190	GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21,
		191	GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL = 22,
		192	GFX_FW_TYPE_MAX = 23
177	};	193	};
178		194
179	/* Command to load HW IP FW. */	195	/* Command to load HW IP FW. */
180	struct psp_gfx_cmd_load_ip_fw	196	struct psp_gfx_cmd_load_ip_fw
181	{	197	{
182	uint32_t fw_phy_addr_lo; /* bits [31:0] of physical address of FW location (must be 4 KB aligned) */	198	uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
183	uint32_t fw_phy_addr_hi; /* bits [63:32] of physical address of FW location */	199	uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
184	uint32_t fw_size; /* FW buffer size in bytes */	200	uint32_t fw_size; /* FW buffer size in bytes */
185	enum psp_gfx_fw_type fw_type; /* FW type */	201	enum psp_gfx_fw_type fw_type; /* FW type */
186		202
187	};	203	};
188		204
		205	/* Command to save/restore HW IP FW. */
		206	struct psp_gfx_cmd_save_restore_ip_fw
		207	{
		208	uint32_t save_fw; /* if set, command is used for saving fw otherwise for resetoring*/
		209	uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
		210	uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */
		211	uint32_t buf_size; /* Size of the save/restore buffer in bytes */
		212	enum psp_gfx_fw_type fw_type; /* FW type */
		213	};
189		214
190	/* All GFX ring buffer commands. */	215	/* All GFX ring buffer commands. */
191	union psp_gfx_commands	216	union psp_gfx_commands
@@ -195,7 +220,7 @@ union psp_gfx_commands · 3 unmodified lines
195	struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd;	220	struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd;
196	struct psp_gfx_cmd_setup_tmr cmd_setup_tmr;	221	struct psp_gfx_cmd_setup_tmr cmd_setup_tmr;
197	struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw;	222	struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw;
198		223	struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw;
199	};	224	};
200		225
201		226
@@ -226,8 +251,8 @@ struct psp_gfx_cmd_resp · 24 unmodified lines
226		251
227	/* These fields are used for RBI only. They are all 0 in GPCOM commands	252	/* These fields are used for RBI only. They are all 0 in GPCOM commands
228	*/	253	*/
229	uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of physical address of response buffer (must be 4 KB aligned) */	254	uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
230	uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of physical address of response buffer */	255	uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */
231	uint32_t resp_offset; /* +20 offset within response buffer */	256	uint32_t resp_offset; /* +20 offset within response buffer */
232	uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */	257	uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */
233		258
@@ -251,19 +276,19 @@ struct psp_gfx_cmd_resp · 17 unmodified lines
251	/* Structure of the Ring Buffer Frame */	276	/* Structure of the Ring Buffer Frame */
252	struct psp_gfx_rb_frame	277	struct psp_gfx_rb_frame
253	{	278	{
254	uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of physical address of command buffer (must be 4 KB aligned) */	279	uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
255	uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of physical address of command buffer */	280	uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */
256	uint32_t cmd_buf_size; /* +8 command buffer size in bytes */	281	uint32_t cmd_buf_size; /* +8 command buffer size in bytes */
257	uint32_t fence_addr_lo; /* +12 bits [31:0] of physical address of Fence for this frame */	282	uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */
258	uint32_t fence_addr_hi; /* +16 bits [63:32] of physical address of Fence for this frame */	283	uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */
259	uint32_t fence_value; /* +20 Fence value */	284	uint32_t fence_value; /* +20 Fence value */
260	uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */	285	uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */
261	uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */	286	uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */
262	uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */	287	uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */
263	uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */	288	uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
264	uint8_t reserved1[2]; /* +34 reserved, must be 0 */	289	uint8_t reserved1[2]; /* +34 reserved, must be 0 */
265	uint32_t reserved2[7]; /* +40 reserved, must be 0 */	290	uint32_t reserved2[7]; /* +36 reserved, must be 0 */
266	/* total 64 bytes */	291	/* total 64 bytes */
267	};	292	};
268		293
269	#endif /* _PSP_TEE_GFX_IF_H_ */	294	#endif /* _PSP_TEE_GFX_IF_H_ */

drivers/gpu/drm/amd/amdgpu/psp_v10_0.c+9−0

@@ -70,6 +70,15 @@ psp_v10_0_get_fw_type(struct amdgpu_firmware_info ucode, enum psp_gfx_fw_type · 69 unmodified lines
70	case AMDGPU_UCODE_ID_RLC_G:	70	case AMDGPU_UCODE_ID_RLC_G:
71	*type = GFX_FW_TYPE_RLC_G;	71	*type = GFX_FW_TYPE_RLC_G;
72	break;	72	break;
		73	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
		74	*type = GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL;
		75	break;
		76	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
		77	*type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
		78	break;
		79	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
		80	*type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
		81	break;
73	case AMDGPU_UCODE_ID_SMC:	82	case AMDGPU_UCODE_ID_SMC:
74	*type = GFX_FW_TYPE_SMU;	83	*type = GFX_FW_TYPE_SMU;
75	break;	84	break;

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c+9−3

 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
+MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
+MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
 		break;
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
+	case CHIP_VEGAM:
 		amdgpu_device_program_register_sequence(adev,
 							golden_settings_polaris11_a11,
 							ARRAY_SIZE(golden_settings_polaris11_a11));
 	case CHIP_FIJI:
 		chip_name = "fiji";
 		break;
-	case CHIP_POLARIS11:
-		chip_name = "polaris11";
-		break;
 	case CHIP_POLARIS10:
 		chip_name = "polaris10";
 		break;
+	case CHIP_POLARIS11:
+		chip_name = "polaris11";
+		break;
 	case CHIP_POLARIS12:
 		chip_name = "polaris12";
 		break;
+	case CHIP_VEGAM:
+		chip_name = "vegam";
+		break;
 	case CHIP_CARRIZO:
 		chip_name = "carrizo";
 		break;

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c+35−28

 }
+static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
+				   int mem_space, int hdp,
+				   uint32_t addr0, uint32_t addr1,
+				   uint32_t ref, uint32_t mask,
+				   uint32_t inv)
+{
+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
+			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
+			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
+	if (mem_space) {
+		/* memory */
+		amdgpu_ring_write(ring, addr0);
+		amdgpu_ring_write(ring, addr1);
+	} else {
+		/* registers */
+		amdgpu_ring_write(ring, addr0 << 2);
+		amdgpu_ring_write(ring, addr1 << 2);
+	}
+	amdgpu_ring_write(ring, ref); /* reference */
+	amdgpu_ring_write(ring, mask); /* mask */
+	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
+			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
+}
 /**
  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
  *
 	else
 		ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+	sdma_v4_0_wait_reg_mem(ring, 0, 1,
-			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
+			       adev->nbio_funcs->get_hdp_flush_done_offset(adev),
-			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
+			       adev->nbio_funcs->get_hdp_flush_req_offset(adev),
-	amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2);
+			       ref_and_mask, ref_and_mask, 10);
-	amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2);
-	amdgpu_ring_write(ring, ref_and_mask); /* reference */
-	amdgpu_ring_write(ring, ref_and_mask); /* mask */
-	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
-			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 }
 /**
 	uint64_t addr = ring->fence_drv.gpu_addr;
 	/* wait for idle */
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+	sdma_v4_0_wait_reg_mem(ring, 1, 0,
-			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
+			       addr & 0xfffffffc,
-			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
+			       upper_32_bits(addr) & 0xffffffff,
-			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
+			       seq, 0xffffffff, 4);
-	amdgpu_ring_write(ring, addr & 0xfffffffc);
-	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
-	amdgpu_ring_write(ring, seq); /* reference */
-	amdgpu_ring_write(ring, 0xffffffff); /* mask */
-	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
-			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
 }
 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
 					 uint32_t val, uint32_t mask)
 {
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+	sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
-			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
-			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
-	amdgpu_ring_write(ring, reg << 2);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, val); /* reference */
-	amdgpu_ring_write(ring, mask); /* mask */
-	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
-			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
 }
 static int sdma_v4_0_early_init(void *handle)
 	.pad_ib = sdma_v4_0_ring_pad_ib,
 	.emit_wreg = sdma_v4_0_ring_emit_wreg,
 	.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 };
 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/si.c+7−0

 	}
 }
+static bool si_need_full_reset(struct amdgpu_device *adev)
+{
+	/* change this when we support soft reset */
+	return true;
+}
 static int si_get_pcie_lanes(struct amdgpu_device *adev)
 {
 	u32 link_width_cntl;
 	.get_config_memsize = &si_get_config_memsize,
 	.flush_hdp = &si_flush_hdp,
 	.invalidate_hdp = &si_invalidate_hdp,
+	.need_full_reset = &si_need_full_reset,
 };
 static uint32_t si_get_rev_id(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/si_dpm.c+1−1

@@ -7580,7 +7580,7 @@ static int si_dpm_late_init(void *handle) · 7579 unmodified lines
7580	int ret;	7580	int ret;
7581	struct amdgpu_device adev = (struct amdgpu_device )handle;	7581	struct amdgpu_device adev = (struct amdgpu_device )handle;
7582		7582
7583	if (!amdgpu_dpm)	7583	if (!adev->pm.dpm_enabled)
7584	return 0;	7584	return 0;
7585		7585
7586	ret = si_set_temperature_range(adev);	7586	ret = si_set_temperature_range(adev);

drivers/gpu/drm/amd/amdgpu/soc15.c+19−58

 #include "gmc_v9_0.h"
 #include "gfxhub_v1_0.h"
 #include "mmhub_v1_0.h"
+#include "df_v1_7.h"
 #include "vega10_ih.h"
 #include "sdma_v4_0.h"
 #include "uvd_v7_0.h"
 #include "dce_virtual.h"
 #include "mxgpu_ai.h"
-#define mmFabricConfigAccessControl                                                                    0x0410
-#define mmFabricConfigAccessControl_BASE_IDX                                                           0
-#define mmFabricConfigAccessControl_DEFAULT                                      0x00000000
-//FabricConfigAccessControl
-#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT                                                     0x0
-#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT                                                0x1
-#define FabricConfigAccessControl__CfgRegInstID__SHIFT                                                        0x10
-#define FabricConfigAccessControl__CfgRegInstAccEn_MASK                                                       0x00000001L
-#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK                                                  0x00000002L
-#define FabricConfigAccessControl__CfgRegInstID_MASK                                                          0x00FF0000L
-#define mmDF_PIE_AON0_DfGlobalClkGater                                                                 0x00fc
-#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX                                                        0
-//DF_PIE_AON0_DfGlobalClkGater
-#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT                                                         0x0
-#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK                                                           0x0000000FL
-enum {
-	DF_MGCG_DISABLE = 0,
-	DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
-	DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
-	DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
-	DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
-	DF_MGCG_ENABLE_63_CYCLE_DELAY =15
-};
 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 	{ SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
+	{ SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 };
 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 	} else {
 		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 			return adev->gfx.config.gb_addr_config;
+		else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
+			return adev->gfx.config.db_debug2;
 		return RREG32(reg_offset);
 	}
 }
 	else
 		adev->nbio_funcs = &nbio_v6_1_funcs;
+	adev->df_funcs = &df_v1_7_funcs;
 	adev->nbio_funcs->detect_hw_virt(adev);
 	if (amdgpu_sriov_vf(adev))
 			HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 }
+static bool soc15_need_full_reset(struct amdgpu_device *adev)
+{
+	/* change this when we implement soft reset */
+	return true;
+}
 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 {
 	.read_disabled_bios = &soc15_read_disabled_bios,
 	.get_config_memsize = &soc15_get_config_memsize,
 	.flush_hdp = &soc15_flush_hdp,
 	.invalidate_hdp = &soc15_invalidate_hdp,
+	.need_full_reset = &soc15_need_full_reset,
 };
 static int soc15_common_early_init(void *handle)
 			AMD_CG_SUPPORT_SDMA_LS;
 		adev->pg_flags = AMD_PG_SUPPORT_SDMA;
+		if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
+			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+				AMD_PG_SUPPORT_CP |
+				AMD_PG_SUPPORT_RLC_SMU_HS;
 		adev->external_rev_id = 0x1;
 		break;
 	default:
 		WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
 }
-static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
-						       bool enable)
-{
-	uint32_t data;
-	/* Put DF on broadcast mode */
-	data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
-	data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
-	WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
-		data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
-		data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
-		data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
-		WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
-	} else {
-		data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
-		data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
-		data |= DF_MGCG_DISABLE;
-		WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
-	}
-	WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
-	       mmFabricConfigAccessControl_DEFAULT);
-}
 static int soc15_common_set_clockgating_state(void *handle,
 					    enum amd_clockgating_state state)
 {
 				state == AMD_CG_STATE_GATE ? true : false);
 		soc15_update_rom_medium_grain_clock_gating(adev,
 				state == AMD_CG_STATE_GATE ? true : false);
-		soc15_update_df_medium_grain_clock_gating(adev,
+		adev->df_funcs->update_medium_grain_clock_gating(adev,
 				state == AMD_CG_STATE_GATE ? true : false);
 		break;
 	case CHIP_RAVEN:
 	if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
 		*flags |= AMD_CG_SUPPORT_ROM_MGCG;
-	/* AMD_CG_SUPPORT_DF_MGCG */
+	adev->df_funcs->get_clockgating_state(adev, flags);
-	data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
-	if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
-		*flags |= AMD_CG_SUPPORT_DF_MGCG;
 }
 static int soc15_common_set_powergating_state(void *handle,

drivers/gpu/drm/amd/amdgpu/soc15d.h+1−0

@@ -159,6 +159,7 @@ · 158 unmodified lines
159	#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */	159	#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
160	#define EOP_TCL1_ACTION_EN (1 << 16)	160	#define EOP_TCL1_ACTION_EN (1 << 16)
161	#define EOP_TC_ACTION_EN (1 << 17) /* L2 */	161	#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
		162	#define EOP_TC_NC_ACTION_EN (1 << 19)
162	#define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */	163	#define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */
163		164
164	#define DATA_SEL(x) ((x) << 29)	165	#define DATA_SEL(x) ((x) << 29)

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c+2−2

@@ -688,7 +688,7 @@ static int uvd_v4_2_set_powergating_state(void *handle, · 687 unmodified lines
688		688
689	if (state == AMD_PG_STATE_GATE) {	689	if (state == AMD_PG_STATE_GATE) {
690	uvd_v4_2_stop(adev);	690	uvd_v4_2_stop(adev);
691	if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {	691	if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) {
692	if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &	692	if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &
693	CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) {	693	CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) {
694	WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK \|	694	WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK \|
@@ -699,7 +699,7 @@ static int uvd_v4_2_set_powergating_state(void *handle, · 4 unmodified lines
699	}	699	}
700	return 0;	700	return 0;
701	} else {	701	} else {
702	if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {	702	if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) {
703	if (RREG32_SMC(ixCURRENT_PG_STATUS) &	703	if (RREG32_SMC(ixCURRENT_PG_STATUS) &
704	CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {	704	CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
705	WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK \|	705	WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK \|

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c+16−4

 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
 {
 	return ((adev->asic_type >= CHIP_POLARIS10) &&
-			(adev->asic_type <= CHIP_POLARIS12) &&
+			(adev->asic_type <= CHIP_VEGAM) &&
 			(!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
 }
 		ring = &adev->uvd.ring_enc[0];
 		rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 		r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
-					  rq, amdgpu_sched_jobs, NULL);
+					  rq, NULL);
 		if (r) {
 			DRM_ERROR("Failed setting up UVD ENC run queue.\n");
 			return r;
 	amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }
+/**
+ * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+	/* The firmware doesn't seem to like touching registers at this point. */
+}
 /**
  * uvd_v6_0_ring_test_ring - register write test
  *
 	.set_wptr = uvd_v6_0_ring_set_wptr,
 	.parse_cs = amdgpu_uvd_ring_parse_cs,
 	.emit_frame_size =
-		6 + 6 + /* hdp flush / invalidate */
+		6 + /* hdp invalidate */
 		10 + /* uvd_v6_0_ring_emit_pipeline_sync */
 		14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
 	.emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
 	.emit_ib = uvd_v6_0_ring_emit_ib,
 	.emit_fence = uvd_v6_0_ring_emit_fence,
+	.emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
 	.test_ring = uvd_v6_0_ring_test_ring,
 	.test_ib = amdgpu_uvd_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
 	.get_wptr = uvd_v6_0_ring_get_wptr,
 	.set_wptr = uvd_v6_0_ring_set_wptr,
 	.emit_frame_size =
-		6 + 6 + /* hdp flush / invalidate */
+		6 + /* hdp invalidate */
 		10 + /* uvd_v6_0_ring_emit_pipeline_sync */
 		VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */
 		14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
 	.emit_fence = uvd_v6_0_ring_emit_fence,
 	.emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
 	.emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
+	.emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
 	.test_ring = uvd_v6_0_ring_test_ring,
 	.test_ib = amdgpu_uvd_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c+15−2

 	ring = &adev->uvd.ring_enc[0];
 	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 	r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
-				  rq, amdgpu_sched_jobs, NULL);
+				  rq, NULL);
 	if (r) {
 		DRM_ERROR("Failed setting up UVD ENC run queue.\n");
 		return r;
 	amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }
+/**
+ * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+	/* The firmware doesn't seem to like touching registers at this point. */
+}
 /**
  * uvd_v7_0_ring_test_ring - register write test
  *
 	.get_wptr = uvd_v7_0_ring_get_wptr,
 	.set_wptr = uvd_v7_0_ring_set_wptr,
 	.emit_frame_size =
-		6 + 6 + /* hdp flush / invalidate */
+		6 + /* hdp invalidate */
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 		8 + /* uvd_v7_0_ring_emit_vm_flush */
 	.emit_ib = uvd_v7_0_ring_emit_ib,
 	.emit_fence = uvd_v7_0_ring_emit_fence,
 	.emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
+	.emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
 	.test_ring = uvd_v7_0_ring_test_ring,
 	.test_ib = amdgpu_uvd_ring_test_ib,
 	.insert_nop = uvd_v7_0_ring_insert_nop,
 	.end_use = amdgpu_uvd_ring_end_use,
 	.emit_wreg = uvd_v7_0_ring_emit_wreg,
 	.emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 };
 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
 	.end_use = amdgpu_uvd_ring_end_use,
 	.emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
 	.emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,
+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 };
 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c+4−3

@@ -388,7 +388,8 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) · 387 unmodified lines
388	default:	388	default:
389	if ((adev->asic_type == CHIP_POLARIS10) \|\|	389	if ((adev->asic_type == CHIP_POLARIS10) \|\|
390	(adev->asic_type == CHIP_POLARIS11) \|\|	390	(adev->asic_type == CHIP_POLARIS11) \|\|
391	(adev->asic_type == CHIP_POLARIS12))	391	(adev->asic_type == CHIP_POLARIS12) \|\|
		392	(adev->asic_type == CHIP_VEGAM))
392	return AMDGPU_VCE_HARVEST_VCE1;	393	return AMDGPU_VCE_HARVEST_VCE1;
393		394
394	return 0;	395	return 0;
@@ -467,8 +468,8 @@ static int vce_v3_0_hw_init(void *handle) · 72 unmodified lines
467	struct amdgpu_device adev = (struct amdgpu_device )handle;	468	struct amdgpu_device adev = (struct amdgpu_device )handle;
468		469
469	vce_v3_0_override_vce_clock_gating(adev, true);	470	vce_v3_0_override_vce_clock_gating(adev, true);
470	if (!(adev->flags & AMD_IS_APU))	471
471	amdgpu_asic_set_vce_clocks(adev, 10000, 10000);	472	amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
472		473
473	for (i = 0; i < adev->vce.num_rings; i++)	474	for (i = 0; i < adev->vce.num_rings; i++)
474	adev->vce.ring[i].ready = false;	475	adev->vce.ring[i].ready = false;

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c+1−0

@@ -1081,6 +1081,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = { · 1080 unmodified lines
1081	.end_use = amdgpu_vce_ring_end_use,	1081	.end_use = amdgpu_vce_ring_end_use,
1082	.emit_wreg = vce_v4_0_emit_wreg,	1082	.emit_wreg = vce_v4_0_emit_wreg,
1083	.emit_reg_wait = vce_v4_0_emit_reg_wait,	1083	.emit_reg_wait = vce_v4_0_emit_reg_wait,
		1084	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1084	};	1085	};
1085		1086
1086	static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev)	1087	static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c+2−0

 	.end_use = amdgpu_vcn_ring_end_use,
 	.emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
 	.emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 };
 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
 	.end_use = amdgpu_vcn_ring_end_use,
 	.emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
 	.emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 };
 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/vi.c+111−19

@@ -305,9 +305,10 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) · 304 unmodified lines
305	stoney_mgcg_cgcg_init,	305	stoney_mgcg_cgcg_init,
306	ARRAY_SIZE(stoney_mgcg_cgcg_init));	306	ARRAY_SIZE(stoney_mgcg_cgcg_init));
307	break;	307	break;
308	case CHIP_POLARIS11:
309	case CHIP_POLARIS10:	308	case CHIP_POLARIS10:
		309	case CHIP_POLARIS11:
310	case CHIP_POLARIS12:	310	case CHIP_POLARIS12:
		311	case CHIP_VEGAM:
311	default:	312	default:
312	break;	313	break;
313	}	314	}
@@ -728,33 +729,59 @@ static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, · 414 unmodified lines
728	return r;	729	return r;
729		730
730	tmp = RREG32_SMC(cntl_reg);	731	tmp = RREG32_SMC(cntl_reg);
731	tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK \|	732
732	CG_DCLK_CNTL__DCLK_DIVIDER_MASK);	733	if (adev->flags & AMD_IS_APU)
		734	tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
		735	else
		736	tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK \|
		737	CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
733	tmp \|= dividers.post_divider;	738	tmp \|= dividers.post_divider;
734	WREG32_SMC(cntl_reg, tmp);	739	WREG32_SMC(cntl_reg, tmp);
735		740
736	for (i = 0; i < 100; i++) {	741	for (i = 0; i < 100; i++) {
737	if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)	742	tmp = RREG32_SMC(status_reg);
738	break;	743	if (adev->flags & AMD_IS_APU) {
		744	if (tmp & 0x10000)
		745	break;
		746	} else {
		747	if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
		748	break;
		749	}
739	mdelay(10);	750	mdelay(10);
740	}	751	}
741	if (i == 100)	752	if (i == 100)
742	return -ETIMEDOUT;	753	return -ETIMEDOUT;
743
744	return 0;	754	return 0;
745	}	755	}
746		756
		757	#define ixGNB_CLK1_DFS_CNTL 0xD82200F0
		758	#define ixGNB_CLK1_STATUS 0xD822010C
		759	#define ixGNB_CLK2_DFS_CNTL 0xD8220110
		760	#define ixGNB_CLK2_STATUS 0xD822012C
		761	#define ixGNB_CLK3_DFS_CNTL 0xD8220130
		762	#define ixGNB_CLK3_STATUS 0xD822014C
		763
747	static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)	764	static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
748	{	765	{
749	int r;	766	int r;
750		767
751	r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);	768	if (adev->flags & AMD_IS_APU) {
752	if (r)	769	r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
753	return r;	770	if (r)
		771	return r;
754		772
755	r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);	773	r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
756	if (r)	774	if (r)
757	return r;	775	return r;
		776	} else {
		777	r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
		778	if (r)
		779	return r;
		780
		781	r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
		782	if (r)
		783	return r;
		784	}
758		785
759	return 0;	786	return 0;
760	}	787	}
@@ -764,6 +791,22 @@ static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) · 3 unmodified lines
764	int r, i;	791	int r, i;
765	struct atom_clock_dividers dividers;	792	struct atom_clock_dividers dividers;
766	u32 tmp;	793	u32 tmp;
		794	u32 reg_ctrl;
		795	u32 reg_status;
		796	u32 status_mask;
		797	u32 reg_mask;
		798
		799	if (adev->flags & AMD_IS_APU) {
		800	reg_ctrl = ixGNB_CLK3_DFS_CNTL;
		801	reg_status = ixGNB_CLK3_STATUS;
		802	status_mask = 0x00010000;
		803	reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
		804	} else {
		805	reg_ctrl = ixCG_ECLK_CNTL;
		806	reg_status = ixCG_ECLK_STATUS;
		807	status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
		808	reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK \| CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
		809	}
767		810
768	r = amdgpu_atombios_get_clock_dividers(adev,	811	r = amdgpu_atombios_get_clock_dividers(adev,
769	COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,	812	COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
@@ -772,24 +815,25 @@ static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) · 2 unmodified lines
772	return r;	815	return r;
773		816
774	for (i = 0; i < 100; i++) {	817	for (i = 0; i < 100; i++) {
775	if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)	818	if (RREG32_SMC(reg_status) & status_mask)
776	break;	819	break;
777	mdelay(10);	820	mdelay(10);
778	}	821	}
		822
779	if (i == 100)	823	if (i == 100)
780	return -ETIMEDOUT;	824	return -ETIMEDOUT;
781		825
782	tmp = RREG32_SMC(ixCG_ECLK_CNTL);	826	tmp = RREG32_SMC(reg_ctrl);
783	tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK \|	827	tmp &= ~reg_mask;
784	CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
785	tmp \|= dividers.post_divider;	828	tmp \|= dividers.post_divider;
786	WREG32_SMC(ixCG_ECLK_CNTL, tmp);	829	WREG32_SMC(reg_ctrl, tmp);
787		830
788	for (i = 0; i < 100; i++) {	831	for (i = 0; i < 100; i++) {
789	if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)	832	if (RREG32_SMC(reg_status) & status_mask)
790	break;	833	break;
791	mdelay(10);	834	mdelay(10);
792	}	835	}
		836
793	if (i == 100)	837	if (i == 100)
794	return -ETIMEDOUT;	838	return -ETIMEDOUT;
795		839
@@ -876,6 +920,27 @@ static void vi_invalidate_hdp(struct amdgpu_device *adev, · 80 unmodified lines
876	}	920	}
877	}	921	}
878		922
		923	static bool vi_need_full_reset(struct amdgpu_device *adev)
		924	{
		925	switch (adev->asic_type) {
		926	case CHIP_CARRIZO:
		927	case CHIP_STONEY:
		928	/* CZ has hang issues with full reset at the moment */
		929	return false;
		930	case CHIP_FIJI:
		931	case CHIP_TONGA:
		932	/* XXX: soft reset should work on fiji and tonga */
		933	return true;
		934	case CHIP_POLARIS10:
		935	case CHIP_POLARIS11:
		936	case CHIP_POLARIS12:
		937	case CHIP_TOPAZ:
		938	default:
		939	/* change this when we support soft reset */
		940	return true;
		941	}
		942	}
		943
879	static const struct amdgpu_asic_funcs vi_asic_funcs =	944	static const struct amdgpu_asic_funcs vi_asic_funcs =
880	{	945	{
881	.read_disabled_bios = &vi_read_disabled_bios,	946	.read_disabled_bios = &vi_read_disabled_bios,
@@ -889,6 +954,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs = · 7 unmodified lines
889	.get_config_memsize = &vi_get_config_memsize,	954	.get_config_memsize = &vi_get_config_memsize,
890	.flush_hdp = &vi_flush_hdp,	955	.flush_hdp = &vi_flush_hdp,
891	.invalidate_hdp = &vi_invalidate_hdp,	956	.invalidate_hdp = &vi_invalidate_hdp,
		957	.need_full_reset = &vi_need_full_reset,
892	};	958	};
893		959
894	#define CZ_REV_BRISTOL(rev) \	960	#define CZ_REV_BRISTOL(rev) \
@@ -1031,6 +1097,30 @@ static int vi_common_early_init(void *handle) · 136 unmodified lines
1031	adev->pg_flags = 0;	1097	adev->pg_flags = 0;
1032	adev->external_rev_id = adev->rev_id + 0x64;	1098	adev->external_rev_id = adev->rev_id + 0x64;
1033	break;	1099	break;
		1100	case CHIP_VEGAM:
		1101	adev->cg_flags = 0;
		1102	/*AMD_CG_SUPPORT_GFX_MGCG \|
		1103	AMD_CG_SUPPORT_GFX_RLC_LS \|
		1104	AMD_CG_SUPPORT_GFX_CP_LS \|
		1105	AMD_CG_SUPPORT_GFX_CGCG \|
		1106	AMD_CG_SUPPORT_GFX_CGLS \|
		1107	AMD_CG_SUPPORT_GFX_3D_CGCG \|
		1108	AMD_CG_SUPPORT_GFX_3D_CGLS \|
		1109	AMD_CG_SUPPORT_SDMA_MGCG \|
		1110	AMD_CG_SUPPORT_SDMA_LS \|
		1111	AMD_CG_SUPPORT_BIF_MGCG \|
		1112	AMD_CG_SUPPORT_BIF_LS \|
		1113	AMD_CG_SUPPORT_HDP_MGCG \|
		1114	AMD_CG_SUPPORT_HDP_LS \|
		1115	AMD_CG_SUPPORT_ROM_MGCG \|
		1116	AMD_CG_SUPPORT_MC_MGCG \|
		1117	AMD_CG_SUPPORT_MC_LS \|
		1118	AMD_CG_SUPPORT_DRM_LS \|
		1119	AMD_CG_SUPPORT_UVD_MGCG \|
		1120	AMD_CG_SUPPORT_VCE_MGCG;*/
		1121	adev->pg_flags = 0;
		1122	adev->external_rev_id = adev->rev_id + 0x6E;
		1123	break;
1034	case CHIP_CARRIZO:	1124	case CHIP_CARRIZO:
1035	adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG \|	1125	adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG \|
1036	AMD_CG_SUPPORT_GFX_MGCG \|	1126	AMD_CG_SUPPORT_GFX_MGCG \|
@@ -1422,6 +1512,7 @@ static int vi_common_set_clockgating_state(void *handle, · 385 unmodified lines
1422	case CHIP_POLARIS10:	1512	case CHIP_POLARIS10:
1423	case CHIP_POLARIS11:	1513	case CHIP_POLARIS11:
1424	case CHIP_POLARIS12:	1514	case CHIP_POLARIS12:
		1515	case CHIP_VEGAM:
1425	vi_common_set_clockgating_state_by_smu(adev, state);	1516	vi_common_set_clockgating_state_by_smu(adev, state);
1426	default:	1517	default:
1427	break;	1518	break;
@@ -1551,9 +1642,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) · 123 unmodified lines
1551	amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);	1642	amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1552	}	1643	}
1553	break;	1644	break;
1554	case CHIP_POLARIS11:
1555	case CHIP_POLARIS10:	1645	case CHIP_POLARIS10:
		1646	case CHIP_POLARIS11:
1556	case CHIP_POLARIS12:	1647	case CHIP_POLARIS12:
		1648	case CHIP_VEGAM:
1557	amdgpu_device_ip_block_add(adev, &vi_common_ip_block);	1649	amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1558	amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);	1650	amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
1559	amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);	1651	amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);

drivers/gpu/drm/amd/display/Kconfig+6−8

 	  support for AMDGPU. This adds required support for Vega and
 	  Raven ASICs.
-config DRM_AMD_DC_PRE_VEGA
-	bool "DC support for Polaris and older ASICs"
-	default y
-	help
-	  Choose this option to enable the new DC support for older asics
-	  by default. This includes Polaris, Carrizo, Tonga, Bonaire,
-	  and Hawaii.
 config DRM_AMD_DC_FBC
 	bool "AMD FBC - Enable Frame Buffer Compression"
 	depends on DRM_AMD_DC
 	  if you want to hit
 	  kdgb_break in assert.
+config DRM_AMD_DC_VEGAM
+        bool "VEGAM support"
+        depends on DRM_AMD_DC
+        help
+         Choose this option if you want to have
+         VEGAM support for display engine
 endmenu

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+153−72

@@ -433,11 +433,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) · 432 unmodified lines
433		433
434	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;	434	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
435		435
436	if (amdgpu_dc_log)
437	init_data.log_mask = DC_DEFAULT_LOG_MASK;
438	else
439	init_data.log_mask = DC_MIN_LOG_MASK;
440
441	/*	436	/*
442	* TODO debug why this doesn't work on Raven	437	* TODO debug why this doesn't work on Raven
443	*/	438	*/
@@ -649,18 +644,6 @@ amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, · 205 unmodified lines
649	static int dm_resume(void *handle)	644	static int dm_resume(void *handle)
650	{	645	{
651	struct amdgpu_device *adev = handle;	646	struct amdgpu_device *adev = handle;
652	struct amdgpu_display_manager *dm = &adev->dm;
653	int ret = 0;
654
655	/* power on hardware */
656	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
657
658	ret = amdgpu_dm_display_resume(adev);
659	return ret;
660	}
661
662	int amdgpu_dm_display_resume(struct amdgpu_device *adev)
663	{
664	struct drm_device *ddev = adev->ddev;	647	struct drm_device *ddev = adev->ddev;
665	struct amdgpu_display_manager *dm = &adev->dm;	648	struct amdgpu_display_manager *dm = &adev->dm;
666	struct amdgpu_dm_connector *aconnector;	649	struct amdgpu_dm_connector *aconnector;
@@ -671,10 +654,12 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 4 unmodified lines
671	struct drm_plane *plane;	654	struct drm_plane *plane;
672	struct drm_plane_state *new_plane_state;	655	struct drm_plane_state *new_plane_state;
673	struct dm_plane_state *dm_new_plane_state;	656	struct dm_plane_state *dm_new_plane_state;
674		657	int ret;
675	int ret = 0;
676	int i;	658	int i;
677		659
		660	/* power on hardware */
		661	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
		662
678	/* program HPD filter */	663	/* program HPD filter */
679	dc_resume(dm->dc);	664	dc_resume(dm->dc);
680		665
@@ -688,8 +673,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 7 unmodified lines
688	amdgpu_dm_irq_resume_early(adev);	673	amdgpu_dm_irq_resume_early(adev);
689		674
690	/* Do detection*/	675	/* Do detection*/
691	list_for_each_entry(connector,	676	list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
692	&ddev->mode_config.connector_list, head) {
693	aconnector = to_amdgpu_dm_connector(connector);	677	aconnector = to_amdgpu_dm_connector(connector);
694		678
695	/*	679	/*
@@ -711,7 +695,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 15 unmodified lines
711	}	695	}
712		696
713	/* Force mode set in atomic comit */	697	/* Force mode set in atomic comit */
714	for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)	698	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
715	new_crtc_state->active_changed = true;	699	new_crtc_state->active_changed = true;
716		700
717	/*	701	/*
@@ -719,7 +703,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 1 unmodified line
719	* them here, since they were duplicated as part of the suspend	703	* them here, since they were duplicated as part of the suspend
720	* procedure.	704	* procedure.
721	*/	705	*/
722	for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {	706	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
723	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);	707	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
724	if (dm_new_crtc_state->stream) {	708	if (dm_new_crtc_state->stream) {
725	WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);	709	WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
@@ -728,7 +712,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 2 unmodified lines
728	}	712	}
729	}	713	}
730		714
731	for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {	715	for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
732	dm_new_plane_state = to_dm_plane_state(new_plane_state);	716	dm_new_plane_state = to_dm_plane_state(new_plane_state);
733	if (dm_new_plane_state->dc_state) {	717	if (dm_new_plane_state->dc_state) {
734	WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);	718	WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
@@ -737,9 +721,9 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) · 2 unmodified lines
737	}	721	}
738	}	722	}
739		723
740	ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);	724	ret = drm_atomic_helper_resume(ddev, dm->cached_state);
741		725
742	adev->dm.cached_state = NULL;	726	dm->cached_state = NULL;
743		727
744	amdgpu_dm_irq_resume_late(adev);	728	amdgpu_dm_irq_resume_late(adev);
745		729
@@ -1529,6 +1513,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) · 783 unmodified lines
1529	case CHIP_POLARIS11:	1513	case CHIP_POLARIS11:
1530	case CHIP_POLARIS10:	1514	case CHIP_POLARIS10:
1531	case CHIP_POLARIS12:	1515	case CHIP_POLARIS12:
		1516	#if defined(CONFIG_DRM_AMD_DC_VEGAM)
		1517	case CHIP_VEGAM:
		1518	#endif
1532	case CHIP_VEGA10:	1519	case CHIP_VEGA10:
1533	case CHIP_VEGA12:	1520	case CHIP_VEGA12:
1534	if (dce110_register_irq_handlers(dm->adev)) {	1521	if (dce110_register_irq_handlers(dm->adev)) {
@@ -1549,7 +1536,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) · 14 unmodified lines
1549	break;	1536	break;
1550	#endif	1537	#endif
1551	default:	1538	default:
1552	DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);	1539	DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1553	goto fail;	1540	goto fail;
1554	}	1541	}
1555		1542
@@ -1657,7 +1644,6 @@ static ssize_t s3_debug_store(struct device *device, · 101 unmodified lines
1657	if (ret == 0) {	1644	if (ret == 0) {
1658	if (s3_state) {	1645	if (s3_state) {
1659	dm_resume(adev);	1646	dm_resume(adev);
1660	amdgpu_dm_display_resume(adev);
1661	drm_kms_helper_hotplug_event(adev->ddev);	1647	drm_kms_helper_hotplug_event(adev->ddev);
1662	} else	1648	} else
1663	dm_suspend(adev);	1649	dm_suspend(adev);
@@ -1722,6 +1708,9 @@ static int dm_early_init(void *handle) · 58 unmodified lines
1722	adev->mode_info.plane_type = dm_plane_type_default;	1708	adev->mode_info.plane_type = dm_plane_type_default;
1723	break;	1709	break;
1724	case CHIP_POLARIS10:	1710	case CHIP_POLARIS10:
		1711	#if defined(CONFIG_DRM_AMD_DC_VEGAM)
		1712	case CHIP_VEGAM:
		1713	#endif
1725	adev->mode_info.num_crtc = 6;	1714	adev->mode_info.num_crtc = 6;
1726	adev->mode_info.num_hpd = 6;	1715	adev->mode_info.num_hpd = 6;
1727	adev->mode_info.num_dig = 6;	1716	adev->mode_info.num_dig = 6;
@@ -1743,7 +1732,7 @@ static int dm_early_init(void *handle) · 15 unmodified lines
1743	break;	1732	break;
1744	#endif	1733	#endif
1745	default:	1734	default:
1746	DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);	1735	DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1747	return -EINVAL;	1736	return -EINVAL;
1748	}	1737	}
1749		1738
@@ -1848,7 +1837,7 @@ static bool fill_rects_from_plane_state(const struct drm_plane_state *state, · 98 unmodified lines
1848	static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,	1837	static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1849	uint64_t *tiling_flags)	1838	uint64_t *tiling_flags)
1850	{	1839	{
1851	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);	1840	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1852	int r = amdgpu_bo_reserve(rbo, false);	1841	int r = amdgpu_bo_reserve(rbo, false);
1853		1842
1854	if (unlikely(r)) {	1843	if (unlikely(r)) {
@@ -2017,7 +2006,6 @@ static int fill_plane_attributes(struct amdgpu_device *adev, · 162 unmodified lines
2017	const struct amdgpu_framebuffer *amdgpu_fb =	2006	const struct amdgpu_framebuffer *amdgpu_fb =
2018	to_amdgpu_framebuffer(plane_state->fb);	2007	to_amdgpu_framebuffer(plane_state->fb);
2019	const struct drm_crtc *crtc = plane_state->crtc;	2008	const struct drm_crtc *crtc = plane_state->crtc;
2020	struct dc_transfer_func *input_tf;
2021	int ret = 0;	2009	int ret = 0;
2022		2010
2023	if (!fill_rects_from_plane_state(plane_state, dc_plane_state))	2011	if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
@@ -2031,13 +2019,6 @@ static int fill_plane_attributes(struct amdgpu_device *adev, · 7 unmodified lines
2031	if (ret)	2019	if (ret)
2032	return ret;	2020	return ret;
2033		2021
2034	input_tf = dc_create_transfer_func();
2035
2036	if (input_tf == NULL)
2037	return -ENOMEM;
2038
2039	dc_plane_state->in_transfer_func = input_tf;
2040
2041	/*	2022	/*
2042	* Always set input transfer function, since plane state is refreshed	2023	* Always set input transfer function, since plane state is refreshed
2043	* every time.	2024	* every time.
@@ -2206,7 +2187,6 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, · 162 unmodified lines
2206	const struct drm_connector *connector)	2187	const struct drm_connector *connector)
2207	{	2188	{
2208	struct dc_crtc_timing *timing_out = &stream->timing;	2189	struct dc_crtc_timing *timing_out = &stream->timing;
2209	struct dc_transfer_func *tf = dc_create_transfer_func();
2210		2190
2211	memset(timing_out, 0, sizeof(struct dc_crtc_timing));	2191	memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2212		2192
@@ -2250,9 +2230,8 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, · 37 unmodified lines
2250		2230
2251	stream->output_color_space = get_output_color_space(timing_out);	2231	stream->output_color_space = get_output_color_space(timing_out);
2252		2232
2253	tf->type = TF_TYPE_PREDEFINED;	2233	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2254	tf->tf = TRANSFER_FUNCTION_SRGB;	2234	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
2255	stream->out_transfer_func = tf;
2256	}	2235	}
2257		2236
2258	static void fill_audio_info(struct audio_info *audio_info,	2237	static void fill_audio_info(struct audio_info *audio_info,
@@ -2488,6 +2467,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 229 unmodified lines
2488		2467
2489	update_stream_signal(stream);	2468	update_stream_signal(stream);
2490		2469
		2470	if (dm_state && dm_state->freesync_capable)
		2471	stream->ignore_msa_timing_param = true;
		2472
2491	return stream;	2473	return stream;
2492	}	2474	}
2493		2475
@@ -2710,18 +2692,15 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) · 216 unmodified lines
2710	const struct dc_link *link = aconnector->dc_link;	2692	const struct dc_link *link = aconnector->dc_link;
2711	struct amdgpu_device *adev = connector->dev->dev_private;	2693	struct amdgpu_device *adev = connector->dev->dev_private;
2712	struct amdgpu_display_manager *dm = &adev->dm;	2694	struct amdgpu_display_manager *dm = &adev->dm;
		2695
2713	#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) \|\|\	2696	#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) \|\|\
2714	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)	2697	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2715		2698
2716	if ((link->connector_signal & (SIGNAL_TYPE_EDP \| SIGNAL_TYPE_LVDS)) &&	2699	if ((link->connector_signal & (SIGNAL_TYPE_EDP \| SIGNAL_TYPE_LVDS)) &&
2717	link->type != dc_connection_none) {	2700	link->type != dc_connection_none &&
2718	amdgpu_dm_register_backlight_device(dm);	2701	dm->backlight_dev) {
2719		2702	backlight_device_unregister(dm->backlight_dev);
2720	if (dm->backlight_dev) {	2703	dm->backlight_dev = NULL;
2721	backlight_device_unregister(dm->backlight_dev);
2722	dm->backlight_dev = NULL;
2723	}
2724
2725	}	2704	}
2726	#endif	2705	#endif
2727	drm_connector_unregister(connector);	2706	drm_connector_unregister(connector);
@@ -2855,7 +2834,7 @@ static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) · 127 unmodified lines
2855	create_eml_sink(aconnector);	2834	create_eml_sink(aconnector);
2856	}	2835	}
2857		2836
2858	int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,	2837	enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2859	struct drm_display_mode *mode)	2838	struct drm_display_mode *mode)
2860	{	2839	{
2861	int result = MODE_ERROR;	2840	int result = MODE_ERROR;
@@ -3058,8 +3037,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, · 196 unmodified lines
3058	}	3037	}
3059		3038
3060	afb = to_amdgpu_framebuffer(new_state->fb);	3039	afb = to_amdgpu_framebuffer(new_state->fb);
3061		3040	obj = new_state->fb->obj[0];
3062	obj = afb->obj;
3063	rbo = gem_to_amdgpu_bo(obj);	3041	rbo = gem_to_amdgpu_bo(obj);
3064	adev = amdgpu_ttm_adev(rbo->tbo.bdev);	3042	adev = amdgpu_ttm_adev(rbo->tbo.bdev);
3065	r = amdgpu_bo_reserve(rbo, false);	3043	r = amdgpu_bo_reserve(rbo, false);
@@ -3067,12 +3045,11 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, · 1 unmodified line
3067	return r;	3045	return r;
3068		3046
3069	if (plane->type != DRM_PLANE_TYPE_CURSOR)	3047	if (plane->type != DRM_PLANE_TYPE_CURSOR)
3070	domain = amdgpu_display_framebuffer_domains(adev);	3048	domain = amdgpu_display_supported_domains(adev);
3071	else	3049	else
3072	domain = AMDGPU_GEM_DOMAIN_VRAM;	3050	domain = AMDGPU_GEM_DOMAIN_VRAM;
3073		3051
3074	r = amdgpu_bo_pin(rbo, domain, &afb->address);	3052	r = amdgpu_bo_pin(rbo, domain, &afb->address);
3075
3076	amdgpu_bo_unreserve(rbo);	3053	amdgpu_bo_unreserve(rbo);
3077		3054
3078	if (unlikely(r != 0)) {	3055	if (unlikely(r != 0)) {
@@ -3123,14 +3100,12 @@ static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, · 44 unmodified lines
3123	struct drm_plane_state *old_state)	3100	struct drm_plane_state *old_state)
3124	{	3101	{
3125	struct amdgpu_bo *rbo;	3102	struct amdgpu_bo *rbo;
3126	struct amdgpu_framebuffer *afb;
3127	int r;	3103	int r;
3128		3104
3129	if (!old_state->fb)	3105	if (!old_state->fb)
3130	return;	3106	return;
3131		3107
3132	afb = to_amdgpu_framebuffer(old_state->fb);	3108	rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
3133	rbo = gem_to_amdgpu_bo(afb->obj);
3134	r = amdgpu_bo_reserve(rbo, false);	3109	r = amdgpu_bo_reserve(rbo, false);
3135	if (unlikely(r)) {	3110	if (unlikely(r)) {
3136	DRM_ERROR("failed to reserve rbo before unpin\n");	3111	DRM_ERROR("failed to reserve rbo before unpin\n");
@@ -3773,7 +3748,7 @@ static void remove_stream(struct amdgpu_device *adev, · 636 unmodified lines
3773	static int get_cursor_position(struct drm_plane plane, struct drm_crtc crtc,	3748	static int get_cursor_position(struct drm_plane plane, struct drm_crtc crtc,
3774	struct dc_cursor_position *position)	3749	struct dc_cursor_position *position)
3775	{	3750	{
3776	struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);	3751	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3777	int x, y;	3752	int x, y;
3778	int xorigin = 0, yorigin = 0;	3753	int xorigin = 0, yorigin = 0;
3779		3754
@@ -3905,7 +3880,7 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc, · 125 unmodified lines
3905	int r, vpos, hpos;	3880	int r, vpos, hpos;
3906	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);	3881	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3907	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);	3882	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3908	struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);	3883	struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
3909	struct amdgpu_device *adev = crtc->dev->dev_private;	3884	struct amdgpu_device *adev = crtc->dev->dev_private;
3910	bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;	3885	bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
3911	struct dc_flip_addrs addr = { {0} };	3886	struct dc_flip_addrs addr = { {0} };
@@ -3986,6 +3961,96 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc, · 74 unmodified lines
3986	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);	3961	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3987	}	3962	}
3988		3963
		3964	/*
		3965	* TODO this whole function needs to go
		3966	*
		3967	* dc_surface_update is needlessly complex. See if we can just replace this
		3968	* with a dc_plane_state and follow the atomic model a bit more closely here.
		3969	*/
		3970	static bool commit_planes_to_stream(
		3971	struct dc *dc,
		3972	struct dc_plane_state **plane_states,
		3973	uint8_t new_plane_count,
		3974	struct dm_crtc_state *dm_new_crtc_state,
		3975	struct dm_crtc_state *dm_old_crtc_state,
		3976	struct dc_state *state)
		3977	{
		3978	/* no need to dynamically allocate this. it's pretty small */
		3979	struct dc_surface_update updates[MAX_SURFACES];
		3980	struct dc_flip_addrs *flip_addr;
		3981	struct dc_plane_info *plane_info;
		3982	struct dc_scaling_info *scaling_info;
		3983	int i;
		3984	struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
		3985	struct dc_stream_update *stream_update =
		3986	kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
		3987
		3988	if (!stream_update) {
		3989	BREAK_TO_DEBUGGER();
		3990	return false;
		3991	}
		3992
		3993	flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
		3994	GFP_KERNEL);
		3995	plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
		3996	GFP_KERNEL);
		3997	scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
		3998	GFP_KERNEL);
		3999
		4000	if (!flip_addr \|\| !plane_info \|\| !scaling_info) {
		4001	kfree(flip_addr);
		4002	kfree(plane_info);
		4003	kfree(scaling_info);
		4004	kfree(stream_update);
		4005	return false;
		4006	}
		4007
		4008	memset(updates, 0, sizeof(updates));
		4009
		4010	stream_update->src = dc_stream->src;
		4011	stream_update->dst = dc_stream->dst;
		4012	stream_update->out_transfer_func = dc_stream->out_transfer_func;
		4013
		4014	for (i = 0; i < new_plane_count; i++) {
		4015	updates[i].surface = plane_states[i];
		4016	updates[i].gamma =
		4017	(struct dc_gamma *)plane_states[i]->gamma_correction;
		4018	updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
		4019	flip_addr[i].address = plane_states[i]->address;
		4020	flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
		4021	plane_info[i].color_space = plane_states[i]->color_space;
		4022	plane_info[i].format = plane_states[i]->format;
		4023	plane_info[i].plane_size = plane_states[i]->plane_size;
		4024	plane_info[i].rotation = plane_states[i]->rotation;
		4025	plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
		4026	plane_info[i].stereo_format = plane_states[i]->stereo_format;
		4027	plane_info[i].tiling_info = plane_states[i]->tiling_info;
		4028	plane_info[i].visible = plane_states[i]->visible;
		4029	plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
		4030	plane_info[i].dcc = plane_states[i]->dcc;
		4031	scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
		4032	scaling_info[i].src_rect = plane_states[i]->src_rect;
		4033	scaling_info[i].dst_rect = plane_states[i]->dst_rect;
		4034	scaling_info[i].clip_rect = plane_states[i]->clip_rect;
		4035
		4036	updates[i].flip_addr = &flip_addr[i];
		4037	updates[i].plane_info = &plane_info[i];
		4038	updates[i].scaling_info = &scaling_info[i];
		4039	}
		4040
		4041	dc_commit_updates_for_stream(
		4042	dc,
		4043	updates,
		4044	new_plane_count,
		4045	dc_stream, stream_update, plane_states, state);
		4046
		4047	kfree(flip_addr);
		4048	kfree(plane_info);
		4049	kfree(scaling_info);
		4050	kfree(stream_update);
		4051	return true;
		4052	}
		4053
3989	static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,	4054	static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3990	struct drm_device *dev,	4055	struct drm_device *dev,
3991	struct amdgpu_display_manager *dm,	4056	struct amdgpu_display_manager *dm,
@@ -4001,6 +4066,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 9 unmodified lines
4001	struct drm_crtc_state *new_pcrtc_state =	4066	struct drm_crtc_state *new_pcrtc_state =
4002	drm_atomic_get_new_crtc_state(state, pcrtc);	4067	drm_atomic_get_new_crtc_state(state, pcrtc);
4003	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);	4068	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
		4069	struct dm_crtc_state *dm_old_crtc_state =
		4070	to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
4004	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);	4071	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4005	int planes_count = 0;	4072	int planes_count = 0;
4006	unsigned long flags;	4073	unsigned long flags;
@@ -4037,7 +4104,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 30 unmodified lines
4037	}	4104	}
4038	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);	4105	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4039		4106
4040	if (!pflip_needed) {	4107	if (!pflip_needed \|\| plane->type == DRM_PLANE_TYPE_OVERLAY) {
4041	WARN_ON(!dm_new_plane_state->dc_state);	4108	WARN_ON(!dm_new_plane_state->dc_state);
4042		4109
4043	plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;	4110	plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
@@ -4079,10 +4146,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 35 unmodified lines
4079	spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);	4146	spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4080	}	4147	}
4081		4148
4082	if (false == dc_commit_planes_to_stream(dm->dc,	4149
		4150	if (false == commit_planes_to_stream(dm->dc,
4083	plane_states_constructed,	4151	plane_states_constructed,
4084	planes_count,	4152	planes_count,
4085	dc_stream_attach,	4153	acrtc_state,
		4154	dm_old_crtc_state,
4086	dm_state->context))	4155	dm_state->context))
4087	dm_error("%s: Failed to attach plane!\n", __func__);	4156	dm_error("%s: Failed to attach plane!\n", __func__);
4088	} else {	4157	} else {
@@ -4307,8 +4376,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 218 unmodified lines
4307	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);	4376	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
4308	struct dc_stream_status *status = NULL;	4377	struct dc_stream_status *status = NULL;
4309		4378
4310	if (acrtc)	4379	if (acrtc) {
4311	new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);	4380	new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
		4381	old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
		4382	}
4312		4383
4313	/* Skip any modesets/resets */	4384	/* Skip any modesets/resets */
4314	if (!acrtc \|\| drm_atomic_crtc_needs_modeset(new_crtc_state))	4385	if (!acrtc \|\| drm_atomic_crtc_needs_modeset(new_crtc_state))
@@ -4331,11 +4402,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 16 unmodified lines
4331	WARN_ON(!status->plane_count);	4402	WARN_ON(!status->plane_count);
4332		4403
4333	/TODO How it works with MPO ?/	4404	/TODO How it works with MPO ?/
4334	if (!dc_commit_planes_to_stream(	4405	if (!commit_planes_to_stream(
4335	dm->dc,	4406	dm->dc,
4336	status->plane_states,	4407	status->plane_states,
4337	status->plane_count,	4408	status->plane_count,
4338	dm_new_crtc_state->stream,	4409	dm_new_crtc_state,
		4410	to_dm_crtc_state(old_crtc_state),
4339	dm_state->context))	4411	dm_state->context))
4340	dm_error("%s: Failed to update stream scaling!\n", __func__);	4412	dm_error("%s: Failed to update stream scaling!\n", __func__);
4341	}	4413	}
@@ -4578,7 +4650,7 @@ static int dm_update_crtcs_state(struct dc *dc, · 236 unmodified lines
4578	if (aconnector && enable) {	4650	if (aconnector && enable) {
4579	// Make sure fake sink is created in plug-in scenario	4651	// Make sure fake sink is created in plug-in scenario
4580	new_con_state = drm_atomic_get_connector_state(state,	4652	new_con_state = drm_atomic_get_connector_state(state,
4581	&aconnector->base);	4653	&aconnector->base);
4582		4654
4583	if (IS_ERR(new_con_state)) {	4655	if (IS_ERR(new_con_state)) {
4584	ret = PTR_ERR_OR_ZERO(new_con_state);	4656	ret = PTR_ERR_OR_ZERO(new_con_state);
@@ -4755,7 +4827,8 @@ static int dm_update_planes_state(struct dc *dc, · 170 unmodified lines
4755		4827
4756	/* Remove any changed/removed planes */	4828	/* Remove any changed/removed planes */
4757	if (!enable) {	4829	if (!enable) {
4758	if (pflip_needed)	4830	if (pflip_needed &&
		4831	plane->type != DRM_PLANE_TYPE_OVERLAY)
4759	continue;	4832	continue;
4760		4833
4761	if (!old_plane_crtc)	4834	if (!old_plane_crtc)
@@ -4802,7 +4875,8 @@ static int dm_update_planes_state(struct dc *dc, · 40 unmodified lines
4802	if (!dm_new_crtc_state->stream)	4875	if (!dm_new_crtc_state->stream)
4803	continue;	4876	continue;
4804		4877
4805	if (pflip_needed)	4878	if (pflip_needed &&
		4879	plane->type != DRM_PLANE_TYPE_OVERLAY)
4806	continue;	4880	continue;
4807		4881
4808	WARN_ON(dm_new_plane_state->dc_state);	4882	WARN_ON(dm_new_plane_state->dc_state);
@@ -5009,17 +5083,24 @@ void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, · 200 unmodified lines
5009	struct edid *edid)	5083	struct edid *edid)
5010	{	5084	{
5011	int i;	5085	int i;
5012	uint64_t val_capable;
5013	bool edid_check_required;	5086	bool edid_check_required;
5014	struct detailed_timing *timing;	5087	struct detailed_timing *timing;
5015	struct detailed_non_pixel *data;	5088	struct detailed_non_pixel *data;
5016	struct detailed_data_monitor_range *range;	5089	struct detailed_data_monitor_range *range;
5017	struct amdgpu_dm_connector *amdgpu_dm_connector =	5090	struct amdgpu_dm_connector *amdgpu_dm_connector =
5018	to_amdgpu_dm_connector(connector);	5091	to_amdgpu_dm_connector(connector);
		5092	struct dm_connector_state *dm_con_state;
5019		5093
5020	struct drm_device *dev = connector->dev;	5094	struct drm_device *dev = connector->dev;
5021	struct amdgpu_device *adev = dev->dev_private;	5095	struct amdgpu_device *adev = dev->dev_private;
5022		5096
		5097	if (!connector->state) {
		5098	DRM_ERROR("%s - Connector has no state", __func__);
		5099	return;
		5100	}
		5101
		5102	dm_con_state = to_dm_connector_state(connector->state);
		5103
5023	edid_check_required = false;	5104	edid_check_required = false;
5024	if (!amdgpu_dm_connector->dc_sink) {	5105	if (!amdgpu_dm_connector->dc_sink) {
5025	DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");	5106	DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
@@ -5038,7 +5119,7 @@ void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, · 12 unmodified lines
5038	amdgpu_dm_connector);	5119	amdgpu_dm_connector);
5039	}	5120	}
5040	}	5121	}
5041	val_capable = 0;	5122	dm_con_state->freesync_capable = false;
5042	if (edid_check_required == true && (edid->version > 1 \|\|	5123	if (edid_check_required == true && (edid->version > 1 \|\|
5043	(edid->version == 1 && edid->revision > 1))) {	5124	(edid->version == 1 && edid->revision > 1))) {
5044	for (i = 0; i < 4; i++) {	5125	for (i = 0; i < 4; i++) {
@@ -5074,7 +5155,7 @@ void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, · 29 unmodified lines
5074	amdgpu_dm_connector->min_vfreq * 1000000;	5155	amdgpu_dm_connector->min_vfreq * 1000000;
5075	amdgpu_dm_connector->caps.max_refresh_in_micro_hz =	5156	amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
5076	amdgpu_dm_connector->max_vfreq * 1000000;	5157	amdgpu_dm_connector->max_vfreq * 1000000;
5077	val_capable = 1;	5158	dm_con_state->freesync_capable = true;
5078	}	5159	}
5079	}	5160	}
5080		5161

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h+3−2

 #include <drm/drmP.h>
 #include <drm/drm_atomic.h>
-#include "dc.h"
 /*
  * This file contains the definition for amdgpu_display_manager
 struct amdgpu_device;
 struct drm_device;
 struct amdgpu_dm_irq_handler_data;
+struct dc;
 struct amdgpu_dm_prev_state {
 	struct drm_framebuffer *fb;
 	uint8_t underscan_hborder;
 	bool underscan_enable;
 	struct mod_freesync_user_enable user_enable;
+	bool freesync_capable;
 };
 #define to_dm_connector_state(x)\
 				     struct dc_link *link,
 				     int link_index);
-int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
+enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
 				   struct drm_display_mode *mode);
 void dm_restore_drm_connector_state(struct drm_device *dev,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c+1−0

@@ -25,6 +25,7 @@ · 24 unmodified lines
25		25
26	#include "amdgpu_mode.h"	26	#include "amdgpu_mode.h"
27	#include "amdgpu_dm.h"	27	#include "amdgpu_dm.h"
		28	#include "dc.h"
28	#include "modules/color/color_gamma.h"	29	#include "modules/color/color_gamma.h"
29		30
30	#define MAX_DRM_LUT_VALUE 0xFFFF	31	#define MAX_DRM_LUT_VALUE 0xFFFF

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+12−8

 	enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
 		I2C_MOT_TRUE : I2C_MOT_FALSE;
 	enum ddc_result res;
-	ssize_t read_bytes;
+	uint32_t read_bytes = msg->size;
 	if (WARN_ON(msg->size > 16))
 		return -E2BIG;
 	switch (msg->request & ~DP_AUX_I2C_MOT) {
 	case DP_AUX_NATIVE_READ:
-		read_bytes = dal_ddc_service_read_dpcd_data(
+		res = dal_ddc_service_read_dpcd_data(
 				TO_DM_AUX(aux)->ddc_service,
 				false,
 				I2C_MOT_UNDEF,
 				msg->address,
 				msg->buffer,
-				msg->size);
+				msg->size,
-		return read_bytes;
+				&read_bytes);
+		break;
 	case DP_AUX_NATIVE_WRITE:
 		res = dal_ddc_service_write_dpcd_data(
 				TO_DM_AUX(aux)->ddc_service,
 				msg->size);
 		break;
 	case DP_AUX_I2C_READ:
-		read_bytes = dal_ddc_service_read_dpcd_data(
+		res = dal_ddc_service_read_dpcd_data(
 				TO_DM_AUX(aux)->ddc_service,
 				true,
 				mot,
 				msg->address,
 				msg->buffer,
-				msg->size);
+				msg->size,
-		return read_bytes;
+				&read_bytes);
+		break;
 	case DP_AUX_I2C_WRITE:
 		res = dal_ddc_service_write_dpcd_data(
 				TO_DM_AUX(aux)->ddc_service,
 		 r == DDC_RESULT_SUCESSFULL);
 #endif
-	return msg->size;
+	if (res != DDC_RESULT_SUCESSFULL)
+		return -EIO;
+	return read_bytes;
 }
 static enum drm_connector_status

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c+11−2

@@ -37,8 +37,17 @@ · 36 unmodified lines
37		37
38	unsigned long long dm_get_timestamp(struct dc_context *ctx)	38	unsigned long long dm_get_timestamp(struct dc_context *ctx)
39	{	39	{
40	/* TODO: return actual timestamp */	40	struct timespec64 time;
41	return 0;	41
		42	getrawmonotonic64(&time);
		43	return timespec64_to_ns(&time);
		44	}
		45
		46	unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
		47	unsigned long long current_time_stamp,
		48	unsigned long long last_time_stamp)
		49	{
		50	return current_time_stamp - last_time_stamp;
42	}	51	}
43		52
44	void dm_perf_trace_timestamp(const char *func_name, unsigned int line)	53	void dm_perf_trace_timestamp(const char *func_name, unsigned int line)

drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c+79−79

@@ -26,13 +26,13 @@ · 25 unmodified lines
26	#include "dm_services.h"	26	#include "dm_services.h"
27	#include "include/fixed31_32.h"	27	#include "include/fixed31_32.h"
28		28
29	static inline uint64_t abs_i64(	29	static inline unsigned long long abs_i64(
30	int64_t arg)	30	long long arg)
31	{	31	{
32	if (arg > 0)	32	if (arg > 0)
33	return (uint64_t)arg;	33	return (unsigned long long)arg;
34	else	34	else
35	return (uint64_t)(-arg);	35	return (unsigned long long)(-arg);
36	}	36	}
37		37
38	/*	38	/*
@@ -40,12 +40,12 @@ static inline uint64_t abs_i64( · 1 unmodified line
40	* result = dividend / divisor	40	* result = dividend / divisor
41	* *remainder = dividend % divisor	41	* *remainder = dividend % divisor
42	*/	42	*/
43	static inline uint64_t complete_integer_division_u64(	43	static inline unsigned long long complete_integer_division_u64(
44	uint64_t dividend,	44	unsigned long long dividend,
45	uint64_t divisor,	45	unsigned long long divisor,
46	uint64_t *remainder)	46	unsigned long long *remainder)
47	{	47	{
48	uint64_t result;	48	unsigned long long result;
49		49
50	ASSERT(divisor);	50	ASSERT(divisor);
51		51
@@ -65,29 +65,29 @@ static inline uint64_t complete_integer_division_u64( · 13 unmodified lines
65	(FRACTIONAL_PART_MASK & (x))	65	(FRACTIONAL_PART_MASK & (x))
66		66
67	struct fixed31_32 dal_fixed31_32_from_fraction(	67	struct fixed31_32 dal_fixed31_32_from_fraction(
68	int64_t numerator,	68	long long numerator,
69	int64_t denominator)	69	long long denominator)
70	{	70	{
71	struct fixed31_32 res;	71	struct fixed31_32 res;
72		72
73	bool arg1_negative = numerator < 0;	73	bool arg1_negative = numerator < 0;
74	bool arg2_negative = denominator < 0;	74	bool arg2_negative = denominator < 0;
75		75
76	uint64_t arg1_value = arg1_negative ? -numerator : numerator;	76	unsigned long long arg1_value = arg1_negative ? -numerator : numerator;
77	uint64_t arg2_value = arg2_negative ? -denominator : denominator;	77	unsigned long long arg2_value = arg2_negative ? -denominator : denominator;
78		78
79	uint64_t remainder;	79	unsigned long long remainder;
80		80
81	/* determine integer part */	81	/* determine integer part */
82		82
83	uint64_t res_value = complete_integer_division_u64(	83	unsigned long long res_value = complete_integer_division_u64(
84	arg1_value, arg2_value, &remainder);	84	arg1_value, arg2_value, &remainder);
85		85
86	ASSERT(res_value <= LONG_MAX);	86	ASSERT(res_value <= LONG_MAX);
87		87
88	/* determine fractional part */	88	/* determine fractional part */
89	{	89	{
90	uint32_t i = FIXED31_32_BITS_PER_FRACTIONAL_PART;	90	unsigned int i = FIXED31_32_BITS_PER_FRACTIONAL_PART;
91		91
92	do {	92	do {
93	remainder <<= 1;	93	remainder <<= 1;
@@ -103,14 +103,14 @@ struct fixed31_32 dal_fixed31_32_from_fraction( · 9 unmodified lines
103		103
104	/* round up LSB */	104	/* round up LSB */
105	{	105	{
106	uint64_t summand = (remainder << 1) >= arg2_value;	106	unsigned long long summand = (remainder << 1) >= arg2_value;
107		107
108	ASSERT(res_value <= LLONG_MAX - summand);	108	ASSERT(res_value <= LLONG_MAX - summand);
109		109
110	res_value += summand;	110	res_value += summand;
111	}	111	}
112		112
113	res.value = (int64_t)res_value;	113	res.value = (long long)res_value;
114		114
115	if (arg1_negative ^ arg2_negative)	115	if (arg1_negative ^ arg2_negative)
116	res.value = -res.value;	116	res.value = -res.value;
@@ -119,7 +119,7 @@ struct fixed31_32 dal_fixed31_32_from_fraction( · 2 unmodified lines
119	}	119	}
120		120
121	struct fixed31_32 dal_fixed31_32_from_int_nonconst(	121	struct fixed31_32 dal_fixed31_32_from_int_nonconst(
122	int64_t arg)	122	long long arg)
123	{	123	{
124	struct fixed31_32 res;	124	struct fixed31_32 res;
125		125
@@ -132,7 +132,7 @@ struct fixed31_32 dal_fixed31_32_from_int_nonconst( · 6 unmodified lines
132		132
133	struct fixed31_32 dal_fixed31_32_shl(	133	struct fixed31_32 dal_fixed31_32_shl(
134	struct fixed31_32 arg,	134	struct fixed31_32 arg,
135	uint8_t shift)	135	unsigned char shift)
136	{	136	{
137	struct fixed31_32 res;	137	struct fixed31_32 res;
138		138
@@ -181,16 +181,16 @@ struct fixed31_32 dal_fixed31_32_mul( · 42 unmodified lines
181	bool arg1_negative = arg1.value < 0;	181	bool arg1_negative = arg1.value < 0;
182	bool arg2_negative = arg2.value < 0;	182	bool arg2_negative = arg2.value < 0;
183		183
184	uint64_t arg1_value = arg1_negative ? -arg1.value : arg1.value;	184	unsigned long long arg1_value = arg1_negative ? -arg1.value : arg1.value;
185	uint64_t arg2_value = arg2_negative ? -arg2.value : arg2.value;	185	unsigned long long arg2_value = arg2_negative ? -arg2.value : arg2.value;
186		186
187	uint64_t arg1_int = GET_INTEGER_PART(arg1_value);	187	unsigned long long arg1_int = GET_INTEGER_PART(arg1_value);
188	uint64_t arg2_int = GET_INTEGER_PART(arg2_value);	188	unsigned long long arg2_int = GET_INTEGER_PART(arg2_value);
189		189
190	uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);	190	unsigned long long arg1_fra = GET_FRACTIONAL_PART(arg1_value);
191	uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);	191	unsigned long long arg2_fra = GET_FRACTIONAL_PART(arg2_value);
192		192
193	uint64_t tmp;	193	unsigned long long tmp;
194		194
195	res.value = arg1_int * arg2_int;	195	res.value = arg1_int * arg2_int;
196		196
@@ -200,22 +200,22 @@ struct fixed31_32 dal_fixed31_32_mul( · 3 unmodified lines
200		200
201	tmp = arg1_int * arg2_fra;	201	tmp = arg1_int * arg2_fra;
202		202
203	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));	203	ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
204		204
205	res.value += tmp;	205	res.value += tmp;
206		206
207	tmp = arg2_int * arg1_fra;	207	tmp = arg2_int * arg1_fra;
208		208
209	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));	209	ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
210		210
211	res.value += tmp;	211	res.value += tmp;
212		212
213	tmp = arg1_fra * arg2_fra;	213	tmp = arg1_fra * arg2_fra;
214		214
215	tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +	215	tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
216	(tmp >= (uint64_t)dal_fixed31_32_half.value);	216	(tmp >= (unsigned long long)dal_fixed31_32_half.value);
217		217
218	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));	218	ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
219		219
220	res.value += tmp;	220	res.value += tmp;
221		221
@@ -230,13 +230,13 @@ struct fixed31_32 dal_fixed31_32_sqr( · 8 unmodified lines
230	{	230	{
231	struct fixed31_32 res;	231	struct fixed31_32 res;
232		232
233	uint64_t arg_value = abs_i64(arg.value);	233	unsigned long long arg_value = abs_i64(arg.value);
234		234
235	uint64_t arg_int = GET_INTEGER_PART(arg_value);	235	unsigned long long arg_int = GET_INTEGER_PART(arg_value);
236		236
237	uint64_t arg_fra = GET_FRACTIONAL_PART(arg_value);	237	unsigned long long arg_fra = GET_FRACTIONAL_PART(arg_value);
238		238
239	uint64_t tmp;	239	unsigned long long tmp;
240		240
241	res.value = arg_int * arg_int;	241	res.value = arg_int * arg_int;
242		242
@@ -246,20 +246,20 @@ struct fixed31_32 dal_fixed31_32_sqr( · 3 unmodified lines
246		246
247	tmp = arg_int * arg_fra;	247	tmp = arg_int * arg_fra;
248		248
249	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));	249	ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
250		250
251	res.value += tmp;	251	res.value += tmp;
252		252
253	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));	253	ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
254		254
255	res.value += tmp;	255	res.value += tmp;
256		256
257	tmp = arg_fra * arg_fra;	257	tmp = arg_fra * arg_fra;
258		258
259	tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +	259	tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
260	(tmp >= (uint64_t)dal_fixed31_32_half.value);	260	(tmp >= (unsigned long long)dal_fixed31_32_half.value);
261		261
262	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));	262	ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
263		263
264	res.value += tmp;	264	res.value += tmp;
265		265
@@ -288,7 +288,7 @@ struct fixed31_32 dal_fixed31_32_sinc( · 22 unmodified lines
288		288
289	struct fixed31_32 res = dal_fixed31_32_one;	289	struct fixed31_32 res = dal_fixed31_32_one;
290		290
291	int32_t n = 27;	291	int n = 27;
292		292
293	struct fixed31_32 arg_norm = arg;	293	struct fixed31_32 arg_norm = arg;
294		294
@@ -299,7 +299,7 @@ struct fixed31_32 dal_fixed31_32_sinc( · 4 unmodified lines
299	arg_norm,	299	arg_norm,
300	dal_fixed31_32_mul_int(	300	dal_fixed31_32_mul_int(
301	dal_fixed31_32_two_pi,	301	dal_fixed31_32_two_pi,
302	(int32_t)div64_s64(	302	(int)div64_s64(
303	arg_norm.value,	303	arg_norm.value,
304	dal_fixed31_32_two_pi.value)));	304	dal_fixed31_32_two_pi.value)));
305	}	305	}
@@ -343,7 +343,7 @@ struct fixed31_32 dal_fixed31_32_cos( · 37 unmodified lines
343		343
344	struct fixed31_32 res = dal_fixed31_32_one;	344	struct fixed31_32 res = dal_fixed31_32_one;
345		345
346	int32_t n = 26;	346	int n = 26;
347		347
348	do {	348	do {
349	res = dal_fixed31_32_sub(	349	res = dal_fixed31_32_sub(
@@ -370,7 +370,7 @@ struct fixed31_32 dal_fixed31_32_cos( · 20 unmodified lines
370	static struct fixed31_32 fixed31_32_exp_from_taylor_series(	370	static struct fixed31_32 fixed31_32_exp_from_taylor_series(
371	struct fixed31_32 arg)	371	struct fixed31_32 arg)
372	{	372	{
373	uint32_t n = 9;	373	unsigned int n = 9;
374		374
375	struct fixed31_32 res = dal_fixed31_32_from_fraction(	375	struct fixed31_32 res = dal_fixed31_32_from_fraction(
376	n + 2,	376	n + 2,
@@ -409,7 +409,7 @@ struct fixed31_32 dal_fixed31_32_exp( · 32 unmodified lines
409	if (dal_fixed31_32_le(	409	if (dal_fixed31_32_le(
410	dal_fixed31_32_ln2_div_2,	410	dal_fixed31_32_ln2_div_2,
411	dal_fixed31_32_abs(arg))) {	411	dal_fixed31_32_abs(arg))) {
412	int32_t m = dal_fixed31_32_round(	412	int m = dal_fixed31_32_round(
413	dal_fixed31_32_div(	413	dal_fixed31_32_div(
414	arg,	414	arg,
415	dal_fixed31_32_ln2));	415	dal_fixed31_32_ln2));
@@ -429,7 +429,7 @@ struct fixed31_32 dal_fixed31_32_exp( · 13 unmodified lines
429	if (m > 0)	429	if (m > 0)
430	return dal_fixed31_32_shl(	430	return dal_fixed31_32_shl(
431	fixed31_32_exp_from_taylor_series(r),	431	fixed31_32_exp_from_taylor_series(r),
432	(uint8_t)m);	432	(unsigned char)m);
433	else	433	else
434	return dal_fixed31_32_div_int(	434	return dal_fixed31_32_div_int(
435	fixed31_32_exp_from_taylor_series(r),	435	fixed31_32_exp_from_taylor_series(r),
@@ -482,50 +482,50 @@ struct fixed31_32 dal_fixed31_32_pow( · 46 unmodified lines
482	arg2));	482	arg2));
483	}	483	}
484		484
485	int32_t dal_fixed31_32_floor(	485	int dal_fixed31_32_floor(
486	struct fixed31_32 arg)	486	struct fixed31_32 arg)
487	{	487	{
488	uint64_t arg_value = abs_i64(arg.value);	488	unsigned long long arg_value = abs_i64(arg.value);
489		489
490	if (arg.value >= 0)	490	if (arg.value >= 0)
491	return (int32_t)GET_INTEGER_PART(arg_value);	491	return (int)GET_INTEGER_PART(arg_value);
492	else	492	else
493	return -(int32_t)GET_INTEGER_PART(arg_value);	493	return -(int)GET_INTEGER_PART(arg_value);
494	}	494	}
495		495
496	int32_t dal_fixed31_32_round(	496	int dal_fixed31_32_round(
497	struct fixed31_32 arg)	497	struct fixed31_32 arg)
498	{	498	{
499	uint64_t arg_value = abs_i64(arg.value);	499	unsigned long long arg_value = abs_i64(arg.value);
500		500
501	const int64_t summand = dal_fixed31_32_half.value;	501	const long long summand = dal_fixed31_32_half.value;
502		502
503	ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);	503	ASSERT(LLONG_MAX - (long long)arg_value >= summand);
504		504
505	arg_value += summand;	505	arg_value += summand;
506		506
507	if (arg.value >= 0)	507	if (arg.value >= 0)
508	return (int32_t)GET_INTEGER_PART(arg_value);	508	return (int)GET_INTEGER_PART(arg_value);
509	else	509	else
510	return -(int32_t)GET_INTEGER_PART(arg_value);	510	return -(int)GET_INTEGER_PART(arg_value);
511	}	511	}
512		512
513	int32_t dal_fixed31_32_ceil(	513	int dal_fixed31_32_ceil(
514	struct fixed31_32 arg)	514	struct fixed31_32 arg)
515	{	515	{
516	uint64_t arg_value = abs_i64(arg.value);	516	unsigned long long arg_value = abs_i64(arg.value);
517		517
518	const int64_t summand = dal_fixed31_32_one.value -	518	const long long summand = dal_fixed31_32_one.value -
519	dal_fixed31_32_epsilon.value;	519	dal_fixed31_32_epsilon.value;
520		520
521	ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);	521	ASSERT(LLONG_MAX - (long long)arg_value >= summand);
522		522
523	arg_value += summand;	523	arg_value += summand;
524		524
525	if (arg.value >= 0)	525	if (arg.value >= 0)
526	return (int32_t)GET_INTEGER_PART(arg_value);	526	return (int)GET_INTEGER_PART(arg_value);
527	else	527	else
528	return -(int32_t)GET_INTEGER_PART(arg_value);	528	return -(int)GET_INTEGER_PART(arg_value);
529	}	529	}
530		530
531	/* this function is a generic helper to translate fixed point value to	531	/* this function is a generic helper to translate fixed point value to
@@ -535,15 +535,15 @@ int32_t dal_fixed31_32_ceil( · 3 unmodified lines
535	* part in 32 bits. It is used in hw programming (scaler)	535	* part in 32 bits. It is used in hw programming (scaler)
536	*/	536	*/
537		537
538	static inline uint32_t ux_dy(	538	static inline unsigned int ux_dy(
539	int64_t value,	539	long long value,
540	uint32_t integer_bits,	540	unsigned int integer_bits,
541	uint32_t fractional_bits)	541	unsigned int fractional_bits)
542	{	542	{
543	/* 1. create mask of integer part */	543	/* 1. create mask of integer part */
544	uint32_t result = (1 << integer_bits) - 1;	544	unsigned int result = (1 << integer_bits) - 1;
545	/* 2. mask out fractional part */	545	/* 2. mask out fractional part */
546	uint32_t fractional_part = FRACTIONAL_PART_MASK & value;	546	unsigned int fractional_part = FRACTIONAL_PART_MASK & value;
547	/* 3. shrink fixed point integer part to be of integer_bits width*/	547	/* 3. shrink fixed point integer part to be of integer_bits width*/
548	result &= GET_INTEGER_PART(value);	548	result &= GET_INTEGER_PART(value);
549	/* 4. make space for fractional part to be filled in after integer */	549	/* 4. make space for fractional part to be filled in after integer */
@@ -554,13 +554,13 @@ static inline uint32_t ux_dy( · 4 unmodified lines
554	return result \| fractional_part;	554	return result \| fractional_part;
555	}	555	}
556		556
557	static inline uint32_t clamp_ux_dy(	557	static inline unsigned int clamp_ux_dy(
558	int64_t value,	558	long long value,
559	uint32_t integer_bits,	559	unsigned int integer_bits,
560	uint32_t fractional_bits,	560	unsigned int fractional_bits,
561	uint32_t min_clamp)	561	unsigned int min_clamp)
562	{	562	{
563	uint32_t truncated_val = ux_dy(value, integer_bits, fractional_bits);	563	unsigned int truncated_val = ux_dy(value, integer_bits, fractional_bits);
564		564
565	if (value >= (1LL << (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART)))	565	if (value >= (1LL << (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART)))
566	return (1 << (integer_bits + fractional_bits)) - 1;	566	return (1 << (integer_bits + fractional_bits)) - 1;
@@ -570,35 +570,35 @@ static inline uint32_t clamp_ux_dy( · 3 unmodified lines
570	return min_clamp;	570	return min_clamp;
571	}	571	}
572		572
573	uint32_t dal_fixed31_32_u2d19(	573	unsigned int dal_fixed31_32_u2d19(
574	struct fixed31_32 arg)	574	struct fixed31_32 arg)
575	{	575	{
576	return ux_dy(arg.value, 2, 19);	576	return ux_dy(arg.value, 2, 19);
577	}	577	}
578		578
579	uint32_t dal_fixed31_32_u0d19(	579	unsigned int dal_fixed31_32_u0d19(
580	struct fixed31_32 arg)	580	struct fixed31_32 arg)
581	{	581	{
582	return ux_dy(arg.value, 0, 19);	582	return ux_dy(arg.value, 0, 19);
583	}	583	}
584		584
585	uint32_t dal_fixed31_32_clamp_u0d14(	585	unsigned int dal_fixed31_32_clamp_u0d14(
586	struct fixed31_32 arg)	586	struct fixed31_32 arg)
587	{	587	{
588	return clamp_ux_dy(arg.value, 0, 14, 1);	588	return clamp_ux_dy(arg.value, 0, 14, 1);
589	}	589	}
590		590
591	uint32_t dal_fixed31_32_clamp_u0d10(	591	unsigned int dal_fixed31_32_clamp_u0d10(
592	struct fixed31_32 arg)	592	struct fixed31_32 arg)
593	{	593	{
594	return clamp_ux_dy(arg.value, 0, 10, 1);	594	return clamp_ux_dy(arg.value, 0, 10, 1);
595	}	595	}
596		596
597	int32_t dal_fixed31_32_s4d19(	597	int dal_fixed31_32_s4d19(
598	struct fixed31_32 arg)	598	struct fixed31_32 arg)
599	{	599	{
600	if (arg.value < 0)	600	if (arg.value < 0)
601	return -(int32_t)ux_dy(dal_fixed31_32_abs(arg).value, 4, 19);	601	return -(int)ux_dy(dal_fixed31_32_abs(arg).value, 4, 19);
602	else	602	else
603	return ux_dy(arg.value, 4, 19);	603	return ux_dy(arg.value, 4, 19);
604	}	604	}

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c+85−1

@@ -70,6 +70,10 @@ static enum bp_result get_firmware_info_v3_1( · 69 unmodified lines
70	struct bios_parser *bp,	70	struct bios_parser *bp,
71	struct dc_firmware_info *info);	71	struct dc_firmware_info *info);
72		72
		73	static enum bp_result get_firmware_info_v3_2(
		74	struct bios_parser *bp,
		75	struct dc_firmware_info *info);
		76
73	static struct atom_hpd_int_record get_hpd_record(struct bios_parser bp,	77	static struct atom_hpd_int_record get_hpd_record(struct bios_parser bp,
74	struct atom_display_object_path_v2 *object);	78	struct atom_display_object_path_v2 *object);
75		79
@@ -1321,9 +1325,11 @@ static enum bp_result bios_parser_get_firmware_info( · 1245 unmodified lines
1321	case 3:	1325	case 3:
1322	switch (revision.minor) {	1326	switch (revision.minor) {
1323	case 1:	1327	case 1:
1324	case 2:
1325	result = get_firmware_info_v3_1(bp, info);	1328	result = get_firmware_info_v3_1(bp, info);
1326	break;	1329	break;
		1330	case 2:
		1331	result = get_firmware_info_v3_2(bp, info);
		1332	break;
1327	default:	1333	default:
1328	break;	1334	break;
1329	}	1335	}
@@ -1383,6 +1389,84 @@ static enum bp_result get_firmware_info_v3_1( · 53 unmodified lines
1383	return BP_RESULT_OK;	1389	return BP_RESULT_OK;
1384	}	1390	}
1385		1391
		1392	static enum bp_result get_firmware_info_v3_2(
		1393	struct bios_parser *bp,
		1394	struct dc_firmware_info *info)
		1395	{
		1396	struct atom_firmware_info_v3_2 *firmware_info;
		1397	struct atom_display_controller_info_v4_1 *dce_info = NULL;
		1398	struct atom_common_table_header *header;
		1399	struct atom_data_revision revision;
		1400	struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
		1401	struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
		1402
		1403	if (!info)
		1404	return BP_RESULT_BADINPUT;
		1405
		1406	firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
		1407	DATA_TABLES(firmwareinfo));
		1408
		1409	dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
		1410	DATA_TABLES(dce_info));
		1411
		1412	if (!firmware_info \|\| !dce_info)
		1413	return BP_RESULT_BADBIOSTABLE;
		1414
		1415	memset(info, 0, sizeof(*info));
		1416
		1417	header = GET_IMAGE(struct atom_common_table_header,
		1418	DATA_TABLES(smu_info));
		1419	get_atom_data_table_revision(header, &revision);
		1420
		1421	if (revision.minor == 2) {
		1422	/* Vega12 */
		1423	smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
		1424	DATA_TABLES(smu_info));
		1425
		1426	if (!smu_info_v3_2)
		1427	return BP_RESULT_BADBIOSTABLE;
		1428
		1429	info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
		1430	} else if (revision.minor == 3) {
		1431	/* Vega20 */
		1432	smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
		1433	DATA_TABLES(smu_info));
		1434
		1435	if (!smu_info_v3_3)
		1436	return BP_RESULT_BADBIOSTABLE;
		1437
		1438	info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
		1439	}
		1440
		1441	// We need to convert from 10KHz units into KHz units.
		1442	info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
		1443
		1444	/* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
		1445	info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
		1446	/* Hardcode frequency if BIOS gives no DCE Ref Clk */
		1447	if (info->pll_info.crystal_frequency == 0) {
		1448	if (revision.minor == 2)
		1449	info->pll_info.crystal_frequency = 27000;
		1450	else if (revision.minor == 3)
		1451	info->pll_info.crystal_frequency = 100000;
		1452	}
		1453	/dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it/
		1454	info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
		1455	info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
		1456
		1457	/* Get GPU PLL VCO Clock */
		1458	if (bp->cmd_tbl.get_smu_clock_info != NULL) {
		1459	if (revision.minor == 2)
		1460	info->smu_gpu_pll_output_freq =
		1461	bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
		1462	else if (revision.minor == 3)
		1463	info->smu_gpu_pll_output_freq =
		1464	bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
		1465	}
		1466
		1467	return BP_RESULT_OK;
		1468	}
		1469
1386	static enum bp_result bios_parser_get_encoder_cap_info(	1470	static enum bp_result bios_parser_get_encoder_cap_info(
1387	struct dc_bios *dcb,	1471	struct dc_bios *dcb,
1388	struct graphics_object_id object_id,	1472	struct graphics_object_id object_id,

drivers/gpu/drm/amd/display/dc/bios/command_table.c+12−10

@@ -24,7 +24,7 @@ · 23 unmodified lines
24	*/	24	*/
25		25
26	#include "dm_services.h"	26	#include "dm_services.h"
27		27	#include "amdgpu.h"
28	#include "atom.h"	28	#include "atom.h"
29		29
30	#include "include/bios_parser_interface.h"	30	#include "include/bios_parser_interface.h"
@@ -35,16 +35,16 @@ · 4 unmodified lines
35	#include "bios_parser_types_internal.h"	35	#include "bios_parser_types_internal.h"
36		36
37	#define EXEC_BIOS_CMD_TABLE(command, params)\	37	#define EXEC_BIOS_CMD_TABLE(command, params)\
38	(cgs_atom_exec_cmd_table(bp->base.ctx->cgs_device, \	38	(amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
39	GetIndexIntoMasterTable(COMMAND, command), \	39	GetIndexIntoMasterTable(COMMAND, command), \
40	&params) == 0)	40	(uint32_t *)&params) == 0)
41		41
42	#define BIOS_CMD_TABLE_REVISION(command, frev, crev)\	42	#define BIOS_CMD_TABLE_REVISION(command, frev, crev)\
43	cgs_atom_get_cmd_table_revs(bp->base.ctx->cgs_device, \	43	amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
44	GetIndexIntoMasterTable(COMMAND, command), &frev, &crev)	44	GetIndexIntoMasterTable(COMMAND, command), &frev, &crev)
45		45
46	#define BIOS_CMD_TABLE_PARA_REVISION(command)\	46	#define BIOS_CMD_TABLE_PARA_REVISION(command)\
47	bios_cmd_table_para_revision(bp->base.ctx->cgs_device, \	47	bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
48	GetIndexIntoMasterTable(COMMAND, command))	48	GetIndexIntoMasterTable(COMMAND, command))
49		49
50	static void init_dig_encoder_control(struct bios_parser *bp);	50	static void init_dig_encoder_control(struct bios_parser *bp);
@@ -82,16 +82,18 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp) · 31 unmodified lines
82	init_set_dce_clock(bp);	82	init_set_dce_clock(bp);
83	}	83	}
84		84
85	static uint32_t bios_cmd_table_para_revision(void *cgs_device,	85	static uint32_t bios_cmd_table_para_revision(void *dev,
86	uint32_t index)	86	uint32_t index)
87	{	87	{
		88	struct amdgpu_device *adev = dev;
88	uint8_t frev, crev;	89	uint8_t frev, crev;
89		90
90	if (cgs_atom_get_cmd_table_revs(cgs_device,	91	if (amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context,
91	index,	92	index,
92	&frev, &crev) != 0)	93	&frev, &crev))
		94	return crev;
		95	else
93	return 0;	96	return 0;
94	return crev;
95	}	97	}
96		98
97	/*******************************************************************************	99	/*******************************************************************************
@@ -368,7 +370,7 @@ static void init_transmitter_control(struct bios_parser *bp) · 270 unmodified lines
368	uint8_t crev;	370	uint8_t crev;
369		371
370	if (BIOS_CMD_TABLE_REVISION(UNIPHYTransmitterControl,	372	if (BIOS_CMD_TABLE_REVISION(UNIPHYTransmitterControl,
371	frev, crev) != 0)	373	frev, crev) == false)
372	BREAK_TO_DEBUGGER();	374	BREAK_TO_DEBUGGER();
373	switch (crev) {	375	switch (crev) {
374	case 2:	376	case 2:

drivers/gpu/drm/amd/display/dc/bios/command_table2.c+16−10

 #include "dm_services.h"
 #include "ObjectID.h"
-#include "atomfirmware.h"
+#include "atomfirmware.h"
+#include "atom.h"
 #include "include/bios_parser_interface.h"
 #include "command_table2.h"
 #include "command_table_helper2.h"
 #include "bios_parser_helper.h"
 #include "bios_parser_types_internal2.h"
+#include "amdgpu.h"
 #define DC_LOGGER \
 	bp->base.ctx->logger
 		->FieldName)-(char *)0)/sizeof(uint16_t))
 #define EXEC_BIOS_CMD_TABLE(fname, params)\
-	(cgs_atom_exec_cmd_table(bp->base.ctx->cgs_device, \
+	(amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
 		GET_INDEX_INTO_MASTER_TABLE(command, fname), \
-		&params) == 0)
+		(uint32_t *)&params) == 0)
 #define BIOS_CMD_TABLE_REVISION(fname, frev, crev)\
-	cgs_atom_get_cmd_table_revs(bp->base.ctx->cgs_device, \
+	amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
 		GET_INDEX_INTO_MASTER_TABLE(command, fname), &frev, &crev)
 #define BIOS_CMD_TABLE_PARA_REVISION(fname)\
-	bios_cmd_table_para_revision(bp->base.ctx->cgs_device, \
+	bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
 			GET_INDEX_INTO_MASTER_TABLE(command, fname))
 static void init_dig_encoder_control(struct bios_parser *bp);
 	init_get_smu_clock_info(bp);
 }
-static uint32_t bios_cmd_table_para_revision(void *cgs_device,
+static uint32_t bios_cmd_table_para_revision(void *dev,
 					     uint32_t index)
 {
+	struct amdgpu_device *adev = dev;
 	uint8_t frev, crev;
-	if (cgs_atom_get_cmd_table_revs(cgs_device,
+	if (amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context,
 					index,
-					&frev, &crev) != 0)
+					&frev, &crev))
+		return crev;
+	else
 		return 0;
-	return crev;
 }
 /******************************************************************************
 	uint8_t frev;
 	uint8_t crev;
-	if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) != 0)
+	if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) == false)
 		BREAK_TO_DEBUGGER();
 	switch (crev) {
 	case 6:

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c+3−0

@@ -51,6 +51,9 @@ bool dal_bios_parser_init_cmd_tbl_helper( · 50 unmodified lines
51	return true;	51	return true;
52		52
53	case DCE_VERSION_11_2:	53	case DCE_VERSION_11_2:
		54	#if defined(CONFIG_DRM_AMD_DC_VEGAM)
		55	case DCE_VERSION_11_22:
		56	#endif
54	*h = dal_cmd_tbl_helper_dce112_get_table();	57	*h = dal_cmd_tbl_helper_dce112_get_table();
55	return true;	58	return true;
56		59

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c+3−0

 		return true;
 	case DCE_VERSION_11_2:
+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
+	case DCE_VERSION_11_22:
+#endif
 		*h = dal_cmd_tbl_helper_dce112_get_table2();
 		return true;
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)

drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h+579−0

@@ -0,0 +1,579 @@
	1	/*
	2	* Copyright 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef _CALCS_CALCS_LOGGER_H_
	27	#define _CALCS_CALCS_LOGGER_H_
	28	#define DC_LOGGER \
	29	logger
	30
	31	static void print_bw_calcs_dceip(struct dal_logger logger, const struct bw_calcs_dceip dceip)
	32	{
	33
	34	DC_LOG_BANDWIDTH_CALCS("#####################################################################");
	35	DC_LOG_BANDWIDTH_CALCS("struct bw_calcs_dceip");
	36	DC_LOG_BANDWIDTH_CALCS("#####################################################################");
	37	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_calcs_version version %d", dceip->version);
	38	DC_LOG_BANDWIDTH_CALCS(" [bool] large_cursor: %d", dceip->large_cursor);
	39	DC_LOG_BANDWIDTH_CALCS(" [bool] dmif_pipe_en_fbc_chunk_tracker: %d", dceip->dmif_pipe_en_fbc_chunk_tracker);
	40	DC_LOG_BANDWIDTH_CALCS(" [bool] display_write_back_supported: %d", dceip->display_write_back_supported);
	41	DC_LOG_BANDWIDTH_CALCS(" [bool] argb_compression_support: %d", dceip->argb_compression_support);
	42	DC_LOG_BANDWIDTH_CALCS(" [bool] pre_downscaler_enabled: %d", dceip->pre_downscaler_enabled);
	43	DC_LOG_BANDWIDTH_CALCS(" [bool] underlay_downscale_prefetch_enabled: %d",
	44	dceip->underlay_downscale_prefetch_enabled);
	45	DC_LOG_BANDWIDTH_CALCS(" [bool] graphics_lb_nodownscaling_multi_line_prefetching: %d",
	46	dceip->graphics_lb_nodownscaling_multi_line_prefetching);
	47	DC_LOG_BANDWIDTH_CALCS(" [bool] limit_excessive_outstanding_dmif_requests: %d",
	48	dceip->limit_excessive_outstanding_dmif_requests);
	49	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] cursor_max_outstanding_group_num: %d",
	50	dceip->cursor_max_outstanding_group_num);
	51	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] lines_interleaved_into_lb: %d", dceip->lines_interleaved_into_lb);
	52	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] low_power_tiling_mode: %d", dceip->low_power_tiling_mode);
	53	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] chunk_width: %d", dceip->chunk_width);
	54	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_graphics_pipes: %d", dceip->number_of_graphics_pipes);
	55	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_underlay_pipes: %d", dceip->number_of_underlay_pipes);
	56	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] max_dmif_buffer_allocated: %d", dceip->max_dmif_buffer_allocated);
	57	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] graphics_dmif_size: %d", dceip->graphics_dmif_size);
	58	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] underlay_luma_dmif_size: %d", dceip->underlay_luma_dmif_size);
	59	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] underlay_chroma_dmif_size: %d", dceip->underlay_chroma_dmif_size);
	60	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] scatter_gather_lines_of_pte_prefetching_in_linear_mode: %d",
	61	dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode);
	62	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] display_write_back420_luma_mcifwr_buffer_size: %d",
	63	dceip->display_write_back420_luma_mcifwr_buffer_size);
	64	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] display_write_back420_chroma_mcifwr_buffer_size: %d",
	65	dceip->display_write_back420_chroma_mcifwr_buffer_size);
	66	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] scatter_gather_pte_request_rows_in_tiling_mode: %d",
	67	dceip->scatter_gather_pte_request_rows_in_tiling_mode);
	68	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_vscaler_efficiency10_bit_per_component: %d",
	69	bw_fixed_to_int(dceip->underlay_vscaler_efficiency10_bit_per_component));
	70	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_vscaler_efficiency12_bit_per_component: %d",
	71	bw_fixed_to_int(dceip->underlay_vscaler_efficiency12_bit_per_component));
	72	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency6_bit_per_component: %d",
	73	bw_fixed_to_int(dceip->graphics_vscaler_efficiency6_bit_per_component));
	74	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency8_bit_per_component: %d",
	75	bw_fixed_to_int(dceip->graphics_vscaler_efficiency8_bit_per_component));
	76	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency10_bit_per_component: %d",
	77	bw_fixed_to_int(dceip->graphics_vscaler_efficiency10_bit_per_component));
	78	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency12_bit_per_component: %d",
	79	bw_fixed_to_int(dceip->graphics_vscaler_efficiency12_bit_per_component));
	80	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] alpha_vscaler_efficiency: %d",
	81	bw_fixed_to_int(dceip->alpha_vscaler_efficiency));
	82	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_write_pixels_per_dispclk: %d",
	83	bw_fixed_to_int(dceip->lb_write_pixels_per_dispclk));
	84	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_size_per_component444: %d",
	85	bw_fixed_to_int(dceip->lb_size_per_component444));
	86	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_and_dram_clock_state_change_gated_before_cursor: %d",
	87	bw_fixed_to_int(dceip->stutter_and_dram_clock_state_change_gated_before_cursor));
	88	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay420_luma_lb_size_per_component: %d",
	89	bw_fixed_to_int(dceip->underlay420_luma_lb_size_per_component));
	90	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay420_chroma_lb_size_per_component: %d",
	91	bw_fixed_to_int(dceip->underlay420_chroma_lb_size_per_component));
	92	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay422_lb_size_per_component: %d",
	93	bw_fixed_to_int(dceip->underlay422_lb_size_per_component));
	94	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_chunk_width: %d", bw_fixed_to_int(dceip->cursor_chunk_width));
	95	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_dcp_buffer_lines: %d",
	96	bw_fixed_to_int(dceip->cursor_dcp_buffer_lines));
	97	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_maximum_width_efficient_for_tiling: %d",
	98	bw_fixed_to_int(dceip->underlay_maximum_width_efficient_for_tiling));
	99	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_maximum_height_efficient_for_tiling: %d",
	100	bw_fixed_to_int(dceip->underlay_maximum_height_efficient_for_tiling));
	101	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display: %d",
	102	bw_fixed_to_int(dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display));
	103	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation: %d",
	104	bw_fixed_to_int(dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation));
	105	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] minimum_outstanding_pte_request_limit: %d",
	106	bw_fixed_to_int(dceip->minimum_outstanding_pte_request_limit));
	107	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_total_outstanding_pte_requests_allowed_by_saw: %d",
	108	bw_fixed_to_int(dceip->maximum_total_outstanding_pte_requests_allowed_by_saw));
	109	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] linear_mode_line_request_alternation_slice: %d",
	110	bw_fixed_to_int(dceip->linear_mode_line_request_alternation_slice));
	111	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] request_efficiency: %d", bw_fixed_to_int(dceip->request_efficiency));
	112	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_per_request: %d", bw_fixed_to_int(dceip->dispclk_per_request));
	113	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_ramping_factor: %d",
	114	bw_fixed_to_int(dceip->dispclk_ramping_factor));
	115	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_pipe_throughput_factor: %d",
	116	bw_fixed_to_int(dceip->display_pipe_throughput_factor));
	117	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_all_surfaces_burst_time: %d",
	118	bw_fixed_to_int(dceip->mcifwr_all_surfaces_burst_time));
	119	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_request_buffer_size: %d",
	120	bw_fixed_to_int(dceip->dmif_request_buffer_size));
	121
	122
	123	}
	124
	125	static void print_bw_calcs_vbios(struct dal_logger logger, const struct bw_calcs_vbios vbios)
	126	{
	127
	128	DC_LOG_BANDWIDTH_CALCS("#####################################################################");
	129	DC_LOG_BANDWIDTH_CALCS("struct bw_calcs_vbios vbios");
	130	DC_LOG_BANDWIDTH_CALCS("#####################################################################");
	131	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines memory_type: %d", vbios->memory_type);
	132	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines memory_type: %d", vbios->memory_type);
	133	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] dram_channel_width_in_bits: %d", vbios->dram_channel_width_in_bits);
	134	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_channels: %d", vbios->number_of_dram_channels);
	135	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_banks: %d", vbios->number_of_dram_banks);
	136	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_yclk: %d", bw_fixed_to_int(vbios->low_yclk));
	137	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid_yclk: %d", bw_fixed_to_int(vbios->mid_yclk));
	138	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_yclk: %d", bw_fixed_to_int(vbios->high_yclk));
	139	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_sclk: %d", bw_fixed_to_int(vbios->low_sclk));
	140	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid1_sclk: %d", bw_fixed_to_int(vbios->mid1_sclk));
	141	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid2_sclk: %d", bw_fixed_to_int(vbios->mid2_sclk));
	142	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid3_sclk: %d", bw_fixed_to_int(vbios->mid3_sclk));
	143	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid4_sclk: %d", bw_fixed_to_int(vbios->mid4_sclk));
	144	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid5_sclk: %d", bw_fixed_to_int(vbios->mid5_sclk));
	145	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid6_sclk: %d", bw_fixed_to_int(vbios->mid6_sclk));
	146	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_sclk: %d", bw_fixed_to_int(vbios->high_sclk));
	147	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_voltage_max_dispclk: %d",
	148	bw_fixed_to_int(vbios->low_voltage_max_dispclk));
	149	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid_voltage_max_dispclk;: %d",
	150	bw_fixed_to_int(vbios->mid_voltage_max_dispclk));
	151	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_voltage_max_dispclk;: %d",
	152	bw_fixed_to_int(vbios->high_voltage_max_dispclk));
	153	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_voltage_max_phyclk: %d",
	154	bw_fixed_to_int(vbios->low_voltage_max_phyclk));
	155	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid_voltage_max_phyclk: %d",
	156	bw_fixed_to_int(vbios->mid_voltage_max_phyclk));
	157	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_voltage_max_phyclk: %d",
	158	bw_fixed_to_int(vbios->high_voltage_max_phyclk));
	159	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] data_return_bus_width: %d", bw_fixed_to_int(vbios->data_return_bus_width));
	160	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] trc: %d", bw_fixed_to_int(vbios->trc));
	161	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmifmc_urgent_latency: %d", bw_fixed_to_int(vbios->dmifmc_urgent_latency));
	162	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_self_refresh_exit_latency: %d",
	163	bw_fixed_to_int(vbios->stutter_self_refresh_exit_latency));
	164	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_self_refresh_entry_latency: %d",
	165	bw_fixed_to_int(vbios->stutter_self_refresh_entry_latency));
	166	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_change_latency: %d",
	167	bw_fixed_to_int(vbios->nbp_state_change_latency));
	168	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwrmc_urgent_latency: %d",
	169	bw_fixed_to_int(vbios->mcifwrmc_urgent_latency));
	170	DC_LOG_BANDWIDTH_CALCS(" [bool] scatter_gather_enable: %d", vbios->scatter_gather_enable);
	171	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] down_spread_percentage: %d",
	172	bw_fixed_to_int(vbios->down_spread_percentage));
	173	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] cursor_width: %d", vbios->cursor_width);
	174	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] average_compression_rate: %d", vbios->average_compression_rate);
	175	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_request_slots_gmc_reserves_for_dmif_per_channel: %d",
	176	vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel);
	177	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] blackout_duration: %d", bw_fixed_to_int(vbios->blackout_duration));
	178	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_blackout_recovery_time: %d",
	179	bw_fixed_to_int(vbios->maximum_blackout_recovery_time));
	180
	181
	182	}
	183
	184	static void print_bw_calcs_data(struct dal_logger logger, struct bw_calcs_data data)
	185	{
	186
	187	int i, j, k;
	188
	189	DC_LOG_BANDWIDTH_CALCS("#####################################################################");
	190	DC_LOG_BANDWIDTH_CALCS("struct bw_calcs_data data");
	191	DC_LOG_BANDWIDTH_CALCS("#####################################################################");
	192	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_displays: %d", data->number_of_displays);
	193	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines underlay_surface_type: %d", data->underlay_surface_type);
	194	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines panning_and_bezel_adjustment: %d",
	195	data->panning_and_bezel_adjustment);
	196	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines graphics_tiling_mode: %d", data->graphics_tiling_mode);
	197	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] graphics_lb_bpc: %d", data->graphics_lb_bpc);
	198	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] underlay_lb_bpc: %d", data->underlay_lb_bpc);
	199	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines underlay_tiling_mode: %d", data->underlay_tiling_mode);
	200	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines d0_underlay_mode: %d", data->d0_underlay_mode);
	201	DC_LOG_BANDWIDTH_CALCS(" [bool] d1_display_write_back_dwb_enable: %d", data->d1_display_write_back_dwb_enable);
	202	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines d1_underlay_mode: %d", data->d1_underlay_mode);
	203	DC_LOG_BANDWIDTH_CALCS(" [bool] cpup_state_change_enable: %d", data->cpup_state_change_enable);
	204	DC_LOG_BANDWIDTH_CALCS(" [bool] cpuc_state_change_enable: %d", data->cpuc_state_change_enable);
	205	DC_LOG_BANDWIDTH_CALCS(" [bool] nbp_state_change_enable: %d", data->nbp_state_change_enable);
	206	DC_LOG_BANDWIDTH_CALCS(" [bool] stutter_mode_enable: %d", data->stutter_mode_enable);
	207	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] y_clk_level: %d", data->y_clk_level);
	208	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] sclk_level: %d", data->sclk_level);
	209	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_underlay_surfaces: %d", data->number_of_underlay_surfaces);
	210	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_wrchannels: %d", data->number_of_dram_wrchannels);
	211	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] chunk_request_delay: %d", data->chunk_request_delay);
	212	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_channels: %d", data->number_of_dram_channels);
	213	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines underlay_micro_tile_mode: %d", data->underlay_micro_tile_mode);
	214	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines graphics_micro_tile_mode: %d", data->graphics_micro_tile_mode);
	215	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] max_phyclk: %d", bw_fixed_to_int(data->max_phyclk));
	216	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_efficiency: %d", bw_fixed_to_int(data->dram_efficiency));
	217	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_width_after_surface_type: %d",
	218	bw_fixed_to_int(data->src_width_after_surface_type));
	219	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_height_after_surface_type: %d",
	220	bw_fixed_to_int(data->src_height_after_surface_type));
	221	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr_after_surface_type: %d",
	222	bw_fixed_to_int(data->hsr_after_surface_type));
	223	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr_after_surface_type: %d", bw_fixed_to_int(data->vsr_after_surface_type));
	224	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_width_after_rotation: %d",
	225	bw_fixed_to_int(data->src_width_after_rotation));
	226	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_height_after_rotation: %d",
	227	bw_fixed_to_int(data->src_height_after_rotation));
	228	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr_after_rotation: %d", bw_fixed_to_int(data->hsr_after_rotation));
	229	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr_after_rotation: %d", bw_fixed_to_int(data->vsr_after_rotation));
	230	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_height_pixels: %d", bw_fixed_to_int(data->source_height_pixels));
	231	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr_after_stereo: %d", bw_fixed_to_int(data->hsr_after_stereo));
	232	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr_after_stereo: %d", bw_fixed_to_int(data->vsr_after_stereo));
	233	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_width_in_lb: %d", bw_fixed_to_int(data->source_width_in_lb));
	234	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_line_pitch: %d", bw_fixed_to_int(data->lb_line_pitch));
	235	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_maximum_source_efficient_for_tiling: %d",
	236	bw_fixed_to_int(data->underlay_maximum_source_efficient_for_tiling));
	237	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] num_lines_at_frame_start: %d",
	238	bw_fixed_to_int(data->num_lines_at_frame_start));
	239	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_dmif_size_in_time: %d", bw_fixed_to_int(data->min_dmif_size_in_time));
	240	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_mcifwr_size_in_time: %d",
	241	bw_fixed_to_int(data->min_mcifwr_size_in_time));
	242	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_requests_for_dmif_size: %d",
	243	bw_fixed_to_int(data->total_requests_for_dmif_size));
	244	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] peak_pte_request_to_eviction_ratio_limiting: %d",
	245	bw_fixed_to_int(data->peak_pte_request_to_eviction_ratio_limiting));
	246	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] useful_pte_per_pte_request: %d",
	247	bw_fixed_to_int(data->useful_pte_per_pte_request));
	248	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_request_rows: %d",
	249	bw_fixed_to_int(data->scatter_gather_pte_request_rows));
	250	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_row_height: %d",
	251	bw_fixed_to_int(data->scatter_gather_row_height));
	252	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_requests_in_vblank: %d",
	253	bw_fixed_to_int(data->scatter_gather_pte_requests_in_vblank));
	254	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] inefficient_linear_pitch_in_bytes: %d",
	255	bw_fixed_to_int(data->inefficient_linear_pitch_in_bytes));
	256	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_total_data: %d", bw_fixed_to_int(data->cursor_total_data));
	257	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_total_request_groups: %d",
	258	bw_fixed_to_int(data->cursor_total_request_groups));
	259	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_total_pte_requests: %d",
	260	bw_fixed_to_int(data->scatter_gather_total_pte_requests));
	261	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_total_pte_request_groups: %d",
	262	bw_fixed_to_int(data->scatter_gather_total_pte_request_groups));
	263	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] tile_width_in_pixels: %d", bw_fixed_to_int(data->tile_width_in_pixels));
	264	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_total_number_of_data_request_page_close_open: %d",
	265	bw_fixed_to_int(data->dmif_total_number_of_data_request_page_close_open));
	266	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_total_number_of_data_request_page_close_open: %d",
	267	bw_fixed_to_int(data->mcifwr_total_number_of_data_request_page_close_open));
	268	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] bytes_per_page_close_open: %d",
	269	bw_fixed_to_int(data->bytes_per_page_close_open));
	270	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_total_page_close_open_time: %d",
	271	bw_fixed_to_int(data->mcifwr_total_page_close_open_time));
	272	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_requests_for_adjusted_dmif_size: %d",
	273	bw_fixed_to_int(data->total_requests_for_adjusted_dmif_size));
	274	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dmifmc_urgent_trips: %d",
	275	bw_fixed_to_int(data->total_dmifmc_urgent_trips));
	276	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dmifmc_urgent_latency: %d",
	277	bw_fixed_to_int(data->total_dmifmc_urgent_latency));
	278	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_reads_required_data: %d",
	279	bw_fixed_to_int(data->total_display_reads_required_data));
	280	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_reads_required_dram_access_data: %d",
	281	bw_fixed_to_int(data->total_display_reads_required_dram_access_data));
	282	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_writes_required_data: %d",
	283	bw_fixed_to_int(data->total_display_writes_required_data));
	284	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_writes_required_dram_access_data: %d",
	285	bw_fixed_to_int(data->total_display_writes_required_dram_access_data));
	286	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_required_data: %d",
	287	bw_fixed_to_int(data->display_reads_required_data));
	288	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_required_dram_access_data: %d",
	289	bw_fixed_to_int(data->display_reads_required_dram_access_data));
	290	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_total_page_close_open_time: %d",
	291	bw_fixed_to_int(data->dmif_total_page_close_open_time));
	292	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_cursor_memory_interface_buffer_size_in_time: %d",
	293	bw_fixed_to_int(data->min_cursor_memory_interface_buffer_size_in_time));
	294	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_read_buffer_size_in_time: %d",
	295	bw_fixed_to_int(data->min_read_buffer_size_in_time));
	296	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_time_for_data_transfer: %d",
	297	bw_fixed_to_int(data->display_reads_time_for_data_transfer));
	298	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_writes_time_for_data_transfer: %d",
	299	bw_fixed_to_int(data->display_writes_time_for_data_transfer));
	300	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_required_dram_bandwidth: %d",
	301	bw_fixed_to_int(data->dmif_required_dram_bandwidth));
	302	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_required_dram_bandwidth: %d",
	303	bw_fixed_to_int(data->mcifwr_required_dram_bandwidth));
	304	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_dmifmc_urgent_latency_for_page_close_open: %d",
	305	bw_fixed_to_int(data->required_dmifmc_urgent_latency_for_page_close_open));
	306	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_mcifmcwr_urgent_latency: %d",
	307	bw_fixed_to_int(data->required_mcifmcwr_urgent_latency));
	308	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_dram_bandwidth_gbyte_per_second: %d",
	309	bw_fixed_to_int(data->required_dram_bandwidth_gbyte_per_second));
	310	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_bandwidth: %d", bw_fixed_to_int(data->dram_bandwidth));
	311	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_required_sclk: %d", bw_fixed_to_int(data->dmif_required_sclk));
	312	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_required_sclk: %d", bw_fixed_to_int(data->mcifwr_required_sclk));
	313	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_sclk: %d", bw_fixed_to_int(data->required_sclk));
	314	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] downspread_factor: %d", bw_fixed_to_int(data->downspread_factor));
	315	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_scaler_efficiency: %d", bw_fixed_to_int(data->v_scaler_efficiency));
	316	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scaler_limits_factor: %d", bw_fixed_to_int(data->scaler_limits_factor));
	317	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_pipe_pixel_throughput: %d",
	318	bw_fixed_to_int(data->display_pipe_pixel_throughput));
	319	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_with_ramping: %d",
	320	bw_fixed_to_int(data->total_dispclk_required_with_ramping));
	321	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_without_ramping: %d",
	322	bw_fixed_to_int(data->total_dispclk_required_without_ramping));
	323	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_read_request_bandwidth: %d",
	324	bw_fixed_to_int(data->total_read_request_bandwidth));
	325	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_write_request_bandwidth: %d",
	326	bw_fixed_to_int(data->total_write_request_bandwidth));
	327	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_total_read_request_bandwidth: %d",
	328	bw_fixed_to_int(data->dispclk_required_for_total_read_request_bandwidth));
	329	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_with_ramping_with_request_bandwidth: %d",
	330	bw_fixed_to_int(data->total_dispclk_required_with_ramping_with_request_bandwidth));
	331	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_without_ramping_with_request_bandwidth: %d",
	332	bw_fixed_to_int(data->total_dispclk_required_without_ramping_with_request_bandwidth));
	333	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk: %d", bw_fixed_to_int(data->dispclk));
	334	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] blackout_recovery_time: %d", bw_fixed_to_int(data->blackout_recovery_time));
	335	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_pixels_per_data_fifo_entry: %d",
	336	bw_fixed_to_int(data->min_pixels_per_data_fifo_entry));
	337	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] sclk_deep_sleep: %d", bw_fixed_to_int(data->sclk_deep_sleep));
	338	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] chunk_request_time: %d", bw_fixed_to_int(data->chunk_request_time));
	339	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_request_time: %d", bw_fixed_to_int(data->cursor_request_time));
	340	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] line_source_pixels_transfer_time: %d",
	341	bw_fixed_to_int(data->line_source_pixels_transfer_time));
	342	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmifdram_access_efficiency: %d",
	343	bw_fixed_to_int(data->dmifdram_access_efficiency));
	344	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwrdram_access_efficiency: %d",
	345	bw_fixed_to_int(data->mcifwrdram_access_efficiency));
	346	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_average_bandwidth_no_compression: %d",
	347	bw_fixed_to_int(data->total_average_bandwidth_no_compression));
	348	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_average_bandwidth: %d",
	349	bw_fixed_to_int(data->total_average_bandwidth));
	350	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_stutter_cycle_duration: %d",
	351	bw_fixed_to_int(data->total_stutter_cycle_duration));
	352	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_burst_time: %d", bw_fixed_to_int(data->stutter_burst_time));
	353	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] time_in_self_refresh: %d", bw_fixed_to_int(data->time_in_self_refresh));
	354	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_efficiency: %d", bw_fixed_to_int(data->stutter_efficiency));
	355	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] worst_number_of_trips_to_memory: %d",
	356	bw_fixed_to_int(data->worst_number_of_trips_to_memory));
	357	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] immediate_flip_time: %d", bw_fixed_to_int(data->immediate_flip_time));
	358	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] latency_for_non_dmif_clients: %d",
	359	bw_fixed_to_int(data->latency_for_non_dmif_clients));
	360	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] latency_for_non_mcifwr_clients: %d",
	361	bw_fixed_to_int(data->latency_for_non_mcifwr_clients));
	362	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmifmc_urgent_latency_supported_in_high_sclk_and_yclk: %d",
	363	bw_fixed_to_int(data->dmifmc_urgent_latency_supported_in_high_sclk_and_yclk));
	364	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_dram_speed_change_margin: %d",
	365	bw_fixed_to_int(data->nbp_state_dram_speed_change_margin));
	366	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_time_for_data_transfer_and_urgent_latency: %d",
	367	bw_fixed_to_int(data->display_reads_time_for_data_transfer_and_urgent_latency));
	368	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_speed_change_margin: %d",
	369	bw_fixed_to_int(data->dram_speed_change_margin));
	370	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_vblank_dram_speed_change_margin: %d",
	371	bw_fixed_to_int(data->min_vblank_dram_speed_change_margin));
	372	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_stutter_refresh_duration: %d",
	373	bw_fixed_to_int(data->min_stutter_refresh_duration));
	374	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] total_stutter_dmif_buffer_size: %d", data->total_stutter_dmif_buffer_size);
	375	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] total_bytes_requested: %d", data->total_bytes_requested);
	376	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] min_stutter_dmif_buffer_size: %d", data->min_stutter_dmif_buffer_size);
	377	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] num_stutter_bursts: %d", data->num_stutter_bursts);
	378	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_blank_nbp_state_dram_speed_change_latency_supported: %d",
	379	bw_fixed_to_int(data->v_blank_nbp_state_dram_speed_change_latency_supported));
	380	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_dram_speed_change_latency_supported: %d",
	381	bw_fixed_to_int(data->nbp_state_dram_speed_change_latency_supported));
	382
	383	for (i = 0; i < maximum_number_of_surfaces; i++) {
	384	DC_LOG_BANDWIDTH_CALCS(" [bool] fbc_en[%d]:%d\n", i, data->fbc_en[i]);
	385	DC_LOG_BANDWIDTH_CALCS(" [bool] lpt_en[%d]:%d", i, data->lpt_en[i]);
	386	DC_LOG_BANDWIDTH_CALCS(" [bool] displays_match_flag[%d]:%d", i, data->displays_match_flag[i]);
	387	DC_LOG_BANDWIDTH_CALCS(" [bool] use_alpha[%d]:%d", i, data->use_alpha[i]);
	388	DC_LOG_BANDWIDTH_CALCS(" [bool] orthogonal_rotation[%d]:%d", i, data->orthogonal_rotation[i]);
	389	DC_LOG_BANDWIDTH_CALCS(" [bool] enable[%d]:%d", i, data->enable[i]);
	390	DC_LOG_BANDWIDTH_CALCS(" [bool] access_one_channel_only[%d]:%d", i, data->access_one_channel_only[i]);
	391	DC_LOG_BANDWIDTH_CALCS(" [bool] scatter_gather_enable_for_pipe[%d]:%d",
	392	i, data->scatter_gather_enable_for_pipe[i]);
	393	DC_LOG_BANDWIDTH_CALCS(" [bool] interlace_mode[%d]:%d",
	394	i, data->interlace_mode[i]);
	395	DC_LOG_BANDWIDTH_CALCS(" [bool] display_pstate_change_enable[%d]:%d",
	396	i, data->display_pstate_change_enable[i]);
	397	DC_LOG_BANDWIDTH_CALCS(" [bool] line_buffer_prefetch[%d]:%d", i, data->line_buffer_prefetch[i]);
	398	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] bytes_per_pixel[%d]:%d", i, data->bytes_per_pixel[i]);
	399	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] max_chunks_non_fbc_mode[%d]:%d",
	400	i, data->max_chunks_non_fbc_mode[i]);
	401	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] lb_bpc[%d]:%d", i, data->lb_bpc[i]);
	402	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bpphdmi[%d]:%d", i, data->output_bpphdmi[i]);
	403	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bppdp4_lane_hbr[%d]:%d", i, data->output_bppdp4_lane_hbr[i]);
	404	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bppdp4_lane_hbr2[%d]:%d",
	405	i, data->output_bppdp4_lane_hbr2[i]);
	406	DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bppdp4_lane_hbr3[%d]:%d",
	407	i, data->output_bppdp4_lane_hbr3[i]);
	408	DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines stereo_mode[%d]:%d", i, data->stereo_mode[i]);
	409	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_buffer_transfer_time[%d]:%d",
	410	i, bw_fixed_to_int(data->dmif_buffer_transfer_time[i]));
	411	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] displays_with_same_mode[%d]:%d",
	412	i, bw_fixed_to_int(data->displays_with_same_mode[i]));
	413	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_dmif_buffer_size[%d]:%d",
	414	i, bw_fixed_to_int(data->stutter_dmif_buffer_size[i]));
	415	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_refresh_duration[%d]:%d",
	416	i, bw_fixed_to_int(data->stutter_refresh_duration[i]));
	417	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_exit_watermark[%d]:%d",
	418	i, bw_fixed_to_int(data->stutter_exit_watermark[i]));
	419	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_entry_watermark[%d]:%d",
	420	i, bw_fixed_to_int(data->stutter_entry_watermark[i]));
	421	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_total[%d]:%d", i, bw_fixed_to_int(data->h_total[i]));
	422	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_total[%d]:%d", i, bw_fixed_to_int(data->v_total[i]));
	423	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pixel_rate[%d]:%d", i, bw_fixed_to_int(data->pixel_rate[i]));
	424	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_width[%d]:%d", i, bw_fixed_to_int(data->src_width[i]));
	425	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pitch_in_pixels[%d]:%d",
	426	i, bw_fixed_to_int(data->pitch_in_pixels[i]));
	427	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pitch_in_pixels_after_surface_type[%d]:%d",
	428	i, bw_fixed_to_int(data->pitch_in_pixels_after_surface_type[i]));
	429	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_height[%d]:%d", i, bw_fixed_to_int(data->src_height[i]));
	430	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scale_ratio[%d]:%d", i, bw_fixed_to_int(data->scale_ratio[i]));
	431	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_taps[%d]:%d", i, bw_fixed_to_int(data->h_taps[i]));
	432	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_taps[%d]:%d", i, bw_fixed_to_int(data->v_taps[i]));
	433	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_scale_ratio[%d]:%d", i, bw_fixed_to_int(data->h_scale_ratio[i]));
	434	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_scale_ratio[%d]:%d", i, bw_fixed_to_int(data->v_scale_ratio[i]));
	435	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] rotation_angle[%d]:%d",
	436	i, bw_fixed_to_int(data->rotation_angle[i]));
	437	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] compression_rate[%d]:%d",
	438	i, bw_fixed_to_int(data->compression_rate[i]));
	439	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr[%d]:%d", i, bw_fixed_to_int(data->hsr[i]));
	440	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr[%d]:%d", i, bw_fixed_to_int(data->vsr[i]));
	441	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_width_rounded_up_to_chunks[%d]:%d",
	442	i, bw_fixed_to_int(data->source_width_rounded_up_to_chunks[i]));
	443	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_width_pixels[%d]:%d",
	444	i, bw_fixed_to_int(data->source_width_pixels[i]));
	445	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_height_rounded_up_to_chunks[%d]:%d",
	446	i, bw_fixed_to_int(data->source_height_rounded_up_to_chunks[i]));
	447	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_bandwidth[%d]:%d",
	448	i, bw_fixed_to_int(data->display_bandwidth[i]));
	449	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] request_bandwidth[%d]:%d",
	450	i, bw_fixed_to_int(data->request_bandwidth[i]));
	451	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] bytes_per_request[%d]:%d",
	452	i, bw_fixed_to_int(data->bytes_per_request[i]));
	453	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] useful_bytes_per_request[%d]:%d",
	454	i, bw_fixed_to_int(data->useful_bytes_per_request[i]));
	455	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lines_interleaved_in_mem_access[%d]:%d",
	456	i, bw_fixed_to_int(data->lines_interleaved_in_mem_access[i]));
	457	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] latency_hiding_lines[%d]:%d",
	458	i, bw_fixed_to_int(data->latency_hiding_lines[i]));
	459	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_partitions[%d]:%d",
	460	i, bw_fixed_to_int(data->lb_partitions[i]));
	461	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_partitions_max[%d]:%d",
	462	i, bw_fixed_to_int(data->lb_partitions_max[i]));
	463	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_with_ramping[%d]:%d",
	464	i, bw_fixed_to_int(data->dispclk_required_with_ramping[i]));
	465	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_without_ramping[%d]:%d",
	466	i, bw_fixed_to_int(data->dispclk_required_without_ramping[i]));
	467	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] data_buffer_size[%d]:%d",
	468	i, bw_fixed_to_int(data->data_buffer_size[i]));
	469	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] outstanding_chunk_request_limit[%d]:%d",
	470	i, bw_fixed_to_int(data->outstanding_chunk_request_limit[i]));
	471	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] urgent_watermark[%d]:%d",
	472	i, bw_fixed_to_int(data->urgent_watermark[i]));
	473	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_change_watermark[%d]:%d",
	474	i, bw_fixed_to_int(data->nbp_state_change_watermark[i]));
	475	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_filter_init[%d]:%d", i, bw_fixed_to_int(data->v_filter_init[i]));
	476	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_cycle_duration[%d]:%d",
	477	i, bw_fixed_to_int(data->stutter_cycle_duration[i]));
	478	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] average_bandwidth[%d]:%d",
	479	i, bw_fixed_to_int(data->average_bandwidth[i]));
	480	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] average_bandwidth_no_compression[%d]:%d",
	481	i, bw_fixed_to_int(data->average_bandwidth_no_compression[i]));
	482	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_request_limit[%d]:%d",
	483	i, bw_fixed_to_int(data->scatter_gather_pte_request_limit[i]));
	484	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_size_per_component[%d]:%d",
	485	i, bw_fixed_to_int(data->lb_size_per_component[i]));
	486	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] memory_chunk_size_in_bytes[%d]:%d",
	487	i, bw_fixed_to_int(data->memory_chunk_size_in_bytes[i]));
	488	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pipe_chunk_size_in_bytes[%d]:%d",
	489	i, bw_fixed_to_int(data->pipe_chunk_size_in_bytes[i]));
	490	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] number_of_trips_to_memory_for_getting_apte_row[%d]:%d",
	491	i, bw_fixed_to_int(data->number_of_trips_to_memory_for_getting_apte_row[i]));
	492	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] adjusted_data_buffer_size[%d]:%d",
	493	i, bw_fixed_to_int(data->adjusted_data_buffer_size[i]));
	494	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] adjusted_data_buffer_size_in_memory[%d]:%d",
	495	i, bw_fixed_to_int(data->adjusted_data_buffer_size_in_memory[i]));
	496	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pixels_per_data_fifo_entry[%d]:%d",
	497	i, bw_fixed_to_int(data->pixels_per_data_fifo_entry[i]));
	498	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_requests_in_row[%d]:%d",
	499	i, bw_fixed_to_int(data->scatter_gather_pte_requests_in_row[i]));
	500	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pte_request_per_chunk[%d]:%d",
	501	i, bw_fixed_to_int(data->pte_request_per_chunk[i]));
	502	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_page_width[%d]:%d",
	503	i, bw_fixed_to_int(data->scatter_gather_page_width[i]));
	504	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_page_height[%d]:%d",
	505	i, bw_fixed_to_int(data->scatter_gather_page_height[i]));
	506	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_lines_in_per_line_out_in_beginning_of_frame[%d]:%d",
	507	i, bw_fixed_to_int(data->lb_lines_in_per_line_out_in_beginning_of_frame[i]));
	508	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_lines_in_per_line_out_in_middle_of_frame[%d]:%d",
	509	i, bw_fixed_to_int(data->lb_lines_in_per_line_out_in_middle_of_frame[i]));
	510	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_width_pixels[%d]:%d",
	511	i, bw_fixed_to_int(data->cursor_width_pixels[i]));
	512	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] minimum_latency_hiding[%d]:%d",
	513	i, bw_fixed_to_int(data->minimum_latency_hiding[i]));
	514	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_latency_hiding[%d]:%d",
	515	i, bw_fixed_to_int(data->maximum_latency_hiding[i]));
	516	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] minimum_latency_hiding_with_cursor[%d]:%d",
	517	i, bw_fixed_to_int(data->minimum_latency_hiding_with_cursor[i]));
	518	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_latency_hiding_with_cursor[%d]:%d",
	519	i, bw_fixed_to_int(data->maximum_latency_hiding_with_cursor[i]));
	520	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_pixels_for_first_output_pixel[%d]:%d",
	521	i, bw_fixed_to_int(data->src_pixels_for_first_output_pixel[i]));
	522	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_pixels_for_last_output_pixel[%d]:%d",
	523	i, bw_fixed_to_int(data->src_pixels_for_last_output_pixel[i]));
	524	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_data_for_first_output_pixel[%d]:%d",
	525	i, bw_fixed_to_int(data->src_data_for_first_output_pixel[i]));
	526	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_data_for_last_output_pixel[%d]:%d",
	527	i, bw_fixed_to_int(data->src_data_for_last_output_pixel[i]));
	528	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] active_time[%d]:%d", i, bw_fixed_to_int(data->active_time[i]));
	529	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] horizontal_blank_and_chunk_granularity_factor[%d]:%d",
	530	i, bw_fixed_to_int(data->horizontal_blank_and_chunk_granularity_factor[i]));
	531	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_latency_hiding[%d]:%d",
	532	i, bw_fixed_to_int(data->cursor_latency_hiding[i]));
	533	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_blank_dram_speed_change_margin[%d]:%d",
	534	i, bw_fixed_to_int(data->v_blank_dram_speed_change_margin[i]));
	535	}
	536
	537	for (i = 0; i < maximum_number_of_surfaces; i++) {
	538	for (j = 0; j < 3; j++) {
	539	for (k = 0; k < 8; k++) {
	540
	541	DC_LOG_BANDWIDTH_CALCS("\n [bw_fixed] line_source_transfer_time[%d][%d][%d]:%d",
	542	i, j, k, bw_fixed_to_int(data->line_source_transfer_time[i][j][k]));
	543	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_speed_change_line_source_transfer_time[%d][%d][%d]:%d",
	544	i, j, k,
	545	bw_fixed_to_int(data->dram_speed_change_line_source_transfer_time[i][j][k]));
	546	}
	547	}
	548	}
	549
	550	for (i = 0; i < 3; i++) {
	551	for (j = 0; j < 8; j++) {
	552
	553	DC_LOG_BANDWIDTH_CALCS("\n [uint32_t] num_displays_with_margin[%d][%d]:%d",
	554	i, j, data->num_displays_with_margin[i][j]);
	555	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_burst_time[%d][%d]:%d",
	556	i, j, bw_fixed_to_int(data->dmif_burst_time[i][j]));
	557	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_burst_time[%d][%d]:%d",
	558	i, j, bw_fixed_to_int(data->mcifwr_burst_time[i][j]));
	559	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_dram_speed_change_margin[%d][%d]:%d",
	560	i, j, bw_fixed_to_int(data->min_dram_speed_change_margin[i][j]));
	561	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_dram_speed_change[%d][%d]:%d",
	562	i, j, bw_fixed_to_int(data->dispclk_required_for_dram_speed_change[i][j]));
	563	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] blackout_duration_margin[%d][%d]:%d",
	564	i, j, bw_fixed_to_int(data->blackout_duration_margin[i][j]));
	565	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_blackout_duration[%d][%d]:%d",
	566	i, j, bw_fixed_to_int(data->dispclk_required_for_blackout_duration[i][j]));
	567	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_blackout_recovery[%d][%d]:%d",
	568	i, j, bw_fixed_to_int(data->dispclk_required_for_blackout_recovery[i][j]));
	569	}
	570	}
	571
	572	for (i = 0; i < 6; i++) {
	573	DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_required_sclk_for_urgent_latency[%d]:%d",
	574	i, bw_fixed_to_int(data->dmif_required_sclk_for_urgent_latency[i]));
	575	}
	576	}
	577	;
	578
	579	#endif /* _CALCS_CALCS_LOGGER_H_ */

drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c+256−4

@@ -28,6 +28,7 @@ · 27 unmodified lines
28	#include "dc.h"	28	#include "dc.h"
29	#include "core_types.h"	29	#include "core_types.h"
30	#include "dal_asic_id.h"	30	#include "dal_asic_id.h"
		31	#include "calcs_logger.h"
31		32
32	/*	33	/*
33	* NOTE:	34	* NOTE:
@@ -52,11 +53,16 @@ static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asi · 18 unmodified lines
52	return BW_CALCS_VERSION_CARRIZO;	53	return BW_CALCS_VERSION_CARRIZO;
53		54
54	case FAMILY_VI:	55	case FAMILY_VI:
		56	if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
		57	return BW_CALCS_VERSION_POLARIS12;
55	if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))	58	if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
56	return BW_CALCS_VERSION_POLARIS10;	59	return BW_CALCS_VERSION_POLARIS10;
57	if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) \|\|	60	if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
58	ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
59	return BW_CALCS_VERSION_POLARIS11;	61	return BW_CALCS_VERSION_POLARIS11;
		62	#if defined(CONFIG_DRM_AMD_DC_VEGAM)
		63	if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
		64	return BW_CALCS_VERSION_VEGAM;
		65	#endif
60	return BW_CALCS_VERSION_INVALID;	66	return BW_CALCS_VERSION_INVALID;
61		67
62	case FAMILY_AI:	68	case FAMILY_AI:
@@ -2145,6 +2151,11 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, · 2082 unmodified lines
2145	dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/	2151	dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
2146	break;	2152	break;
2147	case BW_CALCS_VERSION_POLARIS10:	2153	case BW_CALCS_VERSION_POLARIS10:
		2154	#if defined(CONFIG_DRM_AMD_DC_VEGAM)
		2155	/* TODO: Treat VEGAM the same as P10 for now
		2156	* Need to tune the para for VEGAM if needed */
		2157	case BW_CALCS_VERSION_VEGAM:
		2158	#endif
2148	vbios.memory_type = bw_def_gddr5;	2159	vbios.memory_type = bw_def_gddr5;
2149	vbios.dram_channel_width_in_bits = 32;	2160	vbios.dram_channel_width_in_bits = 32;
2150	vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;	2161	vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
@@ -2373,6 +2384,122 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, · 222 unmodified lines
2373	dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;	2384	dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2374	dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);	2385	dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2375	break;	2386	break;
		2387	case BW_CALCS_VERSION_POLARIS12:
		2388	vbios.memory_type = bw_def_gddr5;
		2389	vbios.dram_channel_width_in_bits = 32;
		2390	vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
		2391	vbios.number_of_dram_banks = 8;
		2392	vbios.high_yclk = bw_int_to_fixed(6000);
		2393	vbios.mid_yclk = bw_int_to_fixed(3200);
		2394	vbios.low_yclk = bw_int_to_fixed(1000);
		2395	vbios.low_sclk = bw_int_to_fixed(678);
		2396	vbios.mid1_sclk = bw_int_to_fixed(864);
		2397	vbios.mid2_sclk = bw_int_to_fixed(900);
		2398	vbios.mid3_sclk = bw_int_to_fixed(920);
		2399	vbios.mid4_sclk = bw_int_to_fixed(940);
		2400	vbios.mid5_sclk = bw_int_to_fixed(960);
		2401	vbios.mid6_sclk = bw_int_to_fixed(980);
		2402	vbios.high_sclk = bw_int_to_fixed(1049);
		2403	vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
		2404	vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
		2405	vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
		2406	vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
		2407	vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
		2408	vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
		2409	vbios.data_return_bus_width = bw_int_to_fixed(32);
		2410	vbios.trc = bw_int_to_fixed(48);
		2411	if (vbios.number_of_dram_channels == 2) // 64-bit
		2412	vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
		2413	else
		2414	vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
		2415	vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
		2416	vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
		2417	vbios.nbp_state_change_latency = bw_int_to_fixed(250);
		2418	vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
		2419	vbios.scatter_gather_enable = false;
		2420	vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
		2421	vbios.cursor_width = 32;
		2422	vbios.average_compression_rate = 4;
		2423	vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
		2424	vbios.blackout_duration = bw_int_to_fixed(0); /* us */
		2425	vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
		2426
		2427	dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
		2428	dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
		2429	dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
		2430	dceip.large_cursor = false;
		2431	dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
		2432	dceip.dmif_pipe_en_fbc_chunk_tracker = false;
		2433	dceip.cursor_max_outstanding_group_num = 1;
		2434	dceip.lines_interleaved_into_lb = 2;
		2435	dceip.chunk_width = 256;
		2436	dceip.number_of_graphics_pipes = 5;
		2437	dceip.number_of_underlay_pipes = 0;
		2438	dceip.low_power_tiling_mode = 0;
		2439	dceip.display_write_back_supported = true;
		2440	dceip.argb_compression_support = true;
		2441	dceip.underlay_vscaler_efficiency6_bit_per_component =
		2442	bw_frc_to_fixed(35556, 10000);
		2443	dceip.underlay_vscaler_efficiency8_bit_per_component =
		2444	bw_frc_to_fixed(34286, 10000);
		2445	dceip.underlay_vscaler_efficiency10_bit_per_component =
		2446	bw_frc_to_fixed(32, 10);
		2447	dceip.underlay_vscaler_efficiency12_bit_per_component =
		2448	bw_int_to_fixed(3);
		2449	dceip.graphics_vscaler_efficiency6_bit_per_component =
		2450	bw_frc_to_fixed(35, 10);
		2451	dceip.graphics_vscaler_efficiency8_bit_per_component =
		2452	bw_frc_to_fixed(34286, 10000);
		2453	dceip.graphics_vscaler_efficiency10_bit_per_component =
		2454	bw_frc_to_fixed(32, 10);
		2455	dceip.graphics_vscaler_efficiency12_bit_per_component =
		2456	bw_int_to_fixed(3);
		2457	dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
		2458	dceip.max_dmif_buffer_allocated = 4;
		2459	dceip.graphics_dmif_size = 12288;
		2460	dceip.underlay_luma_dmif_size = 19456;
		2461	dceip.underlay_chroma_dmif_size = 23552;
		2462	dceip.pre_downscaler_enabled = true;
		2463	dceip.underlay_downscale_prefetch_enabled = true;
		2464	dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
		2465	dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
		2466	dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
		2467	dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
		2468	bw_int_to_fixed(1);
		2469	dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
		2470	82176);
		2471	dceip.underlay420_chroma_lb_size_per_component =
		2472	bw_int_to_fixed(164352);
		2473	dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
		2474	82176);
		2475	dceip.cursor_chunk_width = bw_int_to_fixed(64);
		2476	dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
		2477	dceip.underlay_maximum_width_efficient_for_tiling =
		2478	bw_int_to_fixed(1920);
		2479	dceip.underlay_maximum_height_efficient_for_tiling =
		2480	bw_int_to_fixed(1080);
		2481	dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
		2482	bw_frc_to_fixed(3, 10);
		2483	dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
		2484	bw_int_to_fixed(25);
		2485	dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
		2486	2);
		2487	dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
		2488	bw_int_to_fixed(128);
		2489	dceip.limit_excessive_outstanding_dmif_requests = true;
		2490	dceip.linear_mode_line_request_alternation_slice =
		2491	bw_int_to_fixed(64);
		2492	dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
		2493	32;
		2494	dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
		2495	dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
		2496	dceip.request_efficiency = bw_frc_to_fixed(8, 10);
		2497	dceip.dispclk_per_request = bw_int_to_fixed(2);
		2498	dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
		2499	dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
		2500	dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
		2501	dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
		2502	break;
2376	case BW_CALCS_VERSION_STONEY:	2503	case BW_CALCS_VERSION_STONEY:
2377	vbios.memory_type = bw_def_gddr5;	2504	vbios.memory_type = bw_def_gddr5;
2378	vbios.dram_channel_width_in_bits = 64;	2505	vbios.dram_channel_width_in_bits = 64;
@@ -2815,6 +2942,19 @@ static void populate_initial_data( · 436 unmodified lines
2815	data->bytes_per_pixel[num_displays + 4] = 4;	2942	data->bytes_per_pixel[num_displays + 4] = 4;
2816	break;	2943	break;
2817	}	2944	}
		2945	} else if (pipe[i].stream->dst.width != 0 &&
		2946	pipe[i].stream->dst.height != 0 &&
		2947	pipe[i].stream->src.width != 0 &&
		2948	pipe[i].stream->src.height != 0) {
		2949	data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.width);
		2950	data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
		2951	data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.height);
		2952	data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
		2953	data->v_taps[num_displays + 4] = pipe[i].stream->src.height == pipe[i].stream->dst.height ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
		2954	data->h_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.width, pipe[i].stream->dst.width);
		2955	data->v_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.height, pipe[i].stream->dst.height);
		2956	data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
		2957	data->bytes_per_pixel[num_displays + 4] = 4;
2818	} else {	2958	} else {
2819	data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);	2959	data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);
2820	data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];	2960	data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
@@ -2873,6 +3013,11 @@ bool bw_calcs(struct dc_context *ctx, · 52 unmodified lines
2873	struct bw_fixed mid_yclk = vbios->mid_yclk;	3013	struct bw_fixed mid_yclk = vbios->mid_yclk;
2874	struct bw_fixed low_yclk = vbios->low_yclk;	3014	struct bw_fixed low_yclk = vbios->low_yclk;
2875		3015
		3016	if (ctx->dc->debug.bandwidth_calcs_trace) {
		3017	print_bw_calcs_dceip(ctx->logger, dceip);
		3018	print_bw_calcs_vbios(ctx->logger, vbios);
		3019	print_bw_calcs_data(ctx->logger, data);
		3020	}
2876	calculate_bandwidth(dceip, vbios, data);	3021	calculate_bandwidth(dceip, vbios, data);
2877		3022
2878	yclk_lvl = data->y_clk_level;	3023	yclk_lvl = data->y_clk_level;
@@ -2968,7 +3113,33 @@ bool bw_calcs(struct dc_context *ctx, · 89 unmodified lines
2968	bw_fixed_to_int(bw_mul(data->	3113	bw_fixed_to_int(bw_mul(data->
2969	stutter_exit_watermark[9], bw_int_to_fixed(1000)));	3114	stutter_exit_watermark[9], bw_int_to_fixed(1000)));
2970		3115
2971		3116	calcs_output->stutter_entry_wm_ns[0].a_mark =
		3117	bw_fixed_to_int(bw_mul(data->
		3118	stutter_entry_watermark[4], bw_int_to_fixed(1000)));
		3119	calcs_output->stutter_entry_wm_ns[1].a_mark =
		3120	bw_fixed_to_int(bw_mul(data->
		3121	stutter_entry_watermark[5], bw_int_to_fixed(1000)));
		3122	calcs_output->stutter_entry_wm_ns[2].a_mark =
		3123	bw_fixed_to_int(bw_mul(data->
		3124	stutter_entry_watermark[6], bw_int_to_fixed(1000)));
		3125	if (ctx->dc->caps.max_slave_planes) {
		3126	calcs_output->stutter_entry_wm_ns[3].a_mark =
		3127	bw_fixed_to_int(bw_mul(data->
		3128	stutter_entry_watermark[0], bw_int_to_fixed(1000)));
		3129	calcs_output->stutter_entry_wm_ns[4].a_mark =
		3130	bw_fixed_to_int(bw_mul(data->
		3131	stutter_entry_watermark[1], bw_int_to_fixed(1000)));
		3132	} else {
		3133	calcs_output->stutter_entry_wm_ns[3].a_mark =
		3134	bw_fixed_to_int(bw_mul(data->
		3135	stutter_entry_watermark[7], bw_int_to_fixed(1000)));
		3136	calcs_output->stutter_entry_wm_ns[4].a_mark =
		3137	bw_fixed_to_int(bw_mul(data->
		3138	stutter_entry_watermark[8], bw_int_to_fixed(1000)));
		3139	}
		3140	calcs_output->stutter_entry_wm_ns[5].a_mark =
		3141	bw_fixed_to_int(bw_mul(data->
		3142	stutter_entry_watermark[9], bw_int_to_fixed(1000)));
2972		3143
2973	calcs_output->urgent_wm_ns[0].a_mark =	3144	calcs_output->urgent_wm_ns[0].a_mark =
2974	bw_fixed_to_int(bw_mul(data->	3145	bw_fixed_to_int(bw_mul(data->
@@ -3063,7 +3234,33 @@ bool bw_calcs(struct dc_context *ctx, · 88 unmodified lines
3063	bw_fixed_to_int(bw_mul(data->	3234	bw_fixed_to_int(bw_mul(data->
3064	stutter_exit_watermark[9], bw_int_to_fixed(1000)));	3235	stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3065		3236
3066		3237	calcs_output->stutter_entry_wm_ns[0].b_mark =
		3238	bw_fixed_to_int(bw_mul(data->
		3239	stutter_entry_watermark[4], bw_int_to_fixed(1000)));
		3240	calcs_output->stutter_entry_wm_ns[1].b_mark =
		3241	bw_fixed_to_int(bw_mul(data->
		3242	stutter_entry_watermark[5], bw_int_to_fixed(1000)));
		3243	calcs_output->stutter_entry_wm_ns[2].b_mark =
		3244	bw_fixed_to_int(bw_mul(data->
		3245	stutter_entry_watermark[6], bw_int_to_fixed(1000)));
		3246	if (ctx->dc->caps.max_slave_planes) {
		3247	calcs_output->stutter_entry_wm_ns[3].b_mark =
		3248	bw_fixed_to_int(bw_mul(data->
		3249	stutter_entry_watermark[0], bw_int_to_fixed(1000)));
		3250	calcs_output->stutter_entry_wm_ns[4].b_mark =
		3251	bw_fixed_to_int(bw_mul(data->
		3252	stutter_entry_watermark[1], bw_int_to_fixed(1000)));
		3253	} else {
		3254	calcs_output->stutter_entry_wm_ns[3].b_mark =
		3255	bw_fixed_to_int(bw_mul(data->
		3256	stutter_entry_watermark[7], bw_int_to_fixed(1000)));
		3257	calcs_output->stutter_entry_wm_ns[4].b_mark =
		3258	bw_fixed_to_int(bw_mul(data->
		3259	stutter_entry_watermark[8], bw_int_to_fixed(1000)));
		3260	}
		3261	calcs_output->stutter_entry_wm_ns[5].b_mark =
		3262	bw_fixed_to_int(bw_mul(data->
		3263	stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3067		3264
3068	calcs_output->urgent_wm_ns[0].b_mark =	3265	calcs_output->urgent_wm_ns[0].b_mark =
3069	bw_fixed_to_int(bw_mul(data->	3266	bw_fixed_to_int(bw_mul(data->
@@ -3156,6 +3353,34 @@ bool bw_calcs(struct dc_context *ctx, · 86 unmodified lines
3156	bw_fixed_to_int(bw_mul(data->	3353	bw_fixed_to_int(bw_mul(data->
3157	stutter_exit_watermark[9], bw_int_to_fixed(1000)));	3354	stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3158		3355
		3356	calcs_output->stutter_entry_wm_ns[0].c_mark =
		3357	bw_fixed_to_int(bw_mul(data->
		3358	stutter_entry_watermark[4], bw_int_to_fixed(1000)));
		3359	calcs_output->stutter_entry_wm_ns[1].c_mark =
		3360	bw_fixed_to_int(bw_mul(data->
		3361	stutter_entry_watermark[5], bw_int_to_fixed(1000)));
		3362	calcs_output->stutter_entry_wm_ns[2].c_mark =
		3363	bw_fixed_to_int(bw_mul(data->
		3364	stutter_entry_watermark[6], bw_int_to_fixed(1000)));
		3365	if (ctx->dc->caps.max_slave_planes) {
		3366	calcs_output->stutter_entry_wm_ns[3].c_mark =
		3367	bw_fixed_to_int(bw_mul(data->
		3368	stutter_entry_watermark[0], bw_int_to_fixed(1000)));
		3369	calcs_output->stutter_entry_wm_ns[4].c_mark =
		3370	bw_fixed_to_int(bw_mul(data->
		3371	stutter_entry_watermark[1], bw_int_to_fixed(1000)));
		3372	} else {
		3373	calcs_output->stutter_entry_wm_ns[3].c_mark =
		3374	bw_fixed_to_int(bw_mul(data->
		3375	stutter_entry_watermark[7], bw_int_to_fixed(1000)));
		3376	calcs_output->stutter_entry_wm_ns[4].c_mark =
		3377	bw_fixed_to_int(bw_mul(data->
		3378	stutter_entry_watermark[8], bw_int_to_fixed(1000)));
		3379	}
		3380	calcs_output->stutter_entry_wm_ns[5].c_mark =
		3381	bw_fixed_to_int(bw_mul(data->
		3382	stutter_entry_watermark[9], bw_int_to_fixed(1000)));
		3383
3159	calcs_output->urgent_wm_ns[0].c_mark =	3384	calcs_output->urgent_wm_ns[0].c_mark =
3160	bw_fixed_to_int(bw_mul(data->	3385	bw_fixed_to_int(bw_mul(data->
3161	urgent_watermark[4], bw_int_to_fixed(1000)));	3386	urgent_watermark[4], bw_int_to_fixed(1000)));
@@ -3260,6 +3485,33 @@ bool bw_calcs(struct dc_context *ctx, · 98 unmodified lines
3260	bw_fixed_to_int(bw_mul(data->	3485	bw_fixed_to_int(bw_mul(data->
3261	stutter_exit_watermark[9], bw_int_to_fixed(1000)));	3486	stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3262		3487
		3488	calcs_output->stutter_entry_wm_ns[0].d_mark =
		3489	bw_fixed_to_int(bw_mul(data->
		3490	stutter_entry_watermark[4], bw_int_to_fixed(1000)));
		3491	calcs_output->stutter_entry_wm_ns[1].d_mark =
		3492	bw_fixed_to_int(bw_mul(data->
		3493	stutter_entry_watermark[5], bw_int_to_fixed(1000)));
		3494	calcs_output->stutter_entry_wm_ns[2].d_mark =
		3495	bw_fixed_to_int(bw_mul(data->
		3496	stutter_entry_watermark[6], bw_int_to_fixed(1000)));
		3497	if (ctx->dc->caps.max_slave_planes) {
		3498	calcs_output->stutter_entry_wm_ns[3].d_mark =
		3499	bw_fixed_to_int(bw_mul(data->
		3500	stutter_entry_watermark[0], bw_int_to_fixed(1000)));
		3501	calcs_output->stutter_entry_wm_ns[4].d_mark =
		3502	bw_fixed_to_int(bw_mul(data->
		3503	stutter_entry_watermark[1], bw_int_to_fixed(1000)));
		3504	} else {
		3505	calcs_output->stutter_entry_wm_ns[3].d_mark =
		3506	bw_fixed_to_int(bw_mul(data->
		3507	stutter_entry_watermark[7], bw_int_to_fixed(1000)));
		3508	calcs_output->stutter_entry_wm_ns[4].d_mark =
		3509	bw_fixed_to_int(bw_mul(data->
		3510	stutter_entry_watermark[8], bw_int_to_fixed(1000)));
		3511	}
		3512	calcs_output->stutter_entry_wm_ns[5].d_mark =
		3513	bw_fixed_to_int(bw_mul(data->
		3514	stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3263		3515
3264	calcs_output->urgent_wm_ns[0].d_mark =	3516	calcs_output->urgent_wm_ns[0].d_mark =
3265	bw_fixed_to_int(bw_mul(data->	3517	bw_fixed_to_int(bw_mul(data->

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c+37−37

@@ -1459,39 +1459,39 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) · 1458 unmodified lines
1459	void dcn_bw_sync_calcs_and_dml(struct dc *dc)	1459	void dcn_bw_sync_calcs_and_dml(struct dc *dc)
1460	{	1460	{
1461	kernel_fpu_begin();	1461	kernel_fpu_begin();
1462	DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %d ns\n"	1462	DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
1463	"sr_enter_plus_exit_time: %d ns\n"	1463	"sr_enter_plus_exit_time: %f ns\n"
1464	"urgent_latency: %d ns\n"	1464	"urgent_latency: %f ns\n"
1465	"write_back_latency: %d ns\n"	1465	"write_back_latency: %f ns\n"
1466	"percent_of_ideal_drambw_received_after_urg_latency: %d %\n"	1466	"percent_of_ideal_drambw_received_after_urg_latency: %f %%\n"
1467	"max_request_size: %d bytes\n"	1467	"max_request_size: %d bytes\n"
1468	"dcfclkv_max0p9: %d kHz\n"	1468	"dcfclkv_max0p9: %f kHz\n"
1469	"dcfclkv_nom0p8: %d kHz\n"	1469	"dcfclkv_nom0p8: %f kHz\n"
1470	"dcfclkv_mid0p72: %d kHz\n"	1470	"dcfclkv_mid0p72: %f kHz\n"
1471	"dcfclkv_min0p65: %d kHz\n"	1471	"dcfclkv_min0p65: %f kHz\n"
1472	"max_dispclk_vmax0p9: %d kHz\n"	1472	"max_dispclk_vmax0p9: %f kHz\n"
1473	"max_dispclk_vnom0p8: %d kHz\n"	1473	"max_dispclk_vnom0p8: %f kHz\n"
1474	"max_dispclk_vmid0p72: %d kHz\n"	1474	"max_dispclk_vmid0p72: %f kHz\n"
1475	"max_dispclk_vmin0p65: %d kHz\n"	1475	"max_dispclk_vmin0p65: %f kHz\n"
1476	"max_dppclk_vmax0p9: %d kHz\n"	1476	"max_dppclk_vmax0p9: %f kHz\n"
1477	"max_dppclk_vnom0p8: %d kHz\n"	1477	"max_dppclk_vnom0p8: %f kHz\n"
1478	"max_dppclk_vmid0p72: %d kHz\n"	1478	"max_dppclk_vmid0p72: %f kHz\n"
1479	"max_dppclk_vmin0p65: %d kHz\n"	1479	"max_dppclk_vmin0p65: %f kHz\n"
1480	"socclk: %d kHz\n"	1480	"socclk: %f kHz\n"
1481	"fabric_and_dram_bandwidth_vmax0p9: %d MB/s\n"	1481	"fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n"
1482	"fabric_and_dram_bandwidth_vnom0p8: %d MB/s\n"	1482	"fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n"
1483	"fabric_and_dram_bandwidth_vmid0p72: %d MB/s\n"	1483	"fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n"
1484	"fabric_and_dram_bandwidth_vmin0p65: %d MB/s\n"	1484	"fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n"
1485	"phyclkv_max0p9: %d kHz\n"	1485	"phyclkv_max0p9: %f kHz\n"
1486	"phyclkv_nom0p8: %d kHz\n"	1486	"phyclkv_nom0p8: %f kHz\n"
1487	"phyclkv_mid0p72: %d kHz\n"	1487	"phyclkv_mid0p72: %f kHz\n"
1488	"phyclkv_min0p65: %d kHz\n"	1488	"phyclkv_min0p65: %f kHz\n"
1489	"downspreading: %d %\n"	1489	"downspreading: %f %%\n"
1490	"round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"	1490	"round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
1491	"urgent_out_of_order_return_per_channel: %d Bytes\n"	1491	"urgent_out_of_order_return_per_channel: %d Bytes\n"
1492	"number_of_channels: %d\n"	1492	"number_of_channels: %d\n"
1493	"vmm_page_size: %d Bytes\n"	1493	"vmm_page_size: %d Bytes\n"
1494	"dram_clock_change_latency: %d ns\n"	1494	"dram_clock_change_latency: %f ns\n"
1495	"return_bus_width: %d Bytes\n",	1495	"return_bus_width: %d Bytes\n",
1496	dc->dcn_soc->sr_exit_time * 1000,	1496	dc->dcn_soc->sr_exit_time * 1000,
1497	dc->dcn_soc->sr_enter_plus_exit_time * 1000,	1497	dc->dcn_soc->sr_enter_plus_exit_time * 1000,
@@ -1527,11 +1527,11 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc) · 29 unmodified lines
1527	dc->dcn_soc->vmm_page_size,	1527	dc->dcn_soc->vmm_page_size,
1528	dc->dcn_soc->dram_clock_change_latency * 1000,	1528	dc->dcn_soc->dram_clock_change_latency * 1000,
1529	dc->dcn_soc->return_bus_width);	1529	dc->dcn_soc->return_bus_width);
1530	DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %d\n"	1530	DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n"
1531	"det_buffer_size_in_kbyte: %d\n"	1531	"det_buffer_size_in_kbyte: %f\n"
1532	"dpp_output_buffer_pixels: %d\n"	1532	"dpp_output_buffer_pixels: %f\n"
1533	"opp_output_buffer_lines: %d\n"	1533	"opp_output_buffer_lines: %f\n"
1534	"pixel_chunk_size_in_kbyte: %d\n"	1534	"pixel_chunk_size_in_kbyte: %f\n"
1535	"pte_enable: %d\n"	1535	"pte_enable: %d\n"
1536	"pte_chunk_size: %d kbytes\n"	1536	"pte_chunk_size: %d kbytes\n"
1537	"meta_chunk_size: %d kbytes\n"	1537	"meta_chunk_size: %d kbytes\n"
@@ -1550,13 +1550,13 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc) · 12 unmodified lines
1550	"max_pscl_tolb_throughput: %d pixels/dppclk\n"	1550	"max_pscl_tolb_throughput: %d pixels/dppclk\n"
1551	"max_lb_tovscl_throughput: %d pixels/dppclk\n"	1551	"max_lb_tovscl_throughput: %d pixels/dppclk\n"
1552	"max_vscl_tohscl_throughput: %d pixels/dppclk\n"	1552	"max_vscl_tohscl_throughput: %d pixels/dppclk\n"
1553	"max_hscl_ratio: %d\n"	1553	"max_hscl_ratio: %f\n"
1554	"max_vscl_ratio: %d\n"	1554	"max_vscl_ratio: %f\n"
1555	"max_hscl_taps: %d\n"	1555	"max_hscl_taps: %d\n"
1556	"max_vscl_taps: %d\n"	1556	"max_vscl_taps: %d\n"
1557	"pte_buffer_size_in_requests: %d\n"	1557	"pte_buffer_size_in_requests: %d\n"
1558	"dispclk_ramping_margin: %d %\n"	1558	"dispclk_ramping_margin: %f %%\n"
1559	"under_scan_factor: %d %\n"	1559	"under_scan_factor: %f %%\n"
1560	"max_inter_dcn_tile_repeaters: %d\n"	1560	"max_inter_dcn_tile_repeaters: %d\n"
1561	"can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"	1561	"can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
1562	"bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"	1562	"bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"

drivers/gpu/drm/amd/display/dc/core/dc.c+17−95

@@ -936,95 +936,6 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) · 935 unmodified lines
936	return true;	936	return true;
937	}	937	}
938		938
939	/*
940	* TODO this whole function needs to go
941	*
942	* dc_surface_update is needlessly complex. See if we can just replace this
943	* with a dc_plane_state and follow the atomic model a bit more closely here.
944	*/
945	bool dc_commit_planes_to_stream(
946	struct dc *dc,
947	struct dc_plane_state **plane_states,
948	uint8_t new_plane_count,
949	struct dc_stream_state *dc_stream,
950	struct dc_state *state)
951	{
952	/* no need to dynamically allocate this. it's pretty small */
953	struct dc_surface_update updates[MAX_SURFACES];
954	struct dc_flip_addrs *flip_addr;
955	struct dc_plane_info *plane_info;
956	struct dc_scaling_info *scaling_info;
957	int i;
958	struct dc_stream_update *stream_update =
959	kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
960
961	if (!stream_update) {
962	BREAK_TO_DEBUGGER();
963	return false;
964	}
965
966	flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
967	GFP_KERNEL);
968	plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
969	GFP_KERNEL);
970	scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
971	GFP_KERNEL);
972
973	if (!flip_addr \|\| !plane_info \|\| !scaling_info) {
974	kfree(flip_addr);
975	kfree(plane_info);
976	kfree(scaling_info);
977	kfree(stream_update);
978	return false;
979	}
980
981	memset(updates, 0, sizeof(updates));
982
983	stream_update->src = dc_stream->src;
984	stream_update->dst = dc_stream->dst;
985	stream_update->out_transfer_func = dc_stream->out_transfer_func;
986
987	for (i = 0; i < new_plane_count; i++) {
988	updates[i].surface = plane_states[i];
989	updates[i].gamma =
990	(struct dc_gamma *)plane_states[i]->gamma_correction;
991	updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
992	flip_addr[i].address = plane_states[i]->address;
993	flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
994	plane_info[i].color_space = plane_states[i]->color_space;
995	plane_info[i].input_tf = plane_states[i]->input_tf;
996	plane_info[i].format = plane_states[i]->format;
997	plane_info[i].plane_size = plane_states[i]->plane_size;
998	plane_info[i].rotation = plane_states[i]->rotation;
999	plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
1000	plane_info[i].stereo_format = plane_states[i]->stereo_format;
1001	plane_info[i].tiling_info = plane_states[i]->tiling_info;
1002	plane_info[i].visible = plane_states[i]->visible;
1003	plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
1004	plane_info[i].dcc = plane_states[i]->dcc;
1005	scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
1006	scaling_info[i].src_rect = plane_states[i]->src_rect;
1007	scaling_info[i].dst_rect = plane_states[i]->dst_rect;
1008	scaling_info[i].clip_rect = plane_states[i]->clip_rect;
1009
1010	updates[i].flip_addr = &flip_addr[i];
1011	updates[i].plane_info = &plane_info[i];
1012	updates[i].scaling_info = &scaling_info[i];
1013	}
1014
1015	dc_commit_updates_for_stream(
1016	dc,
1017	updates,
1018	new_plane_count,
1019	dc_stream, stream_update, plane_states, state);
1020
1021	kfree(flip_addr);
1022	kfree(plane_info);
1023	kfree(scaling_info);
1024	kfree(stream_update);
1025	return true;
1026	}
1027
1028	struct dc_state *dc_create_state(void)	939	struct dc_state *dc_create_state(void)
1029	{	940	{
1030	struct dc_state *context = kzalloc(sizeof(struct dc_state),	941	struct dc_state *context = kzalloc(sizeof(struct dc_state),
@@ -1107,9 +1018,6 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa · 76 unmodified lines
1107	if (u->plane_info->color_space != u->surface->color_space)	1018	if (u->plane_info->color_space != u->surface->color_space)
1108	update_flags->bits.color_space_change = 1;	1019	update_flags->bits.color_space_change = 1;
1109		1020
1110	if (u->plane_info->input_tf != u->surface->input_tf)
1111	update_flags->bits.input_tf_change = 1;
1112
1113	if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)	1021	if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
1114	update_flags->bits.horizontal_mirror_change = 1;	1022	update_flags->bits.horizontal_mirror_change = 1;
1115		1023
@@ -1243,12 +1151,20 @@ static enum surface_update_type det_surface_update(const struct dc *dc, · 127 unmodified lines
1243	if (u->input_csc_color_matrix)	1151	if (u->input_csc_color_matrix)
1244	update_flags->bits.input_csc_change = 1;	1152	update_flags->bits.input_csc_change = 1;
1245		1153
1246	if (update_flags->bits.in_transfer_func_change	1154	if (u->coeff_reduction_factor)
1247	\|\| update_flags->bits.input_csc_change) {	1155	update_flags->bits.coeff_reduction_change = 1;
		1156
		1157	if (update_flags->bits.in_transfer_func_change) {
1248	type = UPDATE_TYPE_MED;	1158	type = UPDATE_TYPE_MED;
1249	elevate_update_type(&overall_type, type);	1159	elevate_update_type(&overall_type, type);
1250	}	1160	}
1251		1161
		1162	if (update_flags->bits.input_csc_change
		1163	\|\| update_flags->bits.coeff_reduction_change) {
		1164	type = UPDATE_TYPE_FULL;
		1165	elevate_update_type(&overall_type, type);
		1166	}
		1167
1252	return overall_type;	1168	return overall_type;
1253	}	1169	}
1254		1170
@@ -1297,7 +1213,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( · 42 unmodified lines
1297	type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);	1213	type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
1298	if (type == UPDATE_TYPE_FULL)	1214	if (type == UPDATE_TYPE_FULL)
1299	for (i = 0; i < surface_count; i++)	1215	for (i = 0; i < surface_count; i++)
1300	updates[i].surface->update_flags.bits.full_update = 1;	1216	updates[i].surface->update_flags.raw = 0xFFFFFFFF;
1301		1217
1302	return type;	1218	return type;
1303	}	1219	}
@@ -1375,6 +1291,12 @@ static void commit_planes_for_stream(struct dc *dc, · 71 unmodified lines
1375	pipe_ctx->stream_res.abm->funcs->set_abm_level(	1291	pipe_ctx->stream_res.abm->funcs->set_abm_level(
1376	pipe_ctx->stream_res.abm, stream->abm_level);	1292	pipe_ctx->stream_res.abm, stream->abm_level);
1377	}	1293	}
		1294
		1295	if (stream_update && stream_update->periodic_fn_vsync_delta &&
		1296	pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
		1297	pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
		1298	pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing,
		1299	pipe_ctx->stream->periodic_fn_vsync_delta);
1378	}	1300	}
1379	}	1301	}
1380		1302

drivers/gpu/drm/amd/display/dc/core/dc_debug.c+16−22

@@ -36,8 +36,9 @@ · 35 unmodified lines
36	#include "hw_sequencer.h"	36	#include "hw_sequencer.h"
37		37
38	#include "resource.h"	38	#include "resource.h"
39	#define DC_LOGGER \	39
40	logger	40	#define DC_LOGGER_INIT(logger)
		41
41		42
42	#define SURFACE_TRACE(...) do {\	43	#define SURFACE_TRACE(...) do {\
43	if (dc->debug.surface_trace) \	44	if (dc->debug.surface_trace) \
@@ -60,8 +61,7 @@ void pre_surface_trace( · 16 unmodified lines
60	int surface_count)	61	int surface_count)
61	{	62	{
62	int i;	63	int i;
63	struct dc *core_dc = dc;	64	DC_LOGGER_INIT(dc->ctx->logger);
64	struct dal_logger *logger = core_dc->ctx->logger;
65		65
66	for (i = 0; i < surface_count; i++) {	66	for (i = 0; i < surface_count; i++) {
67	const struct dc_plane_state *plane_state = plane_states[i];	67	const struct dc_plane_state *plane_state = plane_states[i];
@@ -72,8 +72,8 @@ void pre_surface_trace( · 4 unmodified lines
72	"plane_state->visible = %d;\n"	72	"plane_state->visible = %d;\n"
73	"plane_state->flip_immediate = %d;\n"	73	"plane_state->flip_immediate = %d;\n"
74	"plane_state->address.type = %d;\n"	74	"plane_state->address.type = %d;\n"
75	"plane_state->address.grph.addr.quad_part = 0x%X;\n"	75	"plane_state->address.grph.addr.quad_part = 0x%llX;\n"
76	"plane_state->address.grph.meta_addr.quad_part = 0x%X;\n"	76	"plane_state->address.grph.meta_addr.quad_part = 0x%llX;\n"
77	"plane_state->scaling_quality.h_taps = %d;\n"	77	"plane_state->scaling_quality.h_taps = %d;\n"
78	"plane_state->scaling_quality.v_taps = %d;\n"	78	"plane_state->scaling_quality.v_taps = %d;\n"
79	"plane_state->scaling_quality.h_taps_c = %d;\n"	79	"plane_state->scaling_quality.h_taps_c = %d;\n"
@@ -155,7 +155,6 @@ void pre_surface_trace( · 75 unmodified lines
155	"plane_state->tiling_info.gfx8.pipe_config = %d;\n"	155	"plane_state->tiling_info.gfx8.pipe_config = %d;\n"
156	"plane_state->tiling_info.gfx8.array_mode = %d;\n"	156	"plane_state->tiling_info.gfx8.array_mode = %d;\n"
157	"plane_state->color_space = %d;\n"	157	"plane_state->color_space = %d;\n"
158	"plane_state->input_tf = %d;\n"
159	"plane_state->dcc.enable = %d;\n"	158	"plane_state->dcc.enable = %d;\n"
160	"plane_state->format = %d;\n"	159	"plane_state->format = %d;\n"
161	"plane_state->rotation = %d;\n"	160	"plane_state->rotation = %d;\n"
@@ -163,7 +162,6 @@ void pre_surface_trace( · 1 unmodified line
163	plane_state->tiling_info.gfx8.pipe_config,	162	plane_state->tiling_info.gfx8.pipe_config,
164	plane_state->tiling_info.gfx8.array_mode,	163	plane_state->tiling_info.gfx8.array_mode,
165	plane_state->color_space,	164	plane_state->color_space,
166	plane_state->input_tf,
167	plane_state->dcc.enable,	165	plane_state->dcc.enable,
168	plane_state->format,	166	plane_state->format,
169	plane_state->rotation,	167	plane_state->rotation,
@@ -183,8 +181,7 @@ void update_surface_trace( · 13 unmodified lines
183	int surface_count)	181	int surface_count)
184	{	182	{
185	int i;	183	int i;
186	struct dc *core_dc = dc;	184	DC_LOGGER_INIT(dc->ctx->logger);
187	struct dal_logger *logger = core_dc->ctx->logger;
188		185
189	for (i = 0; i < surface_count; i++) {	186	for (i = 0; i < surface_count; i++) {
190	const struct dc_surface_update *update = &updates[i];	187	const struct dc_surface_update *update = &updates[i];
@@ -192,8 +189,8 @@ void update_surface_trace( · 1 unmodified line
192	SURFACE_TRACE("Update %d\n", i);	189	SURFACE_TRACE("Update %d\n", i);
193	if (update->flip_addr) {	190	if (update->flip_addr) {
194	SURFACE_TRACE("flip_addr->address.type = %d;\n"	191	SURFACE_TRACE("flip_addr->address.type = %d;\n"
195	"flip_addr->address.grph.addr.quad_part = 0x%X;\n"	192	"flip_addr->address.grph.addr.quad_part = 0x%llX;\n"
196	"flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n"	193	"flip_addr->address.grph.meta_addr.quad_part = 0x%llX;\n"
197	"flip_addr->flip_immediate = %d;\n",	194	"flip_addr->flip_immediate = %d;\n",
198	update->flip_addr->address.type,	195	update->flip_addr->address.type,
199	update->flip_addr->address.grph.addr.quad_part,	196	update->flip_addr->address.grph.addr.quad_part,
@@ -204,16 +201,15 @@ void update_surface_trace( · 4 unmodified lines
204	if (update->plane_info) {	201	if (update->plane_info) {
205	SURFACE_TRACE(	202	SURFACE_TRACE(
206	"plane_info->color_space = %d;\n"	203	"plane_info->color_space = %d;\n"
207	"plane_info->input_tf = %d;\n"
208	"plane_info->format = %d;\n"	204	"plane_info->format = %d;\n"
209	"plane_info->plane_size.grph.surface_pitch = %d;\n"	205	"plane_info->plane_size.grph.surface_pitch = %d;\n"
210	"plane_info->plane_size.grph.surface_size.height = %d;\n"	206	"plane_info->plane_size.grph.surface_size.height = %d;\n"
211	"plane_info->plane_size.grph.surface_size.width = %d;\n"	207	"plane_info->plane_size.grph.surface_size.width = %d;\n"
212	"plane_info->plane_size.grph.surface_size.x = %d;\n"	208	"plane_info->plane_size.grph.surface_size.x = %d;\n"
213	"plane_info->plane_size.grph.surface_size.y = %d;\n"	209	"plane_info->plane_size.grph.surface_size.y = %d;\n"
214	"plane_info->rotation = %d;\n",	210	"plane_info->rotation = %d;\n"
		211	"plane_info->stereo_format = %d;\n",
215	update->plane_info->color_space,	212	update->plane_info->color_space,
216	update->plane_info->input_tf,
217	update->plane_info->format,	213	update->plane_info->format,
218	update->plane_info->plane_size.grph.surface_pitch,	214	update->plane_info->plane_size.grph.surface_pitch,
219	update->plane_info->plane_size.grph.surface_size.height,	215	update->plane_info->plane_size.grph.surface_size.height,
@@ -303,8 +299,7 @@ void update_surface_trace( · 83 unmodified lines
303		299
304	void post_surface_trace(struct dc *dc)	300	void post_surface_trace(struct dc *dc)
305	{	301	{
306	struct dc *core_dc = dc;	302	DC_LOGGER_INIT(dc->ctx->logger);
307	struct dal_logger *logger = core_dc->ctx->logger;
308		303
309	SURFACE_TRACE("post surface process.\n");	304	SURFACE_TRACE("post surface process.\n");
310		305
@@ -316,10 +311,10 @@ void context_timing_trace( · 5 unmodified lines
316	{	311	{
317	int i;	312	int i;
318	struct dc *core_dc = dc;	313	struct dc *core_dc = dc;
319	struct dal_logger *logger = core_dc->ctx->logger;
320	int h_pos[MAX_PIPES], v_pos[MAX_PIPES];	314	int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
321	struct crtc_position position;	315	struct crtc_position position;
322	unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;	316	unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
		317	DC_LOGGER_INIT(dc->ctx->logger);
323		318
324		319
325	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {	320	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
@@ -354,9 +349,7 @@ void context_clock_trace( · 28 unmodified lines
354	struct dc_state *context)	349	struct dc_state *context)
355	{	350	{
356	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)	351	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
357	struct dc *core_dc = dc;	352	DC_LOGGER_INIT(dc->ctx->logger);
358	struct dal_logger *logger = core_dc->ctx->logger;
359
360	CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"	353	CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
361	"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",	354	"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
362	context->bw.dcn.calc_clk.dispclk_khz,	355	context->bw.dcn.calc_clk.dispclk_khz,
@@ -371,6 +364,7 @@ void context_clock_trace( · 8 unmodified lines
371	context->bw.dcn.calc_clk.dppclk_khz,	364	context->bw.dcn.calc_clk.dppclk_khz,
372	context->bw.dcn.calc_clk.dcfclk_khz,	365	context->bw.dcn.calc_clk.dcfclk_khz,
373	context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,	366	context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
374	context->bw.dcn.calc_clk.fclk_khz);	367	context->bw.dcn.calc_clk.fclk_khz,
		368	context->bw.dcn.calc_clk.socclk_khz);
375	#endif	369	#endif
376	}	370	}

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c+23−1

@@ -208,6 +208,7 @@ void color_space_to_black_color( · 207 unmodified lines
208	case COLOR_SPACE_YCBCR709:	208	case COLOR_SPACE_YCBCR709:
209	case COLOR_SPACE_YCBCR601_LIMITED:	209	case COLOR_SPACE_YCBCR601_LIMITED:
210	case COLOR_SPACE_YCBCR709_LIMITED:	210	case COLOR_SPACE_YCBCR709_LIMITED:
		211	case COLOR_SPACE_2020_YCBCR:
211	*black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];	212	*black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
212	break;	213	break;
213		214
@@ -216,7 +217,25 @@ void color_space_to_black_color( · 2 unmodified lines
216	black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];	217	black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
217	break;	218	break;
218		219
219	default:	220	/**
		221	* Remove default and add case for all color space
		222	* so when we forget to add new color space
		223	* compiler will give a warning
		224	*/
		225	case COLOR_SPACE_UNKNOWN:
		226	case COLOR_SPACE_SRGB:
		227	case COLOR_SPACE_XR_RGB:
		228	case COLOR_SPACE_MSREF_SCRGB:
		229	case COLOR_SPACE_XV_YCC_709:
		230	case COLOR_SPACE_XV_YCC_601:
		231	case COLOR_SPACE_2020_RGB_FULLRANGE:
		232	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
		233	case COLOR_SPACE_ADOBERGB:
		234	case COLOR_SPACE_DCIP3:
		235	case COLOR_SPACE_DISPLAYNATIVE:
		236	case COLOR_SPACE_DOLBYVISION:
		237	case COLOR_SPACE_APPCTRL:
		238	case COLOR_SPACE_CUSTOMPOINTS:
220	/* fefault is sRGB black (full range). */	239	/* fefault is sRGB black (full range). */
221	*black_color =	240	*black_color =
222	black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];	241	black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
@@ -230,6 +249,9 @@ bool hwss_wait_for_blank_complete( · 7 unmodified lines
230	{	249	{
231	int counter;	250	int counter;
232		251
		252	/* Not applicable if the pipe is not primary, save 300ms of boot time */
		253	if (!tg->funcs->is_blanked)
		254	return true;
233	for (counter = 0; counter < 100; counter++) {	255	for (counter = 0; counter < 100; counter++) {
234	if (tg->funcs->is_blanked(tg))	256	if (tg->funcs->is_blanked(tg))
235	break;	257	break;

drivers/gpu/drm/amd/display/dc/core/dc_link.c+42−21

@@ -45,8 +45,9 @@ · 44 unmodified lines
45	#include "dce/dce_11_0_d.h"	45	#include "dce/dce_11_0_d.h"
46	#include "dce/dce_11_0_enum.h"	46	#include "dce/dce_11_0_enum.h"
47	#include "dce/dce_11_0_sh_mask.h"	47	#include "dce/dce_11_0_sh_mask.h"
48	#define DC_LOGGER \	48
49	dc_ctx->logger	49	#define DC_LOGGER_INIT(logger)
		50
50		51
51	#define LINK_INFO(...) \	52	#define LINK_INFO(...) \
52	DC_LOG_HW_HOTPLUG( \	53	DC_LOG_HW_HOTPLUG( \
@@ -561,7 +562,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) · 508 unmodified lines
561	struct dc_context *dc_ctx = link->ctx;	562	struct dc_context *dc_ctx = link->ctx;
562	struct dc_sink *sink = NULL;	563	struct dc_sink *sink = NULL;
563	enum dc_connection_type new_connection_type = dc_connection_none;	564	enum dc_connection_type new_connection_type = dc_connection_none;
564		565	DC_LOGGER_INIT(link->ctx->logger);
565	if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)	566	if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
566	return false;	567	return false;
567		568
@@ -927,6 +928,7 @@ static bool construct( · 359 unmodified lines
927	struct integrated_info info = {{{ 0 }}};	928	struct integrated_info info = {{{ 0 }}};
928	struct dc_bios *bios = init_params->dc->ctx->dc_bios;	929	struct dc_bios *bios = init_params->dc->ctx->dc_bios;
929	const struct dc_vbios_funcs *bp_funcs = bios->funcs;	930	const struct dc_vbios_funcs *bp_funcs = bios->funcs;
		931	DC_LOGGER_INIT(dc_ctx->logger);
930		932
931	link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;	933	link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
932	link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;	934	link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
@@ -1135,7 +1137,8 @@ static void dpcd_configure_panel_mode( · 202 unmodified lines
1135	{	1137	{
1136	union dpcd_edp_config edp_config_set;	1138	union dpcd_edp_config edp_config_set;
1137	bool panel_mode_edp = false;	1139	bool panel_mode_edp = false;
1138	struct dc_context *dc_ctx = link->ctx;	1140	DC_LOGGER_INIT(link->ctx->logger);
		1141
1139	memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));	1142	memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1140		1143
1141	if (DP_PANEL_MODE_DEFAULT != panel_mode) {	1144	if (DP_PANEL_MODE_DEFAULT != panel_mode) {
@@ -1183,16 +1186,21 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) · 41 unmodified lines
1183	{	1186	{
1184	struct dc_stream_state *stream = pipe_ctx->stream;	1187	struct dc_stream_state *stream = pipe_ctx->stream;
1185	struct dc_link *link = stream->sink->link;	1188	struct dc_link *link = stream->sink->link;
1186	union down_spread_ctrl downspread;	1189	union down_spread_ctrl old_downspread;
		1190	union down_spread_ctrl new_downspread;
1187		1191
1188	core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,	1192	core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1189	&downspread.raw, sizeof(downspread));	1193	&old_downspread.raw, sizeof(old_downspread));
1190		1194
1191	downspread.bits.IGNORE_MSA_TIMING_PARAM =	1195	new_downspread.raw = old_downspread.raw;
		1196
		1197	new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1192	(stream->ignore_msa_timing_param) ? 1 : 0;	1198	(stream->ignore_msa_timing_param) ? 1 : 0;
1193		1199
1194	core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,	1200	if (new_downspread.raw != old_downspread.raw) {
1195	&downspread.raw, sizeof(downspread));	1201	core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
		1202	&new_downspread.raw, sizeof(new_downspread));
		1203	}
1196	}	1204	}
1197		1205
1198	static enum dc_status enable_link_dp(	1206	static enum dc_status enable_link_dp(
@@ -1843,9 +1851,22 @@ static void disable_link(struct dc_link *link, enum signal_type signal) · 644 unmodified lines
1843		1851
1844	static bool dp_active_dongle_validate_timing(	1852	static bool dp_active_dongle_validate_timing(
1845	const struct dc_crtc_timing *timing,	1853	const struct dc_crtc_timing *timing,
1846	const struct dc_dongle_caps *dongle_caps)	1854	const struct dpcd_caps *dpcd_caps)
1847	{	1855	{
1848	unsigned int required_pix_clk = timing->pix_clk_khz;	1856	unsigned int required_pix_clk = timing->pix_clk_khz;
		1857	const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
		1858
		1859	switch (dpcd_caps->dongle_type) {
		1860	case DISPLAY_DONGLE_DP_VGA_CONVERTER:
		1861	case DISPLAY_DONGLE_DP_DVI_CONVERTER:
		1862	case DISPLAY_DONGLE_DP_DVI_DONGLE:
		1863	if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
		1864	return true;
		1865	else
		1866	return false;
		1867	default:
		1868	break;
		1869	}
1849		1870
1850	if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER \|\|	1871	if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER \|\|
1851	dongle_caps->extendedCapValid == false)	1872	dongle_caps->extendedCapValid == false)
@@ -1911,7 +1932,7 @@ enum dc_status dc_link_validate_mode_timing( · 59 unmodified lines
1911	const struct dc_crtc_timing *timing)	1932	const struct dc_crtc_timing *timing)
1912	{	1933	{
1913	uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;	1934	uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
1914	struct dc_dongle_caps *dongle_caps = &link->dpcd_caps.dongle_caps;	1935	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1915		1936
1916	/* A hack to avoid failing any modes for EDID override feature on	1937	/* A hack to avoid failing any modes for EDID override feature on
1917	* topology change such as lower quality cable for DP or different dongle	1938	* topology change such as lower quality cable for DP or different dongle
@@ -1924,7 +1945,7 @@ enum dc_status dc_link_validate_mode_timing( · 6 unmodified lines
1924	return DC_EXCEED_DONGLE_CAP;	1945	return DC_EXCEED_DONGLE_CAP;
1925		1946
1926	/* Active Dongle*/	1947	/* Active Dongle*/
1927	if (!dp_active_dongle_validate_timing(timing, dongle_caps))	1948	if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
1928	return DC_EXCEED_DONGLE_CAP;	1949	return DC_EXCEED_DONGLE_CAP;
1929		1950
1930	switch (stream->signal) {	1951	switch (stream->signal) {
@@ -1950,10 +1971,10 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, · 19 unmodified lines
1950	struct dc *core_dc = link->ctx->dc;	1971	struct dc *core_dc = link->ctx->dc;
1951	struct abm *abm = core_dc->res_pool->abm;	1972	struct abm *abm = core_dc->res_pool->abm;
1952	struct dmcu *dmcu = core_dc->res_pool->dmcu;	1973	struct dmcu *dmcu = core_dc->res_pool->dmcu;
1953	struct dc_context *dc_ctx = link->ctx;
1954	unsigned int controller_id = 0;	1974	unsigned int controller_id = 0;
1955	bool use_smooth_brightness = true;	1975	bool use_smooth_brightness = true;
1956	int i;	1976	int i;
		1977	DC_LOGGER_INIT(link->ctx->logger);
1957		1978
1958	if ((dmcu == NULL) \|\|	1979	if ((dmcu == NULL) \|\|
1959	(abm == NULL) \|\|	1980	(abm == NULL) \|\|
@@ -1961,7 +1982,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, · 1 unmodified line
1961	return false;	1982	return false;
1962		1983
1963	if (stream) {	1984	if (stream) {
1964	if (stream->bl_pwm_level == 0)	1985	if (stream->bl_pwm_level == EDP_BACKLIGHT_RAMP_DISABLE_LEVEL)
1965	frame_ramp = 0;	1986	frame_ramp = 0;
1966		1987
1967	((struct dc_stream_state *)stream)->bl_pwm_level = level;	1988	((struct dc_stream_state *)stream)->bl_pwm_level = level;
@@ -2149,8 +2170,8 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) · 181 unmodified lines
2149	struct fixed31_32 avg_time_slots_per_mtp;	2170	struct fixed31_32 avg_time_slots_per_mtp;
2150	struct fixed31_32 pbn;	2171	struct fixed31_32 pbn;
2151	struct fixed31_32 pbn_per_slot;	2172	struct fixed31_32 pbn_per_slot;
2152	struct dc_context *dc_ctx = link->ctx;
2153	uint8_t i;	2173	uint8_t i;
		2174	DC_LOGGER_INIT(link->ctx->logger);
2154		2175
2155	/* enable_link_dp_mst already check link->enabled_stream_count	2176	/* enable_link_dp_mst already check link->enabled_stream_count
2156	* and stream is in link->stream[]. This is called during set mode,	2177	* and stream is in link->stream[]. This is called during set mode,
@@ -2178,11 +2199,11 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) · 21 unmodified lines
2178	link->mst_stream_alloc_table.stream_count);	2199	link->mst_stream_alloc_table.stream_count);
2179		2200
2180	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {	2201	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2181	DC_LOG_MST("stream_enc[%d]: 0x%x "	2202	DC_LOG_MST("stream_enc[%d]: %p "
2182	"stream[%d].vcp_id: %d "	2203	"stream[%d].vcp_id: %d "
2183	"stream[%d].slot_count: %d\n",	2204	"stream[%d].slot_count: %d\n",
2184	i,	2205	i,
2185	link->mst_stream_alloc_table.stream_allocations[i].stream_enc,	2206	(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2186	i,	2207	i,
2187	link->mst_stream_alloc_table.stream_allocations[i].vcp_id,	2208	link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2188	i,	2209	i,
@@ -2229,7 +2250,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) · 40 unmodified lines
2229	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);	2250	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
2230	uint8_t i;	2251	uint8_t i;
2231	bool mst_mode = (link->type == dc_connection_mst_branch);	2252	bool mst_mode = (link->type == dc_connection_mst_branch);
2232	struct dc_context *dc_ctx = link->ctx;	2253	DC_LOGGER_INIT(link->ctx->logger);
2233		2254
2234	/* deallocate_mst_payload is called before disable link. When mode or	2255	/* deallocate_mst_payload is called before disable link. When mode or
2235	* disable/enable monitor, new stream is created which is not in link	2256	* disable/enable monitor, new stream is created which is not in link
@@ -2268,11 +2289,11 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) · 32 unmodified lines
2268	link->mst_stream_alloc_table.stream_count);	2289	link->mst_stream_alloc_table.stream_count);
2269		2290
2270	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {	2291	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2271	DC_LOG_MST("stream_enc[%d]: 0x%x "	2292	DC_LOG_MST("stream_enc[%d]: %p "
2272	"stream[%d].vcp_id: %d "	2293	"stream[%d].vcp_id: %d "
2273	"stream[%d].slot_count: %d\n",	2294	"stream[%d].slot_count: %d\n",
2274	i,	2295	i,
2275	link->mst_stream_alloc_table.stream_allocations[i].stream_enc,	2296	(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2276	i,	2297	i,
2277	link->mst_stream_alloc_table.stream_allocations[i].vcp_id,	2298	link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2278	i,	2299	i,
@@ -2302,8 +2323,8 @@ void core_link_enable_stream( · 23 unmodified lines
2302	struct pipe_ctx *pipe_ctx)	2323	struct pipe_ctx *pipe_ctx)
2303	{	2324	{
2304	struct dc *core_dc = pipe_ctx->stream->ctx->dc;	2325	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2305	struct dc_context *dc_ctx = pipe_ctx->stream->ctx;
2306	enum dc_status status;	2326	enum dc_status status;
		2327	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2307		2328
2308	/* eDP lit up by bios already, no need to enable again. */	2329	/* eDP lit up by bios already, no need to enable again. */
2309	if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&	2330	if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c+7−3

 	return ret;
 }
-ssize_t dal_ddc_service_read_dpcd_data(
+enum ddc_result dal_ddc_service_read_dpcd_data(
 	struct ddc_service *ddc,
 	bool i2c,
 	enum i2c_mot_mode mot,
 	uint32_t address,
 	uint8_t *data,
-	uint32_t len)
+	uint32_t len,
+	uint32_t *read)
 {
 	struct aux_payload read_payload = {
 		.i2c_over_aux = i2c,
 		.mot = mot
 	};
+	*read = 0;
 	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
 		BREAK_TO_DEBUGGER();
 		return DDC_RESULT_FAILED_INVALID_OPERATION;
 		ddc->ctx->i2caux,
 		ddc->ddc_pin,
 		&command)) {
-		return (ssize_t)command.payloads->length;
+		*read = command.payloads->length;
+		return DDC_RESULT_SUCESSFULL;
 	}
 	return DDC_RESULT_FAILED_OPERATION;

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+23−7

 {
 	uint32_t bits_per_channel = 0;
 	uint32_t kbps;
-	switch (timing->display_color_depth) {
+	switch (timing->display_color_depth) {
 	case COLOR_DEPTH_666:
 		bits_per_channel = 6;
 		break;
 	default:
 		break;
 	}
 	ASSERT(bits_per_channel != 0);
 	kbps = timing->pix_clk_khz;
 	kbps *= bits_per_channel;
-	if (timing->flags.Y_ONLY != 1)
+	if (timing->flags.Y_ONLY != 1) {
 		/*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
 		kbps *= 3;
+		if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+			kbps /= 2;
+		else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+			kbps = kbps * 2 / 3;
+	}
 	return kbps;
 	union edp_configuration_cap edp_config_cap;
 	union dp_downstream_port_present ds_port = { 0 };
 	enum dc_status status = DC_ERROR_UNEXPECTED;
+	uint32_t read_dpcd_retry_cnt = 3;
+	int i;
 	memset(dpcd_data, '\0', sizeof(dpcd_data));
 	memset(&down_strm_port_count,
 	memset(&edp_config_cap, '\0',
 		sizeof(union edp_configuration_cap));
-	status = core_link_read_dpcd(
+	for (i = 0; i < read_dpcd_retry_cnt; i++) {
-			link,
+		status = core_link_read_dpcd(
-			DP_DPCD_REV,
+				link,
-			dpcd_data,
+				DP_DPCD_REV,
-			sizeof(dpcd_data));
+				dpcd_data,
+				sizeof(dpcd_data));
+		if (status == DC_OK)
+			break;
+	}
 	if (status != DC_OK) {
 		dm_error("%s: Read dpcd data failed.\n", __func__);
 void detect_edp_sink_caps(struct dc_link *link)
 {
 	retrieve_link_cap(link);
+	if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
+		link->reported_link_cap.link_rate = LINK_RATE_HIGH2;
 	link->verified_link_cap = link->reported_link_cap;
 }

drivers/gpu/drm/amd/display/dc/core/dc_resource.c+94−178

@@ -45,8 +45,9 @@ · 44 unmodified lines
45	#include "dcn10/dcn10_resource.h"	45	#include "dcn10/dcn10_resource.h"
46	#endif	46	#endif
47	#include "dce120/dce120_resource.h"	47	#include "dce120/dce120_resource.h"
48	#define DC_LOGGER \	48
49	ctx->logger	49	#define DC_LOGGER_INIT(logger)
		50
50	enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)	51	enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
51	{	52	{
52	enum dce_version dc_version = DCE_VERSION_UNKNOWN;	53	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
@@ -78,6 +79,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) · 25 unmodified lines
78	ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {	79	ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
79	dc_version = DCE_VERSION_11_2;	80	dc_version = DCE_VERSION_11_2;
80	}	81	}
		82	#if defined(CONFIG_DRM_AMD_DC_VEGAM)
		83	if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
		84	dc_version = DCE_VERSION_11_22;
		85	#endif
81	break;	86	break;
82	case FAMILY_AI:	87	case FAMILY_AI:
83	dc_version = DCE_VERSION_12_0;	88	dc_version = DCE_VERSION_12_0;
@@ -124,6 +129,9 @@ struct resource_pool *dc_create_resource_pool( · 40 unmodified lines
124	num_virtual_links, dc, asic_id);	129	num_virtual_links, dc, asic_id);
125	break;	130	break;
126	case DCE_VERSION_11_2:	131	case DCE_VERSION_11_2:
		132	#if defined(CONFIG_DRM_AMD_DC_VEGAM)
		133	case DCE_VERSION_11_22:
		134	#endif
127	res_pool = dce112_create_resource_pool(	135	res_pool = dce112_create_resource_pool(
128	num_virtual_links, dc);	136	num_virtual_links, dc);
129	break;	137	break;
@@ -835,7 +843,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 705 unmodified lines
835	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;	843	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
836	struct view recout_skip = { 0 };	844	struct view recout_skip = { 0 };
837	bool res = false;	845	bool res = false;
838	struct dc_context *ctx = pipe_ctx->stream->ctx;	846	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
839	/* Important: scaling ratio calculation requires pixel format,	847	/* Important: scaling ratio calculation requires pixel format,
840	* lb depth calculation requires recout and taps require scaling ratios.	848	* lb depth calculation requires recout and taps require scaling ratios.
841	* Inits require viewport, taps, ratios and recout of split pipe	849	* Inits require viewport, taps, ratios and recout of split pipe
@@ -843,6 +851,9 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 1 unmodified line
843	pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(	851	pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
844	pipe_ctx->plane_state->format);	852	pipe_ctx->plane_state->format);
845		853
		854	if (pipe_ctx->stream->timing.flags.INTERLACE)
		855	pipe_ctx->stream->dst.height *= 2;
		856
846	calculate_scaling_ratios(pipe_ctx);	857	calculate_scaling_ratios(pipe_ctx);
847		858
848	calculate_viewport(pipe_ctx);	859	calculate_viewport(pipe_ctx);
@@ -863,6 +874,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 14 unmodified lines
863		874
864	pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;	875	pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
865	pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;	876	pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
		877	if (pipe_ctx->stream->timing.flags.INTERLACE)
		878	pipe_ctx->plane_res.scl_data.v_active *= 2;
866		879
867		880
868	/* Taps calculations */	881	/* Taps calculations */
@@ -908,6 +921,9 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 39 unmodified lines
908	plane_state->dst_rect.x,	921	plane_state->dst_rect.x,
909	plane_state->dst_rect.y);	922	plane_state->dst_rect.y);
910		923
		924	if (pipe_ctx->stream->timing.flags.INTERLACE)
		925	pipe_ctx->stream->dst.height /= 2;
		926
911	return res;	927	return res;
912	}	928	}
913		929
@@ -1294,6 +1310,19 @@ bool dc_add_all_planes_for_stream( · 380 unmodified lines
1294	}	1310	}
1295		1311
1296		1312
		1313	static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
		1314	struct dc_stream_state *new_stream)
		1315	{
		1316	if (cur_stream == NULL)
		1317	return true;
		1318
		1319	if (memcmp(&cur_stream->hdr_static_metadata,
		1320	&new_stream->hdr_static_metadata,
		1321	sizeof(struct dc_info_packet)) != 0)
		1322	return true;
		1323
		1324	return false;
		1325	}
1297		1326
1298	static bool is_timing_changed(struct dc_stream_state *cur_stream,	1327	static bool is_timing_changed(struct dc_stream_state *cur_stream,
1299	struct dc_stream_state *new_stream)	1328	struct dc_stream_state *new_stream)
@@ -1329,6 +1358,9 @@ static bool are_stream_backends_same( · 29 unmodified lines
1329	if (is_timing_changed(stream_a, stream_b))	1358	if (is_timing_changed(stream_a, stream_b))
1330	return false;	1359	return false;
1331		1360
		1361	if (is_hdr_static_meta_changed(stream_a, stream_b))
		1362	return false;
		1363
1332	return true;	1364	return true;
1333	}	1365	}
1334		1366
@@ -1599,18 +1631,6 @@ enum dc_status dc_remove_stream_from_ctx( · 264 unmodified lines
1599	return DC_OK;	1631	return DC_OK;
1600	}	1632	}
1601		1633
1602	static void copy_pipe_ctx(
1603	const struct pipe_ctx from_pipe_ctx, struct pipe_ctx to_pipe_ctx)
1604	{
1605	struct dc_plane_state *plane_state = to_pipe_ctx->plane_state;
1606	struct dc_stream_state *stream = to_pipe_ctx->stream;
1607
1608	to_pipe_ctx = from_pipe_ctx;
1609	to_pipe_ctx->stream = stream;
1610	if (plane_state != NULL)
1611	to_pipe_ctx->plane_state = plane_state;
1612	}
1613
1614	static struct dc_stream_state *find_pll_sharable_stream(	1634	static struct dc_stream_state *find_pll_sharable_stream(
1615	struct dc_stream_state *stream_needs_pll,	1635	struct dc_stream_state *stream_needs_pll,
1616	struct dc_state *context)	1636	struct dc_state *context)
@@ -1703,7 +1723,7 @@ enum dc_status resource_map_pool_resources( · 86 unmodified lines
1703	pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);	1723	pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1704	#endif	1724	#endif
1705		1725
1706	if (pipe_idx < 0)	1726	if (pipe_idx < 0 \|\| context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1707	return DC_NO_CONTROLLER_RESOURCE;	1727	return DC_NO_CONTROLLER_RESOURCE;
1708		1728
1709	pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];	1729	pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
@@ -1752,26 +1772,6 @@ enum dc_status resource_map_pool_resources( · 42 unmodified lines
1752	return DC_ERROR_UNEXPECTED;	1772	return DC_ERROR_UNEXPECTED;
1753	}	1773	}
1754		1774
1755	/* first stream in the context is used to populate the rest */
1756	void validate_guaranteed_copy_streams(
1757	struct dc_state *context,
1758	int max_streams)
1759	{
1760	int i;
1761
1762	for (i = 1; i < max_streams; i++) {
1763	context->streams[i] = context->streams[0];
1764
1765	copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
1766	&context->res_ctx.pipe_ctx[i]);
1767	context->res_ctx.pipe_ctx[i].stream =
1768	context->res_ctx.pipe_ctx[0].stream;
1769
1770	dc_stream_retain(context->streams[i]);
1771	context->stream_count++;
1772	}
1773	}
1774
1775	void dc_resource_state_copy_construct_current(	1775	void dc_resource_state_copy_construct_current(
1776	const struct dc *dc,	1776	const struct dc *dc,
1777	struct dc_state *dst_ctx)	1777	struct dc_state *dst_ctx)
@@ -1798,9 +1798,9 @@ enum dc_status dc_validate_global_state( · 20 unmodified lines
1798	return DC_ERROR_UNEXPECTED;	1798	return DC_ERROR_UNEXPECTED;
1799		1799
1800	if (dc->res_pool->funcs->validate_global) {	1800	if (dc->res_pool->funcs->validate_global) {
1801	result = dc->res_pool->funcs->validate_global(dc, new_ctx);	1801	result = dc->res_pool->funcs->validate_global(dc, new_ctx);
1802	if (result != DC_OK)	1802	if (result != DC_OK)
1803	return result;	1803	return result;
1804	}	1804	}
1805		1805
1806	for (i = 0; i < new_ctx->stream_count; i++) {	1806	for (i = 0; i < new_ctx->stream_count; i++) {
@@ -1843,7 +1843,7 @@ enum dc_status dc_validate_global_state( · 36 unmodified lines
1843	}	1843	}
1844		1844
1845	static void patch_gamut_packet_checksum(	1845	static void patch_gamut_packet_checksum(
1846	struct encoder_info_packet *gamut_packet)	1846	struct dc_info_packet *gamut_packet)
1847	{	1847	{
1848	/* For gamut we recalc checksum */	1848	/* For gamut we recalc checksum */
1849	if (gamut_packet->valid) {	1849	if (gamut_packet->valid) {
@@ -1862,12 +1862,11 @@ static void patch_gamut_packet_checksum( · 12 unmodified lines
1862	}	1862	}
1863		1863
1864	static void set_avi_info_frame(	1864	static void set_avi_info_frame(
1865	struct encoder_info_packet *info_packet,	1865	struct dc_info_packet *info_packet,
1866	struct pipe_ctx *pipe_ctx)	1866	struct pipe_ctx *pipe_ctx)
1867	{	1867	{
1868	struct dc_stream_state *stream = pipe_ctx->stream;	1868	struct dc_stream_state *stream = pipe_ctx->stream;
1869	enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;	1869	enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
1870	struct info_frame info_frame = { {0} };
1871	uint32_t pixel_encoding = 0;	1870	uint32_t pixel_encoding = 0;
1872	enum scanning_type scan_type = SCANNING_TYPE_NODATA;	1871	enum scanning_type scan_type = SCANNING_TYPE_NODATA;
1873	enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;	1872	enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
@@ -1877,22 +1876,24 @@ static void set_avi_info_frame( · 3 unmodified lines
1877	unsigned int cn0_cn1_value = 0;	1876	unsigned int cn0_cn1_value = 0;
1878	uint8_t *check_sum = NULL;	1877	uint8_t *check_sum = NULL;
1879	uint8_t byte_index = 0;	1878	uint8_t byte_index = 0;
1880	union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;	1879	union hdmi_info_packet hdmi_info;
1881	union display_content_support support = {0};	1880	union display_content_support support = {0};
1882	unsigned int vic = pipe_ctx->stream->timing.vic;	1881	unsigned int vic = pipe_ctx->stream->timing.vic;
1883	enum dc_timing_3d_format format;	1882	enum dc_timing_3d_format format;
1884		1883
		1884	memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
		1885
1885	color_space = pipe_ctx->stream->output_color_space;	1886	color_space = pipe_ctx->stream->output_color_space;
1886	if (color_space == COLOR_SPACE_UNKNOWN)	1887	if (color_space == COLOR_SPACE_UNKNOWN)
1887	color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?	1888	color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
1888	COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;	1889	COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
1889		1890
1890	/* Initialize header */	1891	/* Initialize header */
1891	hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;	1892	hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
1892	/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall	1893	/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
1893	* not be used in HDMI 2.0 (Section 10.1) */	1894	* not be used in HDMI 2.0 (Section 10.1) */
1894	hdmi_info->bits.header.version = 2;	1895	hdmi_info.bits.header.version = 2;
1895	hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;	1896	hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
1896		1897
1897	/*	1898	/*
1898	* IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built	1899	* IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
@@ -1918,39 +1919,39 @@ static void set_avi_info_frame( · 19 unmodified lines
1918		1919
1919	/* Y0_Y1_Y2 : The pixel encoding */	1920	/* Y0_Y1_Y2 : The pixel encoding */
1920	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */	1921	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
1921	hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;	1922	hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
1922		1923
1923	/* A0 = 1 Active Format Information valid */	1924	/* A0 = 1 Active Format Information valid */
1924	hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;	1925	hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
1925		1926
1926	/* B0, B1 = 3; Bar info data is valid */	1927	/* B0, B1 = 3; Bar info data is valid */
1927	hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;	1928	hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
1928		1929
1929	hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;	1930	hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
1930		1931
1931	/* S0, S1 : Underscan / Overscan */	1932	/* S0, S1 : Underscan / Overscan */
1932	/* TODO: un-hardcode scan type */	1933	/* TODO: un-hardcode scan type */
1933	scan_type = SCANNING_TYPE_UNDERSCAN;	1934	scan_type = SCANNING_TYPE_UNDERSCAN;
1934	hdmi_info->bits.S0_S1 = scan_type;	1935	hdmi_info.bits.S0_S1 = scan_type;
1935		1936
1936	/* C0, C1 : Colorimetry */	1937	/* C0, C1 : Colorimetry */
1937	if (color_space == COLOR_SPACE_YCBCR709 \|\|	1938	if (color_space == COLOR_SPACE_YCBCR709 \|\|
1938	color_space == COLOR_SPACE_YCBCR709_LIMITED)	1939	color_space == COLOR_SPACE_YCBCR709_LIMITED)
1939	hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;	1940	hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
1940	else if (color_space == COLOR_SPACE_YCBCR601 \|\|	1941	else if (color_space == COLOR_SPACE_YCBCR601 \|\|
1941	color_space == COLOR_SPACE_YCBCR601_LIMITED)	1942	color_space == COLOR_SPACE_YCBCR601_LIMITED)
1942	hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;	1943	hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
1943	else {	1944	else {
1944	hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;	1945	hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
1945	}	1946	}
1946	if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE \|\|	1947	if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE \|\|
1947	color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE \|\|	1948	color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE \|\|
1948	color_space == COLOR_SPACE_2020_YCBCR) {	1949	color_space == COLOR_SPACE_2020_YCBCR) {
1949	hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;	1950	hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
1950	hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;	1951	hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
1951	} else if (color_space == COLOR_SPACE_ADOBERGB) {	1952	} else if (color_space == COLOR_SPACE_ADOBERGB) {
1952	hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;	1953	hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
1953	hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;	1954	hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
1954	}	1955	}
1955		1956
1956	/* TODO: un-hardcode aspect ratio */	1957	/* TODO: un-hardcode aspect ratio */
@@ -1959,18 +1960,18 @@ static void set_avi_info_frame( · 2 unmodified lines
1959	switch (aspect) {	1960	switch (aspect) {
1960	case ASPECT_RATIO_4_3:	1961	case ASPECT_RATIO_4_3:
1961	case ASPECT_RATIO_16_9:	1962	case ASPECT_RATIO_16_9:
1962	hdmi_info->bits.M0_M1 = aspect;	1963	hdmi_info.bits.M0_M1 = aspect;
1963	break;	1964	break;
1964		1965
1965	case ASPECT_RATIO_NO_DATA:	1966	case ASPECT_RATIO_NO_DATA:
1966	case ASPECT_RATIO_64_27:	1967	case ASPECT_RATIO_64_27:
1967	case ASPECT_RATIO_256_135:	1968	case ASPECT_RATIO_256_135:
1968	default:	1969	default:
1969	hdmi_info->bits.M0_M1 = 0;	1970	hdmi_info.bits.M0_M1 = 0;
1970	}	1971	}
1971		1972
1972	/* Active Format Aspect ratio - same as Picture Aspect Ratio. */	1973	/* Active Format Aspect ratio - same as Picture Aspect Ratio. */
1973	hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;	1974	hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
1974		1975
1975	/* TODO: un-hardcode cn0_cn1 and itc */	1976	/* TODO: un-hardcode cn0_cn1 and itc */
1976		1977
@@ -2013,8 +2014,8 @@ static void set_avi_info_frame( · 36 unmodified lines
2013	}	2014	}
2014	}	2015	}
2015	}	2016	}
2016	hdmi_info->bits.CN0_CN1 = cn0_cn1_value;	2017	hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2017	hdmi_info->bits.ITC = itc_value;	2018	hdmi_info.bits.ITC = itc_value;
2018	}	2019	}
2019		2020
2020	/* TODO : We should handle YCC quantization */	2021	/* TODO : We should handle YCC quantization */
@@ -2023,19 +2024,19 @@ static void set_avi_info_frame( · 2 unmodified lines
2023	stream->sink->edid_caps.qy_bit == 1) {	2024	stream->sink->edid_caps.qy_bit == 1) {
2024	if (color_space == COLOR_SPACE_SRGB \|\|	2025	if (color_space == COLOR_SPACE_SRGB \|\|
2025	color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {	2026	color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
2026	hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;	2027	hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2027	hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;	2028	hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
2028	} else if (color_space == COLOR_SPACE_SRGB_LIMITED \|\|	2029	} else if (color_space == COLOR_SPACE_SRGB_LIMITED \|\|
2029	color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {	2030	color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
2030	hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;	2031	hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2031	hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;	2032	hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2032	} else {	2033	} else {
2033	hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;	2034	hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2034	hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;	2035	hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2035	}	2036	}
2036	} else {	2037	} else {
2037	hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;	2038	hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2038	hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;	2039	hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2039	}	2040	}
2040		2041
2041	///VIC	2042	///VIC
@@ -2060,51 +2061,49 @@ static void set_avi_info_frame( · 18 unmodified lines
2060	break;	2061	break;
2061	}	2062	}
2062	}	2063	}
2063	hdmi_info->bits.VIC0_VIC7 = vic;	2064	hdmi_info.bits.VIC0_VIC7 = vic;
2064		2065
2065	/* pixel repetition	2066	/* pixel repetition
2066	* PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel	2067	* PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2067	* repetition start from 1 */	2068	* repetition start from 1 */
2068	hdmi_info->bits.PR0_PR3 = 0;	2069	hdmi_info.bits.PR0_PR3 = 0;
2069		2070
2070	/* Bar Info	2071	/* Bar Info
2071	* barTop: Line Number of End of Top Bar.	2072	* barTop: Line Number of End of Top Bar.
2072	* barBottom: Line Number of Start of Bottom Bar.	2073	* barBottom: Line Number of Start of Bottom Bar.
2073	* barLeft: Pixel Number of End of Left Bar.	2074	* barLeft: Pixel Number of End of Left Bar.
2074	* barRight: Pixel Number of Start of Right Bar. */	2075	* barRight: Pixel Number of Start of Right Bar. */
2075	hdmi_info->bits.bar_top = stream->timing.v_border_top;	2076	hdmi_info.bits.bar_top = stream->timing.v_border_top;
2076	hdmi_info->bits.bar_bottom = (stream->timing.v_total	2077	hdmi_info.bits.bar_bottom = (stream->timing.v_total
2077	- stream->timing.v_border_bottom + 1);	2078	- stream->timing.v_border_bottom + 1);
2078	hdmi_info->bits.bar_left = stream->timing.h_border_left;	2079	hdmi_info.bits.bar_left = stream->timing.h_border_left;
2079	hdmi_info->bits.bar_right = (stream->timing.h_total	2080	hdmi_info.bits.bar_right = (stream->timing.h_total
2080	- stream->timing.h_border_right + 1);	2081	- stream->timing.h_border_right + 1);
2081		2082
2082	/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */	2083	/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
2083	check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];	2084	check_sum = &hdmi_info.packet_raw_data.sb[0];
2084		2085
2085	*check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;	2086	*check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
2086		2087
2087	for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)	2088	for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
2088	*check_sum += hdmi_info->packet_raw_data.sb[byte_index];	2089	*check_sum += hdmi_info.packet_raw_data.sb[byte_index];
2089		2090
2090	/* one byte complement */	2091	/* one byte complement */
2091	check_sum = (uint8_t) (0x100 - check_sum);	2092	check_sum = (uint8_t) (0x100 - check_sum);
2092		2093
2093	/* Store in hw_path_mode */	2094	/* Store in hw_path_mode */
2094	info_packet->hb0 = hdmi_info->packet_raw_data.hb0;	2095	info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2095	info_packet->hb1 = hdmi_info->packet_raw_data.hb1;	2096	info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2096	info_packet->hb2 = hdmi_info->packet_raw_data.hb2;	2097	info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
2097		2098
2098	for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.	2099	for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2099	info_packet_hdmi.packet_raw_data.sb); byte_index++)	2100	info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
2100	info_packet->sb[byte_index] = info_frame.avi_info_packet.
2101	info_packet_hdmi.packet_raw_data.sb[byte_index];
2102		2101
2103	info_packet->valid = true;	2102	info_packet->valid = true;
2104	}	2103	}
2105		2104
2106	static void set_vendor_info_packet(	2105	static void set_vendor_info_packet(
2107	struct encoder_info_packet *info_packet,	2106	struct dc_info_packet *info_packet,
2108	struct dc_stream_state *stream)	2107	struct dc_stream_state *stream)
2109	{	2108	{
2110	uint32_t length = 0;	2109	uint32_t length = 0;
@@ -2217,7 +2216,7 @@ static void set_vendor_info_packet( · 106 unmodified lines
2217	}	2216	}
2218		2217
2219	static void set_spd_info_packet(	2218	static void set_spd_info_packet(
2220	struct encoder_info_packet *info_packet,	2219	struct dc_info_packet *info_packet,
2221	struct dc_stream_state *stream)	2220	struct dc_stream_state *stream)
2222	{	2221	{
2223	/* SPD info packet for FreeSync */	2222	/* SPD info packet for FreeSync */
@@ -2338,104 +2337,19 @@ static void set_spd_info_packet( · 114 unmodified lines
2338	}	2337	}
2339		2338
2340	static void set_hdr_static_info_packet(	2339	static void set_hdr_static_info_packet(
2341	struct encoder_info_packet *info_packet,	2340	struct dc_info_packet *info_packet,
2342	struct dc_stream_state *stream)	2341	struct dc_stream_state *stream)
2343	{	2342	{
2344	uint16_t i = 0;	2343	/* HDR Static Metadata info packet for HDR10 */
2345	enum signal_type signal = stream->signal;
2346	uint32_t data;
2347		2344
2348	if (!stream->hdr_static_metadata.hdr_supported)	2345	if (!stream->hdr_static_metadata.valid)
2349	return;	2346	return;
2350		2347
2351	if (dc_is_hdmi_signal(signal)) {	2348	*info_packet = stream->hdr_static_metadata;
2352	info_packet->valid = true;
2353
2354	info_packet->hb0 = 0x87;
2355	info_packet->hb1 = 0x01;
2356	info_packet->hb2 = 0x1A;
2357	i = 1;
2358	} else if (dc_is_dp_signal(signal)) {
2359	info_packet->valid = true;
2360
2361	info_packet->hb0 = 0x00;
2362	info_packet->hb1 = 0x87;
2363	info_packet->hb2 = 0x1D;
2364	info_packet->hb3 = (0x13 << 2);
2365	i = 2;
2366	}
2367
2368	data = stream->hdr_static_metadata.is_hdr;
2369	info_packet->sb[i++] = data ? 0x02 : 0x00;
2370	info_packet->sb[i++] = 0x00;
2371
2372	data = stream->hdr_static_metadata.chromaticity_green_x / 2;
2373	info_packet->sb[i++] = data & 0xFF;
2374	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2375
2376	data = stream->hdr_static_metadata.chromaticity_green_y / 2;
2377	info_packet->sb[i++] = data & 0xFF;
2378	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2379
2380	data = stream->hdr_static_metadata.chromaticity_blue_x / 2;
2381	info_packet->sb[i++] = data & 0xFF;
2382	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2383
2384	data = stream->hdr_static_metadata.chromaticity_blue_y / 2;
2385	info_packet->sb[i++] = data & 0xFF;
2386	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2387
2388	data = stream->hdr_static_metadata.chromaticity_red_x / 2;
2389	info_packet->sb[i++] = data & 0xFF;
2390	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2391
2392	data = stream->hdr_static_metadata.chromaticity_red_y / 2;
2393	info_packet->sb[i++] = data & 0xFF;
2394	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2395
2396	data = stream->hdr_static_metadata.chromaticity_white_point_x / 2;
2397	info_packet->sb[i++] = data & 0xFF;
2398	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2399
2400	data = stream->hdr_static_metadata.chromaticity_white_point_y / 2;
2401	info_packet->sb[i++] = data & 0xFF;
2402	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2403
2404	data = stream->hdr_static_metadata.max_luminance;
2405	info_packet->sb[i++] = data & 0xFF;
2406	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2407
2408	data = stream->hdr_static_metadata.min_luminance;
2409	info_packet->sb[i++] = data & 0xFF;
2410	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2411
2412	data = stream->hdr_static_metadata.maximum_content_light_level;
2413	info_packet->sb[i++] = data & 0xFF;
2414	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2415
2416	data = stream->hdr_static_metadata.maximum_frame_average_light_level;
2417	info_packet->sb[i++] = data & 0xFF;
2418	info_packet->sb[i++] = (data & 0xFF00) >> 8;
2419
2420	if (dc_is_hdmi_signal(signal)) {
2421	uint32_t checksum = 0;
2422
2423	checksum += info_packet->hb0;
2424	checksum += info_packet->hb1;
2425	checksum += info_packet->hb2;
2426
2427	for (i = 1; i <= info_packet->hb2; i++)
2428	checksum += info_packet->sb[i];
2429
2430	info_packet->sb[0] = 0x100 - checksum;
2431	} else if (dc_is_dp_signal(signal)) {
2432	info_packet->sb[0] = 0x01;
2433	info_packet->sb[1] = 0x1A;
2434	}
2435	}	2349	}
2436		2350
2437	static void set_vsc_info_packet(	2351	static void set_vsc_info_packet(
2438	struct encoder_info_packet *info_packet,	2352	struct dc_info_packet *info_packet,
2439	struct dc_stream_state *stream)	2353	struct dc_stream_state *stream)
2440	{	2354	{
2441	unsigned int vscPacketRevision = 0;	2355	unsigned int vscPacketRevision = 0;
@@ -2650,6 +2564,8 @@ bool pipe_need_reprogram( · 208 unmodified lines
2650	if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))	2564	if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2651	return true;	2565	return true;
2652		2566
		2567	if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
		2568	return true;
2653		2569
2654	return false;	2570	return false;
2655	}	2571	}

drivers/gpu/drm/amd/display/dc/core/dc_stream.c+22−2

 	stream->status.link = stream->sink->link;
 	update_stream_signal(stream);
+	stream->out_transfer_func = dc_create_transfer_func();
+	stream->out_transfer_func->type = TF_TYPE_BYPASS;
 }
 static void destruct(struct dc_stream_state *stream)
 {
 	dc_sink_release(stream->sink);
 	if (stream->out_transfer_func != NULL) {
-		dc_transfer_func_release(
+		dc_transfer_func_release(stream->out_transfer_func);
-				stream->out_transfer_func);
 		stream->out_transfer_func = NULL;
 	}
 }
 	int i;
 	struct dc  *core_dc;
 	struct resource_context *res_ctx;
+	struct pipe_ctx *pipe_to_program = NULL;
 	if (NULL == stream) {
 		dm_error("DC: dc_stream is NULL!\n");
 		if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
 			continue;
+		if (!pipe_to_program) {
+			pipe_to_program = pipe_ctx;
+			core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
+		}
 		core_dc->hwss.set_cursor_attribute(pipe_ctx);
 	}
+	if (pipe_to_program)
+		core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
 	return true;
 }
 	int i;
 	struct dc  *core_dc;
 	struct resource_context *res_ctx;
+	struct pipe_ctx *pipe_to_program = NULL;
 	if (NULL == stream) {
 		dm_error("DC: dc_stream is NULL!\n");
 				!pipe_ctx->plane_res.ipp)
 			continue;
+		if (!pipe_to_program) {
+			pipe_to_program = pipe_ctx;
+			core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
+		}
 		core_dc->hwss.set_cursor_position(pipe_ctx);
 	}
+	if (pipe_to_program)
+		core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
 	return true;
 }

drivers/gpu/drm/amd/display/dc/core/dc_surface.c+14−8

 static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
 {
 	plane_state->ctx = ctx;
+	plane_state->gamma_correction = dc_create_gamma();
+	plane_state->gamma_correction->is_identity = true;
+	plane_state->in_transfer_func = dc_create_transfer_func();
+	plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
 }
 static void destruct(struct dc_plane_state *plane_state)
 {
 	struct dc *core_dc = dc;
-	struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state),
+	struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
-						     GFP_KERNEL);
+						      GFP_KERNEL);
 	if (NULL == plane_state)
 		return NULL;
 {
 	struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
 	destruct(plane_state);
-	kfree(plane_state);
+	kvfree(plane_state);
 }
 void dc_plane_state_release(struct dc_plane_state *plane_state)
 static void dc_gamma_free(struct kref *kref)
 {
 	struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount);
-	kfree(gamma);
+	kvfree(gamma);
 }
 void dc_gamma_release(struct dc_gamma **gamma)
 struct dc_gamma *dc_create_gamma(void)
 {
-	struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL);
+	struct dc_gamma *gamma = kvzalloc(sizeof(*gamma), GFP_KERNEL);
 	if (gamma == NULL)
 		goto alloc_fail;
 static void dc_transfer_func_free(struct kref *kref)
 {
 	struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount);
-	kfree(tf);
+	kvfree(tf);
 }
 void dc_transfer_func_release(struct dc_transfer_func *tf)
 	kref_put(&tf->refcount, dc_transfer_func_free);
 }
-struct dc_transfer_func *dc_create_transfer_func(void)
+struct dc_transfer_func *dc_create_transfer_func()
 {
-	struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL);
+	struct dc_transfer_func *tf = kvzalloc(sizeof(*tf), GFP_KERNEL);
 	if (tf == NULL)
 		goto alloc_fail;

drivers/gpu/drm/amd/display/dc/dc.h+6−24

 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
-#define DC_VER "3.1.38"
+#define DC_VER "3.1.44"
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
 	bool timing_trace;
 	bool clock_trace;
 	bool validation_trace;
+	bool bandwidth_calcs_trace;
 	/* stutter efficiency related */
 	bool disable_stutter;
 	TRANSFER_FUNC_POINTS = 1025
 };
-// Moved here from color module for linux
-enum color_transfer_func {
-	transfer_func_unknown,
-	transfer_func_srgb,
-	transfer_func_bt709,
-	transfer_func_pq2084,
-	transfer_func_pq2084_interim,
-	transfer_func_linear_0_1,
-	transfer_func_linear_0_125,
-	transfer_func_dolbyvision,
-	transfer_func_gamma_22,
-	transfer_func_gamma_26
-};
 struct dc_hdr_static_metadata {
 	/* display chromaticities and white point in units of 0.00001 */
 	unsigned int chromaticity_green_x;
 	uint32_t max_luminance;
 	uint32_t maximum_content_light_level;
 	uint32_t maximum_frame_average_light_level;
-	bool hdr_supported;
-	bool is_hdr;
 };
 enum dc_transfer_func_type {
 		/* Medium updates */
 		uint32_t dcc_change:1;
 		uint32_t color_space_change:1;
-		uint32_t input_tf_change:1;
 		uint32_t horizontal_mirror_change:1;
 		uint32_t per_pixel_alpha_change:1;
 		uint32_t rotation_change:1;
 		uint32_t position_change:1;
 		uint32_t in_transfer_func_change:1;
 		uint32_t input_csc_change:1;
+		uint32_t coeff_reduction_change:1;
 		uint32_t output_tf_change:1;
 		uint32_t pixel_format_change:1;
 	struct dc_gamma *gamma_correction;
 	struct dc_transfer_func *in_transfer_func;
 	struct dc_bias_and_scale *bias_and_scale;
-	struct csc_transform input_csc_color_matrix;
+	struct dc_csc_transform input_csc_color_matrix;
 	struct fixed31_32 coeff_reduction_factor;
 	uint32_t sdr_white_level;
 	struct dc_hdr_static_metadata hdr_static_ctx;
 	enum dc_color_space color_space;
-	enum color_transfer_func input_tf;
 	enum surface_pixel_format format;
 	enum dc_rotation_angle rotation;
 	enum dc_rotation_angle rotation;
 	enum plane_stereo_format stereo_format;
 	enum dc_color_space color_space;
-	enum color_transfer_func input_tf;
 	unsigned int sdr_white_level;
 	bool horizontal_mirror;
 	bool visible;
 	 * null means no updates
 	 */
 	struct dc_gamma *gamma;
-	enum color_transfer_func color_input_tf;
 	struct dc_transfer_func *in_transfer_func;
-	struct csc_transform *input_csc_color_matrix;
+	struct dc_csc_transform *input_csc_color_matrix;
 	struct fixed31_32 *coeff_reduction_factor;
 };
 	struct dc_cursor_attributes attributes;
 };
 /*******************************************************************************
  * Interrupt interfaces
  ******************************************************************************/

drivers/gpu/drm/amd/display/dc/dc_helper.c+59−0

@@ -117,6 +117,65 @@ uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, · 116 unmodified lines
117	return reg_val;	117	return reg_val;
118	}	118	}
119		119
		120	uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
		121	uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
		122	uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
		123	uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
		124	uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
		125	uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
		126	uint8_t shift6, uint32_t mask6, uint32_t *field_value6)
		127	{
		128	uint32_t reg_val = dm_read_reg(ctx, addr);
		129	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
		130	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
		131	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
		132	*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
		133	*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
		134	*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
		135	return reg_val;
		136	}
		137
		138	uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
		139	uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
		140	uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
		141	uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
		142	uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
		143	uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
		144	uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
		145	uint8_t shift7, uint32_t mask7, uint32_t *field_value7)
		146	{
		147	uint32_t reg_val = dm_read_reg(ctx, addr);
		148	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
		149	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
		150	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
		151	*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
		152	*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
		153	*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
		154	*field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
		155	return reg_val;
		156	}
		157
		158	uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
		159	uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
		160	uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
		161	uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
		162	uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
		163	uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
		164	uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
		165	uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
		166	uint8_t shift8, uint32_t mask8, uint32_t *field_value8)
		167	{
		168	uint32_t reg_val = dm_read_reg(ctx, addr);
		169	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
		170	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
		171	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
		172	*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
		173	*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
		174	*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
		175	*field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
		176	*field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8);
		177	return reg_val;
		178	}
120	/* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer	179	/* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer
121	* compiler won't be able to check for size match and is prone to stack corruption type of bugs	180	* compiler won't be able to check for size match and is prone to stack corruption type of bugs
122		181

drivers/gpu/drm/amd/display/dc/dc_hw_types.h+5−0

 	GAMMA_CS_TFM_1D = 3,
 };
+struct dc_csc_transform {
+	uint16_t matrix[12];
+	bool enable_adjustment;
+};
 struct dc_gamma {
 	struct kref refcount;
 	enum dc_gamma_type type;

drivers/gpu/drm/amd/display/dc/dc_link.h+9−0

 	struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
 };
+struct time_stamp {
+	uint64_t edp_poweroff;
+	uint64_t edp_poweron;
+};
+struct link_trace {
+	struct time_stamp time_stamp;
+};
 /*
  * A link contains one or more sinks and their connected status.
  * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
 	struct dc_link_status link_status;
+	struct link_trace link_trace;
 };
 const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);

drivers/gpu/drm/amd/display/dc/dc_stream.h+8−20

 	struct freesync_context freesync_ctx;
-	struct dc_hdr_static_metadata hdr_static_metadata;
+	struct dc_info_packet hdr_static_metadata;
 	struct dc_transfer_func *out_transfer_func;
 	struct colorspace_transform gamut_remap_matrix;
-	struct csc_transform csc_color_matrix;
+	struct dc_csc_transform csc_color_matrix;
 	enum dc_color_space output_color_space;
 	enum dc_dither_option dither_option;
 	enum view_3d_format view_format;
-	enum color_transfer_func output_tf;
 	bool ignore_msa_timing_param;
+	unsigned long long periodic_fn_vsync_delta;
 	/* TODO: custom INFO packets */
 	/* TODO: ABM info (DMCU) */
 	/* PSR info */
 	struct rect src;
 	struct rect dst;
 	struct dc_transfer_func *out_transfer_func;
-	struct dc_hdr_static_metadata *hdr_static_metadata;
+	struct dc_info_packet *hdr_static_metadata;
-	enum color_transfer_func color_output_tf;
 	unsigned int *abm_level;
+	unsigned long long *periodic_fn_vsync_delta;
 };
 bool dc_is_stream_unchanged(
  *   This does not trigger a flip.  No surface address is programmed.
  */
-bool dc_commit_planes_to_stream(
-		struct dc *dc,
-		struct dc_plane_state **plane_states,
-		uint8_t new_plane_count,
-		struct dc_stream_state *dc_stream,
-		struct dc_state *state);
 void dc_commit_updates_for_stream(struct dc *dc,
 		struct dc_surface_update *srf_updates,
 		int surface_count,
 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
-/*
- * This function takes a stream and checks if it is guaranteed to be supported.
- * Guaranteed means that MAX_COFUNC similar streams are supported.
- *
- * After this call:
- *   No hardware is programmed for call.  Only validation is done.
- */
 /*
  * Set up streams and links associated to drive sinks
  * The streams parameter is an absolute set of all active streams.

drivers/gpu/drm/amd/display/dc/dc_types.h+9−6

 	struct fixed31_32 hue;
 };
-enum {
-	MAX_LANES = 2,
-	MAX_COFUNC_PATH = 6,
-	LAYER_INDEX_PRIMARY = -1,
-};
 enum dpcd_downstream_port_max_bpc {
 	DOWN_STREAM_MAX_8BPC = 0,
 	DOWN_STREAM_MAX_10BPC,
 	uint32_t frame_counter;
 };
+struct dc_info_packet {
+	bool valid;
+	uint8_t hb0;
+	uint8_t hb1;
+	uint8_t hb2;
+	uint8_t hb3;
+	uint8_t sb[32];
+};
 #define DC_PLANE_UPDATE_TIMES_MAX 10
 struct dc_plane_flip_time {

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c+5−4

@@ -33,8 +33,9 @@ · 32 unmodified lines
33		33
34	#define CTX \	34	#define CTX \
35	aud->base.ctx	35	aud->base.ctx
36	#define DC_LOGGER \	36
37	aud->base.ctx->logger	37	#define DC_LOGGER_INIT()
		38
38	#define REG(reg)\	39	#define REG(reg)\
39	(aud->regs->reg)	40	(aud->regs->reg)
40		41
@@ -348,8 +349,8 @@ static void set_audio_latency( · 307 unmodified lines
348		349
349	void dce_aud_az_enable(struct audio *audio)	350	void dce_aud_az_enable(struct audio *audio)
350	{	351	{
351	struct dce_audio *aud = DCE_AUD(audio);
352	uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);	352	uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
		353	DC_LOGGER_INIT();
353		354
354	set_reg_field_value(value, 1,	355	set_reg_field_value(value, 1,
355	AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,	356	AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
@@ -371,7 +372,7 @@ void dce_aud_az_enable(struct audio *audio) · 15 unmodified lines
371	void dce_aud_az_disable(struct audio *audio)	372	void dce_aud_az_disable(struct audio *audio)
372	{	373	{
373	uint32_t value;	374	uint32_t value;
374	struct dce_audio *aud = DCE_AUD(audio);	375	DC_LOGGER_INIT();
375		376
376	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);	377	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
377	set_reg_field_value(value, 1,	378	set_reg_field_value(value, 1,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c+12−5

@@ -41,8 +41,9 @@ · 40 unmodified lines
41		41
42	#define CTX \	42	#define CTX \
43	clk_src->base.ctx	43	clk_src->base.ctx
44	#define DC_LOGGER \	44
45	calc_pll_cs->ctx->logger	45	#define DC_LOGGER_INIT()
		46
46	#undef FN	47	#undef FN
47	#define FN(reg_name, field_name) \	48	#define FN(reg_name, field_name) \
48	clk_src->cs_shift->field_name, clk_src->cs_mask->field_name	49	clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
@@ -467,7 +468,7 @@ static uint32_t dce110_get_pix_clk_dividers_helper ( · 418 unmodified lines
467	{	468	{
468	uint32_t field = 0;	469	uint32_t field = 0;
469	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;	470	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
470	struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;	471	DC_LOGGER_INIT();
471	/* Check if reference clock is external (not pcie/xtalin)	472	/* Check if reference clock is external (not pcie/xtalin)
472	* HW Dce80 spec:	473	* HW Dce80 spec:
473	* 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB	474	* 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB
@@ -557,8 +558,8 @@ static uint32_t dce110_get_pix_clk_dividers( · 83 unmodified lines
557	struct pll_settings *pll_settings)	558	struct pll_settings *pll_settings)
558	{	559	{
559	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);	560	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
560	struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
561	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;	561	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
		562	DC_LOGGER_INIT();
562		563
563	if (pix_clk_params == NULL \|\| pll_settings == NULL	564	if (pix_clk_params == NULL \|\| pll_settings == NULL
564	\|\| pix_clk_params->requested_pix_clk == 0) {	565	\|\| pix_clk_params->requested_pix_clk == 0) {
@@ -589,6 +590,9 @@ static uint32_t dce110_get_pix_clk_dividers( · 24 unmodified lines
589	pll_settings, pix_clk_params);	590	pll_settings, pix_clk_params);
590	break;	591	break;
591	case DCE_VERSION_11_2:	592	case DCE_VERSION_11_2:
		593	#if defined(CONFIG_DRM_AMD_DC_VEGAM)
		594	case DCE_VERSION_11_22:
		595	#endif
592	case DCE_VERSION_12_0:	596	case DCE_VERSION_12_0:
593	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)	597	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
594	case DCN_VERSION_1_0:	598	case DCN_VERSION_1_0:
@@ -978,6 +982,9 @@ static bool dce110_program_pix_clk( · 383 unmodified lines
978		982
979	break;	983	break;
980	case DCE_VERSION_11_2:	984	case DCE_VERSION_11_2:
		985	#if defined(CONFIG_DRM_AMD_DC_VEGAM)
		986	case DCE_VERSION_11_22:
		987	#endif
981	case DCE_VERSION_12_0:	988	case DCE_VERSION_12_0:
982	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)	989	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
983	case DCN_VERSION_1_0:	990	case DCN_VERSION_1_0:
@@ -1054,7 +1061,7 @@ static void get_ss_info_from_atombios( · 70 unmodified lines
1054	struct spread_spectrum_info *ss_info_cur;	1061	struct spread_spectrum_info *ss_info_cur;
1055	struct spread_spectrum_data *ss_data_cur;	1062	struct spread_spectrum_data *ss_data_cur;
1056	uint32_t i;	1063	uint32_t i;
1057	struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;	1064	DC_LOGGER_INIT();
1058	if (ss_entries_num == NULL) {	1065	if (ss_entries_num == NULL) {
1059	DC_LOG_SYNC(	1066	DC_LOG_SYNC(
1060	"Invalid entry !!!\n");	1067	"Invalid entry !!!\n");

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c+2−1

@@ -53,7 +53,8 @@ void dce_pipe_control_lock(struct dc *dc, · 52 unmodified lines
53	struct dce_hwseq *hws = dc->hwseq;	53	struct dce_hwseq *hws = dc->hwseq;
54		54
55	/* Not lock pipe when blank */	55	/* Not lock pipe when blank */
56	if (lock && pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))	56	if (lock && pipe->stream_res.tg->funcs->is_blanked &&
		57	pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
57	return;	58	return;
58		59
59	val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],	60	val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c+4−2

 	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
 	.enable_hpd = dce110_link_encoder_enable_hpd,
 	.disable_hpd = dce110_link_encoder_disable_hpd,
+	.is_dig_enabled = dce110_is_dig_enabled,
 	.destroy = dce110_link_encoder_destroy
 };
 		DP_SEC_GSP0_PRIORITY, 1);
 }
-static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
+bool dce110_is_dig_enabled(struct link_encoder *enc)
 {
+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 	uint32_t value;
 	REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
 	struct bp_transmitter_control cntl = { 0 };
 	enum bp_result result;
-	if (!is_dig_enabled(enc110)) {
+	if (!dce110_is_dig_enabled(enc)) {
 		/* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
 		return;
 	}

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h+2−0

@@ -263,4 +263,6 @@ void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, · 262 unmodified lines
263	void dce110_psr_program_secondary_packet(struct link_encoder *enc,	263	void dce110_psr_program_secondary_packet(struct link_encoder *enc,
264	unsigned int sdp_transmit_line_num_deadline);	264	unsigned int sdp_transmit_line_num_deadline);
265		265
		266	bool dce110_is_dig_enabled(struct link_encoder *enc);
		267
266	#endif /* __DC_LINK_ENCODER__DCE110_H__ */	268	#endif /* __DC_LINK_ENCODER__DCE110_H__ */

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c+94−9

@@ -174,6 +174,25 @@ static void program_urgency_watermark( · 173 unmodified lines
174	URGENCY_HIGH_WATERMARK, urgency_high_wm);	174	URGENCY_HIGH_WATERMARK, urgency_high_wm);
175	}	175	}
176		176
		177	static void dce120_program_urgency_watermark(
		178	struct dce_mem_input *dce_mi,
		179	uint32_t wm_select,
		180	uint32_t urgency_low_wm,
		181	uint32_t urgency_high_wm)
		182	{
		183	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
		184	URGENCY_WATERMARK_MASK, wm_select);
		185
		186	REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
		187	URGENCY_LOW_WATERMARK, urgency_low_wm,
		188	URGENCY_HIGH_WATERMARK, urgency_high_wm);
		189
		190	REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0,
		191	URGENT_LEVEL_LOW_WATERMARK, urgency_low_wm,
		192	URGENT_LEVEL_HIGH_WATERMARK, urgency_high_wm);
		193
		194	}
		195
177	static void program_nbp_watermark(	196	static void program_nbp_watermark(
178	struct dce_mem_input *dce_mi,	197	struct dce_mem_input *dce_mi,
179	uint32_t wm_select,	198	uint32_t wm_select,
@@ -206,6 +225,25 @@ static void program_nbp_watermark( · 26 unmodified lines
206	}	225	}
207	}	226	}
208		227
		228	static void dce120_program_stutter_watermark(
		229	struct dce_mem_input *dce_mi,
		230	uint32_t wm_select,
		231	uint32_t stutter_mark,
		232	uint32_t stutter_entry)
		233	{
		234	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
		235	STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
		236
		237	if (REG(DPG_PIPE_STUTTER_CONTROL2))
		238	REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL2,
		239	STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark,
		240	STUTTER_ENTER_SELF_REFRESH_WATERMARK, stutter_entry);
		241	else
		242	REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
		243	STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark,
		244	STUTTER_ENTER_SELF_REFRESH_WATERMARK, stutter_entry);
		245	}
		246
209	static void program_stutter_watermark(	247	static void program_stutter_watermark(
210	struct dce_mem_input *dce_mi,	248	struct dce_mem_input *dce_mi,
211	uint32_t wm_select,	249	uint32_t wm_select,
@@ -225,7 +263,8 @@ static void program_stutter_watermark( · 13 unmodified lines
225	static void dce_mi_program_display_marks(	263	static void dce_mi_program_display_marks(
226	struct mem_input *mi,	264	struct mem_input *mi,
227	struct dce_watermarks nbp,	265	struct dce_watermarks nbp,
228	struct dce_watermarks stutter,	266	struct dce_watermarks stutter_exit,
		267	struct dce_watermarks stutter_enter,
229	struct dce_watermarks urgent,	268	struct dce_watermarks urgent,
230	uint32_t total_dest_line_time_ns)	269	uint32_t total_dest_line_time_ns)
231	{	270	{
@@ -243,13 +282,14 @@ static void dce_mi_program_display_marks( · 11 unmodified lines
243	program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */	282	program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */
244	program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */	283	program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */
245		284
246	program_stutter_watermark(dce_mi, 2, stutter.a_mark); /* set a */	285	program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark); /* set a */
247	program_stutter_watermark(dce_mi, 1, stutter.d_mark); /* set d */	286	program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark); /* set d */
248	}	287	}
249		288
250	static void dce120_mi_program_display_marks(struct mem_input *mi,	289	static void dce112_mi_program_display_marks(struct mem_input *mi,
251	struct dce_watermarks nbp,	290	struct dce_watermarks nbp,
252	struct dce_watermarks stutter,	291	struct dce_watermarks stutter_exit,
		292	struct dce_watermarks stutter_entry,
253	struct dce_watermarks urgent,	293	struct dce_watermarks urgent,
254	uint32_t total_dest_line_time_ns)	294	uint32_t total_dest_line_time_ns)
255	{	295	{
@@ -273,10 +313,43 @@ static void dce120_mi_program_display_marks(struct mem_input *mi, · 17 unmodified lines
273	program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */	313	program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */
274	program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */	314	program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */
275		315
276	program_stutter_watermark(dce_mi, 0, stutter.a_mark); /* set a */	316	program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark); /* set a */
277	program_stutter_watermark(dce_mi, 1, stutter.b_mark); /* set b */	317	program_stutter_watermark(dce_mi, 1, stutter_exit.b_mark); /* set b */
278	program_stutter_watermark(dce_mi, 2, stutter.c_mark); /* set c */	318	program_stutter_watermark(dce_mi, 2, stutter_exit.c_mark); /* set c */
279	program_stutter_watermark(dce_mi, 3, stutter.d_mark); /* set d */	319	program_stutter_watermark(dce_mi, 3, stutter_exit.d_mark); /* set d */
		320	}
		321
		322	static void dce120_mi_program_display_marks(struct mem_input *mi,
		323	struct dce_watermarks nbp,
		324	struct dce_watermarks stutter_exit,
		325	struct dce_watermarks stutter_entry,
		326	struct dce_watermarks urgent,
		327	uint32_t total_dest_line_time_ns)
		328	{
		329	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
		330	uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
		331
		332	dce120_program_urgency_watermark(dce_mi, 0, /* set a */
		333	urgent.a_mark, total_dest_line_time_ns);
		334	dce120_program_urgency_watermark(dce_mi, 1, /* set b */
		335	urgent.b_mark, total_dest_line_time_ns);
		336	dce120_program_urgency_watermark(dce_mi, 2, /* set c */
		337	urgent.c_mark, total_dest_line_time_ns);
		338	dce120_program_urgency_watermark(dce_mi, 3, /* set d */
		339	urgent.d_mark, total_dest_line_time_ns);
		340
		341	REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
		342	STUTTER_ENABLE, stutter_en,
		343	STUTTER_IGNORE_FBC, 1);
		344	program_nbp_watermark(dce_mi, 0, nbp.a_mark); /* set a */
		345	program_nbp_watermark(dce_mi, 1, nbp.b_mark); /* set b */
		346	program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */
		347	program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */
		348
		349	dce120_program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark, stutter_entry.a_mark); /* set a */
		350	dce120_program_stutter_watermark(dce_mi, 1, stutter_exit.b_mark, stutter_entry.b_mark); /* set b */
		351	dce120_program_stutter_watermark(dce_mi, 2, stutter_exit.c_mark, stutter_entry.c_mark); /* set c */
		352	dce120_program_stutter_watermark(dce_mi, 3, stutter_exit.d_mark, stutter_entry.d_mark); /* set d */
280	}	353	}
281		354
282	static void program_tiling(	355	static void program_tiling(
@@ -694,6 +767,18 @@ void dce112_mem_input_construct( · 411 unmodified lines
694	const struct dce_mem_input_registers *regs,	767	const struct dce_mem_input_registers *regs,
695	const struct dce_mem_input_shift *mi_shift,	768	const struct dce_mem_input_shift *mi_shift,
696	const struct dce_mem_input_mask *mi_mask)	769	const struct dce_mem_input_mask *mi_mask)
		770	{
		771	dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
		772	dce_mi->base.funcs->mem_input_program_display_marks = dce112_mi_program_display_marks;
		773	}
		774
		775	void dce120_mem_input_construct(
		776	struct dce_mem_input *dce_mi,
		777	struct dc_context *ctx,
		778	int inst,
		779	const struct dce_mem_input_registers *regs,
		780	const struct dce_mem_input_shift *mi_shift,
		781	const struct dce_mem_input_mask *mi_mask)
697	{	782	{
698	dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);	783	dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
699	dce_mi->base.funcs->mem_input_program_display_marks = dce120_mi_program_display_marks;	784	dce_mi->base.funcs->mem_input_program_display_marks = dce120_mi_program_display_marks;

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h+17−0

 	uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
 	uint32_t DPG_WATERMARK_MASK_CONTROL;
 	uint32_t DPG_PIPE_URGENCY_CONTROL;
+	uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL;
 	uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
 	uint32_t DPG_PIPE_LOW_POWER_CONTROL;
 	uint32_t DPG_PIPE_STUTTER_CONTROL;
 #define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
 	SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
+	SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_ENTER_SELF_REFRESH_WATERMARK, mask_sh),\
+	SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_LOW_WATERMARK, mask_sh),\
+	SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_HIGH_WATERMARK, mask_sh),\
+	SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
+	SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
 	SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
 	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\
 	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
 	type STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK; \
 	type URGENCY_LOW_WATERMARK; \
 	type URGENCY_HIGH_WATERMARK; \
+	type URGENT_LEVEL_LOW_WATERMARK;\
+	type URGENT_LEVEL_HIGH_WATERMARK;\
 	type NB_PSTATE_CHANGE_ENABLE; \
 	type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST; \
 	type NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \
 	type STUTTER_ENABLE; \
 	type STUTTER_IGNORE_FBC; \
 	type STUTTER_EXIT_SELF_REFRESH_WATERMARK; \
+	type STUTTER_ENTER_SELF_REFRESH_WATERMARK; \
 	type DMIF_BUFFERS_ALLOCATED; \
 	type DMIF_BUFFERS_ALLOCATION_COMPLETED; \
 	type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\
 	const struct dce_mem_input_shift *mi_shift,
 	const struct dce_mem_input_mask *mi_mask);
+void dce120_mem_input_construct(
+	struct dce_mem_input *dce_mi,
+	struct dc_context *ctx,
+	int inst,
+	const struct dce_mem_input_registers *regs,
+	const struct dce_mem_input_shift *mi_shift,
+	const struct dce_mem_input_mask *mi_mask);
 #endif /*__DCE_MEM_INPUT_H__*/

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c+19−49

@@ -26,27 +26,10 @@ · 25 unmodified lines
26	#include "dc_bios_types.h"	26	#include "dc_bios_types.h"
27	#include "dce_stream_encoder.h"	27	#include "dce_stream_encoder.h"
28	#include "reg_helper.h"	28	#include "reg_helper.h"
		29	#include "hw_shared.h"
		30
29	#define DC_LOGGER \	31	#define DC_LOGGER \
30	enc110->base.ctx->logger	32	enc110->base.ctx->logger
31	enum DP_PIXEL_ENCODING {
32	DP_PIXEL_ENCODING_RGB444 = 0x00000000,
33	DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
34	DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
35	DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
36	DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
37	DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
38	DP_PIXEL_ENCODING_RESERVED = 0x00000006,
39	};
40
41
42	enum DP_COMPONENT_DEPTH {
43	DP_COMPONENT_DEPTH_6BPC = 0x00000000,
44	DP_COMPONENT_DEPTH_8BPC = 0x00000001,
45	DP_COMPONENT_DEPTH_10BPC = 0x00000002,
46	DP_COMPONENT_DEPTH_12BPC = 0x00000003,
47	DP_COMPONENT_DEPTH_16BPC = 0x00000004,
48	DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
49	};
50		33
51		34
52	#define REG(reg)\	35	#define REG(reg)\
@@ -80,7 +63,7 @@ enum { · 27 unmodified lines
80	static void dce110_update_generic_info_packet(	63	static void dce110_update_generic_info_packet(
81	struct dce110_stream_encoder *enc110,	64	struct dce110_stream_encoder *enc110,
82	uint32_t packet_index,	65	uint32_t packet_index,
83	const struct encoder_info_packet *info_packet)	66	const struct dc_info_packet *info_packet)
84	{	67	{
85	uint32_t regval;	68	uint32_t regval;
86	/* TODOFPGA Figure out a proper number for max_retries polling for lock	69	/* TODOFPGA Figure out a proper number for max_retries polling for lock
@@ -196,7 +179,7 @@ static void dce110_update_generic_info_packet( · 109 unmodified lines
196	static void dce110_update_hdmi_info_packet(	179	static void dce110_update_hdmi_info_packet(
197	struct dce110_stream_encoder *enc110,	180	struct dce110_stream_encoder *enc110,
198	uint32_t packet_index,	181	uint32_t packet_index,
199	const struct encoder_info_packet *info_packet)	182	const struct dc_info_packet *info_packet)
200	{	183	{
201	uint32_t cont, send, line;	184	uint32_t cont, send, line;
202		185
@@ -314,11 +297,11 @@ static void dce110_stream_encoder_dp_set_stream_attribute( · 111 unmodified lines
314	switch (crtc_timing->pixel_encoding) {	297	switch (crtc_timing->pixel_encoding) {
315	case PIXEL_ENCODING_YCBCR422:	298	case PIXEL_ENCODING_YCBCR422:
316	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,	299	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
317	DP_PIXEL_ENCODING_YCBCR422);	300	DP_PIXEL_ENCODING_TYPE_YCBCR422);
318	break;	301	break;
319	case PIXEL_ENCODING_YCBCR444:	302	case PIXEL_ENCODING_YCBCR444:
320	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,	303	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
321	DP_PIXEL_ENCODING_YCBCR444);	304	DP_PIXEL_ENCODING_TYPE_YCBCR444);
322		305
323	if (crtc_timing->flags.Y_ONLY)	306	if (crtc_timing->flags.Y_ONLY)
324	if (crtc_timing->display_color_depth != COLOR_DEPTH_666)	307	if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
@@ -326,7 +309,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( · 1 unmodified line
326	* Color depth of Y-only could be	309	* Color depth of Y-only could be
327	* 8, 10, 12, 16 bits */	310	* 8, 10, 12, 16 bits */
328	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,	311	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
329	DP_PIXEL_ENCODING_Y_ONLY);	312	DP_PIXEL_ENCODING_TYPE_Y_ONLY);
330	/* Note: DP_MSA_MISC1 bit 7 is the indicator	313	/* Note: DP_MSA_MISC1 bit 7 is the indicator
331	* of Y-only mode.	314	* of Y-only mode.
332	* This bit is set in HW if register	315	* This bit is set in HW if register
@@ -334,7 +317,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( · 1 unmodified line
334	break;	317	break;
335	case PIXEL_ENCODING_YCBCR420:	318	case PIXEL_ENCODING_YCBCR420:
336	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,	319	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
337	DP_PIXEL_ENCODING_YCBCR420);	320	DP_PIXEL_ENCODING_TYPE_YCBCR420);
338	if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)	321	if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
339	REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);	322	REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
340		323
@@ -345,7 +328,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( · 4 unmodified lines
345	break;	328	break;
346	default:	329	default:
347	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,	330	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
348	DP_PIXEL_ENCODING_RGB444);	331	DP_PIXEL_ENCODING_TYPE_RGB444);
349	break;	332	break;
350	}	333	}
351		334
@@ -363,20 +346,20 @@ static void dce110_stream_encoder_dp_set_stream_attribute( · 11 unmodified lines
363	break;	346	break;
364	case COLOR_DEPTH_888:	347	case COLOR_DEPTH_888:
365	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,	348	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
366	DP_COMPONENT_DEPTH_8BPC);	349	DP_COMPONENT_PIXEL_DEPTH_8BPC);
367	break;	350	break;
368	case COLOR_DEPTH_101010:	351	case COLOR_DEPTH_101010:
369	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,	352	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
370	DP_COMPONENT_DEPTH_10BPC);	353	DP_COMPONENT_PIXEL_DEPTH_10BPC);
371		354
372	break;	355	break;
373	case COLOR_DEPTH_121212:	356	case COLOR_DEPTH_121212:
374	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,	357	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
375	DP_COMPONENT_DEPTH_12BPC);	358	DP_COMPONENT_PIXEL_DEPTH_12BPC);
376	break;	359	break;
377	default:	360	default:
378	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,	361	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
379	DP_COMPONENT_DEPTH_6BPC);	362	DP_COMPONENT_PIXEL_DEPTH_6BPC);
380	break;	363	break;
381	}	364	}
382		365
@@ -836,7 +819,7 @@ static void dce110_stream_encoder_update_dp_info_packets( · 453 unmodified lines
836	const struct encoder_info_frame *info_frame)	819	const struct encoder_info_frame *info_frame)
837	{	820	{
838	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);	821	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
839	uint32_t value = REG_READ(DP_SEC_CNTL);	822	uint32_t value = 0;
840		823
841	if (info_frame->vsc.valid)	824	if (info_frame->vsc.valid)
842	dce110_update_generic_info_packet(	825	dce110_update_generic_info_packet(
@@ -870,6 +853,7 @@ static void dce110_stream_encoder_update_dp_info_packets( · 27 unmodified lines
870	* Therefore we need to enable master bit	853	* Therefore we need to enable master bit
871	* if at least on of the fields is not 0	854	* if at least on of the fields is not 0
872	*/	855	*/
		856	value = REG_READ(DP_SEC_CNTL);
873	if (value)	857	if (value)
874	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);	858	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
875	}	859	}
@@ -879,7 +863,7 @@ static void dce110_stream_encoder_stop_dp_info_packets( · 3 unmodified lines
879	{	863	{
880	/* stop generic packets on DP */	864	/* stop generic packets on DP */
881	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);	865	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
882	uint32_t value = REG_READ(DP_SEC_CNTL);	866	uint32_t value = 0;
883		867
884	if (enc110->se_mask->DP_SEC_AVI_ENABLE) {	868	if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
885	REG_SET_7(DP_SEC_CNTL, 0,	869	REG_SET_7(DP_SEC_CNTL, 0,
@@ -892,25 +876,10 @@ static void dce110_stream_encoder_stop_dp_info_packets( · 6 unmodified lines
892	DP_SEC_STREAM_ENABLE, 0);	876	DP_SEC_STREAM_ENABLE, 0);
893	}	877	}
894		878
895	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
896	if (enc110->se_mask->DP_SEC_GSP7_ENABLE) {
897	REG_SET_10(DP_SEC_CNTL, 0,
898	DP_SEC_GSP0_ENABLE, 0,
899	DP_SEC_GSP1_ENABLE, 0,
900	DP_SEC_GSP2_ENABLE, 0,
901	DP_SEC_GSP3_ENABLE, 0,
902	DP_SEC_GSP4_ENABLE, 0,
903	DP_SEC_GSP5_ENABLE, 0,
904	DP_SEC_GSP6_ENABLE, 0,
905	DP_SEC_GSP7_ENABLE, 0,
906	DP_SEC_MPG_ENABLE, 0,
907	DP_SEC_STREAM_ENABLE, 0);
908	}
909	#endif
910	/* this register shared with audio info frame.	879	/* this register shared with audio info frame.
911	* therefore we need to keep master enabled	880	* therefore we need to keep master enabled
912	* if at least one of the fields is not 0 */	881	* if at least one of the fields is not 0 */
913		882	value = REG_READ(DP_SEC_CNTL);
914	if (value)	883	if (value)
915	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);	884	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
916		885
@@ -1513,7 +1482,7 @@ static void dce110_se_disable_dp_audio( · 596 unmodified lines
1513	struct stream_encoder *enc)	1482	struct stream_encoder *enc)
1514	{	1483	{
1515	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);	1484	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1516	uint32_t value = REG_READ(DP_SEC_CNTL);	1485	uint32_t value = 0;
1517		1486
1518	/* Disable Audio packets */	1487	/* Disable Audio packets */
1519	REG_UPDATE_5(DP_SEC_CNTL,	1488	REG_UPDATE_5(DP_SEC_CNTL,
@@ -1525,6 +1494,7 @@ static void dce110_se_disable_dp_audio( · 5 unmodified lines
1525		1494
1526	/* This register shared with encoder info frame. Therefore we need to	1495	/* This register shared with encoder info frame. Therefore we need to
1527	keep master enabled if at least on of the fields is not 0 */	1496	keep master enabled if at least on of the fields is not 0 */
		1497	value = REG_READ(DP_SEC_CNTL);
1528	if (value != 0)	1498	if (value != 0)
1529	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);	1499	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1530		1500

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c+0−33

@@ -733,38 +733,6 @@ enum dc_status dce100_add_stream_to_ctx( · 732 unmodified lines
733	return result;	733	return result;
734	}	734	}
735		735
736	enum dc_status dce100_validate_guaranteed(
737	struct dc *dc,
738	struct dc_stream_state *dc_stream,
739	struct dc_state *context)
740	{
741	enum dc_status result = DC_ERROR_UNEXPECTED;
742
743	context->streams[0] = dc_stream;
744	dc_stream_retain(context->streams[0]);
745	context->stream_count++;
746
747	result = resource_map_pool_resources(dc, context, dc_stream);
748
749	if (result == DC_OK)
750	result = resource_map_clock_resources(dc, context, dc_stream);
751
752	if (result == DC_OK)
753	result = build_mapped_resource(dc, context, dc_stream);
754
755	if (result == DC_OK) {
756	validate_guaranteed_copy_streams(
757	context, dc->caps.max_streams);
758	result = resource_build_scaling_params_for_context(dc, context);
759	}
760
761	if (result == DC_OK)
762	if (!dce100_validate_bandwidth(dc, context))
763	result = DC_FAIL_BANDWIDTH_VALIDATE;
764
765	return result;
766	}
767
768	static void dce100_destroy_resource_pool(struct resource_pool **pool)	736	static void dce100_destroy_resource_pool(struct resource_pool **pool)
769	{	737	{
770	struct dce110_resource_pool dce110_pool = TO_DCE110_RES_POOL(pool);	738	struct dce110_resource_pool dce110_pool = TO_DCE110_RES_POOL(pool);
@@ -786,7 +754,6 @@ enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, s · 15 unmodified lines
786	static const struct resource_funcs dce100_res_pool_funcs = {	754	static const struct resource_funcs dce100_res_pool_funcs = {
787	.destroy = dce100_destroy_resource_pool,	755	.destroy = dce100_destroy_resource_pool,
788	.link_enc_create = dce100_link_encoder_create,	756	.link_enc_create = dce100_link_encoder_create,
789	.validate_guaranteed = dce100_validate_guaranteed,
790	.validate_bandwidth = dce100_validate_bandwidth,	757	.validate_bandwidth = dce100_validate_bandwidth,
791	.validate_plane = dce100_validate_plane,	758	.validate_plane = dce100_validate_plane,
792	.add_stream_to_ctx = dce100_add_stream_to_ctx,	759	.add_stream_to_ctx = dce100_add_stream_to_ctx,

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c+74−21

@@ -70,8 +70,9 @@ · 69 unmodified lines
70		70
71	#define CTX \	71	#define CTX \
72	hws->ctx	72	hws->ctx
73	#define DC_LOGGER \	73
74	ctx->logger	74	#define DC_LOGGER_INIT()
		75
75	#define REG(reg)\	76	#define REG(reg)\
76	hws->regs->reg	77	hws->regs->reg
77		78
@@ -279,7 +280,9 @@ dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, · 201 unmodified lines
279	build_prescale_params(&prescale_params, plane_state);	280	build_prescale_params(&prescale_params, plane_state);
280	ipp->funcs->ipp_program_prescale(ipp, &prescale_params);	281	ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
281		282
282	if (plane_state->gamma_correction && dce_use_lut(plane_state->format))	283	if (plane_state->gamma_correction &&
		284	!plane_state->gamma_correction->is_identity &&
		285	dce_use_lut(plane_state->format))
283	ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);	286	ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
284		287
285	if (tf == NULL) {	288	if (tf == NULL) {
@@ -851,6 +854,28 @@ void hwss_edp_power_control( · 565 unmodified lines
851		854
852	if (power_up != is_panel_powered_on(hwseq)) {	855	if (power_up != is_panel_powered_on(hwseq)) {
853	/* Send VBIOS command to prompt eDP panel power */	856	/* Send VBIOS command to prompt eDP panel power */
		857	if (power_up) {
		858	unsigned long long current_ts = dm_get_timestamp(ctx);
		859	unsigned long long duration_in_ms =
		860	dm_get_elapse_time_in_ns(
		861	ctx,
		862	current_ts,
		863	div64_u64(link->link_trace.time_stamp.edp_poweroff, 1000000));
		864	unsigned long long wait_time_ms = 0;
		865
		866	/* max 500ms from LCDVDD off to on */
		867	if (link->link_trace.time_stamp.edp_poweroff == 0)
		868	wait_time_ms = 500;
		869	else if (duration_in_ms < 500)
		870	wait_time_ms = 500 - duration_in_ms;
		871
		872	if (wait_time_ms) {
		873	msleep(wait_time_ms);
		874	dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
		875	__func__, wait_time_ms);
		876	}
		877
		878	}
854		879
855	DC_LOG_HW_RESUME_S3(	880	DC_LOG_HW_RESUME_S3(
856	"%s: Panel Power action: %s\n",	881	"%s: Panel Power action: %s\n",
@@ -864,9 +889,14 @@ void hwss_edp_power_control( · 7 unmodified lines
864	cntl.coherent = false;	889	cntl.coherent = false;
865	cntl.lanes_number = LANE_COUNT_FOUR;	890	cntl.lanes_number = LANE_COUNT_FOUR;
866	cntl.hpd_sel = link->link_enc->hpd_source;	891	cntl.hpd_sel = link->link_enc->hpd_source;
867
868	bp_result = link_transmitter_control(ctx->dc_bios, &cntl);	892	bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
869		893
		894	if (!power_up)
		895	/save driver power off time stamp/
		896	link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
		897	else
		898	link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
		899
870	if (bp_result != BP_RESULT_OK)	900	if (bp_result != BP_RESULT_OK)
871	DC_LOG_ERROR(	901	DC_LOG_ERROR(
872	"%s: Panel Power bp_result: %d\n",	902	"%s: Panel Power bp_result: %d\n",
@@ -1011,7 +1041,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, · 138 unmodified lines
1011		1041
1012	if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {	1042	if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1013	link->dc->hwss.edp_backlight_control(link, true);	1043	link->dc->hwss.edp_backlight_control(link, true);
1014	stream->bl_pwm_level = 0;	1044	stream->bl_pwm_level = EDP_BACKLIGHT_RAMP_DISABLE_LEVEL;
1015	}	1045	}
1016	}	1046	}
1017	void dce110_blank_stream(struct pipe_ctx *pipe_ctx)	1047	void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
@@ -1203,7 +1233,7 @@ static void program_scaler(const struct dc *dc, · 185 unmodified lines
1203	&pipe_ctx->plane_res.scl_data);	1233	&pipe_ctx->plane_res.scl_data);
1204	}	1234	}
1205		1235
1206	static enum dc_status dce110_prog_pixclk_crtc_otg(	1236	static enum dc_status dce110_enable_stream_timing(
1207	struct pipe_ctx *pipe_ctx,	1237	struct pipe_ctx *pipe_ctx,
1208	struct dc_state *context,	1238	struct dc_state *context,
1209	struct dc *dc)	1239	struct dc *dc)
@@ -1269,7 +1299,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( · 59 unmodified lines
1269	pipe_ctx[pipe_ctx->pipe_idx];	1299	pipe_ctx[pipe_ctx->pipe_idx];
1270		1300
1271	/* */	1301	/* */
1272	dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);	1302	dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
1273		1303
1274	/* FPGA does not program backend */	1304	/* FPGA does not program backend */
1275	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {	1305	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
@@ -1441,6 +1471,17 @@ static void disable_vga_and_power_gate_all_controllers( · 165 unmodified lines
1441	}	1471	}
1442	}	1472	}
1443		1473
		1474	static struct dc_link get_link_for_edp(struct dc dc)
		1475	{
		1476	int i;
		1477
		1478	for (i = 0; i < dc->link_count; i++) {
		1479	if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
		1480	return dc->links[i];
		1481	}
		1482	return NULL;
		1483	}
		1484
1444	static struct dc_link *get_link_for_edp_not_in_use(	1485	static struct dc_link *get_link_for_edp_not_in_use(
1445	struct dc *dc,	1486	struct dc *dc,
1446	struct dc_state *context)	1487	struct dc_state *context)
@@ -1475,20 +1516,21 @@ static struct dc_link *get_link_for_edp_not_in_use( · 28 unmodified lines
1475	*/	1516	*/
1476	void dce110_enable_accelerated_mode(struct dc dc, struct dc_state context)	1517	void dce110_enable_accelerated_mode(struct dc dc, struct dc_state context)
1477	{	1518	{
1478	struct dc_bios *dcb = dc->ctx->dc_bios;
1479
1480	/* vbios already light up eDP, so we can leverage vbios and skip eDP
1481	* programming
1482	*/
1483	bool can_eDP_fast_boot_optimize =
1484	(dcb->funcs->get_vga_enabled_displays(dc->ctx->dc_bios) == ATOM_DISPLAY_LCD1_ACTIVE);
1485
1486	/* if OS doesn't light up eDP and eDP link is available, we want to disable */
1487	struct dc_link *edp_link_to_turnoff = NULL;	1519	struct dc_link *edp_link_to_turnoff = NULL;
		1520	struct dc_link *edp_link = get_link_for_edp(dc);
		1521	bool can_eDP_fast_boot_optimize = false;
		1522
		1523	if (edp_link) {
		1524	can_eDP_fast_boot_optimize =
		1525	edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc);
		1526	}
1488		1527
1489	if (can_eDP_fast_boot_optimize) {	1528	if (can_eDP_fast_boot_optimize) {
1490	edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);	1529	edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);
1491		1530
		1531	/* if OS doesn't light up eDP and eDP link is available, we want to disable
		1532	* If resume from S4/S5, should optimization.
		1533	*/
1492	if (!edp_link_to_turnoff)	1534	if (!edp_link_to_turnoff)
1493	dc->apply_edp_fast_boot_optimization = true;	1535	dc->apply_edp_fast_boot_optimization = true;
1494	}	1536	}
@@ -1544,6 +1586,7 @@ static void dce110_set_displaymarks( · 49 unmodified lines
1544	pipe_ctx->plane_res.mi,	1586	pipe_ctx->plane_res.mi,
1545	context->bw.dce.nbp_state_change_wm_ns[num_pipes],	1587	context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1546	context->bw.dce.stutter_exit_wm_ns[num_pipes],	1588	context->bw.dce.stutter_exit_wm_ns[num_pipes],
		1589	context->bw.dce.stutter_entry_wm_ns[num_pipes],
1547	context->bw.dce.urgent_wm_ns[num_pipes],	1590	context->bw.dce.urgent_wm_ns[num_pipes],
1548	total_dest_line_time_ns);	1591	total_dest_line_time_ns);
1549	if (i == underlay_idx) {	1592	if (i == underlay_idx) {
@@ -1569,6 +1612,7 @@ static void set_safe_displaymarks( · 19 unmodified lines
1569	MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };	1612	MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1570	struct dce_watermarks nbp_marks = {	1613	struct dce_watermarks nbp_marks = {
1571	SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };	1614	SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
		1615	struct dce_watermarks min_marks = { 0, 0, 0, 0};
1572		1616
1573	for (i = 0; i < MAX_PIPES; i++) {	1617	for (i = 0; i < MAX_PIPES; i++) {
1574	if (res_ctx->pipe_ctx[i].stream == NULL \|\| res_ctx->pipe_ctx[i].plane_res.mi == NULL)	1618	if (res_ctx->pipe_ctx[i].stream == NULL \|\| res_ctx->pipe_ctx[i].plane_res.mi == NULL)
@@ -1578,6 +1622,7 @@ static void set_safe_displaymarks( · 3 unmodified lines
1578	res_ctx->pipe_ctx[i].plane_res.mi,	1622	res_ctx->pipe_ctx[i].plane_res.mi,
1579	nbp_marks,	1623	nbp_marks,
1580	max_marks,	1624	max_marks,
		1625	min_marks,
1581	max_marks,	1626	max_marks,
1582	MAX_WATERMARK);	1627	MAX_WATERMARK);
1583		1628
@@ -1803,6 +1848,9 @@ static bool should_enable_fbc(struct dc *dc, · 219 unmodified lines
1803	}	1848	}
1804	}	1849	}
1805		1850
		1851	/* Pipe context should be found */
		1852	ASSERT(pipe_ctx);
		1853
1806	/* Only supports eDP */	1854	/* Only supports eDP */
1807	if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)	1855	if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1808	return false;	1856	return false;
@@ -2699,8 +2747,11 @@ static void dce110_program_front_end_for_pipe( · 890 unmodified lines
2699	struct dc_plane_state *plane_state = pipe_ctx->plane_state;	2747	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2700	struct xfm_grph_csc_adjustment adjust;	2748	struct xfm_grph_csc_adjustment adjust;
2701	struct out_csc_color_matrix tbl_entry;	2749	struct out_csc_color_matrix tbl_entry;
		2750	#if defined(CONFIG_DRM_AMD_DC_FBC)
		2751	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
		2752	#endif
2702	unsigned int i;	2753	unsigned int i;
2703	struct dc_context *ctx = dc->ctx;	2754	DC_LOGGER_INIT();
2704	memset(&tbl_entry, 0, sizeof(tbl_entry));	2755	memset(&tbl_entry, 0, sizeof(tbl_entry));
2705		2756
2706	if (dc->current_state)	2757	if (dc->current_state)
@@ -2740,7 +2791,9 @@ static void dce110_program_front_end_for_pipe( · 33 unmodified lines
2740	program_scaler(dc, pipe_ctx);	2791	program_scaler(dc, pipe_ctx);
2741		2792
2742	#if defined(CONFIG_DRM_AMD_DC_FBC)	2793	#if defined(CONFIG_DRM_AMD_DC_FBC)
2743	if (dc->fbc_compressor && old_pipe->stream) {	2794	/* fbc not applicable on Underlay pipe */
		2795	if (dc->fbc_compressor && old_pipe->stream &&
		2796	pipe_ctx->pipe_idx != underlay_idx) {
2744	if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)	2797	if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2745	dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);	2798	dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2746	else	2799	else
@@ -2776,13 +2829,13 @@ static void dce110_program_front_end_for_pipe( · 29 unmodified lines
2776	dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);	2829	dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2777		2830
2778	DC_LOG_SURFACE(	2831	DC_LOG_SURFACE(
2779	"Pipe:%d 0x%x: addr hi:0x%x, "	2832	"Pipe:%d %p: addr hi:0x%x, "
2780	"addr low:0x%x, "	2833	"addr low:0x%x, "
2781	"src: %d, %d, %d,"	2834	"src: %d, %d, %d,"
2782	" %d; dst: %d, %d, %d, %d;"	2835	" %d; dst: %d, %d, %d, %d;"
2783	"clip: %d, %d, %d, %d\n",	2836	"clip: %d, %d, %d, %d\n",
2784	pipe_ctx->pipe_idx,	2837	pipe_ctx->pipe_idx,
2785	pipe_ctx->plane_state,	2838	(void *) pipe_ctx->plane_state,
2786	pipe_ctx->plane_state->address.grph.addr.high_part,	2839	pipe_ctx->plane_state->address.grph.addr.high_part,
2787	pipe_ctx->plane_state->address.grph.addr.low_part,	2840	pipe_ctx->plane_state->address.grph.addr.low_part,
2788	pipe_ctx->plane_state->src_rect.x,	2841	pipe_ctx->plane_state->src_rect.x,
@@ -2993,7 +3046,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { · 204 unmodified lines
2993	.get_position = get_position,	3046	.get_position = get_position,
2994	.set_static_screen_control = set_static_screen_control,	3047	.set_static_screen_control = set_static_screen_control,
2995	.reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,	3048	.reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2996	.prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,	3049	.enable_stream_timing = dce110_enable_stream_timing,
2997	.setup_stereo = NULL,	3050	.setup_stereo = NULL,
2998	.set_avmute = dce110_set_avmute,	3051	.set_avmute = dce110_set_avmute,
2999	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,	3052	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c+1−0

@@ -923,6 +923,7 @@ void dce_mem_input_v_program_display_marks( · 922 unmodified lines
923	struct mem_input *mem_input,	923	struct mem_input *mem_input,
924	struct dce_watermarks nbp,	924	struct dce_watermarks nbp,
925	struct dce_watermarks stutter,	925	struct dce_watermarks stutter,
		926	struct dce_watermarks stutter_enter,
926	struct dce_watermarks urgent,	927	struct dce_watermarks urgent,
927	uint32_t total_dest_line_time_ns)	928	uint32_t total_dest_line_time_ns)
928	{	929	{

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c+0−33

@@ -930,38 +930,6 @@ static enum dc_status dce110_add_stream_to_ctx( · 929 unmodified lines
930	return result;	930	return result;
931	}	931	}
932		932
933	static enum dc_status dce110_validate_guaranteed(
934	struct dc *dc,
935	struct dc_stream_state *dc_stream,
936	struct dc_state *context)
937	{
938	enum dc_status result = DC_ERROR_UNEXPECTED;
939
940	context->streams[0] = dc_stream;
941	dc_stream_retain(context->streams[0]);
942	context->stream_count++;
943
944	result = resource_map_pool_resources(dc, context, dc_stream);
945
946	if (result == DC_OK)
947	result = resource_map_clock_resources(dc, context, dc_stream);
948
949	if (result == DC_OK)
950	result = build_mapped_resource(dc, context, dc_stream);
951
952	if (result == DC_OK) {
953	validate_guaranteed_copy_streams(
954	context, dc->caps.max_streams);
955	result = resource_build_scaling_params_for_context(dc, context);
956	}
957
958	if (result == DC_OK)
959	if (!dce110_validate_bandwidth(dc, context))
960	result = DC_FAIL_BANDWIDTH_VALIDATE;
961
962	return result;
963	}
964
965	static struct pipe_ctx *dce110_acquire_underlay(	933	static struct pipe_ctx *dce110_acquire_underlay(
966	struct dc_state *context,	934	struct dc_state *context,
967	const struct resource_pool *pool,	935	const struct resource_pool *pool,
@@ -1036,7 +1004,6 @@ static void dce110_destroy_resource_pool(struct resource_pool **pool) · 68 unmodified lines
1036	static const struct resource_funcs dce110_res_pool_funcs = {	1004	static const struct resource_funcs dce110_res_pool_funcs = {
1037	.destroy = dce110_destroy_resource_pool,	1005	.destroy = dce110_destroy_resource_pool,
1038	.link_enc_create = dce110_link_encoder_create,	1006	.link_enc_create = dce110_link_encoder_create,
1039	.validate_guaranteed = dce110_validate_guaranteed,
1040	.validate_bandwidth = dce110_validate_bandwidth,	1007	.validate_bandwidth = dce110_validate_bandwidth,
1041	.validate_plane = dce110_validate_plane,	1008	.validate_plane = dce110_validate_plane,
1042	.acquire_idle_pipe_for_layer = dce110_acquire_underlay,	1009	.acquire_idle_pipe_for_layer = dce110_acquire_underlay,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c+8−8

 			0,
 			CRTC_V_TOTAL_CONTROL,
 			CRTC_SET_V_TOTAL_MIN_MASK);
-		set_reg_field_value(v_total_min,
-				0,
-				CRTC_V_TOTAL_MIN,
-				CRTC_V_TOTAL_MIN);
-		set_reg_field_value(v_total_max,
-				0,
-				CRTC_V_TOTAL_MAX,
-				CRTC_V_TOTAL_MAX);
 		set_reg_field_value(v_total_cntl,
 				0,
 				CRTC_V_TOTAL_CONTROL,
 				0,
 				CRTC_V_TOTAL_CONTROL,
 				CRTC_V_TOTAL_MAX_SEL);
+		set_reg_field_value(v_total_min,
+				0,
+				CRTC_V_TOTAL_MIN,
+				CRTC_V_TOTAL_MIN);
+		set_reg_field_value(v_total_max,
+				0,
+				CRTC_V_TOTAL_MAX,
+				CRTC_V_TOTAL_MAX);
 		set_reg_field_value(v_total_cntl,
 				0,
 				CRTC_V_TOTAL_CONTROL,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c+0−7

 	return;
 }
-static bool dce110_tg_v_is_blanked(struct timing_generator *tg)
-{
-	/* Signal comes from the primary pipe, underlay is never blanked. */
-	return false;
-}
 /** ********************************************************************************************
  *
  * DCE11 Timing Generator Constructor / Destructor
 		.set_early_control = dce110_timing_generator_v_set_early_control,
 		.wait_for_state = dce110_timing_generator_v_wait_for_state,
 		.set_blank = dce110_timing_generator_v_set_blank,
-		.is_blanked = dce110_tg_v_is_blanked,
 		.set_colors = dce110_timing_generator_v_set_colors,
 		.set_overscan_blank_color =
 				dce110_timing_generator_v_set_overscan_color_black,

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c+1−34

@@ -430,7 +430,7 @@ static struct stream_encoder *dce112_stream_encoder_create( · 429 unmodified lines
430		430
431	if (!enc110)	431	if (!enc110)
432	return NULL;	432	return NULL;
433		433
434	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,	434	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
435	&stream_enc_regs[eng_id],	435	&stream_enc_regs[eng_id],
436	&se_shift, &se_mask);	436	&se_shift, &se_mask);
@@ -867,38 +867,6 @@ enum dc_status dce112_add_stream_to_ctx( · 430 unmodified lines
867	return result;	867	return result;
868	}	868	}
869		869
870	enum dc_status dce112_validate_guaranteed(
871	struct dc *dc,
872	struct dc_stream_state *stream,
873	struct dc_state *context)
874	{
875	enum dc_status result = DC_ERROR_UNEXPECTED;
876
877	context->streams[0] = stream;
878	dc_stream_retain(context->streams[0]);
879	context->stream_count++;
880
881	result = resource_map_pool_resources(dc, context, stream);
882
883	if (result == DC_OK)
884	result = resource_map_phy_clock_resources(dc, context, stream);
885
886	if (result == DC_OK)
887	result = build_mapped_resource(dc, context, stream);
888
889	if (result == DC_OK) {
890	validate_guaranteed_copy_streams(
891	context, dc->caps.max_streams);
892	result = resource_build_scaling_params_for_context(dc, context);
893	}
894
895	if (result == DC_OK)
896	if (!dce112_validate_bandwidth(dc, context))
897	result = DC_FAIL_BANDWIDTH_VALIDATE;
898
899	return result;
900	}
901
902	enum dc_status dce112_validate_global(	870	enum dc_status dce112_validate_global(
903	struct dc *dc,	871	struct dc *dc,
904	struct dc_state *context)	872	struct dc_state *context)
@@ -921,7 +889,6 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool) · 16 unmodified lines
921	static const struct resource_funcs dce112_res_pool_funcs = {	889	static const struct resource_funcs dce112_res_pool_funcs = {
922	.destroy = dce112_destroy_resource_pool,	890	.destroy = dce112_destroy_resource_pool,
923	.link_enc_create = dce112_link_encoder_create,	891	.link_enc_create = dce112_link_encoder_create,
924	.validate_guaranteed = dce112_validate_guaranteed,
925	.validate_bandwidth = dce112_validate_bandwidth,	892	.validate_bandwidth = dce112_validate_bandwidth,
926	.validate_plane = dce100_validate_plane,	893	.validate_plane = dce100_validate_plane,
927	.add_stream_to_ctx = dce112_add_stream_to_ctx,	894	.add_stream_to_ctx = dce112_add_stream_to_ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h+0−5

 		struct dc_state *context,
 		struct dc_state *old_context);
-enum dc_status dce112_validate_guaranteed(
-		struct dc *dc,
-		struct dc_stream_state *dc_stream,
-		struct dc_state *context);
 bool dce112_validate_bandwidth(
 	struct dc *dc,
 	struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c+1−2

 		return NULL;
 	}
-	dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
+	dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 	return &dce_mi->base;
 }
 static const struct resource_funcs dce120_res_pool_funcs = {
 	.destroy = dce120_destroy_resource_pool,
 	.link_enc_create = dce120_link_encoder_create,
-	.validate_guaranteed = dce112_validate_guaranteed,
 	.validate_bandwidth = dce112_validate_bandwidth,
 	.validate_plane = dce100_validate_plane,
 	.add_stream_to_ctx = dce112_add_stream_to_ctx

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c+6−6

 				0x180);
 	} else {
-		CRTC_REG_UPDATE(
-				CRTC0_CRTC_V_TOTAL_MIN,
-				CRTC_V_TOTAL_MIN, 0);
-		CRTC_REG_UPDATE(
-				CRTC0_CRTC_V_TOTAL_MAX,
-				CRTC_V_TOTAL_MAX, 0);
 		CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 5,
 				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0,
 				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0,
 				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,
 				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,
 				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);
+		CRTC_REG_UPDATE(
+				CRTC0_CRTC_V_TOTAL_MIN,
+				CRTC_V_TOTAL_MIN, 0);
+		CRTC_REG_UPDATE(
+				CRTC0_CRTC_V_TOTAL_MAX,
+				CRTC_V_TOTAL_MAX, 0);
 		CRTC_REG_UPDATE(
 				CRTC0_CRTC_STATIC_SCREEN_CONTROL,
 				CRTC_STATIC_SCREEN_EVENT_MASK,

drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c+0−49

@@ -691,23 +691,6 @@ static void destruct(struct dce110_resource_pool *pool) · 690 unmodified lines
691	}	691	}
692	}	692	}
693		693
694	static enum dc_status build_mapped_resource(
695	const struct dc *dc,
696	struct dc_state *context,
697	struct dc_stream_state *stream)
698	{
699	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
700
701	if (!pipe_ctx)
702	return DC_ERROR_UNEXPECTED;
703
704	dce110_resource_build_pipe_hw_param(pipe_ctx);
705
706	resource_build_info_frame(pipe_ctx);
707
708	return DC_OK;
709	}
710
711	bool dce80_validate_bandwidth(	694	bool dce80_validate_bandwidth(
712	struct dc *dc,	695	struct dc *dc,
713	struct dc_state *context)	696	struct dc_state *context)
@@ -749,37 +732,6 @@ enum dc_status dce80_validate_global( · 35 unmodified lines
749	return DC_OK;	732	return DC_OK;
750	}	733	}
751		734
752	enum dc_status dce80_validate_guaranteed(
753	struct dc *dc,
754	struct dc_stream_state *dc_stream,
755	struct dc_state *context)
756	{
757	enum dc_status result = DC_ERROR_UNEXPECTED;
758
759	context->streams[0] = dc_stream;
760	dc_stream_retain(context->streams[0]);
761	context->stream_count++;
762
763	result = resource_map_pool_resources(dc, context, dc_stream);
764
765	if (result == DC_OK)
766	result = resource_map_clock_resources(dc, context, dc_stream);
767
768	if (result == DC_OK)
769	result = build_mapped_resource(dc, context, dc_stream);
770
771	if (result == DC_OK) {
772	validate_guaranteed_copy_streams(
773	context, dc->caps.max_streams);
774	result = resource_build_scaling_params_for_context(dc, context);
775	}
776
777	if (result == DC_OK)
778	result = dce80_validate_bandwidth(dc, context);
779
780	return result;
781	}
782
783	static void dce80_destroy_resource_pool(struct resource_pool **pool)	735	static void dce80_destroy_resource_pool(struct resource_pool **pool)
784	{	736	{
785	struct dce110_resource_pool dce110_pool = TO_DCE110_RES_POOL(pool);	737	struct dce110_resource_pool dce110_pool = TO_DCE110_RES_POOL(pool);
@@ -792,7 +744,6 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool) · 6 unmodified lines
792	static const struct resource_funcs dce80_res_pool_funcs = {	744	static const struct resource_funcs dce80_res_pool_funcs = {
793	.destroy = dce80_destroy_resource_pool,	745	.destroy = dce80_destroy_resource_pool,
794	.link_enc_create = dce80_link_encoder_create,	746	.link_enc_create = dce80_link_encoder_create,
795	.validate_guaranteed = dce80_validate_guaranteed,
796	.validate_bandwidth = dce80_validate_bandwidth,	747	.validate_bandwidth = dce80_validate_bandwidth,
797	.validate_plane = dce100_validate_plane,	748	.validate_plane = dce100_validate_plane,
798	.add_stream_to_ctx = dce100_add_stream_to_ctx,	749	.add_stream_to_ctx = dce100_add_stream_to_ctx,

drivers/gpu/drm/amd/display/dc/dcn10/Makefile+1−1

@@ -26,7 +26,7 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \ · 25 unmodified lines
26	dcn10_dpp.o dcn10_opp.o dcn10_optc.o \	26	dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
27	dcn10_hubp.o dcn10_mpc.o \	27	dcn10_hubp.o dcn10_mpc.o \
28	dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \	28	dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
29	dcn10_hubbub.o	29	dcn10_hubbub.o dcn10_stream_encoder.o
30		30
31	AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))	31	AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
32		32

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c+6−6

@@ -367,15 +367,15 @@ bool cm_helper_translate_curve_to_hw_format( · 366 unmodified lines
367		367
368	lut_params->hw_points_num = hw_points;	368	lut_params->hw_points_num = hw_points;
369		369
370	i = 1;	370	k = 0;
371	for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {	371	for (i = 1; i < MAX_REGIONS_NUMBER; i++) {
372	if (seg_distr[k] != -1) {	372	if (seg_distr[k] != -1) {
373	lut_params->arr_curve_points[k].segments_num =	373	lut_params->arr_curve_points[k].segments_num =
374	seg_distr[k];	374	seg_distr[k];
375	lut_params->arr_curve_points[i].offset =	375	lut_params->arr_curve_points[i].offset =
376	lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);	376	lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
377	}	377	}
378	i++;	378	k++;
379	}	379	}
380		380
381	if (seg_distr[k] != -1)	381	if (seg_distr[k] != -1)
@@ -529,15 +529,15 @@ bool cm_helper_translate_curve_to_degamma_hw_format( · 147 unmodified lines
529		529
530	lut_params->hw_points_num = hw_points;	530	lut_params->hw_points_num = hw_points;
531		531
532	i = 1;	532	k = 0;
533	for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {	533	for (i = 1; i < MAX_REGIONS_NUMBER; i++) {
534	if (seg_distr[k] != -1) {	534	if (seg_distr[k] != -1) {
535	lut_params->arr_curve_points[k].segments_num =	535	lut_params->arr_curve_points[k].segments_num =
536	seg_distr[k];	536	seg_distr[k];
537	lut_params->arr_curve_points[i].offset =	537	lut_params->arr_curve_points[i].offset =
538	lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);	538	lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
539	}	539	}
540	i++;	540	k++;
541	}	541	}
542		542
543	if (seg_distr[k] != -1)	543	if (seg_distr[k] != -1)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c+34−2

 	GAMUT_REMAP_COMB_COEFF
 };
+void dpp_read_state(struct dpp *dpp_base,
+		struct dcn_dpp_state *s)
+{
+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+	REG_GET(CM_IGAM_CONTROL,
+			CM_IGAM_LUT_MODE, &s->igam_lut_mode);
+	REG_GET(CM_IGAM_CONTROL,
+			CM_IGAM_INPUT_FORMAT, &s->igam_input_format);
+	REG_GET(CM_DGAM_CONTROL,
+			CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
+	REG_GET(CM_RGAM_CONTROL,
+			CM_RGAM_LUT_MODE, &s->rgam_lut_mode);
+	REG_GET(CM_GAMUT_REMAP_CONTROL,
+			CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
+	s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
+	s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
+	s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
+	s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
+	s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
+	s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
+}
 /* Program gamut remap in bypass mode */
 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
 {
 	else
 		pixel_width = scl_data->viewport.width;
+	/* Some ASICs does not support  FP16 scaling, so we reject modes require this*/
+	if (scl_data->viewport.width  != scl_data->h_active &&
+		scl_data->viewport.height != scl_data->v_active &&
+		dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
+		scl_data->format == PIXEL_FORMAT_FP16)
+		return false;
 	/* TODO: add lb check */
 	/* No support for programming ratio of 4, drop to 3.99999.. */
 		struct dpp *dpp_base,
 		enum surface_pixel_format format,
 		enum expansion_mode mode,
-		struct csc_transform input_csc_color_matrix,
+		struct dc_csc_transform input_csc_color_matrix,
 		enum dc_color_space input_color_space)
 {
 	uint32_t pixel_format;
 	if (src_x_offset >= (int)param->viewport_width)
 		cur_en = 0;  /* not visible beyond right edge*/
-	if (src_x_offset + (int)width < 0)
+	if (src_x_offset + (int)width <= 0)
 		cur_en = 0;  /* not visible beyond left edge*/
 	REG_UPDATE(CURSOR0_CONTROL,
 }
 static const struct dpp_funcs dcn10_dpp_funcs = {
+		.dpp_read_state = dpp_read_state,
 		.dpp_reset = dpp_reset,
 		.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
 		.dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h+73−3

 #define TF_REG_LIST_DCN(id) \
 	SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
 	SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
+	SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
+	SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
+	SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
+	SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
 	SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
 	SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
 	SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
 	SRI(CM_DGAM_LUT_DATA, CM, id), \
 	SRI(CM_CONTROL, CM, id), \
 	SRI(CM_DGAM_CONTROL, CM, id), \
+	SRI(CM_TEST_DEBUG_INDEX, CM, id), \
+	SRI(CM_TEST_DEBUG_DATA, CM, id), \
 	SRI(FORMAT_CONTROL, CNVC_CFG, id), \
 	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
 	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
 	TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
 	TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
 	TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
+	TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
+	TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
+	TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
+	TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
+	TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
+	TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
+	TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
+	TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
 	TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
 	TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
 	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
 	TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
 	TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
 	TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
+	TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
 	TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
 	TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
 	TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
+/*
+ *
+	DCN1 CM debug status register definition
+	register :ID9_CM_STATUS do
+	implement_ref :cm
+	map to:  :cmdebugind, at: j
+	width 32
+	disclosure   NEVER
+		field :ID9_VUPDATE_CFG, [0], R
+		field :ID9_IGAM_LUT_MODE, [2..1], R
+		field :ID9_BNS_BYPASS, [3], R
+		field :ID9_ICSC_MODE, [5..4], R
+		field :ID9_DGAM_LUT_MODE, [8..6], R
+		field :ID9_HDR_BYPASS, [9], R
+		field :ID9_GAMUT_REMAP_MODE, [11..10], R
+		field :ID9_RGAM_LUT_MODE, [14..12], R
+		#1 free bit
+		field :ID9_OCSC_MODE, [18..16], R
+		field :ID9_DENORM_MODE, [21..19], R
+		field :ID9_ROUND_TRUNC_MODE, [25..22], R
+		field :ID9_DITHER_EN, [26], R
+		field :ID9_DITHER_MODE, [28..27], R
+	end
+*/
+#define TF_DEBUG_REG_LIST_SH_DCN10 \
+	.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 4, \
+	.CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 16
+#define TF_DEBUG_REG_LIST_MASK_DCN10 \
+	.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30, \
+	.CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 0x70000
 #define TF_REG_FIELD_LIST(type) \
 	type EXT_OVERSCAN_LEFT; \
 	type EXT_OVERSCAN_RIGHT; \
 	type CM_GAMUT_REMAP_MODE; \
 	type CM_GAMUT_REMAP_C11; \
 	type CM_GAMUT_REMAP_C12; \
+	type CM_GAMUT_REMAP_C13; \
+	type CM_GAMUT_REMAP_C14; \
+	type CM_GAMUT_REMAP_C21; \
+	type CM_GAMUT_REMAP_C22; \
+	type CM_GAMUT_REMAP_C23; \
+	type CM_GAMUT_REMAP_C24; \
+	type CM_GAMUT_REMAP_C31; \
+	type CM_GAMUT_REMAP_C32; \
 	type CM_GAMUT_REMAP_C33; \
 	type CM_GAMUT_REMAP_C34; \
 	type CM_COMA_C11; \
 	type CUR0_EXPANSION_MODE; \
 	type CUR0_ENABLE; \
 	type CM_BYPASS; \
+	type CM_TEST_DEBUG_INDEX; \
+	type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \
+	type CM_TEST_DEBUG_DATA_ID9_OCSC_MODE;\
 	type FORMAT_CONTROL__ALPHA_EN; \
 	type CUR0_COLOR0; \
 	type CUR0_COLOR1; \
 	uint32_t RECOUT_SIZE; \
 	uint32_t CM_GAMUT_REMAP_CONTROL; \
 	uint32_t CM_GAMUT_REMAP_C11_C12; \
+	uint32_t CM_GAMUT_REMAP_C13_C14; \
+	uint32_t CM_GAMUT_REMAP_C21_C22; \
+	uint32_t CM_GAMUT_REMAP_C23_C24; \
+	uint32_t CM_GAMUT_REMAP_C31_C32; \
 	uint32_t CM_GAMUT_REMAP_C33_C34; \
 	uint32_t CM_COMA_C11_C12; \
 	uint32_t CM_COMA_C33_C34; \
 	uint32_t CM_IGAM_LUT_RW_CONTROL; \
 	uint32_t CM_IGAM_LUT_RW_INDEX; \
 	uint32_t CM_IGAM_LUT_SEQ_COLOR; \
+	uint32_t CM_TEST_DEBUG_INDEX; \
+	uint32_t CM_TEST_DEBUG_DATA; \
 	uint32_t FORMAT_CONTROL; \
 	uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
 	uint32_t CURSOR_CONTROL; \
 enum dcn10_input_csc_select {
 	INPUT_CSC_SELECT_BYPASS = 0,
-	INPUT_CSC_SELECT_ICSC,
+	INPUT_CSC_SELECT_ICSC = 1,
-	INPUT_CSC_SELECT_COMA
+	INPUT_CSC_SELECT_COMA = 2
 };
 void dpp1_set_cursor_attributes(
 		struct scaler_data *scl_data,
 		const struct scaling_taps *in_taps);
+void dpp_read_state(struct dpp *dpp_base,
+		struct dcn_dpp_state *s);
 void dpp_reset(struct dpp *dpp_base);
 void dpp1_cm_program_regamma_lut(
 		struct dpp *dpp_base,
 		enum surface_pixel_format format,
 		enum expansion_mode mode,
-		struct csc_transform input_csc_color_matrix,
+		struct dc_csc_transform input_csc_color_matrix,
 		enum dc_color_space input_color_space);
 void dpp1_full_bypass(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c+56−34

@@ -216,41 +216,55 @@ static void dpp1_cm_program_color_matrix( · 215 unmodified lines
216	struct dcn10_dpp *dpp,	216	struct dcn10_dpp *dpp,
217	const uint16_t *regval)	217	const uint16_t *regval)
218	{	218	{
219	uint32_t mode;	219	uint32_t ocsc_mode;
		220	uint32_t cur_mode;
220	struct color_matrices_reg gam_regs;	221	struct color_matrices_reg gam_regs;
221		222
222	REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
223
224	if (regval == NULL) {	223	if (regval == NULL) {
225	BREAK_TO_DEBUGGER();	224	BREAK_TO_DEBUGGER();
226	return;	225	return;
227	}	226	}
228	mode = 4;	227
		228	/* determine which CSC matrix (ocsc or comb) we are using
		229	* currently. select the alternate set to double buffer
		230	* the CSC update so CSC is updated on frame boundary
		231	*/
		232	REG_SET(CM_TEST_DEBUG_INDEX, 0,
		233	CM_TEST_DEBUG_INDEX, 9);
		234
		235	REG_GET(CM_TEST_DEBUG_DATA,
		236	CM_TEST_DEBUG_DATA_ID9_OCSC_MODE, &cur_mode);
		237
		238	if (cur_mode != 4)
		239	ocsc_mode = 4;
		240	else
		241	ocsc_mode = 5;
		242
		243
229	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;	244	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
230	gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;	245	gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;
231	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;	246	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
232	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;	247	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
233		248
234	if (mode == 4) {	249	if (ocsc_mode == 4) {
235		250
236	gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);	251	gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
237	gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);	252	gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
238		253
239	cm_helper_program_color_matrices(
240	dpp->base.ctx,
241	regval,
242	&gam_regs);
243
244	} else {	254	} else {
245		255
246	gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);	256	gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
247	gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);	257	gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
248		258
249	cm_helper_program_color_matrices(
250	dpp->base.ctx,
251	regval,
252	&gam_regs);
253	}	259	}
		260
		261	cm_helper_program_color_matrices(
		262	dpp->base.ctx,
		263	regval,
		264	&gam_regs);
		265
		266	REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
		267
254	}	268	}
255		269
256	void dpp1_cm_set_output_csc_default(	270	void dpp1_cm_set_output_csc_default(
@@ -260,15 +274,14 @@ void dpp1_cm_set_output_csc_default( · 3 unmodified lines
260	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);	274	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
261	const uint16_t *regval = NULL;	275	const uint16_t *regval = NULL;
262	int arr_size;	276	int arr_size;
263	uint32_t ocsc_mode = 4;
264		277
265	regval = find_color_matrix(colorspace, &arr_size);	278	regval = find_color_matrix(colorspace, &arr_size);
266	if (regval == NULL) {	279	if (regval == NULL) {
267	BREAK_TO_DEBUGGER();	280	BREAK_TO_DEBUGGER();
268	return;	281	return;
269	}	282	}
		283
270	dpp1_cm_program_color_matrix(dpp, regval);	284	dpp1_cm_program_color_matrix(dpp, regval);
271	REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
272	}	285	}
273		286
274	static void dpp1_cm_get_reg_field(	287	static void dpp1_cm_get_reg_field(
@@ -329,9 +342,8 @@ void dpp1_cm_set_output_csc_adjustment( · 54 unmodified lines
329	const uint16_t *regval)	342	const uint16_t *regval)
330	{	343	{
331	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);	344	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
332	uint32_t ocsc_mode = 4;	345
333	dpp1_cm_program_color_matrix(dpp, regval);	346	dpp1_cm_program_color_matrix(dpp, regval);
334	REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
335	}	347	}
336		348
337	void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,	349	void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,
@@ -437,17 +449,18 @@ void dpp1_cm_program_regamma_lutb_settings( · 99 unmodified lines
437	void dpp1_program_input_csc(	449	void dpp1_program_input_csc(
438	struct dpp *dpp_base,	450	struct dpp *dpp_base,
439	enum dc_color_space color_space,	451	enum dc_color_space color_space,
440	enum dcn10_input_csc_select select,	452	enum dcn10_input_csc_select input_select,
441	const struct out_csc_color_matrix *tbl_entry)	453	const struct out_csc_color_matrix *tbl_entry)
442	{	454	{
443	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);	455	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
444	int i;	456	int i;
445	int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);	457	int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
446	const uint16_t *regval = NULL;	458	const uint16_t *regval = NULL;
447	uint32_t selection = 1;	459	uint32_t cur_select = 0;
		460	enum dcn10_input_csc_select select;
448	struct color_matrices_reg gam_regs;	461	struct color_matrices_reg gam_regs;
449		462
450	if (select == INPUT_CSC_SELECT_BYPASS) {	463	if (input_select == INPUT_CSC_SELECT_BYPASS) {
451	REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);	464	REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
452	return;	465	return;
453	}	466	}
@@ -467,36 +480,45 @@ void dpp1_program_input_csc( · 13 unmodified lines
467	regval = tbl_entry->regval;	480	regval = tbl_entry->regval;
468	}	481	}
469		482
470	if (select == INPUT_CSC_SELECT_COMA)	483	/* determine which CSC matrix (icsc or coma) we are using
471	selection = 2;	484	* currently. select the alternate set to double buffer
472	REG_SET(CM_ICSC_CONTROL, 0,	485	* the CSC update so CSC is updated on frame boundary
473	CM_ICSC_MODE, selection);	486	*/
		487	REG_SET(CM_TEST_DEBUG_INDEX, 0,
		488	CM_TEST_DEBUG_INDEX, 9);
		489
		490	REG_GET(CM_TEST_DEBUG_DATA,
		491	CM_TEST_DEBUG_DATA_ID9_ICSC_MODE, &cur_select);
		492
		493	if (cur_select != INPUT_CSC_SELECT_ICSC)
		494	select = INPUT_CSC_SELECT_ICSC;
		495	else
		496	select = INPUT_CSC_SELECT_COMA;
474		497
475	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;	498	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;
476	gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;	499	gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;
477	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;	500	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;
478	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;	501	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
479		502
480
481	if (select == INPUT_CSC_SELECT_ICSC) {	503	if (select == INPUT_CSC_SELECT_ICSC) {
482		504
483	gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);	505	gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
484	gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);	506	gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);
485		507
486	cm_helper_program_color_matrices(
487	dpp->base.ctx,
488	regval,
489	&gam_regs);
490	} else {	508	} else {
491		509
492	gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);	510	gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
493	gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);	511	gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
494		512
495	cm_helper_program_color_matrices(
496	dpp->base.ctx,
497	regval,
498	&gam_regs);
499	}	513	}
		514
		515	cm_helper_program_color_matrices(
		516	dpp->base.ctx,
		517	regval,
		518	&gam_regs);
		519
		520	REG_SET(CM_ICSC_CONTROL, 0,
		521	CM_ICSC_MODE, select);
500	}	522	}
501		523
502	//keep here for now, decide multi dce support later	524	//keep here for now, decide multi dce support later

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c+220−1

@@ -476,8 +476,227 @@ void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub) · 475 unmodified lines
476	DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);	476	DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
477	}	477	}
478		478
		479	static bool hubbub1_dcc_support_swizzle(
		480	enum swizzle_mode_values swizzle,
		481	unsigned int bytes_per_element,
		482	enum segment_order *segment_order_horz,
		483	enum segment_order *segment_order_vert)
		484	{
		485	bool standard_swizzle = false;
		486	bool display_swizzle = false;
		487
		488	switch (swizzle) {
		489	case DC_SW_4KB_S:
		490	case DC_SW_64KB_S:
		491	case DC_SW_VAR_S:
		492	case DC_SW_4KB_S_X:
		493	case DC_SW_64KB_S_X:
		494	case DC_SW_VAR_S_X:
		495	standard_swizzle = true;
		496	break;
		497	case DC_SW_4KB_D:
		498	case DC_SW_64KB_D:
		499	case DC_SW_VAR_D:
		500	case DC_SW_4KB_D_X:
		501	case DC_SW_64KB_D_X:
		502	case DC_SW_VAR_D_X:
		503	display_swizzle = true;
		504	break;
		505	default:
		506	break;
		507	}
		508
		509	if (bytes_per_element == 1 && standard_swizzle) {
		510	*segment_order_horz = segment_order__contiguous;
		511	*segment_order_vert = segment_order__na;
		512	return true;
		513	}
		514	if (bytes_per_element == 2 && standard_swizzle) {
		515	*segment_order_horz = segment_order__non_contiguous;
		516	*segment_order_vert = segment_order__contiguous;
		517	return true;
		518	}
		519	if (bytes_per_element == 4 && standard_swizzle) {
		520	*segment_order_horz = segment_order__non_contiguous;
		521	*segment_order_vert = segment_order__contiguous;
		522	return true;
		523	}
		524	if (bytes_per_element == 8 && standard_swizzle) {
		525	*segment_order_horz = segment_order__na;
		526	*segment_order_vert = segment_order__contiguous;
		527	return true;
		528	}
		529	if (bytes_per_element == 8 && display_swizzle) {
		530	*segment_order_horz = segment_order__contiguous;
		531	*segment_order_vert = segment_order__non_contiguous;
		532	return true;
		533	}
		534
		535	return false;
		536	}
		537
		538	static bool hubbub1_dcc_support_pixel_format(
		539	enum surface_pixel_format format,
		540	unsigned int *bytes_per_element)
		541	{
		542	/* DML: get_bytes_per_element */
		543	switch (format) {
		544	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
		545	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
		546	*bytes_per_element = 2;
		547	return true;
		548	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
		549	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
		550	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
		551	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
		552	*bytes_per_element = 4;
		553	return true;
		554	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
		555	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
		556	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
		557	*bytes_per_element = 8;
		558	return true;
		559	default:
		560	return false;
		561	}
		562	}
		563
		564	static void hubbub1_get_blk256_size(unsigned int blk256_width, unsigned int blk256_height,
		565	unsigned int bytes_per_element)
		566	{
		567	/* copied from DML. might want to refactor DML to leverage from DML */
		568	/* DML : get_blk256_size */
		569	if (bytes_per_element == 1) {
		570	*blk256_width = 16;
		571	*blk256_height = 16;
		572	} else if (bytes_per_element == 2) {
		573	*blk256_width = 16;
		574	*blk256_height = 8;
		575	} else if (bytes_per_element == 4) {
		576	*blk256_width = 8;
		577	*blk256_height = 8;
		578	} else if (bytes_per_element == 8) {
		579	*blk256_width = 8;
		580	*blk256_height = 4;
		581	}
		582	}
		583
		584	static void hubbub1_det_request_size(
		585	unsigned int height,
		586	unsigned int width,
		587	unsigned int bpe,
		588	bool *req128_horz_wc,
		589	bool *req128_vert_wc)
		590	{
		591	unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */
		592
		593	unsigned int blk256_height = 0;
		594	unsigned int blk256_width = 0;
		595	unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
		596
		597	hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe);
		598
		599	swath_bytes_horz_wc = height * blk256_height * bpe;
		600	swath_bytes_vert_wc = width * blk256_width * bpe;
		601
		602	req128_horz_wc = (2 swath_bytes_horz_wc <= detile_buf_size) ?
		603	false : /* full 256B request */
		604	true; /* half 128b request */
		605
		606	req128_vert_wc = (2 swath_bytes_vert_wc <= detile_buf_size) ?
		607	false : /* full 256B request */
		608	true; /* half 128b request */
		609	}
		610
		611	static bool hubbub1_get_dcc_compression_cap(struct hubbub *hubbub,
		612	const struct dc_dcc_surface_param *input,
		613	struct dc_surface_dcc_cap *output)
		614	{
		615	struct dc *dc = hubbub->ctx->dc;
		616	/* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
		617	enum dcc_control dcc_control;
		618	unsigned int bpe;
		619	enum segment_order segment_order_horz, segment_order_vert;
		620	bool req128_horz_wc, req128_vert_wc;
		621
		622	memset(output, 0, sizeof(*output));
		623
		624	if (dc->debug.disable_dcc == DCC_DISABLE)
		625	return false;
		626
		627	if (!hubbub->funcs->dcc_support_pixel_format(input->format, &bpe))
		628	return false;
		629
		630	if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
		631	&segment_order_horz, &segment_order_vert))
		632	return false;
		633
		634	hubbub1_det_request_size(input->surface_size.height, input->surface_size.width,
		635	bpe, &req128_horz_wc, &req128_vert_wc);
		636
		637	if (!req128_horz_wc && !req128_vert_wc) {
		638	dcc_control = dcc_control__256_256_xxx;
		639	} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
		640	if (!req128_horz_wc)
		641	dcc_control = dcc_control__256_256_xxx;
		642	else if (segment_order_horz == segment_order__contiguous)
		643	dcc_control = dcc_control__128_128_xxx;
		644	else
		645	dcc_control = dcc_control__256_64_64;
		646	} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
		647	if (!req128_vert_wc)
		648	dcc_control = dcc_control__256_256_xxx;
		649	else if (segment_order_vert == segment_order__contiguous)
		650	dcc_control = dcc_control__128_128_xxx;
		651	else
		652	dcc_control = dcc_control__256_64_64;
		653	} else {
		654	if ((req128_horz_wc &&
		655	segment_order_horz == segment_order__non_contiguous) \|\|
		656	(req128_vert_wc &&
		657	segment_order_vert == segment_order__non_contiguous))
		658	/* access_dir not known, must use most constraining */
		659	dcc_control = dcc_control__256_64_64;
		660	else
		661	/* reg128 is true for either horz and vert
		662	* but segment_order is contiguous
		663	*/
		664	dcc_control = dcc_control__128_128_xxx;
		665	}
		666
		667	if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
		668	dcc_control != dcc_control__256_256_xxx)
		669	return false;
		670
		671	switch (dcc_control) {
		672	case dcc_control__256_256_xxx:
		673	output->grph.rgb.max_uncompressed_blk_size = 256;
		674	output->grph.rgb.max_compressed_blk_size = 256;
		675	output->grph.rgb.independent_64b_blks = false;
		676	break;
		677	case dcc_control__128_128_xxx:
		678	output->grph.rgb.max_uncompressed_blk_size = 128;
		679	output->grph.rgb.max_compressed_blk_size = 128;
		680	output->grph.rgb.independent_64b_blks = false;
		681	break;
		682	case dcc_control__256_64_64:
		683	output->grph.rgb.max_uncompressed_blk_size = 256;
		684	output->grph.rgb.max_compressed_blk_size = 64;
		685	output->grph.rgb.independent_64b_blks = true;
		686	break;
		687	}
		688
		689	output->capable = true;
		690	output->const_color_support = false;
		691
		692	return true;
		693	}
		694
479	static const struct hubbub_funcs hubbub1_funcs = {	695	static const struct hubbub_funcs hubbub1_funcs = {
480	.update_dchub = hubbub1_update_dchub	696	.update_dchub = hubbub1_update_dchub,
		697	.dcc_support_swizzle = hubbub1_dcc_support_swizzle,
		698	.dcc_support_pixel_format = hubbub1_dcc_support_pixel_format,
		699	.get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
481	};	700	};
482		701
483	void hubbub1_construct(struct hubbub *hubbub,	702	void hubbub1_construct(struct hubbub *hubbub,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h+1−6

 #define __DC_HUBBUB_DCN10_H__
 #include "core_types.h"
+#include "dchubbub.h"
 #define HUBHUB_REG_LIST_DCN()\
 	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
 	struct dcn_hubbub_wm_set sets[4];
 };
-struct hubbub_funcs {
-	void (*update_dchub)(
-			struct hubbub *hubbub,
-			struct dchub_init_data *dh_data);
-};
 struct hubbub {
 	const struct hubbub_funcs *funcs;
 	struct dc_context *ctx;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c+176−11

@@ -146,6 +146,9 @@ void hubp1_program_size_and_rotation( · 145 unmodified lines
146	* 444 or 420 luma	146	* 444 or 420 luma
147	*/	147	*/
148	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {	148	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
		149	ASSERT(plane_size->video.chroma_pitch != 0);
		150	/* Chroma pitch zero can cause system hang! */
		151
149	pitch = plane_size->video.luma_pitch - 1;	152	pitch = plane_size->video.luma_pitch - 1;
150	meta_pitch = dcc->video.meta_pitch_l - 1;	153	meta_pitch = dcc->video.meta_pitch_l - 1;
151	pitch_c = plane_size->video.chroma_pitch - 1;	154	pitch_c = plane_size->video.chroma_pitch - 1;
@@ -535,11 +538,13 @@ void hubp1_program_deadline( · 383 unmodified lines
535	REG_SET(VBLANK_PARAMETERS_3, 0,	538	REG_SET(VBLANK_PARAMETERS_3, 0,
536	REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);	539	REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
537		540
538	REG_SET(NOM_PARAMETERS_0, 0,	541	if (REG(NOM_PARAMETERS_0))
539	DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);	542	REG_SET(NOM_PARAMETERS_0, 0,
		543	DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
540		544
541	REG_SET(NOM_PARAMETERS_1, 0,	545	if (REG(NOM_PARAMETERS_1))
542	REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);	546	REG_SET(NOM_PARAMETERS_1, 0,
		547	REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
543		548
544	REG_SET(NOM_PARAMETERS_4, 0,	549	REG_SET(NOM_PARAMETERS_4, 0,
545	DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);	550	DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
@@ -568,11 +573,13 @@ void hubp1_program_deadline( · 22 unmodified lines
568	REG_SET(VBLANK_PARAMETERS_4, 0,	573	REG_SET(VBLANK_PARAMETERS_4, 0,
569	REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);	574	REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
570		575
571	REG_SET(NOM_PARAMETERS_2, 0,	576	if (REG(NOM_PARAMETERS_2))
572	DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);	577	REG_SET(NOM_PARAMETERS_2, 0,
		578	DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
573		579
574	REG_SET(NOM_PARAMETERS_3, 0,	580	if (REG(NOM_PARAMETERS_3))
575	REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);	581	REG_SET(NOM_PARAMETERS_3, 0,
		582	REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
576		583
577	REG_SET(NOM_PARAMETERS_6, 0,	584	REG_SET(NOM_PARAMETERS_6, 0,
578	DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);	585	DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
@@ -609,6 +616,13 @@ void hubp1_program_deadline( · 30 unmodified lines
609	REG_SET(DCN_SURF1_TTU_CNTL1, 0,	616	REG_SET(DCN_SURF1_TTU_CNTL1, 0,
610	REFCYC_PER_REQ_DELIVERY_PRE,	617	REFCYC_PER_REQ_DELIVERY_PRE,
611	ttu_attr->refcyc_per_req_delivery_pre_c);	618	ttu_attr->refcyc_per_req_delivery_pre_c);
		619
		620	REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
		621	REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
		622	QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
		623	QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
		624	REG_SET(DCN_CUR0_TTU_CNTL1, 0,
		625	REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
612	}	626	}
613		627
614	static void hubp1_setup(	628	static void hubp1_setup(
@@ -752,9 +766,159 @@ void min_set_viewport( · 137 unmodified lines
752	PRI_VIEWPORT_Y_START_C, viewport_c->y);	766	PRI_VIEWPORT_Y_START_C, viewport_c->y);
753	}	767	}
754		768
755	void hubp1_read_state(struct dcn10_hubp *hubp1,	769	void hubp1_read_state(struct hubp *hubp)
756	struct dcn_hubp_state *s)
757	{	770	{
		771	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
		772	struct dcn_hubp_state *s = &hubp1->state;
		773	struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
		774	struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
		775	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
		776
		777	/* Requester */
		778	REG_GET(HUBPRET_CONTROL,
		779	DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
		780	REG_GET_4(DCN_EXPANSION_MODE,
		781	DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
		782	PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
		783	MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
		784	CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
		785	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
		786	CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
		787	MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
		788	META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
		789	MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
		790	DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
		791	MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
		792	SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
		793	PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
		794	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
		795	CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
		796	MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
		797	META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
		798	MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
		799	DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
		800	MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
		801	SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
		802	PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
		803
		804	/* DLG - Per hubp */
		805	REG_GET_2(BLANK_OFFSET_0,
		806	REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
		807	DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
		808
		809	REG_GET(BLANK_OFFSET_1,
		810	MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
		811
		812	REG_GET(DST_DIMENSIONS,
		813	REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
		814
		815	REG_GET_2(DST_AFTER_SCALER,
		816	REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
		817	DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
		818
		819	if (REG(PREFETCH_SETTINS))
		820	REG_GET_2(PREFETCH_SETTINS,
		821	DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
		822	VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
		823	else
		824	REG_GET_2(PREFETCH_SETTINGS,
		825	DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
		826	VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
		827
		828	REG_GET_2(VBLANK_PARAMETERS_0,
		829	DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
		830	DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
		831
		832	REG_GET(REF_FREQ_TO_PIX_FREQ,
		833	REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
		834
		835	/* DLG - Per luma/chroma */
		836	REG_GET(VBLANK_PARAMETERS_1,
		837	REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
		838
		839	REG_GET(VBLANK_PARAMETERS_3,
		840	REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
		841
		842	if (REG(NOM_PARAMETERS_0))
		843	REG_GET(NOM_PARAMETERS_0,
		844	DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
		845
		846	if (REG(NOM_PARAMETERS_1))
		847	REG_GET(NOM_PARAMETERS_1,
		848	REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
		849
		850	REG_GET(NOM_PARAMETERS_4,
		851	DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
		852
		853	REG_GET(NOM_PARAMETERS_5,
		854	REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
		855
		856	REG_GET_2(PER_LINE_DELIVERY_PRE,
		857	REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
		858	REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
		859
		860	REG_GET_2(PER_LINE_DELIVERY,
		861	REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
		862	REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
		863
		864	if (REG(PREFETCH_SETTINS_C))
		865	REG_GET(PREFETCH_SETTINS_C,
		866	VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
		867	else
		868	REG_GET(PREFETCH_SETTINGS_C,
		869	VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
		870
		871	REG_GET(VBLANK_PARAMETERS_2,
		872	REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
		873
		874	REG_GET(VBLANK_PARAMETERS_4,
		875	REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
		876
		877	if (REG(NOM_PARAMETERS_2))
		878	REG_GET(NOM_PARAMETERS_2,
		879	DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
		880
		881	if (REG(NOM_PARAMETERS_3))
		882	REG_GET(NOM_PARAMETERS_3,
		883	REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
		884
		885	REG_GET(NOM_PARAMETERS_6,
		886	DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
		887
		888	REG_GET(NOM_PARAMETERS_7,
		889	REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
		890
		891	/* TTU - per hubp */
		892	REG_GET_2(DCN_TTU_QOS_WM,
		893	QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
		894	QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
		895
		896	REG_GET_2(DCN_GLOBAL_TTU_CNTL,
		897	MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
		898	QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
		899
		900	/* TTU - per luma/chroma */
		901	/* Assumed surf0 is luma and 1 is chroma */
		902
		903	REG_GET_3(DCN_SURF0_TTU_CNTL0,
		904	REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
		905	QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
		906	QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
		907
		908	REG_GET(DCN_SURF0_TTU_CNTL1,
		909	REFCYC_PER_REQ_DELIVERY_PRE,
		910	&ttu_attr->refcyc_per_req_delivery_pre_l);
		911
		912	REG_GET_3(DCN_SURF1_TTU_CNTL0,
		913	REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
		914	QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
		915	QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
		916
		917	REG_GET(DCN_SURF1_TTU_CNTL1,
		918	REFCYC_PER_REQ_DELIVERY_PRE,
		919	&ttu_attr->refcyc_per_req_delivery_pre_c);
		920
		921	/* Rest of hubp */
758	REG_GET(DCSURF_SURFACE_CONFIG,	922	REG_GET(DCSURF_SURFACE_CONFIG,
759	SURFACE_PIXEL_FORMAT, &s->pixel_format);	923	SURFACE_PIXEL_FORMAT, &s->pixel_format);
760		924
@@ -897,7 +1061,7 @@ void hubp1_cursor_set_position( · 136 unmodified lines
897	if (src_x_offset >= (int)param->viewport_width)	1061	if (src_x_offset >= (int)param->viewport_width)
898	cur_en = 0; /* not visible beyond right edge*/	1062	cur_en = 0; /* not visible beyond right edge*/
899		1063
900	if (src_x_offset + (int)hubp->curs_attr.width < 0)	1064	if (src_x_offset + (int)hubp->curs_attr.width <= 0)
901	cur_en = 0; /* not visible beyond left edge*/	1065	cur_en = 0; /* not visible beyond left edge*/
902		1066
903	if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)	1067	if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
@@ -952,6 +1116,7 @@ static struct hubp_funcs dcn10_hubp_funcs = { · 48 unmodified lines
952	.hubp_disconnect = hubp1_disconnect,	1116	.hubp_disconnect = hubp1_disconnect,
953	.hubp_clk_cntl = hubp1_clk_cntl,	1117	.hubp_clk_cntl = hubp1_clk_cntl,
954	.hubp_vtg_sel = hubp1_vtg_sel,	1118	.hubp_vtg_sel = hubp1_vtg_sel,
		1119	.hubp_read_state = hubp1_read_state,
955	};	1120	};
956		1121
957	/*****************************************/	1122	/*****************************************/

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h+50−29

@@ -30,6 +30,7 @@ · 29 unmodified lines
30	#define TO_DCN10_HUBP(hubp)\	30	#define TO_DCN10_HUBP(hubp)\
31	container_of(hubp, struct dcn10_hubp, base)	31	container_of(hubp, struct dcn10_hubp, base)
32		32
		33	/* Register address initialization macro for all ASICs (including those with reduced functionality) */
33	#define HUBP_REG_LIST_DCN(id)\	34	#define HUBP_REG_LIST_DCN(id)\
34	SRI(DCHUBP_CNTL, HUBP, id),\	35	SRI(DCHUBP_CNTL, HUBP, id),\
35	SRI(HUBPREQ_DEBUG_DB, HUBP, id),\	36	SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
@@ -78,16 +79,12 @@ · 42 unmodified lines
78	SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\	79	SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
79	SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\	80	SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
80	SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\	81	SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
81	SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
82	SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
83	SRI(NOM_PARAMETERS_4, HUBPREQ, id),\	82	SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
84	SRI(NOM_PARAMETERS_5, HUBPREQ, id),\	83	SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
85	SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\	84	SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
86	SRI(PER_LINE_DELIVERY, HUBPREQ, id),\	85	SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
87	SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\	86	SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
88	SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\	87	SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
89	SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
90	SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
91	SRI(NOM_PARAMETERS_6, HUBPREQ, id),\	88	SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
92	SRI(NOM_PARAMETERS_7, HUBPREQ, id),\	89	SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
93	SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\	90	SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
@@ -96,11 +93,21 @@ · 2 unmodified lines
96	SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\	93	SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
97	SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\	94	SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
98	SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\	95	SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
99	SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\	96	SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\
		97	SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\
100	SRI(HUBP_CLK_CNTL, HUBP, id)	98	SRI(HUBP_CLK_CNTL, HUBP, id)
101		99
		100	/* Register address initialization macro for ASICs with VM */
		101	#define HUBP_REG_LIST_DCN_VM(id)\
		102	SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
		103	SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
		104	SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
		105	SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
		106	SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
		107
102	#define HUBP_REG_LIST_DCN10(id)\	108	#define HUBP_REG_LIST_DCN10(id)\
103	HUBP_REG_LIST_DCN(id),\	109	HUBP_REG_LIST_DCN(id),\
		110	HUBP_REG_LIST_DCN_VM(id),\
104	SRI(PREFETCH_SETTINS, HUBPREQ, id),\	111	SRI(PREFETCH_SETTINS, HUBPREQ, id),\
105	SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\	112	SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
106	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\	113	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
@@ -198,6 +205,8 @@ · 91 unmodified lines
198	uint32_t DCN_SURF0_TTU_CNTL1; \	205	uint32_t DCN_SURF0_TTU_CNTL1; \
199	uint32_t DCN_SURF1_TTU_CNTL0; \	206	uint32_t DCN_SURF1_TTU_CNTL0; \
200	uint32_t DCN_SURF1_TTU_CNTL1; \	207	uint32_t DCN_SURF1_TTU_CNTL1; \
		208	uint32_t DCN_CUR0_TTU_CNTL0; \
		209	uint32_t DCN_CUR0_TTU_CNTL1; \
201	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \	210	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \
202	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \	211	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \
203	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \	212	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \
@@ -237,6 +246,7 @@ · 33 unmodified lines
237	#define HUBP_SF(reg_name, field_name, post_fix)\	246	#define HUBP_SF(reg_name, field_name, post_fix)\
238	.field_name = reg_name ## __ ## field_name ## post_fix	247	.field_name = reg_name ## __ ## field_name ## post_fix
239		248
		249	/* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
240	#define HUBP_MASK_SH_LIST_DCN(mask_sh)\	250	#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
241	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\	251	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
242	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\	252	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
@@ -335,8 +345,6 @@ · 92 unmodified lines
335	HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\	345	HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
336	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\	346	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
337	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\	347	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
338	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
339	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
340	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\	348	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
341	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\	349	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
342	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\	350	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
@@ -345,8 +353,6 @@ · 2 unmodified lines
345	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\	353	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
346	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\	354	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
347	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\	355	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
348	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
349	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
350	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\	356	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
351	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\	357	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
352	HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\	358	HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
@@ -357,12 +363,24 @@ · 4 unmodified lines
357	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\	363	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
358	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\	364	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
359	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\	365	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
		366	HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
		367
		368	/* Mask/shift struct generation macro for ASICs with VM */
		369	#define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\
		370	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
		371	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
		372	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
		373	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
360	HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\	374	HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
361	HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\	375	HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
362	HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)	376	HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
		377	HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
		378	HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
		379	HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh)
363		380
364	#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\	381	#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\
365	HUBP_MASK_SH_LIST_DCN(mask_sh),\	382	HUBP_MASK_SH_LIST_DCN(mask_sh),\
		383	HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
366	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\	384	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
367	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\	385	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
368	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\	386	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
@@ -601,8 +619,29 @@ struct dcn_mi_mask { · 232 unmodified lines
601	DCN_HUBP_REG_FIELD_LIST(uint32_t);	619	DCN_HUBP_REG_FIELD_LIST(uint32_t);
602	};	620	};
603		621
		622	struct dcn_hubp_state {
		623	struct _vcs_dpi_display_dlg_regs_st dlg_attr;
		624	struct _vcs_dpi_display_ttu_regs_st ttu_attr;
		625	struct _vcs_dpi_display_rq_regs_st rq_regs;
		626	uint32_t pixel_format;
		627	uint32_t inuse_addr_hi;
		628	uint32_t viewport_width;
		629	uint32_t viewport_height;
		630	uint32_t rotation_angle;
		631	uint32_t h_mirror_en;
		632	uint32_t sw_mode;
		633	uint32_t dcc_en;
		634	uint32_t blank_en;
		635	uint32_t underflow_status;
		636	uint32_t ttu_disable;
		637	uint32_t min_ttu_vblank;
		638	uint32_t qos_level_low_wm;
		639	uint32_t qos_level_high_wm;
		640	};
		641
604	struct dcn10_hubp {	642	struct dcn10_hubp {
605	struct hubp base;	643	struct hubp base;
		644	struct dcn_hubp_state state;
606	const struct dcn_mi_registers *hubp_regs;	645	const struct dcn_mi_registers *hubp_regs;
607	const struct dcn_mi_shift *hubp_shift;	646	const struct dcn_mi_shift *hubp_shift;
608	const struct dcn_mi_mask *hubp_mask;	647	const struct dcn_mi_mask *hubp_mask;
@@ -680,25 +719,7 @@ void dcn10_hubp_construct( · 71 unmodified lines
680	const struct dcn_mi_shift *hubp_shift,	719	const struct dcn_mi_shift *hubp_shift,
681	const struct dcn_mi_mask *hubp_mask);	720	const struct dcn_mi_mask *hubp_mask);
682		721
683		722	void hubp1_read_state(struct hubp *hubp);
684	struct dcn_hubp_state {
685	uint32_t pixel_format;
686	uint32_t inuse_addr_hi;
687	uint32_t viewport_width;
688	uint32_t viewport_height;
689	uint32_t rotation_angle;
690	uint32_t h_mirror_en;
691	uint32_t sw_mode;
692	uint32_t dcc_en;
693	uint32_t blank_en;
694	uint32_t underflow_status;
695	uint32_t ttu_disable;
696	uint32_t min_ttu_vblank;
697	uint32_t qos_level_low_wm;
698	uint32_t qos_level_high_wm;
699	};
700	void hubp1_read_state(struct dcn10_hubp *hubp1,
701	struct dcn_hubp_state *s);
702		723
703	enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);	724	enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
704		725

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c+221−67

@@ -45,8 +45,8 @@ · 44 unmodified lines
45	#include "dcn10_hubbub.h"	45	#include "dcn10_hubbub.h"
46	#include "dcn10_cm_common.h"	46	#include "dcn10_cm_common.h"
47		47
48	#define DC_LOGGER \	48	#define DC_LOGGER_INIT(logger)
49	ctx->logger	49
50	#define CTX \	50	#define CTX \
51	hws->ctx	51	hws->ctx
52	#define REG(reg)\	52	#define REG(reg)\
@@ -56,16 +56,17 @@ · 3 unmodified lines
56	#define FN(reg_name, field_name) \	56	#define FN(reg_name, field_name) \
57	hws->shifts->field_name, hws->masks->field_name	57	hws->shifts->field_name, hws->masks->field_name
58		58
		59	/print is 17 wide, first two characters are spaces/
59	#define DTN_INFO_MICRO_SEC(ref_cycle) \	60	#define DTN_INFO_MICRO_SEC(ref_cycle) \
60	print_microsec(dc_ctx, ref_cycle)	61	print_microsec(dc_ctx, ref_cycle)
61		62
62	void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)	63	void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
63	{	64	{
64	static const uint32_t ref_clk_mhz = 48;	65	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;
65	static const unsigned int frac = 10;	66	static const unsigned int frac = 1000;
66	uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;	67	uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
67		68
68	DTN_INFO("%d.%d \t ",	69	DTN_INFO(" %11d.%03d",
69	us_x10 / frac,	70	us_x10 / frac,
70	us_x10 % frac);	71	us_x10 % frac);
71	}	72	}
@@ -92,14 +93,14 @@ void dcn10_log_hubbub_state(struct dc *dc) · 20 unmodified lines
92		93
93	hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);	94	hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
94		95
95	DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "	96	DTN_INFO("HUBBUB WM: data_urgent pte_meta_urgent"
96	"sr_enter \t sr_exit \t dram_clk_change \n");	97	" sr_enter sr_exit dram_clk_change\n");
97		98
98	for (i = 0; i < 4; i++) {	99	for (i = 0; i < 4; i++) {
99	struct dcn_hubbub_wm_set *s;	100	struct dcn_hubbub_wm_set *s;
100		101
101	s = &wm.sets[i];	102	s = &wm.sets[i];
102	DTN_INFO("WM_Set[%d]:\t ", s->wm_set);	103	DTN_INFO("WM_Set[%d]:", s->wm_set);
103	DTN_INFO_MICRO_SEC(s->data_urgent);	104	DTN_INFO_MICRO_SEC(s->data_urgent);
104	DTN_INFO_MICRO_SEC(s->pte_meta_urgent);	105	DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
105	DTN_INFO_MICRO_SEC(s->sr_enter);	106	DTN_INFO_MICRO_SEC(s->sr_enter);
@@ -111,6 +112,116 @@ void dcn10_log_hubbub_state(struct dc *dc) · 5 unmodified lines
111	DTN_INFO("\n");	112	DTN_INFO("\n");
112	}	113	}
113		114
		115	static void dcn10_log_hubp_states(struct dc *dc)
		116	{
		117	struct dc_context *dc_ctx = dc->ctx;
		118	struct resource_pool *pool = dc->res_pool;
		119	int i;
		120
		121	DTN_INFO("HUBP: format addr_hi width height"
		122	" rot mir sw_mode dcc_en blank_en ttu_dis underflow"
		123	" min_ttu_vblank qos_low_wm qos_high_wm\n");
		124	for (i = 0; i < pool->pipe_count; i++) {
		125	struct hubp *hubp = pool->hubps[i];
		126	struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
		127
		128	hubp->funcs->hubp_read_state(hubp);
		129
		130	DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh"
		131	" %6d %8d %7d %8xh",
		132	hubp->inst,
		133	s->pixel_format,
		134	s->inuse_addr_hi,
		135	s->viewport_width,
		136	s->viewport_height,
		137	s->rotation_angle,
		138	s->h_mirror_en,
		139	s->sw_mode,
		140	s->dcc_en,
		141	s->blank_en,
		142	s->ttu_disable,
		143	s->underflow_status);
		144	DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
		145	DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
		146	DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
		147	DTN_INFO("\n");
		148	}
		149
		150	DTN_INFO("\n=========RQ========\n");
		151	DTN_INFO("HUBP: drq_exp_m prq_exp_m mrq_exp_m crq_exp_m plane1_ba L:chunk_s min_chu_s meta_ch_s"
		152	" min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h C:chunk_s min_chu_s meta_ch_s"
		153	" min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h\n");
		154	for (i = 0; i < pool->pipe_count; i++) {
		155	struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
		156	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
		157
		158	DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
		159	i, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
		160	rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
		161	rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
		162	rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
		163	rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
		164	rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
		165	rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
		166	rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
		167	rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
		168	}
		169
		170	DTN_INFO("========DLG========\n");
		171	DTN_INFO("HUBP: rc_hbe dlg_vbe min_d_y_n rc_per_ht rc_x_a_s "
		172	" dst_y_a_s dst_y_pf dst_y_vvb dst_y_rvb dst_y_vfl dst_y_rfl rf_pix_fq"
		173	" vratio_pf vrat_pf_c rc_pg_vbl rc_pg_vbc rc_mc_vbl rc_mc_vbc rc_pg_fll"
		174	" rc_pg_flc rc_mc_fll rc_mc_flc pr_nom_l pr_nom_c rc_pg_nl rc_pg_nc "
		175	" mr_nom_l mr_nom_c rc_mc_nl rc_mc_nc rc_ld_pl rc_ld_pc rc_ld_l "
		176	" rc_ld_c cha_cur0 ofst_cur1 cha_cur1 vr_af_vc0 ddrq_limt x_rt_dlay"
		177	" x_rp_dlay x_rr_sfl\n");
		178	for (i = 0; i < pool->pipe_count; i++) {
		179	struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
		180	struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
		181
		182	DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
		183	"% 8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
		184	" %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
		185	i, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
		186	dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
		187	dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
		188	dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
		189	dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
		190	dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
		191	dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
		192	dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
		193	dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
		194	dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
		195	dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
		196	dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
		197	dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
		198	dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
		199	dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
		200	dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
		201	dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
		202	dlg_regs->xfc_reg_remote_surface_flip_latency);
		203	}
		204
		205	DTN_INFO("========TTU========\n");
		206	DTN_INFO("HUBP: qos_ll_wm qos_lh_wm mn_ttu_vb qos_l_flp rc_rd_p_l rc_rd_l rc_rd_p_c"
		207	" rc_rd_c rc_rd_c0 rc_rd_pc0 rc_rd_c1 rc_rd_pc1 qos_lf_l qos_rds_l"
		208	" qos_lf_c qos_rds_c qos_lf_c0 qos_rds_c0 qos_lf_c1 qos_rds_c1\n");
		209	for (i = 0; i < pool->pipe_count; i++) {
		210	struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
		211	struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
		212
		213	DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
		214	i, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
		215	ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
		216	ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
		217	ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
		218	ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
		219	ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
		220	ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
		221	}
		222	DTN_INFO("\n");
		223	}
		224
114	void dcn10_log_hw_state(struct dc *dc)	225	void dcn10_log_hw_state(struct dc *dc)
115	{	226	{
116	struct dc_context *dc_ctx = dc->ctx;	227	struct dc_context *dc_ctx = dc->ctx;
@@ -121,41 +232,64 @@ void dcn10_log_hw_state(struct dc *dc) · 4 unmodified lines
121		232
122	dcn10_log_hubbub_state(dc);	233	dcn10_log_hubbub_state(dc);
123		234
124	DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "	235	dcn10_log_hubp_states(dc);
125	"rotation \t mirror \t sw_mode \t "
126	"dcc_en \t blank_en \t ttu_dis \t underflow \t "
127	"min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
128		236
		237	DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode"
		238	" GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 "
		239	"C31 C32 C33 C34\n");
129	for (i = 0; i < pool->pipe_count; i++) {	240	for (i = 0; i < pool->pipe_count; i++) {
130	struct hubp *hubp = pool->hubps[i];	241	struct dpp *dpp = pool->dpps[i];
131	struct dcn_hubp_state s;	242	struct dcn_dpp_state s;
		243
		244	dpp->funcs->dpp_read_state(dpp, &s);
		245
		246	DTN_INFO("[%2d]: %11xh %-11s %-11s %-11s"
		247	"%8x %08xh %08xh %08xh %08xh %08xh %08xh",
		248	dpp->inst,
		249	s.igam_input_format,
		250	(s.igam_lut_mode == 0) ? "BypassFixed" :
		251	((s.igam_lut_mode == 1) ? "BypassFloat" :
		252	((s.igam_lut_mode == 2) ? "RAM" :
		253	((s.igam_lut_mode == 3) ? "RAM" :
		254	"Unknown"))),
		255	(s.dgam_lut_mode == 0) ? "Bypass" :
		256	((s.dgam_lut_mode == 1) ? "sRGB" :
		257	((s.dgam_lut_mode == 2) ? "Ycc" :
		258	((s.dgam_lut_mode == 3) ? "RAM" :
		259	((s.dgam_lut_mode == 4) ? "RAM" :
		260	"Unknown")))),
		261	(s.rgam_lut_mode == 0) ? "Bypass" :
		262	((s.rgam_lut_mode == 1) ? "sRGB" :
		263	((s.rgam_lut_mode == 2) ? "Ycc" :
		264	((s.rgam_lut_mode == 3) ? "RAM" :
		265	((s.rgam_lut_mode == 4) ? "RAM" :
		266	"Unknown")))),
		267	s.gamut_remap_mode,
		268	s.gamut_remap_c11_c12,
		269	s.gamut_remap_c13_c14,
		270	s.gamut_remap_c21_c22,
		271	s.gamut_remap_c23_c24,
		272	s.gamut_remap_c31_c32,
		273	s.gamut_remap_c33_c34);
		274	DTN_INFO("\n");
		275	}
		276	DTN_INFO("\n");
132		277
133	hubp1_read_state(TO_DCN10_HUBP(hubp), &s);	278	DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n");
		279	for (i = 0; i < pool->pipe_count; i++) {
		280	struct mpcc_state s = {0};
134		281
135	DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "	282	pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
136	"%xh \t %xh \t %xh \t "	283	if (s.opp_id != 0xf)
137	"%d \t %d \t %d \t %xh \t",	284	DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d\n",
138	hubp->inst,	285	i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
139	s.pixel_format,	286	s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
140	s.inuse_addr_hi,	287	s.idle);
141	s.viewport_width,
142	s.viewport_height,
143	s.rotation_angle,
144	s.h_mirror_en,
145	s.sw_mode,
146	s.dcc_en,
147	s.blank_en,
148	s.ttu_disable,
149	s.underflow_status);
150	DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
151	DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
152	DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
153	DTN_INFO("\n");
154	}	288	}
155	DTN_INFO("\n");	289	DTN_INFO("\n");
156		290
157	DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "	291	DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel"
158	"h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");	292	" h_bs h_be h_ss h_se hpol htot vtot underflow\n");
159		293
160	for (i = 0; i < pool->timing_generator_count; i++) {	294	for (i = 0; i < pool->timing_generator_count; i++) {
161	struct timing_generator *tg = pool->timing_generators[i];	295	struct timing_generator *tg = pool->timing_generators[i];
@@ -167,9 +301,8 @@ void dcn10_log_hw_state(struct dc *dc) · 5 unmodified lines
167	if ((s.otg_enabled & 1) == 0)	301	if ((s.otg_enabled & 1) == 0)
168	continue;	302	continue;
169		303
170	DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "	304	DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
171	"%d \t %d \t %d \t %d \t %d \t %d \t "	305	" %5d %5d %5d %5d %9d\n",
172	"%d \t %d \t %d \t %d \t %d \t ",
173	tg->inst,	306	tg->inst,
174	s.v_blank_start,	307	s.v_blank_start,
175	s.v_blank_end,	308	s.v_blank_end,
@@ -178,6 +311,8 @@ void dcn10_log_hw_state(struct dc *dc) · 2 unmodified lines
178	s.v_sync_a_pol,	311	s.v_sync_a_pol,
179	s.v_total_max,	312	s.v_total_max,
180	s.v_total_min,	313	s.v_total_min,
		314	s.v_total_max_sel,
		315	s.v_total_min_sel,
181	s.h_blank_start,	316	s.h_blank_start,
182	s.h_blank_end,	317	s.h_blank_end,
183	s.h_sync_a_start,	318	s.h_sync_a_start,
@@ -186,10 +321,19 @@ void dcn10_log_hw_state(struct dc *dc) · 2 unmodified lines
186	s.h_total,	321	s.h_total,
187	s.v_total,	322	s.v_total,
188	s.underflow_occurred_status);	323	s.underflow_occurred_status);
189	DTN_INFO("\n");
190	}	324	}
191	DTN_INFO("\n");	325	DTN_INFO("\n");
192		326
		327	DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n"
		328	"dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
		329	dc->current_state->bw.dcn.calc_clk.dcfclk_khz,
		330	dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
		331	dc->current_state->bw.dcn.calc_clk.dispclk_khz,
		332	dc->current_state->bw.dcn.calc_clk.dppclk_khz,
		333	dc->current_state->bw.dcn.calc_clk.max_supported_dppclk_khz,
		334	dc->current_state->bw.dcn.calc_clk.fclk_khz,
		335	dc->current_state->bw.dcn.calc_clk.socclk_khz);
		336
193	log_mpc_crc(dc);	337	log_mpc_crc(dc);
194		338
195	DTN_INFO_END();	339	DTN_INFO_END();
@@ -354,7 +498,7 @@ static void power_on_plane( · 158 unmodified lines
354	struct dce_hwseq *hws,	498	struct dce_hwseq *hws,
355	int plane_id)	499	int plane_id)
356	{	500	{
357	struct dc_context *ctx = hws->ctx;	501	DC_LOGGER_INIT(hws->ctx->logger);
358	if (REG(DC_IP_REQUEST_CNTL)) {	502	if (REG(DC_IP_REQUEST_CNTL)) {
359	REG_SET(DC_IP_REQUEST_CNTL, 0,	503	REG_SET(DC_IP_REQUEST_CNTL, 0,
360	IP_REQUEST_EN, 1);	504	IP_REQUEST_EN, 1);
@@ -461,7 +605,7 @@ static void false_optc_underflow_wa( · 100 unmodified lines
461	tg->funcs->clear_optc_underflow(tg);	605	tg->funcs->clear_optc_underflow(tg);
462	}	606	}
463		607
464	static enum dc_status dcn10_prog_pixclk_crtc_otg(	608	static enum dc_status dcn10_enable_stream_timing(
465	struct pipe_ctx *pipe_ctx,	609	struct pipe_ctx *pipe_ctx,
466	struct dc_state *context,	610	struct dc_state *context,
467	struct dc *dc)	611	struct dc *dc)
@@ -553,7 +697,7 @@ static void reset_back_end_for_pipe( · 85 unmodified lines
553	struct dc_state *context)	697	struct dc_state *context)
554	{	698	{
555	int i;	699	int i;
556	struct dc_context *ctx = dc->ctx;	700	DC_LOGGER_INIT(dc->ctx->logger);
557	if (pipe_ctx->stream_res.stream_enc == NULL) {	701	if (pipe_ctx->stream_res.stream_enc == NULL) {
558	pipe_ctx->stream = NULL;	702	pipe_ctx->stream = NULL;
559	return;	703	return;
@@ -649,7 +793,7 @@ static void plane_atomic_power_down(struct dc dc, struct pipe_ctx pipe_ctx) · 89 unmodified lines
649	{	793	{
650	struct dce_hwseq *hws = dc->hwseq;	794	struct dce_hwseq *hws = dc->hwseq;
651	struct dpp *dpp = pipe_ctx->plane_res.dpp;	795	struct dpp *dpp = pipe_ctx->plane_res.dpp;
652	struct dc_context *ctx = dc->ctx;	796	DC_LOGGER_INIT(dc->ctx->logger);
653		797
654	if (REG(DC_IP_REQUEST_CNTL)) {	798	if (REG(DC_IP_REQUEST_CNTL)) {
655	REG_SET(DC_IP_REQUEST_CNTL, 0,	799	REG_SET(DC_IP_REQUEST_CNTL, 0,
@@ -699,7 +843,7 @@ static void plane_atomic_disable(struct dc dc, struct pipe_ctx pipe_ctx) · 43 unmodified lines
699		843
700	static void dcn10_disable_plane(struct dc dc, struct pipe_ctx pipe_ctx)	844	static void dcn10_disable_plane(struct dc dc, struct pipe_ctx pipe_ctx)
701	{	845	{
702	struct dc_context *ctx = dc->ctx;	846	DC_LOGGER_INIT(dc->ctx->logger);
703		847
704	if (!pipe_ctx->plane_res.hubp \|\| pipe_ctx->plane_res.hubp->power_gated)	848	if (!pipe_ctx->plane_res.hubp \|\| pipe_ctx->plane_res.hubp->power_gated)
705	return;	849	return;
@@ -945,9 +1089,8 @@ static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx, · 239 unmodified lines
945	tf = plane_state->in_transfer_func;	1089	tf = plane_state->in_transfer_func;
946		1090
947	if (plane_state->gamma_correction &&	1091	if (plane_state->gamma_correction &&
948	plane_state->gamma_correction->is_identity)	1092	!plane_state->gamma_correction->is_identity
949	dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);	1093	&& dce_use_lut(plane_state->format))
950	else if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
951	dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);	1094	dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
952		1095
953	if (tf == NULL)	1096	if (tf == NULL)
@@ -1433,7 +1576,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, · 479 unmodified lines
1433	}	1576	}
1434	}	1577	}
1435		1578
1436	static void program_output_csc(struct dc *dc,	1579	static void dcn10_program_output_csc(struct dc *dc,
1437	struct pipe_ctx *pipe_ctx,	1580	struct pipe_ctx *pipe_ctx,
1438	enum dc_color_space colorspace,	1581	enum dc_color_space colorspace,
1439	uint16_t *matrix,	1582	uint16_t *matrix,
@@ -1623,6 +1766,8 @@ static void update_mpcc(struct dc dc, struct pipe_ctx pipe_ctx) · 183 unmodified lines
1623	struct mpc *mpc = dc->res_pool->mpc;	1766	struct mpc *mpc = dc->res_pool->mpc;
1624	struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);	1767	struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1625		1768
		1769
		1770
1626	/* TODO: proper fix once fpga works */	1771	/* TODO: proper fix once fpga works */
1627		1772
1628	if (dc->debug.surface_visual_confirm)	1773	if (dc->debug.surface_visual_confirm)
@@ -1649,6 +1794,7 @@ static void update_mpcc(struct dc dc, struct pipe_ctx pipe_ctx) · 20 unmodified lines
1649	pipe_ctx->stream->output_color_space)	1794	pipe_ctx->stream->output_color_space)
1650	&& per_pixel_alpha;	1795	&& per_pixel_alpha;
1651		1796
		1797
1652	/*	1798	/*
1653	* TODO: remove hack	1799	* TODO: remove hack
1654	* Note: currently there is a bug in init_hw such that	1800	* Note: currently there is a bug in init_hw such that
@@ -1659,6 +1805,12 @@ static void update_mpcc(struct dc dc, struct pipe_ctx pipe_ctx) · 4 unmodified lines
1659	*/	1805	*/
1660	mpcc_id = hubp->inst;	1806	mpcc_id = hubp->inst;
1661		1807
		1808	/* If there is no full update, don't need to touch MPC tree*/
		1809	if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
		1810	mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
		1811	return;
		1812	}
		1813
1662	/* check if this MPCC is already being used */	1814	/* check if this MPCC is already being used */
1663	new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);	1815	new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1664	/* remove MPCC if being used */	1816	/* remove MPCC if being used */
@@ -1777,7 +1929,7 @@ static void update_dchubp_dpp( · 112 unmodified lines
1777	/gamut remap/	1929	/gamut remap/
1778	program_gamut_remap(pipe_ctx);	1930	program_gamut_remap(pipe_ctx);
1779		1931
1780	program_output_csc(dc,	1932	dc->hwss.program_output_csc(dc,
1781	pipe_ctx,	1933	pipe_ctx,
1782	pipe_ctx->stream->output_color_space,	1934	pipe_ctx->stream->output_color_space,
1783	pipe_ctx->stream->csc_color_matrix.matrix,	1935	pipe_ctx->stream->csc_color_matrix.matrix,
@@ -1810,9 +1962,9 @@ static void update_dchubp_dpp( · 26 unmodified lines
1810	hubp->funcs->set_blank(hubp, false);	1962	hubp->funcs->set_blank(hubp, false);
1811	}	1963	}
1812		1964
1813	static void dcn10_otg_blank(	1965	static void dcn10_blank_pixel_data(
1814	struct dc *dc,	1966	struct dc *dc,
1815	struct stream_resource stream_res,	1967	struct stream_resource *stream_res,
1816	struct dc_stream_state *stream,	1968	struct dc_stream_state *stream,
1817	bool blank)	1969	bool blank)
1818	{	1970	{
@@ -1823,21 +1975,21 @@ static void dcn10_otg_blank( · 4 unmodified lines
1823	color_space = stream->output_color_space;	1975	color_space = stream->output_color_space;
1824	color_space_to_black_color(dc, color_space, &black_color);	1976	color_space_to_black_color(dc, color_space, &black_color);
1825		1977
1826	if (stream_res.tg->funcs->set_blank_color)	1978	if (stream_res->tg->funcs->set_blank_color)
1827	stream_res.tg->funcs->set_blank_color(	1979	stream_res->tg->funcs->set_blank_color(
1828	stream_res.tg,	1980	stream_res->tg,
1829	&black_color);	1981	&black_color);
1830		1982
1831	if (!blank) {	1983	if (!blank) {
1832	if (stream_res.tg->funcs->set_blank)	1984	if (stream_res->tg->funcs->set_blank)
1833	stream_res.tg->funcs->set_blank(stream_res.tg, blank);	1985	stream_res->tg->funcs->set_blank(stream_res->tg, blank);
1834	if (stream_res.abm)	1986	if (stream_res->abm)
1835	stream_res.abm->funcs->set_abm_level(stream_res.abm, stream->abm_level);	1987	stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1836	} else if (blank) {	1988	} else if (blank) {
1837	if (stream_res.abm)	1989	if (stream_res->abm)
1838	stream_res.abm->funcs->set_abm_immediate_disable(stream_res.abm);	1990	stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
1839	if (stream_res.tg->funcs->set_blank)	1991	if (stream_res->tg->funcs->set_blank)
1840	stream_res.tg->funcs->set_blank(stream_res.tg, blank);	1992	stream_res->tg->funcs->set_blank(stream_res->tg, blank);
1841	}	1993	}
1842	}	1994	}
1843		1995
@@ -1876,7 +2028,7 @@ static void program_all_pipe_in_tree( · 32 unmodified lines
1876	pipe_ctx->stream_res.tg->funcs->program_global_sync(	2028	pipe_ctx->stream_res.tg->funcs->program_global_sync(
1877	pipe_ctx->stream_res.tg);	2029	pipe_ctx->stream_res.tg);
1878		2030
1879	dcn10_otg_blank(dc, pipe_ctx->stream_res,	2031	dc->hwss.blank_pixel_data(dc, &pipe_ctx->stream_res,
1880	pipe_ctx->stream, blank);	2032	pipe_ctx->stream, blank);
1881	}	2033	}
1882		2034
@@ -1983,9 +2135,9 @@ static void dcn10_apply_ctx_for_surface( · 100 unmodified lines
1983	bool removed_pipe[4] = { false };	2135	bool removed_pipe[4] = { false };
1984	unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;	2136	unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
1985	bool program_water_mark = false;	2137	bool program_water_mark = false;
1986	struct dc_context *ctx = dc->ctx;
1987	struct pipe_ctx *top_pipe_to_program =	2138	struct pipe_ctx *top_pipe_to_program =
1988	find_top_pipe_for_stream(dc, context, stream);	2139	find_top_pipe_for_stream(dc, context, stream);
		2140	DC_LOGGER_INIT(dc->ctx->logger);
1989		2141
1990	if (!top_pipe_to_program)	2142	if (!top_pipe_to_program)
1991	return;	2143	return;
@@ -1996,7 +2148,7 @@ static void dcn10_apply_ctx_for_surface( · 4 unmodified lines
1996		2148
1997	if (num_planes == 0) {	2149	if (num_planes == 0) {
1998	/* OTG blank before remove all front end */	2150	/* OTG blank before remove all front end */
1999	dcn10_otg_blank(dc, top_pipe_to_program->stream_res, top_pipe_to_program->stream, true);	2151	dc->hwss.blank_pixel_data(dc, &top_pipe_to_program->stream_res, top_pipe_to_program->stream, true);
2000	}	2152	}
2001		2153
2002	/* Disconnect unused mpcc */	2154	/* Disconnect unused mpcc */
@@ -2527,6 +2679,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { · 524 unmodified lines
2527	.update_pending_status = dcn10_update_pending_status,	2679	.update_pending_status = dcn10_update_pending_status,
2528	.set_input_transfer_func = dcn10_set_input_transfer_func,	2680	.set_input_transfer_func = dcn10_set_input_transfer_func,
2529	.set_output_transfer_func = dcn10_set_output_transfer_func,	2681	.set_output_transfer_func = dcn10_set_output_transfer_func,
		2682	.program_output_csc = dcn10_program_output_csc,
2530	.power_down = dce110_power_down,	2683	.power_down = dce110_power_down,
2531	.enable_accelerated_mode = dce110_enable_accelerated_mode,	2684	.enable_accelerated_mode = dce110_enable_accelerated_mode,
2532	.enable_timing_synchronization = dcn10_enable_timing_synchronization,	2685	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
@@ -2538,10 +2691,11 @@ static const struct hw_sequencer_funcs dcn10_funcs = { · 5 unmodified lines
2538	.blank_stream = dce110_blank_stream,	2691	.blank_stream = dce110_blank_stream,
2539	.enable_display_power_gating = dcn10_dummy_display_power_gating,	2692	.enable_display_power_gating = dcn10_dummy_display_power_gating,
2540	.disable_plane = dcn10_disable_plane,	2693	.disable_plane = dcn10_disable_plane,
		2694	.blank_pixel_data = dcn10_blank_pixel_data,
2541	.pipe_control_lock = dcn10_pipe_control_lock,	2695	.pipe_control_lock = dcn10_pipe_control_lock,
2542	.set_bandwidth = dcn10_set_bandwidth,	2696	.set_bandwidth = dcn10_set_bandwidth,
2543	.reset_hw_ctx_wrap = reset_hw_ctx_wrap,	2697	.reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2544	.prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,	2698	.enable_stream_timing = dcn10_enable_stream_timing,
2545	.set_drr = set_drr,	2699	.set_drr = set_drr,
2546	.get_position = get_position,	2700	.get_position = get_position,
2547	.set_static_screen_control = set_static_screen_control,	2701	.set_static_screen_control = set_static_screen_control,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c+22−2

 	int mpcc_id)
 {
 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+	struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
 	REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
 			MPCC_ALPHA_BLND_MODE,		blnd_cfg->alpha_mode,
 			MPCC_GLOBAL_GAIN,		blnd_cfg->global_gain);
 	mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
+	mpcc->blnd_cfg = *blnd_cfg;
 }
 void mpc1_update_stereo_mix(
 	}
 	/* update the blending configuration */
-	new_mpcc->blnd_cfg = *blnd_cfg;
+	mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
-	mpc->funcs->update_blending(mpc, &new_mpcc->blnd_cfg, mpcc_id);
 	/* update the stereo mix settings, if provided */
 	if (sm_cfg != NULL) {
 	}
 }
+void mpc1_read_mpcc_state(
+		struct mpc *mpc,
+		int mpcc_inst,
+		struct mpcc_state *s)
+{
+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+	REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
+	REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
+	REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
+	REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
+			MPCC_ALPHA_BLND_MODE, &s->alpha_mode,
+			MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,
+			MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only);
+	REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
+			MPCC_BUSY, &s->busy);
+}
 const struct mpc_funcs dcn10_mpc_funcs = {
+	.read_mpcc_state = mpc1_read_mpcc_state,
 	.insert_plane = mpc1_insert_plane,
 	.remove_mpcc = mpc1_remove_mpcc,
 	.mpc_init = mpc1_mpc_init,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h+5−0

@@ -183,4 +183,9 @@ struct mpcc *mpc1_get_mpcc_for_dpp( · 182 unmodified lines
183	struct mpc_tree *tree,	183	struct mpc_tree *tree,
184	int dpp_id);	184	int dpp_id);
185		185
		186	void mpc1_read_mpcc_state(
		187	struct mpc *mpc,
		188	int mpcc_inst,
		189	struct mpcc_state *s);
		190
186	#endif	191	#endif

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c+88−6

@@ -93,6 +93,81 @@ static void optc1_disable_stereo(struct timing_generator *optc) · 92 unmodified lines
93	OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);	93	OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
94	}	94	}
95		95
		96	static uint32_t get_start_vline(struct timing_generator optc, const struct dc_crtc_timing dc_crtc_timing)
		97	{
		98	struct dc_crtc_timing patched_crtc_timing;
		99	int vesa_sync_start;
		100	int asic_blank_end;
		101	int interlace_factor;
		102	int vertical_line_start;
		103
		104	patched_crtc_timing = *dc_crtc_timing;
		105	optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);
		106
		107	vesa_sync_start = patched_crtc_timing.h_addressable +
		108	patched_crtc_timing.h_border_right +
		109	patched_crtc_timing.h_front_porch;
		110
		111	asic_blank_end = patched_crtc_timing.h_total -
		112	vesa_sync_start -
		113	patched_crtc_timing.h_border_left;
		114
		115	interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
		116
		117	vesa_sync_start = patched_crtc_timing.v_addressable +
		118	patched_crtc_timing.v_border_bottom +
		119	patched_crtc_timing.v_front_porch;
		120
		121	asic_blank_end = (patched_crtc_timing.v_total -
		122	vesa_sync_start -
		123	patched_crtc_timing.v_border_top)
		124	* interlace_factor;
		125
		126	vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
		127	if (vertical_line_start < 0) {
		128	ASSERT(0);
		129	vertical_line_start = 0;
		130	}
		131
		132	return vertical_line_start;
		133	}
		134
		135	void optc1_program_vline_interrupt(
		136	struct timing_generator *optc,
		137	const struct dc_crtc_timing *dc_crtc_timing,
		138	unsigned long long vsync_delta)
		139	{
		140
		141	struct optc *optc1 = DCN10TG_FROM_TG(optc);
		142
		143	unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 9999), 10000);
		144	unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_khz + 99), 100);
		145	uint32_t req_delta_lines = (uint32_t) div64_u64(
		146	(req_delta_tens_of_usec * pix_clk_hundreds_khz + dc_crtc_timing->h_total - 1),
		147	dc_crtc_timing->h_total);
		148
		149	uint32_t vsync_line = get_start_vline(optc, dc_crtc_timing);
		150	uint32_t start_line = 0;
		151	uint32_t endLine = 0;
		152
		153	if (req_delta_lines != 0)
		154	req_delta_lines--;
		155
		156	if (req_delta_lines > vsync_line)
		157	start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) - 1;
		158	else
		159	start_line = vsync_line - req_delta_lines;
		160
		161	endLine = start_line + 2;
		162
		163	if (endLine >= dc_crtc_timing->v_total)
		164	endLine = 2;
		165
		166	REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
		167	OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
		168	OTG_VERTICAL_INTERRUPT0_LINE_END, endLine);
		169	}
		170
96	/**	171	/**
97	* program_timing_generator used by mode timing set	172	* program_timing_generator used by mode timing set
98	* Program CRTC Timing Registers - OTG_H_, OTG_V_, Pixel repetition.	173	* Program CRTC Timing Registers - OTG_H_, OTG_V_, Pixel repetition.
@@ -780,17 +855,17 @@ void optc1_set_drr( · 681 unmodified lines
780	OTG_SET_V_TOTAL_MIN_MASK_EN, 0,	855	OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
781	OTG_SET_V_TOTAL_MIN_MASK, 0);	856	OTG_SET_V_TOTAL_MIN_MASK, 0);
782	} else {	857	} else {
783	REG_SET(OTG_V_TOTAL_MIN, 0,
784	OTG_V_TOTAL_MIN, 0);
785
786	REG_SET(OTG_V_TOTAL_MAX, 0,
787	OTG_V_TOTAL_MAX, 0);
788
789	REG_UPDATE_4(OTG_V_TOTAL_CONTROL,	858	REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
790	OTG_SET_V_TOTAL_MIN_MASK, 0,	859	OTG_SET_V_TOTAL_MIN_MASK, 0,
791	OTG_V_TOTAL_MIN_SEL, 0,	860	OTG_V_TOTAL_MIN_SEL, 0,
792	OTG_V_TOTAL_MAX_SEL, 0,	861	OTG_V_TOTAL_MAX_SEL, 0,
793	OTG_FORCE_LOCK_ON_EVENT, 0);	862	OTG_FORCE_LOCK_ON_EVENT, 0);
		863
		864	REG_SET(OTG_V_TOTAL_MIN, 0,
		865	OTG_V_TOTAL_MIN, 0);
		866
		867	REG_SET(OTG_V_TOTAL_MAX, 0,
		868	OTG_V_TOTAL_MAX, 0);
794	}	869	}
795	}	870	}
796		871
@@ -1154,6 +1229,12 @@ void optc1_read_otg_state(struct optc *optc1, · 357 unmodified lines
1154	REG_GET(OTG_V_TOTAL_MIN,	1229	REG_GET(OTG_V_TOTAL_MIN,
1155	OTG_V_TOTAL_MIN, &s->v_total_min);	1230	OTG_V_TOTAL_MIN, &s->v_total_min);
1156		1231
		1232	REG_GET(OTG_V_TOTAL_CONTROL,
		1233	OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
		1234
		1235	REG_GET(OTG_V_TOTAL_CONTROL,
		1236	OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
		1237
1157	REG_GET_2(OTG_V_SYNC_A,	1238	REG_GET_2(OTG_V_SYNC_A,
1158	OTG_V_SYNC_A_START, &s->v_sync_a_start,	1239	OTG_V_SYNC_A_START, &s->v_sync_a_start,
1159	OTG_V_SYNC_A_END, &s->v_sync_a_end);	1240	OTG_V_SYNC_A_END, &s->v_sync_a_end);
@@ -1215,6 +1296,7 @@ static bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) · 55 unmodified lines
1215	static const struct timing_generator_funcs dcn10_tg_funcs = {	1296	static const struct timing_generator_funcs dcn10_tg_funcs = {
1216	.validate_timing = optc1_validate_timing,	1297	.validate_timing = optc1_validate_timing,
1217	.program_timing = optc1_program_timing,	1298	.program_timing = optc1_program_timing,
		1299	.program_vline_interrupt = optc1_program_vline_interrupt,
1218	.program_global_sync = optc1_program_global_sync,	1300	.program_global_sync = optc1_program_global_sync,
1219	.enable_crtc = optc1_enable_crtc,	1301	.enable_crtc = optc1_enable_crtc,
1220	.disable_crtc = optc1_disable_crtc,	1302	.disable_crtc = optc1_disable_crtc,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h+16−0

 	SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
 	SRI(OTG_BLACK_COLOR, OTG, inst),\
 	SRI(OTG_CLOCK_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
 	SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
 	SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
 	SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
 	uint32_t OTG_TEST_PATTERN_CONTROL;
 	uint32_t OTG_TEST_PATTERN_COLOR;
 	uint32_t OTG_CLOCK_CONTROL;
+	uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL;
+	uint32_t OTG_VERTICAL_INTERRUPT0_POSITION;
 	uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;
 	uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;
 	uint32_t OPTC_INPUT_CLOCK_CONTROL;
 	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
 	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
 	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
 	SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
 	SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
 	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
 	type OTG_CLOCK_EN;\
 	type OTG_CLOCK_ON;\
 	type OTG_CLOCK_GATE_DIS;\
+	type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\
+	type OTG_VERTICAL_INTERRUPT0_LINE_START;\
+	type OTG_VERTICAL_INTERRUPT0_LINE_END;\
 	type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\
 	type OTG_VERTICAL_INTERRUPT2_LINE_START;\
 	type OPTC_INPUT_CLK_EN;\
 	uint32_t v_total;
 	uint32_t v_total_max;
 	uint32_t v_total_min;
+	uint32_t v_total_min_sel;
+	uint32_t v_total_max_sel;
 	uint32_t v_sync_a_start;
 	uint32_t v_sync_a_end;
 	uint32_t h_blank_start;
 	const struct dc_crtc_timing *dc_crtc_timing,
 	bool use_vbios);
+void optc1_program_vline_interrupt(struct timing_generator *optc,
+		const struct dc_crtc_timing *dc_crtc_timing,
+		unsigned long long vsync_delta);
 void optc1_program_global_sync(
 		struct timing_generator *optc);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c+21−282

@@ -39,7 +39,7 @@ · 38 unmodified lines
39	#include "dce110/dce110_hw_sequencer.h"	39	#include "dce110/dce110_hw_sequencer.h"
40	#include "dcn10/dcn10_opp.h"	40	#include "dcn10/dcn10_opp.h"
41	#include "dce/dce_link_encoder.h"	41	#include "dce/dce_link_encoder.h"
42	#include "dce/dce_stream_encoder.h"	42	#include "dcn10/dcn10_stream_encoder.h"
43	#include "dce/dce_clocks.h"	43	#include "dce/dce_clocks.h"
44	#include "dce/dce_clock_source.h"	44	#include "dce/dce_clock_source.h"
45	#include "dce/dce_audio.h"	45	#include "dce/dce_audio.h"
@@ -166,36 +166,22 @@ static const struct dce_abm_mask abm_mask = { · 120 unmodified lines
166		166
167	#define stream_enc_regs(id)\	167	#define stream_enc_regs(id)\
168	[id] = {\	168	[id] = {\
169	SE_DCN_REG_LIST(id),\	169	SE_DCN_REG_LIST(id)\
170	.TMDS_CNTL = 0,\
171	.AFMT_AVI_INFO0 = 0,\
172	.AFMT_AVI_INFO1 = 0,\
173	.AFMT_AVI_INFO2 = 0,\
174	.AFMT_AVI_INFO3 = 0,\
175	}	170	}
176		171
177	static const struct dce110_stream_enc_registers stream_enc_regs[] = {	172	static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
178	stream_enc_regs(0),	173	stream_enc_regs(0),
179	stream_enc_regs(1),	174	stream_enc_regs(1),
180	stream_enc_regs(2),	175	stream_enc_regs(2),
181	stream_enc_regs(3),	176	stream_enc_regs(3),
182	};	177	};
183		178
184	static const struct dce_stream_encoder_shift se_shift = {	179	static const struct dcn10_stream_encoder_shift se_shift = {
185	SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)	180	SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
186	};	181	};
187		182
188	static const struct dce_stream_encoder_mask se_mask = {	183	static const struct dcn10_stream_encoder_mask se_mask = {
189	SE_COMMON_MASK_SH_LIST_DCN10(_MASK),	184	SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
190	.AFMT_GENERIC0_UPDATE = 0,
191	.AFMT_GENERIC2_UPDATE = 0,
192	.DP_DYN_RANGE = 0,
193	.DP_YCBCR_RANGE = 0,
194	.HDMI_AVI_INFO_SEND = 0,
195	.HDMI_AVI_INFO_CONT = 0,
196	.HDMI_AVI_INFO_LINE = 0,
197	.DP_SEC_AVI_ENABLE = 0,
198	.AFMT_AVI_INFO_VERSION = 0
199	};	185	};
200		186
201	#define audio_regs(id)\	187	#define audio_regs(id)\
@@ -320,11 +306,14 @@ static const struct dcn_dpp_registers tf_regs[] = { · 118 unmodified lines
320	};	306	};
321		307
322	static const struct dcn_dpp_shift tf_shift = {	308	static const struct dcn_dpp_shift tf_shift = {
323	TF_REG_LIST_SH_MASK_DCN10(__SHIFT)	309	TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
		310	TF_DEBUG_REG_LIST_SH_DCN10
		311
324	};	312	};
325		313
326	static const struct dcn_dpp_mask tf_mask = {	314	static const struct dcn_dpp_mask tf_mask = {
327	TF_REG_LIST_SH_MASK_DCN10(_MASK),	315	TF_REG_LIST_SH_MASK_DCN10(_MASK),
		316	TF_DEBUG_REG_LIST_MASK_DCN10
328	};	317	};
329		318
330	static const struct dcn_mpc_registers mpc_regs = {	319	static const struct dcn_mpc_registers mpc_regs = {
@@ -650,16 +639,16 @@ static struct stream_encoder *dcn10_stream_encoder_create( · 319 unmodified lines
650	enum engine_id eng_id,	639	enum engine_id eng_id,
651	struct dc_context *ctx)	640	struct dc_context *ctx)
652	{	641	{
653	struct dce110_stream_encoder *enc110 =	642	struct dcn10_stream_encoder *enc1 =
654	kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);	643	kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
655		644
656	if (!enc110)	645	if (!enc1)
657	return NULL;	646	return NULL;
658		647
659	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,	648	dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
660	&stream_enc_regs[eng_id],	649	&stream_enc_regs[eng_id],
661	&se_shift, &se_mask);	650	&se_shift, &se_mask);
662	return &enc110->base;	651	return &enc1->base;
663	}	652	}
664		653
665	static const struct dce_hwseq_registers hwseq_reg = {	654	static const struct dce_hwseq_registers hwseq_reg = {
@@ -918,36 +907,6 @@ enum dc_status dcn10_add_stream_to_ctx( · 252 unmodified lines
918	return result;	907	return result;
919	}	908	}
920		909
921	enum dc_status dcn10_validate_guaranteed(
922	struct dc *dc,
923	struct dc_stream_state *dc_stream,
924	struct dc_state *context)
925	{
926	enum dc_status result = DC_ERROR_UNEXPECTED;
927
928	context->streams[0] = dc_stream;
929	dc_stream_retain(context->streams[0]);
930	context->stream_count++;
931
932	result = resource_map_pool_resources(dc, context, dc_stream);
933
934	if (result == DC_OK)
935	result = resource_map_phy_clock_resources(dc, context, dc_stream);
936
937	if (result == DC_OK)
938	result = build_mapped_resource(dc, context, dc_stream);
939
940	if (result == DC_OK) {
941	validate_guaranteed_copy_streams(
942	context, dc->caps.max_streams);
943	result = resource_build_scaling_params_for_context(dc, context);
944	}
945	if (result == DC_OK && !dcn_validate_bandwidth(dc, context))
946	return DC_FAIL_BANDWIDTH_VALIDATE;
947
948	return result;
949	}
950
951	static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(	910	static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
952	struct dc_state *context,	911	struct dc_state *context,
953	const struct resource_pool *pool,	912	const struct resource_pool *pool,
@@ -978,235 +937,16 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( · 24 unmodified lines
978	return idle_pipe;	937	return idle_pipe;
979	}	938	}
980		939
981	enum dcc_control {	940	static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
982	dcc_control__256_256_xxx,
983	dcc_control__128_128_xxx,
984	dcc_control__256_64_64,
985	};
986
987	enum segment_order {
988	segment_order__na,
989	segment_order__contiguous,
990	segment_order__non_contiguous,
991	};
992
993	static bool dcc_support_pixel_format(
994	enum surface_pixel_format format,
995	unsigned int *bytes_per_element)
996	{
997	/* DML: get_bytes_per_element */
998	switch (format) {
999	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1000	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1001	*bytes_per_element = 2;
1002	return true;
1003	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1004	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1005	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1006	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1007	*bytes_per_element = 4;
1008	return true;
1009	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1010	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1011	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1012	*bytes_per_element = 8;
1013	return true;
1014	default:
1015	return false;
1016	}
1017	}
1018
1019	static bool dcc_support_swizzle(
1020	enum swizzle_mode_values swizzle,
1021	unsigned int bytes_per_element,
1022	enum segment_order *segment_order_horz,
1023	enum segment_order *segment_order_vert)
1024	{
1025	bool standard_swizzle = false;
1026	bool display_swizzle = false;
1027
1028	switch (swizzle) {
1029	case DC_SW_4KB_S:
1030	case DC_SW_64KB_S:
1031	case DC_SW_VAR_S:
1032	case DC_SW_4KB_S_X:
1033	case DC_SW_64KB_S_X:
1034	case DC_SW_VAR_S_X:
1035	standard_swizzle = true;
1036	break;
1037	case DC_SW_4KB_D:
1038	case DC_SW_64KB_D:
1039	case DC_SW_VAR_D:
1040	case DC_SW_4KB_D_X:
1041	case DC_SW_64KB_D_X:
1042	case DC_SW_VAR_D_X:
1043	display_swizzle = true;
1044	break;
1045	default:
1046	break;
1047	}
1048
1049	if (bytes_per_element == 1 && standard_swizzle) {
1050	*segment_order_horz = segment_order__contiguous;
1051	*segment_order_vert = segment_order__na;
1052	return true;
1053	}
1054	if (bytes_per_element == 2 && standard_swizzle) {
1055	*segment_order_horz = segment_order__non_contiguous;
1056	*segment_order_vert = segment_order__contiguous;
1057	return true;
1058	}
1059	if (bytes_per_element == 4 && standard_swizzle) {
1060	*segment_order_horz = segment_order__non_contiguous;
1061	*segment_order_vert = segment_order__contiguous;
1062	return true;
1063	}
1064	if (bytes_per_element == 8 && standard_swizzle) {
1065	*segment_order_horz = segment_order__na;
1066	*segment_order_vert = segment_order__contiguous;
1067	return true;
1068	}
1069	if (bytes_per_element == 8 && display_swizzle) {
1070	*segment_order_horz = segment_order__contiguous;
1071	*segment_order_vert = segment_order__non_contiguous;
1072	return true;
1073	}
1074
1075	return false;
1076	}
1077
1078	static void get_blk256_size(unsigned int blk256_width, unsigned int blk256_height,
1079	unsigned int bytes_per_element)
1080	{
1081	/* copied from DML. might want to refactor DML to leverage from DML */
1082	/* DML : get_blk256_size */
1083	if (bytes_per_element == 1) {
1084	*blk256_width = 16;
1085	*blk256_height = 16;
1086	} else if (bytes_per_element == 2) {
1087	*blk256_width = 16;
1088	*blk256_height = 8;
1089	} else if (bytes_per_element == 4) {
1090	*blk256_width = 8;
1091	*blk256_height = 8;
1092	} else if (bytes_per_element == 8) {
1093	*blk256_width = 8;
1094	*blk256_height = 4;
1095	}
1096	}
1097
1098	static void det_request_size(
1099	unsigned int height,
1100	unsigned int width,
1101	unsigned int bpe,
1102	bool *req128_horz_wc,
1103	bool *req128_vert_wc)
1104	{
1105	unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */
1106
1107	unsigned int blk256_height = 0;
1108	unsigned int blk256_width = 0;
1109	unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
1110
1111	get_blk256_size(&blk256_width, &blk256_height, bpe);
1112
1113	swath_bytes_horz_wc = height * blk256_height * bpe;
1114	swath_bytes_vert_wc = width * blk256_width * bpe;
1115
1116	req128_horz_wc = (2 swath_bytes_horz_wc <= detile_buf_size) ?
1117	false : /* full 256B request */
1118	true; /* half 128b request */
1119
1120	req128_vert_wc = (2 swath_bytes_vert_wc <= detile_buf_size) ?
1121	false : /* full 256B request */
1122	true; /* half 128b request */
1123	}
1124
1125	static bool get_dcc_compression_cap(const struct dc *dc,
1126	const struct dc_dcc_surface_param *input,	941	const struct dc_dcc_surface_param *input,
1127	struct dc_surface_dcc_cap *output)	942	struct dc_surface_dcc_cap *output)
1128	{	943	{
1129	/* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */	944	return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1130	enum dcc_control dcc_control;	945	dc->res_pool->hubbub,
1131	unsigned int bpe;	946	input,
1132	enum segment_order segment_order_horz, segment_order_vert;	947	output);
1133	bool req128_horz_wc, req128_vert_wc;
1134
1135	memset(output, 0, sizeof(*output));
1136
1137	if (dc->debug.disable_dcc == DCC_DISABLE)
1138	return false;
1139
1140	if (!dcc_support_pixel_format(input->format,
1141	&bpe))
1142	return false;
1143
1144	if (!dcc_support_swizzle(input->swizzle_mode, bpe,
1145	&segment_order_horz, &segment_order_vert))
1146	return false;
1147
1148	det_request_size(input->surface_size.height, input->surface_size.width,
1149	bpe, &req128_horz_wc, &req128_vert_wc);
1150
1151	if (!req128_horz_wc && !req128_vert_wc) {
1152	dcc_control = dcc_control__256_256_xxx;
1153	} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
1154	if (!req128_horz_wc)
1155	dcc_control = dcc_control__256_256_xxx;
1156	else if (segment_order_horz == segment_order__contiguous)
1157	dcc_control = dcc_control__128_128_xxx;
1158	else
1159	dcc_control = dcc_control__256_64_64;
1160	} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
1161	if (!req128_vert_wc)
1162	dcc_control = dcc_control__256_256_xxx;
1163	else if (segment_order_vert == segment_order__contiguous)
1164	dcc_control = dcc_control__128_128_xxx;
1165	else
1166	dcc_control = dcc_control__256_64_64;
1167	} else {
1168	if ((req128_horz_wc &&
1169	segment_order_horz == segment_order__non_contiguous) \|\|
1170	(req128_vert_wc &&
1171	segment_order_vert == segment_order__non_contiguous))
1172	/* access_dir not known, must use most constraining */
1173	dcc_control = dcc_control__256_64_64;
1174	else
1175	/* reg128 is true for either horz and vert
1176	* but segment_order is contiguous
1177	*/
1178	dcc_control = dcc_control__128_128_xxx;
1179	}
1180
1181	if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
1182	dcc_control != dcc_control__256_256_xxx)
1183	return false;
1184
1185	switch (dcc_control) {
1186	case dcc_control__256_256_xxx:
1187	output->grph.rgb.max_uncompressed_blk_size = 256;
1188	output->grph.rgb.max_compressed_blk_size = 256;
1189	output->grph.rgb.independent_64b_blks = false;
1190	break;
1191	case dcc_control__128_128_xxx:
1192	output->grph.rgb.max_uncompressed_blk_size = 128;
1193	output->grph.rgb.max_compressed_blk_size = 128;
1194	output->grph.rgb.independent_64b_blks = false;
1195	break;
1196	case dcc_control__256_64_64:
1197	output->grph.rgb.max_uncompressed_blk_size = 256;
1198	output->grph.rgb.max_compressed_blk_size = 64;
1199	output->grph.rgb.independent_64b_blks = true;
1200	break;
1201	}
1202
1203	output->capable = true;
1204	output->const_color_support = false;
1205
1206	return true;
1207	}	948	}
1208		949
1209
1210	static void dcn10_destroy_resource_pool(struct resource_pool **pool)	950	static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1211	{	951	{
1212	struct dcn10_resource_pool dcn10_pool = TO_DCN10_RES_POOL(pool);	952	struct dcn10_resource_pool dcn10_pool = TO_DCN10_RES_POOL(pool);
@@ -1227,13 +967,12 @@ static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_st · 14 unmodified lines
1227	}	967	}
1228		968
1229	static struct dc_cap_funcs cap_funcs = {	969	static struct dc_cap_funcs cap_funcs = {
1230	.get_dcc_compression_cap = get_dcc_compression_cap	970	.get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1231	};	971	};
1232		972
1233	static struct resource_funcs dcn10_res_pool_funcs = {	973	static struct resource_funcs dcn10_res_pool_funcs = {
1234	.destroy = dcn10_destroy_resource_pool,	974	.destroy = dcn10_destroy_resource_pool,
1235	.link_enc_create = dcn10_link_encoder_create,	975	.link_enc_create = dcn10_link_encoder_create,
1236	.validate_guaranteed = dcn10_validate_guaranteed,
1237	.validate_bandwidth = dcn_validate_bandwidth,	976	.validate_bandwidth = dcn_validate_bandwidth,
1238	.acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,	977	.acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
1239	.validate_plane = dcn10_validate_plane,	978	.validate_plane = dcn10_validate_plane,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c+1490−0

@@ -0,0 +1,1490 @@
	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26
	27	#include "dc_bios_types.h"
	28	#include "dcn10_stream_encoder.h"
	29	#include "reg_helper.h"
	30	#include "hw_shared.h"
	31
	32	#define DC_LOGGER \
	33	enc1->base.ctx->logger
	34
	35
	36	#define REG(reg)\
	37	(enc1->regs->reg)
	38
	39	#undef FN
	40	#define FN(reg_name, field_name) \
	41	enc1->se_shift->field_name, enc1->se_mask->field_name
	42
	43	#define VBI_LINE_0 0
	44	#define DP_BLANK_MAX_RETRY 20
	45	#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
	46
	47
	48	enum {
	49	DP_MST_UPDATE_MAX_RETRY = 50
	50	};
	51
	52	#define CTX \
	53	enc1->base.ctx
	54
	55	void enc1_update_generic_info_packet(
	56	struct dcn10_stream_encoder *enc1,
	57	uint32_t packet_index,
	58	const struct dc_info_packet *info_packet)
	59	{
	60	uint32_t regval;
	61	/* TODOFPGA Figure out a proper number for max_retries polling for lock
	62	* use 50 for now.
	63	*/
	64	uint32_t max_retries = 50;
	65
	66	/we need turn on clock before programming AFMT block/
	67	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
	68
	69	if (packet_index >= 8)
	70	ASSERT(0);
	71
	72	/* poll dig_update_lock is not locked -> asic internal signal
	73	* assume otg master lock will unlock it
	74	*/
	75	/* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
	76	0, 10, max_retries);*/
	77
	78	/* check if HW reading GSP memory */
	79	REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
	80	0, 10, max_retries);
	81
	82	/* HW does is not reading GSP memory not reading too long ->
	83	* something wrong. clear GPS memory access and notify?
	84	* hw SW is writing to GSP memory
	85	*/
	86	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
	87
	88	/* choose which generic packet to use */
	89	regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
	90	REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
	91	AFMT_GENERIC_INDEX, packet_index);
	92
	93	/* write generic packet header
	94	* (4th byte is for GENERIC0 only)
	95	*/
	96	REG_SET_4(AFMT_GENERIC_HDR, 0,
	97	AFMT_GENERIC_HB0, info_packet->hb0,
	98	AFMT_GENERIC_HB1, info_packet->hb1,
	99	AFMT_GENERIC_HB2, info_packet->hb2,
	100	AFMT_GENERIC_HB3, info_packet->hb3);
	101
	102	/* write generic packet contents
	103	* (we never use last 4 bytes)
	104	* there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
	105	*/
	106	{
	107	const uint32_t *content =
	108	(const uint32_t *) &info_packet->sb[0];
	109
	110	REG_WRITE(AFMT_GENERIC_0, *content++);
	111	REG_WRITE(AFMT_GENERIC_1, *content++);
	112	REG_WRITE(AFMT_GENERIC_2, *content++);
	113	REG_WRITE(AFMT_GENERIC_3, *content++);
	114	REG_WRITE(AFMT_GENERIC_4, *content++);
	115	REG_WRITE(AFMT_GENERIC_5, *content++);
	116	REG_WRITE(AFMT_GENERIC_6, *content++);
	117	REG_WRITE(AFMT_GENERIC_7, *content);
	118	}
	119
	120	switch (packet_index) {
	121	case 0:
	122	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
	123	AFMT_GENERIC0_FRAME_UPDATE, 1);
	124	break;
	125	case 1:
	126	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
	127	AFMT_GENERIC1_FRAME_UPDATE, 1);
	128	break;
	129	case 2:
	130	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
	131	AFMT_GENERIC2_FRAME_UPDATE, 1);
	132	break;
	133	case 3:
	134	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
	135	AFMT_GENERIC3_FRAME_UPDATE, 1);
	136	break;
	137	case 4:
	138	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
	139	AFMT_GENERIC4_FRAME_UPDATE, 1);
	140	break;
	141	case 5:
	142	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
	143	AFMT_GENERIC5_FRAME_UPDATE, 1);
	144	break;
	145	case 6:
	146	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
	147	AFMT_GENERIC6_FRAME_UPDATE, 1);
	148	break;
	149	case 7:
	150	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
	151	AFMT_GENERIC7_FRAME_UPDATE, 1);
	152	break;
	153	default:
	154	break;
	155	}
	156	}
	157
	158	static void enc1_update_hdmi_info_packet(
	159	struct dcn10_stream_encoder *enc1,
	160	uint32_t packet_index,
	161	const struct dc_info_packet *info_packet)
	162	{
	163	uint32_t cont, send, line;
	164
	165	if (info_packet->valid) {
	166	enc1_update_generic_info_packet(
	167	enc1,
	168	packet_index,
	169	info_packet);
	170
	171	/* enable transmission of packet(s) -
	172	* packet transmission begins on the next frame
	173	*/
	174	cont = 1;
	175	/* send packet(s) every frame */
	176	send = 1;
	177	/* select line number to send packets on */
	178	line = 2;
	179	} else {
	180	cont = 0;
	181	send = 0;
	182	line = 0;
	183	}
	184
	185	/* choose which generic packet control to use */
	186	switch (packet_index) {
	187	case 0:
	188	REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
	189	HDMI_GENERIC0_CONT, cont,
	190	HDMI_GENERIC0_SEND, send,
	191	HDMI_GENERIC0_LINE, line);
	192	break;
	193	case 1:
	194	REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
	195	HDMI_GENERIC1_CONT, cont,
	196	HDMI_GENERIC1_SEND, send,
	197	HDMI_GENERIC1_LINE, line);
	198	break;
	199	case 2:
	200	REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
	201	HDMI_GENERIC0_CONT, cont,
	202	HDMI_GENERIC0_SEND, send,
	203	HDMI_GENERIC0_LINE, line);
	204	break;
	205	case 3:
	206	REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
	207	HDMI_GENERIC1_CONT, cont,
	208	HDMI_GENERIC1_SEND, send,
	209	HDMI_GENERIC1_LINE, line);
	210	break;
	211	case 4:
	212	REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
	213	HDMI_GENERIC0_CONT, cont,
	214	HDMI_GENERIC0_SEND, send,
	215	HDMI_GENERIC0_LINE, line);
	216	break;
	217	case 5:
	218	REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
	219	HDMI_GENERIC1_CONT, cont,
	220	HDMI_GENERIC1_SEND, send,
	221	HDMI_GENERIC1_LINE, line);
	222	break;
	223	case 6:
	224	REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
	225	HDMI_GENERIC0_CONT, cont,
	226	HDMI_GENERIC0_SEND, send,
	227	HDMI_GENERIC0_LINE, line);
	228	break;
	229	case 7:
	230	REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
	231	HDMI_GENERIC1_CONT, cont,
	232	HDMI_GENERIC1_SEND, send,
	233	HDMI_GENERIC1_LINE, line);
	234	break;
	235	default:
	236	/* invalid HW packet index */
	237	DC_LOG_WARNING(
	238	"Invalid HW packet index: %s()\n",
	239	__func__);
	240	return;
	241	}
	242	}
	243
	244	/* setup stream encoder in dp mode */
	245	void enc1_stream_encoder_dp_set_stream_attribute(
	246	struct stream_encoder *enc,
	247	struct dc_crtc_timing *crtc_timing,
	248	enum dc_color_space output_color_space)
	249	{
	250	uint32_t h_active_start;
	251	uint32_t v_active_start;
	252	uint32_t misc0 = 0;
	253	uint32_t misc1 = 0;
	254	uint32_t h_blank;
	255	uint32_t h_back_porch;
	256	uint8_t synchronous_clock = 0; /* asynchronous mode */
	257	uint8_t colorimetry_bpc;
	258	uint8_t dynamic_range_rgb = 0; /full range/
	259	uint8_t dynamic_range_ycbcr = 1; /bt709/
	260
	261	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	262
	263	REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
	264
	265	/* set pixel encoding */
	266	switch (crtc_timing->pixel_encoding) {
	267	case PIXEL_ENCODING_YCBCR422:
	268	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
	269	DP_PIXEL_ENCODING_TYPE_YCBCR422);
	270	break;
	271	case PIXEL_ENCODING_YCBCR444:
	272	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
	273	DP_PIXEL_ENCODING_TYPE_YCBCR444);
	274
	275	if (crtc_timing->flags.Y_ONLY)
	276	if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
	277	/* HW testing only, no use case yet.
	278	* Color depth of Y-only could be
	279	* 8, 10, 12, 16 bits
	280	*/
	281	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
	282	DP_PIXEL_ENCODING_TYPE_Y_ONLY);
	283	/* Note: DP_MSA_MISC1 bit 7 is the indicator
	284	* of Y-only mode.
	285	* This bit is set in HW if register
	286	* DP_PIXEL_ENCODING is programmed to 0x4
	287	*/
	288	break;
	289	case PIXEL_ENCODING_YCBCR420:
	290	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
	291	DP_PIXEL_ENCODING_TYPE_YCBCR420);
	292	REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
	293	break;
	294	default:
	295	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
	296	DP_PIXEL_ENCODING_TYPE_RGB444);
	297	break;
	298	}
	299
	300	misc1 = REG_READ(DP_MSA_MISC);
	301
	302	/* set color depth */
	303
	304	switch (crtc_timing->display_color_depth) {
	305	case COLOR_DEPTH_666:
	306	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
	307	0);
	308	break;
	309	case COLOR_DEPTH_888:
	310	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
	311	DP_COMPONENT_PIXEL_DEPTH_8BPC);
	312	break;
	313	case COLOR_DEPTH_101010:
	314	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
	315	DP_COMPONENT_PIXEL_DEPTH_10BPC);
	316
	317	break;
	318	case COLOR_DEPTH_121212:
	319	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
	320	DP_COMPONENT_PIXEL_DEPTH_12BPC);
	321	break;
	322	default:
	323	REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
	324	DP_COMPONENT_PIXEL_DEPTH_6BPC);
	325	break;
	326	}
	327
	328	/* set dynamic range and YCbCr range */
	329
	330	switch (crtc_timing->display_color_depth) {
	331	case COLOR_DEPTH_666:
	332	colorimetry_bpc = 0;
	333	break;
	334	case COLOR_DEPTH_888:
	335	colorimetry_bpc = 1;
	336	break;
	337	case COLOR_DEPTH_101010:
	338	colorimetry_bpc = 2;
	339	break;
	340	case COLOR_DEPTH_121212:
	341	colorimetry_bpc = 3;
	342	break;
	343	default:
	344	colorimetry_bpc = 0;
	345	break;
	346	}
	347
	348	misc0 = misc0 \| synchronous_clock;
	349	misc0 = colorimetry_bpc << 5;
	350
	351	switch (output_color_space) {
	352	case COLOR_SPACE_SRGB:
	353	misc0 = misc0 \| 0x0;
	354	misc1 = misc1 & ~0x80; /* bit7 = 0*/
	355	dynamic_range_rgb = 0; /full range/
	356	break;
	357	case COLOR_SPACE_SRGB_LIMITED:
	358	misc0 = misc0 \| 0x8; /* bit3=1 */
	359	misc1 = misc1 & ~0x80; /* bit7 = 0*/
	360	dynamic_range_rgb = 1; /limited range/
	361	break;
	362	case COLOR_SPACE_YCBCR601:
	363	case COLOR_SPACE_YCBCR601_LIMITED:
	364	misc0 = misc0 \| 0x8; /* bit3=1, bit4=0 */
	365	misc1 = misc1 & ~0x80; /* bit7 = 0*/
	366	dynamic_range_ycbcr = 0; /bt601/
	367	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
	368	misc0 = misc0 \| 0x2; /* bit2=0, bit1=1 */
	369	else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
	370	misc0 = misc0 \| 0x4; /* bit2=1, bit1=0 */
	371	break;
	372	case COLOR_SPACE_YCBCR709:
	373	case COLOR_SPACE_YCBCR709_LIMITED:
	374	misc0 = misc0 \| 0x18; /* bit3=1, bit4=1 */
	375	misc1 = misc1 & ~0x80; /* bit7 = 0*/
	376	dynamic_range_ycbcr = 1; /bt709/
	377	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
	378	misc0 = misc0 \| 0x2; /* bit2=0, bit1=1 */
	379	else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
	380	misc0 = misc0 \| 0x4; /* bit2=1, bit1=0 */
	381	break;
	382	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
	383	dynamic_range_rgb = 1; /limited range/
	384	break;
	385	case COLOR_SPACE_2020_RGB_FULLRANGE:
	386	case COLOR_SPACE_2020_YCBCR:
	387	case COLOR_SPACE_XR_RGB:
	388	case COLOR_SPACE_MSREF_SCRGB:
	389	case COLOR_SPACE_ADOBERGB:
	390	case COLOR_SPACE_DCIP3:
	391	case COLOR_SPACE_XV_YCC_709:
	392	case COLOR_SPACE_XV_YCC_601:
	393	case COLOR_SPACE_DISPLAYNATIVE:
	394	case COLOR_SPACE_DOLBYVISION:
	395	case COLOR_SPACE_APPCTRL:
	396	case COLOR_SPACE_CUSTOMPOINTS:
	397	case COLOR_SPACE_UNKNOWN:
	398	/* do nothing */
	399	break;
	400	}
	401
	402	REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
	403	REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
	404
	405	/* dcn new register
	406	* dc_crtc_timing is vesa dmt struct. data from edid
	407	*/
	408	REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
	409	DP_MSA_HTOTAL, crtc_timing->h_total,
	410	DP_MSA_VTOTAL, crtc_timing->v_total);
	411
	412	/* calculate from vesa timing parameters
	413	* h_active_start related to leading edge of sync
	414	*/
	415
	416	h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
	417	crtc_timing->h_addressable - crtc_timing->h_border_right;
	418
	419	h_back_porch = h_blank - crtc_timing->h_front_porch -
	420	crtc_timing->h_sync_width;
	421
	422	/* start at beginning of left border */
	423	h_active_start = crtc_timing->h_sync_width + h_back_porch;
	424
	425
	426	v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
	427	crtc_timing->v_addressable - crtc_timing->v_border_bottom -
	428	crtc_timing->v_front_porch;
	429
	430
	431	/* start at beginning of left border */
	432	REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
	433	DP_MSA_HSTART, h_active_start,
	434	DP_MSA_VSTART, v_active_start);
	435
	436	REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
	437	DP_MSA_HSYNCWIDTH,
	438	crtc_timing->h_sync_width,
	439	DP_MSA_HSYNCPOLARITY,
	440	!crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
	441	DP_MSA_VSYNCWIDTH,
	442	crtc_timing->v_sync_width,
	443	DP_MSA_VSYNCPOLARITY,
	444	!crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
	445
	446	/* HWDITH include border or overscan */
	447	REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
	448	DP_MSA_HWIDTH, crtc_timing->h_border_left +
	449	crtc_timing->h_addressable + crtc_timing->h_border_right,
	450	DP_MSA_VHEIGHT, crtc_timing->v_border_top +
	451	crtc_timing->v_addressable + crtc_timing->v_border_bottom);
	452	}
	453
	454	static void enc1_stream_encoder_set_stream_attribute_helper(
	455	struct dcn10_stream_encoder *enc1,
	456	struct dc_crtc_timing *crtc_timing)
	457	{
	458	switch (crtc_timing->pixel_encoding) {
	459	case PIXEL_ENCODING_YCBCR422:
	460	REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
	461	break;
	462	default:
	463	REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
	464	break;
	465	}
	466	REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
	467	}
	468
	469	/* setup stream encoder in hdmi mode */
	470	void enc1_stream_encoder_hdmi_set_stream_attribute(
	471	struct stream_encoder *enc,
	472	struct dc_crtc_timing *crtc_timing,
	473	int actual_pix_clk_khz,
	474	bool enable_audio)
	475	{
	476	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	477	struct bp_encoder_control cntl = {0};
	478
	479	cntl.action = ENCODER_CONTROL_SETUP;
	480	cntl.engine_id = enc1->base.id;
	481	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
	482	cntl.enable_dp_audio = enable_audio;
	483	cntl.pixel_clock = actual_pix_clk_khz;
	484	cntl.lanes_number = LANE_COUNT_FOUR;
	485
	486	if (enc1->base.bp->funcs->encoder_control(
	487	enc1->base.bp, &cntl) != BP_RESULT_OK)
	488	return;
	489
	490	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
	491
	492	/* setup HDMI engine */
	493	REG_UPDATE_5(HDMI_CONTROL,
	494	HDMI_PACKET_GEN_VERSION, 1,
	495	HDMI_KEEPOUT_MODE, 1,
	496	HDMI_DEEP_COLOR_ENABLE, 0,
	497	HDMI_DATA_SCRAMBLE_EN, 0,
	498	HDMI_CLOCK_CHANNEL_RATE, 0);
	499
	500
	501	switch (crtc_timing->display_color_depth) {
	502	case COLOR_DEPTH_888:
	503	REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
	504	break;
	505	case COLOR_DEPTH_101010:
	506	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
	507	REG_UPDATE_2(HDMI_CONTROL,
	508	HDMI_DEEP_COLOR_DEPTH, 1,
	509	HDMI_DEEP_COLOR_ENABLE, 0);
	510	} else {
	511	REG_UPDATE_2(HDMI_CONTROL,
	512	HDMI_DEEP_COLOR_DEPTH, 1,
	513	HDMI_DEEP_COLOR_ENABLE, 1);
	514	}
	515	break;
	516	case COLOR_DEPTH_121212:
	517	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
	518	REG_UPDATE_2(HDMI_CONTROL,
	519	HDMI_DEEP_COLOR_DEPTH, 2,
	520	HDMI_DEEP_COLOR_ENABLE, 0);
	521	} else {
	522	REG_UPDATE_2(HDMI_CONTROL,
	523	HDMI_DEEP_COLOR_DEPTH, 2,
	524	HDMI_DEEP_COLOR_ENABLE, 1);
	525	}
	526	break;
	527	case COLOR_DEPTH_161616:
	528	REG_UPDATE_2(HDMI_CONTROL,
	529	HDMI_DEEP_COLOR_DEPTH, 3,
	530	HDMI_DEEP_COLOR_ENABLE, 1);
	531	break;
	532	default:
	533	break;
	534	}
	535
	536	if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
	537	/* enable HDMI data scrambler
	538	* HDMI_CLOCK_CHANNEL_RATE_MORE_340M
	539	* Clock channel frequency is 1/4 of character rate.
	540	*/
	541	REG_UPDATE_2(HDMI_CONTROL,
	542	HDMI_DATA_SCRAMBLE_EN, 1,
	543	HDMI_CLOCK_CHANNEL_RATE, 1);
	544	} else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
	545
	546	/* TODO: New feature for DCE11, still need to implement */
	547
	548	/* enable HDMI data scrambler
	549	* HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
	550	* Clock channel frequency is the same
	551	* as character rate
	552	*/
	553	REG_UPDATE_2(HDMI_CONTROL,
	554	HDMI_DATA_SCRAMBLE_EN, 1,
	555	HDMI_CLOCK_CHANNEL_RATE, 0);
	556	}
	557
	558
	559	REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
	560	HDMI_GC_CONT, 1,
	561	HDMI_GC_SEND, 1,
	562	HDMI_NULL_SEND, 1);
	563
	564	/* following belongs to audio */
	565	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
	566
	567	REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
	568
	569	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
	570	VBI_LINE_0 + 2);
	571
	572	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
	573	}
	574
	575	/* setup stream encoder in dvi mode */
	576	void enc1_stream_encoder_dvi_set_stream_attribute(
	577	struct stream_encoder *enc,
	578	struct dc_crtc_timing *crtc_timing,
	579	bool is_dual_link)
	580	{
	581	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	582	struct bp_encoder_control cntl = {0};
	583
	584	cntl.action = ENCODER_CONTROL_SETUP;
	585	cntl.engine_id = enc1->base.id;
	586	cntl.signal = is_dual_link ?
	587	SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
	588	cntl.enable_dp_audio = false;
	589	cntl.pixel_clock = crtc_timing->pix_clk_khz;
	590	cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
	591
	592	if (enc1->base.bp->funcs->encoder_control(
	593	enc1->base.bp, &cntl) != BP_RESULT_OK)
	594	return;
	595
	596	ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
	597	ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
	598	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
	599	}
	600
	601	void enc1_stream_encoder_set_mst_bandwidth(
	602	struct stream_encoder *enc,
	603	struct fixed31_32 avg_time_slots_per_mtp)
	604	{
	605	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	606	uint32_t x = dal_fixed31_32_floor(
	607	avg_time_slots_per_mtp);
	608	uint32_t y = dal_fixed31_32_ceil(
	609	dal_fixed31_32_shl(
	610	dal_fixed31_32_sub_int(
	611	avg_time_slots_per_mtp,
	612	x),
	613	26));
	614
	615	REG_SET_2(DP_MSE_RATE_CNTL, 0,
	616	DP_MSE_RATE_X, x,
	617	DP_MSE_RATE_Y, y);
	618
	619	/* wait for update to be completed on the link */
	620	/* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
	621	/* is reset to 0 (not pending) */
	622	REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
	623	0,
	624	10, DP_MST_UPDATE_MAX_RETRY);
	625	}
	626
	627	static void enc1_stream_encoder_update_hdmi_info_packets(
	628	struct stream_encoder *enc,
	629	const struct encoder_info_frame *info_frame)
	630	{
	631	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	632
	633	/* for bring up, disable dp double TODO */
	634	REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
	635
	636	enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
	637	enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
	638	enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
	639	enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
	640	enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
	641	}
	642
	643	static void enc1_stream_encoder_stop_hdmi_info_packets(
	644	struct stream_encoder *enc)
	645	{
	646	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	647
	648	/* stop generic packets 0 & 1 on HDMI */
	649	REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
	650	HDMI_GENERIC1_CONT, 0,
	651	HDMI_GENERIC1_LINE, 0,
	652	HDMI_GENERIC1_SEND, 0,
	653	HDMI_GENERIC0_CONT, 0,
	654	HDMI_GENERIC0_LINE, 0,
	655	HDMI_GENERIC0_SEND, 0);
	656
	657	/* stop generic packets 2 & 3 on HDMI */
	658	REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
	659	HDMI_GENERIC0_CONT, 0,
	660	HDMI_GENERIC0_LINE, 0,
	661	HDMI_GENERIC0_SEND, 0,
	662	HDMI_GENERIC1_CONT, 0,
	663	HDMI_GENERIC1_LINE, 0,
	664	HDMI_GENERIC1_SEND, 0);
	665
	666	/* stop generic packets 2 & 3 on HDMI */
	667	REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
	668	HDMI_GENERIC0_CONT, 0,
	669	HDMI_GENERIC0_LINE, 0,
	670	HDMI_GENERIC0_SEND, 0,
	671	HDMI_GENERIC1_CONT, 0,
	672	HDMI_GENERIC1_LINE, 0,
	673	HDMI_GENERIC1_SEND, 0);
	674
	675	REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
	676	HDMI_GENERIC0_CONT, 0,
	677	HDMI_GENERIC0_LINE, 0,
	678	HDMI_GENERIC0_SEND, 0,
	679	HDMI_GENERIC1_CONT, 0,
	680	HDMI_GENERIC1_LINE, 0,
	681	HDMI_GENERIC1_SEND, 0);
	682	}
	683
	684	void enc1_stream_encoder_update_dp_info_packets(
	685	struct stream_encoder *enc,
	686	const struct encoder_info_frame *info_frame)
	687	{
	688	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	689	uint32_t value = 0;
	690
	691	if (info_frame->vsc.valid)
	692	enc1_update_generic_info_packet(
	693	enc1,
	694	0, /* packetIndex */
	695	&info_frame->vsc);
	696
	697	if (info_frame->spd.valid)
	698	enc1_update_generic_info_packet(
	699	enc1,
	700	2, /* packetIndex */
	701	&info_frame->spd);
	702
	703	if (info_frame->hdrsmd.valid)
	704	enc1_update_generic_info_packet(
	705	enc1,
	706	3, /* packetIndex */
	707	&info_frame->hdrsmd);
	708
	709	/* enable/disable transmission of packet(s).
	710	* If enabled, packet transmission begins on the next frame
	711	*/
	712	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
	713	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
	714	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
	715
	716
	717	/* This bit is the master enable bit.
	718	* When enabling secondary stream engine,
	719	* this master bit must also be set.
	720	* This register shared with audio info frame.
	721	* Therefore we need to enable master bit
	722	* if at least on of the fields is not 0
	723	*/
	724	value = REG_READ(DP_SEC_CNTL);
	725	if (value)
	726	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
	727	}
	728
	729	void enc1_stream_encoder_stop_dp_info_packets(
	730	struct stream_encoder *enc)
	731	{
	732	/* stop generic packets on DP */
	733	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	734	uint32_t value = 0;
	735
	736	REG_SET_10(DP_SEC_CNTL, 0,
	737	DP_SEC_GSP0_ENABLE, 0,
	738	DP_SEC_GSP1_ENABLE, 0,
	739	DP_SEC_GSP2_ENABLE, 0,
	740	DP_SEC_GSP3_ENABLE, 0,
	741	DP_SEC_GSP4_ENABLE, 0,
	742	DP_SEC_GSP5_ENABLE, 0,
	743	DP_SEC_GSP6_ENABLE, 0,
	744	DP_SEC_GSP7_ENABLE, 0,
	745	DP_SEC_MPG_ENABLE, 0,
	746	DP_SEC_STREAM_ENABLE, 0);
	747
	748	/* this register shared with audio info frame.
	749	* therefore we need to keep master enabled
	750	* if at least one of the fields is not 0 */
	751	value = REG_READ(DP_SEC_CNTL);
	752	if (value)
	753	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
	754
	755	}
	756
	757	void enc1_stream_encoder_dp_blank(
	758	struct stream_encoder *enc)
	759	{
	760	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	761	uint32_t retries = 0;
	762	uint32_t reg1 = 0;
	763	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
	764
	765	/* Note: For CZ, we are changing driver default to disable
	766	* stream deferred to next VBLANK. If results are positive, we
	767	* will make the same change to all DCE versions. There are a
	768	* handful of panels that cannot handle disable stream at
	769	* HBLANK and will result in a white line flash across the
	770	* screen on stream disable.
	771	*/
	772	REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
	773	if ((reg1 & 0x1) == 0)
	774	/stream not enabled/
	775	return;
	776	/* Specify the video stream disable point
	777	* (2 = start of the next vertical blank)
	778	*/
	779	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
	780	/* Larger delay to wait until VBLANK - use max retry of
	781	* 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
	782	* a little more because we may not trust delay accuracy.
	783	*/
	784	max_retries = DP_BLANK_MAX_RETRY * 150;
	785
	786	/* disable DP stream */
	787	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
	788
	789	/* the encoder stops sending the video stream
	790	* at the start of the vertical blanking.
	791	* Poll for DP_VID_STREAM_STATUS == 0
	792	*/
	793
	794	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
	795	0,
	796	10, max_retries);
	797
	798	ASSERT(retries <= max_retries);
	799
	800	/* Tell the DP encoder to ignore timing from CRTC, must be done after
	801	* the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
	802	* complete, stream status will be stuck in video stream enabled state,
	803	* i.e. DP_VID_STREAM_STATUS stuck at 1.
	804	*/
	805
	806	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
	807	}
	808
	809	/* output video stream to link encoder */
	810	void enc1_stream_encoder_dp_unblank(
	811	struct stream_encoder *enc,
	812	const struct encoder_unblank_param *param)
	813	{
	814	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	815
	816	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
	817	uint32_t n_vid = 0x8000;
	818	uint32_t m_vid;
	819
	820	/* M / N = Fstream / Flink
	821	* m_vid / n_vid = pixel rate / link rate
	822	*/
	823
	824	uint64_t m_vid_l = n_vid;
	825
	826	m_vid_l *= param->pixel_clk_khz;
	827	m_vid_l = div_u64(m_vid_l,
	828	param->link_settings.link_rate
	829	* LINK_RATE_REF_FREQ_IN_KHZ);
	830
	831	m_vid = (uint32_t) m_vid_l;
	832
	833	/* enable auto measurement */
	834
	835	REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
	836
	837	/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
	838	* therefore program initial value for Mvid and Nvid
	839	*/
	840
	841	REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
	842
	843	REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
	844
	845	REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
	846	}
	847
	848	/* set DIG_START to 0x1 to resync FIFO */
	849
	850	REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
	851
	852	/* switch DP encoder to CRTC data */
	853
	854	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
	855
	856	/* wait 100us for DIG/DP logic to prime
	857	* (i.e. a few video lines)
	858	*/
	859	udelay(100);
	860
	861	/* the hardware would start sending video at the start of the next DP
	862	* frame (i.e. rising edge of the vblank).
	863	* NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
	864	* register has no effect on enable transition! HW always guarantees
	865	* VID_STREAM enable at start of next frame, and this is not
	866	* programmable
	867	*/
	868
	869	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
	870	}
	871
	872	void enc1_stream_encoder_set_avmute(
	873	struct stream_encoder *enc,
	874	bool enable)
	875	{
	876	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	877	unsigned int value = enable ? 1 : 0;
	878
	879	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
	880	}
	881
	882
	883	#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
	884	#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
	885
	886	#include "include/audio_types.h"
	887
	888	/**
	889	* speakersToChannels
	890	*
	891	* @brief
	892	* translate speakers to channels
	893	*
	894	* FL - Front Left
	895	* FR - Front Right
	896	* RL - Rear Left
	897	* RR - Rear Right
	898	* RC - Rear Center
	899	* FC - Front Center
	900	* FLC - Front Left Center
	901	* FRC - Front Right Center
	902	* RLC - Rear Left Center
	903	* RRC - Rear Right Center
	904	* LFE - Low Freq Effect
	905	*
	906	* FC
	907	* FLC FRC
	908	* FL FR
	909	*
	910	* LFE
	911	* ()
	912	*
	913	*
	914	* RL RR
	915	* RLC RRC
	916	* RC
	917	*
	918	* ch 8 7 6 5 4 3 2 1
	919	* 0b00000011 - - - - - - FR FL
	920	* 0b00000111 - - - - - LFE FR FL
	921	* 0b00001011 - - - - FC - FR FL
	922	* 0b00001111 - - - - FC LFE FR FL
	923	* 0b00010011 - - - RC - - FR FL
	924	* 0b00010111 - - - RC - LFE FR FL
	925	* 0b00011011 - - - RC FC - FR FL
	926	* 0b00011111 - - - RC FC LFE FR FL
	927	* 0b00110011 - - RR RL - - FR FL
	928	* 0b00110111 - - RR RL - LFE FR FL
	929	* 0b00111011 - - RR RL FC - FR FL
	930	* 0b00111111 - - RR RL FC LFE FR FL
	931	* 0b01110011 - RC RR RL - - FR FL
	932	* 0b01110111 - RC RR RL - LFE FR FL
	933	* 0b01111011 - RC RR RL FC - FR FL
	934	* 0b01111111 - RC RR RL FC LFE FR FL
	935	* 0b11110011 RRC RLC RR RL - - FR FL
	936	* 0b11110111 RRC RLC RR RL - LFE FR FL
	937	* 0b11111011 RRC RLC RR RL FC - FR FL
	938	* 0b11111111 RRC RLC RR RL FC LFE FR FL
	939	* 0b11000011 FRC FLC - - - - FR FL
	940	* 0b11000111 FRC FLC - - - LFE FR FL
	941	* 0b11001011 FRC FLC - - FC - FR FL
	942	* 0b11001111 FRC FLC - - FC LFE FR FL
	943	* 0b11010011 FRC FLC - RC - - FR FL
	944	* 0b11010111 FRC FLC - RC - LFE FR FL
	945	* 0b11011011 FRC FLC - RC FC - FR FL
	946	* 0b11011111 FRC FLC - RC FC LFE FR FL
	947	* 0b11110011 FRC FLC RR RL - - FR FL
	948	* 0b11110111 FRC FLC RR RL - LFE FR FL
	949	* 0b11111011 FRC FLC RR RL FC - FR FL
	950	* 0b11111111 FRC FLC RR RL FC LFE FR FL
	951	*
	952	* @param
	953	* speakers - speaker information as it comes from CEA audio block
	954	*/
	955	/* translate speakers to channels */
	956
	957	union audio_cea_channels {
	958	uint8_t all;
	959	struct audio_cea_channels_bits {
	960	uint32_t FL:1;
	961	uint32_t FR:1;
	962	uint32_t LFE:1;
	963	uint32_t FC:1;
	964	uint32_t RL_RC:1;
	965	uint32_t RR:1;
	966	uint32_t RC_RLC_FLC:1;
	967	uint32_t RRC_FRC:1;
	968	} channels;
	969	};
	970
	971	struct audio_clock_info {
	972	/* pixel clock frequency*/
	973	uint32_t pixel_clock_in_10khz;
	974	/* N - 32KHz audio */
	975	uint32_t n_32khz;
	976	/* CTS - 32KHz audio*/
	977	uint32_t cts_32khz;
	978	uint32_t n_44khz;
	979	uint32_t cts_44khz;
	980	uint32_t n_48khz;
	981	uint32_t cts_48khz;
	982	};
	983
	984	/* 25.2MHz/1.001*/
	985	/* 25.2MHz/1.001*/
	986	/* 25.2MHz*/
	987	/* 27MHz */
	988	/* 27MHz1.001/
	989	/* 27MHz1.001/
	990	/* 54MHz*/
	991	/* 54MHz1.001/
	992	/* 74.25MHz/1.001*/
	993	/* 74.25MHz*/
	994	/* 148.5MHz/1.001*/
	995	/* 148.5MHz*/
	996
	997	static const struct audio_clock_info audio_clock_info_table[16] = {
	998	{2517, 4576, 28125, 7007, 31250, 6864, 28125},
	999	{2518, 4576, 28125, 7007, 31250, 6864, 28125},
	1000	{2520, 4096, 25200, 6272, 28000, 6144, 25200},
	1001	{2700, 4096, 27000, 6272, 30000, 6144, 27000},
	1002	{2702, 4096, 27027, 6272, 30030, 6144, 27027},
	1003	{2703, 4096, 27027, 6272, 30030, 6144, 27027},
	1004	{5400, 4096, 54000, 6272, 60000, 6144, 54000},
	1005	{5405, 4096, 54054, 6272, 60060, 6144, 54054},
	1006	{7417, 11648, 210937, 17836, 234375, 11648, 140625},
	1007	{7425, 4096, 74250, 6272, 82500, 6144, 74250},
	1008	{14835, 11648, 421875, 8918, 234375, 5824, 140625},
	1009	{14850, 4096, 148500, 6272, 165000, 6144, 148500},
	1010	{29670, 5824, 421875, 4459, 234375, 5824, 281250},
	1011	{29700, 3072, 222750, 4704, 247500, 5120, 247500},
	1012	{59340, 5824, 843750, 8918, 937500, 5824, 562500},
	1013	{59400, 3072, 445500, 9408, 990000, 6144, 594000}
	1014	};
	1015
	1016	static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
	1017	{2517, 9152, 84375, 7007, 48875, 9152, 56250},
	1018	{2518, 9152, 84375, 7007, 48875, 9152, 56250},
	1019	{2520, 4096, 37800, 6272, 42000, 6144, 37800},
	1020	{2700, 4096, 40500, 6272, 45000, 6144, 40500},
	1021	{2702, 8192, 81081, 6272, 45045, 8192, 54054},
	1022	{2703, 8192, 81081, 6272, 45045, 8192, 54054},
	1023	{5400, 4096, 81000, 6272, 90000, 6144, 81000},
	1024	{5405, 4096, 81081, 6272, 90090, 6144, 81081},
	1025	{7417, 11648, 316406, 17836, 351562, 11648, 210937},
	1026	{7425, 4096, 111375, 6272, 123750, 6144, 111375},
	1027	{14835, 11648, 632812, 17836, 703125, 11648, 421875},
	1028	{14850, 4096, 222750, 6272, 247500, 6144, 222750},
	1029	{29670, 5824, 632812, 8918, 703125, 5824, 421875},
	1030	{29700, 4096, 445500, 4704, 371250, 5120, 371250}
	1031	};
	1032
	1033	static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
	1034	{2517, 4576, 56250, 7007, 62500, 6864, 56250},
	1035	{2518, 4576, 56250, 7007, 62500, 6864, 56250},
	1036	{2520, 4096, 50400, 6272, 56000, 6144, 50400},
	1037	{2700, 4096, 54000, 6272, 60000, 6144, 54000},
	1038	{2702, 4096, 54054, 6267, 60060, 8192, 54054},
	1039	{2703, 4096, 54054, 6272, 60060, 8192, 54054},
	1040	{5400, 4096, 108000, 6272, 120000, 6144, 108000},
	1041	{5405, 4096, 108108, 6272, 120120, 6144, 108108},
	1042	{7417, 11648, 421875, 17836, 468750, 11648, 281250},
	1043	{7425, 4096, 148500, 6272, 165000, 6144, 148500},
	1044	{14835, 11648, 843750, 8918, 468750, 11648, 281250},
	1045	{14850, 4096, 297000, 6272, 330000, 6144, 297000},
	1046	{29670, 5824, 843750, 4459, 468750, 5824, 562500},
	1047	{29700, 3072, 445500, 4704, 495000, 5120, 495000}
	1048
	1049
	1050	};
	1051
	1052	static union audio_cea_channels speakers_to_channels(
	1053	struct audio_speaker_flags speaker_flags)
	1054	{
	1055	union audio_cea_channels cea_channels = {0};
	1056
	1057	/* these are one to one */
	1058	cea_channels.channels.FL = speaker_flags.FL_FR;
	1059	cea_channels.channels.FR = speaker_flags.FL_FR;
	1060	cea_channels.channels.LFE = speaker_flags.LFE;
	1061	cea_channels.channels.FC = speaker_flags.FC;
	1062
	1063	/* if Rear Left and Right exist move RC speaker to channel 7
	1064	* otherwise to channel 5
	1065	*/
	1066	if (speaker_flags.RL_RR) {
	1067	cea_channels.channels.RL_RC = speaker_flags.RL_RR;
	1068	cea_channels.channels.RR = speaker_flags.RL_RR;
	1069	cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
	1070	} else {
	1071	cea_channels.channels.RL_RC = speaker_flags.RC;
	1072	}
	1073
	1074	/* FRONT Left Right Center and REAR Left Right Center are exclusive */
	1075	if (speaker_flags.FLC_FRC) {
	1076	cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
	1077	cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
	1078	} else {
	1079	cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
	1080	cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
	1081	}
	1082
	1083	return cea_channels;
	1084	}
	1085
	1086	static uint32_t calc_max_audio_packets_per_line(
	1087	const struct audio_crtc_info *crtc_info)
	1088	{
	1089	uint32_t max_packets_per_line;
	1090
	1091	max_packets_per_line =
	1092	crtc_info->h_total - crtc_info->h_active;
	1093
	1094	if (crtc_info->pixel_repetition)
	1095	max_packets_per_line *= crtc_info->pixel_repetition;
	1096
	1097	/* for other hdmi features */
	1098	max_packets_per_line -= 58;
	1099	/* for Control Period */
	1100	max_packets_per_line -= 16;
	1101	/* Number of Audio Packets per Line */
	1102	max_packets_per_line /= 32;
	1103
	1104	return max_packets_per_line;
	1105	}
	1106
	1107	static void get_audio_clock_info(
	1108	enum dc_color_depth color_depth,
	1109	uint32_t crtc_pixel_clock_in_khz,
	1110	uint32_t actual_pixel_clock_in_khz,
	1111	struct audio_clock_info *audio_clock_info)
	1112	{
	1113	const struct audio_clock_info *clock_info;
	1114	uint32_t index;
	1115	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
	1116	uint32_t audio_array_size;
	1117
	1118	switch (color_depth) {
	1119	case COLOR_DEPTH_161616:
	1120	clock_info = audio_clock_info_table_48bpc;
	1121	audio_array_size = ARRAY_SIZE(
	1122	audio_clock_info_table_48bpc);
	1123	break;
	1124	case COLOR_DEPTH_121212:
	1125	clock_info = audio_clock_info_table_36bpc;
	1126	audio_array_size = ARRAY_SIZE(
	1127	audio_clock_info_table_36bpc);
	1128	break;
	1129	default:
	1130	clock_info = audio_clock_info_table;
	1131	audio_array_size = ARRAY_SIZE(
	1132	audio_clock_info_table);
	1133	break;
	1134	}
	1135
	1136	if (clock_info != NULL) {
	1137	/* search for exact pixel clock in table */
	1138	for (index = 0; index < audio_array_size; index++) {
	1139	if (clock_info[index].pixel_clock_in_10khz >
	1140	crtc_pixel_clock_in_10khz)
	1141	break; /* not match */
	1142	else if (clock_info[index].pixel_clock_in_10khz ==
	1143	crtc_pixel_clock_in_10khz) {
	1144	/* match found */
	1145	*audio_clock_info = clock_info[index];
	1146	return;
	1147	}
	1148	}
	1149	}
	1150
	1151	/* not found */
	1152	if (actual_pixel_clock_in_khz == 0)
	1153	actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
	1154
	1155	/* See HDMI spec the table entry under
	1156	* pixel clock of "Other". */
	1157	audio_clock_info->pixel_clock_in_10khz =
	1158	actual_pixel_clock_in_khz / 10;
	1159	audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
	1160	audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
	1161	audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
	1162
	1163	audio_clock_info->n_32khz = 4096;
	1164	audio_clock_info->n_44khz = 6272;
	1165	audio_clock_info->n_48khz = 6144;
	1166	}
	1167
	1168	static void enc1_se_audio_setup(
	1169	struct stream_encoder *enc,
	1170	unsigned int az_inst,
	1171	struct audio_info *audio_info)
	1172	{
	1173	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	1174
	1175	uint32_t speakers = 0;
	1176	uint32_t channels = 0;
	1177
	1178	ASSERT(audio_info);
	1179	if (audio_info == NULL)
	1180	/* This should not happen.it does so we don't get BSOD*/
	1181	return;
	1182
	1183	speakers = audio_info->flags.info.ALLSPEAKERS;
	1184	channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
	1185
	1186	/* setup the audio stream source select (audio -> dig mapping) */
	1187	REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
	1188
	1189	/* Channel allocation */
	1190	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
	1191	}
	1192
	1193	static void enc1_se_setup_hdmi_audio(
	1194	struct stream_encoder *enc,
	1195	const struct audio_crtc_info *crtc_info)
	1196	{
	1197	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	1198
	1199	struct audio_clock_info audio_clock_info = {0};
	1200	uint32_t max_packets_per_line;
	1201
	1202	/* For now still do calculation, although this field is ignored when
	1203	* above HDMI_PACKET_GEN_VERSION set to 1
	1204	*/
	1205	max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
	1206
	1207	/* HDMI_AUDIO_PACKET_CONTROL */
	1208	REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
	1209	HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
	1210	HDMI_AUDIO_DELAY_EN, 1);
	1211
	1212	/* AFMT_AUDIO_PACKET_CONTROL */
	1213	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
	1214
	1215	/* AFMT_AUDIO_PACKET_CONTROL2 */
	1216	REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
	1217	AFMT_AUDIO_LAYOUT_OVRD, 0,
	1218	AFMT_60958_OSF_OVRD, 0);
	1219
	1220	/* HDMI_ACR_PACKET_CONTROL */
	1221	REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
	1222	HDMI_ACR_AUTO_SEND, 1,
	1223	HDMI_ACR_SOURCE, 0,
	1224	HDMI_ACR_AUDIO_PRIORITY, 0);
	1225
	1226	/* Program audio clock sample/regeneration parameters */
	1227	get_audio_clock_info(crtc_info->color_depth,
	1228	crtc_info->requested_pixel_clock,
	1229	crtc_info->calculated_pixel_clock,
	1230	&audio_clock_info);
	1231	DC_LOG_HW_AUDIO(
	1232	"\n%s:Input::requested_pixel_clock = %d" \
	1233	"calculated_pixel_clock = %d \n", __func__, \
	1234	crtc_info->requested_pixel_clock, \
	1235	crtc_info->calculated_pixel_clock);
	1236
	1237	/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
	1238	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
	1239
	1240	/* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
	1241	REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
	1242
	1243	/* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
	1244	REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
	1245
	1246	/* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
	1247	REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
	1248
	1249	/* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
	1250	REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
	1251
	1252	/* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
	1253	REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
	1254
	1255	/* Video driver cannot know in advance which sample rate will
	1256	* be used by HD Audio driver
	1257	* HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
	1258	* programmed below in interruppt callback
	1259	*/
	1260
	1261	/* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
	1262	* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
	1263	*/
	1264	REG_UPDATE_2(AFMT_60958_0,
	1265	AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
	1266	AFMT_60958_CS_CLOCK_ACCURACY, 0);
	1267
	1268	/* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
	1269	REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
	1270
	1271	/* AFMT_60958_2 now keep this settings until
	1272	* Programming guide comes out
	1273	*/
	1274	REG_UPDATE_6(AFMT_60958_2,
	1275	AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
	1276	AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
	1277	AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
	1278	AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
	1279	AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
	1280	AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
	1281	}
	1282
	1283	static void enc1_se_setup_dp_audio(
	1284	struct stream_encoder *enc)
	1285	{
	1286	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	1287
	1288	/* --- DP Audio packet configurations --- */
	1289
	1290	/* ATP Configuration */
	1291	REG_SET(DP_SEC_AUD_N, 0,
	1292	DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
	1293
	1294	/* Async/auto-calc timestamp mode */
	1295	REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
	1296	DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
	1297
	1298	/* --- The following are the registers
	1299	* copied from the SetupHDMI ---
	1300	*/
	1301
	1302	/* AFMT_AUDIO_PACKET_CONTROL */
	1303	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
	1304
	1305	/* AFMT_AUDIO_PACKET_CONTROL2 */
	1306	/* Program the ATP and AIP next */
	1307	REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
	1308	AFMT_AUDIO_LAYOUT_OVRD, 0,
	1309	AFMT_60958_OSF_OVRD, 0);
	1310
	1311	/* AFMT_INFOFRAME_CONTROL0 */
	1312	REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
	1313
	1314	/* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
	1315	REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
	1316	}
	1317
	1318	static void enc1_se_enable_audio_clock(
	1319	struct stream_encoder *enc,
	1320	bool enable)
	1321	{
	1322	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	1323
	1324	if (REG(AFMT_CNTL) == 0)
	1325	return; /* DCE8/10 does not have this register */
	1326
	1327	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
	1328
	1329	/* wait for AFMT clock to turn on,
	1330	* expectation: this should complete in 1-2 reads
	1331	*
	1332	* REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
	1333	*
	1334	* TODO: wait for clock_on does not work well. May need HW
	1335	* program sequence. But audio seems work normally even without wait
	1336	* for clock_on status change
	1337	*/
	1338	}
	1339
	1340	static void enc1_se_enable_dp_audio(
	1341	struct stream_encoder *enc)
	1342	{
	1343	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	1344
	1345	/* Enable Audio packets */
	1346	REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
	1347
	1348	/* Program the ATP and AIP next */
	1349	REG_UPDATE_2(DP_SEC_CNTL,
	1350	DP_SEC_ATP_ENABLE, 1,
	1351	DP_SEC_AIP_ENABLE, 1);
	1352
	1353	/* Program STREAM_ENABLE after all the other enables. */
	1354	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
	1355	}
	1356
	1357	static void enc1_se_disable_dp_audio(
	1358	struct stream_encoder *enc)
	1359	{
	1360	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	1361	uint32_t value = 0;
	1362
	1363	/* Disable Audio packets */
	1364	REG_UPDATE_5(DP_SEC_CNTL,
	1365	DP_SEC_ASP_ENABLE, 0,
	1366	DP_SEC_ATP_ENABLE, 0,
	1367	DP_SEC_AIP_ENABLE, 0,
	1368	DP_SEC_ACM_ENABLE, 0,
	1369	DP_SEC_STREAM_ENABLE, 0);
	1370
	1371	/* This register shared with encoder info frame. Therefore we need to
	1372	* keep master enabled if at least on of the fields is not 0
	1373	*/
	1374	value = REG_READ(DP_SEC_CNTL);
	1375	if (value != 0)
	1376	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
	1377
	1378	}
	1379
	1380	void enc1_se_audio_mute_control(
	1381	struct stream_encoder *enc,
	1382	bool mute)
	1383	{
	1384	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	1385
	1386	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
	1387	}
	1388
	1389	void enc1_se_dp_audio_setup(
	1390	struct stream_encoder *enc,
	1391	unsigned int az_inst,
	1392	struct audio_info *info)
	1393	{
	1394	enc1_se_audio_setup(enc, az_inst, info);
	1395	}
	1396
	1397	void enc1_se_dp_audio_enable(
	1398	struct stream_encoder *enc)
	1399	{
	1400	enc1_se_enable_audio_clock(enc, true);
	1401	enc1_se_setup_dp_audio(enc);
	1402	enc1_se_enable_dp_audio(enc);
	1403	}
	1404
	1405	void enc1_se_dp_audio_disable(
	1406	struct stream_encoder *enc)
	1407	{
	1408	enc1_se_disable_dp_audio(enc);
	1409	enc1_se_enable_audio_clock(enc, false);
	1410	}
	1411
	1412	void enc1_se_hdmi_audio_setup(
	1413	struct stream_encoder *enc,
	1414	unsigned int az_inst,
	1415	struct audio_info *info,
	1416	struct audio_crtc_info *audio_crtc_info)
	1417	{
	1418	enc1_se_enable_audio_clock(enc, true);
	1419	enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
	1420	enc1_se_audio_setup(enc, az_inst, info);
	1421	}
	1422
	1423	void enc1_se_hdmi_audio_disable(
	1424	struct stream_encoder *enc)
	1425	{
	1426	enc1_se_enable_audio_clock(enc, false);
	1427	}
	1428
	1429
	1430	void enc1_setup_stereo_sync(
	1431	struct stream_encoder *enc,
	1432	int tg_inst, bool enable)
	1433	{
	1434	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	1435	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
	1436	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
	1437	}
	1438
	1439
	1440	static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
	1441	.dp_set_stream_attribute =
	1442	enc1_stream_encoder_dp_set_stream_attribute,
	1443	.hdmi_set_stream_attribute =
	1444	enc1_stream_encoder_hdmi_set_stream_attribute,
	1445	.dvi_set_stream_attribute =
	1446	enc1_stream_encoder_dvi_set_stream_attribute,
	1447	.set_mst_bandwidth =
	1448	enc1_stream_encoder_set_mst_bandwidth,
	1449	.update_hdmi_info_packets =
	1450	enc1_stream_encoder_update_hdmi_info_packets,
	1451	.stop_hdmi_info_packets =
	1452	enc1_stream_encoder_stop_hdmi_info_packets,
	1453	.update_dp_info_packets =
	1454	enc1_stream_encoder_update_dp_info_packets,
	1455	.stop_dp_info_packets =
	1456	enc1_stream_encoder_stop_dp_info_packets,
	1457	.dp_blank =
	1458	enc1_stream_encoder_dp_blank,
	1459	.dp_unblank =
	1460	enc1_stream_encoder_dp_unblank,
	1461	.audio_mute_control = enc1_se_audio_mute_control,
	1462
	1463	.dp_audio_setup = enc1_se_dp_audio_setup,
	1464	.dp_audio_enable = enc1_se_dp_audio_enable,
	1465	.dp_audio_disable = enc1_se_dp_audio_disable,
	1466
	1467	.hdmi_audio_setup = enc1_se_hdmi_audio_setup,
	1468	.hdmi_audio_disable = enc1_se_hdmi_audio_disable,
	1469	.setup_stereo_sync = enc1_setup_stereo_sync,
	1470	.set_avmute = enc1_stream_encoder_set_avmute,
	1471	};
	1472
	1473	void dcn10_stream_encoder_construct(
	1474	struct dcn10_stream_encoder *enc1,
	1475	struct dc_context *ctx,
	1476	struct dc_bios *bp,
	1477	enum engine_id eng_id,
	1478	const struct dcn10_stream_enc_registers *regs,
	1479	const struct dcn10_stream_encoder_shift *se_shift,
	1480	const struct dcn10_stream_encoder_mask *se_mask)
	1481	{
	1482	enc1->base.funcs = &dcn10_str_enc_funcs;
	1483	enc1->base.ctx = ctx;
	1484	enc1->base.id = eng_id;
	1485	enc1->base.bp = bp;
	1486	enc1->regs = regs;
	1487	enc1->se_shift = se_shift;
	1488	enc1->se_mask = se_mask;
	1489	}
	1490

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h+524−0

@@ -0,0 +1,524 @@
	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef __DC_STREAM_ENCODER_DCN10_H__
	27	#define __DC_STREAM_ENCODER_DCN10_H__
	28
	29	#include "stream_encoder.h"
	30
	31	#define DCN10STRENC_FROM_STRENC(stream_encoder)\
	32	container_of(stream_encoder, struct dcn10_stream_encoder, base)
	33
	34	#define SE_COMMON_DCN_REG_LIST(id) \
	35	SRI(AFMT_CNTL, DIG, id), \
	36	SRI(AFMT_GENERIC_0, DIG, id), \
	37	SRI(AFMT_GENERIC_1, DIG, id), \
	38	SRI(AFMT_GENERIC_2, DIG, id), \
	39	SRI(AFMT_GENERIC_3, DIG, id), \
	40	SRI(AFMT_GENERIC_4, DIG, id), \
	41	SRI(AFMT_GENERIC_5, DIG, id), \
	42	SRI(AFMT_GENERIC_6, DIG, id), \
	43	SRI(AFMT_GENERIC_7, DIG, id), \
	44	SRI(AFMT_GENERIC_HDR, DIG, id), \
	45	SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
	46	SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
	47	SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \
	48	SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
	49	SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
	50	SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
	51	SRI(AFMT_60958_0, DIG, id), \
	52	SRI(AFMT_60958_1, DIG, id), \
	53	SRI(AFMT_60958_2, DIG, id), \
	54	SRI(DIG_FE_CNTL, DIG, id), \
	55	SRI(HDMI_CONTROL, DIG, id), \
	56	SRI(HDMI_DB_CONTROL, DIG, id), \
	57	SRI(HDMI_GC, DIG, id), \
	58	SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
	59	SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
	60	SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
	61	SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
	62	SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
	63	SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
	64	SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
	65	SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
	66	SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
	67	SRI(HDMI_ACR_32_0, DIG, id),\
	68	SRI(HDMI_ACR_32_1, DIG, id),\
	69	SRI(HDMI_ACR_44_0, DIG, id),\
	70	SRI(HDMI_ACR_44_1, DIG, id),\
	71	SRI(HDMI_ACR_48_0, DIG, id),\
	72	SRI(HDMI_ACR_48_1, DIG, id),\
	73	SRI(DP_DB_CNTL, DP, id), \
	74	SRI(DP_MSA_MISC, DP, id), \
	75	SRI(DP_MSA_COLORIMETRY, DP, id), \
	76	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
	77	SRI(DP_MSA_TIMING_PARAM2, DP, id), \
	78	SRI(DP_MSA_TIMING_PARAM3, DP, id), \
	79	SRI(DP_MSA_TIMING_PARAM4, DP, id), \
	80	SRI(DP_MSE_RATE_CNTL, DP, id), \
	81	SRI(DP_MSE_RATE_UPDATE, DP, id), \
	82	SRI(DP_PIXEL_FORMAT, DP, id), \
	83	SRI(DP_SEC_CNTL, DP, id), \
	84	SRI(DP_STEER_FIFO, DP, id), \
	85	SRI(DP_VID_M, DP, id), \
	86	SRI(DP_VID_N, DP, id), \
	87	SRI(DP_VID_STREAM_CNTL, DP, id), \
	88	SRI(DP_VID_TIMING, DP, id), \
	89	SRI(DP_SEC_AUD_N, DP, id), \
	90	SRI(DP_SEC_TIMESTAMP, DP, id)
	91
	92	#define SE_DCN_REG_LIST(id)\
	93	SE_COMMON_DCN_REG_LIST(id)
	94
	95
	96	struct dcn10_stream_enc_registers {
	97	uint32_t AFMT_CNTL;
	98	uint32_t AFMT_AVI_INFO0;
	99	uint32_t AFMT_AVI_INFO1;
	100	uint32_t AFMT_AVI_INFO2;
	101	uint32_t AFMT_AVI_INFO3;
	102	uint32_t AFMT_GENERIC_0;
	103	uint32_t AFMT_GENERIC_1;
	104	uint32_t AFMT_GENERIC_2;
	105	uint32_t AFMT_GENERIC_3;
	106	uint32_t AFMT_GENERIC_4;
	107	uint32_t AFMT_GENERIC_5;
	108	uint32_t AFMT_GENERIC_6;
	109	uint32_t AFMT_GENERIC_7;
	110	uint32_t AFMT_GENERIC_HDR;
	111	uint32_t AFMT_INFOFRAME_CONTROL0;
	112	uint32_t AFMT_VBI_PACKET_CONTROL;
	113	uint32_t AFMT_VBI_PACKET_CONTROL1;
	114	uint32_t AFMT_AUDIO_PACKET_CONTROL;
	115	uint32_t AFMT_AUDIO_PACKET_CONTROL2;
	116	uint32_t AFMT_AUDIO_SRC_CONTROL;
	117	uint32_t AFMT_60958_0;
	118	uint32_t AFMT_60958_1;
	119	uint32_t AFMT_60958_2;
	120	uint32_t DIG_FE_CNTL;
	121	uint32_t DP_MSE_RATE_CNTL;
	122	uint32_t DP_MSE_RATE_UPDATE;
	123	uint32_t DP_PIXEL_FORMAT;
	124	uint32_t DP_SEC_CNTL;
	125	uint32_t DP_STEER_FIFO;
	126	uint32_t DP_VID_M;
	127	uint32_t DP_VID_N;
	128	uint32_t DP_VID_STREAM_CNTL;
	129	uint32_t DP_VID_TIMING;
	130	uint32_t DP_SEC_AUD_N;
	131	uint32_t DP_SEC_TIMESTAMP;
	132	uint32_t HDMI_CONTROL;
	133	uint32_t HDMI_GC;
	134	uint32_t HDMI_GENERIC_PACKET_CONTROL0;
	135	uint32_t HDMI_GENERIC_PACKET_CONTROL1;
	136	uint32_t HDMI_GENERIC_PACKET_CONTROL2;
	137	uint32_t HDMI_GENERIC_PACKET_CONTROL3;
	138	uint32_t HDMI_GENERIC_PACKET_CONTROL4;
	139	uint32_t HDMI_GENERIC_PACKET_CONTROL5;
	140	uint32_t HDMI_INFOFRAME_CONTROL0;
	141	uint32_t HDMI_INFOFRAME_CONTROL1;
	142	uint32_t HDMI_VBI_PACKET_CONTROL;
	143	uint32_t HDMI_AUDIO_PACKET_CONTROL;
	144	uint32_t HDMI_ACR_PACKET_CONTROL;
	145	uint32_t HDMI_ACR_32_0;
	146	uint32_t HDMI_ACR_32_1;
	147	uint32_t HDMI_ACR_44_0;
	148	uint32_t HDMI_ACR_44_1;
	149	uint32_t HDMI_ACR_48_0;
	150	uint32_t HDMI_ACR_48_1;
	151	uint32_t DP_DB_CNTL;
	152	uint32_t DP_MSA_MISC;
	153	uint32_t DP_MSA_COLORIMETRY;
	154	uint32_t DP_MSA_TIMING_PARAM1;
	155	uint32_t DP_MSA_TIMING_PARAM2;
	156	uint32_t DP_MSA_TIMING_PARAM3;
	157	uint32_t DP_MSA_TIMING_PARAM4;
	158	uint32_t HDMI_DB_CONTROL;
	159	};
	160
	161
	162	#define SE_SF(reg_name, field_name, post_fix)\
	163	.field_name = reg_name ## __ ## field_name ## post_fix
	164
	165	#define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\
	166	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
	167	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
	168	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
	169	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
	170	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
	171	SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
	172	SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
	173	SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
	174	SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
	175	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
	176	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
	177	SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
	178	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
	179	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
	180	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
	181	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
	182	SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
	183	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
	184	SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
	185	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
	186	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
	187	SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
	188	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
	189	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
	190	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
	191	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
	192	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
	193	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
	194	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
	195	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
	196	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
	197	SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
	198	SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
	199	SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
	200	SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
	201	SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
	202	SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
	203	SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
	204	SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
	205	SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
	206	SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
	207	SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
	208	SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
	209	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
	210	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
	211	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
	212	SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
	213	SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
	214	SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
	215	SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
	216	SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
	217	SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
	218	SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
	219	SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
	220	SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
	221	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
	222	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
	223	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
	224	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
	225	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
	226	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
	227	SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
	228	SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
	229	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
	230	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
	231	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
	232	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
	233	SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
	234	SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
	235	SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
	236	SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
	237	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
	238	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
	239	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
	240	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
	241	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
	242	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
	243	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
	244	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
	245	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
	246	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
	247	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
	248	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
	249	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
	250	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
	251	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
	252	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
	253	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
	254	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
	255	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
	256	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
	257	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
	258	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
	259	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
	260	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
	261	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
	262	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
	263	SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
	264	SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
	265	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
	266	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
	267	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
	268	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
	269	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
	270	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
	271	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
	272	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
	273	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
	274	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
	275	SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
	276	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
	277
	278	#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
	279	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
	280
	281	#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
	282	SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
	283	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
	284	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
	285	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
	286	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
	287	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
	288	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh)
	289
	290
	291	#define SE_REG_FIELD_LIST_DCN1_0(type) \
	292	type AFMT_GENERIC_INDEX;\
	293	type AFMT_GENERIC_HB0;\
	294	type AFMT_GENERIC_HB1;\
	295	type AFMT_GENERIC_HB2;\
	296	type AFMT_GENERIC_HB3;\
	297	type AFMT_GENERIC_LOCK_STATUS;\
	298	type AFMT_GENERIC_CONFLICT;\
	299	type AFMT_GENERIC_CONFLICT_CLR;\
	300	type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\
	301	type AFMT_GENERIC1_FRAME_UPDATE_PENDING;\
	302	type AFMT_GENERIC2_FRAME_UPDATE_PENDING;\
	303	type AFMT_GENERIC3_FRAME_UPDATE_PENDING;\
	304	type AFMT_GENERIC4_FRAME_UPDATE_PENDING;\
	305	type AFMT_GENERIC5_FRAME_UPDATE_PENDING;\
	306	type AFMT_GENERIC6_FRAME_UPDATE_PENDING;\
	307	type AFMT_GENERIC7_FRAME_UPDATE_PENDING;\
	308	type AFMT_GENERIC0_FRAME_UPDATE;\
	309	type AFMT_GENERIC1_FRAME_UPDATE;\
	310	type AFMT_GENERIC2_FRAME_UPDATE;\
	311	type AFMT_GENERIC3_FRAME_UPDATE;\
	312	type AFMT_GENERIC4_FRAME_UPDATE;\
	313	type AFMT_GENERIC5_FRAME_UPDATE;\
	314	type AFMT_GENERIC6_FRAME_UPDATE;\
	315	type AFMT_GENERIC7_FRAME_UPDATE;\
	316	type HDMI_GENERIC0_CONT;\
	317	type HDMI_GENERIC0_SEND;\
	318	type HDMI_GENERIC0_LINE;\
	319	type HDMI_GENERIC1_CONT;\
	320	type HDMI_GENERIC1_SEND;\
	321	type HDMI_GENERIC1_LINE;\
	322	type HDMI_GENERIC2_CONT;\
	323	type HDMI_GENERIC2_SEND;\
	324	type HDMI_GENERIC2_LINE;\
	325	type HDMI_GENERIC3_CONT;\
	326	type HDMI_GENERIC3_SEND;\
	327	type HDMI_GENERIC3_LINE;\
	328	type HDMI_GENERIC4_CONT;\
	329	type HDMI_GENERIC4_SEND;\
	330	type HDMI_GENERIC4_LINE;\
	331	type HDMI_GENERIC5_CONT;\
	332	type HDMI_GENERIC5_SEND;\
	333	type HDMI_GENERIC5_LINE;\
	334	type HDMI_GENERIC6_CONT;\
	335	type HDMI_GENERIC6_SEND;\
	336	type HDMI_GENERIC6_LINE;\
	337	type HDMI_GENERIC7_CONT;\
	338	type HDMI_GENERIC7_SEND;\
	339	type HDMI_GENERIC7_LINE;\
	340	type DP_PIXEL_ENCODING;\
	341	type DP_COMPONENT_DEPTH;\
	342	type HDMI_PACKET_GEN_VERSION;\
	343	type HDMI_KEEPOUT_MODE;\
	344	type HDMI_DEEP_COLOR_ENABLE;\
	345	type HDMI_CLOCK_CHANNEL_RATE;\
	346	type HDMI_DEEP_COLOR_DEPTH;\
	347	type HDMI_GC_CONT;\
	348	type HDMI_GC_SEND;\
	349	type HDMI_NULL_SEND;\
	350	type HDMI_DATA_SCRAMBLE_EN;\
	351	type HDMI_AUDIO_INFO_SEND;\
	352	type AFMT_AUDIO_INFO_UPDATE;\
	353	type HDMI_AUDIO_INFO_LINE;\
	354	type HDMI_GC_AVMUTE;\
	355	type DP_MSE_RATE_X;\
	356	type DP_MSE_RATE_Y;\
	357	type DP_MSE_RATE_UPDATE_PENDING;\
	358	type DP_SEC_GSP0_ENABLE;\
	359	type DP_SEC_STREAM_ENABLE;\
	360	type DP_SEC_GSP1_ENABLE;\
	361	type DP_SEC_GSP2_ENABLE;\
	362	type DP_SEC_GSP3_ENABLE;\
	363	type DP_SEC_GSP4_ENABLE;\
	364	type DP_SEC_GSP5_ENABLE;\
	365	type DP_SEC_GSP6_ENABLE;\
	366	type DP_SEC_GSP7_ENABLE;\
	367	type DP_SEC_MPG_ENABLE;\
	368	type DP_VID_STREAM_DIS_DEFER;\
	369	type DP_VID_STREAM_ENABLE;\
	370	type DP_VID_STREAM_STATUS;\
	371	type DP_STEER_FIFO_RESET;\
	372	type DP_VID_M_N_GEN_EN;\
	373	type DP_VID_N;\
	374	type DP_VID_M;\
	375	type DIG_START;\
	376	type AFMT_AUDIO_SRC_SELECT;\
	377	type AFMT_AUDIO_CHANNEL_ENABLE;\
	378	type HDMI_AUDIO_PACKETS_PER_LINE;\
	379	type HDMI_AUDIO_DELAY_EN;\
	380	type AFMT_60958_CS_UPDATE;\
	381	type AFMT_AUDIO_LAYOUT_OVRD;\
	382	type AFMT_60958_OSF_OVRD;\
	383	type HDMI_ACR_AUTO_SEND;\
	384	type HDMI_ACR_SOURCE;\
	385	type HDMI_ACR_AUDIO_PRIORITY;\
	386	type HDMI_ACR_CTS_32;\
	387	type HDMI_ACR_N_32;\
	388	type HDMI_ACR_CTS_44;\
	389	type HDMI_ACR_N_44;\
	390	type HDMI_ACR_CTS_48;\
	391	type HDMI_ACR_N_48;\
	392	type AFMT_60958_CS_CHANNEL_NUMBER_L;\
	393	type AFMT_60958_CS_CLOCK_ACCURACY;\
	394	type AFMT_60958_CS_CHANNEL_NUMBER_R;\
	395	type AFMT_60958_CS_CHANNEL_NUMBER_2;\
	396	type AFMT_60958_CS_CHANNEL_NUMBER_3;\
	397	type AFMT_60958_CS_CHANNEL_NUMBER_4;\
	398	type AFMT_60958_CS_CHANNEL_NUMBER_5;\
	399	type AFMT_60958_CS_CHANNEL_NUMBER_6;\
	400	type AFMT_60958_CS_CHANNEL_NUMBER_7;\
	401	type DP_SEC_AUD_N;\
	402	type DP_SEC_TIMESTAMP_MODE;\
	403	type DP_SEC_ASP_ENABLE;\
	404	type DP_SEC_ATP_ENABLE;\
	405	type DP_SEC_AIP_ENABLE;\
	406	type DP_SEC_ACM_ENABLE;\
	407	type AFMT_AUDIO_SAMPLE_SEND;\
	408	type AFMT_AUDIO_CLOCK_EN;\
	409	type TMDS_PIXEL_ENCODING;\
	410	type TMDS_COLOR_FORMAT;\
	411	type DIG_STEREOSYNC_SELECT;\
	412	type DIG_STEREOSYNC_GATE_EN;\
	413	type DP_DB_DISABLE;\
	414	type DP_MSA_MISC0;\
	415	type DP_MSA_HTOTAL;\
	416	type DP_MSA_VTOTAL;\
	417	type DP_MSA_HSTART;\
	418	type DP_MSA_VSTART;\
	419	type DP_MSA_HSYNCWIDTH;\
	420	type DP_MSA_HSYNCPOLARITY;\
	421	type DP_MSA_VSYNCWIDTH;\
	422	type DP_MSA_VSYNCPOLARITY;\
	423	type DP_MSA_HWIDTH;\
	424	type DP_MSA_VHEIGHT;\
	425	type HDMI_DB_DISABLE;\
	426	type DP_VID_N_MUL;\
	427	type DP_VID_M_DOUBLE_VALUE_EN
	428
	429	struct dcn10_stream_encoder_shift {
	430	SE_REG_FIELD_LIST_DCN1_0(uint8_t);
	431	};
	432
	433	struct dcn10_stream_encoder_mask {
	434	SE_REG_FIELD_LIST_DCN1_0(uint32_t);
	435	};
	436
	437	struct dcn10_stream_encoder {
	438	struct stream_encoder base;
	439	const struct dcn10_stream_enc_registers *regs;
	440	const struct dcn10_stream_encoder_shift *se_shift;
	441	const struct dcn10_stream_encoder_mask *se_mask;
	442	};
	443
	444	void dcn10_stream_encoder_construct(
	445	struct dcn10_stream_encoder *enc1,
	446	struct dc_context *ctx,
	447	struct dc_bios *bp,
	448	enum engine_id eng_id,
	449	const struct dcn10_stream_enc_registers *regs,
	450	const struct dcn10_stream_encoder_shift *se_shift,
	451	const struct dcn10_stream_encoder_mask *se_mask);
	452
	453	void enc1_update_generic_info_packet(
	454	struct dcn10_stream_encoder *enc1,
	455	uint32_t packet_index,
	456	const struct dc_info_packet *info_packet);
	457
	458	void enc1_stream_encoder_dp_set_stream_attribute(
	459	struct stream_encoder *enc,
	460	struct dc_crtc_timing *crtc_timing,
	461	enum dc_color_space output_color_space);
	462
	463	void enc1_stream_encoder_hdmi_set_stream_attribute(
	464	struct stream_encoder *enc,
	465	struct dc_crtc_timing *crtc_timing,
	466	int actual_pix_clk_khz,
	467	bool enable_audio);
	468
	469	void enc1_stream_encoder_dvi_set_stream_attribute(
	470	struct stream_encoder *enc,
	471	struct dc_crtc_timing *crtc_timing,
	472	bool is_dual_link);
	473
	474	void enc1_stream_encoder_set_mst_bandwidth(
	475	struct stream_encoder *enc,
	476	struct fixed31_32 avg_time_slots_per_mtp);
	477
	478	void enc1_stream_encoder_update_dp_info_packets(
	479	struct stream_encoder *enc,
	480	const struct encoder_info_frame *info_frame);
	481
	482	void enc1_stream_encoder_stop_dp_info_packets(
	483	struct stream_encoder *enc);
	484
	485	void enc1_stream_encoder_dp_blank(
	486	struct stream_encoder *enc);
	487
	488	void enc1_stream_encoder_dp_unblank(
	489	struct stream_encoder *enc,
	490	const struct encoder_unblank_param *param);
	491
	492	void enc1_setup_stereo_sync(
	493	struct stream_encoder *enc,
	494	int tg_inst, bool enable);
	495
	496	void enc1_stream_encoder_set_avmute(
	497	struct stream_encoder *enc,
	498	bool enable);
	499
	500	void enc1_se_audio_mute_control(
	501	struct stream_encoder *enc,
	502	bool mute);
	503
	504	void enc1_se_dp_audio_setup(
	505	struct stream_encoder *enc,
	506	unsigned int az_inst,
	507	struct audio_info *info);
	508
	509	void enc1_se_dp_audio_enable(
	510	struct stream_encoder *enc);
	511
	512	void enc1_se_dp_audio_disable(
	513	struct stream_encoder *enc);
	514
	515	void enc1_se_hdmi_audio_setup(
	516	struct stream_encoder *enc,
	517	unsigned int az_inst,
	518	struct audio_info *info,
	519	struct audio_crtc_info *audio_crtc_info);
	520
	521	void enc1_se_hdmi_audio_disable(
	522	struct stream_encoder *enc);
	523
	524	#endif /* __DC_STREAM_ENCODER_DCN10_H__ */

drivers/gpu/drm/amd/display/dc/dm_services.h+4−0

@@ -341,6 +341,10 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); · 340 unmodified lines
341		341
342	unsigned long long dm_get_timestamp(struct dc_context *ctx);	342	unsigned long long dm_get_timestamp(struct dc_context *ctx);
343		343
		344	unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
		345	unsigned long long current_time_stamp,
		346	unsigned long long last_time_stamp);
		347
344	/*	348	/*
345	* performance tracing	349	* performance tracing
346	*/	350	*/

drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c+76−62

 #include "display_mode_lib.h"
 #include "dc_features.h"
+static const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
+	.rob_buffer_size_kbytes = 64,
+	.det_buffer_size_kbytes = 164,
+	.dpte_buffer_size_in_pte_reqs = 42,
+	.dpp_output_buffer_pixels = 2560,
+	.opp_output_buffer_lines = 1,
+	.pixel_chunk_size_kbytes = 8,
+	.pte_enable = 1,
+	.pte_chunk_size_kbytes = 2,
+	.meta_chunk_size_kbytes = 2,
+	.writeback_chunk_size_kbytes = 2,
+	.line_buffer_size_bits = 589824,
+	.max_line_buffer_lines = 12,
+	.IsLineBufferBppFixed = 0,
+	.LineBufferFixedBpp = -1,
+	.writeback_luma_buffer_size_kbytes = 12,
+	.writeback_chroma_buffer_size_kbytes = 8,
+	.max_num_dpp = 4,
+	.max_num_wb = 2,
+	.max_dchub_pscl_bw_pix_per_clk = 4,
+	.max_pscl_lb_bw_pix_per_clk = 2,
+	.max_lb_vscl_bw_pix_per_clk = 4,
+	.max_vscl_hscl_bw_pix_per_clk = 4,
+	.max_hscl_ratio = 4,
+	.max_vscl_ratio = 4,
+	.hscl_mults = 4,
+	.vscl_mults = 4,
+	.max_hscl_taps = 8,
+	.max_vscl_taps = 8,
+	.dispclk_ramp_margin_percent = 1,
+	.underscan_factor = 1.10,
+	.min_vblank_lines = 14,
+	.dppclk_delay_subtotal = 90,
+	.dispclk_delay_subtotal = 42,
+	.dcfclk_cstate_latency = 10,
+	.max_inter_dcn_tile_repeaters = 8,
+	.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,
+	.bug_forcing_LC_req_same_size_fixed = 0,
+};
+static const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {
+	.sr_exit_time_us = 9.0,
+	.sr_enter_plus_exit_time_us = 11.0,
+	.urgent_latency_us = 4.0,
+	.writeback_latency_us = 12.0,
+	.ideal_dram_bw_after_urgent_percent = 80.0,
+	.max_request_size_bytes = 256,
+	.downspread_percent = 0.5,
+	.dram_page_open_time_ns = 50.0,
+	.dram_rw_turnaround_time_ns = 17.5,
+	.dram_return_buffer_per_channel_bytes = 8192,
+	.round_trip_ping_latency_dcfclk_cycles = 128,
+	.urgent_out_of_order_return_per_channel_bytes = 256,
+	.channel_interleave_bytes = 256,
+	.num_banks = 8,
+	.num_chans = 2,
+	.vmm_page_size_bytes = 4096,
+	.dram_clock_change_latency_us = 17.0,
+	.writeback_dram_clock_change_latency_us = 23.0,
+	.return_bus_width_bytes = 64,
+};
 static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project)
 {
-	if (project == DML_PROJECT_RAVEN1) {
+	switch (project) {
-		soc->sr_exit_time_us = 9.0;
+	case DML_PROJECT_RAVEN1:
-		soc->sr_enter_plus_exit_time_us = 11.0;
+		*soc = dcn1_0_soc;
-		soc->urgent_latency_us = 4.0;
+		break;
-		soc->writeback_latency_us = 12.0;
+	default:
-		soc->ideal_dram_bw_after_urgent_percent = 80.0;
+		ASSERT(0);
-		soc->max_request_size_bytes = 256;
+		break;
-		soc->downspread_percent = 0.5;
-		soc->dram_page_open_time_ns = 50.0;
-		soc->dram_rw_turnaround_time_ns = 17.5;
-		soc->dram_return_buffer_per_channel_bytes = 8192;
-		soc->round_trip_ping_latency_dcfclk_cycles = 128;
-		soc->urgent_out_of_order_return_per_channel_bytes = 256;
-		soc->channel_interleave_bytes = 256;
-		soc->num_banks = 8;
-		soc->num_chans = 2;
-		soc->vmm_page_size_bytes = 4096;
-		soc->dram_clock_change_latency_us = 17.0;
-		soc->writeback_dram_clock_change_latency_us = 23.0;
-		soc->return_bus_width_bytes = 64;
-	} else {
-		BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
 	}
 }
 static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project project)
 {
-	if (project == DML_PROJECT_RAVEN1) {
+	switch (project) {
-		ip->rob_buffer_size_kbytes = 64;
+	case DML_PROJECT_RAVEN1:
-		ip->det_buffer_size_kbytes = 164;
+		*ip = dcn1_0_ip;
-		ip->dpte_buffer_size_in_pte_reqs = 42;
+		break;
-		ip->dpp_output_buffer_pixels = 2560;
+	default:
-		ip->opp_output_buffer_lines = 1;
+		ASSERT(0);
-		ip->pixel_chunk_size_kbytes = 8;
+		break;
-		ip->pte_enable = 1;
-		ip->pte_chunk_size_kbytes = 2;
-		ip->meta_chunk_size_kbytes = 2;
-		ip->writeback_chunk_size_kbytes = 2;
-		ip->line_buffer_size_bits = 589824;
-		ip->max_line_buffer_lines = 12;
-		ip->IsLineBufferBppFixed = 0;
-		ip->LineBufferFixedBpp = -1;
-		ip->writeback_luma_buffer_size_kbytes = 12;
-		ip->writeback_chroma_buffer_size_kbytes = 8;
-		ip->max_num_dpp = 4;
-		ip->max_num_wb = 2;
-		ip->max_dchub_pscl_bw_pix_per_clk = 4;
-		ip->max_pscl_lb_bw_pix_per_clk = 2;
-		ip->max_lb_vscl_bw_pix_per_clk = 4;
-		ip->max_vscl_hscl_bw_pix_per_clk = 4;
-		ip->max_hscl_ratio = 4;
-		ip->max_vscl_ratio = 4;
-		ip->hscl_mults = 4;
-		ip->vscl_mults = 4;
-		ip->max_hscl_taps = 8;
-		ip->max_vscl_taps = 8;
-		ip->dispclk_ramp_margin_percent = 1;
-		ip->underscan_factor = 1.10;
-		ip->min_vblank_lines = 14;
-		ip->dppclk_delay_subtotal = 90;
-		ip->dispclk_delay_subtotal = 42;
-		ip->dcfclk_cstate_latency = 10;
-		ip->max_inter_dcn_tile_repeaters = 8;
-		ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0;
-		ip->bug_forcing_LC_req_same_size_fixed = 0;
-	} else {
-		BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
 	}
 }

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h+3−2

 	int wb_vtaps_luma;
 	int wb_htaps_chroma;
 	int wb_vtaps_chroma;
-	int wb_hratio;
+	double wb_hratio;
-	int wb_vratio;
+	double wb_vratio;
 };
 struct	_vcs_dpi_display_output_params_st	{
 	int	output_bpp;
 	int	dsc_enable;
 	int	wb_enable;
+	int	num_active_wb;
 	int	opp_input_bpc;
 	int	output_type;
 	int	output_format;

drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c+3−0

 		return true;
 	case DCE_VERSION_11_0:
 	case DCE_VERSION_11_2:
+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
+	case DCE_VERSION_11_22:
+#endif
 		dal_hw_factory_dce110_init(factory);
 		return true;
 	case DCE_VERSION_12_0:

drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c+3−0

 	case DCE_VERSION_10_0:
 	case DCE_VERSION_11_0:
 	case DCE_VERSION_11_2:
+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
+	case DCE_VERSION_11_22:
+#endif
 		dal_hw_translate_dce110_init(translate);
 		return true;
 	case DCE_VERSION_12_0:

drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c+1−1

@@ -527,7 +527,7 @@ static void construct( · 526 unmodified lines
527	REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);	527	REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
528		528
529	if (xtal_ref_div == 0) {	529	if (xtal_ref_div == 0) {
530	DC_LOG_WARNING("Invalid base timer divider\n",	530	DC_LOG_WARNING("Invalid base timer divider [%s]\n",
531	__func__);	531	__func__);
532	xtal_ref_div = 2;	532	xtal_ref_div = 2;
533	}	533	}

drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c+3−0

 	case DCE_VERSION_8_3:
 		return dal_i2caux_dce80_create(ctx);
 	case DCE_VERSION_11_2:
+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
+	case DCE_VERSION_11_22:
+#endif
 		return dal_i2caux_dce112_create(ctx);
 	case DCE_VERSION_11_0:
 		return dal_i2caux_dce110_create(ctx);

drivers/gpu/drm/amd/display/dc/inc/core_types.h+1−5

 	struct link_encoder *(*link_enc_create)(
 			const struct encoder_init_data *init);
-	enum dc_status (*validate_guaranteed)(
-					struct dc *dc,
-					struct dc_stream_state *stream,
-					struct dc_state *context);
 	bool (*validate_bandwidth)(
 					struct dc *dc,
 					struct dc_state *context);
 	bool all_displays_in_sync;
 	struct dce_watermarks urgent_wm_ns[MAX_PIPES];
 	struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
+	struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
 	struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
 	int sclk_khz;
 	int sclk_deep_sleep_khz;

drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h+3−2

 		uint8_t *read_buf,
 		uint32_t read_size);
-ssize_t dal_ddc_service_read_dpcd_data(
+enum ddc_result dal_ddc_service_read_dpcd_data(
 		struct ddc_service *ddc,
 		bool i2c,
 		enum i2c_mot_mode mot,
 		uint32_t address,
 		uint8_t *data,
-		uint32_t len);
+		uint32_t len,
+		uint32_t *read);
 enum ddc_result dal_ddc_service_write_dpcd_data(
 		struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h+4−0

 	BW_CALCS_VERSION_CARRIZO,
 	BW_CALCS_VERSION_POLARIS10,
 	BW_CALCS_VERSION_POLARIS11,
+	BW_CALCS_VERSION_POLARIS12,
+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
+	BW_CALCS_VERSION_VEGAM,
+#endif
 	BW_CALCS_VERSION_STONEY,
 	BW_CALCS_VERSION_VEGA10
 };

drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h+64−0

@@ -0,0 +1,64 @@
	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef __DAL_DCHUBBUB_H__
	27	#define __DAL_DCHUBBUB_H__
	28
	29
	30	enum dcc_control {
	31	dcc_control__256_256_xxx,
	32	dcc_control__128_128_xxx,
	33	dcc_control__256_64_64,
	34	};
	35
	36	enum segment_order {
	37	segment_order__na,
	38	segment_order__contiguous,
	39	segment_order__non_contiguous,
	40	};
	41
	42
	43	struct hubbub_funcs {
	44	void (*update_dchub)(
	45	struct hubbub *hubbub,
	46	struct dchub_init_data *dh_data);
	47
	48	bool (get_dcc_compression_cap)(struct hubbub hubbub,
	49	const struct dc_dcc_surface_param *input,
	50	struct dc_surface_dcc_cap *output);
	51
	52	bool (*dcc_support_swizzle)(
	53	enum swizzle_mode_values swizzle,
	54	unsigned int bytes_per_element,
	55	enum segment_order *segment_order_horz,
	56	enum segment_order *segment_order_vert);
	57
	58	bool (*dcc_support_pixel_format)(
	59	enum surface_pixel_format format,
	60	unsigned int *bytes_per_element);
	61	};
	62
	63
	64	#endif

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h+17−1

@@ -44,7 +44,23 @@ struct dpp_grph_csc_adjustment { · 43 unmodified lines
44	enum graphics_gamut_adjust_type gamut_adjust_type;	44	enum graphics_gamut_adjust_type gamut_adjust_type;
45	};	45	};
46		46
		47	struct dcn_dpp_state {
		48	uint32_t igam_lut_mode;
		49	uint32_t igam_input_format;
		50	uint32_t dgam_lut_mode;
		51	uint32_t rgam_lut_mode;
		52	uint32_t gamut_remap_mode;
		53	uint32_t gamut_remap_c11_c12;
		54	uint32_t gamut_remap_c13_c14;
		55	uint32_t gamut_remap_c21_c22;
		56	uint32_t gamut_remap_c23_c24;
		57	uint32_t gamut_remap_c31_c32;
		58	uint32_t gamut_remap_c33_c34;
		59	};
		60
47	struct dpp_funcs {	61	struct dpp_funcs {
		62	void (dpp_read_state)(struct dpp dpp, struct dcn_dpp_state *s);
		63
48	void (dpp_reset)(struct dpp dpp);	64	void (dpp_reset)(struct dpp dpp);
49		65
50	void (dpp_set_scaler)(struct dpp dpp,	66	void (dpp_set_scaler)(struct dpp dpp,
@@ -117,7 +133,7 @@ struct dpp_funcs { · 66 unmodified lines
117	struct dpp *dpp_base,	133	struct dpp *dpp_base,
118	enum surface_pixel_format format,	134	enum surface_pixel_format format,
119	enum expansion_mode mode,	135	enum expansion_mode mode,
120	struct csc_transform input_csc_color_matrix,	136	struct dc_csc_transform input_csc_color_matrix,
121	enum dc_color_space input_color_space);	137	enum dc_color_space input_color_space);
122		138
123	void (dpp_full_bypass)(struct dpp dpp_base);	139	void (dpp_full_bypass)(struct dpp dpp_base);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h+1−1

 	bool power_gated;
 };
 struct hubp_funcs {
 	void (*hubp_setup)(
 			struct hubp *hubp,
 	void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
 	void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
+	void (*hubp_read_state)(struct hubp *hubp);
 };

drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h+5−5

 	OPP_REGAMMA_USER
 };
-struct csc_transform {
-	uint16_t matrix[12];
-	bool enable_adjustment;
-};
 struct dc_bias_and_scale {
 	uint16_t scale_red;
 	uint16_t bias_red;
 	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
 };
+enum dc_lut_mode {
+	LUT_BYPASS,
+	LUT_RAM_A,
+	LUT_RAM_B
+};
 #endif /* __DAL_HW_SHARED_H__ */

drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h+1−1

@@ -87,7 +87,7 @@ struct ipp_funcs { · 86 unmodified lines
87	struct input_pixel_processor *ipp,	87	struct input_pixel_processor *ipp,
88	enum surface_pixel_format format,	88	enum surface_pixel_format format,
89	enum expansion_mode mode,	89	enum expansion_mode mode,
90	struct csc_transform input_csc_color_matrix,	90	struct dc_csc_transform input_csc_color_matrix,
91	enum dc_color_space input_color_space);	91	enum dc_color_space input_color_space);
92		92
93	/* DCE function to setup IPP. TODO: see if we can consolidate to setup */	93	/* DCE function to setup IPP. TODO: see if we can consolidate to setup */

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h+1−0

@@ -149,6 +149,7 @@ struct link_encoder_funcs { · 148 unmodified lines
149	bool connect);	149	bool connect);
150	void (enable_hpd)(struct link_encoder enc);	150	void (enable_hpd)(struct link_encoder enc);
151	void (disable_hpd)(struct link_encoder enc);	151	void (disable_hpd)(struct link_encoder enc);
		152	bool (is_dig_enabled)(struct link_encoder enc);
152	void (destroy)(struct link_encoder *enc);	153	void (destroy)(struct link_encoder *enc);
153	};	154	};
154		155

drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h+1−0

@@ -104,6 +104,7 @@ struct mem_input_funcs { · 103 unmodified lines
104	struct mem_input *mem_input,	104	struct mem_input *mem_input,
105	struct dce_watermarks nbp,	105	struct dce_watermarks nbp,
106	struct dce_watermarks stutter,	106	struct dce_watermarks stutter,
		107	struct dce_watermarks stutter_enter,
107	struct dce_watermarks urgent,	108	struct dce_watermarks urgent,
108	uint32_t total_dest_line_time_ns);	109	uint32_t total_dest_line_time_ns);
109		110

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h+17−0

@@ -105,7 +105,24 @@ struct mpc { · 104 unmodified lines
105	struct mpcc mpcc_array[MAX_MPCC];	105	struct mpcc mpcc_array[MAX_MPCC];
106	};	106	};
107		107
		108	struct mpcc_state {
		109	uint32_t opp_id;
		110	uint32_t dpp_id;
		111	uint32_t bot_mpcc_id;
		112	uint32_t mode;
		113	uint32_t alpha_mode;
		114	uint32_t pre_multiplied_alpha;
		115	uint32_t overlap_only;
		116	uint32_t idle;
		117	uint32_t busy;
		118	};
		119
108	struct mpc_funcs {	120	struct mpc_funcs {
		121	void (*read_mpcc_state)(
		122	struct mpc *mpc,
		123	int mpcc_inst,
		124	struct mpcc_state *s);
		125
109	/*	126	/*
110	* Insert DPP into MPC tree based on specified blending position.	127	* Insert DPP into MPC tree based on specified blending position.
111	* Only used for planes that are part of blending chain for OPP output	128	* Only used for planes that are part of blending chain for OPP output

drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h+23−13

 #define STREAM_ENCODER_H_
 #include "audio_types.h"
+#include "hw_shared.h"
 struct dc_bios;
 struct dc_context;
 struct dc_crtc_timing;
-struct encoder_info_packet {
+enum dp_pixel_encoding_type {
-	bool valid;
+	DP_PIXEL_ENCODING_TYPE_RGB444		= 0x00000000,
-	uint8_t hb0;
+	DP_PIXEL_ENCODING_TYPE_YCBCR422		= 0x00000001,
-	uint8_t hb1;
+	DP_PIXEL_ENCODING_TYPE_YCBCR444		= 0x00000002,
-	uint8_t hb2;
+	DP_PIXEL_ENCODING_TYPE_RGB_WIDE_GAMUT	= 0x00000003,
-	uint8_t hb3;
+	DP_PIXEL_ENCODING_TYPE_Y_ONLY		= 0x00000004,
-	uint8_t sb[32];
+	DP_PIXEL_ENCODING_TYPE_YCBCR420		= 0x00000005
+};
+enum dp_component_depth {
+	DP_COMPONENT_PIXEL_DEPTH_6BPC		= 0x00000000,
+	DP_COMPONENT_PIXEL_DEPTH_8BPC		= 0x00000001,
+	DP_COMPONENT_PIXEL_DEPTH_10BPC		= 0x00000002,
+	DP_COMPONENT_PIXEL_DEPTH_12BPC		= 0x00000003,
+	DP_COMPONENT_PIXEL_DEPTH_16BPC		= 0x00000004
 };
 struct encoder_info_frame {
 	/* auxiliary video information */
-	struct encoder_info_packet avi;
+	struct dc_info_packet avi;
-	struct encoder_info_packet gamut;
+	struct dc_info_packet gamut;
-	struct encoder_info_packet vendor;
+	struct dc_info_packet vendor;
 	/* source product description */
-	struct encoder_info_packet spd;
+	struct dc_info_packet spd;
 	/* video stream configuration */
-	struct encoder_info_packet vsc;
+	struct dc_info_packet vsc;
 	/* HDR Static MetaData */
-	struct encoder_info_packet hdrsmd;
+	struct dc_info_packet hdrsmd;
 };
 struct encoder_unblank_param {
 	void (*set_avmute)(
 		struct stream_encoder *enc, bool enable);
 };
 #endif /* STREAM_ENCODER_H_ */

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h+3−0

 	void (*program_timing)(struct timing_generator *tg,
 							const struct dc_crtc_timing *timing,
 							bool use_vbios);
+	void (*program_vline_interrupt)(struct timing_generator *optc,
+			const struct dc_crtc_timing *dc_crtc_timing,
+			unsigned long long vsync_delta);
 	bool (*enable_crtc)(struct timing_generator *tg);
 	bool (*disable_crtc)(struct timing_generator *tg);
 	bool (*is_counter_moving)(struct timing_generator *tg);

drivers/gpu/drm/amd/display/dc/inc/hw/transform.h+1−1

@@ -252,7 +252,7 @@ struct transform_funcs { · 251 unmodified lines
252	struct transform *xfm_base,	252	struct transform *xfm_base,
253	enum surface_pixel_format format,	253	enum surface_pixel_format format,
254	enum expansion_mode mode,	254	enum expansion_mode mode,
255	struct csc_transform input_csc_color_matrix,	255	struct dc_csc_transform input_csc_color_matrix,
256	enum dc_color_space input_color_space);	256	enum dc_color_space input_color_space);
257		257
258	void (ipp_full_bypass)(struct transform xfm_base);	258	void (ipp_full_bypass)(struct transform xfm_base);

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h+16−1

 #include "inc/hw/link_encoder.h"
 #include "core_status.h"
+#define EDP_BACKLIGHT_RAMP_DISABLE_LEVEL 0xFFFFFFFF
 enum pipe_gating_control {
 	PIPE_GATING_CONTROL_DISABLE = 0,
 	PIPE_GATING_CONTROL_ENABLE,
 struct dc_static_screen_events;
 struct resource_pool;
 struct resource_context;
+struct stream_resource;
 struct hw_sequencer_funcs {
 			enum dc_color_space colorspace,
 			uint16_t *matrix);
+	void (*program_output_csc)(struct dc *dc,
+			struct pipe_ctx *pipe_ctx,
+			enum dc_color_space colorspace,
+			uint16_t *matrix,
+			int opp_id);
 	void (*update_plane_addr)(
 		const struct dc *dc,
 		struct pipe_ctx *pipe_ctx);
 				struct dc *dc,
 				struct pipe_ctx *pipe,
 				bool lock);
+	void (*blank_pixel_data)(
+			struct dc *dc,
+			struct stream_resource *stream_res,
+			struct dc_stream_state *stream,
+			bool blank);
 	void (*set_bandwidth)(
 			struct dc *dc,
 	void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
 			int num_pipes, const struct dc_static_screen_events *events);
-	enum dc_status (*prog_pixclk_crtc_otg)(
+	enum dc_status (*enable_stream_timing)(
 			struct pipe_ctx *pipe_ctx,
 			struct dc_state *context,
 			struct dc *dc);
 	void (*set_cursor_position)(struct pipe_ctx *pipe);
 	void (*set_cursor_attribute)(struct pipe_ctx *pipe);
 };
 void color_space_to_black_color(

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h+56−0

@@ -183,6 +183,36 @@ · 182 unmodified lines
183	FN(reg_name, f4), v4, \	183	FN(reg_name, f4), v4, \
184	FN(reg_name, f5), v5)	184	FN(reg_name, f5), v5)
185		185
		186	#define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
		187	generic_reg_get6(CTX, REG(reg_name), \
		188	FN(reg_name, f1), v1, \
		189	FN(reg_name, f2), v2, \
		190	FN(reg_name, f3), v3, \
		191	FN(reg_name, f4), v4, \
		192	FN(reg_name, f5), v5, \
		193	FN(reg_name, f6), v6)
		194
		195	#define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
		196	generic_reg_get7(CTX, REG(reg_name), \
		197	FN(reg_name, f1), v1, \
		198	FN(reg_name, f2), v2, \
		199	FN(reg_name, f3), v3, \
		200	FN(reg_name, f4), v4, \
		201	FN(reg_name, f5), v5, \
		202	FN(reg_name, f6), v6, \
		203	FN(reg_name, f7), v7)
		204
		205	#define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
		206	generic_reg_get8(CTX, REG(reg_name), \
		207	FN(reg_name, f1), v1, \
		208	FN(reg_name, f2), v2, \
		209	FN(reg_name, f3), v3, \
		210	FN(reg_name, f4), v4, \
		211	FN(reg_name, f5), v5, \
		212	FN(reg_name, f6), v6, \
		213	FN(reg_name, f7), v7, \
		214	FN(reg_name, f8), v8)
		215
186	/* macro to poll and wait for a register field to read back given value */	216	/* macro to poll and wait for a register field to read back given value */
187		217
188	#define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \	218	#define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \
@@ -389,4 +419,30 @@ uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, · 200 unmodified lines
389	uint8_t shift4, uint32_t mask4, uint32_t *field_value4,	419	uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
390	uint8_t shift5, uint32_t mask5, uint32_t *field_value5);	420	uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
391		421
		422	uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
		423	uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
		424	uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
		425	uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
		426	uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
		427	uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
		428	uint8_t shift6, uint32_t mask6, uint32_t *field_value6);
		429
		430	uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
		431	uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
		432	uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
		433	uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
		434	uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
		435	uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
		436	uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
		437	uint8_t shift7, uint32_t mask7, uint32_t *field_value7);
		438
		439	uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
		440	uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
		441	uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
		442	uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
		443	uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
		444	uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
		445	uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
		446	uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
		447	uint8_t shift8, uint32_t mask8, uint32_t *field_value8);
392	#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */	448	#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */

drivers/gpu/drm/amd/display/dc/inc/resource.h+0−4

 		struct dc_state *context,
 		const struct resource_pool *pool);
-void validate_guaranteed_copy_streams(
-		struct dc_state *context,
-		int max_streams);
 void resource_validate_ctx_update_pointer_after_copy(
 		const struct dc_state *src_ctx,
 		struct dc_state *dst_ctx);

drivers/gpu/drm/amd/display/dc/irq_types.h+7−0

@@ -135,6 +135,13 @@ enum dc_irq_source { · 134 unmodified lines
135	DC_IRQ_SOURCE_VBLANK5,	135	DC_IRQ_SOURCE_VBLANK5,
136	DC_IRQ_SOURCE_VBLANK6,	136	DC_IRQ_SOURCE_VBLANK6,
137		137
		138	DC_IRQ_SOURCE_DC1_VLINE0,
		139	DC_IRQ_SOURCE_DC2_VLINE0,
		140	DC_IRQ_SOURCE_DC3_VLINE0,
		141	DC_IRQ_SOURCE_DC4_VLINE0,
		142	DC_IRQ_SOURCE_DC5_VLINE0,
		143	DC_IRQ_SOURCE_DC6_VLINE0,
		144
138	DAL_IRQ_SOURCES_NUMBER	145	DAL_IRQ_SOURCES_NUMBER
139	};	146	};
140		147

drivers/gpu/drm/amd/display/include/dal_asic_id.h+14−2

 		(eChipRev < VI_POLARIS11_M_A0))
 #define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) &&  \
 		(eChipRev < VI_POLARIS12_V_A0))
+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
+#define VI_VEGAM_A0 110
+#define ASIC_REV_IS_POLARIS12_V(eChipRev) ((eChipRev >= VI_POLARIS12_V_A0) && \
+		(eChipRev < VI_VEGAM_A0))
+#define ASIC_REV_IS_VEGAM(eChipRev) (eChipRev >= VI_VEGAM_A0)
+#else
 #define ASIC_REV_IS_POLARIS12_V(eChipRev) (eChipRev >= VI_POLARIS12_V_A0)
+#endif
 /* DCE11 */
 #define CZ_CARRIZO_A0 0x01
 #define AI_GREENLAND_P_A0 1
 #define AI_GREENLAND_P_A1 2
+#define AI_UNKNOWN 0xFF
-#define ASICREV_IS_GREENLAND_M(eChipRev)  (eChipRev < AI_UNKNOWN)
+#define AI_VEGA12_P_A0 20
-#define ASICREV_IS_GREENLAND_P(eChipRev)  (eChipRev < AI_UNKNOWN)
+#define ASICREV_IS_GREENLAND_M(eChipRev)  (eChipRev < AI_VEGA12_P_A0)
+#define ASICREV_IS_GREENLAND_P(eChipRev)  (eChipRev < AI_VEGA12_P_A0)
+#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
+#define ASICREV_IS_VEGA12_p(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
 /* DCN1_0 */
 #define INTERNAL_REV_RAVEN_A0             0x00    /* First spin of Raven */

drivers/gpu/drm/amd/display/include/dal_types.h+3−0

 	DCE_VERSION_10_0,
 	DCE_VERSION_11_0,
 	DCE_VERSION_11_2,
+#if defined(CONFIG_DRM_AMD_DC_VEGAM)
+	DCE_VERSION_11_22,
+#endif
 	DCE_VERSION_12_0,
 	DCE_VERSION_MAX,
 	DCN_VERSION_1_0,

drivers/gpu/drm/amd/display/include/fixed31_32.h+19−21

 #ifndef __DAL_FIXED31_32_H__
 #define __DAL_FIXED31_32_H__
-#include "os_types.h"
 #define FIXED31_32_BITS_PER_FRACTIONAL_PART 32
 /*
  */
 struct fixed31_32 {
-	int64_t value;
+	long long value;
 };
 /*
  * result = numerator / denominator
  */
 struct fixed31_32 dal_fixed31_32_from_fraction(
-	int64_t numerator,
+	long long numerator,
-	int64_t denominator);
+	long long denominator);
 /*
  * @brief
  * result = arg
  */
-struct fixed31_32 dal_fixed31_32_from_int_nonconst(int64_t arg);
+struct fixed31_32 dal_fixed31_32_from_int_nonconst(long long arg);
-static inline struct fixed31_32 dal_fixed31_32_from_int(int64_t arg)
+static inline struct fixed31_32 dal_fixed31_32_from_int(long long arg)
 {
 	if (__builtin_constant_p(arg)) {
 		struct fixed31_32 res;
  */
 struct fixed31_32 dal_fixed31_32_shl(
 	struct fixed31_32 arg,
-	uint8_t shift);
+	unsigned char shift);
 /*
  * @brief
  */
 static inline struct fixed31_32 dal_fixed31_32_shr(
 	struct fixed31_32 arg,
-	uint8_t shift)
+	unsigned char shift)
 {
 	struct fixed31_32 res;
 	res.value = arg.value >> shift;
  * result = arg1 + arg2
  */
 static inline struct fixed31_32 dal_fixed31_32_add_int(struct fixed31_32 arg1,
-						       int32_t arg2)
+						       int arg2)
 {
 	return dal_fixed31_32_add(arg1,
 				  dal_fixed31_32_from_int(arg2));
  * result = arg1 - arg2
  */
 static inline struct fixed31_32 dal_fixed31_32_sub_int(struct fixed31_32 arg1,
-						       int32_t arg2)
+						       int arg2)
 {
 	return dal_fixed31_32_sub(arg1,
 				  dal_fixed31_32_from_int(arg2));
  * result = arg1 * arg2
  */
 static inline struct fixed31_32 dal_fixed31_32_mul_int(struct fixed31_32 arg1,
-						       int32_t arg2)
+						       int arg2)
 {
 	return dal_fixed31_32_mul(arg1,
 				  dal_fixed31_32_from_int(arg2));
  * result = arg1 / arg2
  */
 static inline struct fixed31_32 dal_fixed31_32_div_int(struct fixed31_32 arg1,
-						       int64_t arg2)
+						       long long arg2)
 {
 	return dal_fixed31_32_from_fraction(arg1.value,
 					    dal_fixed31_32_from_int(arg2).value);
  * @brief
  * result = floor(arg) := greatest integer lower than or equal to arg
  */
-int32_t dal_fixed31_32_floor(
+int dal_fixed31_32_floor(
 	struct fixed31_32 arg);
 /*
  * @brief
  * result = round(arg) := integer nearest to arg
  */
-int32_t dal_fixed31_32_round(
+int dal_fixed31_32_round(
 	struct fixed31_32 arg);
 /*
  * @brief
  * result = ceil(arg) := lowest integer greater than or equal to arg
  */
-int32_t dal_fixed31_32_ceil(
+int dal_fixed31_32_ceil(
 	struct fixed31_32 arg);
 /* the following two function are used in scaler hw programming to convert fixed
  * fractional
  */
-uint32_t dal_fixed31_32_u2d19(
+unsigned int dal_fixed31_32_u2d19(
 	struct fixed31_32 arg);
-uint32_t dal_fixed31_32_u0d19(
+unsigned int dal_fixed31_32_u0d19(
 	struct fixed31_32 arg);
-uint32_t dal_fixed31_32_clamp_u0d14(
+unsigned int dal_fixed31_32_clamp_u0d14(
 	struct fixed31_32 arg);
-uint32_t dal_fixed31_32_clamp_u0d10(
+unsigned int dal_fixed31_32_clamp_u0d10(
 	struct fixed31_32 arg);
-int32_t dal_fixed31_32_s4d19(
+int dal_fixed31_32_s4d19(
 	struct fixed31_32 arg);
 #endif

drivers/gpu/drm/amd/display/include/logger_types.h+32−32

 #include "os_types.h"
 #define MAX_NAME_LEN 32
-#define DC_LOG_ERROR(a, ...) dm_logger_write(DC_LOGGER, LOG_ERROR, a, ## __VA_ARGS__)
-#define DC_LOG_WARNING(a, ...) dm_logger_write(DC_LOGGER, LOG_WARNING, a, ## __VA_ARGS__)
-#define DC_LOG_DEBUG(a, ...) dm_logger_write(DC_LOGGER, LOG_DEBUG, a, ## __VA_ARGS__)
-#define DC_LOG_DC(a, ...) dm_logger_write(DC_LOGGER, LOG_DC, a, ## __VA_ARGS__)
-#define DC_LOG_DTN(a, ...) dm_logger_write(DC_LOGGER, LOG_DTN, a, ## __VA_ARGS__)
-#define DC_LOG_SURFACE(a, ...) dm_logger_write(DC_LOGGER, LOG_SURFACE, a, ## __VA_ARGS__)
-#define DC_LOG_HW_HOTPLUG(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_HOTPLUG, a, ## __VA_ARGS__)
-#define DC_LOG_HW_LINK_TRAINING(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_LINK_TRAINING, a, ## __VA_ARGS__)
-#define DC_LOG_HW_SET_MODE(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_SET_MODE, a, ## __VA_ARGS__)
-#define DC_LOG_HW_RESUME_S3(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_RESUME_S3, a, ## __VA_ARGS__)
-#define DC_LOG_HW_AUDIO(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_AUDIO, a, ## __VA_ARGS__)
-#define DC_LOG_HW_HPD_IRQ(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_HPD_IRQ, a, ## __VA_ARGS__)
-#define DC_LOG_MST(a, ...) dm_logger_write(DC_LOGGER, LOG_MST, a, ## __VA_ARGS__)
-#define DC_LOG_SCALER(a, ...) dm_logger_write(DC_LOGGER, LOG_SCALER, a, ## __VA_ARGS__)
-#define DC_LOG_BIOS(a, ...) dm_logger_write(DC_LOGGER, LOG_BIOS, a, ## __VA_ARGS__)
-#define DC_LOG_BANDWIDTH_CALCS(a, ...) dm_logger_write(DC_LOGGER, LOG_BANDWIDTH_CALCS, a, ## __VA_ARGS__)
-#define DC_LOG_BANDWIDTH_VALIDATION(a, ...) dm_logger_write(DC_LOGGER, LOG_BANDWIDTH_VALIDATION, a, ## __VA_ARGS__)
-#define DC_LOG_I2C_AUX(a, ...) dm_logger_write(DC_LOGGER, LOG_I2C_AUX, a, ## __VA_ARGS__)
-#define DC_LOG_SYNC(a, ...) dm_logger_write(DC_LOGGER, LOG_SYNC, a, ## __VA_ARGS__)
-#define DC_LOG_BACKLIGHT(a, ...) dm_logger_write(DC_LOGGER, LOG_BACKLIGHT, a, ## __VA_ARGS__)
-#define DC_LOG_FEATURE_OVERRIDE(a, ...) dm_logger_write(DC_LOGGER, LOG_FEATURE_OVERRIDE, a, ## __VA_ARGS__)
-#define DC_LOG_DETECTION_EDID_PARSER(a, ...) dm_logger_write(DC_LOGGER, LOG_DETECTION_EDID_PARSER, a, ## __VA_ARGS__)
-#define DC_LOG_DETECTION_DP_CAPS(a, ...) dm_logger_write(DC_LOGGER, LOG_DETECTION_DP_CAPS, a, ## __VA_ARGS__)
-#define DC_LOG_RESOURCE(a, ...) dm_logger_write(DC_LOGGER, LOG_RESOURCE, a, ## __VA_ARGS__)
-#define DC_LOG_DML(a, ...) dm_logger_write(DC_LOGGER, LOG_DML, a, ## __VA_ARGS__)
-#define DC_LOG_EVENT_MODE_SET(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_MODE_SET, a, ## __VA_ARGS__)
-#define DC_LOG_EVENT_DETECTION(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_DETECTION, a, ## __VA_ARGS__)
-#define DC_LOG_EVENT_LINK_TRAINING(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_LINK_TRAINING, a, ## __VA_ARGS__)
-#define DC_LOG_EVENT_LINK_LOSS(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_LINK_LOSS, a, ## __VA_ARGS__)
-#define DC_LOG_EVENT_UNDERFLOW(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_UNDERFLOW, a, ## __VA_ARGS__)
-#define DC_LOG_IF_TRACE(a, ...) dm_logger_write(DC_LOGGER, LOG_IF_TRACE, a, ## __VA_ARGS__)
-#define DC_LOG_PERF_TRACE(a, ...) dm_logger_write(DC_LOGGER, LOG_PERF_TRACE, a, ## __VA_ARGS__)
+#define DC_LOG_ERROR(...) DRM_ERROR(__VA_ARGS__)
+#define DC_LOG_WARNING(...) DRM_WARN(__VA_ARGS__)
+#define DC_LOG_DEBUG(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_DC(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_DTN(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_SURFACE(...) pr_debug("[SURFACE]:"__VA_ARGS__)
+#define DC_LOG_HW_HOTPLUG(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_HW_LINK_TRAINING(...) pr_debug("[HW_LINK_TRAINING]:"__VA_ARGS__)
+#define DC_LOG_HW_SET_MODE(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_HW_RESUME_S3(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_HW_AUDIO(...) pr_debug("[HW_AUDIO]:"__VA_ARGS__)
+#define DC_LOG_HW_HPD_IRQ(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_MST(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_SCALER(...) pr_debug("[SCALER]:"__VA_ARGS__)
+#define DC_LOG_BIOS(...) pr_debug("[BIOS]:"__VA_ARGS__)
+#define DC_LOG_BANDWIDTH_CALCS(...) pr_debug("[BANDWIDTH_CALCS]:"__VA_ARGS__)
+#define DC_LOG_BANDWIDTH_VALIDATION(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_I2C_AUX(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_SYNC(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_BACKLIGHT(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_FEATURE_OVERRIDE(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_DETECTION_EDID_PARSER(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_DETECTION_DP_CAPS(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_RESOURCE(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_DML(...) pr_debug("[DML]:"__VA_ARGS__)
+#define DC_LOG_EVENT_MODE_SET(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_EVENT_DETECTION(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_EVENT_LINK_TRAINING(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_EVENT_LINK_LOSS(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_EVENT_UNDERFLOW(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_IF_TRACE(...) pr_debug("[IF_TRACE]:"__VA_ARGS__)
+#define DC_LOG_PERF_TRACE(...) DRM_DEBUG_KMS(__VA_ARGS__)
 struct dal_logger;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c+337−45

@@ -185,14 +185,14 @@ struct dividers { · 184 unmodified lines
185		185
186	static void build_coefficients(struct gamma_coefficients *coefficients, bool is_2_4)	186	static void build_coefficients(struct gamma_coefficients *coefficients, bool is_2_4)
187	{	187	{
188	static const int32_t numerator01[] = { 31308, 180000};	188	static const int32_t numerator01[] = { 31308, 180000};
189	static const int32_t numerator02[] = { 12920, 4500};	189	static const int32_t numerator02[] = { 12920, 4500};
190	static const int32_t numerator03[] = { 55, 99};	190	static const int32_t numerator03[] = { 55, 99};
191	static const int32_t numerator04[] = { 55, 99};	191	static const int32_t numerator04[] = { 55, 99};
192	static const int32_t numerator05[] = { 2400, 2200};	192	static const int32_t numerator05[] = { 2400, 2200};
193		193
194	uint32_t i = 0;	194	uint32_t i = 0;
195	uint32_t index = is_2_4 == true ? 0:1;	195	uint32_t index = is_2_4 == true ? 0:1;
196		196
197	do {	197	do {
198	coefficients->a0[i] = dal_fixed31_32_from_fraction(	198	coefficients->a0[i] = dal_fixed31_32_from_fraction(
@@ -691,7 +691,7 @@ static void build_degamma(struct pwl_float_data_ex *curve, · 492 unmodified lines
691	}	691	}
692	}	692	}
693		693
694	static bool scale_gamma(struct pwl_float_data *pwl_rgb,	694	static void scale_gamma(struct pwl_float_data *pwl_rgb,
695	const struct dc_gamma *ramp,	695	const struct dc_gamma *ramp,
696	struct dividers dividers)	696	struct dividers dividers)
697	{	697	{
@@ -752,11 +752,9 @@ static bool scale_gamma(struct pwl_float_data *pwl_rgb, · 54 unmodified lines
752	dividers.divider3);	752	dividers.divider3);
753	rgb->b = dal_fixed31_32_mul(rgb_last->b,	753	rgb->b = dal_fixed31_32_mul(rgb_last->b,
754	dividers.divider3);	754	dividers.divider3);
755
756	return true;
757	}	755	}
758		756
759	static bool scale_gamma_dx(struct pwl_float_data *pwl_rgb,	757	static void scale_gamma_dx(struct pwl_float_data *pwl_rgb,
760	const struct dc_gamma *ramp,	758	const struct dc_gamma *ramp,
761	struct dividers dividers)	759	struct dividers dividers)
762	{	760	{
@@ -818,8 +816,71 @@ static bool scale_gamma_dx(struct pwl_float_data *pwl_rgb, · 55 unmodified lines
818	pwl_rgb[i-1].g, 2), pwl_rgb[i-2].g);	816	pwl_rgb[i-1].g, 2), pwl_rgb[i-2].g);
819	pwl_rgb[i].b = dal_fixed31_32_sub(dal_fixed31_32_mul_int(	817	pwl_rgb[i].b = dal_fixed31_32_sub(dal_fixed31_32_mul_int(
820	pwl_rgb[i-1].b, 2), pwl_rgb[i-2].b);	818	pwl_rgb[i-1].b, 2), pwl_rgb[i-2].b);
		819	}
821		820
822	return true;	821	/* todo: all these scale_gamma functions are inherently the same but
		822	* take different structures as params or different format for ramp
		823	* values. We could probably implement it in a more generic fashion
		824	*/
		825	static void scale_user_regamma_ramp(struct pwl_float_data *pwl_rgb,
		826	const struct regamma_ramp *ramp,
		827	struct dividers dividers)
		828	{
		829	unsigned short max_driver = 0xFFFF;
		830	unsigned short max_os = 0xFF00;
		831	unsigned short scaler = max_os;
		832	uint32_t i;
		833	struct pwl_float_data *rgb = pwl_rgb;
		834	struct pwl_float_data *rgb_last = rgb + GAMMA_RGB_256_ENTRIES - 1;
		835
		836	i = 0;
		837	do {
		838	if (ramp->gamma[i] > max_os \|\|
		839	ramp->gamma[i + 256] > max_os \|\|
		840	ramp->gamma[i + 512] > max_os) {
		841	scaler = max_driver;
		842	break;
		843	}
		844	i++;
		845	} while (i != GAMMA_RGB_256_ENTRIES);
		846
		847	i = 0;
		848	do {
		849	rgb->r = dal_fixed31_32_from_fraction(
		850	ramp->gamma[i], scaler);
		851	rgb->g = dal_fixed31_32_from_fraction(
		852	ramp->gamma[i + 256], scaler);
		853	rgb->b = dal_fixed31_32_from_fraction(
		854	ramp->gamma[i + 512], scaler);
		855
		856	++rgb;
		857	++i;
		858	} while (i != GAMMA_RGB_256_ENTRIES);
		859
		860	rgb->r = dal_fixed31_32_mul(rgb_last->r,
		861	dividers.divider1);
		862	rgb->g = dal_fixed31_32_mul(rgb_last->g,
		863	dividers.divider1);
		864	rgb->b = dal_fixed31_32_mul(rgb_last->b,
		865	dividers.divider1);
		866
		867	++rgb;
		868
		869	rgb->r = dal_fixed31_32_mul(rgb_last->r,
		870	dividers.divider2);
		871	rgb->g = dal_fixed31_32_mul(rgb_last->g,
		872	dividers.divider2);
		873	rgb->b = dal_fixed31_32_mul(rgb_last->b,
		874	dividers.divider2);
		875
		876	++rgb;
		877
		878	rgb->r = dal_fixed31_32_mul(rgb_last->r,
		879	dividers.divider3);
		880	rgb->g = dal_fixed31_32_mul(rgb_last->g,
		881	dividers.divider3);
		882	rgb->b = dal_fixed31_32_mul(rgb_last->b,
		883	dividers.divider3);
823	}	884	}
824		885
825	/*	886	/*
@@ -949,7 +1010,7 @@ static inline void copy_rgb_regamma_to_coordinates_x( · 123 unmodified lines
949	uint32_t i = 0;	1010	uint32_t i = 0;
950	const struct pwl_float_data_ex *rgb_regamma = rgb_ex;	1011	const struct pwl_float_data_ex *rgb_regamma = rgb_ex;
951		1012
952	while (i <= hw_points_num) {	1013	while (i <= hw_points_num + 1) {
953	coords->regamma_y_red = rgb_regamma->r;	1014	coords->regamma_y_red = rgb_regamma->r;
954	coords->regamma_y_green = rgb_regamma->g;	1015	coords->regamma_y_green = rgb_regamma->g;
955	coords->regamma_y_blue = rgb_regamma->b;	1016	coords->regamma_y_blue = rgb_regamma->b;
@@ -1002,6 +1063,102 @@ static bool calculate_interpolated_hardware_curve( · 46 unmodified lines
1002	return true;	1063	return true;
1003	}	1064	}
1004		1065
		1066	/* The "old" interpolation uses a complicated scheme to build an array of
		1067	* coefficients while also using an array of 0-255 normalized to 0-1
		1068	* Then there's another loop using both of the above + new scaled user ramp
		1069	* and we concatenate them. It also searches for points of interpolation and
		1070	* uses enums for positions.
		1071	*
		1072	* This function uses a different approach:
		1073	* user ramp is always applied on X with 0/255, 1/255, 2/255, ..., 255/255
		1074	* To find index for hwX , we notice the following:
		1075	* i/255 <= hwX < (i+1)/255 <=> i <= 255*hwX < i+1
		1076	* See apply_lut_1d which is the same principle, but on 4K entry 1D LUT
		1077	*
		1078	* Once the index is known, combined Y is simply:
		1079	* user_ramp(index) + (hwX-index/255)*(user_ramp(index+1) - user_ramp(index)
		1080	*
		1081	* We should switch to this method in all cases, it's simpler and faster
		1082	* ToDo one day - for now this only applies to ADL regamma to avoid regression
		1083	* for regular use cases (sRGB and PQ)
		1084	*/
		1085	static void interpolate_user_regamma(uint32_t hw_points_num,
		1086	struct pwl_float_data *rgb_user,
		1087	bool apply_degamma,
		1088	struct dc_transfer_func_distributed_points *tf_pts)
		1089	{
		1090	uint32_t i;
		1091	uint32_t color = 0;
		1092	int32_t index;
		1093	int32_t index_next;
		1094	struct fixed31_32 *tf_point;
		1095	struct fixed31_32 hw_x;
		1096	struct fixed31_32 norm_factor =
		1097	dal_fixed31_32_from_int_nonconst(255);
		1098	struct fixed31_32 norm_x;
		1099	struct fixed31_32 index_f;
		1100	struct fixed31_32 lut1;
		1101	struct fixed31_32 lut2;
		1102	struct fixed31_32 delta_lut;
		1103	struct fixed31_32 delta_index;
		1104
		1105	i = 0;
		1106	/* fixed_pt library has problems handling too small values */
		1107	while (i != 32) {
		1108	tf_pts->red[i] = dal_fixed31_32_zero;
		1109	tf_pts->green[i] = dal_fixed31_32_zero;
		1110	tf_pts->blue[i] = dal_fixed31_32_zero;
		1111	++i;
		1112	}
		1113	while (i <= hw_points_num + 1) {
		1114	for (color = 0; color < 3; color++) {
		1115	if (color == 0)
		1116	tf_point = &tf_pts->red[i];
		1117	else if (color == 1)
		1118	tf_point = &tf_pts->green[i];
		1119	else
		1120	tf_point = &tf_pts->blue[i];
		1121
		1122	if (apply_degamma) {
		1123	if (color == 0)
		1124	hw_x = coordinates_x[i].regamma_y_red;
		1125	else if (color == 1)
		1126	hw_x = coordinates_x[i].regamma_y_green;
		1127	else
		1128	hw_x = coordinates_x[i].regamma_y_blue;
		1129	} else
		1130	hw_x = coordinates_x[i].x;
		1131
		1132	norm_x = dal_fixed31_32_mul(norm_factor, hw_x);
		1133	index = dal_fixed31_32_floor(norm_x);
		1134	if (index < 0 \|\| index > 255)
		1135	continue;
		1136
		1137	index_f = dal_fixed31_32_from_int_nonconst(index);
		1138	index_next = (index == 255) ? index : index + 1;
		1139
		1140	if (color == 0) {
		1141	lut1 = rgb_user[index].r;
		1142	lut2 = rgb_user[index_next].r;
		1143	} else if (color == 1) {
		1144	lut1 = rgb_user[index].g;
		1145	lut2 = rgb_user[index_next].g;
		1146	} else {
		1147	lut1 = rgb_user[index].b;
		1148	lut2 = rgb_user[index_next].b;
		1149	}
		1150
		1151	// we have everything now, so interpolate
		1152	delta_lut = dal_fixed31_32_sub(lut2, lut1);
		1153	delta_index = dal_fixed31_32_sub(norm_x, index_f);
		1154
		1155	*tf_point = dal_fixed31_32_add(lut1,
		1156	dal_fixed31_32_mul(delta_index, delta_lut));
		1157	}
		1158	++i;
		1159	}
		1160	}
		1161
1005	static void build_new_custom_resulted_curve(	1162	static void build_new_custom_resulted_curve(
1006	uint32_t hw_points_num,	1163	uint32_t hw_points_num,
1007	struct dc_transfer_func_distributed_points *tf_pts)	1164	struct dc_transfer_func_distributed_points *tf_pts)
@@ -1025,6 +1182,29 @@ static void build_new_custom_resulted_curve( · 17 unmodified lines
1025	}	1182	}
1026	}	1183	}
1027		1184
		1185	static void apply_degamma_for_user_regamma(struct pwl_float_data_ex *rgb_regamma,
		1186	uint32_t hw_points_num)
		1187	{
		1188	uint32_t i;
		1189
		1190	struct gamma_coefficients coeff;
		1191	struct pwl_float_data_ex *rgb = rgb_regamma;
		1192	const struct hw_x_point *coord_x = coordinates_x;
		1193
		1194	build_coefficients(&coeff, true);
		1195
		1196	i = 0;
		1197	while (i != hw_points_num + 1) {
		1198	rgb->r = translate_from_linear_space_ex(
		1199	coord_x->x, &coeff, 0);
		1200	rgb->g = rgb->r;
		1201	rgb->b = rgb->r;
		1202	++coord_x;
		1203	++rgb;
		1204	++i;
		1205	}
		1206	}
		1207
1028	static bool map_regamma_hw_to_x_user(	1208	static bool map_regamma_hw_to_x_user(
1029	const struct dc_gamma *ramp,	1209	const struct dc_gamma *ramp,
1030	struct pixel_gamma_point *coeff128,	1210	struct pixel_gamma_point *coeff128,
@@ -1062,6 +1242,7 @@ static bool map_regamma_hw_to_x_user( · 31 unmodified lines
1062	}	1242	}
1063	}	1243	}
1064		1244
		1245	/* this should be named differently, all it does is clamp to 0-1 */
1065	build_new_custom_resulted_curve(hw_points_num, tf_pts);	1246	build_new_custom_resulted_curve(hw_points_num, tf_pts);
1066		1247
1067	return true;	1248	return true;
@@ -1093,19 +1274,19 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf, · 25 unmodified lines
1093		1274
1094	output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;	1275	output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
1095		1276
1096	rgb_user = kzalloc(sizeof(rgb_user) (ramp->num_entries + _EXTRA_POINTS),	1277	rgb_user = kvzalloc(sizeof(rgb_user) (ramp->num_entries + _EXTRA_POINTS),
1097	GFP_KERNEL);	1278	GFP_KERNEL);
1098	if (!rgb_user)	1279	if (!rgb_user)
1099	goto rgb_user_alloc_fail;	1280	goto rgb_user_alloc_fail;
1100	rgb_regamma = kzalloc(sizeof(rgb_regamma) (MAX_HW_POINTS + _EXTRA_POINTS),	1281	rgb_regamma = kvzalloc(sizeof(rgb_regamma) (MAX_HW_POINTS + _EXTRA_POINTS),
1101	GFP_KERNEL);	1282	GFP_KERNEL);
1102	if (!rgb_regamma)	1283	if (!rgb_regamma)
1103	goto rgb_regamma_alloc_fail;	1284	goto rgb_regamma_alloc_fail;
1104	axix_x = kzalloc(sizeof(axix_x) (ramp->num_entries + 3),	1285	axix_x = kvzalloc(sizeof(axix_x) (ramp->num_entries + 3),
1105	GFP_KERNEL);	1286	GFP_KERNEL);
1106	if (!axix_x)	1287	if (!axix_x)
1107	goto axix_x_alloc_fail;	1288	goto axix_x_alloc_fail;
1108	coeff = kzalloc(sizeof(coeff) (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);	1289	coeff = kvzalloc(sizeof(coeff) (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1109	if (!coeff)	1290	if (!coeff)
1110	goto coeff_alloc_fail;	1291	goto coeff_alloc_fail;
1111		1292
@@ -1157,10 +1338,117 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf, · 45 unmodified lines
1157		1338
1158	ret = true;	1339	ret = true;
1159		1340
1160	kfree(coeff);	1341	kvfree(coeff);
1161	coeff_alloc_fail:	1342	coeff_alloc_fail:
1162	kfree(axix_x);	1343	kvfree(axix_x);
1163	axix_x_alloc_fail:	1344	axix_x_alloc_fail:
		1345	kvfree(rgb_regamma);
		1346	rgb_regamma_alloc_fail:
		1347	kvfree(rgb_user);
		1348	rgb_user_alloc_fail:
		1349	return ret;
		1350	}
		1351
		1352	bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,
		1353	const struct regamma_lut *regamma)
		1354	{
		1355	struct gamma_coefficients coeff;
		1356	const struct hw_x_point *coord_x = coordinates_x;
		1357	uint32_t i = 0;
		1358
		1359	do {
		1360	coeff.a0[i] = dal_fixed31_32_from_fraction(
		1361	regamma->coeff.A0[i], 10000000);
		1362	coeff.a1[i] = dal_fixed31_32_from_fraction(
		1363	regamma->coeff.A1[i], 1000);
		1364	coeff.a2[i] = dal_fixed31_32_from_fraction(
		1365	regamma->coeff.A2[i], 1000);
		1366	coeff.a3[i] = dal_fixed31_32_from_fraction(
		1367	regamma->coeff.A3[i], 1000);
		1368	coeff.user_gamma[i] = dal_fixed31_32_from_fraction(
		1369	regamma->coeff.gamma[i], 1000);
		1370
		1371	++i;
		1372	} while (i != 3);
		1373
		1374	i = 0;
		1375	/* fixed_pt library has problems handling too small values */
		1376	while (i != 32) {
		1377	output_tf->tf_pts.red[i] = dal_fixed31_32_zero;
		1378	output_tf->tf_pts.green[i] = dal_fixed31_32_zero;
		1379	output_tf->tf_pts.blue[i] = dal_fixed31_32_zero;
		1380	++coord_x;
		1381	++i;
		1382	}
		1383	while (i != MAX_HW_POINTS + 1) {
		1384	output_tf->tf_pts.red[i] = translate_from_linear_space_ex(
		1385	coord_x->x, &coeff, 0);
		1386	output_tf->tf_pts.green[i] = translate_from_linear_space_ex(
		1387	coord_x->x, &coeff, 1);
		1388	output_tf->tf_pts.blue[i] = translate_from_linear_space_ex(
		1389	coord_x->x, &coeff, 2);
		1390	++coord_x;
		1391	++i;
		1392	}
		1393
		1394	// this function just clamps output to 0-1
		1395	build_new_custom_resulted_curve(MAX_HW_POINTS, &output_tf->tf_pts);
		1396	output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
		1397
		1398	return true;
		1399	}
		1400
		1401	bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf,
		1402	const struct regamma_lut *regamma)
		1403	{
		1404	struct dc_transfer_func_distributed_points *tf_pts = &output_tf->tf_pts;
		1405	struct dividers dividers;
		1406
		1407	struct pwl_float_data *rgb_user = NULL;
		1408	struct pwl_float_data_ex *rgb_regamma = NULL;
		1409	bool ret = false;
		1410
		1411	if (regamma == NULL)
		1412	return false;
		1413
		1414	output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
		1415
		1416	rgb_user = kzalloc(sizeof(rgb_user) (GAMMA_RGB_256_ENTRIES + _EXTRA_POINTS),
		1417	GFP_KERNEL);
		1418	if (!rgb_user)
		1419	goto rgb_user_alloc_fail;
		1420
		1421	rgb_regamma = kzalloc(sizeof(rgb_regamma) (MAX_HW_POINTS + _EXTRA_POINTS),
		1422	GFP_KERNEL);
		1423	if (!rgb_regamma)
		1424	goto rgb_regamma_alloc_fail;
		1425
		1426	dividers.divider1 = dal_fixed31_32_from_fraction(3, 2);
		1427	dividers.divider2 = dal_fixed31_32_from_int(2);
		1428	dividers.divider3 = dal_fixed31_32_from_fraction(5, 2);
		1429
		1430	scale_user_regamma_ramp(rgb_user, &regamma->ramp, dividers);
		1431
		1432	if (regamma->flags.bits.applyDegamma == 1) {
		1433	apply_degamma_for_user_regamma(rgb_regamma, MAX_HW_POINTS);
		1434	copy_rgb_regamma_to_coordinates_x(coordinates_x,
		1435	MAX_HW_POINTS, rgb_regamma);
		1436	}
		1437
		1438	interpolate_user_regamma(MAX_HW_POINTS, rgb_user,
		1439	regamma->flags.bits.applyDegamma, tf_pts);
		1440
		1441	// no custom HDR curves!
		1442	tf_pts->end_exponent = 0;
		1443	tf_pts->x_point_at_y1_red = 1;
		1444	tf_pts->x_point_at_y1_green = 1;
		1445	tf_pts->x_point_at_y1_blue = 1;
		1446
		1447	// this function just clamps output to 0-1
		1448	build_new_custom_resulted_curve(MAX_HW_POINTS, tf_pts);
		1449
		1450	ret = true;
		1451
1164	kfree(rgb_regamma);	1452	kfree(rgb_regamma);
1165	rgb_regamma_alloc_fail:	1453	rgb_regamma_alloc_fail:
1166	kfree(rgb_user);	1454	kfree(rgb_user);
@@ -1192,19 +1480,19 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf, · 25 unmodified lines
1192		1480
1193	input_tf->type = TF_TYPE_DISTRIBUTED_POINTS;	1481	input_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
1194		1482
1195	rgb_user = kzalloc(sizeof(rgb_user) (ramp->num_entries + _EXTRA_POINTS),	1483	rgb_user = kvzalloc(sizeof(rgb_user) (ramp->num_entries + _EXTRA_POINTS),
1196	GFP_KERNEL);	1484	GFP_KERNEL);
1197	if (!rgb_user)	1485	if (!rgb_user)
1198	goto rgb_user_alloc_fail;	1486	goto rgb_user_alloc_fail;
1199	curve = kzalloc(sizeof(curve) (MAX_HW_POINTS + _EXTRA_POINTS),	1487	curve = kvzalloc(sizeof(curve) (MAX_HW_POINTS + _EXTRA_POINTS),
1200	GFP_KERNEL);	1488	GFP_KERNEL);
1201	if (!curve)	1489	if (!curve)
1202	goto curve_alloc_fail;	1490	goto curve_alloc_fail;
1203	axix_x = kzalloc(sizeof(axix_x) (ramp->num_entries + _EXTRA_POINTS),	1491	axix_x = kvzalloc(sizeof(axix_x) (ramp->num_entries + _EXTRA_POINTS),
1204	GFP_KERNEL);	1492	GFP_KERNEL);
1205	if (!axix_x)	1493	if (!axix_x)
1206	goto axix_x_alloc_fail;	1494	goto axix_x_alloc_fail;
1207	coeff = kzalloc(sizeof(coeff) (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);	1495	coeff = kvzalloc(sizeof(coeff) (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1208	if (!coeff)	1496	if (!coeff)
1209	goto coeff_alloc_fail;	1497	goto coeff_alloc_fail;
1210		1498
@@ -1246,13 +1534,13 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf, · 35 unmodified lines
1246		1534
1247	ret = true;	1535	ret = true;
1248		1536
1249	kfree(coeff);	1537	kvfree(coeff);
1250	coeff_alloc_fail:	1538	coeff_alloc_fail:
1251	kfree(axix_x);	1539	kvfree(axix_x);
1252	axix_x_alloc_fail:	1540	axix_x_alloc_fail:
1253	kfree(curve);	1541	kvfree(curve);
1254	curve_alloc_fail:	1542	curve_alloc_fail:
1255	kfree(rgb_user);	1543	kvfree(rgb_user);
1256	rgb_user_alloc_fail:	1544	rgb_user_alloc_fail:
1257		1545
1258	return ret;	1546	return ret;
@@ -1281,8 +1569,9 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans, · 22 unmodified lines
1281	}	1569	}
1282	ret = true;	1570	ret = true;
1283	} else if (trans == TRANSFER_FUNCTION_PQ) {	1571	} else if (trans == TRANSFER_FUNCTION_PQ) {
1284	rgb_regamma = kzalloc(sizeof(rgb_regamma) (MAX_HW_POINTS +	1572	rgb_regamma = kvzalloc(sizeof(rgb_regamma)
1285	_EXTRA_POINTS), GFP_KERNEL);	1573	(MAX_HW_POINTS + _EXTRA_POINTS),
		1574	GFP_KERNEL);
1286	if (!rgb_regamma)	1575	if (!rgb_regamma)
1287	goto rgb_regamma_alloc_fail;	1576	goto rgb_regamma_alloc_fail;
1288	points->end_exponent = 7;	1577	points->end_exponent = 7;
@@ -1302,11 +1591,12 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans, · 13 unmodified lines
1302	}	1591	}
1303	ret = true;	1592	ret = true;
1304		1593
1305	kfree(rgb_regamma);	1594	kvfree(rgb_regamma);
1306	} else if (trans == TRANSFER_FUNCTION_SRGB \|\|	1595	} else if (trans == TRANSFER_FUNCTION_SRGB \|\|
1307	trans == TRANSFER_FUNCTION_BT709) {	1596	trans == TRANSFER_FUNCTION_BT709) {
1308	rgb_regamma = kzalloc(sizeof(rgb_regamma) (MAX_HW_POINTS +	1597	rgb_regamma = kvzalloc(sizeof(rgb_regamma)
1309	_EXTRA_POINTS), GFP_KERNEL);	1598	(MAX_HW_POINTS + _EXTRA_POINTS),
		1599	GFP_KERNEL);
1310	if (!rgb_regamma)	1600	if (!rgb_regamma)
1311	goto rgb_regamma_alloc_fail;	1601	goto rgb_regamma_alloc_fail;
1312	points->end_exponent = 0;	1602	points->end_exponent = 0;
@@ -1324,7 +1614,7 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans, · 11 unmodified lines
1324	}	1614	}
1325	ret = true;	1615	ret = true;
1326		1616
1327	kfree(rgb_regamma);	1617	kvfree(rgb_regamma);
1328	}	1618	}
1329	rgb_regamma_alloc_fail:	1619	rgb_regamma_alloc_fail:
1330	return ret;	1620	return ret;
@@ -1348,8 +1638,9 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans, · 17 unmodified lines
1348	}	1638	}
1349	ret = true;	1639	ret = true;
1350	} else if (trans == TRANSFER_FUNCTION_PQ) {	1640	} else if (trans == TRANSFER_FUNCTION_PQ) {
1351	rgb_degamma = kzalloc(sizeof(rgb_degamma) (MAX_HW_POINTS +	1641	rgb_degamma = kvzalloc(sizeof(rgb_degamma)
1352	_EXTRA_POINTS), GFP_KERNEL);	1642	(MAX_HW_POINTS + _EXTRA_POINTS),
		1643	GFP_KERNEL);
1353	if (!rgb_degamma)	1644	if (!rgb_degamma)
1354	goto rgb_degamma_alloc_fail;	1645	goto rgb_degamma_alloc_fail;
1355		1646
@@ -1364,11 +1655,12 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans, · 8 unmodified lines
1364	}	1655	}
1365	ret = true;	1656	ret = true;
1366		1657
1367	kfree(rgb_degamma);	1658	kvfree(rgb_degamma);
1368	} else if (trans == TRANSFER_FUNCTION_SRGB \|\|	1659	} else if (trans == TRANSFER_FUNCTION_SRGB \|\|
1369	trans == TRANSFER_FUNCTION_BT709) {	1660	trans == TRANSFER_FUNCTION_BT709) {
1370	rgb_degamma = kzalloc(sizeof(rgb_degamma) (MAX_HW_POINTS +	1661	rgb_degamma = kvzalloc(sizeof(rgb_degamma)
1371	_EXTRA_POINTS), GFP_KERNEL);	1662	(MAX_HW_POINTS + _EXTRA_POINTS),
		1663	GFP_KERNEL);
1372	if (!rgb_degamma)	1664	if (!rgb_degamma)
1373	goto rgb_degamma_alloc_fail;	1665	goto rgb_degamma_alloc_fail;
1374		1666
@@ -1382,7 +1674,7 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans, · 7 unmodified lines
1382	}	1674	}
1383	ret = true;	1675	ret = true;
1384		1676
1385	kfree(rgb_degamma);	1677	kvfree(rgb_degamma);
1386	}	1678	}
1387	points->end_exponent = 0;	1679	points->end_exponent = 0;
1388	points->x_point_at_y1_red = 1;	1680	points->x_point_at_y1_red = 1;

drivers/gpu/drm/amd/display/modules/color/color_gamma.h+47−1

@@ -32,6 +32,47 @@ struct dc_transfer_func_distributed_points; · 31 unmodified lines
32	struct dc_rgb_fixed;	32	struct dc_rgb_fixed;
33	enum dc_transfer_func_predefined;	33	enum dc_transfer_func_predefined;
34		34
		35	/* For SetRegamma ADL interface support
		36	* Must match escape type
		37	*/
		38	union regamma_flags {
		39	unsigned int raw;
		40	struct {
		41	unsigned int gammaRampArray :1; // RegammaRamp is in use
		42	unsigned int gammaFromEdid :1; //gamma from edid is in use
		43	unsigned int gammaFromEdidEx :1; //gamma from edid is in use , but only for Display Id 1.2
		44	unsigned int gammaFromUser :1; //user custom gamma is used
		45	unsigned int coeffFromUser :1; //coeff. A0-A3 from user is in use
		46	unsigned int coeffFromEdid :1; //coeff. A0-A3 from edid is in use
		47	unsigned int applyDegamma :1; //flag for additional degamma correction in driver
		48	unsigned int gammaPredefinedSRGB :1; //flag for SRGB gamma
		49	unsigned int gammaPredefinedPQ :1; //flag for PQ gamma
		50	unsigned int gammaPredefinedPQ2084Interim :1; //flag for PQ gamma, lower max nits
		51	unsigned int gammaPredefined36 :1; //flag for 3.6 gamma
		52	unsigned int gammaPredefinedReset :1; //flag to return to previous gamma
		53	} bits;
		54	};
		55
		56	struct regamma_ramp {
		57	unsigned short gamma[256*3]; // gamma ramp packed in same way as OS windows ,r , g & b
		58	};
		59
		60	struct regamma_coeff {
		61	int gamma[3];
		62	int A0[3];
		63	int A1[3];
		64	int A2[3];
		65	int A3[3];
		66	};
		67
		68	struct regamma_lut {
		69	union regamma_flags flags;
		70	union {
		71	struct regamma_ramp ramp;
		72	struct regamma_coeff coeff;
		73	};
		74	};
		75
35	void setup_x_points_distribution(void);	76	void setup_x_points_distribution(void);
36	void precompute_pq(void);	77	void precompute_pq(void);
37	void precompute_de_pq(void);	78	void precompute_de_pq(void);
@@ -45,9 +86,14 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *output_tf, · 7 unmodified lines
45	bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,	86	bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
46	struct dc_transfer_func_distributed_points *points);	87	struct dc_transfer_func_distributed_points *points);
47		88
48	bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,	89	bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
49	struct dc_transfer_func_distributed_points *points);	90	struct dc_transfer_func_distributed_points *points);
50		91
		92	bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,
		93	const struct regamma_lut *regamma);
		94
		95	bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf,
		96	const struct regamma_lut *regamma);
51		97
52		98
53	#endif /* COLOR_MOD_COLOR_GAMMA_H_ */	99	#endif /* COLOR_MOD_COLOR_GAMMA_H_ */

drivers/gpu/drm/amd/display/modules/stats/stats.c+43−22

 			&reg_data, sizeof(unsigned int), &flag))
 		core_stats->enabled = reg_data;
-	core_stats->entries = DAL_STATS_ENTRIES_REGKEY_DEFAULT;
+	if (core_stats->enabled) {
-	if (dm_read_persistent_data(dc->ctx, NULL, NULL,
+		core_stats->entries = DAL_STATS_ENTRIES_REGKEY_DEFAULT;
-			DAL_STATS_ENTRIES_REGKEY,
+		if (dm_read_persistent_data(dc->ctx, NULL, NULL,
-			&reg_data, sizeof(unsigned int), &flag)) {
+				DAL_STATS_ENTRIES_REGKEY,
-		if (reg_data > DAL_STATS_ENTRIES_REGKEY_MAX)
+				&reg_data, sizeof(unsigned int), &flag)) {
-			core_stats->entries = DAL_STATS_ENTRIES_REGKEY_MAX;
+			if (reg_data > DAL_STATS_ENTRIES_REGKEY_MAX)
-		else
+				core_stats->entries = DAL_STATS_ENTRIES_REGKEY_MAX;
-			core_stats->entries = reg_data;
+			else
-	}
+				core_stats->entries = reg_data;
+		}
-	core_stats->time = kzalloc(sizeof(struct stats_time_cache) * core_stats->entries,
+		core_stats->time = kzalloc(sizeof(struct stats_time_cache) * core_stats->entries,
-					GFP_KERNEL);
+						GFP_KERNEL);
+	} else {
+		core_stats->entries = 0;
+	}
 	if (core_stats->time == NULL)
 		goto fail_construct;
 		for (int i = 0; i < core_stats->index && i < core_stats->entries; i++) {
 			dm_logger_write(logger, LOG_PROFILING,
-					"%u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u\n",
+					"%u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u",
 					time[i].render_time_in_us,
 					time[i].avg_render_time_in_us_last_ten,
 					time[i].min_window,
 	memset(core_stats->time, 0,
 		sizeof(struct stats_time_cache) * core_stats->entries);
-	core_stats->index = 0;
+	core_stats->index = 1;
 }
 void mod_stats_update_flip(struct mod_stats *mod_stats,
 	time[index].flip_timestamp_in_ns = timestamp_in_ns;
 	time[index].render_time_in_us =
-		timestamp_in_ns - time[index - 1].flip_timestamp_in_ns;
+		(timestamp_in_ns - time[index - 1].flip_timestamp_in_ns) / 1000;
 	if (index >= 10) {
 		for (unsigned int i = 0; i < 10; i++)
 	if (time[index].num_vsync_between_flips > 0)
 		time[index].vsync_to_flip_time_in_us =
-			timestamp_in_ns - time[index].vupdate_timestamp_in_ns;
+			(timestamp_in_ns -
+				time[index].vupdate_timestamp_in_ns) / 1000;
 	else
 		time[index].vsync_to_flip_time_in_us =
-			timestamp_in_ns - time[index - 1].vupdate_timestamp_in_ns;
+			(timestamp_in_ns -
+				time[index - 1].vupdate_timestamp_in_ns) / 1000;
 	core_stats->index++;
 }
 	struct core_stats *core_stats = NULL;
 	struct stats_time_cache *time = NULL;
 	unsigned int index = 0;
+	unsigned int num_vsyncs = 0;
+	unsigned int prev_vsync_in_ns = 0;
 	if (mod_stats == NULL)
 		return;
 	time = core_stats->time;
 	index = core_stats->index;
+	num_vsyncs = time[index].num_vsync_between_flips;
+	if (num_vsyncs < MOD_STATS_NUM_VSYNCS) {
+		if (num_vsyncs == 0) {
+			prev_vsync_in_ns =
+				time[index - 1].vupdate_timestamp_in_ns;
+			time[index].flip_to_vsync_time_in_us =
+				(timestamp_in_ns -
+					time[index - 1].flip_timestamp_in_ns) /
+					1000;
+		} else {
+			prev_vsync_in_ns =
+				time[index].vupdate_timestamp_in_ns;
+		}
-	time[index].vupdate_timestamp_in_ns = timestamp_in_ns;
+		time[index].v_sync_time_in_us[num_vsyncs] =
-	if (time[index].num_vsync_between_flips < MOD_STATS_NUM_VSYNCS)
+			(timestamp_in_ns - prev_vsync_in_ns) / 1000;
-		time[index].v_sync_time_in_us[time[index].num_vsync_between_flips] =
+	}
-			timestamp_in_ns - time[index - 1].vupdate_timestamp_in_ns;
-	time[index].flip_to_vsync_time_in_us =
-		timestamp_in_ns - time[index - 1].flip_timestamp_in_ns;
+	time[index].vupdate_timestamp_in_ns = timestamp_in_ns;
 	time[index].num_vsync_between_flips++;
 }

drivers/gpu/drm/amd/include/amd_shared.h+20−0

@@ -109,6 +109,26 @@ enum amd_powergating_state { · 108 unmodified lines
109	#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)	109	#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
110	#define AMD_PG_SUPPORT_MMHUB (1 << 13)	110	#define AMD_PG_SUPPORT_MMHUB (1 << 13)
111		111
		112	enum PP_FEATURE_MASK {
		113	PP_SCLK_DPM_MASK = 0x1,
		114	PP_MCLK_DPM_MASK = 0x2,
		115	PP_PCIE_DPM_MASK = 0x4,
		116	PP_SCLK_DEEP_SLEEP_MASK = 0x8,
		117	PP_POWER_CONTAINMENT_MASK = 0x10,
		118	PP_UVD_HANDSHAKE_MASK = 0x20,
		119	PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
		120	PP_VBI_TIME_SUPPORT_MASK = 0x80,
		121	PP_ULV_MASK = 0x100,
		122	PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
		123	PP_CLOCK_STRETCH_MASK = 0x400,
		124	PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
		125	PP_SOCCLK_DPM_MASK = 0x1000,
		126	PP_DCEFCLK_DPM_MASK = 0x2000,
		127	PP_OVERDRIVE_MASK = 0x4000,
		128	PP_GFXOFF_MASK = 0x8000,
		129	PP_ACG_MASK = 0x10000,
		130	};
		131
112	struct amd_ip_funcs {	132	struct amd_ip_funcs {
113	/* Name of IP block */	133	/* Name of IP block */
114	char *name;	134	char *name;

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h+16−3

@@ -3895,6 +3895,10 @@ · 3894 unmodified lines
3895	#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2	3895	#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
3896	#define mmCM0_CM_MEM_PWR_STATUS 0x0d33	3896	#define mmCM0_CM_MEM_PWR_STATUS 0x0d33
3897	#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2	3897	#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
		3898	#define mmCM0_CM_TEST_DEBUG_INDEX 0x0d35
		3899	#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
		3900	#define mmCM0_CM_TEST_DEBUG_DATA 0x0d36
		3901	#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
3898		3902
3899		3903
3900	// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec	3904	// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
@@ -4367,7 +4371,10 @@ · 466 unmodified lines
4367	#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2	4371	#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
4368	#define mmCM1_CM_MEM_PWR_STATUS 0x0e4e	4372	#define mmCM1_CM_MEM_PWR_STATUS 0x0e4e
4369	#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2	4373	#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
4370		4374	#define mmCM1_CM_TEST_DEBUG_INDEX 0x0e50
		4375	#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
		4376	#define mmCM1_CM_TEST_DEBUG_DATA 0x0e51
		4377	#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
4371		4378
4372	// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec	4379	// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
4373	// base address: 0x399c	4380	// base address: 0x399c
@@ -4839,7 +4846,10 @@ · 465 unmodified lines
4839	#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2	4846	#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
4840	#define mmCM2_CM_MEM_PWR_STATUS 0x0f69	4847	#define mmCM2_CM_MEM_PWR_STATUS 0x0f69
4841	#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2	4848	#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
4842		4849	#define mmCM2_CM_TEST_DEBUG_INDEX 0x0f6b
		4850	#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
		4851	#define mmCM2_CM_TEST_DEBUG_DATA 0x0f6c
		4852	#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
4843		4853
4844	// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec	4854	// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
4845	// base address: 0x3e08	4855	// base address: 0x3e08
@@ -5311,7 +5321,10 @@ · 465 unmodified lines
5311	#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2	5321	#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
5312	#define mmCM3_CM_MEM_PWR_STATUS 0x1084	5322	#define mmCM3_CM_MEM_PWR_STATUS 0x1084
5313	#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2	5323	#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
5314		5324	#define mmCM3_CM_TEST_DEBUG_INDEX 0x1086
		5325	#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
		5326	#define mmCM3_CM_TEST_DEBUG_DATA 0x1087
		5327	#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
5315		5328
5316	// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec	5329	// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
5317	// base address: 0x4274	5330	// base address: 0x4274

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h+8−0

@@ -14049,6 +14049,14 @@ · 14048 unmodified lines
14049	#define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2	14049	#define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2
14050	#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L	14050	#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
14051	#define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL	14051	#define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL
		14052	//CM0_CM_TEST_DEBUG_INDEX
		14053	#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
		14054	#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
		14055	#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
		14056	#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
		14057	//CM0_CM_TEST_DEBUG_DATA
		14058	#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
		14059	#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
14052		14060
14053		14061
14054	// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec	14062	// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec

drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_default.h+26−0

@@ -0,0 +1,26 @@
	1	/*
	2	* Copyright (C) 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included
	12	* in all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	15	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
	18	* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	19	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*/
	21	#ifndef _df_1_7_DEFAULT_HEADER
	22	#define _df_1_7_DEFAULT_HEADER
	23
	24	#define mmFabricConfigAccessControl_DEFAULT 0x00000000
	25
	26	#endif

drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h+33−0

@@ -0,0 +1,33 @@
	1	/*
	2	* Copyright (C) 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included
	12	* in all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	15	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
	18	* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	19	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*/
	21	#ifndef _df_1_7_OFFSET_HEADER
	22	#define _df_1_7_OFFSET_HEADER
	23
	24	#define mmFabricConfigAccessControl 0x0410
	25	#define mmFabricConfigAccessControl_BASE_IDX 0
	26
	27	#define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc
	28	#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0
	29
	30	#define mmDF_CS_AON0_DramBaseAddress0 0x0044
	31	#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
	32
	33	#endif

drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h+48−0

@@ -0,0 +1,48 @@
	1	/*
	2	* Copyright (C) 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included
	12	* in all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	15	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
	18	* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	19	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*/
	21	#ifndef _df_1_7_SH_MASK_HEADER
	22	#define _df_1_7_SH_MASK_HEADER
	23
	24	/* FabricConfigAccessControl */
	25	#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0
	26	#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
	27	#define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10
	28	#define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L
	29	#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L
	30	#define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L
	31
	32	/* DF_PIE_AON0_DfGlobalClkGater */
	33	#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
	34	#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
	35
	36	/* DF_CS_AON0_DramBaseAddress0 */
	37	#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
	38	#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
	39	#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
	40	#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
	41	#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
	42	#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
	43	#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
	44	#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
	45	#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
	46	#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
	47
	48	#endif

drivers/gpu/drm/amd/include/atombios.h+7−0

@@ -632,6 +632,13 @@ typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 · 631 unmodified lines
632	ULONG ulReserved;	632	ULONG ulReserved;
633	}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2;	633	}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2;
634		634
		635	typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3
		636	{
		637	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock;
		638	USHORT usMclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536
		639	USHORT usMclk_fcw_int; //integer divider of fcwc
		640	}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3;
		641
635	//Input parameter of DynamicMemorySettingsTable	642	//Input parameter of DynamicMemorySettingsTable
636	//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM	643	//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM
637	typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER	644	typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER

drivers/gpu/drm/amd/include/atomfirmware.h+168−2

@@ -501,6 +501,32 @@ enum atom_cooling_solution_id{ · 500 unmodified lines
501	LIQUID_COOLING = 0x01	501	LIQUID_COOLING = 0x01
502	};	502	};
503		503
		504	struct atom_firmware_info_v3_2 {
		505	struct atom_common_table_header table_header;
		506	uint32_t firmware_revision;
		507	uint32_t bootup_sclk_in10khz;
		508	uint32_t bootup_mclk_in10khz;
		509	uint32_t firmware_capability; // enum atombios_firmware_capability
		510	uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
		511	uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
		512	uint16_t bootup_vddc_mv;
		513	uint16_t bootup_vddci_mv;
		514	uint16_t bootup_mvddc_mv;
		515	uint16_t bootup_vddgfx_mv;
		516	uint8_t mem_module_id;
		517	uint8_t coolingsolution_id; /0: Air cooling; 1: Liquid cooling ... /
		518	uint8_t reserved1[2];
		519	uint32_t mc_baseaddr_high;
		520	uint32_t mc_baseaddr_low;
		521	uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
		522	uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
		523	uint8_t board_i2c_feature_slave_addr;
		524	uint8_t reserved3;
		525	uint16_t bootup_mvddq_mv;
		526	uint16_t bootup_mvpp_mv;
		527	uint32_t zfbstartaddrin16mb;
		528	uint32_t reserved2[3];
		529	};
504		530
505	/*	531	/*
506	***************************************************************************	532	***************************************************************************
@@ -1169,7 +1195,29 @@ struct atom_gfx_info_v2_2 · 662 unmodified lines
1169	uint32_t rlc_gpu_timer_refclk;	1195	uint32_t rlc_gpu_timer_refclk;
1170	};	1196	};
1171		1197
1172		1198	struct atom_gfx_info_v2_3 {
		1199	struct atom_common_table_header table_header;
		1200	uint8_t gfxip_min_ver;
		1201	uint8_t gfxip_max_ver;
		1202	uint8_t max_shader_engines;
		1203	uint8_t max_tile_pipes;
		1204	uint8_t max_cu_per_sh;
		1205	uint8_t max_sh_per_se;
		1206	uint8_t max_backends_per_se;
		1207	uint8_t max_texture_channel_caches;
		1208	uint32_t regaddr_cp_dma_src_addr;
		1209	uint32_t regaddr_cp_dma_src_addr_hi;
		1210	uint32_t regaddr_cp_dma_dst_addr;
		1211	uint32_t regaddr_cp_dma_dst_addr_hi;
		1212	uint32_t regaddr_cp_dma_command;
		1213	uint32_t regaddr_cp_status;
		1214	uint32_t regaddr_rlc_gpu_clock_32;
		1215	uint32_t rlc_gpu_timer_refclk;
		1216	uint8_t active_cu_per_sh;
		1217	uint8_t active_rb_per_se;
		1218	uint16_t gcgoldenoffset;
		1219	uint32_t rm21_sram_vmin_value;
		1220	};
1173		1221
1174	/*	1222	/*
1175	***************************************************************************	1223	***************************************************************************
@@ -1198,6 +1246,76 @@ struct atom_smu_info_v3_1 · 22 unmodified lines
1198	uint8_t fw_ctf_polarity; // GPIO polarity for CTF	1246	uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1199	};	1247	};
1200		1248
		1249	struct atom_smu_info_v3_2 {
		1250	struct atom_common_table_header table_header;
		1251	uint8_t smuip_min_ver;
		1252	uint8_t smuip_max_ver;
		1253	uint8_t smu_rsd1;
		1254	uint8_t gpuclk_ss_mode;
		1255	uint16_t sclk_ss_percentage;
		1256	uint16_t sclk_ss_rate_10hz;
		1257	uint16_t gpuclk_ss_percentage; // in unit of 0.001%
		1258	uint16_t gpuclk_ss_rate_10hz;
		1259	uint32_t core_refclk_10khz;
		1260	uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
		1261	uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
		1262	uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
		1263	uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
		1264	uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
		1265	uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
		1266	uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
		1267	uint8_t fw_ctf_polarity; // GPIO polarity for CTF
		1268	uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
		1269	uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
		1270	uint16_t smugoldenoffset;
		1271	uint32_t gpupll_vco_freq_10khz;
		1272	uint32_t bootup_smnclk_10khz;
		1273	uint32_t bootup_socclk_10khz;
		1274	uint32_t bootup_mp0clk_10khz;
		1275	uint32_t bootup_mp1clk_10khz;
		1276	uint32_t bootup_lclk_10khz;
		1277	uint32_t bootup_dcefclk_10khz;
		1278	uint32_t ctf_threshold_override_value;
		1279	uint32_t reserved[5];
		1280	};
		1281
		1282	struct atom_smu_info_v3_3 {
		1283	struct atom_common_table_header table_header;
		1284	uint8_t smuip_min_ver;
		1285	uint8_t smuip_max_ver;
		1286	uint8_t smu_rsd1;
		1287	uint8_t gpuclk_ss_mode;
		1288	uint16_t sclk_ss_percentage;
		1289	uint16_t sclk_ss_rate_10hz;
		1290	uint16_t gpuclk_ss_percentage; // in unit of 0.001%
		1291	uint16_t gpuclk_ss_rate_10hz;
		1292	uint32_t core_refclk_10khz;
		1293	uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
		1294	uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
		1295	uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
		1296	uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
		1297	uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
		1298	uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
		1299	uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
		1300	uint8_t fw_ctf_polarity; // GPIO polarity for CTF
		1301	uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
		1302	uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
		1303	uint16_t smugoldenoffset;
		1304	uint32_t gpupll_vco_freq_10khz;
		1305	uint32_t bootup_smnclk_10khz;
		1306	uint32_t bootup_socclk_10khz;
		1307	uint32_t bootup_mp0clk_10khz;
		1308	uint32_t bootup_mp1clk_10khz;
		1309	uint32_t bootup_lclk_10khz;
		1310	uint32_t bootup_dcefclk_10khz;
		1311	uint32_t ctf_threshold_override_value;
		1312	uint32_t syspll3_0_vco_freq_10khz;
		1313	uint32_t syspll3_1_vco_freq_10khz;
		1314	uint32_t bootup_fclk_10khz;
		1315	uint32_t bootup_waflclk_10khz;
		1316	uint32_t reserved[3];
		1317	};
		1318
1201	/*	1319	/*
1202	***************************************************************************	1320	***************************************************************************
1203	Data Table smc_dpm_info structure	1321	Data Table smc_dpm_info structure
@@ -1283,7 +1401,6 @@ struct atom_smc_dpm_info_v4_1 · 79 unmodified lines
1283	uint32_t boardreserved[10];	1401	uint32_t boardreserved[10];
1284	};	1402	};
1285		1403
1286
1287	/*	1404	/*
1288	***************************************************************************	1405	***************************************************************************
1289	Data Table asic_profiling_info structure	1406	Data Table asic_profiling_info structure
@@ -1864,6 +1981,55 @@ enum atom_smu9_syspll0_clock_id · 574 unmodified lines
1864	SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK	1981	SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
1865	};	1982	};
1866		1983
		1984	enum atom_smu11_syspll_id {
		1985	SMU11_SYSPLL0_ID = 0,
		1986	SMU11_SYSPLL1_0_ID = 1,
		1987	SMU11_SYSPLL1_1_ID = 2,
		1988	SMU11_SYSPLL1_2_ID = 3,
		1989	SMU11_SYSPLL2_ID = 4,
		1990	SMU11_SYSPLL3_0_ID = 5,
		1991	SMU11_SYSPLL3_1_ID = 6,
		1992	};
		1993
		1994
		1995	enum atom_smu11_syspll0_clock_id {
		1996	SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK
		1997	SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK
		1998	SMU11_SYSPLL0_DCLK_ID = 2, // DCLK
		1999	SMU11_SYSPLL0_VCLK_ID = 3, // VCLK
		2000	SMU11_SYSPLL0_ECLK_ID = 4, // ECLK
		2001	SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
		2002	};
		2003
		2004
		2005	enum atom_smu11_syspll1_0_clock_id {
		2006	SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
		2007	};
		2008
		2009	enum atom_smu11_syspll1_1_clock_id {
		2010	SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
		2011	};
		2012
		2013	enum atom_smu11_syspll1_2_clock_id {
		2014	SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
		2015	};
		2016
		2017	enum atom_smu11_syspll2_clock_id {
		2018	SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
		2019	};
		2020
		2021	enum atom_smu11_syspll3_0_clock_id {
		2022	SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
		2023	SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
		2024	SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
		2025	};
		2026
		2027	enum atom_smu11_syspll3_1_clock_id {
		2028	SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
		2029	SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
		2030	SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
		2031	};
		2032
1867	struct atom_get_smu_clock_info_output_parameters_v3_1	2033	struct atom_get_smu_clock_info_output_parameters_v3_1
1868	{	2034	{
1869	union {	2035	union {

drivers/gpu/drm/amd/include/cgs_common.h+0−170

@@ -42,20 +42,6 @@ enum cgs_ind_reg { · 41 unmodified lines
42	CGS_IND_REG__AUDIO_ENDPT	42	CGS_IND_REG__AUDIO_ENDPT
43	};	43	};
44		44
45	/**
46	* enum cgs_engine - Engines that can be statically power-gated
47	*/
48	enum cgs_engine {
49	CGS_ENGINE__UVD,
50	CGS_ENGINE__VCE,
51	CGS_ENGINE__VP8,
52	CGS_ENGINE__ACP_DMA,
53	CGS_ENGINE__ACP_DSP0,
54	CGS_ENGINE__ACP_DSP1,
55	CGS_ENGINE__ISP,
56	/* ... */
57	};
58
59	/*	45	/*
60	* enum cgs_ucode_id - Firmware types for different IPs	46	* enum cgs_ucode_id - Firmware types for different IPs
61	*/	47	*/
@@ -76,17 +62,6 @@ enum cgs_ucode_id { · 14 unmodified lines
76	CGS_UCODE_ID_MAXIMUM,	62	CGS_UCODE_ID_MAXIMUM,
77	};	63	};
78		64
79	/*
80	* enum cgs_resource_type - GPU resource type
81	*/
82	enum cgs_resource_type {
83	CGS_RESOURCE_TYPE_MMIO = 0,
84	CGS_RESOURCE_TYPE_FB,
85	CGS_RESOURCE_TYPE_IO,
86	CGS_RESOURCE_TYPE_DOORBELL,
87	CGS_RESOURCE_TYPE_ROM,
88	};
89
90	/**	65	/**
91	* struct cgs_firmware_info - Firmware information	66	* struct cgs_firmware_info - Firmware information
92	*/	67	*/
@@ -104,17 +79,6 @@ struct cgs_firmware_info { · 11 unmodified lines
104	bool is_kicker;	79	bool is_kicker;
105	};	80	};
106		81
107	struct cgs_mode_info {
108	uint32_t refresh_rate;
109	uint32_t vblank_time_us;
110	};
111
112	struct cgs_display_info {
113	uint32_t display_count;
114	uint32_t active_display_mask;
115	struct cgs_mode_info *mode_info;
116	};
117
118	typedef unsigned long cgs_handle_t;	82	typedef unsigned long cgs_handle_t;
119		83
120	/**	84	/**
@@ -170,119 +134,18 @@ typedef void (cgs_write_ind_register_t)(struct cgs_device cgs_device, enum cgs · 49 unmodified lines
170	#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \	134	#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \
171	cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) \| (val) << CGS_REG_FIELD_SHIFT(reg, field))	135	cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) \| (val) << CGS_REG_FIELD_SHIFT(reg, field))
172		136
173	/**
174	* cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
175	* @cgs_device: opaque device handle
176	* @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
177	* @size: size of the region
178	* @offset: offset from the start of the region
179	* @resource_base: base address (not including offset) returned
180	*
181	* Return: 0 on success, -errno otherwise
182	*/
183	typedef int (cgs_get_pci_resource_t)(struct cgs_device cgs_device,
184	enum cgs_resource_type resource_type,
185	uint64_t size,
186	uint64_t offset,
187	uint64_t *resource_base);
188
189	/**
190	* cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
191	* @cgs_device: opaque device handle
192	* @table: data table index
193	* @size: size of the table (output, may be NULL)
194	* @frev: table format revision (output, may be NULL)
195	* @crev: table content revision (output, may be NULL)
196	*
197	* Return: Pointer to start of the table, or NULL on failure
198	*/
199	typedef const void (cgs_atom_get_data_table_t)(
200	struct cgs_device *cgs_device, unsigned table,
201	uint16_t size, uint8_t frev, uint8_t *crev);
202
203	/**
204	* cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
205	* @cgs_device: opaque device handle
206	* @table: data table index
207	* @frev: table format revision (output, may be NULL)
208	* @crev: table content revision (output, may be NULL)
209	*
210	* Return: 0 on success, -errno otherwise
211	*/
212	typedef int (cgs_atom_get_cmd_table_revs_t)(struct cgs_device cgs_device, unsigned table,
213	uint8_t frev, uint8_t crev);
214
215	/**
216	* cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
217	* @cgs_device: opaque device handle
218	* @table: command table index
219	* @args: arguments
220	*
221	* Return: 0 on success, -errno otherwise
222	*/
223	typedef int (cgs_atom_exec_cmd_table_t)(struct cgs_device cgs_device,
224	unsigned table, void *args);
225
226	/**
227	* cgs_get_firmware_info - Get the firmware information from core driver
228	* @cgs_device: opaque device handle
229	* @type: the firmware type
230	* @info: returend firmware information
231	*
232	* Return: 0 on success, -errno otherwise
233	*/
234	typedef int (cgs_get_firmware_info)(struct cgs_device cgs_device,	137	typedef int (cgs_get_firmware_info)(struct cgs_device cgs_device,
235	enum cgs_ucode_id type,	138	enum cgs_ucode_id type,
236	struct cgs_firmware_info *info);	139	struct cgs_firmware_info *info);
237		140
238	typedef int (cgs_rel_firmware)(struct cgs_device cgs_device,
239	enum cgs_ucode_id type);
240
241	typedef int(cgs_set_powergating_state)(struct cgs_device cgs_device,
242	enum amd_ip_block_type block_type,
243	enum amd_powergating_state state);
244
245	typedef int(cgs_set_clockgating_state)(struct cgs_device cgs_device,
246	enum amd_ip_block_type block_type,
247	enum amd_clockgating_state state);
248
249	typedef int(*cgs_get_active_displays_info)(
250	struct cgs_device *cgs_device,
251	struct cgs_display_info *info);
252
253	typedef int (cgs_notify_dpm_enabled)(struct cgs_device cgs_device, bool enabled);
254
255	typedef int (cgs_is_virtualization_enabled_t)(void cgs_device);
256
257	typedef int (cgs_enter_safe_mode)(struct cgs_device cgs_device, bool en);
258
259	typedef void (cgs_lock_grbm_idx)(struct cgs_device cgs_device, bool lock);
260
261	struct cgs_ops {	141	struct cgs_ops {
262	/* MMIO access */	142	/* MMIO access */
263	cgs_read_register_t read_register;	143	cgs_read_register_t read_register;
264	cgs_write_register_t write_register;	144	cgs_write_register_t write_register;
265	cgs_read_ind_register_t read_ind_register;	145	cgs_read_ind_register_t read_ind_register;
266	cgs_write_ind_register_t write_ind_register;	146	cgs_write_ind_register_t write_ind_register;
267	/* PCI resources */
268	cgs_get_pci_resource_t get_pci_resource;
269	/* ATOM BIOS */
270	cgs_atom_get_data_table_t atom_get_data_table;
271	cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
272	cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
273	/* Firmware Info */	147	/* Firmware Info */
274	cgs_get_firmware_info get_firmware_info;	148	cgs_get_firmware_info get_firmware_info;
275	cgs_rel_firmware rel_firmware;
276	/* cg pg interface*/
277	cgs_set_powergating_state set_powergating_state;
278	cgs_set_clockgating_state set_clockgating_state;
279	/* display manager */
280	cgs_get_active_displays_info get_active_displays_info;
281	/* notify dpm enabled */
282	cgs_notify_dpm_enabled notify_dpm_enabled;
283	cgs_is_virtualization_enabled_t is_virtualization_enabled;
284	cgs_enter_safe_mode enter_safe_mode;
285	cgs_lock_grbm_idx lock_grbm_idx;
286	};	149	};
287		150
288	struct cgs_os_ops; /* To be define in OS-specific CGS header */	151	struct cgs_os_ops; /* To be define in OS-specific CGS header */
@@ -309,40 +172,7 @@ struct cgs_device · 20 unmodified lines
309	#define cgs_write_ind_register(dev,space,index,value) \	172	#define cgs_write_ind_register(dev,space,index,value) \
310	CGS_CALL(write_ind_register,dev,space,index,value)	173	CGS_CALL(write_ind_register,dev,space,index,value)
311		174
312	#define cgs_atom_get_data_table(dev,table,size,frev,crev) \
313	CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
314	#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
315	CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
316	#define cgs_atom_exec_cmd_table(dev,table,args) \
317	CGS_CALL(atom_exec_cmd_table,dev,table,args)
318
319	#define cgs_get_firmware_info(dev, type, info) \	175	#define cgs_get_firmware_info(dev, type, info) \
320	CGS_CALL(get_firmware_info, dev, type, info)	176	CGS_CALL(get_firmware_info, dev, type, info)
321	#define cgs_rel_firmware(dev, type) \
322	CGS_CALL(rel_firmware, dev, type)
323	#define cgs_set_powergating_state(dev, block_type, state) \
324	CGS_CALL(set_powergating_state, dev, block_type, state)
325	#define cgs_set_clockgating_state(dev, block_type, state) \
326	CGS_CALL(set_clockgating_state, dev, block_type, state)
327	#define cgs_notify_dpm_enabled(dev, enabled) \
328	CGS_CALL(notify_dpm_enabled, dev, enabled)
329
330	#define cgs_get_active_displays_info(dev, info) \
331	CGS_CALL(get_active_displays_info, dev, info)
332
333	#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
334	resource_base) \
335	CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
336	resource_base)
337
338	#define cgs_is_virtualization_enabled(cgs_device) \
339	CGS_CALL(is_virtualization_enabled, cgs_device)
340
341	#define cgs_enter_safe_mode(cgs_device, en) \
342	CGS_CALL(enter_safe_mode, cgs_device, en)
343
344	#define cgs_lock_grbm_idx(cgs_device, lock) \
345	CGS_CALL(lock_grbm_idx, cgs_device, lock)
346
347		177
348	#endif /* _CGS_COMMON_H */	178	#endif /* _CGS_COMMON_H */

drivers/gpu/drm/amd/include/kgd_pp_interface.h+1−12

 	PP_PCIE,
 	OD_SCLK,
 	OD_MCLK,
+	OD_RANGE,
 };
 enum amd_pp_sensors {
 	uint32_t states[16];
 };
-struct pp_gpu_power {
-	uint32_t vddc_power;
-	uint32_t vddci_power;
-	uint32_t max_gpu_power;
-	uint32_t average_gpu_power;
-};
 #define PP_GROUP_MASK        0xF0000000
 #define PP_GROUP_SHIFT       28
 	int (*load_firmware)(void *handle);
 	int (*wait_for_fw_loading_complete)(void *handle);
 	int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
-	int (*notify_smu_memory_info)(void *handle, uint32_t virtual_addr_low,
-					uint32_t virtual_addr_hi,
-					uint32_t mc_addr_low,
-					uint32_t mc_addr_hi,
-					uint32_t size);
 	int (*set_power_limit)(void *handle, uint32_t n);
 	int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
 /* export to DC */

drivers/gpu/drm/amd/powerplay/amd_powerplay.c+158−331

@@ -25,30 +25,16 @@ · 24 unmodified lines
25	#include <linux/kernel.h>	25	#include <linux/kernel.h>
26	#include <linux/gfp.h>	26	#include <linux/gfp.h>
27	#include <linux/slab.h>	27	#include <linux/slab.h>
		28	#include <linux/firmware.h>
28	#include "amd_shared.h"	29	#include "amd_shared.h"
29	#include "amd_powerplay.h"	30	#include "amd_powerplay.h"
30	#include "power_state.h"	31	#include "power_state.h"
31	#include "amdgpu.h"	32	#include "amdgpu.h"
32	#include "hwmgr.h"	33	#include "hwmgr.h"
33		34
34	#define PP_DPM_DISABLED 0xCCCC
35
36	static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
37	enum amd_pm_state_type *user_state);
38		35
39	static const struct amd_pm_funcs pp_dpm_funcs;	36	static const struct amd_pm_funcs pp_dpm_funcs;
40		37
41	static inline int pp_check(struct pp_hwmgr *hwmgr)
42	{
43	if (hwmgr == NULL \|\| hwmgr->smumgr_funcs == NULL)
44	return -EINVAL;
45
46	if (hwmgr->pm_en == 0 \|\| hwmgr->hwmgr_func == NULL)
47	return PP_DPM_DISABLED;
48
49	return 0;
50	}
51
52	static int amd_powerplay_create(struct amdgpu_device *adev)	38	static int amd_powerplay_create(struct amdgpu_device *adev)
53	{	39	{
54	struct pp_hwmgr *hwmgr;	40	struct pp_hwmgr *hwmgr;
@@ -61,19 +47,21 @@ static int amd_powerplay_create(struct amdgpu_device *adev) · 6 unmodified lines
61	return -ENOMEM;	47	return -ENOMEM;
62		48
63	hwmgr->adev = adev;	49	hwmgr->adev = adev;
64	hwmgr->pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;	50	hwmgr->not_vf = !amdgpu_sriov_vf(adev);
		51	hwmgr->pm_en = (amdgpu_dpm && hwmgr->not_vf) ? true : false;
65	hwmgr->device = amdgpu_cgs_create_device(adev);	52	hwmgr->device = amdgpu_cgs_create_device(adev);
66	mutex_init(&hwmgr->smu_lock);	53	mutex_init(&hwmgr->smu_lock);
67	hwmgr->chip_family = adev->family;	54	hwmgr->chip_family = adev->family;
68	hwmgr->chip_id = adev->asic_type;	55	hwmgr->chip_id = adev->asic_type;
69	hwmgr->feature_mask = amdgpu_pp_feature_mask;	56	hwmgr->feature_mask = adev->powerplay.pp_feature;
		57	hwmgr->display_config = &adev->pm.pm_display_cfg;
70	adev->powerplay.pp_handle = hwmgr;	58	adev->powerplay.pp_handle = hwmgr;
71	adev->powerplay.pp_funcs = &pp_dpm_funcs;	59	adev->powerplay.pp_funcs = &pp_dpm_funcs;
72	return 0;	60	return 0;
73	}	61	}
74		62
75		63
76	static int amd_powerplay_destroy(struct amdgpu_device *adev)	64	static void amd_powerplay_destroy(struct amdgpu_device *adev)
77	{	65	{
78	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;	66	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
79		67
@@ -82,8 +70,6 @@ static int amd_powerplay_destroy(struct amdgpu_device *adev) · 2 unmodified lines
82		70
83	kfree(hwmgr);	71	kfree(hwmgr);
84	hwmgr = NULL;	72	hwmgr = NULL;
85
86	return 0;
87	}	73	}
88		74
89	static int pp_early_init(void *handle)	75	static int pp_early_init(void *handle)
@@ -109,18 +95,9 @@ static int pp_sw_init(void *handle) · 19 unmodified lines
109	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;	95	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
110	int ret = 0;	96	int ret = 0;
111		97
112	ret = pp_check(hwmgr);	98	ret = hwmgr_sw_init(hwmgr);
113
114	if (ret >= 0) {
115	if (hwmgr->smumgr_funcs->smu_init == NULL)
116	return -EINVAL;
117
118	ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
119		99
120	phm_register_irq_handlers(hwmgr);	100	pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully");
121
122	pr_debug("amdgpu: powerplay sw initialized\n");
123	}
124		101
125	return ret;	102	return ret;
126	}	103	}
@@ -129,16 +106,14 @@ static int pp_sw_fini(void *handle) · 2 unmodified lines
129	{	106	{
130	struct amdgpu_device *adev = handle;	107	struct amdgpu_device *adev = handle;
131	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;	108	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
132	int ret = 0;
133		109
134	ret = pp_check(hwmgr);	110	hwmgr_sw_fini(hwmgr);
135	if (ret >= 0) {
136	if (hwmgr->smumgr_funcs->smu_fini != NULL)
137	hwmgr->smumgr_funcs->smu_fini(hwmgr);
138	}
139		111
140	if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)	112	if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
		113	release_firmware(adev->pm.fw);
		114	adev->pm.fw = NULL;
141	amdgpu_ucode_fini_bo(adev);	115	amdgpu_ucode_fini_bo(adev);
		116	}
142		117
143	return 0;	118	return 0;
144	}	119	}
@@ -152,55 +127,76 @@ static int pp_hw_init(void *handle) · 7 unmodified lines
152	if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)	127	if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
153	amdgpu_ucode_init_bo(adev);	128	amdgpu_ucode_init_bo(adev);
154		129
155	ret = pp_check(hwmgr);	130	ret = hwmgr_hw_init(hwmgr);
156		131
157	if (ret >= 0) {	132	if (ret)
158	if (hwmgr->smumgr_funcs->start_smu == NULL)	133	pr_err("powerplay hw init failed\n");
159	return -EINVAL;
160		134
161	if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
162	pr_err("smc start failed\n");
163	hwmgr->smumgr_funcs->smu_fini(hwmgr);
164	return -EINVAL;
165	}
166	if (ret == PP_DPM_DISABLED)
167	goto exit;
168	ret = hwmgr_hw_init(hwmgr);
169	if (ret)
170	goto exit;
171	}
172	return ret;	135	return ret;
173	exit:
174	hwmgr->pm_en = 0;
175	cgs_notify_dpm_enabled(hwmgr->device, false);
176	return 0;
177
178	}	136	}
179		137
180	static int pp_hw_fini(void *handle)	138	static int pp_hw_fini(void *handle)
181	{	139	{
182	struct amdgpu_device *adev = handle;	140	struct amdgpu_device *adev = handle;
183	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;	141	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
184	int ret = 0;
185		142
186	ret = pp_check(hwmgr);	143	hwmgr_hw_fini(hwmgr);
187	if (ret == 0)
188	hwmgr_hw_fini(hwmgr);
189		144
190	return 0;	145	return 0;
191	}	146	}
192		147
		148	static void pp_reserve_vram_for_smu(struct amdgpu_device *adev)
		149	{
		150	int r = -EINVAL;
		151	void *cpu_ptr = NULL;
		152	uint64_t gpu_addr;
		153	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
		154
		155	if (amdgpu_bo_create_kernel(adev, adev->pm.smu_prv_buffer_size,
		156	PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
		157	&adev->pm.smu_prv_buffer,
		158	&gpu_addr,
		159	&cpu_ptr)) {
		160	DRM_ERROR("amdgpu: failed to create smu prv buffer\n");
		161	return;
		162	}
		163
		164	if (hwmgr->hwmgr_func->notify_cac_buffer_info)
		165	r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr,
		166	lower_32_bits((unsigned long)cpu_ptr),
		167	upper_32_bits((unsigned long)cpu_ptr),
		168	lower_32_bits(gpu_addr),
		169	upper_32_bits(gpu_addr),
		170	adev->pm.smu_prv_buffer_size);
		171
		172	if (r) {
		173	amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
		174	adev->pm.smu_prv_buffer = NULL;
		175	DRM_ERROR("amdgpu: failed to notify SMU buffer address\n");
		176	}
		177	}
		178
193	static int pp_late_init(void *handle)	179	static int pp_late_init(void *handle)
194	{	180	{
195	struct amdgpu_device *adev = handle;	181	struct amdgpu_device *adev = handle;
196	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;	182	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
197	int ret = 0;	183	int ret;
198
199	ret = pp_check(hwmgr);
200		184
201	if (ret == 0)	185	if (hwmgr && hwmgr->pm_en) {
202	pp_dpm_dispatch_tasks(hwmgr,	186	mutex_lock(&hwmgr->smu_lock);
		187	hwmgr_handle_task(hwmgr,
203	AMD_PP_TASK_COMPLETE_INIT, NULL);	188	AMD_PP_TASK_COMPLETE_INIT, NULL);
		189	mutex_unlock(&hwmgr->smu_lock);
		190	}
		191	if (adev->pm.smu_prv_buffer_size != 0)
		192	pp_reserve_vram_for_smu(adev);
		193
		194	if (hwmgr->hwmgr_func->gfx_off_control &&
		195	(hwmgr->feature_mask & PP_GFXOFF_MASK)) {
		196	ret = hwmgr->hwmgr_func->gfx_off_control(hwmgr, true);
		197	if (ret)
		198	pr_err("gfx off enabling failed!\n");
		199	}
204		200
205	return 0;	201	return 0;
206	}	202	}
@@ -209,6 +205,8 @@ static void pp_late_fini(void *handle) · 2 unmodified lines
209	{	205	{
210	struct amdgpu_device *adev = handle;	206	struct amdgpu_device *adev = handle;
211		207
		208	if (adev->pm.smu_prv_buffer)
		209	amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
212	amd_powerplay_destroy(adev);	210	amd_powerplay_destroy(adev);
213	}	211	}
214		212
@@ -233,12 +231,18 @@ static int pp_set_powergating_state(void *handle, · 18 unmodified lines
233	{	231	{
234	struct amdgpu_device *adev = handle;	232	struct amdgpu_device *adev = handle;
235	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;	233	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
236	int ret = 0;	234	int ret;
237		235
238	ret = pp_check(hwmgr);	236	if (!hwmgr \|\| !hwmgr->pm_en)
		237	return 0;
239		238
240	if (ret)	239	if (hwmgr->hwmgr_func->gfx_off_control) {
241	return ret;	240	/* Enable/disable GFX off through SMU */
		241	ret = hwmgr->hwmgr_func->gfx_off_control(hwmgr,
		242	state == AMD_PG_STATE_GATE);
		243	if (ret)
		244	pr_err("gfx off control failed!\n");
		245	}
242		246
243	if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {	247	if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
244	pr_info("%s was not implemented.\n", __func__);	248	pr_info("%s was not implemented.\n", __func__);
@@ -254,38 +258,16 @@ static int pp_suspend(void *handle) · 9 unmodified lines
254	{	258	{
255	struct amdgpu_device *adev = handle;	259	struct amdgpu_device *adev = handle;
256	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;	260	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
257	int ret = 0;
258		261
259	ret = pp_check(hwmgr);	262	return hwmgr_suspend(hwmgr);
260	if (ret == 0)
261	hwmgr_hw_suspend(hwmgr);
262	return 0;
263	}	263	}
264		264
265	static int pp_resume(void *handle)	265	static int pp_resume(void *handle)
266	{	266	{
267	struct amdgpu_device *adev = handle;	267	struct amdgpu_device *adev = handle;
268	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;	268	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
269	int ret;
270
271	ret = pp_check(hwmgr);
272
273	if (ret < 0)
274	return ret;
275
276	if (hwmgr->smumgr_funcs->start_smu == NULL)
277	return -EINVAL;
278
279	if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
280	pr_err("smc start failed\n");
281	hwmgr->smumgr_funcs->smu_fini(hwmgr);
282	return -EINVAL;
283	}
284
285	if (ret == PP_DPM_DISABLED)
286	return 0;
287		269
288	return hwmgr_hw_resume(hwmgr);	270	return hwmgr_resume(hwmgr);
289	}	271	}
290		272
291	static int pp_set_clockgating_state(void *handle,	273	static int pp_set_clockgating_state(void *handle,
@@ -334,12 +316,9 @@ static int pp_dpm_fw_loading_complete(void *handle) · 42 unmodified lines
334	static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)	316	static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
335	{	317	{
336	struct pp_hwmgr *hwmgr = handle;	318	struct pp_hwmgr *hwmgr = handle;
337	int ret = 0;
338
339	ret = pp_check(hwmgr);
340		319
341	if (ret)	320	if (!hwmgr \|\| !hwmgr->pm_en)
342	return ret;	321	return -EINVAL;
343		322
344	if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {	323	if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
345	pr_info("%s was not implemented.\n", __func__);	324	pr_info("%s was not implemented.\n", __func__);
@@ -362,10 +341,10 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, · 16 unmodified lines
362	if (*level & profile_mode_mask) {	341	if (*level & profile_mode_mask) {
363	hwmgr->saved_dpm_level = hwmgr->dpm_level;	342	hwmgr->saved_dpm_level = hwmgr->dpm_level;
364	hwmgr->en_umd_pstate = true;	343	hwmgr->en_umd_pstate = true;
365	cgs_set_clockgating_state(hwmgr->device,	344	amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
366	AMD_IP_BLOCK_TYPE_GFX,	345	AMD_IP_BLOCK_TYPE_GFX,
367	AMD_CG_STATE_UNGATE);	346	AMD_CG_STATE_UNGATE);
368	cgs_set_powergating_state(hwmgr->device,	347	amdgpu_device_ip_set_powergating_state(hwmgr->adev,
369	AMD_IP_BLOCK_TYPE_GFX,	348	AMD_IP_BLOCK_TYPE_GFX,
370	AMD_PG_STATE_UNGATE);	349	AMD_PG_STATE_UNGATE);
371	}	350	}
@@ -375,10 +354,10 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, · 3 unmodified lines
375	if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)	354	if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
376	*level = hwmgr->saved_dpm_level;	355	*level = hwmgr->saved_dpm_level;
377	hwmgr->en_umd_pstate = false;	356	hwmgr->en_umd_pstate = false;
378	cgs_set_clockgating_state(hwmgr->device,	357	amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
379	AMD_IP_BLOCK_TYPE_GFX,	358	AMD_IP_BLOCK_TYPE_GFX,
380	AMD_CG_STATE_GATE);	359	AMD_CG_STATE_GATE);
381	cgs_set_powergating_state(hwmgr->device,	360	amdgpu_device_ip_set_powergating_state(hwmgr->adev,
382	AMD_IP_BLOCK_TYPE_GFX,	361	AMD_IP_BLOCK_TYPE_GFX,
383	AMD_PG_STATE_GATE);	362	AMD_PG_STATE_GATE);
384	}	363	}
@@ -389,12 +368,9 @@ static int pp_dpm_force_performance_level(void *handle, · 4 unmodified lines
389	enum amd_dpm_forced_level level)	368	enum amd_dpm_forced_level level)
390	{	369	{
391	struct pp_hwmgr *hwmgr = handle;	370	struct pp_hwmgr *hwmgr = handle;
392	int ret = 0;
393		371
394	ret = pp_check(hwmgr);	372	if (!hwmgr \|\| !hwmgr->pm_en)
395		373	return -EINVAL;
396	if (ret)
397	return ret;
398		374
399	if (level == hwmgr->dpm_level)	375	if (level == hwmgr->dpm_level)
400	return 0;	376	return 0;
@@ -412,13 +388,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level( · 11 unmodified lines
412	void *handle)	388	void *handle)
413	{	389	{
414	struct pp_hwmgr *hwmgr = handle;	390	struct pp_hwmgr *hwmgr = handle;
415	int ret = 0;
416	enum amd_dpm_forced_level level;	391	enum amd_dpm_forced_level level;
417		392
418	ret = pp_check(hwmgr);	393	if (!hwmgr \|\| !hwmgr->pm_en)
419		394	return -EINVAL;
420	if (ret)
421	return ret;
422		395
423	mutex_lock(&hwmgr->smu_lock);	396	mutex_lock(&hwmgr->smu_lock);
424	level = hwmgr->dpm_level;	397	level = hwmgr->dpm_level;
@@ -429,13 +402,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level( · 4 unmodified lines
429	static uint32_t pp_dpm_get_sclk(void *handle, bool low)	402	static uint32_t pp_dpm_get_sclk(void *handle, bool low)
430	{	403	{
431	struct pp_hwmgr *hwmgr = handle;	404	struct pp_hwmgr *hwmgr = handle;
432	int ret = 0;
433	uint32_t clk = 0;	405	uint32_t clk = 0;
434		406
435	ret = pp_check(hwmgr);	407	if (!hwmgr \|\| !hwmgr->pm_en)
436		408	return 0;
437	if (ret)
438	return ret;
439		409
440	if (hwmgr->hwmgr_func->get_sclk == NULL) {	410	if (hwmgr->hwmgr_func->get_sclk == NULL) {
441	pr_info("%s was not implemented.\n", __func__);	411	pr_info("%s was not implemented.\n", __func__);
@@ -450,13 +420,10 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low) · 8 unmodified lines
450	static uint32_t pp_dpm_get_mclk(void *handle, bool low)	420	static uint32_t pp_dpm_get_mclk(void *handle, bool low)
451	{	421	{
452	struct pp_hwmgr *hwmgr = handle;	422	struct pp_hwmgr *hwmgr = handle;
453	int ret = 0;
454	uint32_t clk = 0;	423	uint32_t clk = 0;
455		424
456	ret = pp_check(hwmgr);	425	if (!hwmgr \|\| !hwmgr->pm_en)
457		426	return 0;
458	if (ret)
459	return ret;
460		427
461	if (hwmgr->hwmgr_func->get_mclk == NULL) {	428	if (hwmgr->hwmgr_func->get_mclk == NULL) {
462	pr_info("%s was not implemented.\n", __func__);	429	pr_info("%s was not implemented.\n", __func__);
@@ -471,11 +438,8 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low) · 8 unmodified lines
471	static void pp_dpm_powergate_vce(void *handle, bool gate)	438	static void pp_dpm_powergate_vce(void *handle, bool gate)
472	{	439	{
473	struct pp_hwmgr *hwmgr = handle;	440	struct pp_hwmgr *hwmgr = handle;
474	int ret = 0;
475		441
476	ret = pp_check(hwmgr);	442	if (!hwmgr \|\| !hwmgr->pm_en)
477
478	if (ret)
479	return;	443	return;
480		444
481	if (hwmgr->hwmgr_func->powergate_vce == NULL) {	445	if (hwmgr->hwmgr_func->powergate_vce == NULL) {
@@ -490,11 +454,8 @@ static void pp_dpm_powergate_vce(void *handle, bool gate) · 8 unmodified lines
490	static void pp_dpm_powergate_uvd(void *handle, bool gate)	454	static void pp_dpm_powergate_uvd(void *handle, bool gate)
491	{	455	{
492	struct pp_hwmgr *hwmgr = handle;	456	struct pp_hwmgr *hwmgr = handle;
493	int ret = 0;
494
495	ret = pp_check(hwmgr);
496		457
497	if (ret)	458	if (!hwmgr \|\| !hwmgr->pm_en)
498	return;	459	return;
499		460
500	if (hwmgr->hwmgr_func->powergate_uvd == NULL) {	461	if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
@@ -512,10 +473,8 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, · 11 unmodified lines
512	int ret = 0;	473	int ret = 0;
513	struct pp_hwmgr *hwmgr = handle;	474	struct pp_hwmgr *hwmgr = handle;
514		475
515	ret = pp_check(hwmgr);	476	if (!hwmgr \|\| !hwmgr->pm_en)
516		477	return -EINVAL;
517	if (ret)
518	return ret;
519		478
520	mutex_lock(&hwmgr->smu_lock);	479	mutex_lock(&hwmgr->smu_lock);
521	ret = hwmgr_handle_task(hwmgr, task_id, user_state);	480	ret = hwmgr_handle_task(hwmgr, task_id, user_state);
@@ -528,15 +487,9 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) · 6 unmodified lines
528	{	487	{
529	struct pp_hwmgr *hwmgr = handle;	488	struct pp_hwmgr *hwmgr = handle;
530	struct pp_power_state *state;	489	struct pp_power_state *state;
531	int ret = 0;
532	enum amd_pm_state_type pm_type;	490	enum amd_pm_state_type pm_type;
533		491
534	ret = pp_check(hwmgr);	492	if (!hwmgr \|\| !hwmgr->pm_en \|\| !hwmgr->current_ps)
535
536	if (ret)
537	return ret;
538
539	if (hwmgr->current_ps == NULL)
540	return -EINVAL;	493	return -EINVAL;
541		494
542	mutex_lock(&hwmgr->smu_lock);	495	mutex_lock(&hwmgr->smu_lock);
@@ -568,11 +521,8 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) · 25 unmodified lines
568	static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)	521	static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
569	{	522	{
570	struct pp_hwmgr *hwmgr = handle;	523	struct pp_hwmgr *hwmgr = handle;
571	int ret = 0;
572
573	ret = pp_check(hwmgr);
574		524
575	if (ret)	525	if (!hwmgr \|\| !hwmgr->pm_en)
576	return;	526	return;
577		527
578	if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {	528	if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
@@ -587,13 +537,10 @@ static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) · 8 unmodified lines
587	static uint32_t pp_dpm_get_fan_control_mode(void *handle)	537	static uint32_t pp_dpm_get_fan_control_mode(void *handle)
588	{	538	{
589	struct pp_hwmgr *hwmgr = handle;	539	struct pp_hwmgr *hwmgr = handle;
590	int ret = 0;
591	uint32_t mode = 0;	540	uint32_t mode = 0;
592		541
593	ret = pp_check(hwmgr);	542	if (!hwmgr \|\| !hwmgr->pm_en)
594		543	return 0;
595	if (ret)
596	return ret;
597		544
598	if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {	545	if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
599	pr_info("%s was not implemented.\n", __func__);	546	pr_info("%s was not implemented.\n", __func__);
@@ -610,10 +557,8 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) · 10 unmodified lines
610	struct pp_hwmgr *hwmgr = handle;	557	struct pp_hwmgr *hwmgr = handle;
611	int ret = 0;	558	int ret = 0;
612		559
613	ret = pp_check(hwmgr);	560	if (!hwmgr \|\| !hwmgr->pm_en)
614		561	return -EINVAL;
615	if (ret)
616	return ret;
617		562
618	if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {	563	if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
619	pr_info("%s was not implemented.\n", __func__);	564	pr_info("%s was not implemented.\n", __func__);
@@ -630,10 +575,8 @@ static int pp_dpm_get_fan_speed_percent(void handle, uint32_t speed) · 10 unmodified lines
630	struct pp_hwmgr *hwmgr = handle;	575	struct pp_hwmgr *hwmgr = handle;
631	int ret = 0;	576	int ret = 0;
632		577
633	ret = pp_check(hwmgr);	578	if (!hwmgr \|\| !hwmgr->pm_en)
634		579	return -EINVAL;
635	if (ret)
636	return ret;
637		580
638	if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {	581	if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
639	pr_info("%s was not implemented.\n", __func__);	582	pr_info("%s was not implemented.\n", __func__);
@@ -651,10 +594,8 @@ static int pp_dpm_get_fan_speed_rpm(void handle, uint32_t rpm) · 11 unmodified lines
651	struct pp_hwmgr *hwmgr = handle;	594	struct pp_hwmgr *hwmgr = handle;
652	int ret = 0;	595	int ret = 0;
653		596
654	ret = pp_check(hwmgr);	597	if (!hwmgr \|\| !hwmgr->pm_en)
655		598	return -EINVAL;
656	if (ret)
657	return ret;
658		599
659	if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)	600	if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
660	return -EINVAL;	601	return -EINVAL;
@@ -670,16 +611,10 @@ static int pp_dpm_get_pp_num_states(void *handle, · 9 unmodified lines
670	{	611	{
671	struct pp_hwmgr *hwmgr = handle;	612	struct pp_hwmgr *hwmgr = handle;
672	int i;	613	int i;
673	int ret = 0;
674		614
675	memset(data, 0, sizeof(*data));	615	memset(data, 0, sizeof(*data));
676		616
677	ret = pp_check(hwmgr);	617	if (!hwmgr \|\| !hwmgr->pm_en \|\|!hwmgr->ps)
678
679	if (ret)
680	return ret;
681
682	if (hwmgr->ps == NULL)
683	return -EINVAL;	618	return -EINVAL;
684		619
685	mutex_lock(&hwmgr->smu_lock);	620	mutex_lock(&hwmgr->smu_lock);
@@ -713,15 +648,9 @@ static int pp_dpm_get_pp_num_states(void *handle, · 27 unmodified lines
713	static int pp_dpm_get_pp_table(void handle, char *table)	648	static int pp_dpm_get_pp_table(void handle, char *table)
714	{	649	{
715	struct pp_hwmgr *hwmgr = handle;	650	struct pp_hwmgr *hwmgr = handle;
716	int ret = 0;
717	int size = 0;	651	int size = 0;
718		652
719	ret = pp_check(hwmgr);	653	if (!hwmgr \|\| !hwmgr->pm_en \|\|!hwmgr->soft_pp_table)
720
721	if (ret)
722	return ret;
723
724	if (!hwmgr->soft_pp_table)
725	return -EINVAL;	654	return -EINVAL;
726		655
727	mutex_lock(&hwmgr->smu_lock);	656	mutex_lock(&hwmgr->smu_lock);
@@ -736,10 +665,6 @@ static int amd_powerplay_reset(void *handle) · 8 unmodified lines
736	struct pp_hwmgr *hwmgr = handle;	665	struct pp_hwmgr *hwmgr = handle;
737	int ret;	666	int ret;
738		667
739	ret = pp_check(hwmgr);
740	if (ret)
741	return ret;
742
743	ret = hwmgr_hw_fini(hwmgr);	668	ret = hwmgr_hw_fini(hwmgr);
744	if (ret)	669	if (ret)
745	return ret;	670	return ret;
@@ -754,40 +679,38 @@ static int amd_powerplay_reset(void *handle) · 8 unmodified lines
754	static int pp_dpm_set_pp_table(void handle, const char buf, size_t size)	679	static int pp_dpm_set_pp_table(void handle, const char buf, size_t size)
755	{	680	{
756	struct pp_hwmgr *hwmgr = handle;	681	struct pp_hwmgr *hwmgr = handle;
757	int ret = 0;	682	int ret = -ENOMEM;
758		683
759	ret = pp_check(hwmgr);	684	if (!hwmgr \|\| !hwmgr->pm_en)
760		685	return -EINVAL;
761	if (ret)
762	return ret;
763		686
764	mutex_lock(&hwmgr->smu_lock);	687	mutex_lock(&hwmgr->smu_lock);
765	if (!hwmgr->hardcode_pp_table) {	688	if (!hwmgr->hardcode_pp_table) {
766	hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,	689	hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
767	hwmgr->soft_pp_table_size,	690	hwmgr->soft_pp_table_size,
768	GFP_KERNEL);	691	GFP_KERNEL);
769	if (!hwmgr->hardcode_pp_table) {	692	if (!hwmgr->hardcode_pp_table)
770	mutex_unlock(&hwmgr->smu_lock);	693	goto err;
771	return -ENOMEM;
772	}
773	}	694	}
774		695
775	memcpy(hwmgr->hardcode_pp_table, buf, size);	696	memcpy(hwmgr->hardcode_pp_table, buf, size);
776		697
777	hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;	698	hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
778	mutex_unlock(&hwmgr->smu_lock);
779		699
780	ret = amd_powerplay_reset(handle);	700	ret = amd_powerplay_reset(handle);
781	if (ret)	701	if (ret)
782	return ret;	702	goto err;
783		703
784	if (hwmgr->hwmgr_func->avfs_control) {	704	if (hwmgr->hwmgr_func->avfs_control) {
785	ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);	705	ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
786	if (ret)	706	if (ret)
787	return ret;	707	goto err;
788	}	708	}
789		709	mutex_unlock(&hwmgr->smu_lock);
790	return 0;	710	return 0;
		711	err:
		712	mutex_unlock(&hwmgr->smu_lock);
		713	return ret;
791	}	714	}
792		715
793	static int pp_dpm_force_clock_level(void *handle,	716	static int pp_dpm_force_clock_level(void *handle,
@@ -796,10 +719,8 @@ static int pp_dpm_force_clock_level(void *handle, · 2 unmodified lines
796	struct pp_hwmgr *hwmgr = handle;	719	struct pp_hwmgr *hwmgr = handle;
797	int ret = 0;	720	int ret = 0;
798		721
799	ret = pp_check(hwmgr);	722	if (!hwmgr \|\| !hwmgr->pm_en)
800		723	return -EINVAL;
801	if (ret)
802	return ret;
803		724
804	if (hwmgr->hwmgr_func->force_clock_level == NULL) {	725	if (hwmgr->hwmgr_func->force_clock_level == NULL) {
805	pr_info("%s was not implemented.\n", __func__);	726	pr_info("%s was not implemented.\n", __func__);
@@ -820,10 +741,8 @@ static int pp_dpm_print_clock_levels(void *handle, · 14 unmodified lines
820	struct pp_hwmgr *hwmgr = handle;	741	struct pp_hwmgr *hwmgr = handle;
821	int ret = 0;	742	int ret = 0;
822		743
823	ret = pp_check(hwmgr);	744	if (!hwmgr \|\| !hwmgr->pm_en)
824		745	return -EINVAL;
825	if (ret)
826	return ret;
827		746
828	if (hwmgr->hwmgr_func->print_clock_levels == NULL) {	747	if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
829	pr_info("%s was not implemented.\n", __func__);	748	pr_info("%s was not implemented.\n", __func__);
@@ -840,10 +759,8 @@ static int pp_dpm_get_sclk_od(void *handle) · 10 unmodified lines
840	struct pp_hwmgr *hwmgr = handle;	759	struct pp_hwmgr *hwmgr = handle;
841	int ret = 0;	760	int ret = 0;
842		761
843	ret = pp_check(hwmgr);	762	if (!hwmgr \|\| !hwmgr->pm_en)
844		763	return -EINVAL;
845	if (ret)
846	return ret;
847		764
848	if (hwmgr->hwmgr_func->get_sclk_od == NULL) {	765	if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
849	pr_info("%s was not implemented.\n", __func__);	766	pr_info("%s was not implemented.\n", __func__);
@@ -860,10 +777,8 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value) · 10 unmodified lines
860	struct pp_hwmgr *hwmgr = handle;	777	struct pp_hwmgr *hwmgr = handle;
861	int ret = 0;	778	int ret = 0;
862		779
863	ret = pp_check(hwmgr);	780	if (!hwmgr \|\| !hwmgr->pm_en)
864		781	return -EINVAL;
865	if (ret)
866	return ret;
867		782
868	if (hwmgr->hwmgr_func->set_sclk_od == NULL) {	783	if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
869	pr_info("%s was not implemented.\n", __func__);	784	pr_info("%s was not implemented.\n", __func__);
@@ -881,10 +796,8 @@ static int pp_dpm_get_mclk_od(void *handle) · 11 unmodified lines
881	struct pp_hwmgr *hwmgr = handle;	796	struct pp_hwmgr *hwmgr = handle;
882	int ret = 0;	797	int ret = 0;
883		798
884	ret = pp_check(hwmgr);	799	if (!hwmgr \|\| !hwmgr->pm_en)
885		800	return -EINVAL;
886	if (ret)
887	return ret;
888		801
889	if (hwmgr->hwmgr_func->get_mclk_od == NULL) {	802	if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
890	pr_info("%s was not implemented.\n", __func__);	803	pr_info("%s was not implemented.\n", __func__);
@@ -901,10 +814,8 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value) · 10 unmodified lines
901	struct pp_hwmgr *hwmgr = handle;	814	struct pp_hwmgr *hwmgr = handle;
902	int ret = 0;	815	int ret = 0;
903		816
904	ret = pp_check(hwmgr);	817	if (!hwmgr \|\| !hwmgr->pm_en)
905		818	return -EINVAL;
906	if (ret)
907	return ret;
908		819
909	if (hwmgr->hwmgr_func->set_mclk_od == NULL) {	820	if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
910	pr_info("%s was not implemented.\n", __func__);	821	pr_info("%s was not implemented.\n", __func__);
@@ -922,11 +833,7 @@ static int pp_dpm_read_sensor(void *handle, int idx, · 11 unmodified lines
922	struct pp_hwmgr *hwmgr = handle;	833	struct pp_hwmgr *hwmgr = handle;
923	int ret = 0;	834	int ret = 0;
924		835
925	ret = pp_check(hwmgr);	836	if (!hwmgr \|\| !hwmgr->pm_en \|\| !value)
926	if (ret)
927	return ret;
928
929	if (value == NULL)
930	return -EINVAL;	837	return -EINVAL;
931		838
932	switch (idx) {	839	switch (idx) {
@@ -948,14 +855,11 @@ static struct amd_vce_state* · 15 unmodified lines
948	pp_dpm_get_vce_clock_state(void *handle, unsigned idx)	855	pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
949	{	856	{
950	struct pp_hwmgr *hwmgr = handle;	857	struct pp_hwmgr *hwmgr = handle;
951	int ret = 0;
952
953	ret = pp_check(hwmgr);
954		858
955	if (ret)	859	if (!hwmgr \|\| !hwmgr->pm_en)
956	return NULL;	860	return NULL;
957		861
958	if (hwmgr && idx < hwmgr->num_vce_state_tables)	862	if (idx < hwmgr->num_vce_state_tables)
959	return &hwmgr->vce_states[idx];	863	return &hwmgr->vce_states[idx];
960	return NULL;	864	return NULL;
961	}	865	}
@@ -964,7 +868,7 @@ static int pp_get_power_profile_mode(void handle, char buf) · 2 unmodified lines
964	{	868	{
965	struct pp_hwmgr *hwmgr = handle;	869	struct pp_hwmgr *hwmgr = handle;
966		870
967	if (!buf \|\| pp_check(hwmgr))	871	if (!hwmgr \|\| !hwmgr->pm_en \|\| !buf)
968	return -EINVAL;	872	return -EINVAL;
969		873
970	if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {	874	if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
@@ -980,12 +884,12 @@ static int pp_set_power_profile_mode(void handle, long input, uint32_t size) · 9 unmodified lines
980	struct pp_hwmgr *hwmgr = handle;	884	struct pp_hwmgr *hwmgr = handle;
981	int ret = -EINVAL;	885	int ret = -EINVAL;
982		886
983	if (pp_check(hwmgr))	887	if (!hwmgr \|\| !hwmgr->pm_en)
984	return -EINVAL;	888	return ret;
985		889
986	if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {	890	if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
987	pr_info("%s was not implemented.\n", __func__);	891	pr_info("%s was not implemented.\n", __func__);
988	return -EINVAL;	892	return ret;
989	}	893	}
990	mutex_lock(&hwmgr->smu_lock);	894	mutex_lock(&hwmgr->smu_lock);
991	if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)	895	if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
@@ -998,7 +902,7 @@ static int pp_odn_edit_dpm_table(void handle, uint32_t type, long input, uint3 · 6 unmodified lines
998	{	902	{
999	struct pp_hwmgr *hwmgr = handle;	903	struct pp_hwmgr *hwmgr = handle;
1000		904
1001	if (pp_check(hwmgr))	905	if (!hwmgr \|\| !hwmgr->pm_en)
1002	return -EINVAL;	906	return -EINVAL;
1003		907
1004	if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {	908	if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
@@ -1016,7 +920,7 @@ static int pp_dpm_switch_power_profile(void *handle, · 11 unmodified lines
1016	long workload;	920	long workload;
1017	uint32_t index;	921	uint32_t index;
1018		922
1019	if (pp_check(hwmgr))	923	if (!hwmgr \|\| !hwmgr->pm_en)
1020	return -EINVAL;	924	return -EINVAL;
1021		925
1022	if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {	926	if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
@@ -1048,46 +952,12 @@ static int pp_dpm_switch_power_profile(void *handle, · 25 unmodified lines
1048	return 0;	952	return 0;
1049	}	953	}
1050		954
1051	static int pp_dpm_notify_smu_memory_info(void *handle,
1052	uint32_t virtual_addr_low,
1053	uint32_t virtual_addr_hi,
1054	uint32_t mc_addr_low,
1055	uint32_t mc_addr_hi,
1056	uint32_t size)
1057	{
1058	struct pp_hwmgr *hwmgr = handle;
1059	int ret = 0;
1060
1061	ret = pp_check(hwmgr);
1062
1063	if (ret)
1064	return ret;
1065
1066	if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
1067	pr_info("%s was not implemented.\n", __func__);
1068	return -EINVAL;
1069	}
1070
1071	mutex_lock(&hwmgr->smu_lock);
1072
1073	ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low,
1074	virtual_addr_hi, mc_addr_low, mc_addr_hi,
1075	size);
1076
1077	mutex_unlock(&hwmgr->smu_lock);
1078
1079	return ret;
1080	}
1081
1082	static int pp_set_power_limit(void *handle, uint32_t limit)	955	static int pp_set_power_limit(void *handle, uint32_t limit)
1083	{	956	{
1084	struct pp_hwmgr *hwmgr = handle;	957	struct pp_hwmgr *hwmgr = handle;
1085	int ret = 0;
1086		958
1087	ret = pp_check(hwmgr);	959	if (!hwmgr \|\| !hwmgr->pm_en)
1088		960	return -EINVAL;
1089	if (ret)
1090	return ret;
1091		961
1092	if (hwmgr->hwmgr_func->set_power_limit == NULL) {	962	if (hwmgr->hwmgr_func->set_power_limit == NULL) {
1093	pr_info("%s was not implemented.\n", __func__);	963	pr_info("%s was not implemented.\n", __func__);
@@ -1104,20 +974,14 @@ static int pp_set_power_limit(void *handle, uint32_t limit) · 10 unmodified lines
1104	hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);	974	hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
1105	hwmgr->power_limit = limit;	975	hwmgr->power_limit = limit;
1106	mutex_unlock(&hwmgr->smu_lock);	976	mutex_unlock(&hwmgr->smu_lock);
1107	return ret;	977	return 0;
1108	}	978	}
1109		979
1110	static int pp_get_power_limit(void handle, uint32_t limit, bool default_limit)	980	static int pp_get_power_limit(void handle, uint32_t limit, bool default_limit)
1111	{	981	{
1112	struct pp_hwmgr *hwmgr = handle;	982	struct pp_hwmgr *hwmgr = handle;
1113	int ret = 0;
1114
1115	ret = pp_check(hwmgr);
1116		983
1117	if (ret)	984	if (!hwmgr \|\| !hwmgr->pm_en \|\|!limit)
1118	return ret;
1119
1120	if (limit == NULL)
1121	return -EINVAL;	985	return -EINVAL;
1122		986
1123	mutex_lock(&hwmgr->smu_lock);	987	mutex_lock(&hwmgr->smu_lock);
@@ -1129,19 +993,16 @@ static int pp_get_power_limit(void handle, uint32_t limit, bool default_limit) · 5 unmodified lines
1129		993
1130	mutex_unlock(&hwmgr->smu_lock);	994	mutex_unlock(&hwmgr->smu_lock);
1131		995
1132	return ret;	996	return 0;
1133	}	997	}
1134		998
1135	static int pp_display_configuration_change(void *handle,	999	static int pp_display_configuration_change(void *handle,
1136	const struct amd_pp_display_configuration *display_config)	1000	const struct amd_pp_display_configuration *display_config)
1137	{	1001	{
1138	struct pp_hwmgr *hwmgr = handle;	1002	struct pp_hwmgr *hwmgr = handle;
1139	int ret = 0;
1140		1003
1141	ret = pp_check(hwmgr);	1004	if (!hwmgr \|\| !hwmgr->pm_en)
1142		1005	return -EINVAL;
1143	if (ret)
1144	return ret;
1145		1006
1146	mutex_lock(&hwmgr->smu_lock);	1007	mutex_lock(&hwmgr->smu_lock);
1147	phm_store_dal_configuration_data(hwmgr, display_config);	1008	phm_store_dal_configuration_data(hwmgr, display_config);
@@ -1155,12 +1016,7 @@ static int pp_get_display_power_level(void *handle, · 7 unmodified lines
1155	struct pp_hwmgr *hwmgr = handle;	1016	struct pp_hwmgr *hwmgr = handle;
1156	int ret = 0;	1017	int ret = 0;
1157		1018
1158	ret = pp_check(hwmgr);	1019	if (!hwmgr \|\| !hwmgr->pm_en \|\|!output)
1159
1160	if (ret)
1161	return ret;
1162
1163	if (output == NULL)
1164	return -EINVAL;	1020	return -EINVAL;
1165		1021
1166	mutex_lock(&hwmgr->smu_lock);	1022	mutex_lock(&hwmgr->smu_lock);
@@ -1177,10 +1033,8 @@ static int pp_get_current_clocks(void *handle, · 10 unmodified lines
1177	struct pp_hwmgr *hwmgr = handle;	1033	struct pp_hwmgr *hwmgr = handle;
1178	int ret = 0;	1034	int ret = 0;
1179		1035
1180	ret = pp_check(hwmgr);	1036	if (!hwmgr \|\| !hwmgr->pm_en)
1181		1037	return -EINVAL;
1182	if (ret)
1183	return ret;
1184		1038
1185	mutex_lock(&hwmgr->smu_lock);	1039	mutex_lock(&hwmgr->smu_lock);
1186		1040
@@ -1225,10 +1079,8 @@ static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struc · 38 unmodified lines
1225	struct pp_hwmgr *hwmgr = handle;	1079	struct pp_hwmgr *hwmgr = handle;
1226	int ret = 0;	1080	int ret = 0;
1227		1081
1228	ret = pp_check(hwmgr);	1082	if (!hwmgr \|\| !hwmgr->pm_en)
1229		1083	return -EINVAL;
1230	if (ret)
1231	return ret;
1232		1084
1233	if (clocks == NULL)	1085	if (clocks == NULL)
1234	return -EINVAL;	1086	return -EINVAL;
@@ -1246,11 +1098,7 @@ static int pp_get_clock_by_type_with_latency(void *handle, · 11 unmodified lines
1246	struct pp_hwmgr *hwmgr = handle;	1098	struct pp_hwmgr *hwmgr = handle;
1247	int ret = 0;	1099	int ret = 0;
1248		1100
1249	ret = pp_check(hwmgr);	1101	if (!hwmgr \|\| !hwmgr->pm_en \|\|!clocks)
1250	if (ret)
1251	return ret;
1252
1253	if (!clocks)
1254	return -EINVAL;	1102	return -EINVAL;
1255		1103
1256	mutex_lock(&hwmgr->smu_lock);	1104	mutex_lock(&hwmgr->smu_lock);
@@ -1266,11 +1114,7 @@ static int pp_get_clock_by_type_with_voltage(void *handle, · 9 unmodified lines
1266	struct pp_hwmgr *hwmgr = handle;	1114	struct pp_hwmgr *hwmgr = handle;
1267	int ret = 0;	1115	int ret = 0;
1268		1116
1269	ret = pp_check(hwmgr);	1117	if (!hwmgr \|\| !hwmgr->pm_en \|\|!clocks)
1270	if (ret)
1271	return ret;
1272
1273	if (!clocks)
1274	return -EINVAL;	1118	return -EINVAL;
1275		1119
1276	mutex_lock(&hwmgr->smu_lock);	1120	mutex_lock(&hwmgr->smu_lock);
@@ -1287,11 +1131,7 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle, · 10 unmodified lines
1287	struct pp_hwmgr *hwmgr = handle;	1131	struct pp_hwmgr *hwmgr = handle;
1288	int ret = 0;	1132	int ret = 0;
1289		1133
1290	ret = pp_check(hwmgr);	1134	if (!hwmgr \|\| !hwmgr->pm_en \|\|!wm_with_clock_ranges)
1291	if (ret)
1292	return ret;
1293
1294	if (!wm_with_clock_ranges)
1295	return -EINVAL;	1135	return -EINVAL;
1296		1136
1297	mutex_lock(&hwmgr->smu_lock);	1137	mutex_lock(&hwmgr->smu_lock);
@@ -1308,11 +1148,7 @@ static int pp_display_clock_voltage_request(void *handle, · 10 unmodified lines
1308	struct pp_hwmgr *hwmgr = handle;	1148	struct pp_hwmgr *hwmgr = handle;
1309	int ret = 0;	1149	int ret = 0;
1310		1150
1311	ret = pp_check(hwmgr);	1151	if (!hwmgr \|\| !hwmgr->pm_en \|\|!clock)
1312	if (ret)
1313	return ret;
1314
1315	if (!clock)
1316	return -EINVAL;	1152	return -EINVAL;
1317		1153
1318	mutex_lock(&hwmgr->smu_lock);	1154	mutex_lock(&hwmgr->smu_lock);
@@ -1328,12 +1164,7 @@ static int pp_get_display_mode_validation_clocks(void *handle, · 9 unmodified lines
1328	struct pp_hwmgr *hwmgr = handle;	1164	struct pp_hwmgr *hwmgr = handle;
1329	int ret = 0;	1165	int ret = 0;
1330		1166
1331	ret = pp_check(hwmgr);	1167	if (!hwmgr \|\| !hwmgr->pm_en \|\|!clocks)
1332
1333	if (ret)
1334	return ret;
1335
1336	if (clocks == NULL)
1337	return -EINVAL;	1168	return -EINVAL;
1338		1169
1339	mutex_lock(&hwmgr->smu_lock);	1170	mutex_lock(&hwmgr->smu_lock);
@@ -1348,12 +1179,9 @@ static int pp_get_display_mode_validation_clocks(void *handle, · 8 unmodified lines
1348	static int pp_set_mmhub_powergating_by_smu(void *handle)	1179	static int pp_set_mmhub_powergating_by_smu(void *handle)
1349	{	1180	{
1350	struct pp_hwmgr *hwmgr = handle;	1181	struct pp_hwmgr *hwmgr = handle;
1351	int ret = 0;
1352		1182
1353	ret = pp_check(hwmgr);	1183	if (!hwmgr \|\| !hwmgr->pm_en)
1354		1184	return -EINVAL;
1355	if (ret)
1356	return ret;
1357		1185
1358	if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {	1186	if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
1359	pr_info("%s was not implemented.\n", __func__);	1187	pr_info("%s was not implemented.\n", __func__);
@@ -1390,7 +1218,6 @@ static const struct amd_pm_funcs pp_dpm_funcs = { · 30 unmodified lines
1390	.get_vce_clock_state = pp_dpm_get_vce_clock_state,	1218	.get_vce_clock_state = pp_dpm_get_vce_clock_state,
1391	.switch_power_profile = pp_dpm_switch_power_profile,	1219	.switch_power_profile = pp_dpm_switch_power_profile,
1392	.set_clockgating_by_smu = pp_set_clockgating_by_smu,	1220	.set_clockgating_by_smu = pp_set_clockgating_by_smu,
1393	.notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
1394	.get_power_profile_mode = pp_get_power_profile_mode,	1221	.get_power_profile_mode = pp_get_power_profile_mode,
1395	.set_power_profile_mode = pp_set_power_profile_mode,	1222	.set_power_profile_mode = pp_set_power_profile_mode,
1396	.odn_edit_dpm_table = pp_odn_edit_dpm_table,	1223	.odn_edit_dpm_table = pp_odn_edit_dpm_table,

drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c+5−17

 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 {
-	int ret = 1;
+	int ret = -EINVAL;;
-	bool enabled;
 	PHM_FUNC_CHECK(hwmgr);
 	if (smum_is_dpm_running(hwmgr)) {
 	if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
 		ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
-	enabled = ret == 0;
-	cgs_notify_dpm_enabled(hwmgr->device, enabled);
 	return ret;
 }
 int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 {
-	int ret = -1;
+	int ret = -EINVAL;
-	bool enabled;
 	PHM_FUNC_CHECK(hwmgr);
 	if (hwmgr->hwmgr_func->dynamic_state_management_disable)
 		ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
-	enabled = ret == 0 ? false : true;
-	cgs_notify_dpm_enabled(hwmgr->device, enabled);
 	return ret;
 }
 	if (display_config == NULL)
 		return -EINVAL;
-	hwmgr->display_config = *display_config;
 	if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)
-		hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, hwmgr->display_config.min_dcef_deep_sleep_set_clk);
+		hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
-	for (index = 0; index < hwmgr->display_config.num_path_including_non_display; index++) {
+	for (index = 0; index < display_config->num_path_including_non_display; index++) {
-		if (hwmgr->display_config.displays[index].controller_id != 0)
+		if (display_config->displays[index].controller_id != 0)
 			number_of_active_display++;
 	}

drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c+72−18

 extern const struct pp_smumgr_func tonga_smu_funcs;
 extern const struct pp_smumgr_func fiji_smu_funcs;
 extern const struct pp_smumgr_func polaris10_smu_funcs;
+extern const struct pp_smumgr_func vegam_smu_funcs;
 extern const struct pp_smumgr_func vega10_smu_funcs;
 extern const struct pp_smumgr_func vega12_smu_funcs;
 extern const struct pp_smumgr_func smu10_smu_funcs;
 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 {
-	if (hwmgr == NULL)
+	if (!hwmgr)
 		return -EINVAL;
 	hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
 		hwmgr->smumgr_funcs = &ci_smu_funcs;
 		ci_set_asic_special_caps(hwmgr);
 		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
-					PP_ENABLE_GFX_CG_THRU_SMU);
+					 PP_ENABLE_GFX_CG_THRU_SMU |
+					 PP_GFXOFF_MASK);
 		hwmgr->pp_table_version = PP_TABLE_V0;
 		hwmgr->od_enabled = false;
 		smu7_init_function_pointers(hwmgr);
 	case AMDGPU_FAMILY_CZ:
 		hwmgr->od_enabled = false;
 		hwmgr->smumgr_funcs = &smu8_smu_funcs;
+		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 		smu8_init_function_pointers(hwmgr);
 		break;
 	case AMDGPU_FAMILY_VI:
+		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 		switch (hwmgr->chip_id) {
 		case CHIP_TOPAZ:
 			hwmgr->smumgr_funcs = &iceland_smu_funcs;
 			polaris_set_asic_special_caps(hwmgr);
 			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
 			break;
+		case CHIP_VEGAM:
+			hwmgr->smumgr_funcs = &vegam_smu_funcs;
+			polaris_set_asic_special_caps(hwmgr);
+			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
+			break;
 		default:
 			return -EINVAL;
 		}
 		smu7_init_function_pointers(hwmgr);
 		break;
 	case AMDGPU_FAMILY_AI:
+		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 		switch (hwmgr->chip_id) {
 		case CHIP_VEGA10:
 			hwmgr->smumgr_funcs = &vega10_smu_funcs;
 	return 0;
 }
+int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
+{
+	if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
+		return -EINVAL;
+	phm_register_irq_handlers(hwmgr);
+	return hwmgr->smumgr_funcs->smu_init(hwmgr);
+}
+int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
+{
+	if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
+		hwmgr->smumgr_funcs->smu_fini(hwmgr);
+	return 0;
+}
 int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
 {
 	int ret = 0;
-	if (hwmgr == NULL)
+	if (!hwmgr || !hwmgr->smumgr_funcs)
 		return -EINVAL;
-	if (hwmgr->pptable_func == NULL ||
+	if (hwmgr->smumgr_funcs->start_smu) {
-	    hwmgr->pptable_func->pptable_init == NULL ||
+		ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
-	    hwmgr->hwmgr_func->backend_init == NULL)
+		if (ret) {
-		return -EINVAL;
+			pr_err("smc start failed\n");
+			return -EINVAL;
+		}
+	}
+	if (!hwmgr->pm_en)
+		return 0;
+	if (!hwmgr->pptable_func ||
+	    !hwmgr->pptable_func->pptable_init ||
+	    !hwmgr->hwmgr_func->backend_init) {
+		hwmgr->pm_en = false;
+		pr_info("dpm not supported \n");
+		return 0;
+	}
 	ret = hwmgr->pptable_func->pptable_init(hwmgr);
 	if (ret)
 		goto err;
+	((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
+				hwmgr->thermal_controller.fanInfo.bNoFan;
 	ret = hwmgr->hwmgr_func->backend_init(hwmgr);
 	if (ret)
 		goto err1;
 	if (ret)
 		goto err2;
+	((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;
 	return 0;
 err2:
 	if (hwmgr->hwmgr_func->backend_fini)
 	if (hwmgr->pptable_func->pptable_fini)
 		hwmgr->pptable_func->pptable_fini(hwmgr);
 err:
-	pr_err("amdgpu: powerplay initialization failed\n");
 	return ret;
 }
 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
 {
-	if (hwmgr == NULL)
+	if (!hwmgr || !hwmgr->pm_en)
-		return -EINVAL;
+		return 0;
 	phm_stop_thermal_controller(hwmgr);
 	psm_set_boot_states(hwmgr);
 	return psm_fini_power_state_table(hwmgr);
 }
-int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
+int hwmgr_suspend(struct pp_hwmgr *hwmgr)
 {
 	int ret = 0;
-	if (hwmgr == NULL)
+	if (!hwmgr || !hwmgr->pm_en)
-		return -EINVAL;
+		return 0;
 	phm_disable_smc_firmware_ctf(hwmgr);
 	ret = psm_set_boot_states(hwmgr);
 	return ret;
 }
-int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
+int hwmgr_resume(struct pp_hwmgr *hwmgr)
 {
 	int ret = 0;
-	if (hwmgr == NULL)
+	if (!hwmgr)
 		return -EINVAL;
+	if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
+		if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
+			pr_err("smc start failed\n");
+			return -EINVAL;
+		}
+	}
+	if (!hwmgr->pm_en)
+		return 0;
 	ret = phm_setup_asic(hwmgr);
 	if (ret)
 		return ret;
 	if (ret)
 		return ret;
 	ret = phm_start_thermal_controller(hwmgr);
-	if (ret)
-		return ret;
 	ret |= psm_set_performance_states(hwmgr);
 	if (ret)
 		return ret;

drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c+1−1

@@ -46,7 +46,7 @@ int psm_init_power_state_table(struct pp_hwmgr *hwmgr) · 45 unmodified lines
46	sizeof(struct pp_power_state);	46	sizeof(struct pp_power_state);
47		47
48	if (table_entries == 0 \|\| size == 0) {	48	if (table_entries == 0 \|\| size == 0) {
49	pr_warn("Please check whether power state management is suppported on this asic\n");	49	pr_warn("Please check whether power state management is supported on this asic\n");
50	return 0;	50	return 0;
51	}	51	}
52		52

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c+135−69

@@ -23,7 +23,8 @@ · 22 unmodified lines
23	#include "pp_debug.h"	23	#include "pp_debug.h"
24	#include <linux/module.h>	24	#include <linux/module.h>
25	#include <linux/slab.h>	25	#include <linux/slab.h>
26		26	#include <linux/delay.h>
		27	#include "atom.h"
27	#include "ppatomctrl.h"	28	#include "ppatomctrl.h"
28	#include "atombios.h"	29	#include "atombios.h"
29	#include "cgs_common.h"	30	#include "cgs_common.h"
@@ -128,7 +129,6 @@ static int atomctrl_set_mc_reg_address_table( · 98 unmodified lines
128	return 0;	129	return 0;
129	}	130	}
130		131
131
132	int atomctrl_initialize_mc_reg_table(	132	int atomctrl_initialize_mc_reg_table(
133	struct pp_hwmgr *hwmgr,	133	struct pp_hwmgr *hwmgr,
134	uint8_t module_index,	134	uint8_t module_index,
@@ -141,7 +141,7 @@ int atomctrl_initialize_mc_reg_table( · 6 unmodified lines
141	u16 size;	141	u16 size;
142		142
143	vram_info = (ATOM_VRAM_INFO_HEADER_V2_1 *)	143	vram_info = (ATOM_VRAM_INFO_HEADER_V2_1 *)
144	cgs_atom_get_data_table(hwmgr->device,	144	smu_atom_get_data_table(hwmgr->adev,
145	GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev);	145	GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev);
146		146
147	if (module_index >= vram_info->ucNumOfVRAMModule) {	147	if (module_index >= vram_info->ucNumOfVRAMModule) {
@@ -174,6 +174,8 @@ int atomctrl_set_engine_dram_timings_rv770( · 26 unmodified lines
174	uint32_t engine_clock,	174	uint32_t engine_clock,
175	uint32_t memory_clock)	175	uint32_t memory_clock)
176	{	176	{
		177	struct amdgpu_device *adev = hwmgr->adev;
		178
177	SET_ENGINE_CLOCK_PS_ALLOCATION engine_clock_parameters;	179	SET_ENGINE_CLOCK_PS_ALLOCATION engine_clock_parameters;
178		180
179	/* They are both in 10KHz Units. */	181	/* They are both in 10KHz Units. */
@@ -184,9 +186,10 @@ int atomctrl_set_engine_dram_timings_rv770( · 4 unmodified lines
184	/* in 10 khz units.*/	186	/* in 10 khz units.*/
185	engine_clock_parameters.sReserved.ulClock =	187	engine_clock_parameters.sReserved.ulClock =
186	cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK);	188	cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK);
187	return cgs_atom_exec_cmd_table(hwmgr->device,	189
		190	return amdgpu_atom_execute_table(adev->mode_info.atom_context,
188	GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),	191	GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),
189	&engine_clock_parameters);	192	(uint32_t *)&engine_clock_parameters);
190	}	193	}
191		194
192	/**	195	/**
@@ -203,7 +206,7 @@ static ATOM_VOLTAGE_OBJECT_INFO get_voltage_info_table(void device) · 10 unmodified lines
203	union voltage_object_info *voltage_info;	206	union voltage_object_info *voltage_info;
204		207
205	voltage_info = (union voltage_object_info *)	208	voltage_info = (union voltage_object_info *)
206	cgs_atom_get_data_table(device, index,	209	smu_atom_get_data_table(device, index,
207	&size, &frev, &crev);	210	&size, &frev, &crev);
208		211
209	if (voltage_info != NULL)	212	if (voltage_info != NULL)
@@ -247,16 +250,16 @@ int atomctrl_get_memory_pll_dividers_si( · 37 unmodified lines
247	pp_atomctrl_memory_clock_param *mpll_param,	250	pp_atomctrl_memory_clock_param *mpll_param,
248	bool strobe_mode)	251	bool strobe_mode)
249	{	252	{
		253	struct amdgpu_device *adev = hwmgr->adev;
250	COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 mpll_parameters;	254	COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 mpll_parameters;
251	int result;	255	int result;
252		256
253	mpll_parameters.ulClock = cpu_to_le32(clock_value);	257	mpll_parameters.ulClock = cpu_to_le32(clock_value);
254	mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0);	258	mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0);
255		259
256	result = cgs_atom_exec_cmd_table	260	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
257	(hwmgr->device,
258	GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),	261	GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
259	&mpll_parameters);	262	(uint32_t *)&mpll_parameters);
260		263
261	if (0 == result) {	264	if (0 == result) {
262	mpll_param->mpll_fb_divider.clk_frac =	265	mpll_param->mpll_fb_divider.clk_frac =
@@ -295,14 +298,15 @@ int atomctrl_get_memory_pll_dividers_si( · 32 unmodified lines
295	int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,	298	int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
296	uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param)	299	uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param)
297	{	300	{
		301	struct amdgpu_device *adev = hwmgr->adev;
298	COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters;	302	COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters;
299	int result;	303	int result;
300		304
301	mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);	305	mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
302		306
303	result = cgs_atom_exec_cmd_table(hwmgr->device,	307	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
304	GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),	308	GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
305	&mpll_parameters);	309	(uint32_t *)&mpll_parameters);
306		310
307	if (!result)	311	if (!result)
308	mpll_param->mpll_post_divider =	312	mpll_param->mpll_post_divider =
@@ -311,19 +315,49 @@ int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr, · 2 unmodified lines
311	return result;	315	return result;
312	}	316	}
313		317
		318	int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
		319	uint32_t clock_value,
		320	pp_atomctrl_memory_clock_param_ai *mpll_param)
		321	{
		322	struct amdgpu_device *adev = hwmgr->adev;
		323	COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {0};
		324	int result;
		325
		326	mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
		327
		328	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
		329	GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
		330	(uint32_t *)&mpll_parameters);
		331
		332	/* VEGAM's mpll takes sometime to finish computing */
		333	udelay(10);
		334
		335	if (!result) {
		336	mpll_param->ulMclk_fcw_int =
		337	le16_to_cpu(mpll_parameters.usMclk_fcw_int);
		338	mpll_param->ulMclk_fcw_frac =
		339	le16_to_cpu(mpll_parameters.usMclk_fcw_frac);
		340	mpll_param->ulClock =
		341	le32_to_cpu(mpll_parameters.ulClock.ulClock);
		342	mpll_param->ulPostDiv = mpll_parameters.ulClock.ucPostDiv;
		343	}
		344
		345	return result;
		346	}
		347
314	int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,	348	int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
315	uint32_t clock_value,	349	uint32_t clock_value,
316	pp_atomctrl_clock_dividers_kong *dividers)	350	pp_atomctrl_clock_dividers_kong *dividers)
317	{	351	{
		352	struct amdgpu_device *adev = hwmgr->adev;
318	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters;	353	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters;
319	int result;	354	int result;
320		355
321	pll_parameters.ulClock = cpu_to_le32(clock_value);	356	pll_parameters.ulClock = cpu_to_le32(clock_value);
322		357
323	result = cgs_atom_exec_cmd_table	358	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
324	(hwmgr->device,
325	GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),	359	GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
326	&pll_parameters);	360	(uint32_t *)&pll_parameters);
327		361
328	if (0 == result) {	362	if (0 == result) {
329	dividers->pll_post_divider = pll_parameters.ucPostDiv;	363	dividers->pll_post_divider = pll_parameters.ucPostDiv;
@@ -338,16 +372,16 @@ int atomctrl_get_engine_pll_dividers_vi( · 8 unmodified lines
338	uint32_t clock_value,	372	uint32_t clock_value,
339	pp_atomctrl_clock_dividers_vi *dividers)	373	pp_atomctrl_clock_dividers_vi *dividers)
340	{	374	{
		375	struct amdgpu_device *adev = hwmgr->adev;
341	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;	376	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
342	int result;	377	int result;
343		378
344	pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);	379	pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
345	pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;	380	pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
346		381
347	result = cgs_atom_exec_cmd_table	382	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
348	(hwmgr->device,
349	GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),	383	GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
350	&pll_patameters);	384	(uint32_t *)&pll_patameters);
351		385
352	if (0 == result) {	386	if (0 == result) {
353	dividers->pll_post_divider =	387	dividers->pll_post_divider =
@@ -375,16 +409,16 @@ int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, · 21 unmodified lines
375	uint32_t clock_value,	409	uint32_t clock_value,
376	pp_atomctrl_clock_dividers_ai *dividers)	410	pp_atomctrl_clock_dividers_ai *dividers)
377	{	411	{
		412	struct amdgpu_device *adev = hwmgr->adev;
378	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters;	413	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters;
379	int result;	414	int result;
380		415
381	pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);	416	pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
382	pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;	417	pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
383		418
384	result = cgs_atom_exec_cmd_table	419	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
385	(hwmgr->device,
386	GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),	420	GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
387	&pll_patameters);	421	(uint32_t *)&pll_patameters);
388		422
389	if (0 == result) {	423	if (0 == result) {
390	dividers->usSclk_fcw_frac = le16_to_cpu(pll_patameters.usSclk_fcw_frac);	424	dividers->usSclk_fcw_frac = le16_to_cpu(pll_patameters.usSclk_fcw_frac);
@@ -407,6 +441,7 @@ int atomctrl_get_dfs_pll_dividers_vi( · 16 unmodified lines
407	uint32_t clock_value,	441	uint32_t clock_value,
408	pp_atomctrl_clock_dividers_vi *dividers)	442	pp_atomctrl_clock_dividers_vi *dividers)
409	{	443	{
		444	struct amdgpu_device *adev = hwmgr->adev;
410	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;	445	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
411	int result;	446	int result;
412		447
@@ -414,10 +449,9 @@ int atomctrl_get_dfs_pll_dividers_vi( · 1 unmodified line
414	pll_patameters.ulClock.ucPostDiv =	449	pll_patameters.ulClock.ucPostDiv =
415	COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK;	450	COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK;
416		451
417	result = cgs_atom_exec_cmd_table	452	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
418	(hwmgr->device,
419	GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),	453	GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
420	&pll_patameters);	454	(uint32_t *)&pll_patameters);
421		455
422	if (0 == result) {	456	if (0 == result) {
423	dividers->pll_post_divider =	457	dividers->pll_post_divider =
@@ -452,7 +486,7 @@ uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr) · 28 unmodified lines
452	uint32_t clock;	486	uint32_t clock;
453		487
454	fw_info = (ATOM_FIRMWARE_INFO *)	488	fw_info = (ATOM_FIRMWARE_INFO *)
455	cgs_atom_get_data_table(hwmgr->device,	489	smu_atom_get_data_table(hwmgr->adev,
456	GetIndexIntoMasterTable(DATA, FirmwareInfo),	490	GetIndexIntoMasterTable(DATA, FirmwareInfo),
457	&size, &frev, &crev);	491	&size, &frev, &crev);
458		492
@@ -476,7 +510,7 @@ bool atomctrl_is_voltage_controlled_by_gpio_v3( · 17 unmodified lines
476	uint8_t voltage_mode)	510	uint8_t voltage_mode)
477	{	511	{
478	ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =	512	ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
479	(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);	513	(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
480	bool ret;	514	bool ret;
481		515
482	PP_ASSERT_WITH_CODE((NULL != voltage_info),	516	PP_ASSERT_WITH_CODE((NULL != voltage_info),
@@ -495,7 +529,7 @@ int atomctrl_get_voltage_table_v3( · 12 unmodified lines
495	pp_atomctrl_voltage_table *voltage_table)	529	pp_atomctrl_voltage_table *voltage_table)
496	{	530	{
497	ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =	531	ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
498	(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);	532	(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
499	const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;	533	const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
500	unsigned int i;	534	unsigned int i;
501		535
@@ -572,7 +606,7 @@ static ATOM_GPIO_PIN_LUT get_gpio_lookup_table(void device) · 70 unmodified lines
572	void *table_address;	606	void *table_address;
573		607
574	table_address = (ATOM_GPIO_PIN_LUT *)	608	table_address = (ATOM_GPIO_PIN_LUT *)
575	cgs_atom_get_data_table(device,	609	smu_atom_get_data_table(device,
576	GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT),	610	GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT),
577	&size, &frev, &crev);	611	&size, &frev, &crev);
578		612
@@ -592,7 +626,7 @@ bool atomctrl_get_pp_assign_pin( · 13 unmodified lines
592	{	626	{
593	bool bRet = false;	627	bool bRet = false;
594	ATOM_GPIO_PIN_LUT *gpio_lookup_table =	628	ATOM_GPIO_PIN_LUT *gpio_lookup_table =
595	get_gpio_lookup_table(hwmgr->device);	629	get_gpio_lookup_table(hwmgr->adev);
596		630
597	PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table),	631	PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table),
598	"Could not find GPIO lookup Table in BIOS.", return false);	632	"Could not find GPIO lookup Table in BIOS.", return false);
@@ -613,7 +647,7 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 14 unmodified lines
613	bool debug)	647	bool debug)
614	{	648	{
615	ATOM_ASIC_PROFILING_INFO_V3_4 *getASICProfilingInfo;	649	ATOM_ASIC_PROFILING_INFO_V3_4 *getASICProfilingInfo;
616		650	struct amdgpu_device *adev = hwmgr->adev;
617	EFUSE_LINEAR_FUNC_PARAM sRO_fuse;	651	EFUSE_LINEAR_FUNC_PARAM sRO_fuse;
618	EFUSE_LINEAR_FUNC_PARAM sCACm_fuse;	652	EFUSE_LINEAR_FUNC_PARAM sCACm_fuse;
619	EFUSE_LINEAR_FUNC_PARAM sCACb_fuse;	653	EFUSE_LINEAR_FUNC_PARAM sCACb_fuse;
@@ -640,7 +674,7 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 20 unmodified lines
640	int result;	674	int result;
641		675
642	getASICProfilingInfo = (ATOM_ASIC_PROFILING_INFO_V3_4 *)	676	getASICProfilingInfo = (ATOM_ASIC_PROFILING_INFO_V3_4 *)
643	cgs_atom_get_data_table(hwmgr->device,	677	smu_atom_get_data_table(hwmgr->adev,
644	GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),	678	GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
645	NULL, NULL, NULL);	679	NULL, NULL, NULL);
646		680
@@ -706,9 +740,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 59 unmodified lines
706		740
707	sOutput_FuseValues.sEfuse = sInput_FuseValues;	741	sOutput_FuseValues.sEfuse = sInput_FuseValues;
708		742
709	result = cgs_atom_exec_cmd_table(hwmgr->device,	743	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
710	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),	744	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
711	&sOutput_FuseValues);	745	(uint32_t *)&sOutput_FuseValues);
712		746
713	if (result)	747	if (result)
714	return result;	748	return result;
@@ -727,9 +761,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 12 unmodified lines
727		761
728	sOutput_FuseValues.sEfuse = sInput_FuseValues;	762	sOutput_FuseValues.sEfuse = sInput_FuseValues;
729		763
730	result = cgs_atom_exec_cmd_table(hwmgr->device,	764	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
731	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),	765	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
732	&sOutput_FuseValues);	766	(uint32_t *)&sOutput_FuseValues);
733		767
734	if (result)	768	if (result)
735	return result;	769	return result;
@@ -747,9 +781,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 11 unmodified lines
747	sInput_FuseValues.ucBitLength = sCACb_fuse.ucEfuseLength;	781	sInput_FuseValues.ucBitLength = sCACb_fuse.ucEfuseLength;
748	sOutput_FuseValues.sEfuse = sInput_FuseValues;	782	sOutput_FuseValues.sEfuse = sInput_FuseValues;
749		783
750	result = cgs_atom_exec_cmd_table(hwmgr->device,	784	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
751	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),	785	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
752	&sOutput_FuseValues);	786	(uint32_t *)&sOutput_FuseValues);
753		787
754	if (result)	788	if (result)
755	return result;	789	return result;
@@ -768,9 +802,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 12 unmodified lines
768		802
769	sOutput_FuseValues.sEfuse = sInput_FuseValues;	803	sOutput_FuseValues.sEfuse = sInput_FuseValues;
770		804
771	result = cgs_atom_exec_cmd_table(hwmgr->device,	805	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
772	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),	806	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
773	&sOutput_FuseValues);	807	(uint32_t *)&sOutput_FuseValues);
774		808
775	if (result)	809	if (result)
776	return result;	810	return result;
@@ -790,9 +824,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 13 unmodified lines
790		824
791	sOutput_FuseValues.sEfuse = sInput_FuseValues;	825	sOutput_FuseValues.sEfuse = sInput_FuseValues;
792		826
793	result = cgs_atom_exec_cmd_table(hwmgr->device,	827	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
794	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),	828	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
795	&sOutput_FuseValues);	829	(uint32_t *)&sOutput_FuseValues);
796	if (result)	830	if (result)
797	return result;	831	return result;
798		832
@@ -811,9 +845,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 12 unmodified lines
811	sInput_FuseValues.ucBitLength = sKv_b_fuse.ucEfuseLength;	845	sInput_FuseValues.ucBitLength = sKv_b_fuse.ucEfuseLength;
812	sOutput_FuseValues.sEfuse = sInput_FuseValues;	846	sOutput_FuseValues.sEfuse = sInput_FuseValues;
813		847
814	result = cgs_atom_exec_cmd_table(hwmgr->device,	848	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
815	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),	849	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
816	&sOutput_FuseValues);	850	(uint32_t *)&sOutput_FuseValues);
817		851
818	if (result)	852	if (result)
819	return result;	853	return result;
@@ -842,9 +876,9 @@ int atomctrl_calculate_voltage_evv_on_sclk( · 22 unmodified lines
842		876
843	sOutput_FuseValues.sEfuse = sInput_FuseValues;	877	sOutput_FuseValues.sEfuse = sInput_FuseValues;
844		878
845	result = cgs_atom_exec_cmd_table(hwmgr->device,	879	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
846	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),	880	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
847	&sOutput_FuseValues);	881	(uint32_t *)&sOutput_FuseValues);
848		882
849	if (result)	883	if (result)
850	return result;	884	return result;
@@ -1053,8 +1087,9 @@ int atomctrl_get_voltage_evv_on_sclk( · 202 unmodified lines
1053	uint32_t sclk, uint16_t virtual_voltage_Id,	1087	uint32_t sclk, uint16_t virtual_voltage_Id,
1054	uint16_t *voltage)	1088	uint16_t *voltage)
1055	{	1089	{
1056	int result;	1090	struct amdgpu_device *adev = hwmgr->adev;
1057	GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;	1091	GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
		1092	int result;
1058		1093
1059	get_voltage_info_param_space.ucVoltageType =	1094	get_voltage_info_param_space.ucVoltageType =
1060	voltage_type;	1095	voltage_type;
@@ -1065,9 +1100,9 @@ int atomctrl_get_voltage_evv_on_sclk( · 4 unmodified lines
1065	get_voltage_info_param_space.ulSCLKFreq =	1100	get_voltage_info_param_space.ulSCLKFreq =
1066	cpu_to_le32(sclk);	1101	cpu_to_le32(sclk);
1067		1102
1068	result = cgs_atom_exec_cmd_table(hwmgr->device,	1103	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1069	GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),	1104	GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
1070	&get_voltage_info_param_space);	1105	(uint32_t *)&get_voltage_info_param_space);
1071		1106
1072	if (0 != result)	1107	if (0 != result)
1073	return result;	1108	return result;
@@ -1088,9 +1123,10 @@ int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, · 14 unmodified lines
1088	uint16_t virtual_voltage_id,	1123	uint16_t virtual_voltage_id,
1089	uint16_t *voltage)	1124	uint16_t *voltage)
1090	{	1125	{
		1126	struct amdgpu_device *adev = hwmgr->adev;
		1127	GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
1091	int result;	1128	int result;
1092	int entry_id;	1129	int entry_id;
1093	GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
1094		1130
1095	/* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */	1131	/* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
1096	for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) {	1132	for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) {
@@ -1111,9 +1147,9 @@ int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, · 14 unmodified lines
1111	get_voltage_info_param_space.ulSCLKFreq =	1147	get_voltage_info_param_space.ulSCLKFreq =
1112	cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk);	1148	cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk);
1113		1149
1114	result = cgs_atom_exec_cmd_table(hwmgr->device,	1150	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1115	GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),	1151	GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
1116	&get_voltage_info_param_space);	1152	(uint32_t *)&get_voltage_info_param_space);
1117		1153
1118	if (0 != result)	1154	if (0 != result)
1119	return result;	1155	return result;
@@ -1135,7 +1171,7 @@ uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr) · 15 unmodified lines
1135	u16 size;	1171	u16 size;
1136		1172
1137	fw_info = (ATOM_COMMON_TABLE_HEADER *)	1173	fw_info = (ATOM_COMMON_TABLE_HEADER *)
1138	cgs_atom_get_data_table(hwmgr->device,	1174	smu_atom_get_data_table(hwmgr->adev,
1139	GetIndexIntoMasterTable(DATA, FirmwareInfo),	1175	GetIndexIntoMasterTable(DATA, FirmwareInfo),
1140	&size, &frev, &crev);	1176	&size, &frev, &crev);
1141		1177
@@ -1167,7 +1203,7 @@ static ATOM_ASIC_INTERNAL_SS_INFO asic_internal_ss_get_ss_table(void device) · 25 unmodified lines
1167	u16 size;	1203	u16 size;
1168		1204
1169	table = (ATOM_ASIC_INTERNAL_SS_INFO *)	1205	table = (ATOM_ASIC_INTERNAL_SS_INFO *)
1170	cgs_atom_get_data_table(device,	1206	smu_atom_get_data_table(device,
1171	GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info),	1207	GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info),
1172	&size, &frev, &crev);	1208	&size, &frev, &crev);
1173		1209
@@ -1188,7 +1224,7 @@ static int asic_internal_ss_get_ss_asignment(struct pp_hwmgr *hwmgr, · 14 unmodified lines
1188		1224
1189	memset(ssEntry, 0x00, sizeof(pp_atomctrl_internal_ss_info));	1225	memset(ssEntry, 0x00, sizeof(pp_atomctrl_internal_ss_info));
1190		1226
1191	table = asic_internal_ss_get_ss_table(hwmgr->device);	1227	table = asic_internal_ss_get_ss_table(hwmgr->adev);
1192		1228
1193	if (NULL == table)	1229	if (NULL == table)
1194	return -1;	1230	return -1;
@@ -1260,9 +1296,10 @@ int atomctrl_get_engine_clock_spread_spectrum( · 65 unmodified lines
1260	ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo);	1296	ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo);
1261	}	1297	}
1262		1298
1263	int atomctrl_read_efuse(void *device, uint16_t start_index,	1299	int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
1264	uint16_t end_index, uint32_t mask, uint32_t *efuse)	1300	uint16_t end_index, uint32_t mask, uint32_t *efuse)
1265	{	1301	{
		1302	struct amdgpu_device *adev = hwmgr->adev;
1266	int result;	1303	int result;
1267	READ_EFUSE_VALUE_PARAMETER efuse_param;	1304	READ_EFUSE_VALUE_PARAMETER efuse_param;
1268		1305
@@ -1272,9 +1309,9 @@ int atomctrl_read_efuse(void *device, uint16_t start_index, · 3 unmodified lines
1272	efuse_param.sEfuse.ucBitLength = (uint8_t)	1309	efuse_param.sEfuse.ucBitLength = (uint8_t)
1273	((end_index - start_index) + 1);	1310	((end_index - start_index) + 1);
1274		1311
1275	result = cgs_atom_exec_cmd_table(device,	1312	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1276	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),	1313	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
1277	&efuse_param);	1314	(uint32_t *)&efuse_param);
1278	if (!result)	1315	if (!result)
1279	*efuse = le32_to_cpu(efuse_param.ulEfuseValue) & mask;	1316	*efuse = le32_to_cpu(efuse_param.ulEfuseValue) & mask;
1280		1317
@@ -1284,6 +1321,7 @@ int atomctrl_read_efuse(void *device, uint16_t start_index, · 3 unmodified lines
1284	int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,	1321	int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
1285	uint8_t level)	1322	uint8_t level)
1286	{	1323	{
		1324	struct amdgpu_device *adev = hwmgr->adev;
1287	DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters;	1325	DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters;
1288	int result;	1326	int result;
1289		1327
@@ -1293,10 +1331,9 @@ int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, · 3 unmodified lines
1293	ADJUST_MC_SETTING_PARAM;	1331	ADJUST_MC_SETTING_PARAM;
1294	memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level;	1332	memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level;
1295		1333
1296	result = cgs_atom_exec_cmd_table	1334	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1297	(hwmgr->device,
1298	GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),	1335	GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),
1299	&memory_clock_parameters);	1336	(uint32_t *)&memory_clock_parameters);
1300		1337
1301	return result;	1338	return result;
1302	}	1339	}
@@ -1304,7 +1341,7 @@ int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, · 1 unmodified line
1304	int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,	1341	int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
1305	uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage)	1342	uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage)
1306	{	1343	{
1307		1344	struct amdgpu_device *adev = hwmgr->adev;
1308	int result;	1345	int result;
1309	GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 get_voltage_info_param_space;	1346	GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 get_voltage_info_param_space;
1310		1347
@@ -1313,9 +1350,9 @@ int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_ · 2 unmodified lines
1313	get_voltage_info_param_space.usVoltageLevel = cpu_to_le16(virtual_voltage_Id);	1350	get_voltage_info_param_space.usVoltageLevel = cpu_to_le16(virtual_voltage_Id);
1314	get_voltage_info_param_space.ulSCLKFreq = cpu_to_le32(sclk);	1351	get_voltage_info_param_space.ulSCLKFreq = cpu_to_le32(sclk);
1315		1352
1316	result = cgs_atom_exec_cmd_table(hwmgr->device,	1353	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1317	GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),	1354	GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
1318	&get_voltage_info_param_space);	1355	(uint32_t *)&get_voltage_info_param_space);
1319		1356
1320	if (0 != result)	1357	if (0 != result)
1321	return result;	1358	return result;
@@ -1334,7 +1371,7 @@ int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctr · 12 unmodified lines
1334	u16 size;	1371	u16 size;
1335		1372
1336	ATOM_SMU_INFO_V2_1 *psmu_info =	1373	ATOM_SMU_INFO_V2_1 *psmu_info =
1337	(ATOM_SMU_INFO_V2_1 *)cgs_atom_get_data_table(hwmgr->device,	1374	(ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev,
1338	GetIndexIntoMasterTable(DATA, SMU_Info),	1375	GetIndexIntoMasterTable(DATA, SMU_Info),
1339	&size, &frev, &crev);	1376	&size, &frev, &crev);
1340		1377
@@ -1362,7 +1399,7 @@ int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, · 21 unmodified lines
1362	return -EINVAL;	1399	return -EINVAL;
1363		1400
1364	profile = (ATOM_ASIC_PROFILING_INFO_V3_6 *)	1401	profile = (ATOM_ASIC_PROFILING_INFO_V3_6 *)
1365	cgs_atom_get_data_table(hwmgr->device,	1402	smu_atom_get_data_table(hwmgr->adev,
1366	GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),	1403	GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
1367	NULL, NULL, NULL);	1404	NULL, NULL, NULL);
1368	if (!profile)	1405	if (!profile)
@@ -1402,7 +1439,7 @@ int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, · 33 unmodified lines
1402	uint16_t *load_line)	1439	uint16_t *load_line)
1403	{	1440	{
1404	ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =	1441	ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
1405	(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);	1442	(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
1406		1443
1407	const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;	1444	const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
1408		1445
@@ -1421,16 +1458,17 @@ int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, · 12 unmodified lines
1421		1458
1422	int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr hwmgr, uint16_t virtual_voltage_id)	1459	int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr hwmgr, uint16_t virtual_voltage_id)
1423	{	1460	{
1424	int result;	1461	struct amdgpu_device *adev = hwmgr->adev;
1425	SET_VOLTAGE_PS_ALLOCATION allocation;	1462	SET_VOLTAGE_PS_ALLOCATION allocation;
1426	SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters =	1463	SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters =
1427	(SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage;	1464	(SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage;
		1465	int result;
1428		1466
1429	voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID;	1467	voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1430		1468
1431	result = cgs_atom_exec_cmd_table(hwmgr->device,	1469	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1432	GetIndexIntoMasterTable(COMMAND, SetVoltage),	1470	GetIndexIntoMasterTable(COMMAND, SetVoltage),
1433	voltage_parameters);	1471	(uint32_t *)voltage_parameters);
1434		1472
1435	*virtual_voltage_id = voltage_parameters->usVoltageLevel;	1473	*virtual_voltage_id = voltage_parameters->usVoltageLevel;
1436		1474
@@ -1453,7 +1491,7 @@ int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, · 16 unmodified lines
1453	ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);	1491	ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1454		1492
1455	profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)	1493	profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1456	cgs_atom_get_data_table(hwmgr->device,	1494	smu_atom_get_data_table(hwmgr->adev,
1457	ix,	1495	ix,
1458	NULL, NULL, NULL);	1496	NULL, NULL, NULL);
1459	if (!profile)	1497	if (!profile)
@@ -1498,3 +1536,31 @@ int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, · 38 unmodified lines
1498		1536
1499	return 0;	1537	return 0;
1500	}	1538	}
		1539
		1540	void atomctrl_get_voltage_range(struct pp_hwmgr hwmgr, uint32_t max_vddc,
		1541	uint32_t *min_vddc)
		1542	{
		1543	void *profile;
		1544
		1545	profile = smu_atom_get_data_table(hwmgr->adev,
		1546	GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
		1547	NULL, NULL, NULL);
		1548
		1549	if (profile) {
		1550	switch (hwmgr->chip_id) {
		1551	case CHIP_TONGA:
		1552	case CHIP_FIJI:
		1553	max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 )profile)->ulMaxVddc/4);
		1554	min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 )profile)->ulMinVddc/4);
		1555	break;
		1556	case CHIP_POLARIS11:
		1557	case CHIP_POLARIS10:
		1558	case CHIP_POLARIS12:
		1559	max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 )profile)->ulMaxVddc/100);
		1560	min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 )profile)->ulMinVddc/100);
		1561	break;
		1562	default:
		1563	return;
		1564	}
		1565	}
		1566	}

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h+14−1

 };
 typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;
+struct pp_atomctrl_memory_clock_param_ai {
+	uint32_t ulClock;
+	uint32_t ulPostDiv;
+	uint16_t ulMclk_fcw_frac;
+	uint16_t ulMclk_fcw_int;
+};
+typedef struct pp_atomctrl_memory_clock_param_ai pp_atomctrl_memory_clock_param_ai;
 struct pp_atomctrl_internal_ss_info {
 	uint32_t speed_spectrum_percentage;                      /* in 1/100 percentage */
 	uint32_t speed_spectrum_rate;                            /* in KHz */
 extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
 extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
 		uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
+extern int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
+		uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param);
 extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
 						 uint32_t clock_value,
 						 pp_atomctrl_clock_dividers_kong *dividers);
-extern int atomctrl_read_efuse(void *device, uint16_t start_index,
+extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
 		uint16_t end_index, uint32_t mask, uint32_t *efuse);
 extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
 		uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
 					uint16_t virtual_voltage_id,
 					uint16_t efuse_voltage_id);
 extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id);
+extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
+							uint32_t *min_vddc);
 #endif

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c+47−52

@@ -23,9 +23,9 @@ · 22 unmodified lines
23		23
24	#include "ppatomfwctrl.h"	24	#include "ppatomfwctrl.h"
25	#include "atomfirmware.h"	25	#include "atomfirmware.h"
		26	#include "atom.h"
26	#include "pp_debug.h"	27	#include "pp_debug.h"
27		28
28
29	static const union atom_voltage_object_v4 *pp_atomfwctrl_lookup_voltage_type_v4(	29	static const union atom_voltage_object_v4 *pp_atomfwctrl_lookup_voltage_type_v4(
30	const struct atom_voltage_objects_info_v4_1 *voltage_object_info_table,	30	const struct atom_voltage_objects_info_v4_1 *voltage_object_info_table,
31	uint8_t voltage_type, uint8_t voltage_mode)	31	uint8_t voltage_type, uint8_t voltage_mode)
@@ -38,35 +38,34 @@ static const union atom_voltage_object_v4 *pp_atomfwctrl_lookup_voltage_type_v4( · 6 unmodified lines
38		38
39	while (offset < size) {	39	while (offset < size) {
40	const union atom_voltage_object_v4 *voltage_object =	40	const union atom_voltage_object_v4 *voltage_object =
41	(const union atom_voltage_object_v4 *)(start + offset);	41	(const union atom_voltage_object_v4 *)(start + offset);
42		42
43	if (voltage_type == voltage_object->gpio_voltage_obj.header.voltage_type &&	43	if (voltage_type == voltage_object->gpio_voltage_obj.header.voltage_type &&
44	voltage_mode == voltage_object->gpio_voltage_obj.header.voltage_mode)	44	voltage_mode == voltage_object->gpio_voltage_obj.header.voltage_mode)
45	return voltage_object;	45	return voltage_object;
46		46
47	offset += le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size);	47	offset += le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size);
48		48
49	}	49	}
50		50
51	return NULL;	51	return NULL;
52	}	52	}
53		53
54	static struct atom_voltage_objects_info_v4_1 *pp_atomfwctrl_get_voltage_info_table(	54	static struct atom_voltage_objects_info_v4_1 *pp_atomfwctrl_get_voltage_info_table(
55	struct pp_hwmgr *hwmgr)	55	struct pp_hwmgr *hwmgr)
56	{	56	{
57	const void *table_address;	57	const void *table_address;
58	uint16_t idx;	58	uint16_t idx;
59		59
60	idx = GetIndexIntoMasterDataTable(voltageobject_info);	60	idx = GetIndexIntoMasterDataTable(voltageobject_info);
61	table_address = cgs_atom_get_data_table(hwmgr->device,	61	table_address = smu_atom_get_data_table(hwmgr->adev,
62	idx, NULL, NULL, NULL);	62	idx, NULL, NULL, NULL);
63		63
64	PP_ASSERT_WITH_CODE(	64	PP_ASSERT_WITH_CODE(table_address,
65	table_address,	65	"Error retrieving BIOS Table Address!",
66	"Error retrieving BIOS Table Address!",	66	return NULL);
67	return NULL);
68		67
69	return (struct atom_voltage_objects_info_v4_1 *)table_address;	68	return (struct atom_voltage_objects_info_v4_1 *)table_address;
70	}	69	}
71		70
72	/**	71	/**
@@ -167,7 +166,7 @@ static struct atom_gpio_pin_lut_v2_1 *pp_atomfwctrl_get_gpio_lookup_table( · 94 unmodified lines
167	uint16_t idx;	166	uint16_t idx;
168		167
169	idx = GetIndexIntoMasterDataTable(gpio_pin_lut);	168	idx = GetIndexIntoMasterDataTable(gpio_pin_lut);
170	table_address = cgs_atom_get_data_table(hwmgr->device,	169	table_address = smu_atom_get_data_table(hwmgr->adev,
171	idx, NULL, NULL, NULL);	170	idx, NULL, NULL, NULL);
172	PP_ASSERT_WITH_CODE(table_address,	171	PP_ASSERT_WITH_CODE(table_address,
173	"Error retrieving BIOS Table Address!",	172	"Error retrieving BIOS Table Address!",
@@ -248,28 +247,30 @@ int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr, · 74 unmodified lines
248	uint32_t clock_type, uint32_t clock_value,	247	uint32_t clock_type, uint32_t clock_value,
249	struct pp_atomfwctrl_clock_dividers_soc15 *dividers)	248	struct pp_atomfwctrl_clock_dividers_soc15 *dividers)
250	{	249	{
		250	struct amdgpu_device *adev = hwmgr->adev;
251	struct compute_gpu_clock_input_parameter_v1_8 pll_parameters;	251	struct compute_gpu_clock_input_parameter_v1_8 pll_parameters;
252	struct compute_gpu_clock_output_parameter_v1_8 *pll_output;	252	struct compute_gpu_clock_output_parameter_v1_8 *pll_output;
253	int result;
254	uint32_t idx;	253	uint32_t idx;
255		254
256	pll_parameters.gpuclock_10khz = (uint32_t)clock_value;	255	pll_parameters.gpuclock_10khz = (uint32_t)clock_value;
257	pll_parameters.gpu_clock_type = clock_type;	256	pll_parameters.gpu_clock_type = clock_type;
258		257
259	idx = GetIndexIntoMasterCmdTable(computegpuclockparam);	258	idx = GetIndexIntoMasterCmdTable(computegpuclockparam);
260	result = cgs_atom_exec_cmd_table(hwmgr->device, idx, &pll_parameters);	259
261		260	if (amdgpu_atom_execute_table(
262	if (!result) {	261	adev->mode_info.atom_context, idx, (uint32_t *)&pll_parameters))
263	pll_output = (struct compute_gpu_clock_output_parameter_v1_8 *)	262	return -EINVAL;
264	&pll_parameters;	263
265	dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);	264	pll_output = (struct compute_gpu_clock_output_parameter_v1_8 *)
266	dividers->ulDid = le32_to_cpu(pll_output->dfs_did);	265	&pll_parameters;
267	dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);	266	dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);
268	dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);	267	dividers->ulDid = le32_to_cpu(pll_output->dfs_did);
269	dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);	268	dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);
270	dividers->ucPll_ss_enable = pll_output->pll_ss_enable;	269	dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);
271	}	270	dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);
272	return result;	271	dividers->ucPll_ss_enable = pll_output->pll_ss_enable;
		272
		273	return 0;
273	}	274	}
274		275
275	int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,	276	int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
@@ -283,7 +284,7 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, · 7 unmodified lines
283		284
284	idx = GetIndexIntoMasterDataTable(asic_profiling_info);	285	idx = GetIndexIntoMasterDataTable(asic_profiling_info);
285	profile = (struct atom_asic_profiling_info_v4_1 *)	286	profile = (struct atom_asic_profiling_info_v4_1 *)
286	cgs_atom_get_data_table(hwmgr->device,	287	smu_atom_get_data_table(hwmgr->adev,
287	idx, NULL, NULL, NULL);	288	idx, NULL, NULL, NULL);
288		289
289	if (!profile)	290	if (!profile)
@@ -467,7 +468,7 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr, · 177 unmodified lines
467		468
468	idx = GetIndexIntoMasterDataTable(smu_info);	469	idx = GetIndexIntoMasterDataTable(smu_info);
469	info = (struct atom_smu_info_v3_1 *)	470	info = (struct atom_smu_info_v3_1 *)
470	cgs_atom_get_data_table(hwmgr->device,	471	smu_atom_get_data_table(hwmgr->adev,
471	idx, NULL, NULL, NULL);	472	idx, NULL, NULL, NULL);
472		473
473	if (!info) {	474	if (!info) {
@@ -487,8 +488,9 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr, · 13 unmodified lines
487	return 0;	488	return 0;
488	}	489	}
489		490
490	int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr hwmgr, BIOS_CLKID id, uint32_t frequency)	491	int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr hwmgr, BIOS_CLKID id, uint32_t frequency)
491	{	492	{
		493	struct amdgpu_device *adev = hwmgr->adev;
492	struct atom_get_smu_clock_info_parameters_v3_1 parameters;	494	struct atom_get_smu_clock_info_parameters_v3_1 parameters;
493	struct atom_get_smu_clock_info_output_parameters_v3_1 *output;	495	struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
494	uint32_t ix;	496	uint32_t ix;
@@ -497,13 +499,13 @@ int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLK · 2 unmodified lines
497	parameters.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;	499	parameters.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
498		500
499	ix = GetIndexIntoMasterCmdTable(getsmuclockinfo);	501	ix = GetIndexIntoMasterCmdTable(getsmuclockinfo);
500	if (!cgs_atom_exec_cmd_table(hwmgr->device, ix, &parameters)) {	502
501	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&parameters;	503	if (amdgpu_atom_execute_table(
502	*frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000;	504	adev->mode_info.atom_context, ix, (uint32_t *)&parameters))
503	} else {	505	return -EINVAL;
504	pr_info("Error execute_table getsmuclockinfo!");	506
505	return -1;	507	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&parameters;
506	}	508	*frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000;
507		509
508	return 0;	510	return 0;
509	}	511	}
@@ -513,11 +515,10 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, · 3 unmodified lines
513	{	515	{
514	struct atom_firmware_info_v3_1 *info = NULL;	516	struct atom_firmware_info_v3_1 *info = NULL;
515	uint16_t ix;	517	uint16_t ix;
516	uint32_t frequency = 0;
517		518
518	ix = GetIndexIntoMasterDataTable(firmwareinfo);	519	ix = GetIndexIntoMasterDataTable(firmwareinfo);
519	info = (struct atom_firmware_info_v3_1 *)	520	info = (struct atom_firmware_info_v3_1 *)
520	cgs_atom_get_data_table(hwmgr->device,	521	smu_atom_get_data_table(hwmgr->adev,
521	ix, NULL, NULL, NULL);	522	ix, NULL, NULL, NULL);
522		523
523	if (!info) {	524	if (!info) {
@@ -536,12 +537,6 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, · 12 unmodified lines
536	boot_values->ulSocClk = 0;	537	boot_values->ulSocClk = 0;
537	boot_values->ulDCEFClk = 0;	538	boot_values->ulDCEFClk = 0;
538		539
539	if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, &frequency))
540	boot_values->ulSocClk = frequency;
541
542	if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, &frequency))
543	boot_values->ulDCEFClk = frequency;
544
545	return 0;	540	return 0;
546	}	541	}
547		542
@@ -553,7 +548,7 @@ int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr, · 5 unmodified lines
553		548
554	ix = GetIndexIntoMasterDataTable(smc_dpm_info);	549	ix = GetIndexIntoMasterDataTable(smc_dpm_info);
555	info = (struct atom_smc_dpm_info_v4_1 *)	550	info = (struct atom_smc_dpm_info_v4_1 *)
556	cgs_atom_get_data_table(hwmgr->device,	551	smu_atom_get_data_table(hwmgr->adev,
557	ix, NULL, NULL, NULL);	552	ix, NULL, NULL, NULL);
558	if (!info) {	553	if (!info) {
559	pr_info("Error retrieving BIOS Table Address!");	554	pr_info("Error retrieving BIOS Table Address!");

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h+2−0

@@ -230,6 +230,8 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, · 229 unmodified lines
230	struct pp_atomfwctrl_bios_boot_up_values *boot_values);	230	struct pp_atomfwctrl_bios_boot_up_values *boot_values);
231	int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,	231	int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
232	struct pp_atomfwctrl_smc_dpm_parameters *param);	232	struct pp_atomfwctrl_smc_dpm_parameters *param);
		233	int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr,
		234	BIOS_CLKID id, uint32_t *frequency);
233		235
234	#endif	236	#endif
235		237

drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c+38−1

@@ -141,7 +141,7 @@ static const void get_powerplay_table(struct pp_hwmgr hwmgr) · 140 unmodified lines
141		141
142	if (!table_address) {	142	if (!table_address) {
143	table_address = (ATOM_Tonga_POWERPLAYTABLE *)	143	table_address = (ATOM_Tonga_POWERPLAYTABLE *)
144	cgs_atom_get_data_table(hwmgr->device,	144	smu_atom_get_data_table(hwmgr->adev,
145	index, &size, &frev, &crev);	145	index, &size, &frev, &crev);
146	hwmgr->soft_pp_table = table_address; /Cache the result in RAM./	146	hwmgr->soft_pp_table = table_address; /Cache the result in RAM./
147	hwmgr->soft_pp_table_size = size;	147	hwmgr->soft_pp_table_size = size;
@@ -728,6 +728,32 @@ static int get_mm_clock_voltage_table( · 580 unmodified lines
728	return 0;	728	return 0;
729	}	729	}
730		730
		731	static int get_gpio_table(struct pp_hwmgr *hwmgr,
		732	struct phm_ppt_v1_gpio_table **pp_tonga_gpio_table,
		733	const ATOM_Tonga_GPIO_Table *atom_gpio_table)
		734	{
		735	uint32_t table_size;
		736	struct phm_ppt_v1_gpio_table *pp_gpio_table;
		737	struct phm_ppt_v1_information *pp_table_information =
		738	(struct phm_ppt_v1_information *)(hwmgr->pptable);
		739
		740	table_size = sizeof(struct phm_ppt_v1_gpio_table);
		741	pp_gpio_table = kzalloc(table_size, GFP_KERNEL);
		742	if (!pp_gpio_table)
		743	return -ENOMEM;
		744
		745	if (pp_table_information->vdd_dep_on_sclk->count <
		746	atom_gpio_table->ucVRHotTriggeredSclkDpmIndex)
		747	PP_ASSERT_WITH_CODE(false,
		748	"SCLK DPM index for VRHot cannot exceed the total sclk level count!",);
		749	else
		750	pp_gpio_table->vrhot_triggered_sclk_dpm_index =
		751	atom_gpio_table->ucVRHotTriggeredSclkDpmIndex;
		752
		753	*pp_tonga_gpio_table = pp_gpio_table;
		754
		755	return 0;
		756	}
731	/**	757	/**
732	* Private Function used during initialization.	758	* Private Function used during initialization.
733	* Initialize clock voltage dependency	759	* Initialize clock voltage dependency
@@ -761,11 +787,15 @@ static int init_clock_voltage_dependency( · 27 unmodified lines
761	const PPTable_Generic_SubTable_Header *pcie_table =	787	const PPTable_Generic_SubTable_Header *pcie_table =
762	(const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +	788	(const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
763	le16_to_cpu(powerplay_table->usPCIETableOffset));	789	le16_to_cpu(powerplay_table->usPCIETableOffset));
		790	const ATOM_Tonga_GPIO_Table *gpio_table =
		791	(const ATOM_Tonga_GPIO_Table *)(((unsigned long) powerplay_table) +
		792	le16_to_cpu(powerplay_table->usGPIOTableOffset));
764		793
765	pp_table_information->vdd_dep_on_sclk = NULL;	794	pp_table_information->vdd_dep_on_sclk = NULL;
766	pp_table_information->vdd_dep_on_mclk = NULL;	795	pp_table_information->vdd_dep_on_mclk = NULL;
767	pp_table_information->mm_dep_table = NULL;	796	pp_table_information->mm_dep_table = NULL;
768	pp_table_information->pcie_table = NULL;	797	pp_table_information->pcie_table = NULL;
		798	pp_table_information->gpio_table = NULL;
769		799
770	if (powerplay_table->usMMDependencyTableOffset != 0)	800	if (powerplay_table->usMMDependencyTableOffset != 0)
771	result = get_mm_clock_voltage_table(hwmgr,	801	result = get_mm_clock_voltage_table(hwmgr,
@@ -810,6 +840,10 @@ static int init_clock_voltage_dependency( · 38 unmodified lines
810	result = get_valid_clk(hwmgr, &pp_table_information->valid_sclk_values,	840	result = get_valid_clk(hwmgr, &pp_table_information->valid_sclk_values,
811	pp_table_information->vdd_dep_on_sclk);	841	pp_table_information->vdd_dep_on_sclk);
812		842
		843	if (!result && gpio_table)
		844	result = get_gpio_table(hwmgr, &pp_table_information->gpio_table,
		845	gpio_table);
		846
813	return result;	847	return result;
814	}	848	}
815		849
@@ -1116,6 +1150,9 @@ static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr) · 300 unmodified lines
1116	kfree(pp_table_information->pcie_table);	1150	kfree(pp_table_information->pcie_table);
1117	pp_table_information->pcie_table = NULL;	1151	pp_table_information->pcie_table = NULL;
1118		1152
		1153	kfree(pp_table_information->gpio_table);
		1154	pp_table_information->gpio_table = NULL;
		1155
1119	kfree(hwmgr->pptable);	1156	kfree(hwmgr->pptable);
1120	hwmgr->pptable = NULL;	1157	hwmgr->pptable = NULL;
1121		1158

drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c+2−2

@@ -837,7 +837,7 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table( · 836 unmodified lines
837	hwmgr->soft_pp_table = &soft_dummy_pp_table[0];	837	hwmgr->soft_pp_table = &soft_dummy_pp_table[0];
838	hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);	838	hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);
839	} else {	839	} else {
840	table_addr = cgs_atom_get_data_table(hwmgr->device,	840	table_addr = smu_atom_get_data_table(hwmgr->adev,
841	GetIndexIntoMasterTable(DATA, PowerPlayInfo),	841	GetIndexIntoMasterTable(DATA, PowerPlayInfo),
842	&size, &frev, &crev);	842	&size, &frev, &crev);
843	hwmgr->soft_pp_table = table_addr;	843	hwmgr->soft_pp_table = table_addr;
@@ -1058,7 +1058,7 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr, · 214 unmodified lines
1058	return 0;	1058	return 0;
1059		1059
1060	/* We assume here that fw_info is unchanged if this call fails.*/	1060	/* We assume here that fw_info is unchanged if this call fails.*/
1061	fw_info = cgs_atom_get_data_table(hwmgr->device,	1061	fw_info = smu_atom_get_data_table(hwmgr->adev,
1062	GetIndexIntoMasterTable(DATA, FirmwareInfo),	1062	GetIndexIntoMasterTable(DATA, FirmwareInfo),
1063	&size, &frev, &crev);	1063	&size, &frev, &crev);
1064		1064

drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c+158−28

 #include "rv_ppsmc.h"
 #include "smu10_hwmgr.h"
 #include "power_state.h"
-#include "pp_soc15.h"
+#include "soc15_common.h"
 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID     5
 #define SMU10_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed on this chip */
 #define SMU10_DISPCLK_BYPASS_THRESHOLD     10000 /* 100Mhz */
 #define SMC_RAM_END                     0x40000
+#define mmPWR_MISC_CNTL_STATUS					0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX				0
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT	0x0
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT		0x1
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK		0x00000001L
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK		0x00000006L
 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
 	smu10_data->thermal_auto_throttling_treshold = 0;
 	smu10_data->is_nb_dpm_enabled = 1;
 	smu10_data->dpm_flags = 1;
-	smu10_data->gfx_off_controled_by_driver = false;
 	smu10_data->need_min_deep_sleep_dcefclk = true;
 	smu10_data->num_active_display = 0;
 	smu10_data->deep_sleep_dcefclk = 0;
+	if (hwmgr->feature_mask & PP_GFXOFF_MASK)
+		smu10_data->gfx_off_controled_by_driver = true;
+	else
+		smu10_data->gfx_off_controled_by_driver = false;
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 					PHM_PlatformCaps_SclkDeepSleep);
 	struct PP_Clocks clocks = {0};
 	struct pp_display_clock_request clock_req;
-	clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
+	clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
 	clock_req.clock_type = amd_pp_dcf_clock;
 	clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
 {
 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+	struct amdgpu_device *adev = hwmgr->adev;
 	smu10_data->vcn_power_gated = true;
 	smu10_data->isp_tileA_power_gated = true;
 	smu10_data->isp_tileB_power_gated = true;
-	return 0;
+	if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
+		return smum_send_msg_to_smc_with_parameter(hwmgr,
+							   PPSMC_MSG_SetGfxCGPG,
+							   true);
+	else
+		return 0;
 }
 	return smu10_reset_cc6_data(hwmgr);
 }
+static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
+{
+	uint32_t reg;
+	struct amdgpu_device *adev = hwmgr->adev;
+	reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
+	if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
+	    (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
+		return true;
+	return false;
+}
 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 {
 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
-	if (smu10_data->gfx_off_controled_by_driver)
+	if (smu10_data->gfx_off_controled_by_driver) {
 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff);
+		/* confirm gfx is back to "on" state */
+		while (!smu10_is_gfx_on(hwmgr))
+			msleep(1);

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