History

tools headers UAPI: Update tools's copy of drm.h headers

Picking the changes from: c5d3e39caa45 ("drm/i915: Engine discovery query") a88b6e4cbafd ("drm/i915: Allow specification of parallel execbuf") ee1136908e9b ("drm/i915/execlists: Virtual engine bonding") 6d06779e8672 ("drm/i915: Load balancing across a virtual engine") b81dde719439 ("drm/i915: Allow userspace to clone contexts on creation") 8319f44c0525 ("drm/i915: Re-expose SINGLE_TIMELINE flags for context creation") e620f7b3a263 ("drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[]") 976b55f0e1db ("drm/i915: Allow a context to define its set of engines") 7f3f317a66ca ("drm/i915: Restore control over ppgtt for context creation ABI") 75b3f1cb50bd ("drm: Fix drm.h uapi header for GNU/kFreeBSD") Silencing these perf build warnings: Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h' diff -u tools/include/uapi/drm/drm.h include/uapi/drm/drm.h Warning: Kernel ABI header at 'tools/include/uapi/drm/i915_drm.h' differs from latest version at 'include/uapi/drm/i915_drm.h' diff -u tools/include/uapi/drm/i915_drm.h include/uapi/drm/i915_drm.h Now 'perf trace' and other code that might use the tools/perf/trace/beauty autogenerated tables will be able to translate this new ioctl code into a string: $ tools/perf/trace/beauty/drm_ioctl.sh > before $ cp include/uapi/drm/i915_drm.h tools/include/uapi/drm/i915_drm.h $ tools/perf/trace/beauty/drm_ioctl.sh > after $ diff -u before after --- before 2019-07-26 13:02:22.052723640 -0300 +++ after 2019-07-26 13:02:35.354906036 -0300 @@ -163,4 +163,6 @@ [DRM_COMMAND_BASE + 0x37] = "I915_PERF_ADD_CONFIG", [DRM_COMMAND_BASE + 0x38] = "I915_PERF_REMOVE_CONFIG", [DRM_COMMAND_BASE + 0x39] = "I915_QUERY", + [DRM_COMMAND_BASE + 0x3a] = "I915_GEM_VM_CREATE", + [DRM_COMMAND_BASE + 0x3b] = "I915_GEM_VM_DESTROY", }; $

Arnaldo Carvalho de Melo committed 7 years ago

Commit 95dc6631 parent b830f942 files · +207 −3Browse files

Unified · Split

2 files
  1. tools/include/uapi/drm/drm.h +1 −0
  2. tools/include/uapi/drm/i915_drm.h +206 −3
tools/include/uapi/drm/drm.h+1−0
@@ -50,6 +50,7 @@ typedef unsigned int drm_handle_t; · 49 unmodified lines
5050
5151 #else /* One of the BSDs */
5252
53+#include <stdint.h>
5354 #include <sys/ioccom.h>
5455 #include <sys/types.h>
5556 typedef int8_t __s8;
tools/include/uapi/drm/i915_drm.h+206−3
@@ -136,6 +136,8 @@ enum drm_i915_gem_engine_class { · 135 unmodified lines
136136 struct i915_engine_class_instance {
137137 __u16 engine_class; /* see enum drm_i915_gem_engine_class */
138138 __u16 engine_instance;
139+#define I915_ENGINE_CLASS_INVALID_NONE -1
140+#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
139141 };
140142
141143 /**
@@ -355,6 +357,8 @@ typedef struct _drm_i915_sarea { · 213 unmodified lines
355357 #define DRM_I915_PERF_ADD_CONFIG 0x37
356358 #define DRM_I915_PERF_REMOVE_CONFIG 0x38
357359 #define DRM_I915_QUERY 0x39
360+#define DRM_I915_GEM_VM_CREATE 0x3a
361+#define DRM_I915_GEM_VM_DESTROY 0x3b
358362 /* Must be kept compact -- no holes */
359363
360364 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
@@ -415,6 +419,8 @@ typedef struct _drm_i915_sarea { · 54 unmodified lines
415419 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
416420 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
417421 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
422+#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
423+#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
418424
419425 /* Allow drivers to submit batchbuffers directly to hardware, relying
420426 * on the security mechanisms provided by hardware.
@@ -598,6 +604,12 @@ typedef struct drm_i915_irq_wait { · 177 unmodified lines
598604 */
599605 #define I915_PARAM_MMAP_GTT_COHERENT 52
600606
607+/*
608+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
609+ * execution through use of explicit fence support.
610+ * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
611+ */
612+#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
601613 /* Must be kept compact -- no holes and well documented */
602614
603615 typedef struct drm_i915_getparam {
@@ -1120,7 +1132,16 @@ struct drm_i915_gem_execbuffer2 { · 516 unmodified lines
11201132 */
11211133 #define I915_EXEC_FENCE_ARRAY (1<<19)
11221134
1123−#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
1135+/*
1136+ * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
1137+ * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1138+ * the batch.
1139+ *
1140+ * Returns -EINVAL if the sync_file fd cannot be found.
1141+ */
1142+#define I915_EXEC_FENCE_SUBMIT (1 << 20)
1143+
1144+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
11241145
11251146 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
11261147 #define i915_execbuffer2_set_context_id(eb2, context) \
@@ -1464,8 +1485,9 @@ struct drm_i915_gem_context_create_ext { · 337 unmodified lines
14641485 __u32 ctx_id; /* output: id of new context*/
14651486 __u32 flags;
14661487 #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
1488+#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
14671489 #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
1468− (-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))
1490+ (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
14691491 __u64 extensions;
14701492 };
14711493
@@ -1507,6 +1529,41 @@ struct drm_i915_gem_context_param { · 35 unmodified lines
15071529 * On creation, all new contexts are marked as recoverable.
15081530 */
15091531 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1532+
1533+ /*
1534+ * The id of the associated virtual memory address space (ppGTT) of
1535+ * this context. Can be retrieved and passed to another context
1536+ * (on the same fd) for both to use the same ppGTT and so share
1537+ * address layouts, and avoid reloading the page tables on context
1538+ * switches between themselves.
1539+ *
1540+ * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
1541+ */
1542+#define I915_CONTEXT_PARAM_VM 0x9
1543+
1544+/*
1545+ * I915_CONTEXT_PARAM_ENGINES:
1546+ *
1547+ * Bind this context to operate on this subset of available engines. Henceforth,
1548+ * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
1549+ * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
1550+ * and upwards. Slots 0...N are filled in using the specified (class, instance).
1551+ * Use
1552+ * engine_class: I915_ENGINE_CLASS_INVALID,
1553+ * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
1554+ * to specify a gap in the array that can be filled in later, e.g. by a
1555+ * virtual engine used for load balancing.
1556+ *
1557+ * Setting the number of engines bound to the context to 0, by passing a zero
1558+ * sized argument, will revert back to default settings.
1559+ *
1560+ * See struct i915_context_param_engines.
1561+ *
1562+ * Extensions:
1563+ * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
1564+ * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
1565+ */
1566+#define I915_CONTEXT_PARAM_ENGINES 0xa
15101567 /* Must be kept compact -- no holes and well documented */
15111568
15121569 __u64 value;
@@ -1540,9 +1597,10 @@ struct drm_i915_gem_context_param_sseu { · 27 unmodified lines
15401597 struct i915_engine_class_instance engine;
15411598
15421599 /*
1543− * Unused for now. Must be cleared to zero.
1600+ * Unknown flags must be cleared to zero.
15441601 */
15451602 __u32 flags;
1603+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
15461604
15471605 /*
15481606 * Mask of slices to enable for the context. Valid values are a subset
@@ -1570,12 +1628,115 @@ struct drm_i915_gem_context_param_sseu { · 21 unmodified lines
15701628 __u32 rsvd;
15711629 };
15721630
1631+/*
1632+ * i915_context_engines_load_balance:
1633+ *
1634+ * Enable load balancing across this set of engines.
1635+ *
1636+ * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
1637+ * used will proxy the execbuffer request onto one of the set of engines
1638+ * in such a way as to distribute the load evenly across the set.
1639+ *
1640+ * The set of engines must be compatible (e.g. the same HW class) as they
1641+ * will share the same logical GPU context and ring.
1642+ *
1643+ * To intermix rendering with the virtual engine and direct rendering onto
1644+ * the backing engines (bypassing the load balancing proxy), the context must
1645+ * be defined to use a single timeline for all engines.
1646+ */
1647+struct i915_context_engines_load_balance {
1648+ struct i915_user_extension base;
1649+
1650+ __u16 engine_index;
1651+ __u16 num_siblings;
1652+ __u32 flags; /* all undefined flags must be zero */
1653+
1654+ __u64 mbz64; /* reserved for future use; must be zero */
1655+
1656+ struct i915_engine_class_instance engines[0];
1657+} __attribute__((packed));
1658+
1659+#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
1660+ struct i915_user_extension base; \
1661+ __u16 engine_index; \
1662+ __u16 num_siblings; \
1663+ __u32 flags; \
1664+ __u64 mbz64; \
1665+ struct i915_engine_class_instance engines[N__]; \
1666+} __attribute__((packed)) name__
1667+
1668+/*
1669+ * i915_context_engines_bond:
1670+ *
1671+ * Constructed bonded pairs for execution within a virtual engine.
1672+ *
1673+ * All engines are equal, but some are more equal than others. Given
1674+ * the distribution of resources in the HW, it may be preferable to run
1675+ * a request on a given subset of engines in parallel to a request on a
1676+ * specific engine. We enable this selection of engines within a virtual
1677+ * engine by specifying bonding pairs, for any given master engine we will
1678+ * only execute on one of the corresponding siblings within the virtual engine.
1679+ *
1680+ * To execute a request in parallel on the master engine and a sibling requires
1681+ * coordination with a I915_EXEC_FENCE_SUBMIT.
1682+ */
1683+struct i915_context_engines_bond {
1684+ struct i915_user_extension base;
1685+
1686+ struct i915_engine_class_instance master;
1687+
1688+ __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
1689+ __u16 num_bonds;
1690+
1691+ __u64 flags; /* all undefined flags must be zero */
1692+ __u64 mbz64[4]; /* reserved for future use; must be zero */
1693+
1694+ struct i915_engine_class_instance engines[0];
1695+} __attribute__((packed));
1696+
1697+#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
1698+ struct i915_user_extension base; \
1699+ struct i915_engine_class_instance master; \
1700+ __u16 virtual_index; \
1701+ __u16 num_bonds; \
1702+ __u64 flags; \
1703+ __u64 mbz64[4]; \
1704+ struct i915_engine_class_instance engines[N__]; \
1705+} __attribute__((packed)) name__
1706+
1707+struct i915_context_param_engines {
1708+ __u64 extensions; /* linked chain of extension blocks, 0 terminates */
1709+#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
1710+#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
1711+ struct i915_engine_class_instance engines[0];
1712+} __attribute__((packed));
1713+
1714+#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
1715+ __u64 extensions; \
1716+ struct i915_engine_class_instance engines[N__]; \
1717+} __attribute__((packed)) name__
1718+
15731719 struct drm_i915_gem_context_create_ext_setparam {
15741720 #define I915_CONTEXT_CREATE_EXT_SETPARAM 0
15751721 struct i915_user_extension base;
15761722 struct drm_i915_gem_context_param param;
15771723 };
15781724
1725+struct drm_i915_gem_context_create_ext_clone {
1726+#define I915_CONTEXT_CREATE_EXT_CLONE 1
1727+ struct i915_user_extension base;
1728+ __u32 clone_id;
1729+ __u32 flags;
1730+#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
1731+#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
1732+#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
1733+#define I915_CONTEXT_CLONE_SSEU (1u << 3)
1734+#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
1735+#define I915_CONTEXT_CLONE_VM (1u << 5)
1736+#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
1737+ __u64 rsvd;
1738+};
1739+
15791740 struct drm_i915_gem_context_destroy {
15801741 __u32 ctx_id;
15811742 __u32 pad;
@@ -1821,6 +1982,7 @@ struct drm_i915_perf_oa_config { · 239 unmodified lines
18211982 struct drm_i915_query_item {
18221983 __u64 query_id;
18231984 #define DRM_I915_QUERY_TOPOLOGY_INFO 1
1985+#define DRM_I915_QUERY_ENGINE_INFO 2
18241986 /* Must be kept compact -- no holes and well documented */
18251987
18261988 /*
@@ -1919,6 +2081,47 @@ struct drm_i915_query_topology_info { · 92 unmodified lines
19192081 __u8 data[];
19202082 };
19212083
2084+/**
2085+ * struct drm_i915_engine_info
2086+ *
2087+ * Describes one engine and it's capabilities as known to the driver.
2088+ */
2089+struct drm_i915_engine_info {
2090+ /** Engine class and instance. */
2091+ struct i915_engine_class_instance engine;
2092+
2093+ /** Reserved field. */
2094+ __u32 rsvd0;
2095+
2096+ /** Engine flags. */
2097+ __u64 flags;
2098+
2099+ /** Capabilities of this engine. */
2100+ __u64 capabilities;
2101+#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
2102+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
2103+
2104+ /** Reserved fields. */
2105+ __u64 rsvd1[4];
2106+};
2107+
2108+/**
2109+ * struct drm_i915_query_engine_info
2110+ *
2111+ * Engine info query enumerates all engines known to the driver by filling in
2112+ * an array of struct drm_i915_engine_info structures.
2113+ */
2114+struct drm_i915_query_engine_info {
2115+ /** Number of struct drm_i915_engine_info structs following. */
2116+ __u32 num_engines;
2117+
2118+ /** MBZ */
2119+ __u32 rsvd[3];
2120+
2121+ /** Marker for drm_i915_engine_info structures. */
2122+ struct drm_i915_engine_info engines[];
2123+};
2124+
19222125 #if defined(__cplusplus)
19232126 }
19242127 #endif