From Simon Horman: Renesas ARM based SoC fixes for v3.13 * r8a7790 (R-Car H1) SoC - Correct GPIO resources in DT. This problem has been present since GPIOs were added to the r8a7790 SoC by f98e10c88aa95bf7 ("ARM: shmobile: r8a7790: Add GPIO controller devices to device tree") in v3.12-rc1. * irqchip renesas-intc-irqpin - Correct register bitfield shift calculation This bug has been present since the renesas-intc-irqpin driver was introduced by 443580486e3b9657 ("irqchip: Renesas INTC External IRQ pin driver") in v3.10-rc1 * Lager board - Do not build the phy fixup unless CONFIG_PHYLIB is enabled This problem was introduced by 48c8b96f21817aad * tag 'renesas-fixes-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7790: Fix GPIO resources in DTS irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB
Unified · Split
| @@ -87,9 +87,9 @@ · 86 unmodified lines | ||
| 87 | 87 | interrupts = <1 9 0xf04>; |
| 88 | 88 | }; |
| 89 | 89 | |
| 90 | − gpio0: gpio@ffc40000 { | |
| 90 | + gpio0: gpio@e6050000 { | |
| 91 | 91 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 92 | − reg = <0 0xffc40000 0 0x2c>; | |
| 92 | + reg = <0 0xe6050000 0 0x50>; | |
| 93 | 93 | interrupt-parent = <&gic>; |
| 94 | 94 | interrupts = <0 4 0x4>; |
| 95 | 95 | #gpio-cells = <2>; |
| @@ -99,9 +99,9 @@ · 3 unmodified lines | ||
| 99 | 99 | interrupt-controller; |
| 100 | 100 | }; |
| 101 | 101 | |
| 102 | − gpio1: gpio@ffc41000 { | |
| 102 | + gpio1: gpio@e6051000 { | |
| 103 | 103 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 104 | − reg = <0 0xffc41000 0 0x2c>; | |
| 104 | + reg = <0 0xe6051000 0 0x50>; | |
| 105 | 105 | interrupt-parent = <&gic>; |
| 106 | 106 | interrupts = <0 5 0x4>; |
| 107 | 107 | #gpio-cells = <2>; |
| @@ -111,9 +111,9 @@ · 3 unmodified lines | ||
| 111 | 111 | interrupt-controller; |
| 112 | 112 | }; |
| 113 | 113 | |
| 114 | − gpio2: gpio@ffc42000 { | |
| 114 | + gpio2: gpio@e6052000 { | |
| 115 | 115 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 116 | − reg = <0 0xffc42000 0 0x2c>; | |
| 116 | + reg = <0 0xe6052000 0 0x50>; | |
| 117 | 117 | interrupt-parent = <&gic>; |
| 118 | 118 | interrupts = <0 6 0x4>; |
| 119 | 119 | #gpio-cells = <2>; |
| @@ -123,9 +123,9 @@ · 3 unmodified lines | ||
| 123 | 123 | interrupt-controller; |
| 124 | 124 | }; |
| 125 | 125 | |
| 126 | − gpio3: gpio@ffc43000 { | |
| 126 | + gpio3: gpio@e6053000 { | |
| 127 | 127 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 128 | − reg = <0 0xffc43000 0 0x2c>; | |
| 128 | + reg = <0 0xe6053000 0 0x50>; | |
| 129 | 129 | interrupt-parent = <&gic>; |
| 130 | 130 | interrupts = <0 7 0x4>; |
| 131 | 131 | #gpio-cells = <2>; |
| @@ -135,9 +135,9 @@ · 3 unmodified lines | ||
| 135 | 135 | interrupt-controller; |
| 136 | 136 | }; |
| 137 | 137 | |
| 138 | − gpio4: gpio@ffc44000 { | |
| 138 | + gpio4: gpio@e6054000 { | |
| 139 | 139 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 140 | − reg = <0 0xffc44000 0 0x2c>; | |
| 140 | + reg = <0 0xe6054000 0 0x50>; | |
| 141 | 141 | interrupt-parent = <&gic>; |
| 142 | 142 | interrupts = <0 8 0x4>; |
| 143 | 143 | #gpio-cells = <2>; |
| @@ -147,9 +147,9 @@ · 3 unmodified lines | ||
| 147 | 147 | interrupt-controller; |
| 148 | 148 | }; |
| 149 | 149 | |
| 150 | − gpio5: gpio@ffc45000 { | |
| 150 | + gpio5: gpio@e6055000 { | |
| 151 | 151 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 152 | − reg = <0 0xffc45000 0 0x2c>; | |
| 152 | + reg = <0 0xe6055000 0 0x50>; | |
| 153 | 153 | interrupt-parent = <&gic>; |
| 154 | 154 | interrupts = <0 9 0x4>; |
| 155 | 155 | #gpio-cells = <2>; |
| @@ -245,7 +245,9 @@ static void __init lager_init(void) · 244 unmodified lines | ||
| 245 | 245 | { |
| 246 | 246 | lager_add_standard_devices(); |
| 247 | 247 | |
| 248 | − phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup); | |
| 248 | + if (IS_ENABLED(CONFIG_PHYLIB)) | |
| 249 | + phy_register_fixup_for_id("r8a7790-ether-ff:01", | |
| 250 | + lager_ksz8041_fixup); | |
| 249 | 251 | } |
| 250 | 252 | |
| 251 | 253 | static const char * const lager_boards_compat_dt[] __initconst = { |
| @@ -149,8 +149,9 @@ static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, · 148 unmodified lines | ||
| 149 | 149 | static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, |
| 150 | 150 | int irq, int do_mask) |
| 151 | 151 | { |
| 152 | − int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */ | |
| 153 | − int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */ | |
| 152 | + /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */ | |
| 153 | + int bitfield_width = 4; | |
| 154 | + int shift = 32 - (irq + 1) * bitfield_width; | |
| 154 | 155 | |
| 155 | 156 | intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, |
| 156 | 157 | shift, bitfield_width, |
| @@ -159,8 +160,9 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, · 2 unmodified lines | ||
| 159 | 160 | |
| 160 | 161 | static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) |
| 161 | 162 | { |
| 163 | + /* The SENSE register is assumed to be 32-bit. */ | |
| 162 | 164 | int bitfield_width = p->config.sense_bitfield_width; |
| 163 | − int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */ | |
| 165 | + int shift = 32 - (irq + 1) * bitfield_width; | |
| 164 | 166 | |
| 165 | 167 | dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); |
| 166 | 168 | |