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irqchip/gic-v4.1: Add support for VPENDBASER's Dirty+Valid signaling

When a vPE is made resident, the GIC starts parsing the virtual pending table to deliver pending interrupts. This takes place asynchronously, and can at times take a long while. Long enough that the vcpu enters the guest and hits WFI before any interrupt has been signaled yet. The vcpu then exits, blocks, and now gets a doorbell. Rince, repeat. In order to avoid the above, a (optional on GICv4, mandatory on v4.1) feature allows the GIC to feedback to the hypervisor whether it is done parsing the VPT by clearing the GICR_VPENDBASER.Dirty bit. The hypervisor can then wait until the GIC is ready before actually running the vPE. Plug the detection code as well as polling on vPE schedule. While at it, tidy-up the kernel message that displays the GICv4 optional features.

Marc Zyngier committed 6 years ago

Commit 96806221 parent 8f3d9f33 files · +28 −4Browse files

Showing the changes to include/linux (1 of 3 files). Show all

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include/linux/irqchip/arm-gic-v3.h+2−0
@@ -243,6 +243,7 @@ · 242 unmodified lines
243243
244244 #define GICR_TYPER_PLPIS (1U << 0)
245245 #define GICR_TYPER_VLPIS (1U << 1)
246+#define GICR_TYPER_DIRTY (1U << 2)
246247 #define GICR_TYPER_DirectLPIS (1U << 3)
247248 #define GICR_TYPER_LAST (1U << 4)
248249 #define GICR_TYPER_RVPEID (1U << 7)
@@ -686,6 +687,7 @@ struct rdists { · 437 unmodified lines
686687 bool has_vlpis;
687688 bool has_rvpeid;
688689 bool has_direct_lpi;
690+ bool has_vpend_valid_dirty;
689691 };
690692
691693 struct irq_domain;