History

uapi: habanalabs: add gaudi2 defines

Add the new defines for GAUDI2 uapi interface. It includes the following: 1. Enums of engines and PLLs. 2. New information in the info IOCTL that is retrieved by the driver. 3. Update comments regarding the CB/CS/wait for CS ioctls. 4. New fields in the debug IOCTL for configuring the profiler for Gaudi2. There is no new IOCTL. Some of the changes are also relevant for Greco (which will be upstreamed later this year). When ever it says "Greco and onwards", it means it is also for Gaudi2.

Oded Gabbay committed 4 years ago

Commit 97c6d221 parent 01d9ccf1 file · +435 −20Browse files

Unified · Split

include/uapi/misc/habanalabs.h+435−20
@@ -184,6 +184,285 @@ enum gaudi_queue_id { · 183 unmodified lines
184184 GAUDI_QUEUE_ID_SIZE
185185 };
186186
187+/*
188+ * In GAUDI2 we have two modes of operation in regard to queues:
189+ * 1. Legacy mode, where each QMAN exposes 4 streams to the user
190+ * 2. F/W mode, where we use F/W to schedule the JOBS to the different queues.
191+ *
192+ * When in legacy mode, the user sends the queue id per JOB according to
193+ * enum gaudi2_queue_id below.
194+ *
195+ * When in F/W mode, the user sends a stream id per Command Submission. The
196+ * stream id is a running number from 0 up to (N-1), where N is the number
197+ * of streams the F/W exposes and is passed to the user in
198+ * struct hl_info_hw_ip_info
199+ */
200+
201+enum gaudi2_queue_id {
202+ GAUDI2_QUEUE_ID_PDMA_0_0 = 0,
203+ GAUDI2_QUEUE_ID_PDMA_0_1 = 1,
204+ GAUDI2_QUEUE_ID_PDMA_0_2 = 2,
205+ GAUDI2_QUEUE_ID_PDMA_0_3 = 3,
206+ GAUDI2_QUEUE_ID_PDMA_1_0 = 4,
207+ GAUDI2_QUEUE_ID_PDMA_1_1 = 5,
208+ GAUDI2_QUEUE_ID_PDMA_1_2 = 6,
209+ GAUDI2_QUEUE_ID_PDMA_1_3 = 7,
210+ GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0 = 8,
211+ GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1 = 9,
212+ GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2 = 10,
213+ GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3 = 11,
214+ GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0 = 12,
215+ GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1 = 13,
216+ GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2 = 14,
217+ GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3 = 15,
218+ GAUDI2_QUEUE_ID_DCORE0_MME_0_0 = 16,
219+ GAUDI2_QUEUE_ID_DCORE0_MME_0_1 = 17,
220+ GAUDI2_QUEUE_ID_DCORE0_MME_0_2 = 18,
221+ GAUDI2_QUEUE_ID_DCORE0_MME_0_3 = 19,
222+ GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 = 20,
223+ GAUDI2_QUEUE_ID_DCORE0_TPC_0_1 = 21,
224+ GAUDI2_QUEUE_ID_DCORE0_TPC_0_2 = 22,
225+ GAUDI2_QUEUE_ID_DCORE0_TPC_0_3 = 23,
226+ GAUDI2_QUEUE_ID_DCORE0_TPC_1_0 = 24,
227+ GAUDI2_QUEUE_ID_DCORE0_TPC_1_1 = 25,
228+ GAUDI2_QUEUE_ID_DCORE0_TPC_1_2 = 26,
229+ GAUDI2_QUEUE_ID_DCORE0_TPC_1_3 = 27,
230+ GAUDI2_QUEUE_ID_DCORE0_TPC_2_0 = 28,
231+ GAUDI2_QUEUE_ID_DCORE0_TPC_2_1 = 29,
232+ GAUDI2_QUEUE_ID_DCORE0_TPC_2_2 = 30,
233+ GAUDI2_QUEUE_ID_DCORE0_TPC_2_3 = 31,
234+ GAUDI2_QUEUE_ID_DCORE0_TPC_3_0 = 32,
235+ GAUDI2_QUEUE_ID_DCORE0_TPC_3_1 = 33,
236+ GAUDI2_QUEUE_ID_DCORE0_TPC_3_2 = 34,
237+ GAUDI2_QUEUE_ID_DCORE0_TPC_3_3 = 35,
238+ GAUDI2_QUEUE_ID_DCORE0_TPC_4_0 = 36,
239+ GAUDI2_QUEUE_ID_DCORE0_TPC_4_1 = 37,
240+ GAUDI2_QUEUE_ID_DCORE0_TPC_4_2 = 38,
241+ GAUDI2_QUEUE_ID_DCORE0_TPC_4_3 = 39,
242+ GAUDI2_QUEUE_ID_DCORE0_TPC_5_0 = 40,
243+ GAUDI2_QUEUE_ID_DCORE0_TPC_5_1 = 41,
244+ GAUDI2_QUEUE_ID_DCORE0_TPC_5_2 = 42,
245+ GAUDI2_QUEUE_ID_DCORE0_TPC_5_3 = 43,
246+ GAUDI2_QUEUE_ID_DCORE0_TPC_6_0 = 44,
247+ GAUDI2_QUEUE_ID_DCORE0_TPC_6_1 = 45,
248+ GAUDI2_QUEUE_ID_DCORE0_TPC_6_2 = 46,
249+ GAUDI2_QUEUE_ID_DCORE0_TPC_6_3 = 47,
250+ GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0 = 48,
251+ GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1 = 49,
252+ GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2 = 50,
253+ GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3 = 51,
254+ GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0 = 52,
255+ GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1 = 53,
256+ GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2 = 54,
257+ GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3 = 55,
258+ GAUDI2_QUEUE_ID_DCORE1_MME_0_0 = 56,
259+ GAUDI2_QUEUE_ID_DCORE1_MME_0_1 = 57,
260+ GAUDI2_QUEUE_ID_DCORE1_MME_0_2 = 58,
261+ GAUDI2_QUEUE_ID_DCORE1_MME_0_3 = 59,
262+ GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 = 60,
263+ GAUDI2_QUEUE_ID_DCORE1_TPC_0_1 = 61,
264+ GAUDI2_QUEUE_ID_DCORE1_TPC_0_2 = 62,
265+ GAUDI2_QUEUE_ID_DCORE1_TPC_0_3 = 63,
266+ GAUDI2_QUEUE_ID_DCORE1_TPC_1_0 = 64,
267+ GAUDI2_QUEUE_ID_DCORE1_TPC_1_1 = 65,
268+ GAUDI2_QUEUE_ID_DCORE1_TPC_1_2 = 66,
269+ GAUDI2_QUEUE_ID_DCORE1_TPC_1_3 = 67,
270+ GAUDI2_QUEUE_ID_DCORE1_TPC_2_0 = 68,
271+ GAUDI2_QUEUE_ID_DCORE1_TPC_2_1 = 69,
272+ GAUDI2_QUEUE_ID_DCORE1_TPC_2_2 = 70,
273+ GAUDI2_QUEUE_ID_DCORE1_TPC_2_3 = 71,
274+ GAUDI2_QUEUE_ID_DCORE1_TPC_3_0 = 72,
275+ GAUDI2_QUEUE_ID_DCORE1_TPC_3_1 = 73,
276+ GAUDI2_QUEUE_ID_DCORE1_TPC_3_2 = 74,
277+ GAUDI2_QUEUE_ID_DCORE1_TPC_3_3 = 75,
278+ GAUDI2_QUEUE_ID_DCORE1_TPC_4_0 = 76,
279+ GAUDI2_QUEUE_ID_DCORE1_TPC_4_1 = 77,
280+ GAUDI2_QUEUE_ID_DCORE1_TPC_4_2 = 78,
281+ GAUDI2_QUEUE_ID_DCORE1_TPC_4_3 = 79,
282+ GAUDI2_QUEUE_ID_DCORE1_TPC_5_0 = 80,
283+ GAUDI2_QUEUE_ID_DCORE1_TPC_5_1 = 81,
284+ GAUDI2_QUEUE_ID_DCORE1_TPC_5_2 = 82,
285+ GAUDI2_QUEUE_ID_DCORE1_TPC_5_3 = 83,
286+ GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0 = 84,
287+ GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1 = 85,
288+ GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2 = 86,
289+ GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3 = 87,
290+ GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0 = 88,
291+ GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1 = 89,
292+ GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2 = 90,
293+ GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3 = 91,
294+ GAUDI2_QUEUE_ID_DCORE2_MME_0_0 = 92,
295+ GAUDI2_QUEUE_ID_DCORE2_MME_0_1 = 93,
296+ GAUDI2_QUEUE_ID_DCORE2_MME_0_2 = 94,
297+ GAUDI2_QUEUE_ID_DCORE2_MME_0_3 = 95,
298+ GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 = 96,
299+ GAUDI2_QUEUE_ID_DCORE2_TPC_0_1 = 97,
300+ GAUDI2_QUEUE_ID_DCORE2_TPC_0_2 = 98,
301+ GAUDI2_QUEUE_ID_DCORE2_TPC_0_3 = 99,
302+ GAUDI2_QUEUE_ID_DCORE2_TPC_1_0 = 100,
303+ GAUDI2_QUEUE_ID_DCORE2_TPC_1_1 = 101,
304+ GAUDI2_QUEUE_ID_DCORE2_TPC_1_2 = 102,
305+ GAUDI2_QUEUE_ID_DCORE2_TPC_1_3 = 103,
306+ GAUDI2_QUEUE_ID_DCORE2_TPC_2_0 = 104,
307+ GAUDI2_QUEUE_ID_DCORE2_TPC_2_1 = 105,
308+ GAUDI2_QUEUE_ID_DCORE2_TPC_2_2 = 106,
309+ GAUDI2_QUEUE_ID_DCORE2_TPC_2_3 = 107,
310+ GAUDI2_QUEUE_ID_DCORE2_TPC_3_0 = 108,
311+ GAUDI2_QUEUE_ID_DCORE2_TPC_3_1 = 109,
312+ GAUDI2_QUEUE_ID_DCORE2_TPC_3_2 = 110,
313+ GAUDI2_QUEUE_ID_DCORE2_TPC_3_3 = 111,
314+ GAUDI2_QUEUE_ID_DCORE2_TPC_4_0 = 112,
315+ GAUDI2_QUEUE_ID_DCORE2_TPC_4_1 = 113,
316+ GAUDI2_QUEUE_ID_DCORE2_TPC_4_2 = 114,
317+ GAUDI2_QUEUE_ID_DCORE2_TPC_4_3 = 115,
318+ GAUDI2_QUEUE_ID_DCORE2_TPC_5_0 = 116,
319+ GAUDI2_QUEUE_ID_DCORE2_TPC_5_1 = 117,
320+ GAUDI2_QUEUE_ID_DCORE2_TPC_5_2 = 118,
321+ GAUDI2_QUEUE_ID_DCORE2_TPC_5_3 = 119,
322+ GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0 = 120,
323+ GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1 = 121,
324+ GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2 = 122,
325+ GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3 = 123,
326+ GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0 = 124,
327+ GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1 = 125,
328+ GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2 = 126,
329+ GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3 = 127,
330+ GAUDI2_QUEUE_ID_DCORE3_MME_0_0 = 128,
331+ GAUDI2_QUEUE_ID_DCORE3_MME_0_1 = 129,
332+ GAUDI2_QUEUE_ID_DCORE3_MME_0_2 = 130,
333+ GAUDI2_QUEUE_ID_DCORE3_MME_0_3 = 131,
334+ GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 = 132,
335+ GAUDI2_QUEUE_ID_DCORE3_TPC_0_1 = 133,
336+ GAUDI2_QUEUE_ID_DCORE3_TPC_0_2 = 134,
337+ GAUDI2_QUEUE_ID_DCORE3_TPC_0_3 = 135,
338+ GAUDI2_QUEUE_ID_DCORE3_TPC_1_0 = 136,
339+ GAUDI2_QUEUE_ID_DCORE3_TPC_1_1 = 137,
340+ GAUDI2_QUEUE_ID_DCORE3_TPC_1_2 = 138,
341+ GAUDI2_QUEUE_ID_DCORE3_TPC_1_3 = 139,
342+ GAUDI2_QUEUE_ID_DCORE3_TPC_2_0 = 140,
343+ GAUDI2_QUEUE_ID_DCORE3_TPC_2_1 = 141,
344+ GAUDI2_QUEUE_ID_DCORE3_TPC_2_2 = 142,
345+ GAUDI2_QUEUE_ID_DCORE3_TPC_2_3 = 143,
346+ GAUDI2_QUEUE_ID_DCORE3_TPC_3_0 = 144,
347+ GAUDI2_QUEUE_ID_DCORE3_TPC_3_1 = 145,
348+ GAUDI2_QUEUE_ID_DCORE3_TPC_3_2 = 146,
349+ GAUDI2_QUEUE_ID_DCORE3_TPC_3_3 = 147,
350+ GAUDI2_QUEUE_ID_DCORE3_TPC_4_0 = 148,
351+ GAUDI2_QUEUE_ID_DCORE3_TPC_4_1 = 149,
352+ GAUDI2_QUEUE_ID_DCORE3_TPC_4_2 = 150,
353+ GAUDI2_QUEUE_ID_DCORE3_TPC_4_3 = 151,
354+ GAUDI2_QUEUE_ID_DCORE3_TPC_5_0 = 152,
355+ GAUDI2_QUEUE_ID_DCORE3_TPC_5_1 = 153,
356+ GAUDI2_QUEUE_ID_DCORE3_TPC_5_2 = 154,
357+ GAUDI2_QUEUE_ID_DCORE3_TPC_5_3 = 155,
358+ GAUDI2_QUEUE_ID_NIC_0_0 = 156,
359+ GAUDI2_QUEUE_ID_NIC_0_1 = 157,
360+ GAUDI2_QUEUE_ID_NIC_0_2 = 158,
361+ GAUDI2_QUEUE_ID_NIC_0_3 = 159,
362+ GAUDI2_QUEUE_ID_NIC_1_0 = 160,
363+ GAUDI2_QUEUE_ID_NIC_1_1 = 161,
364+ GAUDI2_QUEUE_ID_NIC_1_2 = 162,
365+ GAUDI2_QUEUE_ID_NIC_1_3 = 163,
366+ GAUDI2_QUEUE_ID_NIC_2_0 = 164,
367+ GAUDI2_QUEUE_ID_NIC_2_1 = 165,
368+ GAUDI2_QUEUE_ID_NIC_2_2 = 166,
369+ GAUDI2_QUEUE_ID_NIC_2_3 = 167,
370+ GAUDI2_QUEUE_ID_NIC_3_0 = 168,
371+ GAUDI2_QUEUE_ID_NIC_3_1 = 169,
372+ GAUDI2_QUEUE_ID_NIC_3_2 = 170,
373+ GAUDI2_QUEUE_ID_NIC_3_3 = 171,
374+ GAUDI2_QUEUE_ID_NIC_4_0 = 172,
375+ GAUDI2_QUEUE_ID_NIC_4_1 = 173,
376+ GAUDI2_QUEUE_ID_NIC_4_2 = 174,
377+ GAUDI2_QUEUE_ID_NIC_4_3 = 175,
378+ GAUDI2_QUEUE_ID_NIC_5_0 = 176,
379+ GAUDI2_QUEUE_ID_NIC_5_1 = 177,
380+ GAUDI2_QUEUE_ID_NIC_5_2 = 178,
381+ GAUDI2_QUEUE_ID_NIC_5_3 = 179,
382+ GAUDI2_QUEUE_ID_NIC_6_0 = 180,
383+ GAUDI2_QUEUE_ID_NIC_6_1 = 181,
384+ GAUDI2_QUEUE_ID_NIC_6_2 = 182,
385+ GAUDI2_QUEUE_ID_NIC_6_3 = 183,
386+ GAUDI2_QUEUE_ID_NIC_7_0 = 184,
387+ GAUDI2_QUEUE_ID_NIC_7_1 = 185,
388+ GAUDI2_QUEUE_ID_NIC_7_2 = 186,
389+ GAUDI2_QUEUE_ID_NIC_7_3 = 187,
390+ GAUDI2_QUEUE_ID_NIC_8_0 = 188,
391+ GAUDI2_QUEUE_ID_NIC_8_1 = 189,
392+ GAUDI2_QUEUE_ID_NIC_8_2 = 190,
393+ GAUDI2_QUEUE_ID_NIC_8_3 = 191,
394+ GAUDI2_QUEUE_ID_NIC_9_0 = 192,
395+ GAUDI2_QUEUE_ID_NIC_9_1 = 193,
396+ GAUDI2_QUEUE_ID_NIC_9_2 = 194,
397+ GAUDI2_QUEUE_ID_NIC_9_3 = 195,
398+ GAUDI2_QUEUE_ID_NIC_10_0 = 196,
399+ GAUDI2_QUEUE_ID_NIC_10_1 = 197,
400+ GAUDI2_QUEUE_ID_NIC_10_2 = 198,
401+ GAUDI2_QUEUE_ID_NIC_10_3 = 199,
402+ GAUDI2_QUEUE_ID_NIC_11_0 = 200,
403+ GAUDI2_QUEUE_ID_NIC_11_1 = 201,
404+ GAUDI2_QUEUE_ID_NIC_11_2 = 202,
405+ GAUDI2_QUEUE_ID_NIC_11_3 = 203,
406+ GAUDI2_QUEUE_ID_NIC_12_0 = 204,
407+ GAUDI2_QUEUE_ID_NIC_12_1 = 205,
408+ GAUDI2_QUEUE_ID_NIC_12_2 = 206,
409+ GAUDI2_QUEUE_ID_NIC_12_3 = 207,
410+ GAUDI2_QUEUE_ID_NIC_13_0 = 208,
411+ GAUDI2_QUEUE_ID_NIC_13_1 = 209,
412+ GAUDI2_QUEUE_ID_NIC_13_2 = 210,
413+ GAUDI2_QUEUE_ID_NIC_13_3 = 211,
414+ GAUDI2_QUEUE_ID_NIC_14_0 = 212,
415+ GAUDI2_QUEUE_ID_NIC_14_1 = 213,
416+ GAUDI2_QUEUE_ID_NIC_14_2 = 214,
417+ GAUDI2_QUEUE_ID_NIC_14_3 = 215,
418+ GAUDI2_QUEUE_ID_NIC_15_0 = 216,
419+ GAUDI2_QUEUE_ID_NIC_15_1 = 217,
420+ GAUDI2_QUEUE_ID_NIC_15_2 = 218,
421+ GAUDI2_QUEUE_ID_NIC_15_3 = 219,
422+ GAUDI2_QUEUE_ID_NIC_16_0 = 220,
423+ GAUDI2_QUEUE_ID_NIC_16_1 = 221,
424+ GAUDI2_QUEUE_ID_NIC_16_2 = 222,
425+ GAUDI2_QUEUE_ID_NIC_16_3 = 223,
426+ GAUDI2_QUEUE_ID_NIC_17_0 = 224,
427+ GAUDI2_QUEUE_ID_NIC_17_1 = 225,
428+ GAUDI2_QUEUE_ID_NIC_17_2 = 226,
429+ GAUDI2_QUEUE_ID_NIC_17_3 = 227,
430+ GAUDI2_QUEUE_ID_NIC_18_0 = 228,
431+ GAUDI2_QUEUE_ID_NIC_18_1 = 229,
432+ GAUDI2_QUEUE_ID_NIC_18_2 = 230,
433+ GAUDI2_QUEUE_ID_NIC_18_3 = 231,
434+ GAUDI2_QUEUE_ID_NIC_19_0 = 232,
435+ GAUDI2_QUEUE_ID_NIC_19_1 = 233,
436+ GAUDI2_QUEUE_ID_NIC_19_2 = 234,
437+ GAUDI2_QUEUE_ID_NIC_19_3 = 235,
438+ GAUDI2_QUEUE_ID_NIC_20_0 = 236,
439+ GAUDI2_QUEUE_ID_NIC_20_1 = 237,
440+ GAUDI2_QUEUE_ID_NIC_20_2 = 238,
441+ GAUDI2_QUEUE_ID_NIC_20_3 = 239,
442+ GAUDI2_QUEUE_ID_NIC_21_0 = 240,
443+ GAUDI2_QUEUE_ID_NIC_21_1 = 241,
444+ GAUDI2_QUEUE_ID_NIC_21_2 = 242,
445+ GAUDI2_QUEUE_ID_NIC_21_3 = 243,
446+ GAUDI2_QUEUE_ID_NIC_22_0 = 244,
447+ GAUDI2_QUEUE_ID_NIC_22_1 = 245,
448+ GAUDI2_QUEUE_ID_NIC_22_2 = 246,
449+ GAUDI2_QUEUE_ID_NIC_22_3 = 247,
450+ GAUDI2_QUEUE_ID_NIC_23_0 = 248,
451+ GAUDI2_QUEUE_ID_NIC_23_1 = 249,
452+ GAUDI2_QUEUE_ID_NIC_23_2 = 250,
453+ GAUDI2_QUEUE_ID_NIC_23_3 = 251,
454+ GAUDI2_QUEUE_ID_ROT_0_0 = 252,
455+ GAUDI2_QUEUE_ID_ROT_0_1 = 253,
456+ GAUDI2_QUEUE_ID_ROT_0_2 = 254,
457+ GAUDI2_QUEUE_ID_ROT_0_3 = 255,
458+ GAUDI2_QUEUE_ID_ROT_1_0 = 256,
459+ GAUDI2_QUEUE_ID_ROT_1_1 = 257,
460+ GAUDI2_QUEUE_ID_ROT_1_2 = 258,
461+ GAUDI2_QUEUE_ID_ROT_1_3 = 259,
462+ GAUDI2_QUEUE_ID_CPU_PQ = 260,
463+ GAUDI2_QUEUE_ID_SIZE
464+};
465+
187466 /*
188467 * Engine Numbering
189468 *
@@ -242,6 +521,85 @@ enum gaudi_engine_id { · 52 unmodified lines
242521 GAUDI_ENGINE_ID_SIZE
243522 };
244523
524+enum gaudi2_engine_id {
525+ GAUDI2_DCORE0_ENGINE_ID_EDMA_0 = 0,
526+ GAUDI2_DCORE0_ENGINE_ID_EDMA_1,
527+ GAUDI2_DCORE0_ENGINE_ID_MME,
528+ GAUDI2_DCORE0_ENGINE_ID_TPC_0,
529+ GAUDI2_DCORE0_ENGINE_ID_TPC_1,
530+ GAUDI2_DCORE0_ENGINE_ID_TPC_2,
531+ GAUDI2_DCORE0_ENGINE_ID_TPC_3,
532+ GAUDI2_DCORE0_ENGINE_ID_TPC_4,
533+ GAUDI2_DCORE0_ENGINE_ID_TPC_5,
534+ GAUDI2_DCORE0_ENGINE_ID_DEC_0,
535+ GAUDI2_DCORE0_ENGINE_ID_DEC_1,
536+ GAUDI2_DCORE1_ENGINE_ID_EDMA_0,
537+ GAUDI2_DCORE1_ENGINE_ID_EDMA_1,
538+ GAUDI2_DCORE1_ENGINE_ID_MME,
539+ GAUDI2_DCORE1_ENGINE_ID_TPC_0,
540+ GAUDI2_DCORE1_ENGINE_ID_TPC_1,
541+ GAUDI2_DCORE1_ENGINE_ID_TPC_2,
542+ GAUDI2_DCORE1_ENGINE_ID_TPC_3,
543+ GAUDI2_DCORE1_ENGINE_ID_TPC_4,
544+ GAUDI2_DCORE1_ENGINE_ID_TPC_5,
545+ GAUDI2_DCORE1_ENGINE_ID_DEC_0,
546+ GAUDI2_DCORE1_ENGINE_ID_DEC_1,
547+ GAUDI2_DCORE2_ENGINE_ID_EDMA_0,
548+ GAUDI2_DCORE2_ENGINE_ID_EDMA_1,
549+ GAUDI2_DCORE2_ENGINE_ID_MME,
550+ GAUDI2_DCORE2_ENGINE_ID_TPC_0,
551+ GAUDI2_DCORE2_ENGINE_ID_TPC_1,
552+ GAUDI2_DCORE2_ENGINE_ID_TPC_2,
553+ GAUDI2_DCORE2_ENGINE_ID_TPC_3,
554+ GAUDI2_DCORE2_ENGINE_ID_TPC_4,
555+ GAUDI2_DCORE2_ENGINE_ID_TPC_5,
556+ GAUDI2_DCORE2_ENGINE_ID_DEC_0,
557+ GAUDI2_DCORE2_ENGINE_ID_DEC_1,
558+ GAUDI2_DCORE3_ENGINE_ID_EDMA_0,
559+ GAUDI2_DCORE3_ENGINE_ID_EDMA_1,
560+ GAUDI2_DCORE3_ENGINE_ID_MME,
561+ GAUDI2_DCORE3_ENGINE_ID_TPC_0,
562+ GAUDI2_DCORE3_ENGINE_ID_TPC_1,
563+ GAUDI2_DCORE3_ENGINE_ID_TPC_2,
564+ GAUDI2_DCORE3_ENGINE_ID_TPC_3,
565+ GAUDI2_DCORE3_ENGINE_ID_TPC_4,
566+ GAUDI2_DCORE3_ENGINE_ID_TPC_5,
567+ GAUDI2_DCORE3_ENGINE_ID_DEC_0,
568+ GAUDI2_DCORE3_ENGINE_ID_DEC_1,
569+ GAUDI2_DCORE0_ENGINE_ID_TPC_6,
570+ GAUDI2_ENGINE_ID_PDMA_0,
571+ GAUDI2_ENGINE_ID_PDMA_1,
572+ GAUDI2_ENGINE_ID_ROT_0,
573+ GAUDI2_ENGINE_ID_ROT_1,
574+ GAUDI2_PCIE_ENGINE_ID_DEC_0,
575+ GAUDI2_PCIE_ENGINE_ID_DEC_1,
576+ GAUDI2_ENGINE_ID_NIC0_0,
577+ GAUDI2_ENGINE_ID_NIC0_1,
578+ GAUDI2_ENGINE_ID_NIC1_0,
579+ GAUDI2_ENGINE_ID_NIC1_1,
580+ GAUDI2_ENGINE_ID_NIC2_0,
581+ GAUDI2_ENGINE_ID_NIC2_1,
582+ GAUDI2_ENGINE_ID_NIC3_0,
583+ GAUDI2_ENGINE_ID_NIC3_1,
584+ GAUDI2_ENGINE_ID_NIC4_0,
585+ GAUDI2_ENGINE_ID_NIC4_1,
586+ GAUDI2_ENGINE_ID_NIC5_0,
587+ GAUDI2_ENGINE_ID_NIC5_1,
588+ GAUDI2_ENGINE_ID_NIC6_0,
589+ GAUDI2_ENGINE_ID_NIC6_1,
590+ GAUDI2_ENGINE_ID_NIC7_0,
591+ GAUDI2_ENGINE_ID_NIC7_1,
592+ GAUDI2_ENGINE_ID_NIC8_0,
593+ GAUDI2_ENGINE_ID_NIC8_1,
594+ GAUDI2_ENGINE_ID_NIC9_0,
595+ GAUDI2_ENGINE_ID_NIC9_1,
596+ GAUDI2_ENGINE_ID_NIC10_0,
597+ GAUDI2_ENGINE_ID_NIC10_1,
598+ GAUDI2_ENGINE_ID_NIC11_0,
599+ GAUDI2_ENGINE_ID_NIC11_1,
600+ GAUDI2_ENGINE_ID_SIZE
601+};
602+
245603 /*
246604 * ASIC specific PLL index
247605 *
@@ -275,6 +633,22 @@ enum hl_gaudi_pll_index { · 27 unmodified lines
275633 HL_GAUDI_PLL_MAX
276634 };
277635
636+enum hl_gaudi2_pll_index {
637+ HL_GAUDI2_CPU_PLL = 0,
638+ HL_GAUDI2_PCI_PLL,
639+ HL_GAUDI2_SRAM_PLL,
640+ HL_GAUDI2_HBM_PLL,
641+ HL_GAUDI2_NIC_PLL,
642+ HL_GAUDI2_DMA_PLL,
643+ HL_GAUDI2_MESH_PLL,
644+ HL_GAUDI2_MME_PLL,
645+ HL_GAUDI2_TPC_PLL,
646+ HL_GAUDI2_IF_PLL,
647+ HL_GAUDI2_VID_PLL,
648+ HL_GAUDI2_MSS_PLL,
649+ HL_GAUDI2_PLL_MAX
650+};
651+
278652 /**
279653 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is
280654 * submitted to the GOYA's DMA QMAN. This attribute is not relevant
@@ -326,7 +700,8 @@ enum hl_server_type { · 45 unmodified lines
326700 HL_SERVER_GAUDI_HLS1 = 1,
327701 HL_SERVER_GAUDI_HLS1H = 2,
328702 HL_SERVER_GAUDI_TYPE1 = 3,
329− HL_SERVER_GAUDI_TYPE2 = 4
703+ HL_SERVER_GAUDI_TYPE2 = 4,
704+ HL_SERVER_GAUDI2_HLS2 = 5
330705 };
331706
332707 /* Opcode for management ioctl
@@ -428,8 +803,10 @@ enum hl_server_type { · 95 unmodified lines
428803 * @device_id: PCI device ID of the ASIC.
429804 * @module_id: Module ID of the ASIC for mezzanine cards in servers
430805 * (From OCP spec).
806+ * @decoder_enabled_mask: Bit-mask that represents which decoders are enabled.
431807 * @first_available_interrupt_id: The first available interrupt ID for the user
432808 * to be used when it works with user interrupts.
809+ * Relevant for Gaudi2 and later.
433810 * @server_type: Server type that the Gaudi ASIC is currently installed in.
434811 * The value is according to enum hl_server_type
435812 * @cpld_version: CPLD version on the board.
@@ -441,9 +818,15 @@ enum hl_server_type { · 5 unmodified lines
441818 * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant
442819 * for Goya/Gaudi only.
443820 * @dram_enabled: Whether the DRAM is enabled.
821+ * @mme_master_slave_mode: Indicate whether the MME is working in master/slave
822+ * configuration. Relevant for Greco and later.
444823 * @cpucp_version: The CPUCP f/w version.
445824 * @card_name: The card name as passed by the f/w.
825+ * @tpc_enabled_mask_ext: Bit-mask that represents which TPCs are enabled.
826+ * Relevant for Greco and later.
446827 * @dram_page_size: The DRAM physical page size.
828+ * @edma_enabled_mask: Bit-mask that represents which EDMAs are enabled.
829+ * Relevant for Gaudi2 and later.
447830 * @number_of_user_interrupts: The number of interrupts that are available to the userspace
448831 * application to use. Relevant for Gaudi2 and later.
449832 * @device_mem_alloc_default_page_size: default page size used in device memory allocation.
@@ -456,7 +839,7 @@ struct hl_info_hw_ip_info { · 6 unmodified lines
456839 __u32 num_of_events;
457840 __u32 device_id;
458841 __u32 module_id;
459− __u32 reserved;
842+ __u32 decoder_enabled_mask;
460843 __u16 first_available_interrupt_id;
461844 __u16 server_type;
462845 __u32 cpld_version;
@@ -466,12 +849,13 @@ struct hl_info_hw_ip_info { · 3 unmodified lines
466849 __u32 psoc_pci_pll_div_factor;
467850 __u8 tpc_enabled_mask;
468851 __u8 dram_enabled;
469− __u8 pad[2];
852+ __u8 reserved;
853+ __u8 mme_master_slave_mode;
470854 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN];
471855 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
472− __u64 reserved2;
856+ __u64 tpc_enabled_mask_ext;
473857 __u64 dram_page_size;
474− __u32 reserved3;
858+ __u32 edma_enabled_mask;
475859 __u16 number_of_user_interrupts;
476860 __u16 pad2;
477861 __u64 reserved4;
@@ -821,16 +1205,16 @@ union hl_cb_args { · 343 unmodified lines
8211205 /* HL_CS_CHUNK_FLAGS_ values
8221206 *
8231207 * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB:
824− * Indicates if the CB was allocated and mapped by userspace.
825− * User allocated CB is a command buffer allocated by the user, via malloc
826− * (or similar). After allocating the CB, the user invokes “memory ioctl”
827− * to map the user memory into a device virtual address. The user provides
828− * this address via the cb_handle field. The interface provides the
829− * ability to create a large CBs, Which aren’t limited to
830− * “HL_MAX_CB_SIZE”. Therefore, it increases the PCI-DMA queues
831− * throughput. This CB allocation method also reduces the use of Linux
832− * DMA-able memory pool. Which are limited and used by other Linux
833− * sub-systems.
1208+ * Indicates if the CB was allocated and mapped by userspace
1209+ * (relevant to greco and above). User allocated CB is a command buffer,
1210+ * allocated by the user, via malloc (or similar). After allocating the
1211+ * CB, the user invokes - “memory ioctl” to map the user memory into a
1212+ * device virtual address. The user provides this address via the
1213+ * cb_handle field. The interface provides the ability to create a
1214+ * large CBs, Which aren’t limited to “HL_MAX_CB_SIZE”. Therefore, it
1215+ * increases the PCI-DMA queues throughput. This CB allocation method
1216+ * also reduces the use of Linux DMA-able memory pool. Which are limited
1217+ * and used by other Linux sub-systems.
8341218 */
8351219 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1
8361220
@@ -840,12 +1224,17 @@ union hl_cb_args { · 3 unmodified lines
8401224 */
8411225 struct hl_cs_chunk {
8421226 union {
843− /* For external queue, this represents a Handle of CB on the
1227+ /* Goya/Gaudi:
1228+ * For external queue, this represents a Handle of CB on the
8441229 * Host.
8451230 * For internal queue in Goya, this represents an SRAM or
8461231 * a DRAM address of the internal CB. In Gaudi, this might also
8471232 * represent a mapped host address of the CB.
8481233 *
1234+ * Greco onwards:
1235+ * For H/W queue, this represents either a Handle of CB on the
1236+ * Host, or an SRAM, a DRAM, or a mapped host address of the CB.
1237+ *
8491238 * A mapped host address is in the device address space, after
8501239 * a host address was mapped by the device MMU.
8511240 */
@@ -910,11 +1299,12 @@ struct hl_cs_chunk { · 58 unmodified lines
9101299 __u32 pad[10];
9111300 };
9121301
913−/* SIGNAL and WAIT/COLLECTIVE_WAIT flags are mutually exclusive */
1302+/* SIGNAL/WAIT/COLLECTIVE_WAIT flags are mutually exclusive */
9141303 #define HL_CS_FLAGS_FORCE_RESTORE 0x1
9151304 #define HL_CS_FLAGS_SIGNAL 0x2
9161305 #define HL_CS_FLAGS_WAIT 0x4
9171306 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8
1307+
9181308 #define HL_CS_FLAGS_TIMESTAMP 0x20
9191309 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40
9201310 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80
@@ -1174,14 +1564,19 @@ union hl_wait_cs_args { · 253 unmodified lines
11741564
11751565 /* Opcode to allocate device memory */
11761566 #define HL_MEM_OP_ALLOC 0
1567+
11771568 /* Opcode to free previously allocated device memory */
11781569 #define HL_MEM_OP_FREE 1
1570+
11791571 /* Opcode to map host and device memory */
11801572 #define HL_MEM_OP_MAP 2
1573+
11811574 /* Opcode to unmap previously mapped host and device memory */
11821575 #define HL_MEM_OP_UNMAP 3
1576+
11831577 /* Opcode to map a hw block */
11841578 #define HL_MEM_OP_MAP_BLOCK 4
1579+
11851580 /* Opcode to create DMA-BUF object for an existing device memory allocation
11861581 * and to export an FD of that DMA-BUF back to the caller
11871582 */
@@ -1400,7 +1795,16 @@ struct hl_debug_params_bmon { · 212 unmodified lines
14001795
14011796 /* Trace source ID */
14021797 __u32 id;
1403− __u32 pad;
1798+
1799+ /* Control register */
1800+ __u32 control;
1801+
1802+ /* Two more address ranges that the user can request to filter */
1803+ __u64 start_addr2;
1804+ __u64 end_addr2;
1805+
1806+ __u64 start_addr3;
1807+ __u64 end_addr3;
14041808 };
14051809
14061810 struct hl_debug_params_spmu {
@@ -1409,7 +1813,11 @@ struct hl_debug_params_spmu { · 2 unmodified lines
14091813
14101814 /* Number of event types selection */
14111815 __u32 event_types_num;
1412− __u32 pad;
1816+
1817+ /* TRC configuration register values */
1818+ __u32 pmtrc_val;
1819+ __u32 trc_ctrl_host_val;
1820+ __u32 trc_en_host_val;
14131821 };
14141822
14151823 /* Opcode for ETR component */
@@ -1524,16 +1932,23 @@ struct hl_debug_args { · 108 unmodified lines
15241932 * (or if its the first CS for this context). The user can also order the
15251933 * driver to run the "restore" phase explicitly
15261934 *
1935+ * Goya/Gaudi:
15271936 * There are two types of queues - external and internal. External queues
15281937 * are DMA queues which transfer data from/to the Host. All other queues are
15291938 * internal. The driver will get completion notifications from the device only
15301939 * on JOBS which are enqueued in the external queues.
15311940 *
1941+ * Greco onwards:
1942+ * There is a single type of queue for all types of engines, either DMA engines
1943+ * for transfers from/to the host or inside the device, or compute engines.
1944+ * The driver will get completion notifications from the device for all queues.
1945+ *
15321946 * For jobs on external queues, the user needs to create command buffers
15331947 * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on
15341948 * internal queues, the user needs to prepare a "command buffer" with packets
15351949 * on either the device SRAM/DRAM or the host, and give the device address of
15361950 * that buffer to the CS ioctl.
1951+ * For jobs on H/W queues both options of command buffers are valid.
15371952 *
15381953 * This IOCTL is asynchronous in regard to the actual execution of the CS. This
15391954 * means it returns immediately after ALL the JOBS were enqueued on their
@@ -1542,7 +1957,7 @@ struct hl_debug_args { · 2 unmodified lines
15421957 *
15431958 * Upon successful enqueue, the IOCTL returns a sequence number which the user
15441959 * can use with the "Wait for CS" IOCTL to check whether the handle's CS
1545− * external JOBS have been completed. Note that if the CS has internal JOBS
1960+ * non-internal JOBS have been completed. Note that if the CS has internal JOBS
15461961 * which can execute AFTER the external JOBS have finished, the driver might
15471962 * report that the CS has finished executing BEFORE the internal JOBS have
15481963 * actually finished executing.