powerpc/mm: Fixup kernel read only mapping

With commit e58e87adc8bf9 ("powerpc/mm: Update _PAGE_KERNEL_RO") we started using the ppp value 0b110 to map kernel readonly. But that facility was only added as part of ISA 2.04. For earlier ISA version only supported ppp bit value for readonly mapping is 0b011. (This implies both user and kernel get mapped using the same ppp bit value for readonly mapping.). Update the code such that for earlier architecture version we use ppp value 0b011 for readonly mapping. We don't differentiate between power5+ and power5 here and apply the new ppp bits only from power6 (ISA 2.05). This keep the changes minimal. This fixes issue with PS3 spu usage reported at https://lkml.kernel.org/r/rep.1421449714.geoff@infradead.org

Aneesh Kumar K.V committed 9 years ago

Commit 984d7a11 parent a1ff5742 files · +16 −6Browse files

Unified · Split

2 files

arch/powerpc/include/asm/mmu.h +10 −4
arch/powerpc/mm/hash_utils_64.c +6 −2

arch/powerpc/include/asm/mmu.h+10−4

@@ -28,6 +28,12 @@ · 27 unmodified lines
28	28	* Individual features below.
29	29	*/
30	30
	31	+/*
	32	+ * Kernel read only support.
	33	+ * We added the ppp value 0b110 in ISA 2.04.
	34	+ */
	35	+#define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000)
	36	+
31	37	/*
32	38	* We need to clear top 16bits of va (from the remaining 64 bits )in
33	39	* tlbie* instructions
@@ -103,10 +109,10 @@ · 69 unmodified lines
103	109	#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
104	110	#define MMU_FTRS_PPC970 MMU_FTRS_POWER4 \| MMU_FTR_TLBIE_CROP_VA
105	111	#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
106		−#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
107		−#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
108		−#define MMU_FTRS_POWER8 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
109		−#define MMU_FTRS_POWER9 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
	112	+#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE \| MMU_FTR_KERNEL_RO
	113	+#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE \| MMU_FTR_KERNEL_RO
	114	+#define MMU_FTRS_POWER8 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE \| MMU_FTR_KERNEL_RO
	115	+#define MMU_FTRS_POWER9 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE \| MMU_FTR_KERNEL_RO
110	116	#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \| \
111	117	MMU_FTR_CI_LARGE_PAGE
112	118	#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \| \

arch/powerpc/mm/hash_utils_64.c+6−2

@@ -193,8 +193,12 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags) · 192 unmodified lines
193	193	/*
194	194	* Kernel read only mapped with ppp bits 0b110
195	195	*/
196		− if (!(pteflags & _PAGE_WRITE))
197		− rflags \|= (HPTE_R_PP0 \| 0x2);
	196	+ if (!(pteflags & _PAGE_WRITE)) {
	197	+ if (mmu_has_feature(MMU_FTR_KERNEL_RO))
	198	+ rflags \|= (HPTE_R_PP0 \| 0x2);
	199	+ else
	200	+ rflags \|= 0x3;
	201	+ }
198	202	} else {
199	203	if (pteflags & _PAGE_RWX)
200	204	rflags \|= 0x2;