Since the sys_info and flash_info registers differ significantly in Gen4 hardware, separate out the Gen3 registers into their own structure with a union in the main structure. No functional changes intended.
Unified · Split
| @@ -317,8 +317,12 @@ static ssize_t field ## _show(struct device *dev, \ · 316 unmodified lines | ||
| 317 | 317 | struct device_attribute *attr, char *buf) \ |
| 318 | 318 | { \ |
| 319 | 319 | struct switchtec_dev *stdev = to_stdev(dev); \ |
| 320 | − return io_string_show(buf, &stdev->mmio_sys_info->field, \ | |
| 321 | − sizeof(stdev->mmio_sys_info->field)); \ | |
| 320 | + struct sys_info_regs __iomem *si = stdev->mmio_sys_info; \ | |
| 321 | + if (stdev->gen == SWITCHTEC_GEN3) \ | |
| 322 | + return io_string_show(buf, &si->gen3.field, \ | |
| 323 | + sizeof(si->gen3.field)); \ | |
| 324 | + else \ | |
| 325 | + return -ENOTSUPP; \ | |
| 322 | 326 | } \ |
| 323 | 327 | \ |
| 324 | 328 | static DEVICE_ATTR_RO(field) |
| @@ -337,8 +341,8 @@ static ssize_t component_vendor_show(struct device *dev, · 12 unmodified lines | ||
| 337 | 341 | if (stdev->gen != SWITCHTEC_GEN3) |
| 338 | 342 | return sprintf(buf, "none\n"); |
| 339 | 343 | |
| 340 | − return io_string_show(buf, &si->component_vendor, | |
| 341 | − sizeof(si->component_vendor)); | |
| 344 | + return io_string_show(buf, &si->gen3.component_vendor, | |
| 345 | + sizeof(si->gen3.component_vendor)); | |
| 342 | 346 | } |
| 343 | 347 | static DEVICE_ATTR_RO(component_vendor); |
| 344 | 348 | |
| @@ -346,7 +350,7 @@ static ssize_t component_id_show(struct device *dev, · 1 unmodified line | ||
| 346 | 350 | struct device_attribute *attr, char *buf) |
| 347 | 351 | { |
| 348 | 352 | struct switchtec_dev *stdev = to_stdev(dev); |
| 349 | − int id = ioread16(&stdev->mmio_sys_info->component_id); | |
| 353 | + int id = ioread16(&stdev->mmio_sys_info->gen3.component_id); | |
| 350 | 354 | |
| 351 | 355 | /* component_id field not supported after gen3 */ |
| 352 | 356 | if (stdev->gen != SWITCHTEC_GEN3) |
| @@ -360,7 +364,7 @@ static ssize_t component_revision_show(struct device *dev, · 7 unmodified lines | ||
| 360 | 364 | struct device_attribute *attr, char *buf) |
| 361 | 365 | { |
| 362 | 366 | struct switchtec_dev *stdev = to_stdev(dev); |
| 363 | − int rev = ioread8(&stdev->mmio_sys_info->component_revision); | |
| 367 | + int rev = ioread8(&stdev->mmio_sys_info->gen3.component_revision); | |
| 364 | 368 | |
| 365 | 369 | /* component_revision field not supported after gen3 */ |
| 366 | 370 | if (stdev->gen != SWITCHTEC_GEN3) |
| @@ -590,8 +594,12 @@ static int ioctl_flash_info(struct switchtec_dev *stdev, · 223 unmodified lines | ||
| 590 | 594 | struct switchtec_ioctl_flash_info info = {0}; |
| 591 | 595 | struct flash_info_regs __iomem *fi = stdev->mmio_flash_info; |
| 592 | 596 | |
| 593 | − info.flash_length = ioread32(&fi->flash_length); | |
| 594 | − info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN3; | |
| 597 | + if (stdev->gen == SWITCHTEC_GEN3) { | |
| 598 | + info.flash_length = ioread32(&fi->gen3.flash_length); | |
| 599 | + info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN3; | |
| 600 | + } else { | |
| 601 | + return -ENOTSUPP; | |
| 602 | + } | |
| 595 | 603 | |
| 596 | 604 | if (copy_to_user(uinfo, &info, sizeof(info))) |
| 597 | 605 | return -EFAULT; |
| @@ -609,8 +617,9 @@ static void set_fw_info_part(struct switchtec_ioctl_flash_part_info *info, · 11 unmodified lines | ||
| 609 | 617 | static int flash_part_info_gen3(struct switchtec_dev *stdev, |
| 610 | 618 | struct switchtec_ioctl_flash_part_info *info) |
| 611 | 619 | { |
| 612 | − struct flash_info_regs __iomem *fi = stdev->mmio_flash_info; | |
| 613 | − struct sys_info_regs __iomem *si = stdev->mmio_sys_info; | |
| 620 | + struct flash_info_regs_gen3 __iomem *fi = | |
| 621 | + &stdev->mmio_flash_info->gen3; | |
| 622 | + struct sys_info_regs_gen3 __iomem *si = &stdev->mmio_sys_info->gen3; | |
| 614 | 623 | u32 active_addr = -1; |
| 615 | 624 | |
| 616 | 625 | switch (info->flash_partition) { |
| @@ -1382,6 +1391,7 @@ static int switchtec_init_pci(struct switchtec_dev *stdev, · 765 unmodified lines | ||
| 1382 | 1391 | int rc; |
| 1383 | 1392 | void __iomem *map; |
| 1384 | 1393 | unsigned long res_start, res_len; |
| 1394 | + u32 __iomem *part_id; | |
| 1385 | 1395 | |
| 1386 | 1396 | rc = pcim_enable_device(pdev); |
| 1387 | 1397 | if (rc) |
| @@ -1416,7 +1426,13 @@ static int switchtec_init_pci(struct switchtec_dev *stdev, · 28 unmodified lines | ||
| 1416 | 1426 | stdev->mmio_sys_info = stdev->mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET; |
| 1417 | 1427 | stdev->mmio_flash_info = stdev->mmio + SWITCHTEC_GAS_FLASH_INFO_OFFSET; |
| 1418 | 1428 | stdev->mmio_ntb = stdev->mmio + SWITCHTEC_GAS_NTB_OFFSET; |
| 1419 | − stdev->partition = ioread8(&stdev->mmio_sys_info->partition_id); | |
| 1429 | + | |
| 1430 | + if (stdev->gen == SWITCHTEC_GEN3) | |
| 1431 | + part_id = &stdev->mmio_sys_info->gen3.partition_id; | |
| 1432 | + else | |
| 1433 | + return -ENOTSUPP; | |
| 1434 | + | |
| 1435 | + stdev->partition = ioread8(part_id); | |
| 1420 | 1436 | stdev->partition_count = ioread8(&stdev->mmio_ntb->partition_count); |
| 1421 | 1437 | stdev->mmio_part_cfg_all = stdev->mmio + SWITCHTEC_GAS_PART_CFG_OFFSET; |
| 1422 | 1438 | stdev->mmio_part_cfg = &stdev->mmio_part_cfg_all[stdev->partition]; |
| @@ -108,10 +108,7 @@ enum { · 107 unmodified lines | ||
| 108 | 108 | SWITCHTEC_GEN3_IMG1_RUNNING = 0x07, |
| 109 | 109 | }; |
| 110 | 110 | |
| 111 | −struct sys_info_regs { | |
| 112 | − u32 device_id; | |
| 113 | − u32 device_version; | |
| 114 | − u32 firmware_version; | |
| 111 | +struct sys_info_regs_gen3 { | |
| 115 | 112 | u32 reserved1; |
| 116 | 113 | u32 vendor_table_revision; |
| 117 | 114 | u32 table_format_version; |
| @@ -128,26 +125,36 @@ struct sys_info_regs { · 10 unmodified lines | ||
| 128 | 125 | u8 component_revision; |
| 129 | 126 | } __packed; |
| 130 | 127 | |
| 131 | −struct flash_info_regs { | |
| 128 | +struct sys_info_regs { | |
| 129 | + u32 device_id; | |
| 130 | + u32 device_version; | |
| 131 | + u32 firmware_version; | |
| 132 | + union { | |
| 133 | + struct sys_info_regs_gen3 gen3; | |
| 134 | + }; | |
| 135 | +} __packed; | |
| 136 | + | |
| 137 | +struct partition_info { | |
| 138 | + u32 address; | |
| 139 | + u32 length; | |
| 140 | +}; | |
| 141 | + | |
| 142 | +struct flash_info_regs_gen3 { | |
| 132 | 143 | u32 flash_part_map_upd_idx; |
| 133 | 144 | |
| 134 | − struct active_partition_info { | |
| 145 | + struct active_partition_info_gen3 { | |
| 135 | 146 | u32 address; |
| 136 | 147 | u32 build_version; |
| 137 | 148 | u32 build_string; |
| 138 | 149 | } active_img; |
| 139 | 150 | |
| 140 | − struct active_partition_info active_cfg; | |
| 141 | − struct active_partition_info inactive_img; | |
| 142 | − struct active_partition_info inactive_cfg; | |
| 151 | + struct active_partition_info_gen3 active_cfg; | |
| 152 | + struct active_partition_info_gen3 inactive_img; | |
| 153 | + struct active_partition_info_gen3 inactive_cfg; | |
| 143 | 154 | |
| 144 | 155 | u32 flash_length; |
| 145 | 156 | |
| 146 | − struct partition_info { | |
| 147 | − u32 address; | |
| 148 | − u32 length; | |
| 149 | − } cfg0; | |
| 150 | − | |
| 157 | + struct partition_info cfg0; | |
| 151 | 158 | struct partition_info cfg1; |
| 152 | 159 | struct partition_info img0; |
| 153 | 160 | struct partition_info img1; |
| @@ -155,6 +162,12 @@ struct flash_info_regs { · 1 unmodified line | ||
| 155 | 162 | struct partition_info vendor[8]; |
| 156 | 163 | }; |
| 157 | 164 | |
| 165 | +struct flash_info_regs { | |
| 166 | + union { | |
| 167 | + struct flash_info_regs_gen3 gen3; | |
| 168 | + }; | |
| 169 | +}; | |
| 170 | + | |
| 158 | 171 | enum { |
| 159 | 172 | SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000, |
| 160 | 173 | SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000, |