History

drm/i915/perf: remove generated code

A little bit of history : Back when i915-perf was introduced (4.13), there was no way to dynamically add new OA configurations to i915. Only the generated configs baked in at build time were allowed. It quickly became obvious that we would need to allow applications to upload their own configurations, for instance to be able to test new ones, and so by the next stable version (4.14) we added uAPIs to allow uploading new configurations. When adding that capability, we took the opportunity to remove most HW configurations except the TestOa one which is a configuration IGT would rely on to verify that the HW is outputting correct values. At the time it made sense to have that confiuration in at the same time a given HW platform added to the i915-perf driver. Now that IGT has become the reference point for HW configurations (see commit 53f8f541ca ("lib: Add i915_perf library"), previously this was located in the GPUTop repository), the need for having those configurations in i915-perf is gone. On the Mesa side, we haven't relied on this test configuration for a while. The MDAPI library always required 4.14 feature level and always loaded its configuration into i915. I'm sure nobody will miss this generated stuff in i915 :) v2: Fix selftests by creating an empty config v3: Fix unlocking on allocation error (Dan Carpenter) v4: Fixup checkpatch warnings v5: Fix incorrect unlock in error path (Umesh)

Lionel Landwerlin committed 6 years ago

Commit 9aba9c11 parent a22f34734 files · +96 −1757Browse files

Unified · Split

34 files
  1. drivers/gpu/drm/i915/Makefile +0 −17
  2. drivers/gpu/drm/i915/i915_perf.c +1 −80
  3. drivers/gpu/drm/i915/i915_perf_types.h +0 −2
  4. drivers/gpu/drm/i915/oa/i915_oa_bdw.c +0 −90
  5. drivers/gpu/drm/i915/oa/i915_oa_bdw.h +0 −16
  6. drivers/gpu/drm/i915/oa/i915_oa_bxt.c +0 −88
  7. drivers/gpu/drm/i915/oa/i915_oa_bxt.h +0 −16
  8. drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c +0 −89
  9. drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h +0 −16
  10. drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c +0 −89
  11. drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h +0 −16
  12. drivers/gpu/drm/i915/oa/i915_oa_chv.c +0 −89
  13. drivers/gpu/drm/i915/oa/i915_oa_chv.h +0 −16
  14. drivers/gpu/drm/i915/oa/i915_oa_cnl.c +0 −101
  15. drivers/gpu/drm/i915/oa/i915_oa_cnl.h +0 −16
  16. drivers/gpu/drm/i915/oa/i915_oa_glk.c +0 −88
  17. drivers/gpu/drm/i915/oa/i915_oa_glk.h +0 −16
  18. drivers/gpu/drm/i915/oa/i915_oa_hsw.c +0 −118
  19. drivers/gpu/drm/i915/oa/i915_oa_hsw.h +0 −16
  20. drivers/gpu/drm/i915/oa/i915_oa_icl.c +0 −98
  21. drivers/gpu/drm/i915/oa/i915_oa_icl.h +0 −16
  22. drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c +0 −89
  23. drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h +0 −16
  24. drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c +0 −89
  25. drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h +0 −16
  26. drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c +0 −88
  27. drivers/gpu/drm/i915/oa/i915_oa_sklgt2.h +0 −16
  28. drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c +0 −89
  29. drivers/gpu/drm/i915/oa/i915_oa_sklgt3.h +0 −16
  30. drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c +0 −89
  31. drivers/gpu/drm/i915/oa/i915_oa_sklgt4.h +0 −16
  32. drivers/gpu/drm/i915/oa/i915_oa_tgl.c +0 −121
  33. drivers/gpu/drm/i915/oa/i915_oa_tgl.h +0 −16
  34. drivers/gpu/drm/i915/selftests/i915_perf.c +95 −3
drivers/gpu/drm/i915/Makefile+0−17
@@ -243,23 +243,6 @@ i915-y += \ · 242 unmodified lines
243 display/vlv_dsi.o \243 display/vlv_dsi.o \
244 display/vlv_dsi_pll.o244 display/vlv_dsi_pll.o
245 245
246# perf code
247i915-y += \
248 oa/i915_oa_hsw.o \
249 oa/i915_oa_bdw.o \
250 oa/i915_oa_chv.o \
251 oa/i915_oa_sklgt2.o \
252 oa/i915_oa_sklgt3.o \
253 oa/i915_oa_sklgt4.o \
254 oa/i915_oa_bxt.o \
255 oa/i915_oa_kblgt2.o \
256 oa/i915_oa_kblgt3.o \
257 oa/i915_oa_glk.o \
258 oa/i915_oa_cflgt2.o \
259 oa/i915_oa_cflgt3.o \
260 oa/i915_oa_cnl.o \
261 oa/i915_oa_icl.o \
262 oa/i915_oa_tgl.o
263i915-y += i915_perf.o246i915-y += i915_perf.o
264 247
265# Post-mortem debug and GPU hang state capture248# Post-mortem debug and GPU hang state capture
drivers/gpu/drm/i915/i915_perf.c+1−80
@@ -204,21 +204,6 @@ · 203 unmodified lines
204 204
205#include "i915_drv.h"205#include "i915_drv.h"
206#include "i915_perf.h"206#include "i915_perf.h"
207#include "oa/i915_oa_hsw.h"
208#include "oa/i915_oa_bdw.h"
209#include "oa/i915_oa_chv.h"
210#include "oa/i915_oa_sklgt2.h"
211#include "oa/i915_oa_sklgt3.h"
212#include "oa/i915_oa_sklgt4.h"
213#include "oa/i915_oa_bxt.h"
214#include "oa/i915_oa_kblgt2.h"
215#include "oa/i915_oa_kblgt3.h"
216#include "oa/i915_oa_glk.h"
217#include "oa/i915_oa_cflgt2.h"
218#include "oa/i915_oa_cflgt3.h"
219#include "oa/i915_oa_cnl.h"
220#include "oa/i915_oa_icl.h"
221#include "oa/i915_oa_tgl.h"
222 207
223/* HW requires this to be a power of two, between 128k and 16M, though driver208/* HW requires this to be a power of two, between 128k and 16M, though driver
224 * is currently generally designed assuming the largest 16M size is used such209 * is currently generally designed assuming the largest 16M size is used such
@@ -409,10 +394,7 @@ i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set) · 184 unmodified lines
409 struct i915_oa_config *oa_config;394 struct i915_oa_config *oa_config;
410 395
411 rcu_read_lock();396 rcu_read_lock();
412 if (metrics_set == 1)397 oa_config = idr_find(&perf->metrics_idr, metrics_set);
413 oa_config = &perf->test_config;
414 else
415 oa_config = idr_find(&perf->metrics_idr, metrics_set);
416 if (oa_config)398 if (oa_config)
417 oa_config = i915_oa_config_get(oa_config);399 oa_config = i915_oa_config_get(oa_config);
418 rcu_read_unlock();400 rcu_read_unlock();
@@ -3716,7 +3698,6 @@ int i915_perf_open_ioctl(struct drm_device *dev, void *data, · 3297 unmodified lines
3716void i915_perf_register(struct drm_i915_private *i915)3698void i915_perf_register(struct drm_i915_private *i915)
3717{3699{
3718 struct i915_perf *perf = &i915->perf;3700 struct i915_perf *perf = &i915->perf;
3719 int ret;
3720 3701
3721 if (!perf->i915)3702 if (!perf->i915)
3722 return;3703 return;
@@ -3730,64 +3711,7 @@ void i915_perf_register(struct drm_i915_private *i915) · 7 unmodified lines
3730 perf->metrics_kobj =3711 perf->metrics_kobj =
3731 kobject_create_and_add("metrics",3712 kobject_create_and_add("metrics",
3732 &i915->drm.primary->kdev->kobj);3713 &i915->drm.primary->kdev->kobj);
3733 if (!perf->metrics_kobj)
3734 goto exit;
3735
3736 sysfs_attr_init(&perf->test_config.sysfs_metric_id.attr);
3737
3738 if (IS_TIGERLAKE(i915)) {
3739 i915_perf_load_test_config_tgl(i915);
3740 } else if (INTEL_GEN(i915) >= 11) {
3741 i915_perf_load_test_config_icl(i915);
3742 } else if (IS_CANNONLAKE(i915)) {
3743 i915_perf_load_test_config_cnl(i915);
3744 } else if (IS_COFFEELAKE(i915)) {
3745 if (IS_CFL_GT2(i915))
3746 i915_perf_load_test_config_cflgt2(i915);
3747 if (IS_CFL_GT3(i915))
3748 i915_perf_load_test_config_cflgt3(i915);
3749 } else if (IS_GEMINILAKE(i915)) {
3750 i915_perf_load_test_config_glk(i915);
3751 } else if (IS_KABYLAKE(i915)) {
3752 if (IS_KBL_GT2(i915))
3753 i915_perf_load_test_config_kblgt2(i915);
3754 else if (IS_KBL_GT3(i915))
3755 i915_perf_load_test_config_kblgt3(i915);
3756 } else if (IS_BROXTON(i915)) {
3757 i915_perf_load_test_config_bxt(i915);
3758 } else if (IS_SKYLAKE(i915)) {
3759 if (IS_SKL_GT2(i915))
3760 i915_perf_load_test_config_sklgt2(i915);
3761 else if (IS_SKL_GT3(i915))
3762 i915_perf_load_test_config_sklgt3(i915);
3763 else if (IS_SKL_GT4(i915))
3764 i915_perf_load_test_config_sklgt4(i915);
3765 } else if (IS_CHERRYVIEW(i915)) {
3766 i915_perf_load_test_config_chv(i915);
3767 } else if (IS_BROADWELL(i915)) {
3768 i915_perf_load_test_config_bdw(i915);
3769 } else if (IS_HASWELL(i915)) {
3770 i915_perf_load_test_config_hsw(i915);
3771 }
3772
3773 if (perf->test_config.id == 0)
3774 goto sysfs_error;
3775
3776 ret = sysfs_create_group(perf->metrics_kobj,
3777 &perf->test_config.sysfs_metric);
3778 if (ret)
3779 goto sysfs_error;
3780 3714
3781 perf->test_config.perf = perf;
3782 kref_init(&perf->test_config.ref);
3783
3784 goto exit;
3785
3786sysfs_error:
3787 kobject_put(perf->metrics_kobj);
3788 perf->metrics_kobj = NULL;
3789
3790exit:
3791 mutex_unlock(&perf->lock);3715 mutex_unlock(&perf->lock);
3792}3716}
3793 3717
@@ -3807,9 +3731,6 @@ void i915_perf_unregister(struct drm_i915_private *i915) · 13 unmodified lines
3807 if (!perf->metrics_kobj)3731 if (!perf->metrics_kobj)
3808 return;3732 return;
3809 3733
3810 sysfs_remove_group(perf->metrics_kobj,
3811 &perf->test_config.sysfs_metric);
3812
3813 kobject_put(perf->metrics_kobj);3734 kobject_put(perf->metrics_kobj);
3814 perf->metrics_kobj = NULL;3735 perf->metrics_kobj = NULL;
3815}3736}
drivers/gpu/drm/i915/i915_perf_types.h+0−2
@@ -413,8 +413,6 @@ struct i915_perf { · 412 unmodified lines
413 */413 */
414 struct ratelimit_state spurious_report_rs;414 struct ratelimit_state spurious_report_rs;
415 415
416 struct i915_oa_config test_config;
417
418 u32 gen7_latched_oastatus1;416 u32 gen7_latched_oastatus1;
419 u32 ctx_oactxctrl_offset;417 u32 ctx_oactxctrl_offset;
420 u32 ctx_flexeu0_offset;418 u32 ctx_flexeu0_offset;
drivers/gpu/drm/i915/oa/i915_oa_bdw.c+0−90
@@ -1,90 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_bdw.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2744), 0x00800000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2710), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2720), 0x00000000 },
21 { _MMIO(0x2770), 0x00000004 },
22 { _MMIO(0x2774), 0x00000000 },
23 { _MMIO(0x2778), 0x00000003 },
24 { _MMIO(0x277c), 0x00000000 },
25 { _MMIO(0x2780), 0x00000007 },
26 { _MMIO(0x2784), 0x00000000 },
27 { _MMIO(0x2788), 0x00100002 },
28 { _MMIO(0x278c), 0x0000fff7 },
29 { _MMIO(0x2790), 0x00100002 },
30 { _MMIO(0x2794), 0x0000ffcf },
31 { _MMIO(0x2798), 0x00100082 },
32 { _MMIO(0x279c), 0x0000ffef },
33 { _MMIO(0x27a0), 0x001000c2 },
34 { _MMIO(0x27a4), 0x0000ffe7 },
35 { _MMIO(0x27a8), 0x00100001 },
36 { _MMIO(0x27ac), 0x0000ffe7 },
37};
38
39static const struct i915_oa_reg flex_eu_config_test_oa[] = {
40};
41
42static const struct i915_oa_reg mux_config_test_oa[] = {
43 { _MMIO(0x9840), 0x000000a0 },
44 { _MMIO(0x9888), 0x198b0000 },
45 { _MMIO(0x9888), 0x078b0066 },
46 { _MMIO(0x9888), 0x118b0000 },
47 { _MMIO(0x9888), 0x258b0000 },
48 { _MMIO(0x9888), 0x21850008 },
49 { _MMIO(0x9888), 0x0d834000 },
50 { _MMIO(0x9888), 0x07844000 },
51 { _MMIO(0x9888), 0x17804000 },
52 { _MMIO(0x9888), 0x21800000 },
53 { _MMIO(0x9888), 0x4f800000 },
54 { _MMIO(0x9888), 0x41800000 },
55 { _MMIO(0x9888), 0x31800000 },
56 { _MMIO(0x9840), 0x00000080 },
57};
58
59static ssize_t
60show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
61{
62 return sprintf(buf, "1\n");
63}
64
65void
66i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv)
67{
68 strlcpy(dev_priv->perf.test_config.uuid,
69 "d6de6f55-e526-4f79-a6a6-d7315c09044e",
70 sizeof(dev_priv->perf.test_config.uuid));
71 dev_priv->perf.test_config.id = 1;
72
73 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
74 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
75
76 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
77 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
78
79 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
80 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
81
82 dev_priv->perf.test_config.sysfs_metric.name = "d6de6f55-e526-4f79-a6a6-d7315c09044e";
83 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
84
85 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
86
87 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
88 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
89 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
90}
drivers/gpu/drm/i915/oa/i915_oa_bdw.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_BDW_H__
10#define __I915_OA_BDW_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_bxt.c+0−88
@@ -1,88 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_bxt.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2744), 0x00800000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2710), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2720), 0x00000000 },
21 { _MMIO(0x2770), 0x00000004 },
22 { _MMIO(0x2774), 0x00000000 },
23 { _MMIO(0x2778), 0x00000003 },
24 { _MMIO(0x277c), 0x00000000 },
25 { _MMIO(0x2780), 0x00000007 },
26 { _MMIO(0x2784), 0x00000000 },
27 { _MMIO(0x2788), 0x00100002 },
28 { _MMIO(0x278c), 0x0000fff7 },
29 { _MMIO(0x2790), 0x00100002 },
30 { _MMIO(0x2794), 0x0000ffcf },
31 { _MMIO(0x2798), 0x00100082 },
32 { _MMIO(0x279c), 0x0000ffef },
33 { _MMIO(0x27a0), 0x001000c2 },
34 { _MMIO(0x27a4), 0x0000ffe7 },
35 { _MMIO(0x27a8), 0x00100001 },
36 { _MMIO(0x27ac), 0x0000ffe7 },
37};
38
39static const struct i915_oa_reg flex_eu_config_test_oa[] = {
40};
41
42static const struct i915_oa_reg mux_config_test_oa[] = {
43 { _MMIO(0x9840), 0x00000080 },
44 { _MMIO(0x9888), 0x19800000 },
45 { _MMIO(0x9888), 0x07800063 },
46 { _MMIO(0x9888), 0x11800000 },
47 { _MMIO(0x9888), 0x23810008 },
48 { _MMIO(0x9888), 0x1d950400 },
49 { _MMIO(0x9888), 0x0f922000 },
50 { _MMIO(0x9888), 0x1f908000 },
51 { _MMIO(0x9888), 0x37900000 },
52 { _MMIO(0x9888), 0x55900000 },
53 { _MMIO(0x9888), 0x47900000 },
54 { _MMIO(0x9888), 0x33900000 },
55};
56
57static ssize_t
58show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
59{
60 return sprintf(buf, "1\n");
61}
62
63void
64i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv)
65{
66 strlcpy(dev_priv->perf.test_config.uuid,
67 "5ee72f5c-092f-421e-8b70-225f7c3e9612",
68 sizeof(dev_priv->perf.test_config.uuid));
69 dev_priv->perf.test_config.id = 1;
70
71 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
72 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
73
74 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
75 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
76
77 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
78 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
79
80 dev_priv->perf.test_config.sysfs_metric.name = "5ee72f5c-092f-421e-8b70-225f7c3e9612";
81 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
82
83 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
84
85 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
86 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
87 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
88}
drivers/gpu/drm/i915/oa/i915_oa_bxt.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_BXT_H__
10#define __I915_OA_BXT_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c+0−89
@@ -1,89 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_cflgt2.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2744), 0x00800000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2710), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2720), 0x00000000 },
21 { _MMIO(0x2770), 0x00000004 },
22 { _MMIO(0x2774), 0x00000000 },
23 { _MMIO(0x2778), 0x00000003 },
24 { _MMIO(0x277c), 0x00000000 },
25 { _MMIO(0x2780), 0x00000007 },
26 { _MMIO(0x2784), 0x00000000 },
27 { _MMIO(0x2788), 0x00100002 },
28 { _MMIO(0x278c), 0x0000fff7 },
29 { _MMIO(0x2790), 0x00100002 },
30 { _MMIO(0x2794), 0x0000ffcf },
31 { _MMIO(0x2798), 0x00100082 },
32 { _MMIO(0x279c), 0x0000ffef },
33 { _MMIO(0x27a0), 0x001000c2 },
34 { _MMIO(0x27a4), 0x0000ffe7 },
35 { _MMIO(0x27a8), 0x00100001 },
36 { _MMIO(0x27ac), 0x0000ffe7 },
37};
38
39static const struct i915_oa_reg flex_eu_config_test_oa[] = {
40};
41
42static const struct i915_oa_reg mux_config_test_oa[] = {
43 { _MMIO(0x9840), 0x00000080 },
44 { _MMIO(0x9888), 0x11810000 },
45 { _MMIO(0x9888), 0x07810013 },
46 { _MMIO(0x9888), 0x1f810000 },
47 { _MMIO(0x9888), 0x1d810000 },
48 { _MMIO(0x9888), 0x1b930040 },
49 { _MMIO(0x9888), 0x07e54000 },
50 { _MMIO(0x9888), 0x1f908000 },
51 { _MMIO(0x9888), 0x11900000 },
52 { _MMIO(0x9888), 0x37900000 },
53 { _MMIO(0x9888), 0x53900000 },
54 { _MMIO(0x9888), 0x45900000 },
55 { _MMIO(0x9888), 0x33900000 },
56};
57
58static ssize_t
59show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
60{
61 return sprintf(buf, "1\n");
62}
63
64void
65i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv)
66{
67 strlcpy(dev_priv->perf.test_config.uuid,
68 "74fb4902-d3d3-4237-9e90-cbdc68d0a446",
69 sizeof(dev_priv->perf.test_config.uuid));
70 dev_priv->perf.test_config.id = 1;
71
72 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
73 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
74
75 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
76 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
77
78 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
79 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
80
81 dev_priv->perf.test_config.sysfs_metric.name = "74fb4902-d3d3-4237-9e90-cbdc68d0a446";
82 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
83
84 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
85
86 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
87 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
88 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
89}
drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_CFLGT2_H__
10#define __I915_OA_CFLGT2_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c+0−89
@@ -1,89 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_cflgt3.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2744), 0x00800000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2710), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2720), 0x00000000 },
21 { _MMIO(0x2770), 0x00000004 },
22 { _MMIO(0x2774), 0x00000000 },
23 { _MMIO(0x2778), 0x00000003 },
24 { _MMIO(0x277c), 0x00000000 },
25 { _MMIO(0x2780), 0x00000007 },
26 { _MMIO(0x2784), 0x00000000 },
27 { _MMIO(0x2788), 0x00100002 },
28 { _MMIO(0x278c), 0x0000fff7 },
29 { _MMIO(0x2790), 0x00100002 },
30 { _MMIO(0x2794), 0x0000ffcf },
31 { _MMIO(0x2798), 0x00100082 },
32 { _MMIO(0x279c), 0x0000ffef },
33 { _MMIO(0x27a0), 0x001000c2 },
34 { _MMIO(0x27a4), 0x0000ffe7 },
35 { _MMIO(0x27a8), 0x00100001 },
36 { _MMIO(0x27ac), 0x0000ffe7 },
37};
38
39static const struct i915_oa_reg flex_eu_config_test_oa[] = {
40};
41
42static const struct i915_oa_reg mux_config_test_oa[] = {
43 { _MMIO(0x9840), 0x00000080 },
44 { _MMIO(0x9888), 0x11810000 },
45 { _MMIO(0x9888), 0x07810013 },
46 { _MMIO(0x9888), 0x1f810000 },
47 { _MMIO(0x9888), 0x1d810000 },
48 { _MMIO(0x9888), 0x1b930040 },
49 { _MMIO(0x9888), 0x07e54000 },
50 { _MMIO(0x9888), 0x1f908000 },
51 { _MMIO(0x9888), 0x11900000 },
52 { _MMIO(0x9888), 0x37900000 },
53 { _MMIO(0x9888), 0x53900000 },
54 { _MMIO(0x9888), 0x45900000 },
55 { _MMIO(0x9888), 0x33900000 },
56};
57
58static ssize_t
59show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
60{
61 return sprintf(buf, "1\n");
62}
63
64void
65i915_perf_load_test_config_cflgt3(struct drm_i915_private *dev_priv)
66{
67 strlcpy(dev_priv->perf.test_config.uuid,
68 "577e8e2c-3fa0-4875-8743-3538d585e3b0",
69 sizeof(dev_priv->perf.test_config.uuid));
70 dev_priv->perf.test_config.id = 1;
71
72 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
73 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
74
75 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
76 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
77
78 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
79 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
80
81 dev_priv->perf.test_config.sysfs_metric.name = "577e8e2c-3fa0-4875-8743-3538d585e3b0";
82 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
83
84 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
85
86 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
87 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
88 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
89}
drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_CFLGT3_H__
10#define __I915_OA_CFLGT3_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_cflgt3(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_chv.c+0−89
@@ -1,89 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_chv.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2744), 0x00800000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2710), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2720), 0x00000000 },
21 { _MMIO(0x2770), 0x00000004 },
22 { _MMIO(0x2774), 0x00000000 },
23 { _MMIO(0x2778), 0x00000003 },
24 { _MMIO(0x277c), 0x00000000 },
25 { _MMIO(0x2780), 0x00000007 },
26 { _MMIO(0x2784), 0x00000000 },
27 { _MMIO(0x2788), 0x00100002 },
28 { _MMIO(0x278c), 0x0000fff7 },
29 { _MMIO(0x2790), 0x00100002 },
30 { _MMIO(0x2794), 0x0000ffcf },
31 { _MMIO(0x2798), 0x00100082 },
32 { _MMIO(0x279c), 0x0000ffef },
33 { _MMIO(0x27a0), 0x001000c2 },
34 { _MMIO(0x27a4), 0x0000ffe7 },
35 { _MMIO(0x27a8), 0x00100001 },
36 { _MMIO(0x27ac), 0x0000ffe7 },
37};
38
39static const struct i915_oa_reg flex_eu_config_test_oa[] = {
40};
41
42static const struct i915_oa_reg mux_config_test_oa[] = {
43 { _MMIO(0x9840), 0x000000a0 },
44 { _MMIO(0x9888), 0x59800000 },
45 { _MMIO(0x9888), 0x59800001 },
46 { _MMIO(0x9888), 0x338b0000 },
47 { _MMIO(0x9888), 0x258b0066 },
48 { _MMIO(0x9888), 0x058b0000 },
49 { _MMIO(0x9888), 0x038b0000 },
50 { _MMIO(0x9888), 0x03844000 },
51 { _MMIO(0x9888), 0x47800080 },
52 { _MMIO(0x9888), 0x57800000 },
53 { _MMIO(0x1823a4), 0x00000000 },
54 { _MMIO(0x9888), 0x59800000 },
55 { _MMIO(0x9840), 0x00000080 },
56};
57
58static ssize_t
59show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
60{
61 return sprintf(buf, "1\n");
62}
63
64void
65i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv)
66{
67 strlcpy(dev_priv->perf.test_config.uuid,
68 "4a534b07-cba3-414d-8d60-874830e883aa",
69 sizeof(dev_priv->perf.test_config.uuid));
70 dev_priv->perf.test_config.id = 1;
71
72 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
73 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
74
75 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
76 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
77
78 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
79 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
80
81 dev_priv->perf.test_config.sysfs_metric.name = "4a534b07-cba3-414d-8d60-874830e883aa";
82 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
83
84 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
85
86 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
87 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
88 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
89}
drivers/gpu/drm/i915/oa/i915_oa_chv.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_CHV_H__
10#define __I915_OA_CHV_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_cnl.c+0−101
@@ -1,101 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_cnl.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2710), 0x00000000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2720), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2770), 0x00000004 },
21 { _MMIO(0x2774), 0x0000ffff },
22 { _MMIO(0x2778), 0x00000003 },
23 { _MMIO(0x277c), 0x0000ffff },
24 { _MMIO(0x2780), 0x00000007 },
25 { _MMIO(0x2784), 0x0000ffff },
26 { _MMIO(0x2788), 0x00100002 },
27 { _MMIO(0x278c), 0x0000fff7 },
28 { _MMIO(0x2790), 0x00100002 },
29 { _MMIO(0x2794), 0x0000ffcf },
30 { _MMIO(0x2798), 0x00100082 },
31 { _MMIO(0x279c), 0x0000ffef },
32 { _MMIO(0x27a0), 0x001000c2 },
33 { _MMIO(0x27a4), 0x0000ffe7 },
34 { _MMIO(0x27a8), 0x00100001 },
35 { _MMIO(0x27ac), 0x0000ffe7 },
36};
37
38static const struct i915_oa_reg flex_eu_config_test_oa[] = {
39};
40
41static const struct i915_oa_reg mux_config_test_oa[] = {
42 { _MMIO(0xd04), 0x00000200 },
43 { _MMIO(0x9884), 0x00000007 },
44 { _MMIO(0x9888), 0x17060000 },
45 { _MMIO(0x9840), 0x00000000 },
46 { _MMIO(0x9884), 0x00000007 },
47 { _MMIO(0x9888), 0x13034000 },
48 { _MMIO(0x9884), 0x00000007 },
49 { _MMIO(0x9888), 0x07060066 },
50 { _MMIO(0x9884), 0x00000007 },
51 { _MMIO(0x9888), 0x05060000 },
52 { _MMIO(0x9884), 0x00000007 },
53 { _MMIO(0x9888), 0x0f080040 },
54 { _MMIO(0x9884), 0x00000007 },
55 { _MMIO(0x9888), 0x07091000 },
56 { _MMIO(0x9884), 0x00000007 },
57 { _MMIO(0x9888), 0x0f041000 },
58 { _MMIO(0x9884), 0x00000007 },
59 { _MMIO(0x9888), 0x1d004000 },
60 { _MMIO(0x9884), 0x00000007 },
61 { _MMIO(0x9888), 0x35000000 },
62 { _MMIO(0x9884), 0x00000007 },
63 { _MMIO(0x9888), 0x49000000 },
64 { _MMIO(0x9884), 0x00000007 },
65 { _MMIO(0x9888), 0x3d000000 },
66 { _MMIO(0x9884), 0x00000007 },
67 { _MMIO(0x9888), 0x31000000 },
68};
69
70static ssize_t
71show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
72{
73 return sprintf(buf, "1\n");
74}
75
76void
77i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv)
78{
79 strlcpy(dev_priv->perf.test_config.uuid,
80 "db41edd4-d8e7-4730-ad11-b9a2d6833503",
81 sizeof(dev_priv->perf.test_config.uuid));
82 dev_priv->perf.test_config.id = 1;
83
84 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
85 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
86
87 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
88 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
89
90 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
91 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
92
93 dev_priv->perf.test_config.sysfs_metric.name = "db41edd4-d8e7-4730-ad11-b9a2d6833503";
94 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
95
96 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
97
98 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
99 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
100 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
101}
drivers/gpu/drm/i915/oa/i915_oa_cnl.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_CNL_H__
10#define __I915_OA_CNL_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_glk.c+0−88
@@ -1,88 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_glk.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2744), 0x00800000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2710), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2720), 0x00000000 },
21 { _MMIO(0x2770), 0x00000004 },
22 { _MMIO(0x2774), 0x00000000 },
23 { _MMIO(0x2778), 0x00000003 },
24 { _MMIO(0x277c), 0x00000000 },
25 { _MMIO(0x2780), 0x00000007 },
26 { _MMIO(0x2784), 0x00000000 },
27 { _MMIO(0x2788), 0x00100002 },
28 { _MMIO(0x278c), 0x0000fff7 },
29 { _MMIO(0x2790), 0x00100002 },
30 { _MMIO(0x2794), 0x0000ffcf },
31 { _MMIO(0x2798), 0x00100082 },
32 { _MMIO(0x279c), 0x0000ffef },
33 { _MMIO(0x27a0), 0x001000c2 },
34 { _MMIO(0x27a4), 0x0000ffe7 },
35 { _MMIO(0x27a8), 0x00100001 },
36 { _MMIO(0x27ac), 0x0000ffe7 },
37};
38
39static const struct i915_oa_reg flex_eu_config_test_oa[] = {
40};
41
42static const struct i915_oa_reg mux_config_test_oa[] = {
43 { _MMIO(0x9840), 0x00000080 },
44 { _MMIO(0x9888), 0x19800000 },
45 { _MMIO(0x9888), 0x07800063 },
46 { _MMIO(0x9888), 0x11800000 },
47 { _MMIO(0x9888), 0x23810008 },
48 { _MMIO(0x9888), 0x1d950400 },
49 { _MMIO(0x9888), 0x0f922000 },
50 { _MMIO(0x9888), 0x1f908000 },
51 { _MMIO(0x9888), 0x37900000 },
52 { _MMIO(0x9888), 0x55900000 },
53 { _MMIO(0x9888), 0x47900000 },
54 { _MMIO(0x9888), 0x33900000 },
55};
56
57static ssize_t
58show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
59{
60 return sprintf(buf, "1\n");
61}
62
63void
64i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv)
65{
66 strlcpy(dev_priv->perf.test_config.uuid,
67 "dd3fd789-e783-4204-8cd0-b671bbccb0cf",
68 sizeof(dev_priv->perf.test_config.uuid));
69 dev_priv->perf.test_config.id = 1;
70
71 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
72 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
73
74 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
75 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
76
77 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
78 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
79
80 dev_priv->perf.test_config.sysfs_metric.name = "dd3fd789-e783-4204-8cd0-b671bbccb0cf";
81 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
82
83 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
84
85 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
86 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
87 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
88}
drivers/gpu/drm/i915/oa/i915_oa_glk.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_GLK_H__
10#define __I915_OA_GLK_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_hsw.c+0−118
@@ -1,118 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_hsw.h"
13
14static const struct i915_oa_reg b_counter_config_render_basic[] = {
15 { _MMIO(0x2724), 0x00800000 },
16 { _MMIO(0x2720), 0x00000000 },
17 { _MMIO(0x2714), 0x00800000 },
18 { _MMIO(0x2710), 0x00000000 },
19};
20
21static const struct i915_oa_reg flex_eu_config_render_basic[] = {
22};
23
24static const struct i915_oa_reg mux_config_render_basic[] = {
25 { _MMIO(0x9840), 0x00000080 },
26 { _MMIO(0x253a4), 0x01600000 },
27 { _MMIO(0x25440), 0x00100000 },
28 { _MMIO(0x25128), 0x00000000 },
29 { _MMIO(0x2691c), 0x00000800 },
30 { _MMIO(0x26aa0), 0x01500000 },
31 { _MMIO(0x26b9c), 0x00006000 },
32 { _MMIO(0x2791c), 0x00000800 },
33 { _MMIO(0x27aa0), 0x01500000 },
34 { _MMIO(0x27b9c), 0x00006000 },
35 { _MMIO(0x2641c), 0x00000400 },
36 { _MMIO(0x25380), 0x00000010 },
37 { _MMIO(0x2538c), 0x00000000 },
38 { _MMIO(0x25384), 0x0800aaaa },
39 { _MMIO(0x25400), 0x00000004 },
40 { _MMIO(0x2540c), 0x06029000 },
41 { _MMIO(0x25410), 0x00000002 },
42 { _MMIO(0x25404), 0x5c30ffff },
43 { _MMIO(0x25100), 0x00000016 },
44 { _MMIO(0x25110), 0x00000400 },
45 { _MMIO(0x25104), 0x00000000 },
46 { _MMIO(0x26804), 0x00001211 },
47 { _MMIO(0x26884), 0x00000100 },
48 { _MMIO(0x26900), 0x00000002 },
49 { _MMIO(0x26908), 0x00700000 },
50 { _MMIO(0x26904), 0x00000000 },
51 { _MMIO(0x26984), 0x00001022 },
52 { _MMIO(0x26a04), 0x00000011 },
53 { _MMIO(0x26a80), 0x00000006 },
54 { _MMIO(0x26a88), 0x00000c02 },
55 { _MMIO(0x26a84), 0x00000000 },
56 { _MMIO(0x26b04), 0x00001000 },
57 { _MMIO(0x26b80), 0x00000002 },
58 { _MMIO(0x26b8c), 0x00000007 },
59 { _MMIO(0x26b84), 0x00000000 },
60 { _MMIO(0x27804), 0x00004844 },
61 { _MMIO(0x27884), 0x00000400 },
62 { _MMIO(0x27900), 0x00000002 },
63 { _MMIO(0x27908), 0x0e000000 },
64 { _MMIO(0x27904), 0x00000000 },
65 { _MMIO(0x27984), 0x00004088 },
66 { _MMIO(0x27a04), 0x00000044 },
67 { _MMIO(0x27a80), 0x00000006 },
68 { _MMIO(0x27a88), 0x00018040 },
69 { _MMIO(0x27a84), 0x00000000 },
70 { _MMIO(0x27b04), 0x00004000 },
71 { _MMIO(0x27b80), 0x00000002 },
72 { _MMIO(0x27b8c), 0x000000e0 },
73 { _MMIO(0x27b84), 0x00000000 },
74 { _MMIO(0x26104), 0x00002222 },
75 { _MMIO(0x26184), 0x0c006666 },
76 { _MMIO(0x26284), 0x04000000 },
77 { _MMIO(0x26304), 0x04000000 },
78 { _MMIO(0x26400), 0x00000002 },
79 { _MMIO(0x26410), 0x000000a0 },
80 { _MMIO(0x26404), 0x00000000 },
81 { _MMIO(0x25420), 0x04108020 },
82 { _MMIO(0x25424), 0x1284a420 },
83 { _MMIO(0x2541c), 0x00000000 },
84 { _MMIO(0x25428), 0x00042049 },
85};
86
87static ssize_t
88show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
89{
90 return sprintf(buf, "1\n");
91}
92
93void
94i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv)
95{
96 strlcpy(dev_priv->perf.test_config.uuid,
97 "403d8832-1a27-4aa6-a64e-f5389ce7b212",
98 sizeof(dev_priv->perf.test_config.uuid));
99 dev_priv->perf.test_config.id = 1;
100
101 dev_priv->perf.test_config.mux_regs = mux_config_render_basic;
102 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_render_basic);
103
104 dev_priv->perf.test_config.b_counter_regs = b_counter_config_render_basic;
105 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_render_basic);
106
107 dev_priv->perf.test_config.flex_regs = flex_eu_config_render_basic;
108 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_render_basic);
109
110 dev_priv->perf.test_config.sysfs_metric.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212";
111 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
112
113 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
114
115 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
116 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
117 dev_priv->perf.test_config.sysfs_metric_id.show = show_render_basic_id;
118}
drivers/gpu/drm/i915/oa/i915_oa_hsw.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_HSW_H__
10#define __I915_OA_HSW_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_icl.c+0−98
@@ -1,98 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_icl.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2710), 0x00000000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2720), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2770), 0x00000004 },
21 { _MMIO(0x2774), 0x0000ffff },
22 { _MMIO(0x2778), 0x00000003 },
23 { _MMIO(0x277c), 0x0000ffff },
24 { _MMIO(0x2780), 0x00000007 },
25 { _MMIO(0x2784), 0x0000ffff },
26 { _MMIO(0x2788), 0x00100002 },
27 { _MMIO(0x278c), 0x0000fff7 },
28 { _MMIO(0x2790), 0x00100002 },
29 { _MMIO(0x2794), 0x0000ffcf },
30 { _MMIO(0x2798), 0x00100082 },
31 { _MMIO(0x279c), 0x0000ffef },
32 { _MMIO(0x27a0), 0x001000c2 },
33 { _MMIO(0x27a4), 0x0000ffe7 },
34 { _MMIO(0x27a8), 0x00100001 },
35 { _MMIO(0x27ac), 0x0000ffe7 },
36};
37
38static const struct i915_oa_reg flex_eu_config_test_oa[] = {
39};
40
41static const struct i915_oa_reg mux_config_test_oa[] = {
42 { _MMIO(0xd04), 0x00000200 },
43 { _MMIO(0x9840), 0x00000000 },
44 { _MMIO(0x9884), 0x00000000 },
45 { _MMIO(0x9888), 0x10060000 },
46 { _MMIO(0x9888), 0x22060000 },
47 { _MMIO(0x9888), 0x16060000 },
48 { _MMIO(0x9888), 0x24060000 },
49 { _MMIO(0x9888), 0x18060000 },
50 { _MMIO(0x9888), 0x1a060000 },
51 { _MMIO(0x9888), 0x12060000 },
52 { _MMIO(0x9888), 0x14060000 },
53 { _MMIO(0x9888), 0x10060000 },
54 { _MMIO(0x9888), 0x22060000 },
55 { _MMIO(0x9884), 0x00000003 },
56 { _MMIO(0x9888), 0x16130000 },
57 { _MMIO(0x9888), 0x24000001 },
58 { _MMIO(0x9888), 0x0e130056 },
59 { _MMIO(0x9888), 0x10130000 },
60 { _MMIO(0x9888), 0x1a130000 },
61 { _MMIO(0x9888), 0x541f0001 },
62 { _MMIO(0x9888), 0x181f0000 },
63 { _MMIO(0x9888), 0x4c1f0000 },
64 { _MMIO(0x9888), 0x301f0000 },
65};
66
67static ssize_t
68show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
69{
70 return sprintf(buf, "1\n");
71}
72
73void
74i915_perf_load_test_config_icl(struct drm_i915_private *dev_priv)
75{
76 strlcpy(dev_priv->perf.test_config.uuid,
77 "a291665e-244b-4b76-9b9a-01de9d3c8068",
78 sizeof(dev_priv->perf.test_config.uuid));
79 dev_priv->perf.test_config.id = 1;
80
81 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
82 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
83
84 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
85 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
86
87 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
88 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
89
90 dev_priv->perf.test_config.sysfs_metric.name = "a291665e-244b-4b76-9b9a-01de9d3c8068";
91 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
92
93 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
94
95 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
96 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
97 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
98}
drivers/gpu/drm/i915/oa/i915_oa_icl.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_ICL_H__
10#define __I915_OA_ICL_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_icl(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c+0−89
@@ -1,89 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_kblgt2.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2744), 0x00800000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2710), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2720), 0x00000000 },
21 { _MMIO(0x2770), 0x00000004 },
22 { _MMIO(0x2774), 0x00000000 },
23 { _MMIO(0x2778), 0x00000003 },
24 { _MMIO(0x277c), 0x00000000 },
25 { _MMIO(0x2780), 0x00000007 },
26 { _MMIO(0x2784), 0x00000000 },
27 { _MMIO(0x2788), 0x00100002 },
28 { _MMIO(0x278c), 0x0000fff7 },
29 { _MMIO(0x2790), 0x00100002 },
30 { _MMIO(0x2794), 0x0000ffcf },
31 { _MMIO(0x2798), 0x00100082 },
32 { _MMIO(0x279c), 0x0000ffef },
33 { _MMIO(0x27a0), 0x001000c2 },
34 { _MMIO(0x27a4), 0x0000ffe7 },
35 { _MMIO(0x27a8), 0x00100001 },
36 { _MMIO(0x27ac), 0x0000ffe7 },
37};
38
39static const struct i915_oa_reg flex_eu_config_test_oa[] = {
40};
41
42static const struct i915_oa_reg mux_config_test_oa[] = {
43 { _MMIO(0x9840), 0x00000080 },
44 { _MMIO(0x9888), 0x11810000 },
45 { _MMIO(0x9888), 0x07810013 },
46 { _MMIO(0x9888), 0x1f810000 },
47 { _MMIO(0x9888), 0x1d810000 },
48 { _MMIO(0x9888), 0x1b930040 },
49 { _MMIO(0x9888), 0x07e54000 },
50 { _MMIO(0x9888), 0x1f908000 },
51 { _MMIO(0x9888), 0x11900000 },
52 { _MMIO(0x9888), 0x37900000 },
53 { _MMIO(0x9888), 0x53900000 },
54 { _MMIO(0x9888), 0x45900000 },
55 { _MMIO(0x9888), 0x33900000 },
56};
57
58static ssize_t
59show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
60{
61 return sprintf(buf, "1\n");
62}
63
64void
65i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv)
66{
67 strlcpy(dev_priv->perf.test_config.uuid,
68 "baa3c7e4-52b6-4b85-801e-465a94b746dd",
69 sizeof(dev_priv->perf.test_config.uuid));
70 dev_priv->perf.test_config.id = 1;
71
72 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
73 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
74
75 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
76 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
77
78 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
79 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
80
81 dev_priv->perf.test_config.sysfs_metric.name = "baa3c7e4-52b6-4b85-801e-465a94b746dd";
82 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
83
84 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
85
86 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
87 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
88 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
89}
drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_KBLGT2_H__
10#define __I915_OA_KBLGT2_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c+0−89
@@ -1,89 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_kblgt3.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2744), 0x00800000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2710), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2720), 0x00000000 },
21 { _MMIO(0x2770), 0x00000004 },
22 { _MMIO(0x2774), 0x00000000 },
23 { _MMIO(0x2778), 0x00000003 },
24 { _MMIO(0x277c), 0x00000000 },
25 { _MMIO(0x2780), 0x00000007 },
26 { _MMIO(0x2784), 0x00000000 },
27 { _MMIO(0x2788), 0x00100002 },
28 { _MMIO(0x278c), 0x0000fff7 },
29 { _MMIO(0x2790), 0x00100002 },
30 { _MMIO(0x2794), 0x0000ffcf },
31 { _MMIO(0x2798), 0x00100082 },
32 { _MMIO(0x279c), 0x0000ffef },
33 { _MMIO(0x27a0), 0x001000c2 },
34 { _MMIO(0x27a4), 0x0000ffe7 },
35 { _MMIO(0x27a8), 0x00100001 },
36 { _MMIO(0x27ac), 0x0000ffe7 },
37};
38
39static const struct i915_oa_reg flex_eu_config_test_oa[] = {
40};
41
42static const struct i915_oa_reg mux_config_test_oa[] = {
43 { _MMIO(0x9840), 0x00000080 },
44 { _MMIO(0x9888), 0x11810000 },
45 { _MMIO(0x9888), 0x07810013 },
46 { _MMIO(0x9888), 0x1f810000 },
47 { _MMIO(0x9888), 0x1d810000 },
48 { _MMIO(0x9888), 0x1b930040 },
49 { _MMIO(0x9888), 0x07e54000 },
50 { _MMIO(0x9888), 0x1f908000 },
51 { _MMIO(0x9888), 0x11900000 },
52 { _MMIO(0x9888), 0x37900000 },
53 { _MMIO(0x9888), 0x53900000 },
54 { _MMIO(0x9888), 0x45900000 },
55 { _MMIO(0x9888), 0x33900000 },
56};
57
58static ssize_t
59show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
60{
61 return sprintf(buf, "1\n");
62}
63
64void
65i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv)
66{
67 strlcpy(dev_priv->perf.test_config.uuid,
68 "f1792f32-6db2-4b50-b4b2-557128f1688d",
69 sizeof(dev_priv->perf.test_config.uuid));
70 dev_priv->perf.test_config.id = 1;
71
72 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
73 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
74
75 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
76 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
77
78 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
79 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
80
81 dev_priv->perf.test_config.sysfs_metric.name = "f1792f32-6db2-4b50-b4b2-557128f1688d";
82 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
83
84 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
85
86 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
87 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
88 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
89}
drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_KBLGT3_H__
10#define __I915_OA_KBLGT3_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c+0−88
@@ -1,88 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_sklgt2.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2714), 0xf0800000 },
17 { _MMIO(0x2710), 0x00000000 },
18 { _MMIO(0x2724), 0xf0800000 },
19 { _MMIO(0x2720), 0x00000000 },
20 { _MMIO(0x2770), 0x00000004 },
21 { _MMIO(0x2774), 0x00000000 },
22 { _MMIO(0x2778), 0x00000003 },
23 { _MMIO(0x277c), 0x00000000 },
24 { _MMIO(0x2780), 0x00000007 },
25 { _MMIO(0x2784), 0x00000000 },
26 { _MMIO(0x2788), 0x00100002 },
27 { _MMIO(0x278c), 0x0000fff7 },
28 { _MMIO(0x2790), 0x00100002 },
29 { _MMIO(0x2794), 0x0000ffcf },
30 { _MMIO(0x2798), 0x00100082 },
31 { _MMIO(0x279c), 0x0000ffef },
32 { _MMIO(0x27a0), 0x001000c2 },
33 { _MMIO(0x27a4), 0x0000ffe7 },
34 { _MMIO(0x27a8), 0x00100001 },
35 { _MMIO(0x27ac), 0x0000ffe7 },
36};
37
38static const struct i915_oa_reg flex_eu_config_test_oa[] = {
39};
40
41static const struct i915_oa_reg mux_config_test_oa[] = {
42 { _MMIO(0x9840), 0x00000080 },
43 { _MMIO(0x9888), 0x11810000 },
44 { _MMIO(0x9888), 0x07810016 },
45 { _MMIO(0x9888), 0x1f810000 },
46 { _MMIO(0x9888), 0x1d810000 },
47 { _MMIO(0x9888), 0x1b930040 },
48 { _MMIO(0x9888), 0x07e54000 },
49 { _MMIO(0x9888), 0x1f908000 },
50 { _MMIO(0x9888), 0x11900000 },
51 { _MMIO(0x9888), 0x37900000 },
52 { _MMIO(0x9888), 0x53900000 },
53 { _MMIO(0x9888), 0x45900000 },
54 { _MMIO(0x9888), 0x33900000 },
55};
56
57static ssize_t
58show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
59{
60 return sprintf(buf, "1\n");
61}
62
63void
64i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv)
65{
66 strlcpy(dev_priv->perf.test_config.uuid,
67 "1651949f-0ac0-4cb1-a06f-dafd74a407d1",
68 sizeof(dev_priv->perf.test_config.uuid));
69 dev_priv->perf.test_config.id = 1;
70
71 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
72 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
73
74 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
75 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
76
77 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
78 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
79
80 dev_priv->perf.test_config.sysfs_metric.name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1";
81 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
82
83 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
84
85 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
86 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
87 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
88}
drivers/gpu/drm/i915/oa/i915_oa_sklgt2.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_SKLGT2_H__
10#define __I915_OA_SKLGT2_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c+0−89
@@ -1,89 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_sklgt3.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2744), 0x00800000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2710), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2720), 0x00000000 },
21 { _MMIO(0x2770), 0x00000004 },
22 { _MMIO(0x2774), 0x00000000 },
23 { _MMIO(0x2778), 0x00000003 },
24 { _MMIO(0x277c), 0x00000000 },
25 { _MMIO(0x2780), 0x00000007 },
26 { _MMIO(0x2784), 0x00000000 },
27 { _MMIO(0x2788), 0x00100002 },
28 { _MMIO(0x278c), 0x0000fff7 },
29 { _MMIO(0x2790), 0x00100002 },
30 { _MMIO(0x2794), 0x0000ffcf },
31 { _MMIO(0x2798), 0x00100082 },
32 { _MMIO(0x279c), 0x0000ffef },
33 { _MMIO(0x27a0), 0x001000c2 },
34 { _MMIO(0x27a4), 0x0000ffe7 },
35 { _MMIO(0x27a8), 0x00100001 },
36 { _MMIO(0x27ac), 0x0000ffe7 },
37};
38
39static const struct i915_oa_reg flex_eu_config_test_oa[] = {
40};
41
42static const struct i915_oa_reg mux_config_test_oa[] = {
43 { _MMIO(0x9840), 0x00000080 },
44 { _MMIO(0x9888), 0x11810000 },
45 { _MMIO(0x9888), 0x07810013 },
46 { _MMIO(0x9888), 0x1f810000 },
47 { _MMIO(0x9888), 0x1d810000 },
48 { _MMIO(0x9888), 0x1b930040 },
49 { _MMIO(0x9888), 0x07e54000 },
50 { _MMIO(0x9888), 0x1f908000 },
51 { _MMIO(0x9888), 0x11900000 },
52 { _MMIO(0x9888), 0x37900000 },
53 { _MMIO(0x9888), 0x53900000 },
54 { _MMIO(0x9888), 0x45900000 },
55 { _MMIO(0x9888), 0x33900000 },
56};
57
58static ssize_t
59show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
60{
61 return sprintf(buf, "1\n");
62}
63
64void
65i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv)
66{
67 strlcpy(dev_priv->perf.test_config.uuid,
68 "2b985803-d3c9-4629-8a4f-634bfecba0e8",
69 sizeof(dev_priv->perf.test_config.uuid));
70 dev_priv->perf.test_config.id = 1;
71
72 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
73 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
74
75 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
76 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
77
78 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
79 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
80
81 dev_priv->perf.test_config.sysfs_metric.name = "2b985803-d3c9-4629-8a4f-634bfecba0e8";
82 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
83
84 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
85
86 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
87 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
88 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
89}
drivers/gpu/drm/i915/oa/i915_oa_sklgt3.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_SKLGT3_H__
10#define __I915_OA_SKLGT3_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c+0−89
@@ -1,89 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_sklgt4.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0x2740), 0x00000000 },
16 { _MMIO(0x2744), 0x00800000 },
17 { _MMIO(0x2714), 0xf0800000 },
18 { _MMIO(0x2710), 0x00000000 },
19 { _MMIO(0x2724), 0xf0800000 },
20 { _MMIO(0x2720), 0x00000000 },
21 { _MMIO(0x2770), 0x00000004 },
22 { _MMIO(0x2774), 0x00000000 },
23 { _MMIO(0x2778), 0x00000003 },
24 { _MMIO(0x277c), 0x00000000 },
25 { _MMIO(0x2780), 0x00000007 },
26 { _MMIO(0x2784), 0x00000000 },
27 { _MMIO(0x2788), 0x00100002 },
28 { _MMIO(0x278c), 0x0000fff7 },
29 { _MMIO(0x2790), 0x00100002 },
30 { _MMIO(0x2794), 0x0000ffcf },
31 { _MMIO(0x2798), 0x00100082 },
32 { _MMIO(0x279c), 0x0000ffef },
33 { _MMIO(0x27a0), 0x001000c2 },
34 { _MMIO(0x27a4), 0x0000ffe7 },
35 { _MMIO(0x27a8), 0x00100001 },
36 { _MMIO(0x27ac), 0x0000ffe7 },
37};
38
39static const struct i915_oa_reg flex_eu_config_test_oa[] = {
40};
41
42static const struct i915_oa_reg mux_config_test_oa[] = {
43 { _MMIO(0x9840), 0x00000080 },
44 { _MMIO(0x9888), 0x11810000 },
45 { _MMIO(0x9888), 0x07810013 },
46 { _MMIO(0x9888), 0x1f810000 },
47 { _MMIO(0x9888), 0x1d810000 },
48 { _MMIO(0x9888), 0x1b930040 },
49 { _MMIO(0x9888), 0x07e54000 },
50 { _MMIO(0x9888), 0x1f908000 },
51 { _MMIO(0x9888), 0x11900000 },
52 { _MMIO(0x9888), 0x37900000 },
53 { _MMIO(0x9888), 0x53900000 },
54 { _MMIO(0x9888), 0x45900000 },
55 { _MMIO(0x9888), 0x33900000 },
56};
57
58static ssize_t
59show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
60{
61 return sprintf(buf, "1\n");
62}
63
64void
65i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv)
66{
67 strlcpy(dev_priv->perf.test_config.uuid,
68 "882fa433-1f4a-4a67-a962-c741888fe5f5",
69 sizeof(dev_priv->perf.test_config.uuid));
70 dev_priv->perf.test_config.id = 1;
71
72 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
73 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
74
75 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
76 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
77
78 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
79 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
80
81 dev_priv->perf.test_config.sysfs_metric.name = "882fa433-1f4a-4a67-a962-c741888fe5f5";
82 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
83
84 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
85
86 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
87 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
88 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
89}
drivers/gpu/drm/i915/oa/i915_oa_sklgt4.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018-2019 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_SKLGT4_H__
10#define __I915_OA_SKLGT4_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/oa/i915_oa_tgl.c+0−121
@@ -1,121 +0,0 @@
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#include <linux/sysfs.h>
10
11#include "i915_drv.h"
12#include "i915_oa_tgl.h"
13
14static const struct i915_oa_reg b_counter_config_test_oa[] = {
15 { _MMIO(0xD920), 0x00000000 },
16 { _MMIO(0xD900), 0x00000000 },
17 { _MMIO(0xD904), 0xF0800000 },
18 { _MMIO(0xD910), 0x00000000 },
19 { _MMIO(0xD914), 0xF0800000 },
20 { _MMIO(0xDC40), 0x00FF0000 },
21 { _MMIO(0xD940), 0x00000004 },
22 { _MMIO(0xD944), 0x0000FFFF },
23 { _MMIO(0xDC00), 0x00000004 },
24 { _MMIO(0xDC04), 0x0000FFFF },
25 { _MMIO(0xD948), 0x00000003 },
26 { _MMIO(0xD94C), 0x0000FFFF },
27 { _MMIO(0xDC08), 0x00000003 },
28 { _MMIO(0xDC0C), 0x0000FFFF },
29 { _MMIO(0xD950), 0x00000007 },
30 { _MMIO(0xD954), 0x0000FFFF },
31 { _MMIO(0xDC10), 0x00000007 },
32 { _MMIO(0xDC14), 0x0000FFFF },
33 { _MMIO(0xD958), 0x00100002 },
34 { _MMIO(0xD95C), 0x0000FFF7 },
35 { _MMIO(0xDC18), 0x00100002 },
36 { _MMIO(0xDC1C), 0x0000FFF7 },
37 { _MMIO(0xD960), 0x00100002 },
38 { _MMIO(0xD964), 0x0000FFCF },
39 { _MMIO(0xDC20), 0x00100002 },
40 { _MMIO(0xDC24), 0x0000FFCF },
41 { _MMIO(0xD968), 0x00100082 },
42 { _MMIO(0xD96C), 0x0000FFEF },
43 { _MMIO(0xDC28), 0x00100082 },
44 { _MMIO(0xDC2C), 0x0000FFEF },
45 { _MMIO(0xD970), 0x001000C2 },
46 { _MMIO(0xD974), 0x0000FFE7 },
47 { _MMIO(0xDC30), 0x001000C2 },
48 { _MMIO(0xDC34), 0x0000FFE7 },
49 { _MMIO(0xD978), 0x00100001 },
50 { _MMIO(0xD97C), 0x0000FFE7 },
51 { _MMIO(0xDC38), 0x00100001 },
52 { _MMIO(0xDC3C), 0x0000FFE7 },
53};
54
55static const struct i915_oa_reg flex_eu_config_test_oa[] = {
56};
57
58static const struct i915_oa_reg mux_config_test_oa[] = {
59 { _MMIO(0x0D04), 0x00000200 },
60 { _MMIO(0x9840), 0x00000000 },
61 { _MMIO(0x9884), 0x00000000 },
62 { _MMIO(0x9888), 0x280E0000 },
63 { _MMIO(0x9888), 0x1E0E0147 },
64 { _MMIO(0x9888), 0x180E0000 },
65 { _MMIO(0x9888), 0x160E0000 },
66 { _MMIO(0x9888), 0x1E0F1000 },
67 { _MMIO(0x9888), 0x1E104000 },
68 { _MMIO(0x9888), 0x2E020100 },
69 { _MMIO(0x9888), 0x2C030004 },
70 { _MMIO(0x9888), 0x38003000 },
71 { _MMIO(0x9888), 0x1E0A8000 },
72 { _MMIO(0x9884), 0x00000003 },
73 { _MMIO(0x9888), 0x49110000 },
74 { _MMIO(0x9888), 0x5D101400 },
75 { _MMIO(0x9888), 0x1D140020 },
76 { _MMIO(0x9888), 0x1D1103A3 },
77 { _MMIO(0x9888), 0x01110000 },
78 { _MMIO(0x9888), 0x61111000 },
79 { _MMIO(0x9888), 0x1F128000 },
80 { _MMIO(0x9888), 0x17100000 },
81 { _MMIO(0x9888), 0x55100630 },
82 { _MMIO(0x9888), 0x57100000 },
83 { _MMIO(0x9888), 0x31100000 },
84 { _MMIO(0x9884), 0x00000003 },
85 { _MMIO(0x9888), 0x65100002 },
86 { _MMIO(0x9884), 0x00000000 },
87 { _MMIO(0x9888), 0x42000001 },
88};
89
90static ssize_t
91show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
92{
93 return sprintf(buf, "1\n");
94}
95
96void
97i915_perf_load_test_config_tgl(struct drm_i915_private *dev_priv)
98{
99 strlcpy(dev_priv->perf.test_config.uuid,
100 "80a833f0-2504-4321-8894-e9277844ce7b",
101 sizeof(dev_priv->perf.test_config.uuid));
102 dev_priv->perf.test_config.id = 1;
103
104 dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
105 dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
106
107 dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
108 dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
109
110 dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
111 dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
112
113 dev_priv->perf.test_config.sysfs_metric.name = "80a833f0-2504-4321-8894-e9277844ce7b";
114 dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
115
116 dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
117
118 dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
119 dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
120 dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
121}
drivers/gpu/drm/i915/oa/i915_oa_tgl.h+0−16
@@ -1,16 +0,0 @@
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Autogenerated file by GPU Top : https://github.com/rib/gputop
6 * DO NOT EDIT manually!
7 */
8
9#ifndef __I915_OA_TGL_H__
10#define __I915_OA_TGL_H__
11
12struct drm_i915_private;
13
14void i915_perf_load_test_config_tgl(struct drm_i915_private *dev_priv);
15
16#endif
drivers/gpu/drm/i915/selftests/i915_perf.c+95−3
@@ -14,10 +14,85 @@ · 13 unmodified lines
14#include "igt_flush_test.h"14#include "igt_flush_test.h"
15#include "lib_sw_fence.h"15#include "lib_sw_fence.h"
16 16
17#define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
18
19static int
20alloc_empty_config(struct i915_perf *perf)
21{
22 struct i915_oa_config *oa_config;
23
24 oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL);
25 if (!oa_config)
26 return -ENOMEM;
27
28 oa_config->perf = perf;
29 kref_init(&oa_config->ref);
30
31 strlcpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid));
32
33 mutex_lock(&perf->metrics_lock);
34
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL);
36 if (oa_config->id < 0) {
37 mutex_unlock(&perf->metrics_lock);
38 i915_oa_config_put(oa_config);
39 return -ENOMEM;
40 }
41
42 mutex_unlock(&perf->metrics_lock);
43
44 return 0;
45}
46
47static void
48destroy_empty_config(struct i915_perf *perf)
49{
50 struct i915_oa_config *oa_config = NULL, *tmp;
51 int id;
52
53 mutex_lock(&perf->metrics_lock);
54
55 idr_for_each_entry(&perf->metrics_idr, tmp, id) {
56 if (!strcmp(tmp->uuid, TEST_OA_CONFIG_UUID)) {
57 oa_config = tmp;
58 break;
59 }
60 }
61
62 if (oa_config)
63 idr_remove(&perf->metrics_idr, oa_config->id);
64
65 mutex_unlock(&perf->metrics_lock);
66
67 if (oa_config)
68 i915_oa_config_put(oa_config);
69}
70
71static struct i915_oa_config *
72get_empty_config(struct i915_perf *perf)
73{
74 struct i915_oa_config *oa_config = NULL, *tmp;
75 int id;
76
77 mutex_lock(&perf->metrics_lock);
78
79 idr_for_each_entry(&perf->metrics_idr, tmp, id) {
80 if (!strcmp(tmp->uuid, TEST_OA_CONFIG_UUID)) {
81 oa_config = i915_oa_config_get(tmp);
82 break;
83 }
84 }
85
86 mutex_unlock(&perf->metrics_lock);
87
88 return oa_config;
89}
90
17static struct i915_perf_stream *91static struct i915_perf_stream *
18test_stream(struct i915_perf *perf)92test_stream(struct i915_perf *perf)
19{93{
20 struct drm_i915_perf_open_param param = {};94 struct drm_i915_perf_open_param param = {};
95 struct i915_oa_config *oa_config = get_empty_config(perf);
21 struct perf_open_properties props = {96 struct perf_open_properties props = {
22 .engine = intel_engine_lookup_user(perf->i915,97 .engine = intel_engine_lookup_user(perf->i915,
23 I915_ENGINE_CLASS_RENDER,98 I915_ENGINE_CLASS_RENDER,
@@ -25,13 +100,19 @@ test_stream(struct i915_perf *perf) · 1 unmodified line
25 .sample_flags = SAMPLE_OA_REPORT,100 .sample_flags = SAMPLE_OA_REPORT,
26 .oa_format = IS_GEN(perf->i915, 12) ?101 .oa_format = IS_GEN(perf->i915, 12) ?
27 I915_OA_FORMAT_A32u40_A4u32_B8_C8 : I915_OA_FORMAT_C4_B8,102 I915_OA_FORMAT_A32u40_A4u32_B8_C8 : I915_OA_FORMAT_C4_B8,
28 .metrics_set = 1,
29 };103 };
30 struct i915_perf_stream *stream;104 struct i915_perf_stream *stream;
31 105
106 if (!oa_config)
107 return NULL;
108
109 props.metrics_set = oa_config->id;
110
32 stream = kzalloc(sizeof(*stream), GFP_KERNEL);111 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
33 if (!stream)112 if (!stream) {
113 i915_oa_config_put(oa_config);
34 return NULL;114 return NULL;
115 }
35 116
36 stream->perf = perf;117 stream->perf = perf;
37 118
@@ -42,6 +123,8 @@ test_stream(struct i915_perf *perf) · 4 unmodified lines
42 }123 }
43 mutex_unlock(&perf->lock);124 mutex_unlock(&perf->lock);
44 125
126 i915_oa_config_put(oa_config);
127
45 return stream;128 return stream;
46}129}
47 130
@@ -206,6 +289,7 @@ int i915_perf_live_selftests(struct drm_i915_private *i915) · 158 unmodified lines
206 SUBTEST(live_noa_delay),289 SUBTEST(live_noa_delay),
207 };290 };
208 struct i915_perf *perf = &i915->perf;291 struct i915_perf *perf = &i915->perf;
292 int err;
209 293
210 if (!perf->metrics_kobj || !perf->ops.enable_metric_set)294 if (!perf->metrics_kobj || !perf->ops.enable_metric_set)
211 return 0;295 return 0;
@@ -213,5 +297,13 @@ int i915_perf_live_selftests(struct drm_i915_private *i915) · 1 unmodified line
213 if (intel_gt_is_wedged(&i915->gt))297 if (intel_gt_is_wedged(&i915->gt))
214 return 0;298 return 0;
215 299
216 return i915_subtests(tests, i915);300 err = alloc_empty_config(&i915->perf);
301 if (err)
302 return err;
303
304 err = i915_subtests(tests, i915);
305
306 destroy_empty_config(&i915->perf);
307
308 return err;
217}309}

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