Pull pin control fixes from Linus Walleij: - Mark som pins as invalid for IRQ use in the Qualcomm driver - Fix up the use of device properties on the MA35DX Nuvoton, apparently something went sidewise - Clear the GPIO debounce settings when going down for suspend in the AMD driver. Very good for some AMD laptops that now wake up from suspend again! - Add the compulsory .can_sleep bool flag in the AW9523 driver, should have been there from the beginning, now there are users finding the bug - Drop some bouncing email address from MAINTAINERS * tag 'pinctrl-v6.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: aw9523: fix can_sleep flag for GPIO chip pinctrl: amd: Clear GPIO debounce for suspend pinctrl: nuvoton: Fix boot on ma35dx platforms MAINTAINERS: drop bouncing Lakshmi Sowjanya D pinctrl: qcom: msm: mark certain pins as invalid for interrupts
Unified · Split
| @@ -19603,8 +19603,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git · 19602 unmodified lines | ||
| 19603 | 19603 | F: drivers/pinctrl/intel/ |
| 19604 | 19604 | |
| 19605 | 19605 | PIN CONTROLLER - KEEMBAY |
| 19606 | −M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> | |
| 19607 | −S: Supported | |
| 19606 | +S: Orphan | |
| 19608 | 19607 | F: drivers/pinctrl/pinctrl-keembay* |
| 19609 | 19608 | |
| 19610 | 19609 | PIN CONTROLLER - MEDIATEK |
| @@ -1074,7 +1074,10 @@ static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinct · 1073 unmodified lines | ||
| 1074 | 1074 | u32 idx = 0; |
| 1075 | 1075 | int ret; |
| 1076 | 1076 | |
| 1077 | − for_each_gpiochip_node(dev, child) { | |
| 1077 | + device_for_each_child_node(dev, child) { | |
| 1078 | + if (fwnode_property_present(child, "gpio-controller")) | |
| 1079 | + continue; | |
| 1080 | + | |
| 1078 | 1081 | npctl->nfunctions++; |
| 1079 | 1082 | npctl->ngroups += of_get_child_count(to_of_node(child)); |
| 1080 | 1083 | } |
| @@ -1092,7 +1095,10 @@ static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinct · 11 unmodified lines | ||
| 1092 | 1095 | if (!npctl->groups) |
| 1093 | 1096 | return -ENOMEM; |
| 1094 | 1097 | |
| 1095 | − for_each_gpiochip_node(dev, child) { | |
| 1098 | + device_for_each_child_node(dev, child) { | |
| 1099 | + if (fwnode_property_present(child, "gpio-controller")) | |
| 1100 | + continue; | |
| 1101 | + | |
| 1096 | 1102 | ret = ma35_pinctrl_parse_functions(child, npctl, idx++); |
| 1097 | 1103 | if (ret) { |
| 1098 | 1104 | fwnode_handle_put(child); |
| @@ -979,6 +979,17 @@ static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend · 978 unmodified lines | ||
| 979 | 979 | pin, is_suspend ? "suspend" : "hibernate"); |
| 980 | 980 | } |
| 981 | 981 | |
| 982 | + /* | |
| 983 | + * debounce enabled over suspend has shown issues with a GPIO | |
| 984 | + * being unable to wake the system, as we're only interested in | |
| 985 | + * the actual wakeup event, clear it. | |
| 986 | + */ | |
| 987 | + if (gpio_dev->saved_regs[i] & (DB_CNTRl_MASK << DB_CNTRL_OFF)) { | |
| 988 | + amd_gpio_set_debounce(gpio_dev, pin, 0); | |
| 989 | + pm_pr_dbg("Clearing debounce for GPIO #%d during %s.\n", | |
| 990 | + pin, is_suspend ? "suspend" : "hibernate"); | |
| 991 | + } | |
| 992 | + | |
| 982 | 993 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
| 983 | 994 | } |
| 984 | 995 | |
| @@ -784,7 +784,7 @@ static int aw9523_init_gpiochip(struct aw9523 *awi, unsigned int npins) · 783 unmodified lines | ||
| 784 | 784 | gc->set_config = gpiochip_generic_config; |
| 785 | 785 | gc->parent = dev; |
| 786 | 786 | gc->owner = THIS_MODULE; |
| 787 | − gc->can_sleep = false; | |
| 787 | + gc->can_sleep = true; | |
| 788 | 788 | |
| 789 | 789 | return 0; |
| 790 | 790 | } |
| @@ -1038,6 +1038,25 @@ static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d, · 1037 unmodified lines | ||
| 1038 | 1038 | test_bit(d->hwirq, pctrl->skip_wake_irqs); |
| 1039 | 1039 | } |
| 1040 | 1040 | |
| 1041 | +static void msm_gpio_irq_init_valid_mask(struct gpio_chip *gc, | |
| 1042 | + unsigned long *valid_mask, | |
| 1043 | + unsigned int ngpios) | |
| 1044 | +{ | |
| 1045 | + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); | |
| 1046 | + const struct msm_pingroup *g; | |
| 1047 | + int i; | |
| 1048 | + | |
| 1049 | + bitmap_fill(valid_mask, ngpios); | |
| 1050 | + | |
| 1051 | + for (i = 0; i < ngpios; i++) { | |
| 1052 | + g = &pctrl->soc->groups[i]; | |
| 1053 | + | |
| 1054 | + if (g->intr_detection_width != 1 && | |
| 1055 | + g->intr_detection_width != 2) | |
| 1056 | + clear_bit(i, valid_mask); | |
| 1057 | + } | |
| 1058 | +} | |
| 1059 | + | |
| 1041 | 1060 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
| 1042 | 1061 | { |
| 1043 | 1062 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| @@ -1441,6 +1460,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) · 397 unmodified lines | ||
| 1441 | 1460 | girq->default_type = IRQ_TYPE_NONE; |
| 1442 | 1461 | girq->handler = handle_bad_irq; |
| 1443 | 1462 | girq->parents[0] = pctrl->irq; |
| 1463 | + girq->init_valid_mask = msm_gpio_irq_init_valid_mask; | |
| 1444 | 1464 | |
| 1445 | 1465 | ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); |
| 1446 | 1466 | if (ret) { |