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Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux

Pull drm updates from Dave Airlie: "Been a bit busy, first week of kids school, and waiting on other trees to go in before I could send this, so its a bit later than I'd normally like. Highlights: - core: timestamp fixes, lots of misc cleanups - new drivers: bochs virtual vga - vmwgfx: major overhaul for their nextgen virt gpu. - i915: runtime D3 on HSW, watermark fixes, power well work, fbc fixes, bdw is no longer prelim. - nouveau: gk110/208 acceleration, more pm groundwork, old overlay support - radeon: dpm rework and clockgating for CIK, pci config reset, big endian fixes - tegra: panel support and DSI support, build as module, prime. - armada, omap, gma500, rcar, exynos, mgag200, cirrus, ast: fixes - msm: hdmi support for mdp5" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (595 commits) drm/nouveau: resume display if any later suspend bits fail drm/nouveau: fix lock unbalance in nouveau_crtc_page_flip drm/nouveau: implement hooks for needed for drm vblank timestamping support drm/nouveau/disp: add a method to fetch info needed by drm vblank timestamping drm/nv50: fill in crtc mode struct members from crtc_mode_fixup drm/radeon/dce8: workaround for atom BlankCrtc table drm/radeon/DCE4+: clear bios scratch dpms bit (v2) drm/radeon: set si_notify_smc_display_change properly drm/radeon: fix DAC interrupt handling on DCE5+ drm/radeon: clean up active vram sizing drm/radeon: skip async dma init on r6xx drm/radeon/runpm: don't runtime suspend non-PX cards drm/radeon: add ring to fence trace functions drm/radeon: add missing trace point drm/radeon: fix VMID use tracking drm: ast,cirrus,mgag200: use drm_can_sleep drm/gma500: Lock struct_mutex around cursor updates drm/i915: Fix the offset issue for the stolen GEM objects DRM: armada: fix missing DRM_KMS_FB_HELPER select drm/i915: Decouple GPU error reporting from ring initialisation ...

Linus Torvalds committed 12 years ago

Commit 9b0cd302 parents ca2a650 ef64cf9512 files · +35539 −11886Browse files

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4 files
  1. include/uapi/drm/drm.h +0 −1
  2. include/uapi/drm/i915_drm.h +20 −1
  3. include/uapi/drm/radeon_drm.h +2 −0
  4. include/uapi/drm/vmwgfx_drm.h +260 −0
include/uapi/drm/drm.h+0−1
@@ -181,7 +181,6 @@ enum drm_map_type { · 180 unmodified lines
181181 _DRM_AGP = 3, /**< AGP/GART */
182182 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
183183 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
184− _DRM_GEM = 6, /**< GEM object (obsolete) */
185184 };
186185
187186 /**
include/uapi/drm/i915_drm.h+20−1
@@ -222,6 +222,7 @@ typedef struct _drm_i915_sarea { · 221 unmodified lines
222222 #define DRM_I915_GEM_SET_CACHING 0x2f
223223 #define DRM_I915_GEM_GET_CACHING 0x30
224224 #define DRM_I915_REG_READ 0x31
225+#define DRM_I915_GET_RESET_STATS 0x32
225226
226227 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
227228 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -271,6 +272,7 @@ typedef struct _drm_i915_sarea { · 43 unmodified lines
271272 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
272273 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
273274 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
275+#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
274276
275277 /* Allow drivers to submit batchbuffers directly to hardware, relying
276278 * on the security mechanisms provided by hardware.
@@ -719,7 +721,7 @@ struct drm_i915_gem_execbuffer2 { · 442 unmodified lines
719721 */
720722 #define I915_EXEC_IS_PINNED (1<<10)
721723
722−/** Provide a hint to the kernel that the command stream and auxilliary
724+/** Provide a hint to the kernel that the command stream and auxiliary
723725 * state buffers already holds the correct presumed addresses and so the
724726 * relocation process may be skipped if no buffers need to be moved in
725727 * preparation for the execbuffer.
@@ -1030,4 +1032,21 @@ struct drm_i915_reg_read { · 304 unmodified lines
10301032 __u64 offset;
10311033 __u64 val; /* Return value */
10321034 };
1035+
1036+struct drm_i915_reset_stats {
1037+ __u32 ctx_id;
1038+ __u32 flags;
1039+
1040+ /* All resets since boot/module reload, for all contexts */
1041+ __u32 reset_count;
1042+
1043+ /* Number of batches lost when active in GPU, for this context */
1044+ __u32 batch_active;
1045+
1046+ /* Number of batches lost pending for execution, for this context */
1047+ __u32 batch_pending;
1048+
1049+ __u32 pad;
1050+};
1051+
10331052 #endif /* _UAPI_I915_DRM_H_ */
include/uapi/drm/radeon_drm.h+2−0
@@ -985,6 +985,8 @@ struct drm_radeon_cs { · 984 unmodified lines
985985 #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
986986 /* query the number of render backends */
987987 #define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
988+/* max engine clock - needed for OpenCL */
989+#define RADEON_INFO_MAX_SCLK 0x1a
988990
989991
990992 struct drm_radeon_info {
include/uapi/drm/vmwgfx_drm.h+260−0
@@ -28,6 +28,10 @@ · 27 unmodified lines
2828 #ifndef __VMWGFX_DRM_H__
2929 #define __VMWGFX_DRM_H__
3030
31+#ifndef __KERNEL__
32+#include <drm.h>
33+#endif
34+
3135 #define DRM_VMW_MAX_SURFACE_FACES 6
3236 #define DRM_VMW_MAX_MIP_LEVELS 24
3337
@@ -55,6 +59,11 @@ · 21 unmodified lines
5559 #define DRM_VMW_PRESENT 18
5660 #define DRM_VMW_PRESENT_READBACK 19
5761 #define DRM_VMW_UPDATE_LAYOUT 20
62+#define DRM_VMW_CREATE_SHADER 21
63+#define DRM_VMW_UNREF_SHADER 22
64+#define DRM_VMW_GB_SURFACE_CREATE 23
65+#define DRM_VMW_GB_SURFACE_REF 24
66+#define DRM_VMW_SYNCCPU 25
5867
5968 /*************************************************************************/
6069 /**
@@ -76,6 +85,8 @@ · 15 unmodified lines
7685 #define DRM_VMW_PARAM_MAX_FB_SIZE 5
7786 #define DRM_VMW_PARAM_FIFO_HW_VERSION 6
7887 #define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
88+#define DRM_VMW_PARAM_3D_CAPS_SIZE 8
89+#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
7990
8091 /**
8192 * struct drm_vmw_getparam_arg
@@ -788,4 +799,253 @@ struct drm_vmw_update_layout_arg { · 706 unmodified lines
788799 uint64_t rects;
789800 };
790801
802+
803+/*************************************************************************/
804+/**
805+ * DRM_VMW_CREATE_SHADER - Create shader
806+ *
807+ * Creates a shader and optionally binds it to a dma buffer containing
808+ * the shader byte-code.
809+ */
810+
811+/**
812+ * enum drm_vmw_shader_type - Shader types
813+ */
814+enum drm_vmw_shader_type {
815+ drm_vmw_shader_type_vs = 0,
816+ drm_vmw_shader_type_ps,
817+ drm_vmw_shader_type_gs
818+};
819+
820+
821+/**
822+ * struct drm_vmw_shader_create_arg
823+ *
824+ * @shader_type: Shader type of the shader to create.
825+ * @size: Size of the byte-code in bytes.
826+ * where the shader byte-code starts
827+ * @buffer_handle: Buffer handle identifying the buffer containing the
828+ * shader byte-code
829+ * @shader_handle: On successful completion contains a handle that
830+ * can be used to subsequently identify the shader.
831+ * @offset: Offset in bytes into the buffer given by @buffer_handle,
832+ *
833+ * Input / Output argument to the DRM_VMW_CREATE_SHADER Ioctl.
834+ */
835+struct drm_vmw_shader_create_arg {
836+ enum drm_vmw_shader_type shader_type;
837+ uint32_t size;
838+ uint32_t buffer_handle;
839+ uint32_t shader_handle;
840+ uint64_t offset;
841+};
842+
843+/*************************************************************************/
844+/**
845+ * DRM_VMW_UNREF_SHADER - Unreferences a shader
846+ *
847+ * Destroys a user-space reference to a shader, optionally destroying
848+ * it.
849+ */
850+
851+/**
852+ * struct drm_vmw_shader_arg
853+ *
854+ * @handle: Handle identifying the shader to destroy.
855+ *
856+ * Input argument to the DRM_VMW_UNREF_SHADER ioctl.
857+ */
858+struct drm_vmw_shader_arg {
859+ uint32_t handle;
860+ uint32_t pad64;
861+};
862+
863+/*************************************************************************/
864+/**
865+ * DRM_VMW_GB_SURFACE_CREATE - Create a host guest-backed surface.
866+ *
867+ * Allocates a surface handle and queues a create surface command
868+ * for the host on the first use of the surface. The surface ID can
869+ * be used as the surface ID in commands referencing the surface.
870+ */
871+
872+/**
873+ * enum drm_vmw_surface_flags
874+ *
875+ * @drm_vmw_surface_flag_shareable: Whether the surface is shareable
876+ * @drm_vmw_surface_flag_scanout: Whether the surface is a scanout
877+ * surface.
878+ * @drm_vmw_surface_flag_create_buffer: Create a backup buffer if none is
879+ * given.
880+ */
881+enum drm_vmw_surface_flags {
882+ drm_vmw_surface_flag_shareable = (1 << 0),
883+ drm_vmw_surface_flag_scanout = (1 << 1),
884+ drm_vmw_surface_flag_create_buffer = (1 << 2)
885+};
886+
887+/**
888+ * struct drm_vmw_gb_surface_create_req
889+ *
890+ * @svga3d_flags: SVGA3d surface flags for the device.
891+ * @format: SVGA3d format.
892+ * @mip_level: Number of mip levels for all faces.
893+ * @drm_surface_flags Flags as described above.
894+ * @multisample_count Future use. Set to 0.
895+ * @autogen_filter Future use. Set to 0.
896+ * @buffer_handle Buffer handle of backup buffer. SVGA3D_INVALID_ID
897+ * if none.
898+ * @base_size Size of the base mip level for all faces.
899+ *
900+ * Input argument to the DRM_VMW_GB_SURFACE_CREATE Ioctl.
901+ * Part of output argument for the DRM_VMW_GB_SURFACE_REF Ioctl.
902+ */
903+struct drm_vmw_gb_surface_create_req {
904+ uint32_t svga3d_flags;
905+ uint32_t format;
906+ uint32_t mip_levels;
907+ enum drm_vmw_surface_flags drm_surface_flags;
908+ uint32_t multisample_count;
909+ uint32_t autogen_filter;
910+ uint32_t buffer_handle;
911+ uint32_t pad64;
912+ struct drm_vmw_size base_size;
913+};
914+
915+/**
916+ * struct drm_vmw_gb_surface_create_rep
917+ *
918+ * @handle: Surface handle.
919+ * @backup_size: Size of backup buffers for this surface.
920+ * @buffer_handle: Handle of backup buffer. SVGA3D_INVALID_ID if none.
921+ * @buffer_size: Actual size of the buffer identified by
922+ * @buffer_handle
923+ * @buffer_map_handle: Offset into device address space for the buffer
924+ * identified by @buffer_handle.
925+ *
926+ * Part of output argument for the DRM_VMW_GB_SURFACE_REF ioctl.
927+ * Output argument for the DRM_VMW_GB_SURFACE_CREATE ioctl.
928+ */
929+struct drm_vmw_gb_surface_create_rep {
930+ uint32_t handle;
931+ uint32_t backup_size;
932+ uint32_t buffer_handle;
933+ uint32_t buffer_size;
934+ uint64_t buffer_map_handle;
935+};
936+
937+/**
938+ * union drm_vmw_gb_surface_create_arg
939+ *
940+ * @req: Input argument as described above.
941+ * @rep: Output argument as described above.
942+ *
943+ * Argument to the DRM_VMW_GB_SURFACE_CREATE ioctl.
944+ */
945+union drm_vmw_gb_surface_create_arg {
946+ struct drm_vmw_gb_surface_create_rep rep;
947+ struct drm_vmw_gb_surface_create_req req;
948+};
949+
950+/*************************************************************************/
951+/**
952+ * DRM_VMW_GB_SURFACE_REF - Reference a host surface.
953+ *
954+ * Puts a reference on a host surface with a given handle, as previously
955+ * returned by the DRM_VMW_GB_SURFACE_CREATE ioctl.
956+ * A reference will make sure the surface isn't destroyed while we hold
957+ * it and will allow the calling client to use the surface handle in
958+ * the command stream.
959+ *
960+ * On successful return, the Ioctl returns the surface information given
961+ * to and returned from the DRM_VMW_GB_SURFACE_CREATE ioctl.
962+ */
963+
964+/**
965+ * struct drm_vmw_gb_surface_reference_arg
966+ *
967+ * @creq: The data used as input when the surface was created, as described
968+ * above at "struct drm_vmw_gb_surface_create_req"
969+ * @crep: Additional data output when the surface was created, as described
970+ * above at "struct drm_vmw_gb_surface_create_rep"
971+ *
972+ * Output Argument to the DRM_VMW_GB_SURFACE_REF ioctl.
973+ */
974+struct drm_vmw_gb_surface_ref_rep {
975+ struct drm_vmw_gb_surface_create_req creq;
976+ struct drm_vmw_gb_surface_create_rep crep;
977+};
978+
979+/**
980+ * union drm_vmw_gb_surface_reference_arg
981+ *
982+ * @req: Input data as described above at "struct drm_vmw_surface_arg"
983+ * @rep: Output data as described above at "struct drm_vmw_gb_surface_ref_rep"
984+ *
985+ * Argument to the DRM_VMW_GB_SURFACE_REF Ioctl.
986+ */
987+union drm_vmw_gb_surface_reference_arg {
988+ struct drm_vmw_gb_surface_ref_rep rep;
989+ struct drm_vmw_surface_arg req;
990+};
991+
992+
993+/*************************************************************************/
994+/**
995+ * DRM_VMW_SYNCCPU - Sync a DMA buffer / MOB for CPU access.
996+ *
997+ * Idles any previously submitted GPU operations on the buffer and
998+ * by default blocks command submissions that reference the buffer.
999+ * If the file descriptor used to grab a blocking CPU sync is closed, the
1000+ * cpu sync is released.
1001+ * The flags argument indicates how the grab / release operation should be
1002+ * performed:
1003+ */
1004+
1005+/**
1006+ * enum drm_vmw_synccpu_flags - Synccpu flags:
1007+ *
1008+ * @drm_vmw_synccpu_read: Sync for read. If sync is done for read only, it's a
1009+ * hint to the kernel to allow command submissions that references the buffer
1010+ * for read-only.
1011+ * @drm_vmw_synccpu_write: Sync for write. Block all command submissions
1012+ * referencing this buffer.
1013+ * @drm_vmw_synccpu_dontblock: Dont wait for GPU idle, but rather return
1014+ * -EBUSY should the buffer be busy.
1015+ * @drm_vmw_synccpu_allow_cs: Allow command submission that touches the buffer
1016+ * while the buffer is synced for CPU. This is similar to the GEM bo idle
1017+ * behavior.
1018+ */
1019+enum drm_vmw_synccpu_flags {
1020+ drm_vmw_synccpu_read = (1 << 0),
1021+ drm_vmw_synccpu_write = (1 << 1),
1022+ drm_vmw_synccpu_dontblock = (1 << 2),
1023+ drm_vmw_synccpu_allow_cs = (1 << 3)
1024+};
1025+
1026+/**
1027+ * enum drm_vmw_synccpu_op - Synccpu operations:
1028+ *
1029+ * @drm_vmw_synccpu_grab: Grab the buffer for CPU operations
1030+ * @drm_vmw_synccpu_release: Release a previous grab.
1031+ */
1032+enum drm_vmw_synccpu_op {
1033+ drm_vmw_synccpu_grab,
1034+ drm_vmw_synccpu_release
1035+};
1036+
1037+/**
1038+ * struct drm_vmw_synccpu_arg
1039+ *
1040+ * @op: The synccpu operation as described above.
1041+ * @handle: Handle identifying the buffer object.
1042+ * @flags: Flags as described above.
1043+ */
1044+struct drm_vmw_synccpu_arg {
1045+ enum drm_vmw_synccpu_op op;
1046+ enum drm_vmw_synccpu_flags flags;
1047+ uint32_t handle;
1048+ uint32_t pad64;
1049+};
1050+
7911051 #endif