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Merge branches 'iommu/fixes', 'arm/qcom', 'arm/renesas', 'arm/rockchip', 'arm/mediatek', 'arm/tegra', 'arm/smmu', 'x86/amd', 'x86/vt-d', 'virtio' and 'core' into next

Joerg Roedel committed 7 years ago

Commit 9b3a71311 parents 4e7120d da6b05d 1289f7f 5b47748 c90ae4a 96d3ab8 34d1b08 3c12443 6c3a44e c1c8058 808be0a43 files · +1651 −1213Browse files

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include/uapi/linux/iommu.h+169−0
@@ -152,4 +152,173 @@ struct iommu_page_response { · 151 unmodified lines
152152 __u32 code;
153153 };
154154
155+/* defines the granularity of the invalidation */
156+enum iommu_inv_granularity {
157+ IOMMU_INV_GRANU_DOMAIN, /* domain-selective invalidation */
158+ IOMMU_INV_GRANU_PASID, /* PASID-selective invalidation */
159+ IOMMU_INV_GRANU_ADDR, /* page-selective invalidation */
160+ IOMMU_INV_GRANU_NR, /* number of invalidation granularities */
161+};
162+
163+/**
164+ * struct iommu_inv_addr_info - Address Selective Invalidation Structure
165+ *
166+ * @flags: indicates the granularity of the address-selective invalidation
167+ * - If the PASID bit is set, the @pasid field is populated and the invalidation
168+ * relates to cache entries tagged with this PASID and matching the address
169+ * range.
170+ * - If ARCHID bit is set, @archid is populated and the invalidation relates
171+ * to cache entries tagged with this architecture specific ID and matching
172+ * the address range.
173+ * - Both PASID and ARCHID can be set as they may tag different caches.
174+ * - If neither PASID or ARCHID is set, global addr invalidation applies.
175+ * - The LEAF flag indicates whether only the leaf PTE caching needs to be
176+ * invalidated and other paging structure caches can be preserved.
177+ * @pasid: process address space ID
178+ * @archid: architecture-specific ID
179+ * @addr: first stage/level input address
180+ * @granule_size: page/block size of the mapping in bytes
181+ * @nb_granules: number of contiguous granules to be invalidated
182+ */
183+struct iommu_inv_addr_info {
184+#define IOMMU_INV_ADDR_FLAGS_PASID (1 << 0)
185+#define IOMMU_INV_ADDR_FLAGS_ARCHID (1 << 1)
186+#define IOMMU_INV_ADDR_FLAGS_LEAF (1 << 2)
187+ __u32 flags;
188+ __u32 archid;
189+ __u64 pasid;
190+ __u64 addr;
191+ __u64 granule_size;
192+ __u64 nb_granules;
193+};
194+
195+/**
196+ * struct iommu_inv_pasid_info - PASID Selective Invalidation Structure
197+ *
198+ * @flags: indicates the granularity of the PASID-selective invalidation
199+ * - If the PASID bit is set, the @pasid field is populated and the invalidation
200+ * relates to cache entries tagged with this PASID and matching the address
201+ * range.
202+ * - If the ARCHID bit is set, the @archid is populated and the invalidation
203+ * relates to cache entries tagged with this architecture specific ID and
204+ * matching the address range.
205+ * - Both PASID and ARCHID can be set as they may tag different caches.
206+ * - At least one of PASID or ARCHID must be set.
207+ * @pasid: process address space ID
208+ * @archid: architecture-specific ID
209+ */
210+struct iommu_inv_pasid_info {
211+#define IOMMU_INV_PASID_FLAGS_PASID (1 << 0)
212+#define IOMMU_INV_PASID_FLAGS_ARCHID (1 << 1)
213+ __u32 flags;
214+ __u32 archid;
215+ __u64 pasid;
216+};
217+
218+/**
219+ * struct iommu_cache_invalidate_info - First level/stage invalidation
220+ * information
221+ * @version: API version of this structure
222+ * @cache: bitfield that allows to select which caches to invalidate
223+ * @granularity: defines the lowest granularity used for the invalidation:
224+ * domain > PASID > addr
225+ * @padding: reserved for future use (should be zero)
226+ * @pasid_info: invalidation data when @granularity is %IOMMU_INV_GRANU_PASID
227+ * @addr_info: invalidation data when @granularity is %IOMMU_INV_GRANU_ADDR
228+ *
229+ * Not all the combinations of cache/granularity are valid:
230+ *
231+ * +--------------+---------------+---------------+---------------+
232+ * | type / | DEV_IOTLB | IOTLB | PASID |
233+ * | granularity | | | cache |
234+ * +==============+===============+===============+===============+
235+ * | DOMAIN | N/A | Y | Y |
236+ * +--------------+---------------+---------------+---------------+
237+ * | PASID | Y | Y | Y |
238+ * +--------------+---------------+---------------+---------------+
239+ * | ADDR | Y | Y | N/A |
240+ * +--------------+---------------+---------------+---------------+
241+ *
242+ * Invalidations by %IOMMU_INV_GRANU_DOMAIN don't take any argument other than
243+ * @version and @cache.
244+ *
245+ * If multiple cache types are invalidated simultaneously, they all
246+ * must support the used granularity.
247+ */
248+struct iommu_cache_invalidate_info {
249+#define IOMMU_CACHE_INVALIDATE_INFO_VERSION_1 1
250+ __u32 version;
251+/* IOMMU paging structure cache */
252+#define IOMMU_CACHE_INV_TYPE_IOTLB (1 << 0) /* IOMMU IOTLB */
253+#define IOMMU_CACHE_INV_TYPE_DEV_IOTLB (1 << 1) /* Device IOTLB */
254+#define IOMMU_CACHE_INV_TYPE_PASID (1 << 2) /* PASID cache */
255+#define IOMMU_CACHE_INV_TYPE_NR (3)
256+ __u8 cache;
257+ __u8 granularity;
258+ __u8 padding[2];
259+ union {
260+ struct iommu_inv_pasid_info pasid_info;
261+ struct iommu_inv_addr_info addr_info;
262+ };
263+};
264+
265+/**
266+ * struct iommu_gpasid_bind_data_vtd - Intel VT-d specific data on device and guest
267+ * SVA binding.
268+ *
269+ * @flags: VT-d PASID table entry attributes
270+ * @pat: Page attribute table data to compute effective memory type
271+ * @emt: Extended memory type
272+ *
273+ * Only guest vIOMMU selectable and effective options are passed down to
274+ * the host IOMMU.
275+ */
276+struct iommu_gpasid_bind_data_vtd {
277+#define IOMMU_SVA_VTD_GPASID_SRE (1 << 0) /* supervisor request */
278+#define IOMMU_SVA_VTD_GPASID_EAFE (1 << 1) /* extended access enable */
279+#define IOMMU_SVA_VTD_GPASID_PCD (1 << 2) /* page-level cache disable */
280+#define IOMMU_SVA_VTD_GPASID_PWT (1 << 3) /* page-level write through */
281+#define IOMMU_SVA_VTD_GPASID_EMTE (1 << 4) /* extended mem type enable */
282+#define IOMMU_SVA_VTD_GPASID_CD (1 << 5) /* PASID-level cache disable */
283+ __u64 flags;
284+ __u32 pat;
285+ __u32 emt;
286+};
287+
288+/**
289+ * struct iommu_gpasid_bind_data - Information about device and guest PASID binding
290+ * @version: Version of this data structure
291+ * @format: PASID table entry format
292+ * @flags: Additional information on guest bind request
293+ * @gpgd: Guest page directory base of the guest mm to bind
294+ * @hpasid: Process address space ID used for the guest mm in host IOMMU
295+ * @gpasid: Process address space ID used for the guest mm in guest IOMMU
296+ * @addr_width: Guest virtual address width
297+ * @padding: Reserved for future use (should be zero)
298+ * @vtd: Intel VT-d specific data
299+ *
300+ * Guest to host PASID mapping can be an identity or non-identity, where guest
301+ * has its own PASID space. For non-identify mapping, guest to host PASID lookup
302+ * is needed when VM programs guest PASID into an assigned device. VMM may
303+ * trap such PASID programming then request host IOMMU driver to convert guest
304+ * PASID to host PASID based on this bind data.
305+ */
306+struct iommu_gpasid_bind_data {
307+#define IOMMU_GPASID_BIND_VERSION_1 1
308+ __u32 version;
309+#define IOMMU_PASID_FORMAT_INTEL_VTD 1
310+ __u32 format;
311+#define IOMMU_SVA_GPASID_VAL (1 << 0) /* guest PASID valid */
312+ __u64 flags;
313+ __u64 gpgd;
314+ __u64 hpasid;
315+ __u64 gpasid;
316+ __u32 addr_width;
317+ __u8 padding[12];
318+ /* Vendor specific data */
319+ union {
320+ struct iommu_gpasid_bind_data_vtd vtd;
321+ };
322+};
323+
155324 #endif /* _UAPI_IOMMU_H */