History

Merge tag 'arc-v3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC updates from Vineet Gupta: "Nothing too exciting here, just minor fixes/cleanup. Only noteworthy ones are: - Moving cache disabling to early boot - ARC UART enabled only if earlyprintk setup in cmdline" * tag 'arc-v3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: Disable caches in early boot if so configured ARC: [arcfpga] Early ARC UART to be only activated by cmdline ARC: [arcfpga] Get rid of legacy BVCI latency unit support ARC: remove duplicate header exports ARC: arc_local_timer_setup() need not pass own cpu id ARC: Fixed spelling errors within comments ARC: make start_thread() out-of-line ARC: fix mmuv2 warning ARC: [SMP] ISS SMP extension bitrot

Linus Torvalds committed 12 years ago

Commit 9b651cc2 parents 214b931 ef680cd16 files · +158 −249Browse files

Unified · Split

16 files
  1. arch/arc/boot/dts/angel4.dts +1 −1
  2. arch/arc/include/asm/cache.h +27 −0
  3. arch/arc/include/asm/irq.h +1 −3
  4. arch/arc/include/asm/processor.h +4 −25
  5. arch/arc/include/uapi/asm/Kbuild +0 −7
  6. arch/arc/kernel/entry.S +6 −6
  7. arch/arc/kernel/head.S +35 −3
  8. arch/arc/kernel/irq.c +0 −18
  9. arch/arc/kernel/process.c +23 −0
  10. arch/arc/kernel/smp.c +1 −1
  11. arch/arc/kernel/time.c +6 −5
  12. arch/arc/mm/cache_arc700.c +29 −81
  13. arch/arc/plat-arcfpga/Kconfig +0 −32
  14. arch/arc/plat-arcfpga/Makefile +1 −1
  15. arch/arc/plat-arcfpga/platform.c +6 −66
  16. arch/arc/plat-arcfpga/smp.c +18 −0
arch/arc/boot/dts/angel4.dts+1−1
@@ -17,7 +17,7 @@ · 16 unmodified lines
1717 interrupt-parent = <&intc>;
1818
1919 chosen {
20− bootargs = "console=ttyARC0,115200n8";
20+ bootargs = "console=ttyARC0,115200n8 earlyprintk=ttyARC0";
2121 };
2222
2323 aliases {
arch/arc/include/asm/cache.h+27−0
@@ -55,4 +55,31 @@ extern void read_decode_cache_bcr(void); · 54 unmodified lines
5555
5656 #endif /* !__ASSEMBLY__ */
5757
58+/* Instruction cache related Auxiliary registers */
59+#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
60+#define ARC_REG_IC_IVIC 0x10
61+#define ARC_REG_IC_CTRL 0x11
62+#define ARC_REG_IC_IVIL 0x19
63+#if defined(CONFIG_ARC_MMU_V3) || defined (CONFIG_ARC_MMU_V4)
64+#define ARC_REG_IC_PTAG 0x1E
65+#endif
66+
67+/* Bit val in IC_CTRL */
68+#define IC_CTRL_CACHE_DISABLE 0x1
69+
70+/* Data cache related Auxiliary registers */
71+#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
72+#define ARC_REG_DC_IVDC 0x47
73+#define ARC_REG_DC_CTRL 0x48
74+#define ARC_REG_DC_IVDL 0x4A
75+#define ARC_REG_DC_FLSH 0x4B
76+#define ARC_REG_DC_FLDL 0x4C
77+#if defined(CONFIG_ARC_MMU_V3) || defined (CONFIG_ARC_MMU_V4)
78+#define ARC_REG_DC_PTAG 0x5C
79+#endif
80+
81+/* Bit val in DC_CTRL */
82+#define DC_CTRL_INV_MODE_FLUSH 0x40
83+#define DC_CTRL_FLUSH_STATUS 0x100
84+
5885 #endif /* _ASM_CACHE_H */
arch/arc/include/asm/irq.h+1−3
@@ -19,8 +19,6 @@ · 18 unmodified lines
1919 #include <asm-generic/irq.h>
2020
2121 extern void arc_init_IRQ(void);
22−extern int get_hw_config_num_irq(void);
23−
24−void arc_local_timer_setup(unsigned int cpu);
22+void arc_local_timer_setup(void);
2523
2624 #endif
arch/arc/include/asm/processor.h+4−25
@@ -18,7 +18,6 @@ · 17 unmodified lines
1818
1919 #ifndef __ASSEMBLY__
2020
21−#include <asm/arcregs.h> /* for STATUS_E1_MASK et all */
2221 #include <asm/ptrace.h>
2322
2423 /* Arch specific stuff which needs to be saved per task.
@@ -41,15 +40,13 @@ struct thread_struct { · 16 unmodified lines
4140 /* Forward declaration, a strange C thing */
4241 struct task_struct;
4342
44−/*
45− * Return saved PC of a blocked thread.
46− */
43+/* Return saved PC of a blocked thread */
4744 unsigned long thread_saved_pc(struct task_struct *t);
4845
4946 #define task_pt_regs(p) \
5047 ((struct pt_regs *)(THREAD_SIZE + (void *)task_stack_page(p)) - 1)
5148
52−/* Free all resources held by a thread. */
49+/* Free all resources held by a thread */
5350 #define release_thread(thread) do { } while (0)
5451
5552 /* Prepare to copy thread state - unlazy all lazy status */
@@ -82,26 +79,8 @@ unsigned long thread_saved_pc(struct task_struct *t); · 26 unmodified lines
8279 #define KSTK_BLINK(tsk) KSTK_REG(tsk, 4)
8380 #define KSTK_FP(tsk) KSTK_REG(tsk, 0)
8481
85−/*
86− * Do necessary setup to start up a newly executed thread.
87− *
88− * E1,E2 so that Interrupts are enabled in user mode
89− * L set, so Loop inhibited to begin with
90− * lp_start and lp_end seeded with bogus non-zero values so to easily catch
91− * the ARC700 sr to lp_start hardware bug
92− */
93−#define start_thread(_regs, _pc, _usp) \
94−do { \
95− set_fs(USER_DS); /* reads from user space */ \
96− (_regs)->ret = (_pc); \
97− /* Interrupts enabled in User Mode */ \
98− (_regs)->status32 = STATUS_U_MASK | STATUS_L_MASK \
99− | STATUS_E1_MASK | STATUS_E2_MASK; \
100− (_regs)->sp = (_usp); \
101− /* bogus seed values for debugging */ \
102− (_regs)->lp_start = 0x10; \
103− (_regs)->lp_end = 0x80; \
104−} while (0)
82+extern void start_thread(struct pt_regs * regs, unsigned long pc,
83+ unsigned long usp);
10584
10685 extern unsigned int get_wchan(struct task_struct *p);
10786
arch/arc/include/uapi/asm/Kbuild+0−7
@@ -2,11 +2,4 @@ · 1 unmodified line
22 include include/uapi/asm-generic/Kbuild.asm
33 header-y += elf.h
44 header-y += page.h
5−header-y += setup.h
6−header-y += byteorder.h
75 header-y += cachectl.h
8−header-y += ptrace.h
9−header-y += sigcontext.h
10−header-y += signal.h
11−header-y += swab.h
12−header-y += unistd.h
arch/arc/kernel/entry.S+6−6
@@ -156,7 +156,7 @@ ARCFP_DATA int1_saved_reg · 155 unmodified lines
156156 int1_saved_reg:
157157 .zero 4
158158
159−/* Each Interrupt level needs it's own scratch */
159+/* Each Interrupt level needs its own scratch */
160160 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
161161
162162 ARCFP_DATA int2_saved_reg
@@ -473,7 +473,7 @@ trap_with_param: · 310 unmodified lines
473473 lr r0, [efa]
474474 mov r1, sp
475475
476− ; Now that we have read EFA, its safe to do "fake" rtie
476+ ; Now that we have read EFA, it is safe to do "fake" rtie
477477 ; and get out of CPU exception mode
478478 FAKE_RET_FROM_EXCPN r11
479479
@@ -678,9 +678,9 @@ not_exception: · 198 unmodified lines
678678 brne r9, event_IRQ2, 149f
679679
680680 ;------------------------------------------------------------------
681− ; if L2 IRQ interrupted a L1 ISR, we'd disbaled preemption earlier
682− ; so that sched doesnt move to new task, causing L1 to be delayed
683− ; undeterministically. Now that we've achieved that, lets reset
681+ ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
682+ ; so that sched doesn't move to new task, causing L1 to be delayed
683+ ; undeterministically. Now that we've achieved that, let's reset
684684 ; things to what they were, before returning from L2 context
685685 ;----------------------------------------------------------------
686686
@@ -736,7 +736,7 @@ ENTRY(ret_from_fork) · 49 unmodified lines
736736 ; put last task in scheduler queue
737737 bl @schedule_tail
738738
739− ; If kernel thread, jump to it's entry-point
739+ ; If kernel thread, jump to its entry-point
740740 ld r9, [sp, PT_status32]
741741 brne r9, 0, 1f
742742
arch/arc/kernel/head.S+35−3
@@ -12,10 +12,42 @@ · 11 unmodified lines
1212 * to skip certain things during boot on simulator
1313 */
1414
15+#include <linux/linkage.h>
1516 #include <asm/asm-offsets.h>
1617 #include <asm/entry.h>
17−#include <linux/linkage.h>
1818 #include <asm/arcregs.h>
19+#include <asm/cache.h>
20+
21+.macro CPU_EARLY_SETUP
22+
23+ ; Setting up Vectror Table (in case exception happens in early boot
24+ sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
25+
26+ ; Disable I-cache/D-cache if kernel so configured
27+ lr r5, [ARC_REG_IC_BCR]
28+ breq r5, 0, 1f ; I$ doesn't exist
29+ lr r5, [ARC_REG_IC_CTRL]
30+#ifdef CONFIG_ARC_HAS_ICACHE
31+ bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
32+#else
33+ bset r5, r5, 0 ; I$ exists, but is not used
34+#endif
35+ sr r5, [ARC_REG_IC_CTRL]
36+
37+1:
38+ lr r5, [ARC_REG_DC_BCR]
39+ breq r5, 0, 1f ; D$ doesn't exist
40+ lr r5, [ARC_REG_DC_CTRL]
41+ bclr r5, r5, 6 ; Invalidate (discard w/o wback)
42+#ifdef CONFIG_ARC_HAS_DCACHE
43+ bclr r5, r5, 0 ; Enable (+Inv)
44+#else
45+ bset r5, r5, 0 ; Disable (+Inv)
46+#endif
47+ sr r5, [ARC_REG_DC_CTRL]
48+
49+1:
50+.endm
1951
2052 .cpu A7
2153
@@ -27,7 +59,7 @@ stext: · 5 unmodified lines
2759 ; Don't clobber r0-r2 yet. It might have bootloader provided info
2860 ;-------------------------------------------------------------------
2961
30− sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
62+ CPU_EARLY_SETUP
3163
3264 #ifdef CONFIG_SMP
3365 ; Ensure Boot (Master) proceeds. Others wait in platform dependent way
@@ -90,7 +122,7 @@ stext: · 56 unmodified lines
90122
91123 first_lines_of_secondary:
92124
93− sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
125+ CPU_EARLY_SETUP
94126
95127 ; setup per-cpu idle task as "current" on this CPU
96128 ld r0, [@secondary_idle_tsk]
arch/arc/kernel/irq.c+0−18
@@ -150,24 +150,6 @@ void arch_do_IRQ(unsigned int irq, struct pt_regs *regs) · 149 unmodified lines
150150 set_irq_regs(old_regs);
151151 }
152152
153−int get_hw_config_num_irq(void)
154−{
155− uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR);
156−
157− switch (val & 0x03) {
158− case 0:
159− return 16;
160− case 1:
161− return 32;
162− case 2:
163− return 8;
164− default:
165− return 0;
166− }
167−
168− return 0;
169−}
170−
171153 /*
172154 * arch_local_irq_enable - Enable interrupts.
173155 *
arch/arc/kernel/process.c+23−0
@@ -150,6 +150,29 @@ int copy_thread(unsigned long clone_flags, · 149 unmodified lines
150150 return 0;
151151 }
152152
153+/*
154+ * Do necessary setup to start up a new user task
155+ */
156+void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long usp)
157+{
158+ set_fs(USER_DS); /* user space */
159+
160+ regs->sp = usp;
161+ regs->ret = pc;
162+
163+ /*
164+ * [U]ser Mode bit set
165+ * [L] ZOL loop inhibited to begin with - cleared by a LP insn
166+ * Interrupts enabled
167+ */
168+ regs->status32 = STATUS_U_MASK | STATUS_L_MASK |
169+ STATUS_E1_MASK | STATUS_E2_MASK;
170+
171+ /* bogus seed values for debugging */
172+ regs->lp_start = 0x10;
173+ regs->lp_end = 0x80;
174+}
175+
153176 /*
154177 * Some archs flush debug and FPU info here
155178 */
arch/arc/kernel/smp.c+1−1
@@ -138,7 +138,7 @@ void start_kernel_secondary(void) · 137 unmodified lines
138138 if (machine_desc->init_smp)
139139 machine_desc->init_smp(smp_processor_id());
140140
141− arc_local_timer_setup(cpu);
141+ arc_local_timer_setup();
142142
143143 local_irq_enable();
144144 preempt_disable();
arch/arc/kernel/time.c+6−5
@@ -219,12 +219,13 @@ static struct irqaction arc_timer_irq = { · 218 unmodified lines
219219 /*
220220 * Setup the local event timer for @cpu
221221 */
222−void arc_local_timer_setup(unsigned int cpu)
222+void arc_local_timer_setup()
223223 {
224− struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu);
224+ struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
225+ int cpu = smp_processor_id();
225226
226− clk->cpumask = cpumask_of(cpu);
227− clockevents_config_and_register(clk, arc_get_core_freq(),
227+ evt->cpumask = cpumask_of(cpu);
228+ clockevents_config_and_register(evt, arc_get_core_freq(),
228229 0, ARC_TIMER_MAX);
229230
230231 /*
@@ -261,7 +262,7 @@ void __init time_init(void) · 30 unmodified lines
261262 clocksource_register_hz(&arc_counter, arc_get_core_freq());
262263
263264 /* sets up the periodic event timer */
264− arc_local_timer_setup(smp_processor_id());
265+ arc_local_timer_setup();
265266
266267 if (machine_desc->init_time)
267268 machine_desc->init_time();
arch/arc/mm/cache_arc700.c+29−81
@@ -73,33 +73,6 @@ · 72 unmodified lines
7373 #include <asm/cachectl.h>
7474 #include <asm/setup.h>
7575
76−/* Instruction cache related Auxiliary registers */
77−#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
78−#define ARC_REG_IC_IVIC 0x10
79−#define ARC_REG_IC_CTRL 0x11
80−#define ARC_REG_IC_IVIL 0x19
81−#if (CONFIG_ARC_MMU_VER > 2)
82−#define ARC_REG_IC_PTAG 0x1E
83−#endif
84−
85−/* Bit val in IC_CTRL */
86−#define IC_CTRL_CACHE_DISABLE 0x1
87−
88−/* Data cache related Auxiliary registers */
89−#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
90−#define ARC_REG_DC_IVDC 0x47
91−#define ARC_REG_DC_CTRL 0x48
92−#define ARC_REG_DC_IVDL 0x4A
93−#define ARC_REG_DC_FLSH 0x4B
94−#define ARC_REG_DC_FLDL 0x4C
95−#if (CONFIG_ARC_MMU_VER > 2)
96−#define ARC_REG_DC_PTAG 0x5C
97−#endif
98−
99−/* Bit val in DC_CTRL */
100−#define DC_CTRL_INV_MODE_FLUSH 0x40
101−#define DC_CTRL_FLUSH_STATUS 0x100
102−
10376 char *arc_cache_mumbojumbo(int c, char *buf, int len)
10477 {
10578 int n = 0;
@@ -168,72 +141,43 @@ void read_decode_cache_bcr(void) · 62 unmodified lines
168141 */
169142 void arc_cache_init(void)
170143 {
171− unsigned int cpu = smp_processor_id();
172− struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
173− struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
174− unsigned int dcache_does_alias, temp;
144+ unsigned int __maybe_unused cpu = smp_processor_id();
145+ struct cpuinfo_arc_cache __maybe_unused *ic, __maybe_unused *dc;
175146 char str[256];
176147
177148 printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
178149
179− if (!ic->ver)
180− goto chk_dc;
181−
182−#ifdef CONFIG_ARC_HAS_ICACHE
183− /* 1. Confirm some of I-cache params which Linux assumes */
184− if (ic->line_len != L1_CACHE_BYTES)
185− panic("Cache H/W doesn't match kernel Config");
186−
187− if (ic->ver != CONFIG_ARC_MMU_VER)
188− panic("Cache ver doesn't match MMU ver\n");
189−#endif
190−
191− /* Enable/disable I-Cache */
192− temp = read_aux_reg(ARC_REG_IC_CTRL);
193−
194150 #ifdef CONFIG_ARC_HAS_ICACHE
195− temp &= ~IC_CTRL_CACHE_DISABLE;
196−#else
197− temp |= IC_CTRL_CACHE_DISABLE;
151+ ic = &cpuinfo_arc700[cpu].icache;
152+ if (ic->ver) {
153+ if (ic->line_len != L1_CACHE_BYTES)
154+ panic("ICache line [%d] != kernel Config [%d]",
155+ ic->line_len, L1_CACHE_BYTES);
156+
157+ if (ic->ver != CONFIG_ARC_MMU_VER)
158+ panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
159+ ic->ver, CONFIG_ARC_MMU_VER);
160+ }
198161 #endif
199162
200− write_aux_reg(ARC_REG_IC_CTRL, temp);
201−
202−chk_dc:
203− if (!dc->ver)
204− return;
205−
206163 #ifdef CONFIG_ARC_HAS_DCACHE
207− if (dc->line_len != L1_CACHE_BYTES)
208− panic("Cache H/W doesn't match kernel Config");
164+ dc = &cpuinfo_arc700[cpu].dcache;
165+ if (dc->ver) {
166+ unsigned int dcache_does_alias;
209167
210− /* check for D-Cache aliasing */
211− dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;
168+ if (dc->line_len != L1_CACHE_BYTES)
169+ panic("DCache line [%d] != kernel Config [%d]",
170+ dc->line_len, L1_CACHE_BYTES);
212171
213− if (dcache_does_alias && !cache_is_vipt_aliasing())
214− panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
215− else if (!dcache_does_alias && cache_is_vipt_aliasing())
216− panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
217−#endif
218−
219− /* Set the default Invalidate Mode to "simpy discard dirty lines"
220− * as this is more frequent then flush before invalidate
221− * Ofcourse we toggle this default behviour when desired
222− */
223− temp = read_aux_reg(ARC_REG_DC_CTRL);
224− temp &= ~DC_CTRL_INV_MODE_FLUSH;
172+ /* check for D-Cache aliasing */
173+ dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;
225174
226−#ifdef CONFIG_ARC_HAS_DCACHE
227− /* Enable D-Cache: Clear Bit 0 */
228− write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE);
229−#else
230− /* Flush D cache */
231− write_aux_reg(ARC_REG_DC_FLSH, 0x1);
232− /* Disable D cache */
233− write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE);
175+ if (dcache_does_alias && !cache_is_vipt_aliasing())
176+ panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
177+ else if (!dcache_does_alias && cache_is_vipt_aliasing())
178+ panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
179+ }
234180 #endif
235−
236− return;
237181 }
238182
239183 #define OP_INV 0x1
@@ -253,12 +197,16 @@ static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr, · 13 unmodified lines
253197
254198 if (cacheop == OP_INV_IC) {
255199 aux_cmd = ARC_REG_IC_IVIL;
200+#if (CONFIG_ARC_MMU_VER > 2)
256201 aux_tag = ARC_REG_IC_PTAG;
202+#endif
257203 }
258204 else {
259205 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
260206 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
207+#if (CONFIG_ARC_MMU_VER > 2)
261208 aux_tag = ARC_REG_DC_PTAG;
209+#endif
262210 }
263211
264212 /* Ensure we properly floor/ceil the non-line aligned/sized requests
arch/arc/plat-arcfpga/Kconfig+0−32
@@ -48,36 +48,4 @@ config ARC_SERIAL_BAUD · 47 unmodified lines
4848 help
4949 Baud rate for the ARC UART
5050
51−menuconfig ARC_HAS_BVCI_LAT_UNIT
52− bool "BVCI Bus Latency Unit"
53− depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4
54− help
55− IP to add artificial latency to BVCI Bus Based FPGA builds.
56− The default latency (even worst case) for FPGA is non-realistic
57− (~10 SDRAM, ~5 SSRAM).
58−
59−config BVCI_LAT_UNITS
60− hex "Latency Unit(s) Bitmap"
61− default "0x0"
62− depends on ARC_HAS_BVCI_LAT_UNIT
63− help
64− There are multiple Latency Units corresponding to the many
65− interfaces of the system bus arbiter (both CPU side as well as
66− the peripheral side).
67− To add latency to ALL memory transaction, choose Unit 0, otherwise
68− for finer grainer - interface wise latency, specify a bitmap (1 bit
69− per unit) of all units. e.g. 1,2,12 will be 0x1003
70−
71− Unit 0 - System Arb and Mem Controller
72− Unit 1 - I$ and System Bus
73− Unit 2 - D$ and System Bus
74− ..
75− Unit 12 - IDE Disk controller and System Bus
76−
77−config BVCI_LAT_CYCLES
78− int "Latency Value in cycles"
79− range 0 63
80− default "30"
81− depends on ARC_HAS_BVCI_LAT_UNIT
82−
8351 endif
arch/arc/plat-arcfpga/Makefile+1−1
@@ -9,4 +9,4 @@ · 8 unmodified lines
99 KBUILD_CFLAGS += -Iarch/arc/plat-arcfpga/include
1010
1111 obj-y := platform.o irq.o
12−obj-$(CONFIG_SMP) += smp.o
12+obj-$(CONFIG_ISS_SMP_EXTN) += smp.o
arch/arc/plat-arcfpga/platform.c+6−66
@@ -22,59 +22,6 @@ · 21 unmodified lines
2222 #include <plat/smp.h>
2323 #include <plat/irq.h>
2424
25−/*-----------------------BVCI Latency Unit -----------------------------*/
26−
27−#ifdef CONFIG_ARC_HAS_BVCI_LAT_UNIT
28−
29−int lat_cycles = CONFIG_BVCI_LAT_CYCLES;
30−
31−/* BVCI Bus Profiler: Latency Unit */
32−static void __init setup_bvci_lat_unit(void)
33−{
34−#define MAX_BVCI_UNITS 12
35−
36− unsigned int i;
37− unsigned int *base = (unsigned int *)BVCI_LAT_UNIT_BASE;
38− const unsigned long units_req = CONFIG_BVCI_LAT_UNITS;
39− const unsigned int REG_UNIT = 21;
40− const unsigned int REG_VAL = 22;
41−
42− /*
43− * There are multiple Latency Units corresponding to the many
44− * interfaces of the system bus arbiter (both CPU side as well as
45− * the peripheral side).
46− *
47− * Unit 0 - System Arb and Mem Controller - adds latency to all
48− * memory trasactions
49− * Unit 1 - I$ and System Bus
50− * Unit 2 - D$ and System Bus
51− * ..
52− * Unit 12 - IDE Disk controller and System Bus
53− *
54− * The programmers model requires writing to lat_unit reg first
55− * and then the latency value (cycles) to lat_value reg
56− */
57−
58− if (CONFIG_BVCI_LAT_UNITS == 0) {
59− writel(0, base + REG_UNIT);
60− writel(lat_cycles, base + REG_VAL);
61− pr_info("BVCI Latency for all Memory Transactions %d cycles\n",
62− lat_cycles);
63− } else {
64− for_each_set_bit(i, &units_req, MAX_BVCI_UNITS) {
65− writel(i + 1, base + REG_UNIT); /* loop is 0 based */
66− writel(lat_cycles, base + REG_VAL);
67− pr_info("BVCI Latency for Unit[%d] = %d cycles\n",
68− (i + 1), lat_cycles);
69− }
70− }
71−}
72−#else
73−static void __init setup_bvci_lat_unit(void)
74−{
75−}
76−#endif
77−
7825 /*----------------------- Platform Devices -----------------------------*/
7926
8027 #if IS_ENABLED(CONFIG_SERIAL_ARC)
@@ -132,16 +79,11 @@ static void arc_fpga_serial_init(void) · 51 unmodified lines
13279 ARRAY_SIZE(fpga_early_devs));
13380
13481 /*
135− * ARC console driver registers itself as an early platform driver
136− * of class "earlyprintk".
137− * Install it here, followed by probe of devices.
138− * The installation here doesn't require earlyprintk in command line
139− * To do so however, replace the lines below with
140− * parse_early_param();
141− * early_platform_driver_probe("earlyprintk", 1, 1);
142− * ^^
82+ * ARC console driver registers (build time) as an early platform driver
83+ * of class "earlyprintk". However it needs explicit cmdline toggle
84+ * "earlyprintk=ttyARC0" to be successfuly runtime registered.
85+ * Otherwise the early probe below fails to find the driver
14386 */
144− early_platform_driver_register_all("earlyprintk");
14587 early_platform_driver_probe("earlyprintk", 1, 0);
14688
14789 /*
@@ -165,11 +107,9 @@ static void __init plat_fpga_early_init(void) · 17 unmodified lines
165107 {
166108 pr_info("[plat-arcfpga]: registering early dev resources\n");
167109
168− setup_bvci_lat_unit();
169−
170110 arc_fpga_serial_init();
171111
172−#ifdef CONFIG_SMP
112+#ifdef CONFIG_ISS_SMP_EXTN
173113 iss_model_init_early_smp();
174114 #endif
175115 }
@@ -211,7 +151,7 @@ MACHINE_START(ANGEL4, "angel4") · 35 unmodified lines
211151 .init_early = plat_fpga_early_init,
212152 .init_machine = plat_fpga_populate_dev,
213153 .init_irq = plat_fpga_init_IRQ,
214−#ifdef CONFIG_SMP
154+#ifdef CONFIG_ISS_SMP_EXTN
215155 .init_smp = iss_model_init_smp,
216156 #endif
217157 MACHINE_END
arch/arc/plat-arcfpga/smp.c+18−0
@@ -42,6 +42,24 @@ static void iss_model_smp_wakeup_cpu(int cpu, unsigned long pc) · 41 unmodified lines
4242
4343 }
4444
45+static inline int get_hw_config_num_irq(void)
46+{
47+ uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR);
48+
49+ switch (val & 0x03) {
50+ case 0:
51+ return 16;
52+ case 1:
53+ return 32;
54+ case 2:
55+ return 8;
56+ default:
57+ return 0;
58+ }
59+
60+ return 0;
61+}
62+
4563 /*
4664 * Any SMP specific init any CPU does when it comes up.
4765 * Here we setup the CPU to enable Inter-Processor-Interrupts