drm/tegra: Changes for v4.16-rc1 The bulk of these changes are preparation work and addition of support for Tegra186. Currently only HDMI output (the primary output on Jetson TX2) is supported, but the hardware is also capable of doing DSI and DisplayPort. Tegra DRM now also uses the atomic commit helpers instead of the open- coded variant that was only doing half its job. As a bit of a byproduct of the Tegra186 support the driver also gained HDMI 2.0 as well as zpos property support. Along the way there are also a few patches to clean up a few things and fix minor issues. * tag 'drm/tegra/for-4.16-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux: (51 commits) drm/tegra: dc: Properly cleanup overlay planes drm/tegra: dc: Fix possible_crtcs mask for planes drm/tegra: dc: Restore YUV overlay support drm/tegra: dc: Implement legacy blending drm/tegra: Correct timeout in tegra_syncpt_wait drm/tegra: gem: Correct iommu_map_sg() error checking drm/tegra: dc: Link DC1 to DC0 on Tegra20 drm/tegra: Fix non-debugfs builds drm/tegra: dpaux: Keep reset defaults for hybrid pad parameters drm/tegra: Mark Tegra186 display hub PM functions __maybe_unused drm/tegra: Use IOMMU groups gpu: host1x: Use IOMMU groups drm/tegra: Implement zpos property drm/tegra: dc: Remove redundant spinlock drm/tegra: dc: Use direct offset to plane registers drm/tegra: dc: Support more formats drm/tegra: fb: Force alpha formats drm/tegra: dpaux: Add Tegra186 support drm/tegra: dpaux: Implement runtime PM drm/tegra: sor: Support HDMI 2.0 modes ...
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| @@ -178,7 +178,7 @@ extern "C" { · 177 unmodified lines | ||
| 178 | 178 | #define DRM_FORMAT_MOD_VENDOR_NONE 0 |
| 179 | 179 | #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 |
| 180 | 180 | #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 |
| 181 | −#define DRM_FORMAT_MOD_VENDOR_NV 0x03 | |
| 181 | +#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 | |
| 182 | 182 | #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 |
| 183 | 183 | #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 |
| 184 | 184 | #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 |
| @@ -188,7 +188,7 @@ extern "C" { · 3 unmodified lines | ||
| 188 | 188 | #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) |
| 189 | 189 | |
| 190 | 190 | #define fourcc_mod_code(vendor, val) \ |
| 191 | − ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) | |
| 191 | + ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) | |
| 192 | 192 | |
| 193 | 193 | /* |
| 194 | 194 | * Format Modifier tokens: |
| @@ -338,29 +338,17 @@ extern "C" { · 143 unmodified lines | ||
| 338 | 338 | */ |
| 339 | 339 | #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) |
| 340 | 340 | |
| 341 | −/* NVIDIA Tegra frame buffer modifiers */ | |
| 342 | − | |
| 343 | −/* | |
| 344 | − * Some modifiers take parameters, for example the number of vertical GOBs in | |
| 345 | − * a block. Reserve the lower 32 bits for parameters | |
| 346 | − */ | |
| 347 | −#define __fourcc_mod_tegra_mode_shift 32 | |
| 348 | −#define fourcc_mod_tegra_code(val, params) \ | |
| 349 | − fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params)) | |
| 350 | −#define fourcc_mod_tegra_mod(m) \ | |
| 351 | − (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) | |
| 352 | −#define fourcc_mod_tegra_param(m) \ | |
| 353 | − (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) | |
| 341 | +/* NVIDIA frame buffer modifiers */ | |
| 354 | 342 | |
| 355 | 343 | /* |
| 356 | 344 | * Tegra Tiled Layout, used by Tegra 2, 3 and 4. |
| 357 | 345 | * |
| 358 | 346 | * Pixels are arranged in simple tiles of 16 x 16 bytes. |
| 359 | 347 | */ |
| 360 | −#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) | |
| 348 | +#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) | |
| 361 | 349 | |
| 362 | 350 | /* |
| 363 | − * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 | |
| 351 | + * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later | |
| 364 | 352 | * |
| 365 | 353 | * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked |
| 366 | 354 | * vertically by a power of 2 (1 to 32 GOBs) to form a block. |
| @@ -380,7 +368,21 @@ extern "C" { · 13 unmodified lines | ||
| 380 | 368 | * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format |
| 381 | 369 | * in full detail. |
| 382 | 370 | */ |
| 383 | −#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) | |
| 371 | +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ | |
| 372 | + fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) | |
| 373 | + | |
| 374 | +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ | |
| 375 | + fourcc_mod_code(NVIDIA, 0x10) | |
| 376 | +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ | |
| 377 | + fourcc_mod_code(NVIDIA, 0x11) | |
| 378 | +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ | |
| 379 | + fourcc_mod_code(NVIDIA, 0x12) | |
| 380 | +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ | |
| 381 | + fourcc_mod_code(NVIDIA, 0x13) | |
| 382 | +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ | |
| 383 | + fourcc_mod_code(NVIDIA, 0x14) | |
| 384 | +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ | |
| 385 | + fourcc_mod_code(NVIDIA, 0x15) | |
| 384 | 386 | |
| 385 | 387 | /* |
| 386 | 388 | * Broadcom VC4 "T" format |